AmbiqMicro apollo2 2024.05.18 Ultra-Low power ARM Cortex-M4 MCU from Ambiq Micro CM4 r1p0 little 3 false 8 32 ADC Analog Digital Converter Control ADC 0x0 0x0 0x210 registers n ADC 16 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 ADCEN This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'. 0 1 read-write DIS Disable the ADC module. 0 EN Enable the ADC module. 1 CKMODE Clock mode register 4 5 read-write LPCKMODE Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC. 0 LLCKMODE Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0. 1 CLKSEL Select the source and frequency for the ADC clock. All values not enumerated below are undefined. 24 26 read-write OFF Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing. 0 HFRC HFRC Core Clock Frequency 1 HFRC_DIV2 HFRC Core Clock / 2 2 LPMODE Select power mode to enter between active scans. 3 4 read-write MODE0 Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection. 0 MODE1 Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode. 1 REFSEL Select the ADC reference voltage. 8 10 read-write INT2P0 Internal 2.0V Bandgap Reference Voltage 0 INT1P5 Internal 1.5V Bandgap Reference Voltage 1 EXT2P0 Off Chip 2.0V Reference 2 EXT1P5 Off Chip 1.5V Reference 3 RPTEN This bit enables Repeating Scan Mode. 2 3 read-write SINGLE_SCAN In Single Scan Mode, the ADC will complete a single scan upon each trigger event. 0 REPEATING_SCAN In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared. 1 TRIGPOL This bit selects the ADC trigger polarity for external off chip triggers. 19 20 read-write RISING_EDGE Trigger on rising edge. 0 FALLING_EDGE Trigger on falling edge. 1 TRIGSEL Select the ADC trigger source. 16 19 read-write EXT0 Off chip External Trigger0 (ADC_ET0) 0 EXT1 Off chip External Trigger1 (ADC_ET1) 1 EXT2 Off chip External Trigger2 (ADC_ET2) 2 EXT3 Off chip External Trigger3 (ADC_ET3) 3 VCOMP Voltage Comparator Output 4 SWT Software Trigger 7 FIFO FIFO Data and Valid Count Register 0x38 32 read-write n 0x0 0x0 COUNT Number of valid entries in the ADC FIFO. 20 28 read-write DATA Oldest data in the FIFO. 0 20 read-write RSVD RESERVED. 31 32 read-write SLOTNUM Slot number associated with this FIFO data. 28 31 read-write INTCLR ADC Interrupt registers: Clear 0x208 32 read-write n 0x0 0x0 CNVCMP ADC conversion complete interrupt. 0 1 read-write CNVCMPINT ADC conversion complete interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. 2 3 read-write FIFO75INT FIFO 75 percent full interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. 3 4 read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. 1 2 read-write SCNCMPINT ADC scan complete interrupt. 1 WCEXC Window comparator voltage excursion interrupt. 4 5 read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 WCINC Window comparator voltage incursion interrupt. 5 6 read-write WCINCINT Window comparitor voltage incursion interrupt. 1 INTEN ADC Interrupt registers: Enable 0x200 32 read-write n 0x0 0x0 CNVCMP ADC conversion complete interrupt. 0 1 read-write CNVCMPINT ADC conversion complete interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. 2 3 read-write FIFO75INT FIFO 75 percent full interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. 3 4 read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. 1 2 read-write SCNCMPINT ADC scan complete interrupt. 1 WCEXC Window comparator voltage excursion interrupt. 4 5 read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 WCINC Window comparator voltage incursion interrupt. 5 6 read-write WCINCINT Window comparitor voltage incursion interrupt. 1 INTSET ADC Interrupt registers: Set 0x20C 32 read-write n 0x0 0x0 CNVCMP ADC conversion complete interrupt. 0 1 read-write CNVCMPINT ADC conversion complete interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. 2 3 read-write FIFO75INT FIFO 75 percent full interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. 3 4 read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. 1 2 read-write SCNCMPINT ADC scan complete interrupt. 1 WCEXC Window comparator voltage excursion interrupt. 4 5 read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 WCINC Window comparator voltage incursion interrupt. 5 6 read-write WCINCINT Window comparitor voltage incursion interrupt. 1 INTSTAT ADC Interrupt registers: Status 0x204 32 read-write n 0x0 0x0 CNVCMP ADC conversion complete interrupt. 0 1 read-write CNVCMPINT ADC conversion complete interrupt. 1 FIFOOVR1 FIFO 75 percent full interrupt. 2 3 read-write FIFO75INT FIFO 75 percent full interrupt. 1 FIFOOVR2 FIFO 100 percent full interrupt. 3 4 read-write FIFOFULLINT FIFO 100 percent full interrupt. 1 SCNCMP ADC scan complete interrupt. 1 2 read-write SCNCMPINT ADC scan complete interrupt. 1 WCEXC Window comparator voltage excursion interrupt. 4 5 read-write WCEXCINT Window comparitor voltage excursion interrupt. 1 WCINC Window comparator voltage incursion interrupt. 5 6 read-write WCINCINT Window comparitor voltage incursion interrupt. 1 SL0CFG Slot 0 Configuration Register 0xC 32 read-write n 0x0 0x0 ADSEL0 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL0 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE0 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN0 This bit enables slot 0 for ADC conversions. 0 1 read-write SLEN Enable slot 0 for ADC conversions. 1 WCEN0 This bit enables the window compare function for slot 0. 1 2 read-write WCEN Enable the window compare for slot 0. 1 SL1CFG Slot 1 Configuration Register 0x10 32 read-write n 0x0 0x0 ADSEL1 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL1 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE1 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN1 This bit enables slot 1 for ADC conversions. 0 1 read-write SLEN Enable slot 1 for ADC conversions. 1 WCEN1 This bit enables the window compare function for slot 1. 1 2 read-write WCEN Enable the window compare for slot 1. 1 SL2CFG Slot 2 Configuration Register 0x14 32 read-write n 0x0 0x0 ADSEL2 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL2 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE2 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN2 This bit enables slot 2 for ADC conversions. 0 1 read-write SLEN Enable slot 2 for ADC conversions. 1 WCEN2 This bit enables the window compare function for slot 2. 1 2 read-write WCEN Enable the window compare for slot 2. 1 SL3CFG Slot 3 Configuration Register 0x18 32 read-write n 0x0 0x0 ADSEL3 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL3 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE3 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN3 This bit enables slot 3 for ADC conversions. 0 1 read-write SLEN Enable slot 3 for ADC conversions. 1 WCEN3 This bit enables the window compare function for slot 3. 1 2 read-write WCEN Enable the window compare for slot 3. 1 SL4CFG Slot 4 Configuration Register 0x1C 32 read-write n 0x0 0x0 ADSEL4 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL4 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE4 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN4 This bit enables slot 4 for ADC conversions. 0 1 read-write SLEN Enable slot 4 for ADC conversions. 1 WCEN4 This bit enables the window compare function for slot 4. 1 2 read-write WCEN Enable the window compare for slot 4. 1 SL5CFG Slot 5 Configuration Register 0x20 32 read-write n 0x0 0x0 ADSEL5 Select number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL5 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE5 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN5 This bit enables slot 5 for ADC conversions. 0 1 read-write SLEN Enable slot 5 for ADC conversions. 1 WCEN5 This bit enables the window compare function for slot 5. 1 2 read-write WCEN Enable the window compare for slot 5. 1 SL6CFG Slot 6 Configuration Register 0x24 32 read-write n 0x0 0x0 ADSEL6 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL6 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE6 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN6 This bit enables slot 6 for ADC conversions. 0 1 read-write SLEN Enable slot 6 for ADC conversions. 1 WCEN6 This bit enables the window compare function for slot 6. 1 2 read-write WCEN Enable the window compare for slot 6. 1 SL7CFG Slot 7 Configuration Register 0x28 32 read-write n 0x0 0x0 ADSEL7 Select the number of measurements to average in the accumulate divide module for this slot. 24 27 read-write AVG_1_MSRMT Average in 1 measurement in the accumulate divide module for this slot. 0 AVG_2_MSRMTS Average in 2 measurements in the accumulate divide module for this slot. 1 AVG_4_MSRMTS Average in 4 measurements in the accumulate divide module for this slot. 2 AVG_8_MSRMT Average in 8 measurements in the accumulate divide module for this slot. 3 AVG_16_MSRMTS Average in 16 measurements in the accumulate divide module for this slot. 4 AVG_32_MSRMTS Average in 32 measurements in the accumulate divide module for this slot. 5 AVG_64_MSRMTS Average in 64 measurements in the accumulate divide module for this slot. 6 AVG_128_MSRMTS Average in 128 measurements in the accumulate divide module for this slot. 7 CHSEL7 Select one of the 14 channel inputs for this slot. 8 12 read-write SE0 single ended external GPIO connection to pad16. 0 SE1 single ended external GPIO connection to pad29. 1 DF0 differential external GPIO connections to pad12(N) and pad13(P). 10 DF1 differential external GPIO connections to pad15(N) and pad14(P). 11 TEMP internal temperature sensor. 12 BATT internal voltage divide-by-3 connection. 13 VSS Input VSS 14 SE2 single ended external GPIO connection to pad11. 2 SE3 single ended external GPIO connection to pad31. 3 SE4 single ended external GPIO connection to pad32. 4 SE5 single ended external GPIO connection to pad33. 5 SE6 single ended external GPIO connection to pad34. 6 SE7 single ended external GPIO connection to pad35. 7 SE8 single ended external GPIO connection to pad13. 8 SE9 single ended external GPIO connection to pad12. 9 PRMODE7 Set the Precision Mode For Slot. 16 18 read-write P14B 14-bit precision mode 0 P12B 12-bit precision mode 1 P10B 10-bit precision mode 2 P8B 8-bit precision mode 3 SLEN7 This bit enables slot 7 for ADC conversions. 0 1 read-write SLEN Enable slot 7 for ADC conversions. 1 WCEN7 This bit enables the window compare function for slot 7. 1 2 read-write WCEN Enable the window compare for slot 7. 1 STAT ADC Power Status 0x4 32 read-write n 0x0 0x0 PWDSTAT Indicates the power-status of the ADC. 0 1 read-write ON Powered on. 0 POWERED_DOWN ADC Low Power Mode 1. 1 SWT Software trigger 0x8 32 read-write n 0x0 0x0 SWT Writing 0x37 to this register generates a software trigger. 0 8 read-write GEN_SW_TRIGGER Writing this value generates a software trigger. 55 WLLIM Window Comparator Lower Limits Register 0x30 32 read-write n 0x0 0x0 LLIM Sets the lower limit for the wondow comparator. 0 20 read-write WULIM Window Comparator Upper Limits Register 0x2C 32 read-write n 0x0 0x0 ULIM Sets the upper limit for the wondow comparator. 0 20 read-write CACHECTRL Flash Cache Controller CACHECTRL 0x0 0x0 0x240 registers n CACHECFG Flash Cache Control Register 0x0 32 read-write n 0x0 0x0 CACHE_CLKGATE Enable clock gating of individual cache RAMs. This bit should be enabled for normal operation for lowest power consumption. 10 11 read-write CACHE_LS Enable LS (light sleep) of cache RAMs. This should not be enabled for normal operation. When this bit is set, the cache's RAMS will be put into light sleep mode while inactive. NOTE: if the cache is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved. 11 12 read-write CONFIG Sets the cache configuration. Only a single configuration of 0x5 is valid. 4 7 read-write W2_128B_512E Two-way set associative, 128-bit linesize, 512 entries (8 SRAMs active) 5 DATA_CLKGATE Enable clock gating of entire cache data array subsystem. This should be enabled for normal operation. 20 21 read-write DCACHE_ENABLE Enable Flash Data Caching. When set to 1, all instruction accesses to flash will be cached. 9 10 read-write DLY Unused. Should be left at default value. 12 16 read-write ENABLE Enables the main flash cache controller logic and enables power to the cache RAMs. Instruction and Data caching need to be enabled independently using the ICACHE_ENABLE and DCACHE_ENABLE bits. 0 1 read-write ENABLE_MONITOR Enable Cache Monitoring Stats. Only enable this for debug/performance analysis since it will consume additional power. See IMON/DMON registers for data. 24 25 read-write ENABLE_NC0 Enable Non-cacheable region 0. See the NCR0 registers to set the region boundaries and size. 2 3 read-write ENABLE_NC1 Enable Non-cacheable region 1. See the NCR1 registers to set the region boundaries and size. 3 4 read-write ICACHE_ENABLE Enable Flash Instruction Caching. When set to 1, all instruction accesses to flash will be cached. 8 9 read-write LRU Sets the cache replacement policy. 0=LRR (least recently replaced), 1=LRU (least recently used). LRR minimizes writes to the TAG SRAM and is recommended. 1 2 read-write SERIAL Bitfield should always be programmed to 0. 7 8 read-write SMDLY Unused. Should be left at default value. 16 20 read-write CACHEMODE Flash Cache Mode Register. Used to trim performance/power. 0x30 32 read-write n 0x0 0x0 THROTTLE1 Disallow cache data RAM writes on tag RAM fill cycles. Value should be left at zero for optimal performance. 0 1 read-write THROTTLE2 Disallow cache data RAM writes on tag RAM read cycles. Value should be left at zero for optimal performance. 1 2 read-write THROTTLE3 Disallow cache data RAM writes on data RAM read cycles. Value should be left at zero for optimal performance. 2 3 read-write THROTTLE4 Disallow Data RAM reads (from line hits) on tag RAM fill cycles. Value should be left at zero for optimal performance. 3 4 read-write THROTTLE5 Disallow Data RAM reads (from line hits) during lookup read ops. Value should be left at zero for optimal performance. 4 5 read-write THROTTLE6 Disallow Simultaneous Data RAM reads (from 2 line hits on each bus). Value should be left at zero for optimal performance. 5 6 read-write CTRL Cache Control 0x8 32 read-write n 0x0 0x0 CACHE_READY Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation. 2 3 read-write FLASH0_SLM_DISABLE Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array. 5 6 read-write FLASH0_SLM_ENABLE Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time. 6 7 read-write FLASH0_SLM_STATUS Flash Sleep Mode Status. When 1, flash instance 0 is asleep. 4 5 read-write FLASH1_SLM_DISABLE Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array. 9 10 read-write FLASH1_SLM_ENABLE Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time. 10 11 read-write FLASH1_SLM_STATUS Flash Sleep Mode Status. When 1, flash instance 1 is asleep. 8 9 read-write INVALIDATE Writing a 1 to this bitfield invalidates the flash cache contents. 0 1 read-write GO Initiate a programming operation to flash info. 1 RESET_STAT Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield. 1 2 read-write CLEAR Clear Cache Stats 1 DMON0 Data Cache Total Accesses 0x40 32 read-write n 0x0 0x0 DACCESS_COUNT Total accesses to data cache 0 32 read-write DMON1 Data Cache Tag Lookups 0x44 32 read-write n 0x0 0x0 DLOOKUP_COUNT Total tag lookups from data cache 0 32 read-write DMON2 Data Cache Hits 0x48 32 read-write n 0x0 0x0 DHIT_COUNT Cache hits from lookup operations 0 32 read-write DMON3 Data Cache Line Hits 0x4C 32 read-write n 0x0 0x0 DLINE_COUNT Cache hits from line cache 0 32 read-write FLASHCFG Flash Control Register 0x4 32 read-write n 0x0 0x0 RD_WAIT Sets read waitstates for flash accesses (in clock cycles). This should be left at the default value for normal flash operation. 0 3 read-write IMON0 Instruction Cache Total Accesses 0x50 32 read-write n 0x0 0x0 IACCESS_COUNT Total accesses to Instruction cache 0 32 read-write IMON1 Instruction Cache Tag Lookups 0x54 32 read-write n 0x0 0x0 ILOOKUP_COUNT Total tag lookups from Instruction cache 0 32 read-write IMON2 Instruction Cache Hits 0x58 32 read-write n 0x0 0x0 IHIT_COUNT Cache hits from lookup operations 0 32 read-write IMON3 Instruction Cache Line Hits 0x5C 32 read-write n 0x0 0x0 ILINE_COUNT Cache hits from line cache 0 32 read-write NCR0END Flash Cache Noncachable Region 0 End 0x14 32 read-write n 0x0 0x0 ADDR End address for non-cacheable region 0. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused). 4 20 read-write NCR0START Flash Cache Noncachable Region 0 Start Address. 0x10 32 read-write n 0x0 0x0 ADDR Start address for non-cacheable region 0. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused). 4 20 read-write NCR1END Flash Cache Noncachable Region 1 End 0x1C 32 read-write n 0x0 0x0 ADDR End address for non-cacheable region 1. The physical address of the end of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused). 4 20 read-write NCR1START Flash Cache Noncachable Region 1 Start 0x18 32 read-write n 0x0 0x0 ADDR Start address for non-cacheable region 1. The physical address of the start of this region should be programmed to this register and must be aligned to a 16-byte boundary (thus the lower 4 address bits are unused). 4 20 read-write CLKGEN Clock Generator CLKGEN 0x0 0x0 0x110 registers n CLKGEN_RTC 2 ACALCTR Autocalibration Counter 0x8 32 read-write n 0x0 0x0 ACALCTR Autocalibration Counter result. 0 24 read-write CALRC RC Oscillator Control 0x4 32 read-write n 0x0 0x0 CALRC LFRC Oscillator calibration value 0 18 read-write CALXT XT Oscillator Control 0x0 32 read-write n 0x0 0x0 CALXT XT Oscillator calibration value 0 11 read-write CCTRL HFRC Clock Control 0x18 32 read-write n 0x0 0x0 CORESEL Core Clock divisor 0 1 read-write HFRC Core Clock is HFRC 0 HFRC_DIV2 Core Clock is HFRC / 2 1 CLKKEY Key Register for Clock Control Register 0x14 32 read-write n 0x0 0x0 CLKKEY Key register value. 0 32 read-write Key Key 71 CLKOUT CLKOUT Frequency Select 0x10 32 read-write n 0x0 0x0 CKEN Enable the CLKOUT signal 7 8 read-write DIS Disable CLKOUT 0 EN Enable CLKOUT 1 CKSEL CLKOUT signal select. Note that HIGH_DRIVE should be selected if any high frequencies (such as from HFRC) are selected for CLKOUT. 0 6 read-write LFRC LFRC 0 XT_DIV2 XT / 2 1 RTC_1Hz 1 Hz as selected in RTC 16 XT_DIV4 XT / 4 2 XT_DIV2M XT / 2^21 22 XT XT 23 CG_100Hz 100 Hz as selected in CLKGEN 24 HFRC HFRC 25 HFRC_DIV4 HFRC / 4 26 HFRC_DIV8 HFRC / 8 27 HFRC_DIV16 HFRC / 16 28 HFRC_DIV64 HFRC / 64 29 XT_DIV8 XT / 8 3 HFRC_DIV128 HFRC / 128 30 HFRC_DIV256 HFRC / 256 31 HFRC_DIV512 HFRC / 512 32 FLASH_CLK Flash Clock 34 LFRC_DIV2 LFRC / 2 35 LFRC_DIV32 LFRC / 32 36 LFRC_DIV512 LFRC / 512 37 LFRC_DIV32K LFRC / 32768 38 XT_DIV256 XT / 256 39 XT_DIV16 XT / 16 4 XT_DIV8K XT / 8192 40 XT_DIV64K XT / 2^16 41 ULFRC_DIV16 Uncal LFRC / 16 42 ULFRC_DIV128 Uncal LFRC / 128 43 ULFRC_1Hz Uncal LFRC / 1024 44 ULFRC_DIV4K Uncal LFRC / 4096 45 ULFRC_DIV1M Uncal LFRC / 2^20 46 HFRC_DIV64K HFRC / 2^16 47 HFRC_DIV16M HFRC / 2^24 48 LFRC_DIV2M LFRC / 2^20 49 XT_DIV32 XT / 32 5 HFRCNE HFRC (not autoenabled) 50 HFRCNE_DIV8 HFRC / 8 (not autoenabled) 51 XTNE XT (not autoenabled) 53 XTNE_DIV16 XT / 16 (not autoenabled) 54 LFRCNE_DIV32 LFRC / 32 (not autoenabled) 55 LFRCNE LFRC (not autoenabled) - Default for undefined values 57 CLOCKEN Clock Enable Status 0x28 32 read-write n 0x0 0x0 CLOCKEN Clock enable status 0 32 read-write ADC_CLKEN Clock enable for the ADC. 1 IOMSTR0_CLKEN Clock enable for the IO Master 0. 1024 IOMSTRIFC4_CLKEN Clock enable for the IO Master IFC4. 1048576 UART0_HCLK_CLKEN Clock enable for the UART0_HCLK. 1073741824 CTIMER2B_CLKEN Clock enable for the CTIMER2B. 128 IOMSTRIFC1_CLKEN Clock enable for the IO Master IFC1. 131072 STIMER_CLKEN Clock enable for the STIMER. 134217728 CTIMER1A_CLKEN Clock enable for the CTIMER1A. 16 IOMSTR4_CLKEN Clock enable for the IO Master 4. 16384 PDMIFC_CLKEN Clock enable for the PDM IFC. 16777216 CTIMER_CLKEN Clock enable for the CTIMER. 2 IOMSTR1_CLKEN Clock enable for the IO Master 1. 2048 IOMSTRIFC5_CLKEN Clock enable for the IO Master IFC5. 2097152 UART0HF_CLKEN Clock enable for the UART0HF. 2147483648 CTIMER3A_CLKEN Clock enable for the CTIMER3A. 256 IOMSTRIFC2_CLKEN Clock enable for the IO Master IFC2. 262144 STIMER_CNT_CLKEN Clock enable for the STIMER_CNT. 268435456 CTIMER1B_CLKEN Clock enable for the CTIMER1B. 32 IOMSTR5_CLKEN Clock enable for the IO Master 5. 32768 RSTGEN_CLKEN Clock enable for the RSTGEN. 33554432 CTIMER0A_CLKEN Clock enable for the CTIMER0A. 4 IOMSTR2_CLKEN Clock enable for the IO Master 2. 4096 IOSLAVE_CLKEN Clock enable for the IO Slave. 4194304 CTIMER3B_CLKEN Clock enable for the CTIMER3B. 512 IOMSTRIFC3_CLKEN Clock enable for the IO Master IFC3. 524288 TPIU_CLKEN Clock enable for the TPIU. 536870912 CTIMER2A_CLKEN Clock enable for the CTIMER2A. 64 IOMSTRIFC0_CLKEN Clock enable for the IO Master IFC0. 65536 SRAM_WIPE_CLKEN Clock enable for the SRAM_WIPE. 67108864 CTIMER0B_CLKEN Clock enable for the CTIMER0B. 8 IOMSTR3_CLKEN Clock enable for the IO Master 3. 8192 PDM_CLKEN Clock enable for the PDM. 8388608 CLOCKEN2 Clock Enable Status 0x2C 32 read-write n 0x0 0x0 CLOCKEN2 Clock enable status 2 0 32 read-write UART1_HCLK_CLKEN Clock enable for the UART1_HCLK. 1 XT_32KHz_EN Clock enable for the XT_32KHz. 1073741824 UART1HF_CLKEN Clock enable for the UART1HF. 2 FRCHFRC Force HFRC On Status. 2147483648 WDT_CLKEN Clock enable for the WDT. 4 CLOCKEN3 Clock Enable Status 0x30 32 read-write n 0x0 0x0 CLOCKEN3 Clock enable status 3 0 32 read-write HFRC_EN HFRC is enabled Status 1073741824 HFRC_en_out HFRC is enabled during adjustment status 134217728 periph_all_xtal_en At least 1 peripherial is requesting for XTAL Clock 16777216 FLASHCLK_EN Flash Clock is enabled Status 2147483648 RTC_SOURCE Selects the RTC oscillator (0 => LFRC, 1 => XT) 268435456 periph_all_hfrc_en At least 1 peripherial is requesting for HFRC Clock 33554432 XTAL_EN XT is enabled Status 536870912 HFADJEN HFRC Adjust Enable Status 67108864 HFADJ HFRC Adjustment 0x20 32 read-write n 0x0 0x0 HFADJCK Repeat period for HFRC adjustment 1 4 read-write 4SEC Autoadjust repeat period = 4 seconds 0 16SEC Autoadjust repeat period = 16 seconds 1 32SEC Autoadjust repeat period = 32 seconds 2 64SEC Autoadjust repeat period = 64 seconds 3 128SEC Autoadjust repeat period = 128 seconds 4 256SEC Autoadjust repeat period = 256 seconds 5 512SEC Autoadjust repeat period = 512 seconds 6 1024SEC Autoadjust repeat period = 1024 seconds 7 HFADJEN HFRC adjustment control 0 1 read-write DIS Disable the HFRC adjustment 0 EN Enable the HFRC adjustment 1 HFADJ_GAIN Gain control for HFRC adjustment 21 24 read-write Gain_of_1 HF Adjust with Gain of 1 0 Gain_of_1_in_2 HF Adjust with Gain of 0.5 1 Gain_of_1_in_4 HF Adjust with Gain of 0.25 2 Gain_of_1_in_8 HF Adjust with Gain of 0.125 3 Gain_of_1_in_16 HF Adjust with Gain of 0.0625 4 Gain_of_1_in_32 HF Adjust with Gain of 0.03125 5 HFWARMUP XT warmup period for HFRC adjustment 20 21 read-write 1SEC Autoadjust XT warmup period = 1-2 seconds 0 2SEC Autoadjust XT warmup period = 2-4 seconds 1 HFXTADJ Target HFRC adjustment value. 8 20 read-write INTCLR CLKGEN Interrupt Register: Clear 0x108 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTEN CLKGEN Interrupt Register: Enable 0x100 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTSET CLKGEN Interrupt Register: Set 0x10C 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTSTAT CLKGEN Interrupt Register: Status 0x104 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write OCTRL Oscillator Control 0xC 32 read-write n 0x0 0x0 ACAL Autocalibration control 8 11 read-write DIS Disable Autocalibration 0 1024SEC Autocalibrate every 1024 seconds 2 512SEC Autocalibrate every 512 seconds 3 XTFREQ Frequency measurement using XT 6 EXTFREQ Frequency measurement using external clock 7 FOS Oscillator switch on failure function 6 7 read-write DIS Disable the oscillator switch on failure function 0 EN Enable the oscillator switch on failure function 1 OSEL Selects the RTC oscillator (1 => LFRC, 0 => XT) 7 8 read-write RTC_XT RTC uses the XT 0 RTC_LFRC RTC uses the LFRC 1 STOPRC Stop the LFRC Oscillator to the RTC 1 2 read-write EN Enable the LFRC Oscillator to drive the RTC 0 STOP Stop the LFRC Oscillator when driving the RTC 1 STOPXT Stop the XT Oscillator to the RTC 0 1 read-write EN Enable the XT Oscillator to drive the RTC 0 STOP Stop the XT Oscillator when driving the RTC 1 STATUS Clock Generator Status 0x1C 32 read-write n 0x0 0x0 OMODE Current RTC oscillator (1 => LFRC, 0 => XT) 0 1 read-write OSCF XT Oscillator is enabled but not oscillating 1 2 read-write UARTEN UART Enable 0x34 32 read-write n 0x0 0x0 UART0EN UART0 system clock control 0 2 read-write DIS Disable the UART0 system clock 0 EN Enable the UART0 system clock 1 REDUCE_FREQ Run UART_Hclk at the same frequency as UART_hfclk 2 EN_POWER_SAV Enable UART_hclk to reduce to UART_hfclk at low power mode 3 UART1EN UART1 system clock control 8 10 read-write DIS Disable the UART1 system clock 0 EN Enable the UART1 system clock 1 REDUCE_FREQ Run UART_Hclk at the same frequency as UART_hfclk 2 EN_POWER_SAV Enable UART_hclk to reduce to UART_hfclk at low power mode 3 CTIMER Counter/Timer CTIMER 0x0 0x0 0x310 registers n CTIMER 13 STIMER 18 STIMER_CMPR0 19 STIMER_CMPR1 20 STIMER_CMPR2 21 STIMER_CMPR3 22 STIMER_CMPR4 23 STIMER_CMPR5 24 STIMER_CMPR6 25 STIMER_CMPR7 26 CAPTURE_CONTROL Capture Control Register 0x108 32 read-write n 0x0 0x0 CAPTURE_A Selects whether capture is enabled for the specified capture register. 0 1 read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE_B Selects whether capture is enabled for the specified capture register. 1 2 read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE_C Selects whether capture is enabled for the specified capture register. 2 3 read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CAPTURE_D Selects whether capture is enabled for the specified capture register. 3 4 read-write DISABLE Capture function disabled. 0 ENABLE Capture function enabled. 1 CMPRA0 Counter/Timer A0 Compare Registers 0x4 32 read-write n 0x0 0x0 CMPR0A0 Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A. 0 16 read-write CMPR1A0 Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A. 16 32 read-write CMPRA1 Counter/Timer A1 Compare Registers 0x14 32 read-write n 0x0 0x0 CMPR0A1 Counter/Timer A1 Compare Register 0. 0 16 read-write CMPR1A1 Counter/Timer A1 Compare Register 1. 16 32 read-write CMPRA2 Counter/Timer A2 Compare Registers 0x24 32 read-write n 0x0 0x0 CMPR0A2 Counter/Timer A2 Compare Register 0. 0 16 read-write CMPR1A2 Counter/Timer A2 Compare Register 1. 16 32 read-write CMPRA3 Counter/Timer A3 Compare Registers 0x34 32 read-write n 0x0 0x0 CMPR0A3 Counter/Timer A3 Compare Register 0. 0 16 read-write CMPR1A3 Counter/Timer A3 Compare Register 1. 16 32 read-write CMPRB0 Counter/Timer B0 Compare Registers 0x8 32 read-write n 0x0 0x0 CMPR0B0 Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B. 0 16 read-write CMPR1B0 Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B. 16 32 read-write CMPRB1 Counter/Timer B1 Compare Registers 0x18 32 read-write n 0x0 0x0 CMPR0B1 Counter/Timer B1 Compare Register 0. 0 16 read-write CMPR1B1 Counter/Timer B1 Compare Register 1. 16 32 read-write CMPRB2 Counter/Timer B2 Compare Registers 0x28 32 read-write n 0x0 0x0 CMPR0B2 Counter/Timer B2 Compare Register 0. 0 16 read-write CMPR1B2 Counter/Timer B2 Compare Register 1. 16 32 read-write CMPRB3 Counter/Timer B3 Compare Registers 0x38 32 read-write n 0x0 0x0 CMPR0B3 Counter/Timer B3 Compare Register 0. 0 16 read-write CMPR1B3 Counter/Timer B3 Compare Register 1. 16 32 read-write CTRL0 Counter/Timer Control 0xC 32 read-write n 0x0 0x0 CTLINK0 Counter/Timer A0/B0 Link bit. 31 32 read-write TWO_16BIT_TIMERS Use A0/B0 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A0/B0 timers into a single 32-bit timer. 1 TMRA0CLK Counter/Timer A0 Clock Select. 1 6 read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK_DIV4 Clock source is HCLK / 4. 15 BUCKA Clock source is buck converter stream from MEM Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRA0CLR Counter/Timer A0 Clear bit. 11 12 read-write RUN Allow counter/timer A0 to run 0 CLEAR Holds counter/timer A0 at 0x0000. 1 TMRA0EN Counter/Timer A0 Enable bit. 0 1 read-write DIS Counter/Timer A0 Disable. 0 EN Counter/Timer A0 Enable. 1 TMRA0FN Counter/Timer A0 Function Select. 6 9 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1A0, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA0IE0 Counter/Timer A0 Interrupt Enable bit based on COMPR0. 9 10 read-write DIS Disable counter/timer A0 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A0 to generate an interrupt based on COMPR0. 1 TMRA0IE1 Counter/Timer A0 Interrupt Enable bit based on COMPR1. 10 11 read-write DIS Disable counter/timer A0 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A0 to generate an interrupt based on COMPR1. 1 TMRA0PE Counter/Timer A0 Output Enable bit. 13 14 read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA0POL. 0 EN Enable counter/timer A0 to generate a signal on TMRPINA. 1 TMRA0POL Counter/Timer A0 output polarity. 12 13 read-write NORMAL The polarity of the TMRPINA0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA0 pin is the inverse of the timer output. 1 TMRB0CLK Counter/Timer B0 Clock Select. 17 22 read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream from CORE Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRB0CLR Counter/Timer B0 Clear bit. 27 28 read-write RUN Allow counter/timer B0 to run 0 CLEAR Holds counter/timer B0 at 0x0000. 1 TMRB0EN Counter/Timer B0 Enable bit. 16 17 read-write DIS Counter/Timer B0 Disable. 0 EN Counter/Timer B0 Enable. 1 TMRB0FN Counter/Timer B0 Function Select. 22 25 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B0, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B0, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB0IE0 Counter/Timer B0 Interrupt Enable bit for COMPR0. 25 26 read-write DIS Disable counter/timer B0 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B0 to generate an interrupt based on COMPR0 1 TMRB0IE1 Counter/Timer B0 Interrupt Enable bit for COMPR1. 26 27 read-write DIS Disable counter/timer B0 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B0 to generate an interrupt based on COMPR1. 1 TMRB0PE Counter/Timer B0 Output Enable bit. 29 30 read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB0POL. 0 EN Enable counter/timer B0 to generate a signal on TMRPINB. 1 TMRB0POL Counter/Timer B0 output polarity. 28 29 read-write NORMAL The polarity of the TMRPINB0 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB0 pin is the inverse of the timer output. 1 CTRL1 Counter/Timer Control 0x1C 32 read-write n 0x0 0x0 CTLINK1 Counter/Timer A1/B1 Link bit. 31 32 read-write TWO_16BIT_TIMERS Use A1/B1 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A1/B1 timers into a single 32-bit timer. 1 TMRA1CLK Counter/Timer A1 Clock Select. 1 6 read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream from MEM Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRA1CLR Counter/Timer A1 Clear bit. 11 12 read-write RUN Allow counter/timer A1 to run 0 CLEAR Holds counter/timer A1 at 0x0000. 1 TMRA1EN Counter/Timer A1 Enable bit. 0 1 read-write DIS Counter/Timer A1 Disable. 0 EN Counter/Timer A1 Enable. 1 TMRA1FN Counter/Timer A1 Function Select. 6 9 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1A1, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA1IE0 Counter/Timer A1 Interrupt Enable bit based on COMPR0. 9 10 read-write DIS Disable counter/timer A1 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A1 to generate an interrupt based on COMPR0. 1 TMRA1IE1 Counter/Timer A1 Interrupt Enable bit based on COMPR1. 10 11 read-write DIS Disable counter/timer A1 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A1 to generate an interrupt based on COMPR1. 1 TMRA1PE Counter/Timer A1 Output Enable bit. 13 14 read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA1POL. 0 EN Enable counter/timer A1 to generate a signal on TMRPINA. 1 TMRA1POL Counter/Timer A1 output polarity. 12 13 read-write NORMAL The polarity of the TMRPINA1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA1 pin is the inverse of the timer output. 1 TMRB1CLK Counter/Timer B1 Clock Select. 17 22 read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream from CORE Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRB1CLR Counter/Timer B1 Clear bit. 27 28 read-write RUN Allow counter/timer B1 to run 0 CLEAR Holds counter/timer B1 at 0x0000. 1 TMRB1EN Counter/Timer B1 Enable bit. 16 17 read-write DIS Counter/Timer B1 Disable. 0 EN Counter/Timer B1 Enable. 1 TMRB1FN Counter/Timer B1 Function Select. 22 25 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B1, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B1, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB1IE0 Counter/Timer B1 Interrupt Enable bit for COMPR0. 25 26 read-write DIS Disable counter/timer B1 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B1 to generate an interrupt based on COMPR0 1 TMRB1IE1 Counter/Timer B1 Interrupt Enable bit for COMPR1. 26 27 read-write DIS Disable counter/timer B1 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B1 to generate an interrupt based on COMPR1. 1 TMRB1PE Counter/Timer B1 Output Enable bit. 29 30 read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB1POL. 0 EN Enable counter/timer B1 to generate a signal on TMRPINB. 1 TMRB1POL Counter/Timer B1 output polarity. 28 29 read-write NORMAL The polarity of the TMRPINB1 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB1 pin is the inverse of the timer output. 1 CTRL2 Counter/Timer Control 0x2C 32 read-write n 0x0 0x0 CTLINK2 Counter/Timer A2/B2 Link bit. 31 32 read-write TWO_16BIT_TIMERS Use A2/B2 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A2/B2 timers into a single 32-bit timer. 1 TMRA2CLK Counter/Timer A2 Clock Select. 1 6 read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream from CORE Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRA2CLR Counter/Timer A2 Clear bit. 11 12 read-write RUN Allow counter/timer A2 to run 0 CLEAR Holds counter/timer A2 at 0x0000. 1 TMRA2EN Counter/Timer A2 Enable bit. 0 1 read-write DIS Counter/Timer A2 Disable. 0 EN Counter/Timer A2 Enable. 1 TMRA2FN Counter/Timer A2 Function Select. 6 9 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1A2, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA2IE0 Counter/Timer A2 Interrupt Enable bit based on COMPR0. 9 10 read-write DIS Disable counter/timer A2 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A2 to generate an interrupt based on COMPR0. 1 TMRA2IE1 Counter/Timer A2 Interrupt Enable bit based on COMPR1. 10 11 read-write DIS Disable counter/timer A2 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A2 to generate an interrupt based on COMPR1. 1 TMRA2PE Counter/Timer A2 Output Enable bit. 13 14 read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA2POL. 0 EN Enable counter/timer A2 to generate a signal on TMRPINA. 1 TMRA2POL Counter/Timer A2 output polarity. 12 13 read-write NORMAL The polarity of the TMRPINA2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA2 pin is the inverse of the timer output. 1 TMRB2CLK Counter/Timer B2 Clock Select. 17 22 read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream from MEM Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRB2CLR Counter/Timer B2 Clear bit. 27 28 read-write RUN Allow counter/timer B2 to run 0 CLEAR Holds counter/timer B2 at 0x0000. 1 TMRB2EN Counter/Timer B2 Enable bit. 16 17 read-write DIS Counter/Timer B2 Disable. 0 EN Counter/Timer B2 Enable. 1 TMRB2FN Counter/Timer B2 Function Select. 22 25 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B2, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B2, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB2IE0 Counter/Timer B2 Interrupt Enable bit for COMPR0. 25 26 read-write DIS Disable counter/timer B2 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B2 to generate an interrupt based on COMPR0 1 TMRB2IE1 Counter/Timer B2 Interrupt Enable bit for COMPR1. 26 27 read-write DIS Disable counter/timer B2 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B2 to generate an interrupt based on COMPR1. 1 TMRB2PE Counter/Timer B2 Output Enable bit. 29 30 read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB2POL. 0 EN Enable counter/timer B2 to generate a signal on TMRPINB. 1 TMRB2POL Counter/Timer B2 output polarity. 28 29 read-write NORMAL The polarity of the TMRPINB2 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB2 pin is the inverse of the timer output. 1 CTRL3 Counter/Timer Control 0x3C 32 read-write n 0x0 0x0 ADCEN Special Timer A3 enable for ADC function. 15 16 read-write CTLINK3 Counter/Timer A3/B3 Link bit. 31 32 read-write TWO_16BIT_TIMERS Use A3/B3 timers as two independent 16-bit timers (default). 0 32BIT_TIMER Link A3/B3 timers into a single 32-bit timer. 1 TMRA3CLK Counter/Timer A3 Clock Select. 1 6 read-write TMRPIN Clock source is TMRPINA. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKB Clock source is buck converter stream from CORE Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRA3CLR Counter/Timer A3 Clear bit. 11 12 read-write RUN Allow counter/timer A3 to run 0 CLEAR Holds counter/timer A3 at 0x0000. 1 TMRA3EN Counter/Timer A3 Enable bit. 0 1 read-write DIS Counter/Timer A3 Disable. 0 EN Counter/Timer A3 Enable. 1 TMRA3FN Counter/Timer A3 Function Select. 6 9 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0A3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1A3, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRA3IE0 Counter/Timer A3 Interrupt Enable bit based on COMPR0. 9 10 read-write DIS Disable counter/timer A3 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer A3 to generate an interrupt based on COMPR0. 1 TMRA3IE1 Counter/Timer A3 Interrupt Enable bit based on COMPR1. 10 11 read-write DIS Disable counter/timer A3 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer A3 to generate an interrupt based on COMPR1. 1 TMRA3PE Counter/Timer A3 Output Enable bit. 13 14 read-write DIS Counter/Timer A holds the TMRPINA signal at the value TMRA3POL. 0 EN Enable counter/timer A3 to generate a signal on TMRPINA. 1 TMRA3POL Counter/Timer A3 output polarity. 12 13 read-write NORMAL The polarity of the TMRPINA3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINA3 pin is the inverse of the timer output. 1 TMRB3CLK Counter/Timer B3 Clock Select. 17 22 read-write TMRPIN Clock source is TMRPINB. 0 HFRC_DIV4 Clock source is HFRC / 4 1 LFRC_DIV2 Clock source is LFRC / 2 10 LFRC_DIV32 Clock source is LFRC / 32 11 LFRC_DIV1K Clock source is LFRC / 1024 12 LFRC Clock source is LFRC 13 RTC_100HZ Clock source is 100 Hz from the current RTC oscillator. 14 HCLK Clock source is HCLK. 15 BUCKA Clock source is buck converter stream from MEM Buck. 16 HFRC_DIV16 Clock source is HFRC / 16 2 HFRC_DIV256 Clock source is HFRC / 256 3 HFRC_DIV1024 Clock source is HFRC / 1024 4 HFRC_DIV4K Clock source is HFRC / 4096 5 XT Clock source is the XT (uncalibrated). 6 XT_DIV2 Clock source is XT / 2 7 XT_DIV16 Clock source is XT / 16 8 XT_DIV256 Clock source is XT / 256 9 TMRB3CLR Counter/Timer B3 Clear bit. 27 28 read-write RUN Allow counter/timer B3 to run 0 CLEAR Holds counter/timer B3 at 0x0000. 1 TMRB3EN Counter/Timer B3 Enable bit. 16 17 read-write DIS Counter/Timer B3 Disable. 0 EN Counter/Timer B3 Enable. 1 TMRB3FN Counter/Timer B3 Function Select. 22 25 read-write SINGLECOUNT Single count (output toggles and sticks). Count to CMPR0B3, stop. 0 REPEATEDCOUNT Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart. 1 PULSE_ONCE Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B3, deassert, stop. 2 PULSE_CONT Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart. 3 CONTINUOUS Continuous run (aka Free Run). Count continuously. 4 TMRB3IE0 Counter/Timer B3 Interrupt Enable bit for COMPR0. 25 26 read-write DIS Disable counter/timer B3 from generating an interrupt based on COMPR0. 0 EN Enable counter/timer B3 to generate an interrupt based on COMPR0 1 TMRB3IE1 Counter/Timer B3 Interrupt Enable bit for COMPR1. 26 27 read-write DIS Disable counter/timer B3 from generating an interrupt based on COMPR1. 0 EN Enable counter/timer B3 to generate an interrupt based on COMPR1. 1 TMRB3PE Counter/Timer B3 Output Enable bit. 29 30 read-write DIS Counter/Timer B holds the TMRPINB signal at the value TMRB3POL. 0 EN Enable counter/timer B3 to generate a signal on TMRPINB. 1 TMRB3POL Counter/Timer B3 output polarity. 28 29 read-write NORMAL The polarity of the TMRPINB3 pin is the same as the timer output. 0 INVERTED The polarity of the TMRPINB3 pin is the inverse of the timer output. 1 INTCLR Counter/Timer Interrupts: Clear 0x208 32 read-write n 0x0 0x0 CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. 0 1 read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. 8 9 read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. 2 3 read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. 10 11 read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. 4 5 read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. 12 13 read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. 6 7 read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. 14 15 read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. 1 2 read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. 9 10 read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. 3 4 read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. 11 12 read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. 5 6 read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. 13 14 read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. 7 8 read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. 15 16 read-write INTEN Counter/Timer Interrupts: Enable 0x200 32 read-write n 0x0 0x0 CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. 0 1 read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. 8 9 read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. 2 3 read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. 10 11 read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. 4 5 read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. 12 13 read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. 6 7 read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. 14 15 read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. 1 2 read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. 9 10 read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. 3 4 read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. 11 12 read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. 5 6 read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. 13 14 read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. 7 8 read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. 15 16 read-write INTSET Counter/Timer Interrupts: Set 0x20C 32 read-write n 0x0 0x0 CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. 0 1 read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. 8 9 read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. 2 3 read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. 10 11 read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. 4 5 read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. 12 13 read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. 6 7 read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. 14 15 read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. 1 2 read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. 9 10 read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. 3 4 read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. 11 12 read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. 5 6 read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. 13 14 read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. 7 8 read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. 15 16 read-write INTSTAT Counter/Timer Interrupts: Status 0x204 32 read-write n 0x0 0x0 CTMRA0C0INT Counter/Timer A0 interrupt based on COMPR0. 0 1 read-write CTMRA0C1INT Counter/Timer A0 interrupt based on COMPR1. 8 9 read-write CTMRA1C0INT Counter/Timer A1 interrupt based on COMPR0. 2 3 read-write CTMRA1C1INT Counter/Timer A1 interrupt based on COMPR1. 10 11 read-write CTMRA2C0INT Counter/Timer A2 interrupt based on COMPR0. 4 5 read-write CTMRA2C1INT Counter/Timer A2 interrupt based on COMPR1. 12 13 read-write CTMRA3C0INT Counter/Timer A3 interrupt based on COMPR0. 6 7 read-write CTMRA3C1INT Counter/Timer A3 interrupt based on COMPR1. 14 15 read-write CTMRB0C0INT Counter/Timer B0 interrupt based on COMPR0. 1 2 read-write CTMRB0C1INT Counter/Timer B0 interrupt based on COMPR1. 9 10 read-write CTMRB1C0INT Counter/Timer B1 interrupt based on COMPR0. 3 4 read-write CTMRB1C1INT Counter/Timer B1 interrupt based on COMPR1. 11 12 read-write CTMRB2C0INT Counter/Timer B2 interrupt based on COMPR0. 5 6 read-write CTMRB2C1INT Counter/Timer B2 interrupt based on COMPR1. 13 14 read-write CTMRB3C0INT Counter/Timer B3 interrupt based on COMPR0. 7 8 read-write CTMRB3C1INT Counter/Timer B3 interrupt based on COMPR1. 15 16 read-write SCAPT0 Capture Register A 0x1E0 32 read-write n 0x0 0x0 VALUE Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 0 32 read-write SCAPT1 Capture Register B 0x1E4 32 read-write n 0x0 0x0 VALUE Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 0 32 read-write SCAPT2 Capture Register C 0x1E8 32 read-write n 0x0 0x0 VALUE Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 0 32 read-write SCAPT3 Capture Register D 0x1EC 32 read-write n 0x0 0x0 VALUE Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set. 0 32 read-write SCMPR0 Compare Register A 0x110 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_A_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR1 Compare Register B 0x114 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_B_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR2 Compare Register C 0x118 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_C_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR3 Compare Register D 0x11C 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_D_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR4 Compare Register E 0x120 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_E_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR5 Compare Register F 0x124 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_F_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR6 Compare Register G 0x128 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_G_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SCMPR7 Compare Register H 0x12C 32 read-write n 0x0 0x0 VALUE Compare this value to the value in the COUNTER register according to the match criterion, as selected in the COMPARE_H_EN bit in the REG_CTIMER_STCGF register. 0 32 read-write SNVR0 System Timer NVRAM_A Register 0x1F0 32 read-write n 0x0 0x0 VALUE Value of the 32-bit counter as it ticks over. 0 32 read-write SNVR1 System Timer NVRAM_B Register 0x1F4 32 read-write n 0x0 0x0 VALUE Value of the 32-bit counter as it ticks over. 0 32 read-write SNVR2 System Timer NVRAM_C Register 0x1F8 32 read-write n 0x0 0x0 VALUE Value of the 32-bit counter as it ticks over. 0 32 read-write STCFG Configuration Register 0x100 32 read-write n 0x0 0x0 CLEAR Set this bit to one to clear the System Timer register. If this bit is set to '1', the system timer register will stay cleared. It needs to be set to '0' for the system timer to start running. 30 31 read-write RUN Let the COUNTER register run on its input clock. 0 CLEAR Stop the COUNTER register for loading. 1 CLKSEL Selects an appropriate clock source and divider to use for the System Timer clock. 0 4 read-write NOCLK No clock enabled. 0 HFRC_DIV16 3MHz from the HFRC clock divider. 1 HFRC_DIV256 187.5KHz from the HFRC clock divider. 2 XTAL_DIV1 32768Hz from the crystal oscillator. 3 XTAL_DIV2 16384Hz from the crystal oscillator. 4 XTAL_DIV32 1024Hz from the crystal oscillator. 5 LFRC_DIV1 Approximately 1KHz from the LFRC oscillator (uncalibrated). 6 CTIMER0A Use CTIMER 0 section A as a prescaler for the clock source. 7 CTIMER0B Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source. 8 COMPARE_A_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 8 9 read-write DISABLE Compare A disabled. 0 ENABLE Compare A enabled. 1 COMPARE_B_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 9 10 read-write DISABLE Compare B disabled. 0 ENABLE Compare B enabled. 1 COMPARE_C_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 10 11 read-write DISABLE Compare C disabled. 0 ENABLE Compare C enabled. 1 COMPARE_D_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 11 12 read-write DISABLE Compare D disabled. 0 ENABLE Compare D enabled. 1 COMPARE_E_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 12 13 read-write DISABLE Compare E disabled. 0 ENABLE Compare E enabled. 1 COMPARE_F_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 13 14 read-write DISABLE Compare F disabled. 0 ENABLE Compare F enabled. 1 COMPARE_G_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 14 15 read-write DISABLE Compare G disabled. 0 ENABLE Compare G enabled. 1 COMPARE_H_EN Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. 15 16 read-write DISABLE Compare H disabled. 0 ENABLE Compare H enabled. 1 FREEZE Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume. 31 32 read-write THAW Let the COUNTER register run on its input clock. 0 FREEZE Stop the COUNTER register for loading. 1 STMINTCLR STIMER Interrupt registers: Clear 0x308 32 read-write n 0x0 0x0 CAPTUREA CAPTURE register A has grabbed the value in the counter 9 10 read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter 10 11 read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter 11 12 read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTURED CAPTURE register D has grabbed the value in the counter 12 13 read-write CAPD_INT Capture D interrupt status bit was set. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. 0 1 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. 1 2 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. 2 3 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. 3 4 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. 4 5 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. 5 6 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. 6 7 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. 7 8 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 8 9 read-write OFLOW_INT Overflow interrupt status bit was set. 1 STMINTEN STIMER Interrupt registers: Enable 0x300 32 read-write n 0x0 0x0 CAPTUREA CAPTURE register A has grabbed the value in the counter 9 10 read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter 10 11 read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter 11 12 read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTURED CAPTURE register D has grabbed the value in the counter 12 13 read-write CAPD_INT Capture D interrupt status bit was set. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. 0 1 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. 1 2 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. 2 3 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. 3 4 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. 4 5 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. 5 6 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. 6 7 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. 7 8 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 8 9 read-write OFLOW_INT Overflow interrupt status bit was set. 1 STMINTSET STIMER Interrupt registers: Set 0x30C 32 read-write n 0x0 0x0 CAPTUREA CAPTURE register A has grabbed the value in the counter 9 10 read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter 10 11 read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter 11 12 read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTURED CAPTURE register D has grabbed the value in the counter 12 13 read-write CAPD_INT Capture D interrupt status bit was set. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. 0 1 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. 1 2 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. 2 3 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. 3 4 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. 4 5 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. 5 6 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. 6 7 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. 7 8 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 8 9 read-write OFLOW_INT Overflow interrupt status bit was set. 1 STMINTSTAT STIMER Interrupt registers: Status 0x304 32 read-write n 0x0 0x0 CAPTUREA CAPTURE register A has grabbed the value in the counter 9 10 read-write CAPA_INT CAPTURE A interrupt status bit was set. 1 CAPTUREB CAPTURE register B has grabbed the value in the counter 10 11 read-write CAPB_INT CAPTURE B interrupt status bit was set. 1 CAPTUREC CAPTURE register C has grabbed the value in the counter 11 12 read-write CAPC_INT CAPTURE C interrupt status bit was set. 1 CAPTURED CAPTURE register D has grabbed the value in the counter 12 13 read-write CAPD_INT Capture D interrupt status bit was set. 1 COMPAREA COUNTER is greater than or equal to COMPARE register A. 0 1 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREB COUNTER is greater than or equal to COMPARE register B. 1 2 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREC COUNTER is greater than or equal to COMPARE register C. 2 3 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPARED COUNTER is greater than or equal to COMPARE register D. 3 4 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREE COUNTER is greater than or equal to COMPARE register E. 4 5 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREF COUNTER is greater than or equal to COMPARE register F. 5 6 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREG COUNTER is greater than or equal to COMPARE register G. 6 7 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 COMPAREH COUNTER is greater than or equal to COMPARE register H. 7 8 read-write COMPARED COUNTER greater than or equal to COMPARE register. 1 OVERFLOW COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. 8 9 read-write OFLOW_INT Overflow interrupt status bit was set. 1 STTMR System Timer Count Register (Real Time Counter) 0x104 32 read-write n 0x0 0x0 VALUE Value of the 32-bit counter as it ticks over. 0 32 read-write TMR0 Counter/Timer Register 0x0 32 read-write n 0x0 0x0 CTTMRA0 Counter/Timer A0. 0 16 read-write CTTMRB0 Counter/Timer B0. 16 32 read-write TMR1 Counter/Timer Register 0x10 32 read-write n 0x0 0x0 CTTMRA1 Counter/Timer A1. 0 16 read-write CTTMRB1 Counter/Timer B1. 16 32 read-write TMR2 Counter/Timer Register 0x20 32 read-write n 0x0 0x0 CTTMRA2 Counter/Timer A2. 0 16 read-write CTTMRB2 Counter/Timer B2. 16 32 read-write TMR3 Counter/Timer Register 0x30 32 read-write n 0x0 0x0 CTTMRA3 Counter/Timer A3. 0 16 read-write CTTMRB3 Counter/Timer B3. 16 32 read-write GPIO General Purpose IO GPIO 0x0 0x0 0x220 registers n GPIO 12 ALTPADCFGA Alternate Pad Configuration reg0 (Pads 3,2,1,0) 0xE0 32 read-write n 0x0 0x0 PAD0_DS1 Pad 0 high order drive strength selection. Used in conjunction with PAD0STRNG field to set the pad drive strength. 0 1 read-write PAD0_SR Pad 0 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD1_DS1 Pad 1 high order drive strength selection. Used in conjunction with PAD1STRNG field to set the pad drive strength. 8 9 read-write PAD1_SR Pad 1 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD2_DS1 Pad 2 high order drive strength selection. Used in conjunction with PAD2STRNG field to set the pad drive strength. 16 17 read-write PAD2_SR Pad 2 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD3_DS1 Pad 3 high order drive strength selection. Used in conjunction with PAD3STRNG field to set the pad drive strength. 24 25 read-write PAD3_SR Pad 3 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGB Alternate Pad Configuration reg1 (Pads 7,6,5,4) 0xE4 32 read-write n 0x0 0x0 PAD4_DS1 Pad 4 high order drive strength selection. Used in conjunction with PAD4STRNG field to set the pad drive strength. 0 1 read-write PAD4_SR Pad 4 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD5_DS1 Pad 5 high order drive strength selection. Used in conjunction with PAD5STRNG field to set the pad drive strength. 8 9 read-write PAD5_SR Pad 5 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD6_DS1 Pad 6 high order drive strength selection. Used in conjunction with PAD6STRNG field to set the pad drive strength. 16 17 read-write PAD6_SR Pad 6 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD7_DS1 Pad 7 high order drive strength selection. Used in conjunction with PAD7STRNG field to set the pad drive strength. 24 25 read-write PAD7_SR Pad 7 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGC Alternate Pad Configuration reg2 (Pads 11,10,9,8) 0xE8 32 read-write n 0x0 0x0 PAD10_DS1 Pad 10 high order drive strength selection. Used in conjunction with PAD10STRNG field to set the pad drive strength. 16 17 read-write PAD10_SR Pad 10 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD11_DS1 Pad 11 high order drive strength selection. Used in conjunction with PAD11STRNG field to set the pad drive strength. 24 25 read-write PAD11_SR Pad 11 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 PAD8_DS1 Pad 8 high order drive strength selection. Used in conjunction with PAD8STRNG field to set the pad drive strength. 0 1 read-write PAD8_SR Pad 8 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD9_DS1 Pad 9 high order drive strength selection. Used in conjunction with PAD9STRNG field to set the pad drive strength. 8 9 read-write PAD9_SR Pad 9 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGD Alternate Pad Configuration reg3 (Pads 15,14,13,12) 0xEC 32 read-write n 0x0 0x0 PAD12_DS1 Pad 12 high order drive strength selection. Used in conjunction with PAD12STRNG field to set the pad drive strength. 0 1 read-write PAD12_SR Pad 12 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD13_DS1 Pad 13 high order drive strength selection. Used in conjunction with PAD13STRNG field to set the pad drive strength. 8 9 read-write PAD13_SR Pad 13 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD14_DS1 Pad 14 high order drive strength selection. Used in conjunction with PAD14STRNG field to set the pad drive strength. 16 17 read-write PAD14_SR Pad 14 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD15_DS1 Pad 15 high order drive strength selection. Used in conjunction with PAD15STRNG field to set the pad drive strength. 24 25 read-write PAD15_SR Pad 15 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGE Alternate Pad Configuration reg4 (Pads 19,18,17,16) 0xF0 32 read-write n 0x0 0x0 PAD16_DS1 Pad 16 high order drive strength selection. Used in conjunction with PAD16STRNG field to set the pad drive strength. 0 1 read-write PAD16_SR Pad 16 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD17_DS1 Pad 17 high order drive strength selection. Used in conjunction with PAD17STRNG field to set the pad drive strength. 8 9 read-write PAD17_SR Pad 17 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD18_DS1 Pad 18 high order drive strength selection. Used in conjunction with PAD18STRNG field to set the pad drive strength. 16 17 read-write PAD18_SR Pad 18 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD19_DS1 Pad 19 high order drive strength selection. Used in conjunction with PAD19STRNG field to set the pad drive strength. 24 25 read-write PAD19_SR Pad 19 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGF Alternate Pad Configuration reg5 (Pads 23,22,21,20) 0xF4 32 read-write n 0x0 0x0 PAD20_DS1 Pad 20 high order drive strength selection. Used in conjunction with PAD20STRNG field to set the pad drive strength. 0 1 read-write PAD20_SR Pad 20 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD21_DS1 Pad 21 high order drive strength selection. Used in conjunction with PAD21STRNG field to set the pad drive strength. 8 9 read-write PAD21_SR Pad 21 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD22_DS1 Pad 22 high order drive strength selection. Used in conjunction with PAD22STRNG field to set the pad drive strength. 16 17 read-write PAD22_SR Pad 22 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD23_DS1 Pad 23 high order drive strength selection. Used in conjunction with PAD23STRNG field to set the pad drive strength. 24 25 read-write PAD23_SR Pad 23 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGG Alternate Pad Configuration reg6 (Pads 27,26,25,24) 0xF8 32 read-write n 0x0 0x0 PAD24_DS1 Pad 24 high order drive strength selection. Used in conjunction with PAD24STRNG field to set the pad drive strength. 0 1 read-write PAD24_SR Pad 24 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD25_DS1 Pad 25 high order drive strength selection. Used in conjunction with PAD25STRNG field to set the pad drive strength. 8 9 read-write PAD25_SR Pad 25 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD26_DS1 Pad 26 high order drive strength selection. Used in conjunction with PAD26STRNG field to set the pad drive strength. 16 17 read-write PAD26_SR Pad 26 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD27_DS1 Pad 27 high order drive strength selection. Used in conjunction with PAD27STRNG field to set the pad drive strength. 24 25 read-write PAD27_SR Pad 27 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGH Alternate Pad Configuration reg7 (Pads 31,30,29,28) 0xFC 32 read-write n 0x0 0x0 PAD28_DS1 Pad 28 high order drive strength selection. Used in conjunction with PAD28STRNG field to set the pad drive strength. 0 1 read-write PAD28_SR Pad 28 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD29_DS1 Pad 29 high order drive strength selection. Used in conjunction with PAD29STRNG field to set the pad drive strength. 8 9 read-write PAD29_SR Pad 29 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD30_DS1 Pad 30 high order drive strength selection. Used in conjunction with PAD30STRNG field to set the pad drive strength. 16 17 read-write PAD30_SR Pad 30 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD31_DS1 Pad 31 high order drive strength selection. Used in conjunction with PAD31STRNG field to set the pad drive strength. 24 25 read-write PAD31_SR Pad 31 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGI Alternate Pad Configuration reg8 (Pads 35,34,33,32) 0x100 32 read-write n 0x0 0x0 PAD32_DS1 Pad 32 high order drive strength selection. Used in conjunction with PAD32STRNG field to set the pad drive strength. 0 1 read-write PAD32_SR Pad 32 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD33_DS1 Pad 33 high order drive strength selection. Used in conjunction with PAD33STRNG field to set the pad drive strength. 8 9 read-write PAD33_SR Pad 33 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD34_DS1 Pad 34 high order drive strength selection. Used in conjunction with PAD34STRNG field to set the pad drive strength. 16 17 read-write PAD34_SR Pad 34 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD35_DS1 Pad 35 high order drive strength selection. Used in conjunction with PAD35STRNG field to set the pad drive strength. 24 25 read-write PAD35_SR Pad 35 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGJ Alternate Pad Configuration reg9 (Pads 39,38,37,36) 0x104 32 read-write n 0x0 0x0 PAD36_DS1 Pad 36 high order drive strength selection. Used in conjunction with PAD36STRNG field to set the pad drive strength. 0 1 read-write PAD36_SR Pad 36 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD37_DS1 Pad 37 high order drive strength selection. Used in conjunction with PAD37STRNG field to set the pad drive strength. 8 9 read-write PAD37_SR Pad 37 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD38_DS1 Pad 38 high order drive strength selection. Used in conjunction with PAD38STRNG field to set the pad drive strength. 16 17 read-write PAD38_SR Pad 38 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD39_DS1 Pad 39 high order drive strength selection. Used in conjunction with PAD39STRNG field to set the pad drive strength. 24 25 read-write PAD39_SR Pad 39 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGK Alternate Pad Configuration reg10 (Pads 43,42,41,40) 0x108 32 read-write n 0x0 0x0 PAD40_DS1 Pad 40 high order drive strength selection. Used in conjunction with PAD40STRNG field to set the pad drive strength. 0 1 read-write PAD40_SR Pad 40 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD41_DS1 Pad 41 high order drive strength selection. Used in conjunction with PAD41STRNG field to set the pad drive strength. 8 9 read-write PAD41_SR Pad 41 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD42_DS1 Pad 42 high order drive strength selection. Used in conjunction with PAD42STRNG field to set the pad drive strength. 16 17 read-write PAD42_SR Pad 42 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD43_DS1 Pad 43 high order drive strength selection. Used in conjunction with PAD43STRNG field to set the pad drive strength. 24 25 read-write PAD43_SR Pad 43 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGL Alternate Pad Configuration reg11 (Pads 47,46,45,44) 0x10C 32 read-write n 0x0 0x0 PAD44_DS1 Pad 44 high order drive strength selection. Used in conjunction with PAD44STRNG field to set the pad drive strength. 0 1 read-write PAD44_SR Pad 44 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD45_DS1 Pad 45 high order drive strength selection. Used in conjunction with PAD45STRNG field to set the pad drive strength. 8 9 read-write PAD45_SR Pad 45 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 PAD46_DS1 Pad 46 high order drive strength selection. Used in conjunction with PAD46STRNG field to set the pad drive strength. 16 17 read-write PAD46_SR Pad 46 slew rate selection. 20 21 read-write SR_EN Enables Slew rate control on pad 1 PAD47_DS1 Pad 47 high order drive strength selection. Used in conjunction with PAD47STRNG field to set the pad drive strength. 24 25 read-write PAD47_SR Pad 47 slew rate selection. 28 29 read-write SR_EN Enables Slew rate control on pad 1 ALTPADCFGM Alternate Pad Configuration reg12 (Pads 49,48) 0x110 32 read-write n 0x0 0x0 PAD48_DS1 Pad 48 high order drive strength selection. Used in conjunction with PAD48STRNG field to set the pad drive strength. 0 1 read-write PAD48_SR Pad 48 slew rate selection. 4 5 read-write SR_EN Enables Slew rate control on pad 1 PAD49_DS1 Pad 49 high order drive strength selection. Used in conjunction with PAD49STRNG field to set the pad drive strength. 8 9 read-write PAD49_SR Pad 49 slew rate selection. 12 13 read-write SR_EN Enables Slew rate control on pad 1 CFGA GPIO Configuration Register A 0x40 32 read-write n 0x0 0x0 GPIO0INCFG GPIO0 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO0INTD GPIO0 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO0OUTCFG GPIO0 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO1INCFG GPIO1 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO1INTD GPIO1 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO1OUTCFG GPIO1 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO2INCFG GPIO2 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO2INTD GPIO2 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO2OUTCFG GPIO2 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO3INCFG GPIO3 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO3INTD GPIO3 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO3OUTCFG GPIO3 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO4INCFG GPIO4 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO4INTD GPIO4 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO4OUTCFG GPIO4 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO5INCFG GPIO5 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO5INTD GPIO5 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO5OUTCFG GPIO5 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO6INCFG GPIO6 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO6INTD GPIO6 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO6OUTCFG GPIO6 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO7INCFG GPIO7 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO7INTD GPIO7 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO7OUTCFG GPIO7 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGB GPIO Configuration Register B 0x44 32 read-write n 0x0 0x0 GPIO10INCFG GPIO10 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO10INTD GPIO10 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO10OUTCFG GPIO10 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO11INCFG GPIO11 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO11INTD GPIO11 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO11OUTCFG GPIO11 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO12INCFG GPIO12 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO12INTD GPIO12 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO12OUTCFG GPIO12 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO13INCFG GPIO13 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO13INTD GPIO13 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO13OUTCFG GPIO13 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO14INCFG GPIO14 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO14INTD GPIO14 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO14OUTCFG GPIO14 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO15INCFG GPIO15 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO15INTD GPIO15 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO15OUTCFG GPIO15 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO8INCFG GPIO8 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO8INTD GPIO8 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO8OUTCFG GPIO8 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO9INCFG GPIO9 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO9INTD GPIO9 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO9OUTCFG GPIO9 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGC GPIO Configuration Register C 0x48 32 read-write n 0x0 0x0 GPIO16INCFG GPIO16 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO16INTD GPIO16 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO16OUTCFG GPIO16 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO17INCFG GPIO17 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO17INTD GPIO17 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO17OUTCFG GPIO17 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO18INCFG GPIO18 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO18INTD GPIO18 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO18OUTCFG GPIO18 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO19INCFG GPIO19 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO19INTD GPIO19 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO19OUTCFG GPIO19 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO20INCFG GPIO20 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO20INTD GPIO20 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO20OUTCFG GPIO20 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO21INCFG GPIO21 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO21INTD GPIO21 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO21OUTCFG GPIO21 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO22INCFG GPIO22 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO22INTD GPIO22 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO22OUTCFG GPIO22 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO23INCFG GPIO23 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO23INTD GPIO23 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO23OUTCFG GPIO23 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGD GPIO Configuration Register D 0x4C 32 read-write n 0x0 0x0 GPIO24INCFG GPIO24 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO24INTD GPIO24 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO24OUTCFG GPIO24 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO25INCFG GPIO25 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO25INTD GPIO25 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO25OUTCFG GPIO25 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO26INCFG GPIO26 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO26INTD GPIO26 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO26OUTCFG GPIO26 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO27INCFG GPIO27 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO27INTD GPIO27 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO27OUTCFG GPIO27 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO28INCFG GPIO28 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO28INTD GPIO28 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO28OUTCFG GPIO28 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO29INCFG GPIO29 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO29INTD GPIO29 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO29OUTCFG GPIO29 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO30INCFG GPIO30 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO30INTD GPIO30 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO30OUTCFG GPIO30 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO31INCFG GPIO31 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO31INTD GPIO31 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO31OUTCFG GPIO31 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGE GPIO Configuration Register E 0x50 32 read-write n 0x0 0x0 GPIO32INCFG GPIO32 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO32INTD GPIO32 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO32OUTCFG GPIO32 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO33INCFG GPIO33 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO33INTD GPIO33 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO33OUTCFG GPIO33 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO34INCFG GPIO34 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO34INTD GPIO34 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO34OUTCFG GPIO34 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO35INCFG GPIO35 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO35INTD GPIO35 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO35OUTCFG GPIO35 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO36INCFG GPIO36 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO36INTD GPIO36 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO36OUTCFG GPIO36 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO37INCFG GPIO37 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO37INTD GPIO37 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO37OUTCFG GPIO37 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO38INCFG GPIO38 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO38INTD GPIO38 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO38OUTCFG GPIO38 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO39INCFG GPIO39 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO39INTD GPIO39 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO39OUTCFG GPIO39 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGF GPIO Configuration Register F 0x54 32 read-write n 0x0 0x0 GPIO40INCFG GPIO40 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO40INTD GPIO40 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO40OUTCFG GPIO40 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO41INCFG GPIO41 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO41INTD GPIO41 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO41OUTCFG GPIO41 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO42INCFG GPIO42 input enable. 8 9 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO42INTD GPIO42 interrupt direction. 11 12 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO42OUTCFG GPIO42 output configuration. 9 11 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO43INCFG GPIO43 input enable. 12 13 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO43INTD GPIO43 interrupt direction. 15 16 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO43OUTCFG GPIO43 output configuration. 13 15 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO44INCFG GPIO44 input enable. 16 17 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO44INTD GPIO44 interrupt direction. 19 20 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO44OUTCFG GPIO44 output configuration. 17 19 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO45INCFG GPIO45 input enable. 20 21 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO45INTD GPIO45 interrupt direction. 23 24 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO45OUTCFG GPIO45 output configuration. 21 23 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO46INCFG GPIO46 input enable. 24 25 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO46INTD GPIO46 interrupt direction. 27 28 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO46OUTCFG GPIO46 output configuration. 25 27 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO47INCFG GPIO47 input enable. 28 29 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO47INTD GPIO47 interrupt direction. 31 32 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO47OUTCFG GPIO47 output configuration. 29 31 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 CFGG GPIO Configuration Register G 0x58 32 read-write n 0x0 0x0 GPIO48INCFG GPIO48 input enable. 0 1 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO48INTD GPIO48 interrupt direction. 3 4 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO48OUTCFG GPIO48 output configuration. 1 3 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 GPIO49INCFG GPIO49 input enable. 4 5 read-write READ Read the GPIO pin data 0 RDZERO Readback will always be zero 1 GPIO49INTD GPIO49 interrupt direction. 7 8 read-write INTLH Interrupt on low to high GPIO transition 0 INTHL Interrupt on high to low GPIO transition 1 GPIO49OUTCFG GPIO49 output configuration. 5 7 read-write DIS Output disabled 0 PUSHPULL Output is push-pull 1 OD Output is open drain 2 TS Output is tri-state 3 ENA GPIO Enable Register A 0xA0 32 read-write n 0x0 0x0 ENA GPIO31-0 output enables 0 32 read-write ENB GPIO Enable Register B 0xA4 32 read-write n 0x0 0x0 ENB GPIO49-32 output enables 0 18 read-write ENCA GPIO Enable Register A Clear 0xB4 32 read-write n 0x0 0x0 ENCA Clear the GPIO31-0 output enables 0 32 read-write ENCB GPIO Enable Register B Clear 0xB8 32 read-write n 0x0 0x0 ENCB Clear the GPIO49-32 output enables 0 18 read-write ENSA GPIO Enable Register A Set 0xA8 32 read-write n 0x0 0x0 ENSA Set the GPIO31-0 output enables 0 32 read-write ENSB GPIO Enable Register B Set 0xAC 32 read-write n 0x0 0x0 ENSB Set the GPIO49-32 output enables 0 18 read-write GPIOOBS GPIO Observation Mode Sample register 0xDC 32 read-write n 0x0 0x0 OBS_DATA Sample of the data output on the GPIO observation port. May have async sampling issues, as the data is not synronized to the read operation. Intended for debug purposes only 0 16 read-write INT0CLR GPIO Interrupt Registers 31-0: Clear 0x208 32 read-write n 0x0 0x0 GPIO0 GPIO0 interrupt. 0 1 read-write GPIO1 GPIO1 interrupt. 1 2 read-write GPIO10 GPIO10 interrupt. 10 11 read-write GPIO11 GPIO11 interrupt. 11 12 read-write GPIO12 GPIO12 interrupt. 12 13 read-write GPIO13 GPIO13 interrupt. 13 14 read-write GPIO14 GPIO14 interrupt. 14 15 read-write GPIO15 GPIO15 interrupt. 15 16 read-write GPIO16 GPIO16 interrupt. 16 17 read-write GPIO17 GPIO17 interrupt. 17 18 read-write GPIO18 GPIO18interrupt. 18 19 read-write GPIO19 GPIO19 interrupt. 19 20 read-write GPIO2 GPIO2 interrupt. 2 3 read-write GPIO20 GPIO20 interrupt. 20 21 read-write GPIO21 GPIO21 interrupt. 21 22 read-write GPIO22 GPIO22 interrupt. 22 23 read-write GPIO23 GPIO23 interrupt. 23 24 read-write GPIO24 GPIO24 interrupt. 24 25 read-write GPIO25 GPIO25 interrupt. 25 26 read-write GPIO26 GPIO26 interrupt. 26 27 read-write GPIO27 GPIO27 interrupt. 27 28 read-write GPIO28 GPIO28 interrupt. 28 29 read-write GPIO29 GPIO29 interrupt. 29 30 read-write GPIO3 GPIO3 interrupt. 3 4 read-write GPIO30 GPIO30 interrupt. 30 31 read-write GPIO31 GPIO31 interrupt. 31 32 read-write GPIO4 GPIO4 interrupt. 4 5 read-write GPIO5 GPIO5 interrupt. 5 6 read-write GPIO6 GPIO6 interrupt. 6 7 read-write GPIO7 GPIO7 interrupt. 7 8 read-write GPIO8 GPIO8 interrupt. 8 9 read-write GPIO9 GPIO9 interrupt. 9 10 read-write INT0EN GPIO Interrupt Registers 31-0: Enable 0x200 32 read-write n 0x0 0x0 GPIO0 GPIO0 interrupt. 0 1 read-write GPIO1 GPIO1 interrupt. 1 2 read-write GPIO10 GPIO10 interrupt. 10 11 read-write GPIO11 GPIO11 interrupt. 11 12 read-write GPIO12 GPIO12 interrupt. 12 13 read-write GPIO13 GPIO13 interrupt. 13 14 read-write GPIO14 GPIO14 interrupt. 14 15 read-write GPIO15 GPIO15 interrupt. 15 16 read-write GPIO16 GPIO16 interrupt. 16 17 read-write GPIO17 GPIO17 interrupt. 17 18 read-write GPIO18 GPIO18interrupt. 18 19 read-write GPIO19 GPIO19 interrupt. 19 20 read-write GPIO2 GPIO2 interrupt. 2 3 read-write GPIO20 GPIO20 interrupt. 20 21 read-write GPIO21 GPIO21 interrupt. 21 22 read-write GPIO22 GPIO22 interrupt. 22 23 read-write GPIO23 GPIO23 interrupt. 23 24 read-write GPIO24 GPIO24 interrupt. 24 25 read-write GPIO25 GPIO25 interrupt. 25 26 read-write GPIO26 GPIO26 interrupt. 26 27 read-write GPIO27 GPIO27 interrupt. 27 28 read-write GPIO28 GPIO28 interrupt. 28 29 read-write GPIO29 GPIO29 interrupt. 29 30 read-write GPIO3 GPIO3 interrupt. 3 4 read-write GPIO30 GPIO30 interrupt. 30 31 read-write GPIO31 GPIO31 interrupt. 31 32 read-write GPIO4 GPIO4 interrupt. 4 5 read-write GPIO5 GPIO5 interrupt. 5 6 read-write GPIO6 GPIO6 interrupt. 6 7 read-write GPIO7 GPIO7 interrupt. 7 8 read-write GPIO8 GPIO8 interrupt. 8 9 read-write GPIO9 GPIO9 interrupt. 9 10 read-write INT0SET GPIO Interrupt Registers 31-0: Set 0x20C 32 read-write n 0x0 0x0 GPIO0 GPIO0 interrupt. 0 1 read-write GPIO1 GPIO1 interrupt. 1 2 read-write GPIO10 GPIO10 interrupt. 10 11 read-write GPIO11 GPIO11 interrupt. 11 12 read-write GPIO12 GPIO12 interrupt. 12 13 read-write GPIO13 GPIO13 interrupt. 13 14 read-write GPIO14 GPIO14 interrupt. 14 15 read-write GPIO15 GPIO15 interrupt. 15 16 read-write GPIO16 GPIO16 interrupt. 16 17 read-write GPIO17 GPIO17 interrupt. 17 18 read-write GPIO18 GPIO18interrupt. 18 19 read-write GPIO19 GPIO19 interrupt. 19 20 read-write GPIO2 GPIO2 interrupt. 2 3 read-write GPIO20 GPIO20 interrupt. 20 21 read-write GPIO21 GPIO21 interrupt. 21 22 read-write GPIO22 GPIO22 interrupt. 22 23 read-write GPIO23 GPIO23 interrupt. 23 24 read-write GPIO24 GPIO24 interrupt. 24 25 read-write GPIO25 GPIO25 interrupt. 25 26 read-write GPIO26 GPIO26 interrupt. 26 27 read-write GPIO27 GPIO27 interrupt. 27 28 read-write GPIO28 GPIO28 interrupt. 28 29 read-write GPIO29 GPIO29 interrupt. 29 30 read-write GPIO3 GPIO3 interrupt. 3 4 read-write GPIO30 GPIO30 interrupt. 30 31 read-write GPIO31 GPIO31 interrupt. 31 32 read-write GPIO4 GPIO4 interrupt. 4 5 read-write GPIO5 GPIO5 interrupt. 5 6 read-write GPIO6 GPIO6 interrupt. 6 7 read-write GPIO7 GPIO7 interrupt. 7 8 read-write GPIO8 GPIO8 interrupt. 8 9 read-write GPIO9 GPIO9 interrupt. 9 10 read-write INT0STAT GPIO Interrupt Registers 31-0: Status 0x204 32 read-write n 0x0 0x0 GPIO0 GPIO0 interrupt. 0 1 read-write GPIO1 GPIO1 interrupt. 1 2 read-write GPIO10 GPIO10 interrupt. 10 11 read-write GPIO11 GPIO11 interrupt. 11 12 read-write GPIO12 GPIO12 interrupt. 12 13 read-write GPIO13 GPIO13 interrupt. 13 14 read-write GPIO14 GPIO14 interrupt. 14 15 read-write GPIO15 GPIO15 interrupt. 15 16 read-write GPIO16 GPIO16 interrupt. 16 17 read-write GPIO17 GPIO17 interrupt. 17 18 read-write GPIO18 GPIO18interrupt. 18 19 read-write GPIO19 GPIO19 interrupt. 19 20 read-write GPIO2 GPIO2 interrupt. 2 3 read-write GPIO20 GPIO20 interrupt. 20 21 read-write GPIO21 GPIO21 interrupt. 21 22 read-write GPIO22 GPIO22 interrupt. 22 23 read-write GPIO23 GPIO23 interrupt. 23 24 read-write GPIO24 GPIO24 interrupt. 24 25 read-write GPIO25 GPIO25 interrupt. 25 26 read-write GPIO26 GPIO26 interrupt. 26 27 read-write GPIO27 GPIO27 interrupt. 27 28 read-write GPIO28 GPIO28 interrupt. 28 29 read-write GPIO29 GPIO29 interrupt. 29 30 read-write GPIO3 GPIO3 interrupt. 3 4 read-write GPIO30 GPIO30 interrupt. 30 31 read-write GPIO31 GPIO31 interrupt. 31 32 read-write GPIO4 GPIO4 interrupt. 4 5 read-write GPIO5 GPIO5 interrupt. 5 6 read-write GPIO6 GPIO6 interrupt. 6 7 read-write GPIO7 GPIO7 interrupt. 7 8 read-write GPIO8 GPIO8 interrupt. 8 9 read-write GPIO9 GPIO9 interrupt. 9 10 read-write INT1CLR GPIO Interrupt Registers 49-32: Clear 0x218 32 read-write n 0x0 0x0 GPIO32 GPIO32 interrupt. 0 1 read-write GPIO33 GPIO33 interrupt. 1 2 read-write GPIO34 GPIO34 interrupt. 2 3 read-write GPIO35 GPIO35 interrupt. 3 4 read-write GPIO36 GPIO36 interrupt. 4 5 read-write GPIO37 GPIO37 interrupt. 5 6 read-write GPIO38 GPIO38 interrupt. 6 7 read-write GPIO39 GPIO39 interrupt. 7 8 read-write GPIO40 GPIO40 interrupt. 8 9 read-write GPIO41 GPIO41 interrupt. 9 10 read-write GPIO42 GPIO42 interrupt. 10 11 read-write GPIO43 GPIO43 interrupt. 11 12 read-write GPIO44 GPIO44 interrupt. 12 13 read-write GPIO45 GPIO45 interrupt. 13 14 read-write GPIO46 GPIO46 interrupt. 14 15 read-write GPIO47 GPIO47 interrupt. 15 16 read-write GPIO48 GPIO48 interrupt. 16 17 read-write GPIO49 GPIO49 interrupt. 17 18 read-write INT1EN GPIO Interrupt Registers 49-32: Enable 0x210 32 read-write n 0x0 0x0 GPIO32 GPIO32 interrupt. 0 1 read-write GPIO33 GPIO33 interrupt. 1 2 read-write GPIO34 GPIO34 interrupt. 2 3 read-write GPIO35 GPIO35 interrupt. 3 4 read-write GPIO36 GPIO36 interrupt. 4 5 read-write GPIO37 GPIO37 interrupt. 5 6 read-write GPIO38 GPIO38 interrupt. 6 7 read-write GPIO39 GPIO39 interrupt. 7 8 read-write GPIO40 GPIO40 interrupt. 8 9 read-write GPIO41 GPIO41 interrupt. 9 10 read-write GPIO42 GPIO42 interrupt. 10 11 read-write GPIO43 GPIO43 interrupt. 11 12 read-write GPIO44 GPIO44 interrupt. 12 13 read-write GPIO45 GPIO45 interrupt. 13 14 read-write GPIO46 GPIO46 interrupt. 14 15 read-write GPIO47 GPIO47 interrupt. 15 16 read-write GPIO48 GPIO48 interrupt. 16 17 read-write GPIO49 GPIO49 interrupt. 17 18 read-write INT1SET GPIO Interrupt Registers 49-32: Set 0x21C 32 read-write n 0x0 0x0 GPIO32 GPIO32 interrupt. 0 1 read-write GPIO33 GPIO33 interrupt. 1 2 read-write GPIO34 GPIO34 interrupt. 2 3 read-write GPIO35 GPIO35 interrupt. 3 4 read-write GPIO36 GPIO36 interrupt. 4 5 read-write GPIO37 GPIO37 interrupt. 5 6 read-write GPIO38 GPIO38 interrupt. 6 7 read-write GPIO39 GPIO39 interrupt. 7 8 read-write GPIO40 GPIO40 interrupt. 8 9 read-write GPIO41 GPIO41 interrupt. 9 10 read-write GPIO42 GPIO42 interrupt. 10 11 read-write GPIO43 GPIO43 interrupt. 11 12 read-write GPIO44 GPIO44 interrupt. 12 13 read-write GPIO45 GPIO45 interrupt. 13 14 read-write GPIO46 GPIO46 interrupt. 14 15 read-write GPIO47 GPIO47 interrupt. 15 16 read-write GPIO48 GPIO48 interrupt. 16 17 read-write GPIO49 GPIO49 interrupt. 17 18 read-write INT1STAT GPIO Interrupt Registers 49-32: Status 0x214 32 read-write n 0x0 0x0 GPIO32 GPIO32 interrupt. 0 1 read-write GPIO33 GPIO33 interrupt. 1 2 read-write GPIO34 GPIO34 interrupt. 2 3 read-write GPIO35 GPIO35 interrupt. 3 4 read-write GPIO36 GPIO36 interrupt. 4 5 read-write GPIO37 GPIO37 interrupt. 5 6 read-write GPIO38 GPIO38 interrupt. 6 7 read-write GPIO39 GPIO39 interrupt. 7 8 read-write GPIO40 GPIO40 interrupt. 8 9 read-write GPIO41 GPIO41 interrupt. 9 10 read-write GPIO42 GPIO42 interrupt. 10 11 read-write GPIO43 GPIO43 interrupt. 11 12 read-write GPIO44 GPIO44 interrupt. 12 13 read-write GPIO45 GPIO45 interrupt. 13 14 read-write GPIO46 GPIO46 interrupt. 14 15 read-write GPIO47 GPIO47 interrupt. 15 16 read-write GPIO48 GPIO48 interrupt. 16 17 read-write GPIO49 GPIO49 interrupt. 17 18 read-write IOM0IRQ IOM0 Flow Control IRQ Select 0xC0 32 read-write n 0x0 0x0 IOM0IRQ IOMSTR0 IRQ pad select. 0 6 read-write IOM1IRQ IOM1 Flow Control IRQ Select 0xC4 32 read-write n 0x0 0x0 IOM1IRQ IOMSTR1 IRQ pad select. 0 6 read-write IOM2IRQ IOM2 Flow Control IRQ Select 0xC8 32 read-write n 0x0 0x0 IOM2IRQ IOMSTR2 IRQ pad select. 0 6 read-write IOM3IRQ IOM3 Flow Control IRQ Select 0xCC 32 read-write n 0x0 0x0 IOM3IRQ IOMSTR3 IRQ pad select. 0 6 read-write IOM4IRQ IOM4 Flow Control IRQ Select 0xD0 32 read-write n 0x0 0x0 IOM4IRQ IOMSTR4 IRQ pad select. 0 6 read-write IOM5IRQ IOM5 Flow Control IRQ Select 0xD4 32 read-write n 0x0 0x0 IOM5IRQ IOMSTR5 IRQ pad select. 0 6 read-write LOOPBACK IOM to IOS Loopback Control 0xD8 32 read-write n 0x0 0x0 LOOPBACK IOM to IOS loopback control. 0 3 read-write LOOP0 Loop IOM0 to IOS 0 LOOP1 Loop IOM1 to IOS 1 LOOP2 Loop IOM2 to IOS 2 LOOP3 Loop IOM3 to IOS 3 LOOP4 Loop IOM4 to IOS 4 LOOP5 Loop IOM5 to IOS 5 LOOPNONE No loopback connections 6 PADKEY Key Register for all pad configuration registers 0x60 32 read-write n 0x0 0x0 PADKEY Key register value. 0 32 read-write Key Key 115 PADREGA Pad Configuration Register A 0x0 32 read-write n 0x0 0x0 PAD0FNCSEL Pad 0 function select 3 6 read-write SLSCL Configure as the IOSLAVE I2C SCL signal 0 SLSCK Configure as the IOSLAVE SPI SCK signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO0 Configure as GPIO0 3 MxSCKLB Configure as the IOSLAVE SPI SCK loopback signal from IOMSTRx 4 M2SCK Configure as the IOMSTR2 SPI SCK output 5 MxSCLLB Configure as the IOSLAVE I2C SCL loopback signal from IOMSTRx 6 M2SCL Configure as the IOMSTR2 I2C SCL clock I/O signal 7 PAD0INPEN Pad 0 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD0PULL Pad 0 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD0RSEL Pad 0 pullup resistor selection. 6 8 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD0STRNG Pad 0 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD1FNCSEL Pad 1 function select 11 14 read-write SLSDA Configure as the IOSLAVE I2C SDA signal 0 SLMISO Configure as the IOSLAVE SPI MISO signal 1 UART0TX Configure as the UART0 TX output signal 2 GPIO1 Configure as GPIO1 3 MxMISOLB Configure as the IOSLAVE SPI MISO loopback signal from IOMSTRx 4 M2MISO Configure as the IOMSTR2 SPI MISO input signal 5 MxSDALB Configure as the IOSLAVE I2C SDA loopback signal from IOMSTRx 6 M2SDA Configure as the IOMSTR2 I2C Serial data I/O signal 7 PAD1INPEN Pad 1 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD1PULL Pad 1 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD1RSEL Pad 1 pullup resistor selection. 14 16 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD1STRNG Pad 1 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD2FNCSEL Pad 2 function select 19 22 read-write SLWIR3 Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal 0 SLMOSI Configure as the IOSLAVE SPI MOSI signal 1 UART0RX Configure as the UART0 RX input 2 GPIO2 Configure as GPIO2 3 MxMOSILB Configure as the IOSLAVE SPI MOSI loopback signal from IOMSTRx 4 M2MOSI Configure as the IOMSTR2 SPI MOSI output signal 5 MxWIR3LB Configure as the IOSLAVE SPI 3-wire MOSI/MISO loopback signal from IOMSTRx 6 M2WIR3 Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal 7 PAD2INPEN Pad 2 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD2PULL Pad 2 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD2STRNG Pad 2 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD3FNCSEL Pad 3 function select 27 30 read-write UA0RTS Configure as the UART0 RTS output 0 SLnCE Configure as the IOSLAVE SPI nCE signal 1 M1nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR1 2 GPIO3 Configure as GPIO3 3 MxnCELB Configure as the IOSLAVE SPI nCE loopback signal from IOMSTRx 4 M2nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR2 5 TRIG1 Configure as the ADC Trigger 1 signal 6 I2S_WCLK Configure as the I2S Word Clock input 7 PAD3INPEN Pad 3 input enable. 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD3PULL Pad 3 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD3STRNG Pad 3 drive strength. 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGB Pad Configuration Register B 0x4 32 read-write n 0x0 0x0 PAD4FNCSEL Pad 4 function select 3 6 read-write UA0CTS Configure as the UART0 CTS input signal 0 SLINT Configure as the IOSLAVE interrupt out signal 1 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 2 GPIO4 Configure as GPIO4 3 SLINTGP Configure as the IOSLAVE interrupt loopback signal 4 M2nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR2 5 CLKOUT Configure as the CLKOUT signal 6 32khz_XT Configure as the 32kHz crystal output signal 7 PAD4INPEN Pad 4 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD4PULL Pad 4 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD4PWRDN Pad 4 VSS power switch enable 7 8 read-write DIS Power switch disabled 0 EN Power switch enabled (switch to GND) 1 PAD4STRNG Pad 4 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD5FNCSEL Pad 5 function select 11 14 read-write M0SCL Configure as the IOMSTR0 I2C SCL signal 0 M0SCK Configure as the IOMSTR0 SPI SCK signal 1 UA0RTS Configure as the UART0 RTS signal output 2 GPIO5 Configure as GPIO5 3 M0SCKLB Configure as the IOMSTR0 SPI SCK loopback signal from IOSLAVE 4 EXTHFA Configure as the External HFA input clock 5 M0SCLLB Configure as the IOMSTR0 I2C SCL loopback signal from IOSLAVE 6 M1nCE2 Configure as the SPI Channel 2 nCE signal from IOMSTR1 7 PAD5INPEN Pad 5 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD5PULL Pad 5 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD5RSEL Pad 5 pullup resistor selection. 14 16 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD5STRNG Pad 5 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD6FNCSEL Pad 6 function select 19 22 read-write M0SDA Configure as the IOMSTR0 I2C SDA signal 0 M0MISO Configure as the IOMSTR0 SPI MISO signal 1 UA0CTS Configure as the UART0 CTS input signal 2 GPIO6 Configure as GPIO6 3 SLMISOLB Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE 4 M1nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR1 5 SLSDALB Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE 6 I2S_DAT Configure as the I2S Data output signal 7 PAD6INPEN Pad 6 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD6PULL Pad 6 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD6RSEL Pad 6 pullup resistor selection. 22 24 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD6STRNG Pad 6 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD7FNCSEL Pad 7 function select 27 30 read-write M0WIR3 Configure as the IOMSTR0 SPI 3-wire MOSI/MISO signal 0 M0MOSI Configure as the IOMSTR0 SPI MOSI signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO7 Configure as GPIO7 3 TRIG0 Configure as the ADC Trigger 0 signal 4 UART0TX Configure as the UART0 TX output signal 5 SLWIR3LB Configure as the IOMSTR0 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 6 M1nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR1 7 PAD7INPEN Pad 7 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD7PULL Pad 7 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD7STRNG Pad 7 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGC Pad Configuration Register C 0x8 32 read-write n 0x0 0x0 PAD10FNCSEL Pad 10 function select 19 22 read-write M1WIR3 Configure as the IOMSTR1 SPI 3-wire MOSI/MISO signal 0 M1MOSI Configure as the IOMSTR1 SPI MOSI signal 1 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 2 GPIO10 Configure as GPIO10 3 M2nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR2 4 UA1RTS Configure as the UART1 RTS output signal 5 M4nCE4 Configure as the SPI channel 4 nCE signal from the IOMSTR4 6 SLWIR3LB Configure as the IOMSTR1 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD10INPEN Pad 10 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD10PULL Pad 10 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD10STRNG Pad 10 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD11FNCSEL Pad 11 function select 27 30 read-write ADCSE2 Configure as the analog input for ADC single ended input 2 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 CLKOUT Configure as the CLKOUT signal 2 GPIO11 Configure as GPIO11 3 M2nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR2 4 UA1CTS Configure as the UART1 CTS input signal 5 UART0RX Configure as the UART0 RX input signal 6 PDM_DATA Configure as the PDM Data input signal 7 PAD11INPEN Pad 11 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD11PULL Pad 11 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD11STRNG Pad 11 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD8FNCSEL Pad 8 function select 3 6 read-write M1SCL Configure as the IOMSTR1 I2C SCL signal 0 M1SCK Configure as the IOMSTR1 SPI SCK signal 1 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 2 GPIO8 Configure as GPIO8 3 M2nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR2 4 M1SCKLB Configure as the IOMSTR1 SPI SCK loopback signal from IOSLAVE 5 UART1TX Configure as the UART1 TX output signal 6 M1SCLLB Configure as the IOMSTR1 I2C SCL loopback signal from IOSLAVE 7 PAD8INPEN Pad 8 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD8PULL Pad 8 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD8RSEL Pad 8 pullup resistor selection. 6 8 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD8STRNG Pad 8 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD9FNCSEL Pad 9 function select 11 14 read-write M1SDA Configure as the IOMSTR1 I2C SDA signal 0 M1MISO Configure as the IOMSTR1 SPI MISO signal 1 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 2 GPIO9 Configure as GPIO9 3 M4nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR4 4 SLMISOLB Configure as the IOMSTR1 SPI MISO loopback signal from IOSLAVE 5 UART1RX Configure as UART1 RX input signal 6 SLSDALB Configure as the IOMSTR1 I2C SDA loopback signal from IOSLAVE 7 PAD9INPEN Pad 9 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD9PULL Pad 9 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD9RSEL Pad 9 pullup resistor selection 14 16 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD9STRNG Pad 9 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGD Pad Configuration Register D 0xC 32 read-write n 0x0 0x0 PAD12FNCSEL Pad 12 function select 3 6 read-write ADCD0NSE9 Configure as the ADC Differential pair 0 N, or Single Ended input 9 analog input signal. Determination of the D0N vs SE9 usage is done when the particular channel is selected within the ADC module 0 M1nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR1 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO12 Configure as GPIO12 3 CLKOUT Configure as CLKOUT signal 4 PDM_CLK Configure as the PDM CLK output signal 5 UA0CTS Configure as the UART0 CTS input signal 6 UART1TX Configure as the UART1 TX output signal 7 PAD12INPEN Pad 12 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD12PULL Pad 12 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD12STRNG Pad 12 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD13FNCSEL Pad 13 function select 11 14 read-write ADCD0PSE8 Configure as the ADC Differential pair 0 P, or Single Ended input 8 analog input signal. Determination of the D0P vs SE8 usage is done when the particular channel is selected within the ADC module 0 M1nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR1 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO13 Configure as GPIO13 3 M2nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR2 4 EXTHFB Configure as the external HFRC oscillator input 5 UA0RTS Configure as the UART0 RTS signal output 6 UART1RX Configure as the UART1 RX input signal 7 PAD13INPEN Pad 13 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD13PULL Pad 13 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD13STRNG Pad 13 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD14FNCSEL Pad 14 function select 19 22 read-write ADCD1P Configure as the analog ADC differential pair 1 P input signal 0 M1nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR1 1 UART1TX Configure as the UART1 TX output signal 2 GPIO14 Configure as GPIO14 3 M2nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR2 4 EXTHFS Configure as the External HFRC oscillator input select 5 SWDCK Configure as the alternate input for the SWDCK input signal 6 32khz_XT Configure as the 32kHz crystal output signal 7 PAD14INPEN Pad 14 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD14PULL Pad 14 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD14STRNG Pad 14 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD15FNCSEL Pad 15 function select 27 30 read-write ADCD1N Configure as the analog ADC differential pair 1 N input signal 0 M1nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR1 1 UART1RX Configure as the UART1 RX signal 2 GPIO15 Configure as GPIO15 3 M2nCE2 Configure as the SPI Channel 2 nCE signal from IOMSTR2 4 EXTXT Configure as the external XTAL oscillator input 5 SWDIO Configure as an alternate port for the SWDIO I/O signal 6 SWO Configure as an SWO (Serial Wire Trace output) 7 PAD15INPEN Pad 15 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD15PULL Pad 15 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD15STRNG Pad 15 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGE Pad Configuration Register E 0x10 32 read-write n 0x0 0x0 PAD16FNCSEL Pad 16 function select 3 6 read-write ADCSE0 Configure as the analog ADC single ended port 0 input signal 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TRIG0 Configure as the ADC Trigger 0 signal 2 GPIO16 Configure as GPIO16 3 M2nCE3 Configure as SPI channel 3 nCE for IOMSTR2 4 CMPIN0 Configure as comparator input 0 signal 5 UART0TX Configure as UART0 TX output signal 6 UA1RTS Configure as UART1 RTS output signal 7 PAD16INPEN Pad 16 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD16PULL Pad 16 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD16STRNG Pad 16 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD17FNCSEL Pad 17 function select 11 14 read-write CMPRF1 Configure as the analog comparator reference signal 1 input signal 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 TRIG1 Configure as the ADC Trigger 1 signal 2 GPIO17 Configure as GPIO17 3 M4nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR4 4 EXTLF Configure as external LFRC oscillator input 5 UART0RX Configure as UART0 RX input signal 6 UA1CTS Configure as UART1 CTS input signal 7 PAD17INPEN Pad 17 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD17PULL Pad 17 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD17STRNG Pad 17 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD18FNCSEL Pad 18 function select 19 22 read-write CMPIN1 Configure as the analog comparator input 1 signal 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO18 Configure as GPIO18 3 M4nCE1 Configure as the SPI nCE channel 1 from IOMSTR4 4 ANATEST2 Configure as ANATEST2 I/O signal 5 UART1TX Configure as UART1 TX output signal 6 32khz_XT Configure as the 32kHz output clock from the crystal 7 PAD18INPEN Pad 18 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD18PULL Pad 18 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD18STRNG Pad 18 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD19FNCSEL Pad 19 function select 27 30 read-write CMPRF0 Configure as the analog comparator reference 0 signal 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO19 Configure as GPIO19 3 TCTA1 Configure as the input/output signal from CTIMER A1 4 ANATEST1 Configure as the ANATEST1 I/O signal 5 UART1RX Configure as the UART1 RX input signal 6 I2S_BCLK Configure as the I2S Byte clock input signal 7 PAD19INPEN Pad 19 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD19PULL Pad 19 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD19STRNG Pad 19 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGF Pad Configuration Register F 0x14 32 read-write n 0x0 0x0 PAD20FNCSEL Pad 20 function select 3 6 read-write SWDCK Configure as the serial wire debug clock signal 0 M1nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR1 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO20 Configure as GPIO20 3 UART0TX Configure as UART0 TX output signal 4 UART1TX Configure as UART1 TX output signal 5 UNDEF6 Undefined/should not be used 6 UNDEF7 Undefined/should not be used 7 PAD20INPEN Pad 20 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD20PULL Pad 20 pulldown enable 0 1 read-write DIS Pulldown disabled 0 EN Pulldown enabled 1 PAD20STRNG Pad 20 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD21FNCSEL Pad 21 function select 11 14 read-write SWDIO Configure as the serial wire debug data signal 0 M1nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR1 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO21 Configure as GPIO21 3 UART0RX Configure as UART0 RX input signal 4 UART1RX Configure as UART1 RX input signal 5 UNDEF6 Undefined/should not be used 6 UNDEF7 Undefined/should not be used 7 PAD21INPEN Pad 21 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD21PULL Pad 21 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD21STRNG Pad 21 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD22FNCSEL Pad 22 function select 19 22 read-write UART0TX Configure as the UART0 TX signal 0 M1nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR1 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO22 Configure as GPIO22 3 PDM_CLK Configure as the PDM CLK output 4 UNDEF5 Undefined/should not be used 5 TCTB1 Configure as the input/output signal from CTIMER B1 6 SWO Configure as the serial trace data output signal 7 PAD22INPEN Pad 22 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD22PULL Pad 22 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD22PWRUP Pad 22 upper power switch enable 23 24 read-write DIS Power switch disabled 0 EN Power switch enabled 1 PAD22STRNG Pad 22 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD23FNCSEL Pad 23 function select 27 30 read-write UART0RX Configure as the UART0 RX signal 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO23 Configure as GPIO23 3 PDM_DATA Configure as PDM Data input to the PDM module 4 CMPOUT Configure as voltage comparitor output 5 TCTB1 Configure as the input/output signal from CTIMER B1 6 UNDEF7 Undefined/should not be used 7 PAD23INPEN Pad 23 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD23PULL Pad 23 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD23STRNG Pad 23 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGG Pad Configuration Register G 0x18 32 read-write n 0x0 0x0 PAD24FNCSEL Pad 24 function select 3 6 read-write M2nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR2 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 CLKOUT Configure as the CLKOUT signal 2 GPIO24 Configure as GPIO24 3 M5nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR5 4 TCTA1 Configure as the input/output signal from CTIMER A1 5 I2S_BCLK Configure as the I2S Byte clock input signal 6 SWO Configure as the serial trace data output signal 7 PAD24INPEN Pad 24 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD24PULL Pad 24 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD24STRNG Pad 24 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD25FNCSEL Pad 25 function select 11 14 read-write EXTXT Configure as the external XTAL oscillator input 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO25 Configure as GPIO25 3 M2SDA Configure as the IOMSTR2 I2C Serial data I/O signal 4 M2MISO Configure as the IOMSTR2 SPI MISO input signal 5 SLMISOLB Configure as the IOMSTR0 SPI MISO loopback signal from IOSLAVE 6 SLSDALB Configure as the IOMSTR0 I2C SDA loopback signal from IOSLAVE 7 PAD25INPEN Pad 25 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD25PULL Pad 25 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD25RSEL Pad 25 pullup resistor selection. 14 16 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD25STRNG Pad 25 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD26FNCSEL Pad 26 function select 19 22 read-write EXTLF Configure as the external LFRC oscillator input 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO26 Configure as GPIO26 3 M2nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR2 4 TCTA1 Configure as the input/output signal from CTIMER A1 5 M5nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR5 6 M3nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR3 7 PAD26INPEN Pad 26 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD26PULL Pad 26 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD26STRNG Pad 26 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD27FNCSEL Pad 27 function select 27 30 read-write EXTHF Configure as the external HFRC oscillator input 0 M1nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR1 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO27 Configure as GPIO27 3 M2SCL Configure as I2C clock I/O signal from IOMSTR2 4 M2SCK Configure as SPI clock output signal from IOMSTR2 5 M2SCKLB Configure as IOMSTR2 SPI SCK loopback signal from IOSLAVE 6 M2SCLLB Configure as IOMSTR2 I2C SCL loopback signal from IOSLAVE 7 PAD27INPEN Pad 27 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD27PULL Pad 27 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD27RSEL Pad 27 pullup resistor selection. 30 32 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD27STRNG Pad 27 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGH Pad Configuration Register H 0x1C 32 read-write n 0x0 0x0 PAD28FNCSEL Pad 28 function select 3 6 read-write I2S_WCLK Configure as the I2S Word Clock input 0 M1nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR1 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO28 Configure as GPIO28 3 M2WIR3 Configure as the IOMSTR2 SPI 3-wire MOSI/MISO signal 4 M2MOSI Configure as the IOMSTR2 SPI MOSI output signal 5 M5nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR5 6 SLWIR3LB Configure as the IOMSTR2 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD28INPEN Pad 28 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD28PULL Pad 28 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD28STRNG Pad 28 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD29FNCSEL Pad 29 function select 11 14 read-write ADCSE1 Configure as the analog input for ADC single ended input 1 0 M1nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR1 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO29 Configure as GPIO29 3 UA0CTS Configure as the UART0 CTS signal 4 UA1CTS Configure as the UART1 CTS signal 5 M4nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR4 6 PDM_DATA Configure as PDM DATA input 7 PAD29INPEN Pad 29 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD29PULL Pad 29 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD29STRNG Pad 29 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD30FNCSEL Pad 30 function select 19 22 read-write UNDEF0 Undefined/should not be used 0 M1nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR1 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO30 Configure as GPIO30 3 UART0TX Configure as UART0 TX output signal 4 UA1RTS Configure as UART1 RTS output signal 5 UNDEF6 Undefined/should not be used 6 I2S_DAT Configure as the I2S Data output signal 7 PAD30INPEN Pad 30 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD30PULL Pad 30 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD30STRNG Pad 30 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD31FNCSEL Pad 31 function select 27 30 read-write ADCSE3 Configure as the analog input for ADC single ended input 3 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO31 Configure as GPIO31 3 UART0RX Configure as the UART0 RX input signal 4 TCTB1 Configure as the input/output signal from CTIMER B1 5 UNDEF6 Undefined/should not be used 6 UNDEF7 Undefined/should not be used 7 PAD31INPEN Pad 31 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD31PULL Pad 31 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD31STRNG Pad 31 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGI Pad Configuration Register I 0x20 32 read-write n 0x0 0x0 PAD32FNCSEL Pad 32 function select 3 6 read-write ADCSE4 Configure as the analog input for ADC single ended input 4 0 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO32 Configure as GPIO32 3 UNDEF4 Undefined/should not be used 4 TCTB1 Configure as the input/output signal from CTIMER B1 5 UNDEF6 Undefined/should not be used 6 UNDEF7 Undefined/should not be used 7 PAD32INPEN Pad 32 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD32PULL Pad 32 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD32STRNG Pad 32 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD33FNCSEL Pad 33 function select 11 14 read-write ADCSE5 Configure as the analog ADC single ended port 5 input signal 0 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 1 32khz_XT Configure as the 32kHz crystal output signal 2 GPIO33 Configure as GPIO33 3 UNDEF4 Undefined/should not be used 4 M3nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR3 5 TCTB1 Configure as the input/output signal from CTIMER B1 6 SWO Configure as the serial trace data output signal 7 PAD33INPEN Pad 33 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD33PULL Pad 33 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD33STRNG Pad 33 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD34FNCSEL Pad 34 function select 19 22 read-write ADCSE6 Configure as the analog input for ADC single ended input 6 0 M0nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR0 1 M2nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR2 2 GPIO34 Configure as GPIO34 3 CMPRF2 Configure as the analog comparator reference 2 signal 4 M3nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR3 5 M4nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR4 6 M5nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR5 7 PAD34INPEN Pad 34 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD34PULL Pad 34 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD34STRNG Pad 34 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD35FNCSEL Pad 35 function select 27 30 read-write ADCSE7 Configure as the analog input for ADC single ended input 7 0 M1nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR1 1 UART1TX Configure as the UART1 TX signal 2 GPIO35 Configure as GPIO35 3 M4nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR4 4 TCTA1 Configure as the input/output signal from CTIMER A1 5 UA0RTS Configure as the UART0 RTS output 6 M3nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR3 7 PAD35INPEN Pad 35 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD35PULL Pad 35 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD35STRNG Pad 35 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGJ Pad Configuration Register J 0x24 32 read-write n 0x0 0x0 PAD36FNCSEL Pad 36 function select 3 6 read-write TRIG1 Configure as the ADC Trigger 1 signal 0 M1nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR1 1 UART1RX Configure as the UART1 RX signal 2 GPIO36 Configure as GPIO36 3 32khz_XT Configure as the 32kHz output clock from the crystal 4 M2nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR2 5 UA0CTS Configure as the UART0 CTS signal 6 M3nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR3 7 PAD36INPEN Pad 36 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD36PULL Pad 36 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD36STRNG Pad 36 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD37FNCSEL Pad 37 function select 11 14 read-write TRIG2 Configure as the ADC Trigger 2 signal 0 M1nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR1 1 UA0RTS Configure as the UART0 RTS signal 2 GPIO37 Configure as GPIO37 3 M3nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR3 4 M4nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR4 5 PDM_CLK Configure as the PDM CLK output signal 6 TCTA1 Configure as the input/output signal from CTIMER A1 7 PAD37INPEN Pad 37 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD37PULL Pad 37 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD37STRNG Pad 37 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD38FNCSEL Pad 38 function select 19 22 read-write TRIG3 Configure as the ADC Trigger 3 signal 0 M1nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR1 1 UA0CTS Configure as the UART0 CTS signal 2 GPIO38 Configure as GPIO38 3 M3WIR3 Configure as the IOSLAVE SPI 3-wire MOSI/MISO signal 4 M3MOSI Configure as the IOMSTR3 SPI MOSI output signal 5 M4nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR4 6 SLWIR3LB Configure as the IOMSTR3 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD38INPEN Pad 38 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD38PULL Pad 38 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD38STRNG Pad 38 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD39FNCSEL Pad 39 function select 27 30 read-write UART0TX Configure as the UART0 TX Signal 0 UART1TX Configure as the UART1 TX signal 1 CLKOUT Configure as the CLKOUT signal 2 GPIO39 Configure as GPIO39 3 M4SCL Configure as the IOMSTR4 I2C SCL signal 4 M4SCK Configure as the IOMSTR4 SPI SCK signal 5 M4SCKLB Configure as the IOMSTR4 SPI SCK loopback signal from IOSLAVE 6 M4SCLLB Configure as the IOMSTR4 I2C SCL loopback signal from IOSLAVE 7 PAD39INPEN Pad 39 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD39PULL Pad 39 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD39RSEL Pad 39 pullup resistor selection. 30 32 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD39STRNG Pad 39 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGK Pad Configuration Register K 0x28 32 read-write n 0x0 0x0 PAD40FNCSEL Pad 40 function select 3 6 read-write UART0RX Configure as the UART0 RX input signal 0 UART1RX Configure as the UART1 RX input signal 1 TRIG0 Configure as the ADC Trigger 0 signal 2 GPIO40 Configure as GPIO40 3 M4SDA Configure as the IOMSTR4 I2C serial data I/O signal 4 M4MISO Configure as the IOMSTR4 SPI MISO input signal 5 SLMISOLB Configure as the IOMSTR4 SPI MISO loopback signal from IOSLAVE 6 SLSDALB Configure as the IOMSTR4 I2C SDA loopback signal from IOSLAVE 7 PAD40INPEN Pad 40 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD40PULL Pad 40 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD40RSEL Pad 40 pullup resistor selection. 6 8 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD40STRNG Pad 40 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD41FNCSEL Pad 41 function select 11 14 read-write M2nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR2 0 CLKOUT Configure as the CLKOUT signal 1 SWO Configure as the serial wire debug SWO signal 2 GPIO41 Configure as GPIO41 3 M3nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR3 4 M5nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR5 5 M4nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR4 6 UA0RTS Configure as the UART0 RTS output 7 PAD41INPEN Pad 41 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD41PULL Pad 41 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD41PWRUP Pad 41 upper power switch enable 15 16 read-write DIS Power switch disabled 0 EN Power switch enabled (VDD switch) 1 PAD41STRNG Pad 41 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD42FNCSEL Pad 42 function select 19 22 read-write M2nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR2 0 M0nCE0 Configure as the SPI channel 0 nCE signal from IOMSTR0 1 TCTA0 Configure as the input/output signal from CTIMER A0 2 GPIO42 Configure as GPIO42 3 M3SCL Configure as the IOMSTR3 I2C SCL clock I/O signal 4 M3SCK Configure as the IOMSTR3 SPI SCK output 5 M3SCKLB Configure as the IOMSTR3 SPI clock loopback to the IOSLAVE device 6 M3SCLLB Configure as the IOMSTR3 I2C clock loopback to the IOSLAVE device 7 PAD42INPEN Pad 42 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD42PULL Pad 42 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD42RSEL Pad 42 pullup resistor selection. 22 24 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD42STRNG Pad 42 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD43FNCSEL Pad 43 function select 27 30 read-write M2nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR2 0 M0nCE1 Configure as the SPI channel 1 nCE signal from IOMSTR0 1 TCTB0 Configure as the input/output signal from CTIMER B0 2 GPIO43 Configure as GPIO43 3 M3SDA Configure as the IOMSTR3 I2C SDA signal 4 M3MISO Configure as the IOMSTR3 SPI MISO signal 5 SLMISOLB Configure as the IOMSTR3 SPI MISO loopback signal from IOSLAVE 6 SLSDALB Configure as the IOMSTR3 I2C SDA loopback signal from IOSLAVE 7 PAD43INPEN Pad 43 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD43PULL Pad 43 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD43RSEL Pad 43 pullup resistor selection. 30 32 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD43STRNG Pad 43 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGL Pad Configuration Register L 0x2C 32 read-write n 0x0 0x0 PAD44FNCSEL Pad 44 function select 3 6 read-write UA1RTS Configure as the UART1 RTS output signal 0 M0nCE2 Configure as the SPI channel 2 nCE signal from IOMSTR0 1 TCTA1 Configure as the input/output signal from CTIMER A1 2 GPIO44 Configure as GPIO44 3 M4WIR3 Configure as the IOMSTR4 SPI 3-wire MOSI/MISO signal 4 M4MOSI Configure as the IOMSTR4 SPI MOSI signal 5 M5nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR5 6 SLWIR3LB Configure as the IOMSTR4 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD44INPEN Pad 44 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD44PULL Pad 44 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD44STRNG Pad 44 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD45FNCSEL Pad 45 function select 11 14 read-write UA1CTS Configure as the UART1 CTS input signal 0 M0nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR0 1 TCTB1 Configure as the input/output signal from CTIMER B1 2 GPIO45 Configure as GPIO45 3 M4nCE3 Configure as the SPI channel 3 nCE signal from IOMSTR4 4 M3nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR3 5 M5nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR5 6 TCTA1 Configure as the input/output signal from CTIMER A1 7 PAD45INPEN Pad 45 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD45PULL Pad 45 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD45STRNG Pad 45 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD46FNCSEL Pad 46 function select 19 22 read-write 32khz_XT Configure as the 32kHz output clock from the crystal 0 M0nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR0 1 TCTA2 Configure as the input/output signal from CTIMER A2 2 GPIO46 Configure as GPIO46 3 TCTA1 Configure as the input/output signal from CTIMER A1 4 M5nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR5 5 M4nCE4 Configure as the SPI channel 4 nCE signal from IOMSTR4 6 SWO Configure as the serial wire debug SWO signal 7 PAD46INPEN Pad 46 input enable 17 18 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD46PULL Pad 46 pullup enable 16 17 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD46STRNG Pad 46 drive strength 18 19 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD47FNCSEL Pad 47 function select 27 30 read-write M2nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR2 0 M0nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR0 1 TCTB2 Configure as the input/output signal from CTIMER B2 2 GPIO47 Configure as GPIO47 3 M5WIR3 Configure as the IOMSTR5 SPI 3-wire MOSI/MISO signal 4 M5MOSI Configure as the IOMSTR5 SPI MOSI output signal 5 M4nCE5 Configure as the SPI channel 5 nCE signal from IOMSTR4 6 SLWIR3LB Configure as the IOMSTR5 SPI 3-wire MOSI/MISO loopback signal from IOSLAVE 7 PAD47INPEN Pad 47 input enable 25 26 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD47PULL Pad 47 pullup enable 24 25 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD47STRNG Pad 47 drive strength 26 27 read-write LOW Low drive strength 0 HIGH High drive strength 1 PADREGM Pad Configuration Register M 0x30 32 read-write n 0x0 0x0 PAD48FNCSEL Pad 48 function select 3 6 read-write M2nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR2 0 M0nCE6 Configure as the SPI channel 6 nCE signal from IOMSTR0 1 TCTA3 Configure as the input/output signal from CTIMER A3 2 GPIO48 Configure as GPIO48 3 M5SCL Configure as the IOMSTR5 I2C SCL clock I/O signal 4 M5SCK Configure as the IOMSTR5 SPI SCK output 5 M5SCKLB Configure as the IOMSTR5 SPI clock loopback to the IOSLAVE device 6 M5SCLLB Configure as the IOMSTR5 I2C clock loopback to the IOSLAVE device 7 PAD48INPEN Pad 48 input enable 1 2 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD48PULL Pad 48 pullup enable 0 1 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD48RSEL Pad 48 pullup resistor selection. 6 8 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD48STRNG Pad 48 drive strength 2 3 read-write LOW Low drive strength 0 HIGH High drive strength 1 PAD49FNCSEL Pad 49 function select 11 14 read-write M2nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR2 0 M0nCE7 Configure as the SPI channel 7 nCE signal from IOMSTR0 1 TCTB3 Configure as the input/output signal from CTIMER B3 2 GPIO49 Configure as GPIO49 3 M5SDA Configure as the IOMSTR5 I2C serial data I/O signal 4 M5MISO Configure as the IOMSTR5 SPI MISO input signal 5 SLMISOLB Configure as the IOMSTR5 SPI MISO loopback signal from IOSLAVE 6 SLSDALB Configure as the IOMSTR5 I2C SDA loopback signal from IOSLAVE 7 PAD49INPEN Pad 49 input enable 9 10 read-write DIS Pad input disabled 0 EN Pad input enabled 1 PAD49PULL Pad 49 pullup enable 8 9 read-write DIS Pullup disabled 0 EN Pullup enabled 1 PAD49RSEL Pad 49 pullup resistor selection. 14 16 read-write PULL1_5K Pullup is ~1.5 KOhms 0 PULL6K Pullup is ~6 KOhms 1 PULL12K Pullup is ~12 KOhms 2 PULL24K Pullup is ~24 KOhms 3 PAD49STRNG Pad 49 drive strength 10 11 read-write LOW Low drive strength 0 HIGH High drive strength 1 RDA GPIO Input Register A 0x80 32 read-write n 0x0 0x0 RDA GPIO31-0 read data. 0 32 read-write RDB GPIO Input Register B 0x84 32 read-write n 0x0 0x0 RDB GPIO49-32 read data. 0 18 read-write STMRCAP STIMER Capture Control 0xBC 32 read-write n 0x0 0x0 STPOL0 STIMER Capture 0 Polarity. 6 7 read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STPOL1 STIMER Capture 1 Polarity. 14 15 read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STPOL2 STIMER Capture 2 Polarity. 22 23 read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STPOL3 STIMER Capture 3 Polarity. 30 31 read-write CAPLH Capture on low to high GPIO transition 0 CAPHL Capture on high to low GPIO transition 1 STSEL0 STIMER Capture 0 Select. 0 6 read-write STSEL1 STIMER Capture 1 Select. 8 14 read-write STSEL2 STIMER Capture 2 Select. 16 22 read-write STSEL3 STIMER Capture 3 Select. 24 30 read-write WTA GPIO Output Register A 0x88 32 read-write n 0x0 0x0 WTA GPIO31-0 write data. 0 32 read-write WTB GPIO Output Register B 0x8C 32 read-write n 0x0 0x0 WTB GPIO49-32 write data. 0 18 read-write WTCA GPIO Output Register A Clear 0x98 32 read-write n 0x0 0x0 WTCA Clear the GPIO31-0 write data. 0 32 read-write WTCB GPIO Output Register B Clear 0x9C 32 read-write n 0x0 0x0 WTCB Clear the GPIO49-32 write data. 0 18 read-write WTSA GPIO Output Register A Set 0x90 32 read-write n 0x0 0x0 WTSA Set the GPIO31-0 write data. 0 32 read-write WTSB GPIO Output Register B Set 0x94 32 read-write n 0x0 0x0 WTSB Set the GPIO49-32 write data. 0 18 read-write IOMSTR0 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR0 6 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOMSTR1 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR1 7 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOMSTR2 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR2 8 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOMSTR3 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR3 9 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOMSTR4 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR4 10 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOMSTR5 I2C/SPI Master IOMSTR0 0x0 0x0 0x308 registers n IOMSTR5 11 CFG I/O Master Configuration 0x11C 32 read-write n 0x0 0x0 FCDEL This bit must be left at the default value of 0. 11 12 read-write FULLDUP This bit selects full duplex mode. 3 4 read-write NORMAL 128 byte FIFO in half duplex mode. 0 FULLDUP 64 byte FIFO in full duplex mode. 1 IFCEN This bit enables the IO Master. 31 32 read-write DIS Disable the IO Master. 0 EN Enable the IO Master. 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the I/O Master. 0 SPI Selects SPI interface for the I/O Master. 1 MOSIINV This bit invewrts MOSI when flow control is enabled. 10 11 read-write NORMAL MOSI is set to 0 in read mode and 1 in write mode. 0 INVERT MOSI is set to 1 in read mode and 0 in write mode. 1 RDFC This bit enables read mode flow control. 9 10 read-write DIS Read mode flow control disabled. 0 EN Read mode flow control enabled. 1 RDFCPOL This bit selects the read flow control signal polarity. 14 15 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 SPHA This bit selects SPI phase. 2 3 read-write SAMPLE_LEADING_EDGE Sample on the leading (first) clock edge. 0 SAMPLE_TRAILING_EDGE Sample on the trailing (second) clock edge. 1 SPOL This bit selects SPI polarity. 1 2 read-write CLK_BASE_0 The base value of the clock is 0. 0 CLK_BASE_1 The base value of the clock is 1. 1 STARTRD This bit selects the preread timing. 4 6 read-write PRERD0 0 read delay cycles. 0 PRERD1 1 read delay cycles. 1 PRERD2 2 read delay cycles. 2 PRERD3 3 read delay cycles. 3 WTFC This bit enables write mode flow control. 8 9 read-write DIS Write mode flow control disabled. 0 EN Write mode flow control enabled. 1 WTFCIRQ This bit selects the write mode flow control signal. 12 13 read-write MISO MISO is used as the write mode flow control signal. 0 IRQ IRQ is used as the write mode flow control signal. 1 WTFCPOL This bit selects the write flow control signal polarity. 13 14 read-write HIGH Flow control signal high creates flow control. 0 LOW Flow control signal low creates flow control. 1 CLKCFG I/O Clock Configuration 0x10C 32 read-write n 0x0 0x0 DIV3 Enable divide by 3. 11 12 read-write DIS Select divide by 1. 0 EN Select divide by 3. 1 DIVEN Enable clock division by TOTPER. 12 13 read-write DIS Disable TOTPER division. 0 EN Enable TOTPER division. 1 FSEL Select the input clock frequency. 8 11 read-write MIN_PWR Selects the minimum power clock. This setting should be used whenever the IOMSTR is not active. 0 HFRC Selects the HFRC as the input clock. 1 HFRC_DIV2 Selects the HFRC / 2 as the input clock. 2 HFRC_DIV4 Selects the HFRC / 4 as the input clock. 3 HFRC_DIV8 Selects the HFRC / 8 as the input clock. 4 HFRC_DIV16 Selects the HFRC / 16 as the input clock. 5 HFRC_DIV32 Selects the HFRC / 32 as the input clock. 6 HFRC_DIV64 Selects the HFRC / 64 as the input clock. 7 LOWPER Clock low count minus 1. 16 24 read-write TOTPER Clock total count minus 1. 24 32 read-write CMD Command Register 0x110 32 read-write n 0x0 0x0 CMD This register holds the I/O Command 0 32 read-write CMDRPT Command Repeat Register 0x114 32 read-write n 0x0 0x0 CMDRPT These bits hold the Command repeat count. 0 5 read-write FIFO FIFO Access Port 0x0 32 read-write n 0x0 0x0 FIFO FIFO access port. 0 32 read-write FIFOPTR Current FIFO Pointers 0x100 32 read-write n 0x0 0x0 FIFOREM The number of bytes remaining in the FIFO (i.e. 128-FIFOSIZ if FULLDUP = 0 or 64-FIFOSIZ if FULLDUP = 1)). 16 24 read-write FIFOSIZ The number of bytes currently in the FIFO. 0 8 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFORTHR FIFO read threshold. 0 7 read-write FIFOWTHR FIFO write threshold. 8 15 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 ARB This is the arbitration loss interrupt. This error occurs if another master collides with an IO Master transfer. Generally, the IOM started an operation but found SDA already low. 10 11 read-write CMDCMP This is the Command Complete interrupt. 0 1 read-write FOVFL This is the Write FIFO Overflow interrupt. An attempt was made to write the FIFO while it was full (i.e. while FIFOSIZ > 124). 3 4 read-write FUNDFL This is the Read FIFO Underflow interrupt. An attempt was made to read FIFO when empty (i.e. while FIFOSIZ less than 4). 2 3 read-write IACC This is the illegal FIFO access interrupt. An attempt was made to read the FIFO during a write CMD. Or an attempt was made to write the FIFO on a read CMD. 6 7 read-write ICMD This is the illegal command interrupt. Software attempted to issue a CMD while another CMD was already in progress. Or an attempt was made to issue a non-zero-length write CMD with an empty FIFO. 7 8 read-write NAK This is the I2C NAK interrupt. The expected ACK from the slave was not received by the IOM. 4 5 read-write START This is the START command interrupt. A START from another master was detected. Software must wait for a STOP before proceeding. 8 9 read-write STOP This is the STOP command interrupt. A STOP bit was detected by the IOM. 9 10 read-write THR This is the FIFO Threshold interrupt. 1 2 read-write WTLEN This is the WTLEN interrupt. 5 6 read-write STATUS Status Register 0x118 32 read-write n 0x0 0x0 CMDACT This bit indicates if the I/O Command is active. 1 2 read-write ACTIVE An I/O command is active. 1 ERR This bit indicates if an error interrupt has occurred. 0 1 read-write ERROR An error has been indicated by the IOM. 1 IDLEST This bit indicates if the I/O state machine is IDLE. 2 3 read-write IDLE The I/O state machine is in the idle state. 1 TLNGTH Transfer Length 0x104 32 read-write n 0x0 0x0 TLNGTH Remaining transfer length. 0 12 read-write IOSLAVE I2C/SPI Slave IOSLAVE 0x0 0x0 0x220 registers n IOSLAVE 4 IOSLAVEACC 5 CFG I/O Slave Configuration 0x118 32 read-write n 0x0 0x0 I2CADDR 7-bit or 10-bit I2C device address. 8 20 read-write IFCEN IOSLAVE interface enable. 31 32 read-write DIS Disable the IOSLAVE 0 EN Enable the IOSLAVE 1 IFCSEL This bit selects the I/O interface. 0 1 read-write I2C Selects I2C interface for the IO Slave. 0 SPI Selects SPI interface for the IO Slave. 1 LSB This bit selects the transfer bit ordering. 2 3 read-write MSB_FIRST Data is assumed to be sent and received with MSB first. 0 LSB_FIRST Data is assumed to be sent and received with LSB first. 1 SPOL This bit selects SPI polarity. 1 2 read-write SPI_MODES_0_3 Polarity 0, handles SPI modes 0 and 3. 0 SPI_MODES_1_2 Polarity 1, handles SPI modes 1 and 2. 1 STARTRD This bit holds the cycle to initiate an I/O RAM read. 4 5 read-write LATE Initiate I/O RAM read late in each transferred byte. 0 EARLY Initiate I/O RAM read early in each transferred byte. 1 FIFOCFG FIFO Configuration 0x104 32 read-write n 0x0 0x0 FIFOBASE These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1). 0 5 read-write FIFOMAX These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F. 8 14 read-write ROBASE Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOOBASE*8-1) 24 30 read-write FIFOCTR Overall FIFO Counter 0x110 32 read-write n 0x0 0x0 FIFOCTR Virtual FIFO byte count 0 10 read-write FIFOINC Overall FIFO Counter Increment 0x114 32 read-write n 0x0 0x0 FIFOINC Increment the Overall FIFO Counter by this value on a write 0 10 read-write FIFOPTR Current FIFO Pointer 0x100 32 read-write n 0x0 0x0 FIFOPTR Current FIFO pointer. 0 8 read-write FIFOSIZ The number of bytes currently in the hardware FIFO. 8 16 read-write FIFOTHR FIFO Threshold Configuration 0x108 32 read-write n 0x0 0x0 FIFOTHR FIFO size interrupt threshold. 0 8 read-write FUPD FIFO Update Status 0x10C 32 read-write n 0x0 0x0 FIFOUPD This bit indicates that a FIFO update is underway. 0 1 read-write IOREAD This bitfield indicates an IO read is active. 1 2 read-write GENADD General Address Data 0x124 32 read-write n 0x0 0x0 GADATA The data supplied on the last General Address reference. 0 8 read-write INTCLR IO Slave Interrupts: Clear 0x208 32 read-write n 0x0 0x0 FOVFL FIFO Overflow interrupt. 1 2 read-write FRDERR FIFO Read Error interrupt. 3 4 read-write FSIZE FIFO Size interrupt. 0 1 read-write FUNDFL FIFO Underflow interrupt. 2 3 read-write GENAD I2C General Address interrupt. 4 5 read-write IOINTW I2C Interrupt Write interrupt. 5 6 read-write XCMPRF Transfer complete interrupt, read from FIFO space. 6 7 read-write XCMPRR Transfer complete interrupt, read from register space. 7 8 read-write XCMPWF Transfer complete interrupt, write to FIFO space. 8 9 read-write XCMPWR Transfer complete interrupt, write to register space. 9 10 read-write INTEN IO Slave Interrupts: Enable 0x200 32 read-write n 0x0 0x0 FOVFL FIFO Overflow interrupt. 1 2 read-write FRDERR FIFO Read Error interrupt. 3 4 read-write FSIZE FIFO Size interrupt. 0 1 read-write FUNDFL FIFO Underflow interrupt. 2 3 read-write GENAD I2C General Address interrupt. 4 5 read-write IOINTW I2C Interrupt Write interrupt. 5 6 read-write XCMPRF Transfer complete interrupt, read from FIFO space. 6 7 read-write XCMPRR Transfer complete interrupt, read from register space. 7 8 read-write XCMPWF Transfer complete interrupt, write to FIFO space. 8 9 read-write XCMPWR Transfer complete interrupt, write to register space. 9 10 read-write INTSET IO Slave Interrupts: Set 0x20C 32 read-write n 0x0 0x0 FOVFL FIFO Overflow interrupt. 1 2 read-write FRDERR FIFO Read Error interrupt. 3 4 read-write FSIZE FIFO Size interrupt. 0 1 read-write FUNDFL FIFO Underflow interrupt. 2 3 read-write GENAD I2C General Address interrupt. 4 5 read-write IOINTW I2C Interrupt Write interrupt. 5 6 read-write XCMPRF Transfer complete interrupt, read from FIFO space. 6 7 read-write XCMPRR Transfer complete interrupt, read from register space. 7 8 read-write XCMPWF Transfer complete interrupt, write to FIFO space. 8 9 read-write XCMPWR Transfer complete interrupt, write to register space. 9 10 read-write INTSTAT IO Slave Interrupts: Status 0x204 32 read-write n 0x0 0x0 FOVFL FIFO Overflow interrupt. 1 2 read-write FRDERR FIFO Read Error interrupt. 3 4 read-write FSIZE FIFO Size interrupt. 0 1 read-write FUNDFL FIFO Underflow interrupt. 2 3 read-write GENAD I2C General Address interrupt. 4 5 read-write IOINTW I2C Interrupt Write interrupt. 5 6 read-write XCMPRF Transfer complete interrupt, read from FIFO space. 6 7 read-write XCMPRR Transfer complete interrupt, read from register space. 7 8 read-write XCMPWF Transfer complete interrupt, write to FIFO space. 8 9 read-write XCMPWR Transfer complete interrupt, write to register space. 9 10 read-write IOINTCTL I/O Interrupt Control 0x120 32 read-write n 0x0 0x0 IOINT These bits read the IOINT interrupts. 8 16 read-write IOINTCLR This bit clears all of the IOINT interrupts when written with a 1. 16 17 read-write IOINTEN These read-only bits indicate whether the IOINT interrupts are enabled. 0 8 read-write IOINTSET These bits set the IOINT interrupts when written with a 1. 24 32 read-write PRENC I/O Slave Interrupt Priority Encode 0x11C 32 read-write n 0x0 0x0 PRENC These bits hold the priority encode of the REGACC interrupts. 0 5 read-write REGACCINTCLR Register Access Interrupts: Clear 0x218 32 read-write n 0x0 0x0 REGACC Register access interrupts. 0 32 read-write REGACCINTEN Register Access Interrupts: Enable 0x210 32 read-write n 0x0 0x0 REGACC Register access interrupts. 0 32 read-write REGACCINTSET Register Access Interrupts: Set 0x21C 32 read-write n 0x0 0x0 REGACC Register access interrupts. 0 32 read-write REGACCINTSTAT Register Access Interrupts: Status 0x214 32 read-write n 0x0 0x0 REGACC Register access interrupts. 0 32 read-write MCUCTRL MCU Miscellaneous Control Logic MCUCTRL 0x0 0x0 0x34C registers n BROWNOUT 0 ADCBATTLOAD ADC Battery Load Enable 0x110 32 read-write n 0x0 0x0 BATTLOAD Enable the ADC battery load resistor 0 1 read-write DIS Battery load is disconnected 0 EN Battery load is enabled 1 ADCCAL ADC Calibration Control 0x10C 32 read-write n 0x0 0x0 ADCCALIBRATED Status for ADC Calibration 1 2 read-write FALSE ADC is not calibrated 0 TRUE ADC is calibrated 1 CALONPWRUP Run ADC Calibration on initial power up sequence 0 1 read-write DIS Disable automatic calibration on initial power up 0 EN Enable automatic calibration on initial power up 1 ADCPWRDLY ADC Power Up Delay Control 0x104 32 read-write n 0x0 0x0 ADCPWR0 ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2. 0 8 read-write ADCPWR1 ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2. 8 16 read-write BODPORCTRL BOD and PDR control Register 0x100 32 read-write n 0x0 0x0 BODEXTREFSEL BOD External Reference Select. 3 4 read-write SELECT BOD external reference select. 1 PDREXTREFSEL PDR External Reference Select. 2 3 read-write SELECT PDR external reference select. 1 PWDBOD BOD Power Down. 1 2 read-write PWR_DN BOD power down. 1 PWDPDR PDR Power Down. 0 1 read-write PWR_DN PDR power down 1 BOOTLOADERLOW Determines whether the bootloader code is visible at address 0x00000000 0x1A0 32 read-write n 0x0 0x0 VALUE Determines whether the bootloader code is visible at address 0x00000000 or not. 0 1 read-write ADDR0 Bootloader code at 0x00000000. 1 BUCK Analog Buck Control 0x60 32 read-write n 0x0 0x0 BUCKSWE Buck Register Software Override Enable. This will enable the override values for MEMBUCKPWD, COREBUCKPWD, COREBUCKRST, MEMBUCKRST, all to be propagated to the control logic, instead of the normal power control module signal. Note - Must take care to have correct value for ALL the register bits when this SWE is enabled. 0 1 read-write OVERRIDE_DIS BUCK Software Override Disable. 0 OVERRIDE_EN BUCK Software Override Enable. 1 BYPBUCKCORE Not used. Additional control of buck is available in the power control module 1 2 read-write BYPBUCKMEM Not used. Additional control of buck is available in the power control module 5 6 read-write COREBUCKPWD Core buck power down override. 1=Powered Down 0=Enabled Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module. 2 3 read-write EN Core Buck enable. 0 COREBUCKRST Reset control override for Core Buck 0=enabled, 1=reset Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module. 6 7 read-write MEMBUCKPWD Memory buck power down override. 1=Powered Down 0=Enabled Value is propagated only when the BUCKSWE bit is active, otherwise control is from the power control module. 4 5 read-write EN Memory Buck Enable. 0 MEMBUCKRST Reset control override for Mem Buck 0=enabled, 1=reset Value is propagated only when the BUCKSWE bit is active, otherwise contrl is from the power control module. 7 8 read-write SLEEPBUCKANA HFRC clkgen bit 0 override. When set, this will override to 0 bit 0 of the hfrc_freq_clkgen internal bus (see internal Shelby-1473) 3 4 read-write BUCK3 Buck control reg 3 0x68 32 read-write n 0x0 0x0 COREBUCKBURSTEN Core Buck burst enable. 0=disabled, 1=enabled 6 7 read-write COREBUCKHYSTTRIM Hysterisis trim for core buck 0 2 read-write COREBUCKLOTON Core Buck low TON trim value 7 11 read-write COREBUCKZXTRIM Core buck zero crossing trim value 2 6 read-write MEMBUCKBURSTEN MEM Buck burst enable 0=disable, 0=disabled, 1=enable. 17 18 read-write MEMBUCKHYSTTRIM Hysterisis trim for mem buck 11 13 read-write MEMBUCKLOTON MEM Buck low TON trim value 18 22 read-write MEMBUCKZXTRIM Memory buck zero crossing trim value 13 17 read-write BUCKTRIM Trim settings for Core and Mem buck modules 0x114 32 read-write n 0x0 0x0 COREBUCKR1_HI Core Buck voltage output trim bits[9:6]. Concatenate with field COREBUCKR1_LO for the full trim value. 16 20 read-write COREBUCKR1_LO Core Buck voltage output trim bits[5:0], Concatenate with field COREBUCKR1_HI for the full trim value. 8 14 read-write MEMBUCKR1 Trim values for BUCK regulator. 0 6 read-write RSVD2 RESERVED. 24 30 read-write CHIPID0 Unique Chip ID 0 0x4 32 read-write n 0x0 0x0 VALUE Unique chip ID 0. 0 32 read-write APOLLO2 Apollo2 CHIPID0. The lower 32-bits of the 64-bit CHIPID value, which is unique for each part. 0 CHIPID1 Unique Chip ID 1 0x8 32 read-write n 0x0 0x0 VALUE Unique chip ID 1. 0 32 read-write APOLLO2 Apollo2 CHIPID1. The upper 32-bits of the 64-bit CHIPID value, which is unique for each part. 0 CHIPREV Chip Revision 0xC 32 read-write n 0x0 0x0 REVMAJ Major Revision ID. 4 8 read-write A Apollo2 revision A 1 B Apollo2 revision B 2 REVMIN Minor Revision ID. 0 4 read-write REV0 Apollo2 minor revision value. Succeeding minor revisions will increment from this value. 0 REV2 Apollo2 minor revision value. 2 CHIP_INFO Chip Information Register 0x0 32 read-write n 0x0 0x0 PARTNUM BCD part number. 0 32 read-write APOLLO Apollo part number is 0x01XXXXXX. 16777216 PN_M Mask for the PN field. 4278190080 APOLLO2 Apollo2 part number is 0x03XXXXXX. 50331648 DBGR1 Read-only debug register 1 0x200 32 read-write n 0x0 0x0 ONETO8 Read-only register for communication validation 0 32 read-write DBGR2 Read-only debug register 2 0x204 32 read-write n 0x0 0x0 COOLCODE Read-only register for communication validation 0 32 read-write DCODEFAULTADDR DCODE bus address which was present when a bus fault occurred. 0x1C4 32 read-write n 0x0 0x0 ADDR The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. 0 32 read-write DEBUGGER Debugger Access Control 0x14 32 read-write n 0x0 0x0 LOCKOUT Lockout of debugger (SWD). 0 1 read-write FAULTCAPTUREEN Enable the fault capture registers 0x1D0 32 read-write n 0x0 0x0 ENABLE Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers. 0 1 read-write DIS Disable fault capture. 0 EN Enable fault capture. 1 FAULTSTATUS Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. 0x1CC 32 read-write n 0x0 0x0 DCODE DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault. 1 2 read-write NOFAULT No DCODE fault has been detected. 0 FAULT DCODE fault detected. 1 ICODE The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault. 0 1 read-write NOFAULT No ICODE fault has been detected. 0 FAULT ICODE fault detected. 1 SYS SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault. 2 3 read-write NOFAULT No bus fault has been detected. 0 FAULT Bus fault detected. 1 ICODEFAULTADDR ICODE bus address which was present when a bus fault occurred. 0x1C0 32 read-write n 0x0 0x0 ADDR The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. 0 32 read-write LDOREG1 Analog LDO Reg 1 0x80 32 read-write n 0x0 0x0 CORELDOIBSTRM CORE LDO IBIAS Trim 20 21 read-write CORELDOLPTRIM CORE LDO Low Power Trim 14 20 read-write TRIMCORELDOR1 CORE LDO Active mode ouput trim (R1). 0 10 read-write TRIMCORELDOR3 CORE LDO tempco trim (R3). 10 14 read-write LDOREG3 LDO Control Register 3 0x88 32 read-write n 0x0 0x0 MEMLDOLPALTTRIM MEM LDO TRIM for low power mode with ADC active 6 12 read-write MEMLDOLPTRIM MEM LDO TRIM for low power mode with ADC inactive 0 6 read-write TRIMMEMLDOR1 MEM LDO active mode trim (R1). 12 18 read-write PMUENABLE Control bit to enable/disable the PMU 0x220 32 read-write n 0x0 0x0 ENABLE PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode. 0 1 read-write DIS Disable MCU power management. 0 EN Enable MCU power management. 1 SHADOWVALID Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space. 0x1A4 32 read-write n 0x0 0x0 BL_DSLEEP Indicates whether the bootloader should sleep or deep sleep if no image loaded. 1 2 read-write DEEPSLEEP Bootloader will go to deep sleep if no flash image loaded 1 VALID Indicates whether the shadow registers contain valid data from the Flash Information Space. 0 1 read-write VALID Flash information space contains valid data. 1 SYSFAULTADDR System bus address which was present when a bus fault occurred. 0x1C8 32 read-write n 0x0 0x0 ADDR SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register. 0 32 read-write TPIUCTRL TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. 0x250 32 read-write n 0x0 0x0 CLKSEL This field selects the frequency of the ARM M4 TPIU port. 8 11 read-write LOW_PWR Low power state. 0 HFRC_DIV_2 Selects HFRC divided by 2 as the source TPIU clk 1 HFRC_DIV_8 Selects HFRC divided by 8 as the source TPIU clk 2 HFRC_DIV_16 Selects HFRC divided by 16 as the source TPIU clk 3 HFRC_DIV_32 Selects HFRC divided by 32 as the source TPIU clk 4 ENABLE TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules. 0 1 read-write DIS Disable the TPIU. 0 EN Enable the TPIU. 1 VENDORID Unique Vendor ID 0x10 32 read-write n 0x0 0x0 VALUE Unique Vendor ID 0 32 read-write AMBIQ Ambiq Vendor ID 1095582289 XTALGENCTRL XTAL Oscillator General Control 0x124 32 read-write n 0x0 0x0 ACWARMUP Auto-calibration delay control 0 2 read-write 1SEC Warmup period of 1-2 seconds 0 2SEC Warmup period of 2-4 seconds 1 4SEC Warmup period of 4-8 seconds 2 8SEC Warmup period of 8-16 seconds 3 XTALBIASTRIM XTAL IBIAS trim 2 8 read-write XTALKSBIASTRIM XTAL IBIAS Kick start trim . This trim value is used during the startup process to enable a faster lock and is applied when the kickstart signal is active. 8 14 read-write PDM PDM Audio PDM 0x0 0x0 0x210 registers n PDM 17 FLUSH FIFO Flush 0x10 32 read-write n 0x0 0x0 FIFOFLUSH FIFO FLUSH. 0 1 read-write FR Voice Status Register 0x8 32 read-write n 0x0 0x0 FIFOCNT Valid 32-bit entries currently in the FIFO. 0 9 read-write FRD FIFO Read 0xC 32 read-write n 0x0 0x0 FIFOREAD FIFO read data. 0 32 read-write FTHR FIFO Threshold 0x14 32 read-write n 0x0 0x0 FIFOTHR FIFO interrupt threshold. 0 8 read-write INTCLR IO Master Interrupts: Clear 0x208 32 read-write n 0x0 0x0 OVF This is the FIFO overflow interrupt. 1 2 read-write THR This is the FIFO threshold interrupt. 0 1 read-write UNDFL This is the FIFO underflow interrupt. 2 3 read-write INTEN IO Master Interrupts: Enable 0x200 32 read-write n 0x0 0x0 OVF This is the FIFO overflow interrupt. 1 2 read-write THR This is the FIFO threshold interrupt. 0 1 read-write UNDFL This is the FIFO underflow interrupt. 2 3 read-write INTSET IO Master Interrupts: Set 0x20C 32 read-write n 0x0 0x0 OVF This is the FIFO overflow interrupt. 1 2 read-write THR This is the FIFO threshold interrupt. 0 1 read-write UNDFL This is the FIFO underflow interrupt. 2 3 read-write INTSTAT IO Master Interrupts: Status 0x204 32 read-write n 0x0 0x0 OVF This is the FIFO overflow interrupt. 1 2 read-write THR This is the FIFO threshold interrupt. 0 1 read-write UNDFL This is the FIFO underflow interrupt. 2 3 read-write PCFG PDM Configuration Register 0x0 32 read-write n 0x0 0x0 ADCHPD High pass filter disable. 9 10 read-write EN Enable high pass filter. 0 DIS Disable high pass filter. 1 CYCLES Number of clocks during gain-setting changes. 2 5 read-write HPCUTOFF High pass filter coefficients. 5 9 read-write LRSWAP Left/right channel swap. 31 32 read-write NOSWAP No channel swapping (IFO Read LEFT_RIGHT). 0 EN Swap left and right channels (FIFO Read RIGHT_LEFT). 1 MCLKDIV PDM_CLK frequency divisor. 17 19 read-write MCKDIV1 Divide input clock by 1 0 MCKDIV2 Divide input clock by 2 1 MCKDIV3 Divide input clock by 3 2 MCKDIV4 Divide input clock by 4 3 PDMCORE Data Streaming Control. 0 1 read-write DIS Disable Data Streaming. 0 EN Enable Data Streaming. 1 PGALEFT Left channel PGA gain. 23 27 read-write 0DB 0.0 db gain. 0 P15DB 1.5 db gain. 1 M90DB -9.0 db gain. 10 M75DB -7.5 db gain. 11 M60DB -6.0 db gain. 12 M45DB -4.5 db gain. 13 M300DB -3.0 db gain. 14 M15DB -1.5 db gain. 15 P30DB 3.0 db gain. 2 P45DB 4.5 db gain. 3 P60DB 6.0 db gain. 4 P75DB 7.5 db gain. 5 P90DB 9.0 db gain. 6 P105DB 10.5 db gain. 7 M120DB -12.0 db gain. 8 M105DB -10.5 db gain. 9 PGARIGHT Right channel PGA gain. 27 31 read-write 0DB 0.0 db gain. 0 P15DB 1.5 db gain. 1 M90DB -9.0 db gain. 10 M75DB -7.5 db gain. 11 M60DB -6.0 db gain. 12 M45DB -4.5 db gain. 13 M300DB -3.0 db gain. 14 M15DB -1.5 db gain. 15 P30DB 3.0 db gain. 2 P45DB 4.5 db gain. 3 P60DB 6.0 db gain. 4 P75DB 7.5 db gain. 5 P90DB 9.0 db gain. 6 P105DB 10.5 db gain. 7 M120DB -12.0 db gain. 8 M105DB -10.5 db gain. 9 SINCRATE SINC decimation rate. 10 17 read-write SOFTMUTE Soft mute control. 1 2 read-write DIS Disable Soft Mute. 0 EN Enable Soft Mute. 1 VCFG Voice Configuration Register 0x4 32 read-write n 0x0 0x0 BCLKINV I2S BCLK input inversion. 19 20 read-write INV BCLK inverted. 0 NORM BCLK not inverted. 1 CHSET Set PCM channels. 3 5 read-write DIS Channel disabled. 0 LEFT Mono left channel. 1 RIGHT Mono right channel. 2 STEREO Stereo channels. 3 DMICKDEL PDM clock sampling delay. 17 18 read-write 0CYC No delay. 0 1CYC 1 cycle delay. 1 I2SMODE I2S interface enable. 20 21 read-write DIS Disable I2S interface. 0 EN Enable I2S interface. 1 IOCLKEN Enable the IO clock. 31 32 read-write DIS Disable FIFO read. 0 EN Enable FIFO read. 1 PCMPACK PCM data packing enable. 8 9 read-write DIS Disable PCM packing. 0 EN Enable PCM packing. 1 PDMCLK Enable the serial clock. 26 27 read-write DIS Disable serial clock. 0 EN Enable serial clock. 1 PDMCLKSEL Select the PDM input clock. 27 30 read-write DISABLE Static value. 0 12MHz PDM clock is 12 MHz. 1 6MHz PDM clock is 6 MHz. 2 3MHz PDM clock is 3 MHz. 3 1_5MHz PDM clock is 1.5 MHz. 4 750KHz PDM clock is 750 KHz. 5 375KHz PDM clock is 375 KHz. 6 187KHz PDM clock is 187.5 KHz. 7 RSTB Reset the IP core. 30 31 read-write RESET Reset the core. 0 NORM Enable the core. 1 SELAP Select PDM input clock source. 16 17 read-write INTERNAL Clock source from internal clock generator. 0 I2S Clock source from I2S BCLK. 1 PWRCTRL PWR Controller Register Bank PWRCTRL 0x0 0x0 0x24 registers n ADCSTATUS Power Status Register for ADC Block 0x1C 32 read-write n 0x0 0x0 ADC_BGT_PWD This bit indicates that the ADC Band Gap is powered down 1 2 read-write ADC_PWD This bit indicates that the ADC is powered down 0 1 read-write ADC_REFBUF_PWD This bit indicates that the ADC REFBUF is powered down 5 6 read-write ADC_REFKEEP_PWD This bit indicates that the ADC REFKEEP is powered down 4 5 read-write ADC_VBAT_PWD This bit indicates that the ADC VBAT resistor divider is powered down 3 4 read-write ADC_VPTAT_PWD This bit indicates that the ADC temperature sensor input buffer is powered down 2 3 read-write DEVICEEN DEVICE ENABLES for SHELBY 0x8 32 read-write n 0x0 0x0 IO_MASTER0 Enable IO MASTER 0 1 2 read-write DIS Disables IO MASTER 0 0 EN Enable IO MASTER 0 1 IO_MASTER1 Enable IO MASTER 1 2 3 read-write DIS Disables IO MASTER 1 0 EN Enable IO MASTER 1 1 IO_MASTER2 Enable IO MASTER 2 3 4 read-write DIS Disables IO MASTER 2 0 EN Enable IO MASTER 2 1 IO_MASTER3 Enable IO MASTER 3 4 5 read-write DIS Disables IO MASTER 3 0 EN Enable IO MASTER 3 1 IO_MASTER4 Enable IO MASTER 4 5 6 read-write DIS Disables IO MASTER 4 0 EN Enable IO MASTER 4 1 IO_MASTER5 Enable IO MASTER 5 6 7 read-write DIS Disables IO MASTER 5 0 EN Enable IO MASTER 5 1 IO_SLAVE Enable IO SLAVE 0 1 read-write DIS Disables IO SLAVE 0 EN Enable IO SLAVE 1 PWRADC Enable ADC Digital Block 9 10 read-write DIS Disables ADC 0 EN Enable ADC 1 PWRPDM Enable PDM Digital Block 10 11 read-write DIS Disables PDM 0 EN Enable PDM 1 PWRUART0 Enable UART 0 7 8 read-write DIS Disables UART 0 0 EN Enable UART 0 1 PWRUART1 Enable UART 1 8 9 read-write DIS Disables UART 1 0 EN Enable UART 1 1 MEMEN Disables individual banks of the MEMORY array 0x10 32 read-write n 0x0 0x0 CACHEB0 Enable CACHE BANK 0 29 30 read-write DIS Disable CACHE BANK 0 0 EN Enable CACHE BANK 0 1 CACHEB2 Enable CACHE BANK 2 31 32 read-write DIS Disable CACHE BANK 2 0 EN Enable CACHE BANK 2 1 FLASH0 Enable FLASH 0 11 12 read-write DIS Disables FLASH 0 0 EN Enable FLASH 0 1 FLASH1 Enable FLASH1 12 13 read-write DIS Disables FLASH1 0 EN Enable FLASH1 1 SRAMEN Enables power for selected SRAM banks (else an access to its address space to generate a Hard Fault). 0 11 read-write NONE All banks disabled 0 GROUP0_SRAM0 0KB-8KB SRAM 1 GROUP7 224KB-256KB SRAMs 1024 SRAM128K ENABLE lower 128KB 127 GROUP4 128KB-160KB SRAMs 128 SRAM32K ENABLE lower 32KB 15 GROUP1 32KB-64KB SRAMs 16 GROUP0_SRAM1 8KB-16KB SRAM 2 SRAM256K ENABLE lower 256KB 2047 GROUP5 160KB-192KB SRAMs 256 SRAM16K ENABLE lower 16KB 3 SRAM64K ENABLE lower 64KB 31 GROUP2 64KB-96KB SRAMs 32 GROUP0_SRAM2 16KB-24KB SRAM 4 GROUP6 192KB-224KB SRAMs 512 GROUP3 96KB-128KB SRAMs 64 GROUP0_SRAM3 24KB-32KB SRAM 8 MISCOPT Power Optimization Control Bits 0x20 32 read-write n 0x0 0x0 DIS_LDOLPMODE_TIMERS Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep even when the ctimers or stimers are running 2 3 read-write POWERSTATUS Power Status Register for MCU supplies and peripherals 0x4 32 read-write n 0x0 0x0 COREBUCKON Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck. 1 2 read-write LDO Indicates the the LDO is supplying the Core low-voltage. 0 BUCK Indicates the the Buck is supplying the Core low-voltage. 1 MEMBUCKON Indicate whether the Memory power domain is supplied from the LDO or the Buck. 0 1 read-write LDO Indicates the LDO is supplying the memory power domain. 0 BUCK Indicates the Buck is supplying the memory power domain. 1 PWRONSTATUS POWER ON Status 0x14 32 read-write n 0x0 0x0 PDA This bit is 1 if power is supplied to power domain A, which supplies IOS and UART0,1. 1 2 read-write PDADC This bit is 1 if power is supplied to domain PD_ADC 7 8 read-write PDB This bit is 1 if power is supplied to power domain B, which supplies IOM0-2. 2 3 read-write PDC This bit is 1 if power is supplied to power domain C, which supplies IOM3-5. 3 4 read-write PD_CACHEB0 This bit is 1 if power is supplied to CACHE BANK 0 19 20 read-write PD_CACHEB2 This bit is 1 if power is supplied to CACHE BANK 2 21 22 read-write PD_FLAM0 This bit is 1 if power is supplied to domain PD_FLAM0 5 6 read-write PD_FLAM1 This bit is 1 if power is supplied to domain PD_FLAM1 6 7 read-write PD_GRP0_SRAM0 This bit is 1 if power is supplied to SRAM domain SRAM0_0 8 9 read-write PD_GRP0_SRAM1 This bit is 1 if power is supplied to SRAM domain SRAM0_1 9 10 read-write PD_GRP0_SRAM2 This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2 10 11 read-write PD_GRP0_SRAM3 This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3 11 12 read-write PD_GRP1_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP1 12 13 read-write PD_GRP2_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP2 13 14 read-write PD_GRP3_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP3 14 15 read-write PD_GRP4_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP4 15 16 read-write PD_GRP5_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP5 16 17 read-write PD_GRP6_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP6 17 18 read-write PD_GRP7_SRAM This bit is 1 if power is supplied to SRAM domain PD_GRP7 18 19 read-write PD_PDM This bit is 1 if power is supplied to domain PD_PDM 4 5 read-write SRAMCTRL SRAM Control register 0x18 32 read-write n 0x0 0x0 SRAM_CLKGATE Enables individual per-RAM clock gating in the SRAM block. This bit should be enabled for lowest power operation. 1 2 read-write DIS Disables Individual SRAM Clock Gating 0 EN Enable Individual SRAM Clock Gating 1 SRAM_LIGHT_SLEEP Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will be put into light sleep mode while inactive. NOTE: if the SRAM is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved. 0 1 read-write DIS Disables LIGHT SLEEP for SRAMs 0 EN Enable LIGHT SLEEP for SRAMs 1 SRAM_MASTER_CLKGATE Enables top-level clock gating in the SRAM block. This bit should be enabled for lowest power operation. 2 3 read-write DIS Disables Master SRAM Clock Gating 0 EN Enable Master SRAM Clock Gate 1 SRAMPWDINSLEEP Powerdown an SRAM Banks in Deep Sleep mode 0xC 32 read-write n 0x0 0x0 CACHE_PWD_SLP Enable CACHE BANKS to power down in deep sleep 31 32 read-write DIS CACHE BANKS STAYS in Retention in CORE SLEEP 0 EN CACHE BANKS POWER DOWN in CORE SLEEP 1 SRAMSLEEPPOWERDOWN Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost. 0 11 read-write NONE All banks retained 0 GROUP0_SRAM0 0KB-8KB SRAM 1 GROUP7 224KB-256KB SRAMs 1024 SRAM128K Do not Retain lower 128KB 127 GROUP4 128KB-160KB SRAMs 128 SRAM32K Do not Retain lower 32KB 15 GROUP1 32KB-64KB SRAMs 16 ALLBUTLOWER128K All banks but lower 128k powered down. 1920 GROUP0_SRAM1 8KB-16KB SRAM 2 ALLBUTLOWER64K All banks but lower 64k powered down. 2016 ALLBUTLOWER32K All banks but lower 32k powered down. 2032 ALLBUTLOWER24K All banks but lower 24k powered down. 2040 ALLBUTLOWER16K All banks but lower 16k powered down. 2044 ALLBUTLOWER8K All banks but lower 8k powered down. 2046 ALL All banks powered down. 2047 GROUP5 160KB-192KB SRAMs 256 SRAM16K Do not Retain lower 16KB 3 SRAM64K Do not Retain lower 64KB 31 GROUP2 64KB-96KB SRAMs 32 GROUP0_SRAM2 16KB-24KB SRAM 4 GROUP6 192KB-224KB SRAMs 512 GROUP3 96KB-128KB SRAMs 64 GROUP0_SRAM3 24KB-32KB SRAM 8 SUPPLYSRC Memory and Core Voltage Supply Source Select Register 0x0 32 read-write n 0x0 0x0 COREBUCKEN Enables and Selects the Core Buck as the supply for the low-voltage power domain. 1 2 read-write EN Enable the Core Buck for the low-voltage power domain. 1 MEMBUCKEN Enables and select the Memory Buck as the supply for the Flash and SRAM power domain. 0 1 read-write EN Enable the Memory Buck as the supply for flash and SRAM. 1 SWITCH_LDO_IN_SLEEP Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in DEEP SLEEP. If all the devices are off then this does not matter and LDO (low power mode) is used 2 3 read-write EN Automatically switch from CORE BUCK to CORE LDO when CPU is in DEEP SLEEP 1 RSTGEN MCU Reset Generator RSTGEN 0x0 0x0 0x210 registers n CFG Configuration Register 0x0 32 read-write n 0x0 0x0 BODHREN Brown out high (2.1v) reset enable. 0 1 read-write WDREN Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. 1 2 read-write CLRSTAT Clear the status register 0x10 32 read-write n 0x0 0x0 CLRSTAT Writing a 1 to this bit clears all bits in the RST_STAT. 0 1 read-write INTCLR Reset Interrupt register: Clear 0x208 32 read-write n 0x0 0x0 BODH Enables an interrupt that triggers when VCC is below BODH level. 0 1 read-write INTEN Reset Interrupt register: Enable 0x200 32 read-write n 0x0 0x0 BODH Enables an interrupt that triggers when VCC is below BODH level. 0 1 read-write INTSET Reset Interrupt register: Set 0x20C 32 read-write n 0x0 0x0 BODH Enables an interrupt that triggers when VCC is below BODH level. 0 1 read-write INTSTAT Reset Interrupt register: Status 0x204 32 read-write n 0x0 0x0 BODH Enables an interrupt that triggers when VCC is below BODH level. 0 1 read-write STAT Status Register 0xC 32 read-write n 0x0 0x0 BORSTAT Reset was initiated by a Brown-Out Reset. 2 3 read-write DBGRSTAT Reset was a initiated by Debugger Reset. 5 6 read-write EXRSTAT Reset was initiated by an External Reset. 0 1 read-write POIRSTAT Reset was a initiated by Software POI Reset. 4 5 read-write PORSTAT Reset was initiated by a Power-On Reset. 1 2 read-write SWRSTAT Reset was a initiated by SW POR or AIRCR Reset. 3 4 read-write WDRSTAT Reset was initiated by a Watchdog Timer Reset. 6 7 read-write SWPOI Software POI Reset 0x4 32 read-write n 0x0 0x0 SWPOIKEY 0x1B generates a software POI reset. 0 8 read-write KEYVALUE Writing 0x1B key value generates a software POI reset. 27 SWPOR Software POR Reset 0x8 32 read-write n 0x0 0x0 SWPORKEY 0xD4 generates a software POR reset. 0 8 read-write KEYVALUE Writing 0xD4 key value generates a software POR reset. 212 TPIU_RST TPIU reset 0x14 32 read-write n 0x0 0x0 TPIURST Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset. 0 1 read-write RTC Real Time Clock RTC 0x0 0x0 0xD0 registers n ALMLOW RTC Alarms Lower 0x8 32 read-write n 0x0 0x0 ALM100 100ths of a second Alarm 0 8 read-write ALMHR Hours Alarm 24 30 read-write ALMMIN Minutes Alarm 16 23 read-write ALMSEC Seconds Alarm 8 15 read-write ALMUP RTC Alarms Upper 0xC 32 read-write n 0x0 0x0 ALMDATE Date Alarm 0 6 read-write ALMMO Months Alarm 8 13 read-write ALMWKDY Weekdays Alarm 16 19 read-write CTRLOW RTC Counters Lower 0x0 32 read-write n 0x0 0x0 CTR100 100ths of a second Counter 0 8 read-write CTRHR Hours Counter 24 30 read-write CTRMIN Minutes Counter 16 23 read-write CTRSEC Seconds Counter 8 15 read-write CTRUP RTC Counters Upper 0x4 32 read-write n 0x0 0x0 CB Century 27 28 read-write 2000 Century is 2000s 0 1900_2100 Century is 1900s/2100s 1 CEB Century enable 28 29 read-write DIS Disable the Century bit from changing 0 EN Enable the Century bit to change 1 CTERR Counter read error status 31 32 read-write NOERR No read error occurred 0 RDERR Read error occurred 1 CTRDATE Date Counter 0 6 read-write CTRMO Months Counter 8 13 read-write CTRWKDY Weekdays Counter 24 27 read-write CTRYR Years Counter 16 24 read-write INTCLR RTC Interrupt Register: Clear 0xC8 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTEN RTC Interrupt Register: Enable 0xC0 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTSET RTC Interrupt Register: Set 0xCC 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write INTSTAT RTC Interrupt Register: Status 0xC4 32 read-write n 0x0 0x0 ACC Autocalibration Complete interrupt 1 2 read-write ACF Autocalibration Fail interrupt 0 1 read-write ALM RTC Alarm interrupt 3 4 read-write OF XT Oscillator Fail interrupt 2 3 read-write RTCCTL RTC Control Register 0x10 32 read-write n 0x0 0x0 HR1224 Hours Counter mode 5 6 read-write 24HR Hours in 24 hour mode 0 12HR Hours in 12 hour mode 1 RPT Alarm repeat interval 1 4 read-write DIS Alarm interrupt disabled 0 YEAR Interrupt every year 1 MONTH Interrupt every month 2 WEEK Interrupt every week 3 DAY Interrupt every day 4 HR Interrupt every hour 5 MIN Interrupt every minute 6 SEC Interrupt every second/10th/100th 7 RSTOP RTC input clock control 4 5 read-write RUN Allow the RTC input clock to run 0 STOP Stop the RTC input clock 1 WRTC Counter write control 0 1 read-write DIS Counter writes are disabled 0 EN Counter writes are enabled 1 UART0 Serial UART UART0 0x0 0x0 0x48 registers n UART0 14 CR Control Register 0x30 32 read-write n 0x0 0x0 CLKEN This bit is the UART clock enable. 3 4 read-write CLKSEL This bitfield is the UART clock select. 4 7 read-write NOCLK No UART clock. This is the low power default. 0 24MHZ 24 MHz clock. 1 12MHZ 12 MHz clock. 2 6MHZ 6 MHz clock. 3 3MHZ 3 MHz clock. 4 CTSEN This bit enables CTS hardware flow control. 15 16 read-write DTR This bit enables data transmit ready. 10 11 read-write LBE This bit is the loopback enable. 7 8 read-write OUT1 This bit holds modem Out1. 12 13 read-write OUT2 This bit holds modem Out2. 13 14 read-write RTS This bit enables request to send. 11 12 read-write RTSEN This bit enables RTS hardware flow control. 14 15 read-write RXE This bit is the receive enable. 9 10 read-write SIREN This bit is the SIR ENDEC enable. 1 2 read-write SIRLP This bit is the SIR low power select. 2 3 read-write TXE This bit is the transmit enable. 8 9 read-write UARTEN This bit is the UART enable. 0 1 read-write DR UART Data Register 0x0 32 read-write n 0x0 0x0 BEDATA This is the break error indicator. 10 11 read-write NOERR No error on UART BEDATA, break error indicator. 0 ERR Error on UART BEDATA, break error indicator. 1 DATA This is the UART data port. 0 8 read-write FEDATA This is the framing error indicator. 8 9 read-write NOERR No error on UART FEDATA, framing error indicator. 0 ERR Error on UART FEDATA, framing error indicator. 1 OEDATA This is the overrun error indicator. 11 12 read-write NOERR No error on UART OEDATA, overrun error indicator. 0 ERR Error on UART OEDATA, overrun error indicator. 1 PEDATA This is the parity error indicator. 9 10 read-write NOERR No error on UART PEDATA, parity error indicator. 0 ERR Error on UART PEDATA, parity error indicator. 1 FBRD Fractional Baud Rate Divisor 0x28 32 read-write n 0x0 0x0 DIVFRAC These bits hold the baud fractional divisor. 0 6 read-write FR Flag Register 0x18 32 read-write n 0x0 0x0 BUSY This bit holds the busy indicator. 3 4 read-write BUSY UART busy indicator. 1 CTS This bit holds the clear to send indicator. 0 1 read-write CLEARTOSEND Clear to send is indicated. 1 DCD This bit holds the data carrier detect indicator. 2 3 read-write DETECTED Data carrier detect detected. 1 DSR This bit holds the data set ready indicator. 1 2 read-write READY Data set ready. 1 RXFE This bit holds the receive FIFO empty indicator. 4 5 read-write RCVFIFO_EMPTY Receive fifo is empty. 1 RXFF This bit holds the receive FIFO full indicator. 6 7 read-write RCVFIFO_FULL Receive fifo is full. 1 TXBUSY This bit holds the transmit BUSY indicator. 8 9 read-write TXFE This bit holds the transmit FIFO empty indicator. 7 8 read-write XMTFIFO_EMPTY Transmit fifo is empty. 1 TXFF This bit holds the transmit FIFO full indicator. 5 6 read-write XMTFIFO_FULL Transmit fifo is full. 1 IBRD Integer Baud Rate Divisor 0x24 32 read-write n 0x0 0x0 DIVINT These bits hold the baud integer divisor. 0 16 read-write IEC Interrupt Clear 0x44 32 read-write n 0x0 0x0 BEIC This bit holds the break error interrupt clear. 9 10 read-write CTSMIC This bit holds the modem CTS interrupt clear. 1 2 read-write DCDMIC This bit holds the modem DCD interrupt clear. 2 3 read-write DSRMIC This bit holds the modem DSR interrupt clear. 3 4 read-write FEIC This bit holds the framing error interrupt clear. 7 8 read-write OEIC This bit holds the overflow interrupt clear. 10 11 read-write PEIC This bit holds the parity error interrupt clear. 8 9 read-write RTIC This bit holds the receive timeout interrupt clear. 6 7 read-write RXIC This bit holds the receive interrupt clear. 4 5 read-write TXCMPMIC This bit holds the modem TXCMP interrupt clear. 0 1 read-write TXIC This bit holds the transmit interrupt clear. 5 6 read-write IER Interrupt Enable 0x38 32 read-write n 0x0 0x0 BEIM This bit holds the break error interrupt enable. 9 10 read-write CTSMIM This bit holds the modem CTS interrupt enable. 1 2 read-write DCDMIM This bit holds the modem DCD interrupt enable. 2 3 read-write DSRMIM This bit holds the modem DSR interrupt enable. 3 4 read-write FEIM This bit holds the framing error interrupt enable. 7 8 read-write OEIM This bit holds the overflow interrupt enable. 10 11 read-write PEIM This bit holds the parity error interrupt enable. 8 9 read-write RTIM This bit holds the receive timeout interrupt enable. 6 7 read-write RXIM This bit holds the receive interrupt enable. 4 5 read-write TXCMPMIM This bit holds the modem TXCMP interrupt enable. 0 1 read-write TXIM This bit holds the transmit interrupt enable. 5 6 read-write IES Interrupt Status 0x3C 32 read-write n 0x0 0x0 BERIS This bit holds the break error interrupt status. 9 10 read-write CTSMRIS This bit holds the modem CTS interrupt status. 1 2 read-write DCDMRIS This bit holds the modem DCD interrupt status. 2 3 read-write DSRMRIS This bit holds the modem DSR interrupt status. 3 4 read-write FERIS This bit holds the framing error interrupt status. 7 8 read-write OERIS This bit holds the overflow interrupt status. 10 11 read-write PERIS This bit holds the parity error interrupt status. 8 9 read-write RTRIS This bit holds the receive timeout interrupt status. 6 7 read-write RXRIS This bit holds the receive interrupt status. 4 5 read-write TXCMPMRIS This bit holds the modem TXCMP interrupt status. 0 1 read-write TXRIS This bit holds the transmit interrupt status. 5 6 read-write IFLS FIFO Interrupt Level Select 0x34 32 read-write n 0x0 0x0 RXIFLSEL These bits hold the receive FIFO interrupt level. 3 6 read-write TXIFLSEL These bits hold the transmit FIFO interrupt level. 0 3 read-write ILPR IrDA Counter 0x20 32 read-write n 0x0 0x0 ILPDVSR These bits hold the IrDA counter divisor. 0 8 read-write LCRH Line Control High 0x2C 32 read-write n 0x0 0x0 BRK This bit holds the break set. 0 1 read-write EPS This bit holds the even parity select. 2 3 read-write FEN This bit holds the FIFO enable. 4 5 read-write PEN This bit holds the parity enable. 1 2 read-write SPS This bit holds the stick parity select. 7 8 read-write STP2 This bit holds the two stop bits select. 3 4 read-write WLEN These bits hold the write length. 5 7 read-write MIS Masked Interrupt Status 0x40 32 read-write n 0x0 0x0 BEMIS This bit holds the break error interrupt status masked. 9 10 read-write CTSMMIS This bit holds the modem CTS interrupt status masked. 1 2 read-write DCDMMIS This bit holds the modem DCD interrupt status masked. 2 3 read-write DSRMMIS This bit holds the modem DSR interrupt status masked. 3 4 read-write FEMIS This bit holds the framing error interrupt status masked. 7 8 read-write OEMIS This bit holds the overflow interrupt status masked. 10 11 read-write PEMIS This bit holds the parity error interrupt status masked. 8 9 read-write RTMIS This bit holds the receive timeout interrupt status masked. 6 7 read-write RXMIS This bit holds the receive interrupt status masked. 4 5 read-write TXCMPMMIS This bit holds the modem TXCMP interrupt status masked. 0 1 read-write TXMIS This bit holds the transmit interrupt status masked. 5 6 read-write RSR UART Status Register 0x4 32 read-write n 0x0 0x0 BESTAT This is the break error indicator. 2 3 read-write NOERR No error on UART BESTAT, break error indicator. 0 ERR Error on UART BESTAT, break error indicator. 1 FESTAT This is the framing error indicator. 0 1 read-write NOERR No error on UART FESTAT, framing error indicator. 0 ERR Error on UART FESTAT, framing error indicator. 1 OESTAT This is the overrun error indicator. 3 4 read-write NOERR No error on UART OESTAT, overrun error indicator. 0 ERR Error on UART OESTAT, overrun error indicator. 1 PESTAT This is the parity error indicator. 1 2 read-write NOERR No error on UART PESTAT, parity error indicator. 0 ERR Error on UART PESTAT, parity error indicator. 1 UART1 Serial UART UART0 0x0 0x0 0x48 registers n UART1 15 CR Control Register 0x30 32 read-write n 0x0 0x0 CLKEN This bit is the UART clock enable. 3 4 read-write CLKSEL This bitfield is the UART clock select. 4 7 read-write NOCLK No UART clock. This is the low power default. 0 24MHZ 24 MHz clock. 1 12MHZ 12 MHz clock. 2 6MHZ 6 MHz clock. 3 3MHZ 3 MHz clock. 4 CTSEN This bit enables CTS hardware flow control. 15 16 read-write DTR This bit enables data transmit ready. 10 11 read-write LBE This bit is the loopback enable. 7 8 read-write OUT1 This bit holds modem Out1. 12 13 read-write OUT2 This bit holds modem Out2. 13 14 read-write RTS This bit enables request to send. 11 12 read-write RTSEN This bit enables RTS hardware flow control. 14 15 read-write RXE This bit is the receive enable. 9 10 read-write SIREN This bit is the SIR ENDEC enable. 1 2 read-write SIRLP This bit is the SIR low power select. 2 3 read-write TXE This bit is the transmit enable. 8 9 read-write UARTEN This bit is the UART enable. 0 1 read-write DR UART Data Register 0x0 32 read-write n 0x0 0x0 BEDATA This is the break error indicator. 10 11 read-write NOERR No error on UART BEDATA, break error indicator. 0 ERR Error on UART BEDATA, break error indicator. 1 DATA This is the UART data port. 0 8 read-write FEDATA This is the framing error indicator. 8 9 read-write NOERR No error on UART FEDATA, framing error indicator. 0 ERR Error on UART FEDATA, framing error indicator. 1 OEDATA This is the overrun error indicator. 11 12 read-write NOERR No error on UART OEDATA, overrun error indicator. 0 ERR Error on UART OEDATA, overrun error indicator. 1 PEDATA This is the parity error indicator. 9 10 read-write NOERR No error on UART PEDATA, parity error indicator. 0 ERR Error on UART PEDATA, parity error indicator. 1 FBRD Fractional Baud Rate Divisor 0x28 32 read-write n 0x0 0x0 DIVFRAC These bits hold the baud fractional divisor. 0 6 read-write FR Flag Register 0x18 32 read-write n 0x0 0x0 BUSY This bit holds the busy indicator. 3 4 read-write BUSY UART busy indicator. 1 CTS This bit holds the clear to send indicator. 0 1 read-write CLEARTOSEND Clear to send is indicated. 1 DCD This bit holds the data carrier detect indicator. 2 3 read-write DETECTED Data carrier detect detected. 1 DSR This bit holds the data set ready indicator. 1 2 read-write READY Data set ready. 1 RXFE This bit holds the receive FIFO empty indicator. 4 5 read-write RCVFIFO_EMPTY Receive fifo is empty. 1 RXFF This bit holds the receive FIFO full indicator. 6 7 read-write RCVFIFO_FULL Receive fifo is full. 1 TXBUSY This bit holds the transmit BUSY indicator. 8 9 read-write TXFE This bit holds the transmit FIFO empty indicator. 7 8 read-write XMTFIFO_EMPTY Transmit fifo is empty. 1 TXFF This bit holds the transmit FIFO full indicator. 5 6 read-write XMTFIFO_FULL Transmit fifo is full. 1 IBRD Integer Baud Rate Divisor 0x24 32 read-write n 0x0 0x0 DIVINT These bits hold the baud integer divisor. 0 16 read-write IEC Interrupt Clear 0x44 32 read-write n 0x0 0x0 BEIC This bit holds the break error interrupt clear. 9 10 read-write CTSMIC This bit holds the modem CTS interrupt clear. 1 2 read-write DCDMIC This bit holds the modem DCD interrupt clear. 2 3 read-write DSRMIC This bit holds the modem DSR interrupt clear. 3 4 read-write FEIC This bit holds the framing error interrupt clear. 7 8 read-write OEIC This bit holds the overflow interrupt clear. 10 11 read-write PEIC This bit holds the parity error interrupt clear. 8 9 read-write RTIC This bit holds the receive timeout interrupt clear. 6 7 read-write RXIC This bit holds the receive interrupt clear. 4 5 read-write TXCMPMIC This bit holds the modem TXCMP interrupt clear. 0 1 read-write TXIC This bit holds the transmit interrupt clear. 5 6 read-write IER Interrupt Enable 0x38 32 read-write n 0x0 0x0 BEIM This bit holds the break error interrupt enable. 9 10 read-write CTSMIM This bit holds the modem CTS interrupt enable. 1 2 read-write DCDMIM This bit holds the modem DCD interrupt enable. 2 3 read-write DSRMIM This bit holds the modem DSR interrupt enable. 3 4 read-write FEIM This bit holds the framing error interrupt enable. 7 8 read-write OEIM This bit holds the overflow interrupt enable. 10 11 read-write PEIM This bit holds the parity error interrupt enable. 8 9 read-write RTIM This bit holds the receive timeout interrupt enable. 6 7 read-write RXIM This bit holds the receive interrupt enable. 4 5 read-write TXCMPMIM This bit holds the modem TXCMP interrupt enable. 0 1 read-write TXIM This bit holds the transmit interrupt enable. 5 6 read-write IES Interrupt Status 0x3C 32 read-write n 0x0 0x0 BERIS This bit holds the break error interrupt status. 9 10 read-write CTSMRIS This bit holds the modem CTS interrupt status. 1 2 read-write DCDMRIS This bit holds the modem DCD interrupt status. 2 3 read-write DSRMRIS This bit holds the modem DSR interrupt status. 3 4 read-write FERIS This bit holds the framing error interrupt status. 7 8 read-write OERIS This bit holds the overflow interrupt status. 10 11 read-write PERIS This bit holds the parity error interrupt status. 8 9 read-write RTRIS This bit holds the receive timeout interrupt status. 6 7 read-write RXRIS This bit holds the receive interrupt status. 4 5 read-write TXCMPMRIS This bit holds the modem TXCMP interrupt status. 0 1 read-write TXRIS This bit holds the transmit interrupt status. 5 6 read-write IFLS FIFO Interrupt Level Select 0x34 32 read-write n 0x0 0x0 RXIFLSEL These bits hold the receive FIFO interrupt level. 3 6 read-write TXIFLSEL These bits hold the transmit FIFO interrupt level. 0 3 read-write ILPR IrDA Counter 0x20 32 read-write n 0x0 0x0 ILPDVSR These bits hold the IrDA counter divisor. 0 8 read-write LCRH Line Control High 0x2C 32 read-write n 0x0 0x0 BRK This bit holds the break set. 0 1 read-write EPS This bit holds the even parity select. 2 3 read-write FEN This bit holds the FIFO enable. 4 5 read-write PEN This bit holds the parity enable. 1 2 read-write SPS This bit holds the stick parity select. 7 8 read-write STP2 This bit holds the two stop bits select. 3 4 read-write WLEN These bits hold the write length. 5 7 read-write MIS Masked Interrupt Status 0x40 32 read-write n 0x0 0x0 BEMIS This bit holds the break error interrupt status masked. 9 10 read-write CTSMMIS This bit holds the modem CTS interrupt status masked. 1 2 read-write DCDMMIS This bit holds the modem DCD interrupt status masked. 2 3 read-write DSRMMIS This bit holds the modem DSR interrupt status masked. 3 4 read-write FEMIS This bit holds the framing error interrupt status masked. 7 8 read-write OEMIS This bit holds the overflow interrupt status masked. 10 11 read-write PEMIS This bit holds the parity error interrupt status masked. 8 9 read-write RTMIS This bit holds the receive timeout interrupt status masked. 6 7 read-write RXMIS This bit holds the receive interrupt status masked. 4 5 read-write TXCMPMMIS This bit holds the modem TXCMP interrupt status masked. 0 1 read-write TXMIS This bit holds the transmit interrupt status masked. 5 6 read-write RSR UART Status Register 0x4 32 read-write n 0x0 0x0 BESTAT This is the break error indicator. 2 3 read-write NOERR No error on UART BESTAT, break error indicator. 0 ERR Error on UART BESTAT, break error indicator. 1 FESTAT This is the framing error indicator. 0 1 read-write NOERR No error on UART FESTAT, framing error indicator. 0 ERR Error on UART FESTAT, framing error indicator. 1 OESTAT This is the overrun error indicator. 3 4 read-write NOERR No error on UART OESTAT, overrun error indicator. 0 ERR Error on UART OESTAT, overrun error indicator. 1 PESTAT This is the parity error indicator. 1 2 read-write NOERR No error on UART PESTAT, parity error indicator. 0 ERR Error on UART PESTAT, parity error indicator. 1 VCOMP Voltage Comparator VCOMP 0x0 0x0 0x210 registers n VCOMP 3 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 LVLSEL When the reference input NSEL is set to NSEL_DAC, this bitfield selects the voltage level for the negative input to the comparator. 16 20 read-write 0P58V Set Reference input to 0.58 Volts. 0 0P77V Set Reference input to 0.77 Volts. 1 2P51V Set Reference input to 2.51 Volts. 10 2P71V Set Reference input to 2.71 Volts. 11 2P90V Set Reference input to 2.90 Volts. 12 3P09V Set Reference input to 3.09 Volts. 13 3P29V Set Reference input to 3.29 Volts. 14 3P48V Set Reference input to 3.48 Volts. 15 0P97V Set Reference input to 0.97 Volts. 2 1P16V Set Reference input to 1.16 Volts. 3 1P35V Set Reference input to 1.35 Volts. 4 1P55V Set Reference input to 1.55 Volts. 5 1P74V Set Reference input to 1.74 Volts. 6 1P93V Set Reference input to 1.93 Volts. 7 2P13V Set Reference input to 2.13 Volts. 8 2P32V Set Reference input to 2.32 Volts. 9 NSEL This bitfield selects the negative input to the comparator. 8 10 read-write VREFEXT1 Use external reference 1 for reference input. 0 VREFEXT2 Use external reference 2 for reference input. 1 VREFEXT3 Use external reference 3 for reference input. 2 DAC Use DAC output selected by LVLSEL for reference input. 3 PSEL This bitfield selects the positive input to the comparator. 0 2 read-write VDDADJ Use VDDADJ for the positive input. 0 VTEMP Use the temperature sensor output for the positive input. Note: If this channel is selected for PSEL, the bandap circuit required for temperature comparisons will automatically turn on. The bandgap circuit requires 11us to stabalize. 1 VEXT1 Use external voltage 0 for positive input. 2 VEXT2 Use external voltage 1 for positive input. 3 INTCLR Voltage Comparator Interrupt registers: Clear 0x208 32 read-write n 0x0 0x0 OUTHI This bit is the vcompout high interrupt. 1 2 read-write OUTLOW This bit is the vcompout low interrupt. 0 1 read-write INTEN Voltage Comparator Interrupt registers: Enable 0x200 32 read-write n 0x0 0x0 OUTHI This bit is the vcompout high interrupt. 1 2 read-write OUTLOW This bit is the vcompout low interrupt. 0 1 read-write INTSET Voltage Comparator Interrupt registers: Set 0x20C 32 read-write n 0x0 0x0 OUTHI This bit is the vcompout high interrupt. 1 2 read-write OUTLOW This bit is the vcompout low interrupt. 0 1 read-write INTSTAT Voltage Comparator Interrupt registers: Status 0x204 32 read-write n 0x0 0x0 OUTHI This bit is the vcompout high interrupt. 1 2 read-write OUTLOW This bit is the vcompout low interrupt. 0 1 read-write PWDKEY Key Register for Powering Down the Voltage Comparator 0x8 32 read-write n 0x0 0x0 PWDKEY Key register value. 0 32 read-write Key Key 55 STAT Status Register 0x4 32 read-write n 0x0 0x0 CMPOUT This bit is 1 if the positive input of the comparator is greater than the negative input. 0 1 read-write VOUT_LOW The negative input of the comparator is greater than the positive input. 0 VOUT_HIGH The positive input of the comparator is greater than the negative input. 1 PWDSTAT This bit indicates the power down state of the voltage comparator. 1 2 read-write POWERED_DOWN The voltage comparator is powered down. 1 WDT Watchdog Timer WDT 0x0 0x0 0x210 registers n WDT 1 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 CLKSEL Select the frequency for the WDT. All values not enumerated below are undefined. 24 27 read-write OFF Low Power Mode. 0 128HZ 128 Hz LFRC clock. 1 16HZ 16 Hz LFRC clock. 2 1HZ 1 Hz LFRC clock. 3 1_16HZ 1/16th Hz LFRC clock. 4 INTEN This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC. 1 2 read-write INTVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt. 16 24 read-write RESEN This bitfield enables the WDT reset. 2 3 read-write RESVAL This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset. 8 16 read-write WDTEN This bitfield enables the WDT. 0 1 read-write COUNT Current Counter Value for WDT 0xC 32 read-write n 0x0 0x0 COUNT Read-Only current value of the WDT counter 0 8 read-write INTCLR WDT Interrupt register: Clear 0x208 32 read-write n 0x0 0x0 WDTINT Watchdog Timer Interrupt. 0 1 read-write INTEN WDT Interrupt register: Enable 0x200 32 read-write n 0x0 0x0 WDTINT Watchdog Timer Interrupt. 0 1 read-write INTSET WDT Interrupt register: Set 0x20C 32 read-write n 0x0 0x0 WDTINT Watchdog Timer Interrupt. 0 1 read-write INTSTAT WDT Interrupt register: Status 0x204 32 read-write n 0x0 0x0 WDTINT Watchdog Timer Interrupt. 0 1 read-write LOCK Locks the WDT 0x8 32 read-write n 0x0 0x0 LOCK Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be written and WDTEN is set. 0 8 read-write KEYVALUE This is the key value to write to WDTLOCK to lock the WDT. 58 RSTRT Restart the watchdog timer 0x4 32 read-write n 0x0 0x0 RSTRT Writing 0xB2 to WDTRSTRT restarts the watchdog timer. 0 8 read-write KEYVALUE This is the key value to write to WDTRSTRT to restart the WDT. 178