Espressif esp32 2024.05.04 esp32 Xtensa LX6 1 little true 3 false 32 AES AES 0x0 0x0 0x0 registers n ENDIAN AES Endian selection 0x40 32 read-write n 0x0 0x0 MODE Select AES endian mode 0 6 IDLE AES Idle 0x4 32 read-only n 0x0 0x0 IDLE 0 when AES is busy, 1 otherwise 0 1 KEY_0 AES Key material 0 0x10 32 read-write n 0x0 0x0 KEY_1 AES Key material 1 0x14 32 read-write n 0x0 0x0 KEY_2 AES Key material 2 0x18 32 read-write n 0x0 0x0 KEY_3 AES Key material 3 0x1C 32 read-write n 0x0 0x0 KEY_4 AES Key material 4 0x20 32 read-write n 0x0 0x0 KEY_5 AES Key material 5 0x24 32 read-write n 0x0 0x0 KEY_6 AES Key material 6 0x28 32 read-write n 0x0 0x0 KEY_7 AES Key material 7 0x2C 32 read-write n 0x0 0x0 MODE AES Mode 0x8 32 read-write n 0x0 0x0 MODE Selects AES accelerator mode 0 3 MODE read-write AES128_ENCRYPT AES-128 Encryption 0 AES192_ENCRYPT AES-192 Encryption 1 AES256_ENCRYPT AES-256 Encryption 2 AES128_DECRYPT AES-128 Decryption 4 AES192_DECRYPT AES-192 Decryption 5 AES256_DECRYPT AES-256 Decryption 6 START AES Start 0x0 32 write-only n 0x0 0x0 START Write 1 to start AES operation 0 1 TEXT_0 Plaintext and ciphertext register 0 0x30 32 read-write n 0x0 0x0 TEXT_1 Plaintext and ciphertext register 1 0x34 32 read-write n 0x0 0x0 TEXT_2 Plaintext and ciphertext register 2 0x38 32 read-write n 0x0 0x0 TEXT_3 Plaintext and ciphertext register 3 0x3C 32 read-write n 0x0 0x0 APB_CTRL APB_CTRL 0x0 0x0 0x220 registers n APB_SARADC_CTRL APB_CTRL_APB_SARADC_CTRL 0x10 32 read-write n 0x0 0x0 SARADC_DATA_SAR_SEL 25 1 SARADC_DATA_TO_I2S 26 1 SARADC_SAR1_PATT_LEN 15 4 SARADC_SAR1_PATT_P_CLEAR 23 1 SARADC_SAR2_MUX 2 1 SARADC_SAR2_PATT_LEN 19 4 SARADC_SAR2_PATT_P_CLEAR 24 1 SARADC_SAR_CLK_DIV 7 8 SARADC_SAR_CLK_GATED 6 1 SARADC_SAR_SEL 5 1 SARADC_START 1 1 SARADC_START_FORCE 0 1 SARADC_WORK_MODE 3 2 APB_SARADC_CTRL2 APB_CTRL_APB_SARADC_CTRL2 0x14 32 read-write n 0x0 0x0 SARADC_MAX_MEAS_NUM 1 8 SARADC_MEAS_NUM_LIMIT 0 1 SARADC_SAR1_INV 9 1 SARADC_SAR2_INV 10 1 APB_SARADC_FSM APB_CTRL_APB_SARADC_FSM 0x18 32 read-write n 0x0 0x0 SARADC_RSTB_WAIT 0 8 SARADC_SAMPLE_CYCLE 24 8 SARADC_STANDBY_WAIT 8 8 SARADC_START_WAIT 16 8 APB_SARADC_SAR1_PATT_TAB1 APB_CTRL_APB_SARADC_SAR1_PATT_TAB1 0x1C 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB1 0 32 APB_SARADC_SAR1_PATT_TAB2 APB_CTRL_APB_SARADC_SAR1_PATT_TAB2 0x20 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB2 0 32 APB_SARADC_SAR1_PATT_TAB3 APB_CTRL_APB_SARADC_SAR1_PATT_TAB3 0x24 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB3 0 32 APB_SARADC_SAR1_PATT_TAB4 APB_CTRL_APB_SARADC_SAR1_PATT_TAB4 0x28 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB4 0 32 APB_SARADC_SAR2_PATT_TAB1 APB_CTRL_APB_SARADC_SAR2_PATT_TAB1 0x2C 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB1 0 32 APB_SARADC_SAR2_PATT_TAB2 APB_CTRL_APB_SARADC_SAR2_PATT_TAB2 0x30 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB2 0 32 APB_SARADC_SAR2_PATT_TAB3 APB_CTRL_APB_SARADC_SAR2_PATT_TAB3 0x34 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB3 0 32 APB_SARADC_SAR2_PATT_TAB4 APB_CTRL_APB_SARADC_SAR2_PATT_TAB4 0x38 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB4 0 32 APLL_TICK_CONF APB_CTRL_APLL_TICK_CONF 0x3C 32 read-write n 0x0 0x0 APLL_TICK_NUM 0 8 CK8M_TICK_CONF APB_CTRL_CK8M_TICK_CONF 0xC 32 read-write n 0x0 0x0 CK8M_TICK_NUM 0 8 DATE APB_CTRL_DATE 0x7C 32 read-write n 0x0 0x0 DATE 0 32 PLL_TICK_CONF APB_CTRL_PLL_TICK_CONF 0x8 32 read-write n 0x0 0x0 PLL_TICK_NUM 0 8 SYSCLK_CONF APB_CTRL_SYSCLK_CONF 0x0 32 read-write n 0x0 0x0 CLK_320M_EN 10 1 CLK_EN 11 1 PRE_DIV_CNT 0 10 QUICK_CLK_CHNG 13 1 RST_TICK_CNT 12 1 XTAL_TICK_CONF APB_CTRL_XTAL_TICK_CONF 0x4 32 read-write n 0x0 0x0 XTAL_TICK_NUM 0 8 BB BB 0x0 0x0 0x0 registers n BT BT 0x0 0x0 0x0 registers n BT_BB BT_BB 0x0 BT_BB_INTR interrupt of BT BB, level 4 BT_BB_NMI interrupt of BT BB, NMI, use if BB have bug to fix in NMI 5 BT_MAC BT_MAC 0x0 BT_MAC_INTR will be cancelled 3 CAN CAN 0x0 0x0 0x0 registers n CAN_INTR interrupt of can, level 45 DPORT DPORT 0x0 0x0 0x2DE0 registers n ACCESS_CHECK DPORT_ACCESS_CHECK 0x8 32 read-write n 0x0 0x0 ACCESS_CHECK_APP 8 1 ACCESS_CHECK_PRO 0 1 AHBLITE_MPU_TABLE_APB_CTRL DPORT_AHBLITE_MPU_TABLE_APB_CTRL 0x3B0 32 read-write n 0x0 0x0 APBCTRL_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_BB DPORT_AHBLITE_MPU_TABLE_BB 0x398 32 read-write n 0x0 0x0 BB_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_BT DPORT_AHBLITE_MPU_TABLE_BT 0x36C 32 read-write n 0x0 0x0 BT_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_BTMAC DPORT_AHBLITE_MPU_TABLE_BTMAC 0x3DC 32 read-write n 0x0 0x0 BTMAC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_BT_BUFFER DPORT_AHBLITE_MPU_TABLE_BT_BUFFER 0x370 32 read-write n 0x0 0x0 BTBUFFER_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_CAN DPORT_AHBLITE_MPU_TABLE_CAN 0x3C0 32 read-write n 0x0 0x0 CAN_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_EFUSE DPORT_AHBLITE_MPU_TABLE_EFUSE 0x390 32 read-write n 0x0 0x0 EFUSE_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_EMAC DPORT_AHBLITE_MPU_TABLE_EMAC 0x3BC 32 read-write n 0x0 0x0 EMAC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_FE DPORT_AHBLITE_MPU_TABLE_FE 0x340 32 read-write n 0x0 0x0 FE_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_FE2 DPORT_AHBLITE_MPU_TABLE_FE2 0x33C 32 read-write n 0x0 0x0 FE2_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_GPIO DPORT_AHBLITE_MPU_TABLE_GPIO 0x338 32 read-write n 0x0 0x0 GPIO_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_HINF DPORT_AHBLITE_MPU_TABLE_HINF 0x354 32 read-write n 0x0 0x0 HINF_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_I2C DPORT_AHBLITE_MPU_TABLE_I2C 0x360 32 read-write n 0x0 0x0 I2C_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_I2C_EXT0 DPORT_AHBLITE_MPU_TABLE_I2C_EXT0 0x374 32 read-write n 0x0 0x0 I2CEXT0_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_I2C_EXT1 DPORT_AHBLITE_MPU_TABLE_I2C_EXT1 0x3B4 32 read-write n 0x0 0x0 I2CEXT1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_I2S0 DPORT_AHBLITE_MPU_TABLE_I2S0 0x364 32 read-write n 0x0 0x0 I2S0_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_I2S1 DPORT_AHBLITE_MPU_TABLE_I2S1 0x3C8 32 read-write n 0x0 0x0 I2S1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_IO_MUX DPORT_AHBLITE_MPU_TABLE_IO_MUX 0x34C 32 read-write n 0x0 0x0 IOMUX_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_LEDC DPORT_AHBLITE_MPU_TABLE_LEDC 0x38C 32 read-write n 0x0 0x0 LEDC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_MISC DPORT_AHBLITE_MPU_TABLE_MISC 0x35C 32 read-write n 0x0 0x0 MISC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PCNT DPORT_AHBLITE_MPU_TABLE_PCNT 0x384 32 read-write n 0x0 0x0 PCNT_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PWM0 DPORT_AHBLITE_MPU_TABLE_PWM0 0x39C 32 read-write n 0x0 0x0 PWM0_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PWM1 DPORT_AHBLITE_MPU_TABLE_PWM1 0x3C4 32 read-write n 0x0 0x0 PWM1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PWM2 DPORT_AHBLITE_MPU_TABLE_PWM2 0x3D0 32 read-write n 0x0 0x0 PWM2_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PWM3 DPORT_AHBLITE_MPU_TABLE_PWM3 0x3D4 32 read-write n 0x0 0x0 PWM3_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_PWR DPORT_AHBLITE_MPU_TABLE_PWR 0x3E4 32 read-write n 0x0 0x0 PWR_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_RMT DPORT_AHBLITE_MPU_TABLE_RMT 0x380 32 read-write n 0x0 0x0 RMT_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_RTC DPORT_AHBLITE_MPU_TABLE_RTC 0x348 32 read-write n 0x0 0x0 RTC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_RWBT DPORT_AHBLITE_MPU_TABLE_RWBT 0x3D8 32 read-write n 0x0 0x0 RWBT_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SDIO_HOST DPORT_AHBLITE_MPU_TABLE_SDIO_HOST 0x3B8 32 read-write n 0x0 0x0 SDIOHOST_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SLC DPORT_AHBLITE_MPU_TABLE_SLC 0x388 32 read-write n 0x0 0x0 SLC_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SLCHOST DPORT_AHBLITE_MPU_TABLE_SLCHOST 0x37C 32 read-write n 0x0 0x0 SLCHOST_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SPI0 DPORT_AHBLITE_MPU_TABLE_SPI0 0x334 32 read-write n 0x0 0x0 SPI0_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SPI1 DPORT_AHBLITE_MPU_TABLE_SPI1 0x330 32 read-write n 0x0 0x0 SPI1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SPI2 DPORT_AHBLITE_MPU_TABLE_SPI2 0x3A8 32 read-write n 0x0 0x0 SPI2_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SPI3 DPORT_AHBLITE_MPU_TABLE_SPI3 0x3AC 32 read-write n 0x0 0x0 SPI3_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_SPI_ENCRYPT DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT 0x394 32 read-write n 0x0 0x0 SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_TIMER DPORT_AHBLITE_MPU_TABLE_TIMER 0x344 32 read-write n 0x0 0x0 TIMER_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_TIMERGROUP DPORT_AHBLITE_MPU_TABLE_TIMERGROUP 0x3A0 32 read-write n 0x0 0x0 TIMERGROUP_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_TIMERGROUP1 DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1 0x3A4 32 read-write n 0x0 0x0 TIMERGROUP1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_UART DPORT_AHBLITE_MPU_TABLE_UART 0x32C 32 read-write n 0x0 0x0 UART_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_UART1 DPORT_AHBLITE_MPU_TABLE_UART1 0x368 32 read-write n 0x0 0x0 UART1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_UART2 DPORT_AHBLITE_MPU_TABLE_UART2 0x3CC 32 read-write n 0x0 0x0 UART2_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_UHCI0 DPORT_AHBLITE_MPU_TABLE_UHCI0 0x378 32 read-write n 0x0 0x0 UHCI0_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_UHCI1 DPORT_AHBLITE_MPU_TABLE_UHCI1 0x358 32 read-write n 0x0 0x0 UHCI1_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_WDG DPORT_AHBLITE_MPU_TABLE_WDG 0x350 32 read-write n 0x0 0x0 WDG_ACCESS_GRANT_CONFIG 0 6 AHBLITE_MPU_TABLE_WIFIMAC DPORT_AHBLITE_MPU_TABLE_WIFIMAC 0x3E0 32 read-write n 0x0 0x0 WIFIMAC_ACCESS_GRANT_CONFIG 0 6 AHB_LITE_MASK DPORT_AHB_LITE_MASK 0xB0 32 read-write n 0x0 0x0 AHB_LITE_MASK_APP 4 1 AHB_LITE_MASK_APPDPORT 10 1 AHB_LITE_MASK_PRO 0 1 AHB_LITE_MASK_PRODPORT 9 1 AHB_LITE_MASK_SDIO 8 1 AHB_LITE_SDHOST_PID_REG 11 3 AHB_MPU_TABLE_0 DPORT_AHB_MPU_TABLE_0 0xB4 32 read-write n 0x0 0x0 AHB_ACCESS_GRANT_0 0 32 AHB_MPU_TABLE_1 DPORT_AHB_MPU_TABLE_1 0xB8 32 read-write n 0x0 0x0 AHB_ACCESS_GRANT_1 0 9 APPCPU_CTRL_A DPORT_APPCPU_CTRL_A 0x2C 32 read-write n 0x0 0x0 APPCPU_RESETTING 0 1 APPCPU_CTRL_B DPORT_APPCPU_CTRL_B 0x30 32 read-write n 0x0 0x0 APPCPU_CLKGATE_EN 0 1 APPCPU_CTRL_C DPORT_APPCPU_CTRL_C 0x34 32 read-write n 0x0 0x0 APPCPU_RUNSTALL 0 1 APPCPU_CTRL_D DPORT_APPCPU_CTRL_D 0x38 32 read-write n 0x0 0x0 APPCPU_BOOT_ADDR 0 32 APP_BB_INT_MAP DPORT_APP_BB_INT_MAP 0x220 32 read-write n 0x0 0x0 APP_BB_INT_MAP 0 5 APP_BOOT_REMAP_CTRL DPORT_APP_BOOT_REMAP_CTRL 0x4 32 read-write n 0x0 0x0 APP_BOOT_REMAP 0 1 APP_BT_BB_INT_MAP DPORT_APP_BT_BB_INT_MAP 0x228 32 read-write n 0x0 0x0 APP_BT_BB_INT_MAP 0 5 APP_BT_BB_NMI_MAP DPORT_APP_BT_BB_NMI_MAP 0x22C 32 read-write n 0x0 0x0 APP_BT_BB_NMI_MAP 0 5 APP_BT_MAC_INT_MAP DPORT_APP_BT_MAC_INT_MAP 0x224 32 read-write n 0x0 0x0 APP_BT_MAC_INT_MAP 0 5 APP_CACHE_CTRL DPORT_APP_CACHE_CTRL 0x58 32 read-write n 0x0 0x0 APP_AHB_SPI_REQ 12 1 APP_CACHE_ENABLE 3 1 APP_CACHE_FLUSH_DONE 5 1 APP_CACHE_FLUSH_ENA 4 1 APP_CACHE_LOCK_0_EN 6 1 APP_CACHE_LOCK_1_EN 7 1 APP_CACHE_LOCK_2_EN 8 1 APP_CACHE_LOCK_3_EN 9 1 APP_CACHE_MODE 2 1 APP_DRAM_HL 14 1 APP_DRAM_SPLIT 11 1 APP_SINGLE_IRAM_ENA 10 1 APP_SLAVE_REQ 13 1 APP_CACHE_CTRL1 DPORT_APP_CACHE_CTRL1 0x5C 32 read-write n 0x0 0x0 APP_CACHE_MASK_DRAM1 3 1 APP_CACHE_MASK_DROM0 4 1 APP_CACHE_MASK_IRAM0 0 1 APP_CACHE_MASK_IRAM1 1 1 APP_CACHE_MASK_IROM0 2 1 APP_CACHE_MASK_OPSDRAM 5 1 APP_CACHE_MMU_IA_CLR 13 1 APP_CMMU_FLASH_PAGE_MODE 9 2 APP_CMMU_FORCE_ON 11 1 APP_CMMU_PD 12 1 APP_CMMU_SRAM_PAGE_MODE 6 3 APP_CACHE_IA_INT_MAP DPORT_APP_CACHE_IA_INT_MAP 0x328 32 read-write n 0x0 0x0 APP_CACHE_IA_INT_MAP 0 5 APP_CACHE_LOCK_0_ADDR DPORT_APP_CACHE_LOCK_0_ADDR 0x60 32 read-write n 0x0 0x0 APP_CACHE_LOCK_0_ADDR_MAX 18 4 APP_CACHE_LOCK_0_ADDR_MIN 14 4 APP_CACHE_LOCK_0_ADDR_PRE 0 14 APP_CACHE_LOCK_1_ADDR DPORT_APP_CACHE_LOCK_1_ADDR 0x64 32 read-write n 0x0 0x0 APP_CACHE_LOCK_1_ADDR_MAX 18 4 APP_CACHE_LOCK_1_ADDR_MIN 14 4 APP_CACHE_LOCK_1_ADDR_PRE 0 14 APP_CACHE_LOCK_2_ADDR DPORT_APP_CACHE_LOCK_2_ADDR 0x68 32 read-write n 0x0 0x0 APP_CACHE_LOCK_2_ADDR_MAX 18 4 APP_CACHE_LOCK_2_ADDR_MIN 14 4 APP_CACHE_LOCK_2_ADDR_PRE 0 14 APP_CACHE_LOCK_3_ADDR DPORT_APP_CACHE_LOCK_3_ADDR 0x6C 32 read-write n 0x0 0x0 APP_CACHE_LOCK_3_ADDR_MAX 18 4 APP_CACHE_LOCK_3_ADDR_MIN 14 4 APP_CACHE_LOCK_3_ADDR_PRE 0 14 APP_CAN_INT_MAP DPORT_APP_CAN_INT_MAP 0x2CC 32 read-write n 0x0 0x0 APP_CAN_INT_MAP 0 5 APP_CPU_INTR_FROM_CPU_0_MAP DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x278 32 read-write n 0x0 0x0 APP_CPU_INTR_FROM_CPU_0_MAP 0 5 APP_CPU_INTR_FROM_CPU_1_MAP DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x27C 32 read-write n 0x0 0x0 APP_CPU_INTR_FROM_CPU_1_MAP 0 5 APP_CPU_INTR_FROM_CPU_2_MAP DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x280 32 read-write n 0x0 0x0 APP_CPU_INTR_FROM_CPU_2_MAP 0 5 APP_CPU_INTR_FROM_CPU_3_MAP DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x284 32 read-write n 0x0 0x0 APP_CPU_INTR_FROM_CPU_3_MAP 0 5 APP_CPU_RECORD_CTRL DPORT_APP_CPU_RECORD_CTRL 0x468 32 read-write n 0x0 0x0 APP_CPU_PDEBUG_ENABLE 8 1 APP_CPU_RECORD_DISABLE 4 1 APP_CPU_RECORD_ENABLE 0 1 APP_CPU_RECORD_PDEBUGDATA DPORT_APP_CPU_RECORD_PDEBUGDATA 0x47C 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGDATA 0 32 APP_CPU_RECORD_PDEBUGINST DPORT_APP_CPU_RECORD_PDEBUGINST 0x474 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGINST 0 32 APP_CPU_RECORD_PDEBUGLS0ADDR DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR 0x488 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGLS0ADDR 0 32 APP_CPU_RECORD_PDEBUGLS0DATA DPORT_APP_CPU_RECORD_PDEBUGLS0DATA 0x48C 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGLS0DATA 0 32 APP_CPU_RECORD_PDEBUGLS0STAT DPORT_APP_CPU_RECORD_PDEBUGLS0STAT 0x484 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGLS0STAT 0 32 APP_CPU_RECORD_PDEBUGPC DPORT_APP_CPU_RECORD_PDEBUGPC 0x480 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGPC 0 32 APP_CPU_RECORD_PDEBUGSTATUS DPORT_APP_CPU_RECORD_PDEBUGSTATUS 0x478 32 read-write n 0x0 0x0 RECORD_APP_PDEBUGSTATUS 0 8 APP_CPU_RECORD_PID DPORT_APP_CPU_RECORD_PID 0x470 32 read-write n 0x0 0x0 RECORD_APP_PID 0 3 APP_CPU_RECORD_STATUS DPORT_APP_CPU_RECORD_STATUS 0x46C 32 read-write n 0x0 0x0 APP_CPU_RECORDING 0 1 APP_DCACHE_DBUG0 DPORT_APP_DCACHE_DBUG0 0x418 32 read-write n 0x0 0x0 APP_CACHE_IA 1 6 APP_CACHE_MMU_IA 0 1 APP_CACHE_STATE 7 12 APP_RX_END 23 1 APP_SLAVE_WDATA_V 22 1 APP_SLAVE_WR 21 1 APP_TX_END 20 1 APP_WR_BAK_TO_READ 19 1 APP_DCACHE_DBUG1 DPORT_APP_DCACHE_DBUG1 0x41C 32 read-write n 0x0 0x0 APP_CTAG_RAM_RDATA 0 32 APP_DCACHE_DBUG2 DPORT_APP_DCACHE_DBUG2 0x420 32 read-write n 0x0 0x0 APP_CACHE_VADDR 0 27 APP_DCACHE_DBUG3 DPORT_APP_DCACHE_DBUG3 0x424 32 read-write n 0x0 0x0 APP_CACHE_IRAM0_PID_ERROR 15 1 APP_CPU_DISABLED_CACHE_IA 9 6 APP_DCACHE_DBUG4 DPORT_APP_DCACHE_DBUG4 0x428 32 read-write n 0x0 0x0 APP_DRAM1ADDR0_IA 0 20 APP_DCACHE_DBUG5 DPORT_APP_DCACHE_DBUG5 0x42C 32 read-write n 0x0 0x0 APP_DROM0ADDR0_IA 0 20 APP_DCACHE_DBUG6 DPORT_APP_DCACHE_DBUG6 0x430 32 read-write n 0x0 0x0 APP_IRAM0ADDR_IA 0 20 APP_DCACHE_DBUG7 DPORT_APP_DCACHE_DBUG7 0x434 32 read-write n 0x0 0x0 APP_IRAM1ADDR_IA 0 20 APP_DCACHE_DBUG8 DPORT_APP_DCACHE_DBUG8 0x438 32 read-write n 0x0 0x0 APP_IROM0ADDR_IA 0 20 APP_DCACHE_DBUG9 DPORT_APP_DCACHE_DBUG9 0x43C 32 read-write n 0x0 0x0 APP_OPSDRAMADDR_IA 0 20 APP_DPORT_APB_MASK0 DPORT_APP_DPORT_APB_MASK0 0x14 32 read-write n 0x0 0x0 APPDPORT_APB_MASK0 0 32 APP_DPORT_APB_MASK1 DPORT_APP_DPORT_APB_MASK1 0x18 32 read-write n 0x0 0x0 APPDPORT_APB_MASK1 0 32 APP_EFUSE_INT_MAP DPORT_APP_EFUSE_INT_MAP 0x2C8 32 read-write n 0x0 0x0 APP_EFUSE_INT_MAP 0 5 APP_EMAC_INT_MAP DPORT_APP_EMAC_INT_MAP 0x2B0 32 read-write n 0x0 0x0 APP_EMAC_INT_MAP 0 5 APP_GPIO_INTERRUPT_MAP DPORT_APP_GPIO_INTERRUPT_MAP 0x270 32 read-write n 0x0 0x0 APP_GPIO_INTERRUPT_APP_MAP 0 5 APP_GPIO_INTERRUPT_NMI_MAP DPORT_APP_GPIO_INTERRUPT_NMI_MAP 0x274 32 read-write n 0x0 0x0 APP_GPIO_INTERRUPT_APP_NMI_MAP 0 5 APP_I2C_EXT0_INTR_MAP DPORT_APP_I2C_EXT0_INTR_MAP 0x2DC 32 read-write n 0x0 0x0 APP_I2C_EXT0_INTR_MAP 0 5 APP_I2C_EXT1_INTR_MAP DPORT_APP_I2C_EXT1_INTR_MAP 0x2E0 32 read-write n 0x0 0x0 APP_I2C_EXT1_INTR_MAP 0 5 APP_I2S0_INT_MAP DPORT_APP_I2S0_INT_MAP 0x298 32 read-write n 0x0 0x0 APP_I2S0_INT_MAP 0 5 APP_I2S1_INT_MAP DPORT_APP_I2S1_INT_MAP 0x29C 32 read-write n 0x0 0x0 APP_I2S1_INT_MAP 0 5 APP_INTRUSION_CTRL DPORT_APP_INTRUSION_CTRL 0x58C 32 read-write n 0x0 0x0 APP_INTRUSION_RECORD_RESET_N 0 1 APP_INTRUSION_STATUS DPORT_APP_INTRUSION_STATUS 0x590 32 read-write n 0x0 0x0 APP_INTRUSION_RECORD 0 4 APP_INTR_STATUS_0 DPORT_APP_INTR_STATUS_0 0xF8 32 read-write n 0x0 0x0 APP_INTR_STATUS_0 0 32 APP_INTR_STATUS_1 DPORT_APP_INTR_STATUS_1 0xFC 32 read-write n 0x0 0x0 APP_INTR_STATUS_1 0 32 APP_INTR_STATUS_2 DPORT_APP_INTR_STATUS_2 0x100 32 read-write n 0x0 0x0 APP_INTR_STATUS_2 0 32 APP_LEDC_INT_MAP DPORT_APP_LEDC_INT_MAP 0x2C4 32 read-write n 0x0 0x0 APP_LEDC_INT_MAP 0 5 APP_MAC_INTR_MAP DPORT_APP_MAC_INTR_MAP 0x218 32 read-write n 0x0 0x0 APP_MAC_INTR_MAP 0 5 APP_MAC_NMI_MAP DPORT_APP_MAC_NMI_MAP 0x21C 32 read-write n 0x0 0x0 APP_MAC_NMI_MAP 0 5 APP_MMU_IA_INT_MAP DPORT_APP_MMU_IA_INT_MAP 0x320 32 read-write n 0x0 0x0 APP_MMU_IA_INT_MAP 0 5 APP_MPU_IA_INT_MAP DPORT_APP_MPU_IA_INT_MAP 0x324 32 read-write n 0x0 0x0 APP_MPU_IA_INT_MAP 0 5 APP_PCNT_INTR_MAP DPORT_APP_PCNT_INTR_MAP 0x2D8 32 read-write n 0x0 0x0 APP_PCNT_INTR_MAP 0 5 APP_PWM0_INTR_MAP DPORT_APP_PWM0_INTR_MAP 0x2B4 32 read-write n 0x0 0x0 APP_PWM0_INTR_MAP 0 5 APP_PWM1_INTR_MAP DPORT_APP_PWM1_INTR_MAP 0x2B8 32 read-write n 0x0 0x0 APP_PWM1_INTR_MAP 0 5 APP_PWM2_INTR_MAP DPORT_APP_PWM2_INTR_MAP 0x2BC 32 read-write n 0x0 0x0 APP_PWM2_INTR_MAP 0 5 APP_PWM3_INTR_MAP DPORT_APP_PWM3_INTR_MAP 0x2C0 32 read-write n 0x0 0x0 APP_PWM3_INTR_MAP 0 5 APP_RMT_INTR_MAP DPORT_APP_RMT_INTR_MAP 0x2D4 32 read-write n 0x0 0x0 APP_RMT_INTR_MAP 0 5 APP_RSA_INTR_MAP DPORT_APP_RSA_INTR_MAP 0x2E4 32 read-write n 0x0 0x0 APP_RSA_INTR_MAP 0 5 APP_RTC_CORE_INTR_MAP DPORT_APP_RTC_CORE_INTR_MAP 0x2D0 32 read-write n 0x0 0x0 APP_RTC_CORE_INTR_MAP 0 5 APP_RWBLE_IRQ_MAP DPORT_APP_RWBLE_IRQ_MAP 0x234 32 read-write n 0x0 0x0 APP_RWBLE_IRQ_MAP 0 5 APP_RWBLE_NMI_MAP DPORT_APP_RWBLE_NMI_MAP 0x23C 32 read-write n 0x0 0x0 APP_RWBLE_NMI_MAP 0 5 APP_RWBT_IRQ_MAP DPORT_APP_RWBT_IRQ_MAP 0x230 32 read-write n 0x0 0x0 APP_RWBT_IRQ_MAP 0 5 APP_RWBT_NMI_MAP DPORT_APP_RWBT_NMI_MAP 0x238 32 read-write n 0x0 0x0 APP_RWBT_NMI_MAP 0 5 APP_SDIO_HOST_INTERRUPT_MAP DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x2AC 32 read-write n 0x0 0x0 APP_SDIO_HOST_INTERRUPT_MAP 0 5 APP_SLC0_INTR_MAP DPORT_APP_SLC0_INTR_MAP 0x240 32 read-write n 0x0 0x0 APP_SLC0_INTR_MAP 0 5 APP_SLC1_INTR_MAP DPORT_APP_SLC1_INTR_MAP 0x244 32 read-write n 0x0 0x0 APP_SLC1_INTR_MAP 0 5 APP_SPI1_DMA_INT_MAP DPORT_APP_SPI1_DMA_INT_MAP 0x2E8 32 read-write n 0x0 0x0 APP_SPI1_DMA_INT_MAP 0 5 APP_SPI2_DMA_INT_MAP DPORT_APP_SPI2_DMA_INT_MAP 0x2EC 32 read-write n 0x0 0x0 APP_SPI2_DMA_INT_MAP 0 5 APP_SPI3_DMA_INT_MAP DPORT_APP_SPI3_DMA_INT_MAP 0x2F0 32 read-write n 0x0 0x0 APP_SPI3_DMA_INT_MAP 0 5 APP_SPI_INTR_0_MAP DPORT_APP_SPI_INTR_0_MAP 0x288 32 read-write n 0x0 0x0 APP_SPI_INTR_0_MAP 0 5 APP_SPI_INTR_1_MAP DPORT_APP_SPI_INTR_1_MAP 0x28C 32 read-write n 0x0 0x0 APP_SPI_INTR_1_MAP 0 5 APP_SPI_INTR_2_MAP DPORT_APP_SPI_INTR_2_MAP 0x290 32 read-write n 0x0 0x0 APP_SPI_INTR_2_MAP 0 5 APP_SPI_INTR_3_MAP DPORT_APP_SPI_INTR_3_MAP 0x294 32 read-write n 0x0 0x0 APP_SPI_INTR_3_MAP 0 5 APP_TG1_LACT_EDGE_INT_MAP DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x31C 32 read-write n 0x0 0x0 APP_TG1_LACT_EDGE_INT_MAP 0 5 APP_TG1_LACT_LEVEL_INT_MAP DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x26C 32 read-write n 0x0 0x0 APP_TG1_LACT_LEVEL_INT_MAP 0 5 APP_TG1_T0_EDGE_INT_MAP DPORT_APP_TG1_T0_EDGE_INT_MAP 0x310 32 read-write n 0x0 0x0 APP_TG1_T0_EDGE_INT_MAP 0 5 APP_TG1_T0_LEVEL_INT_MAP DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x260 32 read-write n 0x0 0x0 APP_TG1_T0_LEVEL_INT_MAP 0 5 APP_TG1_T1_EDGE_INT_MAP DPORT_APP_TG1_T1_EDGE_INT_MAP 0x314 32 read-write n 0x0 0x0 APP_TG1_T1_EDGE_INT_MAP 0 5 APP_TG1_T1_LEVEL_INT_MAP DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x264 32 read-write n 0x0 0x0 APP_TG1_T1_LEVEL_INT_MAP 0 5 APP_TG1_WDT_EDGE_INT_MAP DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x318 32 read-write n 0x0 0x0 APP_TG1_WDT_EDGE_INT_MAP 0 5 APP_TG1_WDT_LEVEL_INT_MAP DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x268 32 read-write n 0x0 0x0 APP_TG1_WDT_LEVEL_INT_MAP 0 5 APP_TG_LACT_EDGE_INT_MAP DPORT_APP_TG_LACT_EDGE_INT_MAP 0x30C 32 read-write n 0x0 0x0 APP_TG_LACT_EDGE_INT_MAP 0 5 APP_TG_LACT_LEVEL_INT_MAP DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x25C 32 read-write n 0x0 0x0 APP_TG_LACT_LEVEL_INT_MAP 0 5 APP_TG_T0_EDGE_INT_MAP DPORT_APP_TG_T0_EDGE_INT_MAP 0x300 32 read-write n 0x0 0x0 APP_TG_T0_EDGE_INT_MAP 0 5 APP_TG_T0_LEVEL_INT_MAP DPORT_APP_TG_T0_LEVEL_INT_MAP 0x250 32 read-write n 0x0 0x0 APP_TG_T0_LEVEL_INT_MAP 0 5 APP_TG_T1_EDGE_INT_MAP DPORT_APP_TG_T1_EDGE_INT_MAP 0x304 32 read-write n 0x0 0x0 APP_TG_T1_EDGE_INT_MAP 0 5 APP_TG_T1_LEVEL_INT_MAP DPORT_APP_TG_T1_LEVEL_INT_MAP 0x254 32 read-write n 0x0 0x0 APP_TG_T1_LEVEL_INT_MAP 0 5 APP_TG_WDT_EDGE_INT_MAP DPORT_APP_TG_WDT_EDGE_INT_MAP 0x308 32 read-write n 0x0 0x0 APP_TG_WDT_EDGE_INT_MAP 0 5 APP_TG_WDT_LEVEL_INT_MAP DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x258 32 read-write n 0x0 0x0 APP_TG_WDT_LEVEL_INT_MAP 0 5 APP_TIMER_INT1_MAP DPORT_APP_TIMER_INT1_MAP 0x2F8 32 read-write n 0x0 0x0 APP_TIMER_INT1_MAP 0 5 APP_TIMER_INT2_MAP DPORT_APP_TIMER_INT2_MAP 0x2FC 32 read-write n 0x0 0x0 APP_TIMER_INT2_MAP 0 5 APP_TRACEMEM_ENA DPORT_APP_TRACEMEM_ENA 0x78 32 read-write n 0x0 0x0 APP_TRACEMEM_ENA 0 1 APP_UART1_INTR_MAP DPORT_APP_UART1_INTR_MAP 0x2A4 32 read-write n 0x0 0x0 APP_UART1_INTR_MAP 0 5 APP_UART2_INTR_MAP DPORT_APP_UART2_INTR_MAP 0x2A8 32 read-write n 0x0 0x0 APP_UART2_INTR_MAP 0 5 APP_UART_INTR_MAP DPORT_APP_UART_INTR_MAP 0x2A0 32 read-write n 0x0 0x0 APP_UART_INTR_MAP 0 5 APP_UHCI0_INTR_MAP DPORT_APP_UHCI0_INTR_MAP 0x248 32 read-write n 0x0 0x0 APP_UHCI0_INTR_MAP 0 5 APP_UHCI1_INTR_MAP DPORT_APP_UHCI1_INTR_MAP 0x24C 32 read-write n 0x0 0x0 APP_UHCI1_INTR_MAP 0 5 APP_VECBASE_CTRL DPORT_APP_VECBASE_CTRL 0x5B4 32 read-write n 0x0 0x0 APP_OUT_VECBASE_SEL 0 2 APP_VECBASE_SET DPORT_APP_VECBASE_SET 0x5B8 32 read-write n 0x0 0x0 APP_OUT_VECBASE_REG 0 22 APP_WDG_INT_MAP DPORT_APP_WDG_INT_MAP 0x2F4 32 read-write n 0x0 0x0 APP_WDG_INT_MAP 0 5 BT_LPCK_DIV_FRAC DPORT_BT_LPCK_DIV_FRAC 0xD8 32 read-write n 0x0 0x0 BT_LPCK_DIV_A 12 12 BT_LPCK_DIV_B 0 12 LPCLK_SEL_8M 25 1 LPCLK_SEL_RTC_SLOW 24 1 LPCLK_SEL_XTAL 26 1 LPCLK_SEL_XTAL32K 27 1 BT_LPCK_DIV_INT DPORT_BT_LPCK_DIV_INT 0xD4 32 read-write n 0x0 0x0 BTEXTWAKEUP_REQ 12 1 BT_LPCK_DIV_NUM 0 12 CACHE_IA_INT_EN DPORT_CACHE_IA_INT_EN 0x5A0 32 read-write n 0x0 0x0 CACHE_IA_INT_APP_DROM0 0 1 CACHE_IA_INT_APP_IRAM0 1 1 CACHE_IA_INT_APP_IRAM1 2 1 CACHE_IA_INT_APP_IROM0 3 1 CACHE_IA_INT_APP_OPPOSITE 5 1 CACHE_IA_INT_EN 0 28 CACHE_IA_INT_PRO_DRAM1 18 1 CACHE_IA_INT_PRO_DROM0 14 1 CACHE_IA_INT_PRO_IRAM0 15 1 CACHE_IA_INT_PRO_IRAM1 16 1 CACHE_IA_INT_PRO_IROM0 17 1 CACHE_IA_INT_PRO_OPPOSITE 19 1 CACHE_MUX_MODE DPORT_CACHE_MUX_MODE 0x7C 32 read-write n 0x0 0x0 CACHE_MUX_MODE 0 2 CORE_RST_EN DPORT_CORE_RST_EN 0xD0 32 read-write n 0x0 0x0 CORE_RST 0 32 CPU_INTR_FROM_CPU_0 DPORT_CPU_INTR_FROM_CPU_0 0xDC 32 read-write n 0x0 0x0 CPU_INTR_FROM_CPU_0 0 1 CPU_INTR_FROM_CPU_1 DPORT_CPU_INTR_FROM_CPU_1 0xE0 32 read-write n 0x0 0x0 CPU_INTR_FROM_CPU_1 0 1 CPU_INTR_FROM_CPU_2 DPORT_CPU_INTR_FROM_CPU_2 0xE4 32 read-write n 0x0 0x0 CPU_INTR_FROM_CPU_2 0 1 CPU_INTR_FROM_CPU_3 DPORT_CPU_INTR_FROM_CPU_3 0xE8 32 read-write n 0x0 0x0 CPU_INTR_FROM_CPU_3 0 1 CPU_PER_CONF DPORT_CPU_PER_CONF 0x3C 32 read-write n 0x0 0x0 CPUPERIOD_SEL 0 2 CPUPERIOD_SEL read-write SEL_80 Select 80 MHz clock 0 SEL_160 Select 160 MHz clock 1 SEL_240 Select 240 MHz clock 2 FAST_CLK_RTC_SEL 3 1 LOWSPEED_CLK_SEL 2 1 DATE DPORT_DATE 0xFFC 32 read-write n 0x0 0x0 DATE 0 28 DMMU_PAGE_MODE DPORT_DMMU_PAGE_MODE 0x84 32 read-write n 0x0 0x0 DMMU_PAGE_MODE 1 2 INTERNAL_SRAM_DMMU_ENA 0 1 DMMU_TABLE0 DPORT_DMMU_TABLE0 0x544 32 read-write n 0x0 0x0 DMMU_TABLE0 0 7 DMMU_TABLE1 DPORT_DMMU_TABLE1 0x548 32 read-write n 0x0 0x0 DMMU_TABLE1 0 7 DMMU_TABLE10 DPORT_DMMU_TABLE10 0x56C 32 read-write n 0x0 0x0 DMMU_TABLE10 0 7 DMMU_TABLE11 DPORT_DMMU_TABLE11 0x570 32 read-write n 0x0 0x0 DMMU_TABLE11 0 7 DMMU_TABLE12 DPORT_DMMU_TABLE12 0x574 32 read-write n 0x0 0x0 DMMU_TABLE12 0 7 DMMU_TABLE13 DPORT_DMMU_TABLE13 0x578 32 read-write n 0x0 0x0 DMMU_TABLE13 0 7 DMMU_TABLE14 DPORT_DMMU_TABLE14 0x57C 32 read-write n 0x0 0x0 DMMU_TABLE14 0 7 DMMU_TABLE15 DPORT_DMMU_TABLE15 0x580 32 read-write n 0x0 0x0 DMMU_TABLE15 0 7 DMMU_TABLE2 DPORT_DMMU_TABLE2 0x54C 32 read-write n 0x0 0x0 DMMU_TABLE2 0 7 DMMU_TABLE3 DPORT_DMMU_TABLE3 0x550 32 read-write n 0x0 0x0 DMMU_TABLE3 0 7 DMMU_TABLE4 DPORT_DMMU_TABLE4 0x554 32 read-write n 0x0 0x0 DMMU_TABLE4 0 7 DMMU_TABLE5 DPORT_DMMU_TABLE5 0x558 32 read-write n 0x0 0x0 DMMU_TABLE5 0 7 DMMU_TABLE6 DPORT_DMMU_TABLE6 0x55C 32 read-write n 0x0 0x0 DMMU_TABLE6 0 7 DMMU_TABLE7 DPORT_DMMU_TABLE7 0x560 32 read-write n 0x0 0x0 DMMU_TABLE7 0 7 DMMU_TABLE8 DPORT_DMMU_TABLE8 0x564 32 read-write n 0x0 0x0 DMMU_TABLE8 0 7 DMMU_TABLE9 DPORT_DMMU_TABLE9 0x568 32 read-write n 0x0 0x0 DMMU_TABLE9 0 7 FRONT_END_MEM_PD DPORT_FRONT_END_MEM_PD 0x594 32 read-write n 0x0 0x0 AGC_MEM_FORCE_PD 1 1 AGC_MEM_FORCE_PU 0 1 PBUS_MEM_FORCE_PD 3 1 PBUS_MEM_FORCE_PU 2 1 HOST_INF_SEL DPORT_HOST_INF_SEL 0xBC 32 read-write n 0x0 0x0 LINK_DEVICE_SEL 8 8 PERI_IO_SWAP 0 8 IMMU_PAGE_MODE DPORT_IMMU_PAGE_MODE 0x80 32 read-write n 0x0 0x0 IMMU_PAGE_MODE 1 2 INTERNAL_SRAM_IMMU_ENA 0 1 IMMU_TABLE0 DPORT_IMMU_TABLE0 0x504 32 read-write n 0x0 0x0 IMMU_TABLE0 0 7 IMMU_TABLE1 DPORT_IMMU_TABLE1 0x508 32 read-write n 0x0 0x0 IMMU_TABLE1 0 7 IMMU_TABLE10 DPORT_IMMU_TABLE10 0x52C 32 read-write n 0x0 0x0 IMMU_TABLE10 0 7 IMMU_TABLE11 DPORT_IMMU_TABLE11 0x530 32 read-write n 0x0 0x0 IMMU_TABLE11 0 7 IMMU_TABLE12 DPORT_IMMU_TABLE12 0x534 32 read-write n 0x0 0x0 IMMU_TABLE12 0 7 IMMU_TABLE13 DPORT_IMMU_TABLE13 0x538 32 read-write n 0x0 0x0 IMMU_TABLE13 0 7 IMMU_TABLE14 DPORT_IMMU_TABLE14 0x53C 32 read-write n 0x0 0x0 IMMU_TABLE14 0 7 IMMU_TABLE15 DPORT_IMMU_TABLE15 0x540 32 read-write n 0x0 0x0 IMMU_TABLE15 0 7 IMMU_TABLE2 DPORT_IMMU_TABLE2 0x50C 32 read-write n 0x0 0x0 IMMU_TABLE2 0 7 IMMU_TABLE3 DPORT_IMMU_TABLE3 0x510 32 read-write n 0x0 0x0 IMMU_TABLE3 0 7 IMMU_TABLE4 DPORT_IMMU_TABLE4 0x514 32 read-write n 0x0 0x0 IMMU_TABLE4 0 7 IMMU_TABLE5 DPORT_IMMU_TABLE5 0x518 32 read-write n 0x0 0x0 IMMU_TABLE5 0 7 IMMU_TABLE6 DPORT_IMMU_TABLE6 0x51C 32 read-write n 0x0 0x0 IMMU_TABLE6 0 7 IMMU_TABLE7 DPORT_IMMU_TABLE7 0x520 32 read-write n 0x0 0x0 IMMU_TABLE7 0 7 IMMU_TABLE8 DPORT_IMMU_TABLE8 0x524 32 read-write n 0x0 0x0 IMMU_TABLE8 0 7 IMMU_TABLE9 DPORT_IMMU_TABLE9 0x528 32 read-write n 0x0 0x0 IMMU_TABLE9 0 7 IRAM_DRAM_AHB_SEL DPORT_IRAM_DRAM_AHB_SEL 0xA8 32 read-write n 0x0 0x0 MAC_DUMP_MODE 5 2 MASK_AHB 4 1 MASK_APP_DRAM 3 1 MASK_APP_IRAM 1 1 MASK_PRO_DRAM 2 1 MASK_PRO_IRAM 0 1 MEM_ACCESS_DBUG0 DPORT_MEM_ACCESS_DBUG0 0x3E8 32 read-write n 0x0 0x0 APP_ROM_IA 3 1 APP_ROM_MPU_AD 2 1 INTERNAL_SRAM_IA 14 12 INTERNAL_SRAM_MMU_AD 10 4 INTERNAL_SRAM_MMU_MULTI_HIT 26 4 PRO_ROM_IA 1 1 PRO_ROM_MPU_AD 0 1 SHARE_ROM_IA 6 4 SHARE_ROM_MPU_AD 4 2 MEM_ACCESS_DBUG1 DPORT_MEM_ACCESS_DBUG1 0x3EC 32 read-write n 0x0 0x0 AHBLITE_ACCESS_DENY 9 1 AHBLITE_IA 10 1 AHB_ACCESS_DENY 8 1 ARB_IA 4 2 INTERNAL_SRAM_MMU_MISS 0 4 PIDGEN_IA 6 2 MEM_PD_MASK DPORT_MEM_PD_MASK 0x8C 32 read-write n 0x0 0x0 LSLP_MEM_PD_MASK 0 1 MMU_IA_INT_EN DPORT_MMU_IA_INT_EN 0x598 32 read-write n 0x0 0x0 MMU_IA_INT_EN 0 24 MPU_IA_INT_EN DPORT_MPU_IA_INT_EN 0x59C 32 read-write n 0x0 0x0 MPU_IA_INT_EN 0 17 PERIP_CLK_EN DPORT_PERIP_CLK_EN 0xC0 32 read-write n 0x0 0x0 CAN 19 1 EFUSE 14 1 I2C0 7 1 I2C1 18 1 I2S0 4 1 I2S1 21 1 LED_PWM 11 1 PERIP_CLK_EN 0 32 PULSE_CNT 10 1 PWM0 17 1 PWM1 20 1 PWM2 25 1 PWM3 26 1 REMOTE_CONTROLLER 9 1 SPI0 1 1 SPI2 6 1 SPI3 16 1 SPI_DMA 22 1 TIMERS 0 1 TIMER_GROUP0 13 1 TIMER_GROUP1 15 1 UART0 2 1 UART1 5 1 UART2 23 1 UART_MEM 24 1 UHCI0 8 1 UHCI1 12 1 WDG 3 1 PERIP_RST_EN DPORT_PERIP_RST_EN 0xC4 32 read-write n 0x0 0x0 CAN 19 1 EFUSE 14 1 I2C0 7 1 I2C1 18 1 I2S0 4 1 I2S1 21 1 LED_PWM 11 1 PERIP_RST 0 32 PULSE_CNT 10 1 PWM0 17 1 PWM1 20 1 PWM2 25 1 PWM3 26 1 REMOTE_CONTROLLER 9 1 SLAVE_SPI_MASK_APP 4 1 SLAVE_SPI_MASK_PRO 0 1 SPI0 1 1 SPI2 6 1 SPI3 16 1 SPI_DECRYPT_ENABLE 12 1 SPI_DMA 22 1 SPI_ENCRYPT_ENABLE 8 1 TIMERS 0 1 TIMER_GROUP0 13 1 TIMER_GROUP1 15 1 UART0 2 1 UART1 5 1 UART2 23 1 UART_MEM 24 1 UHCI0 8 1 UHCI1 12 1 WDG 3 1 PERI_CLK_EN DPORT_PERI_CLK_EN 0x1C 32 read-write n 0x0 0x0 AES_ACCELERATOR 0 1 DIGITAL_SIGNATURE 4 1 PERI_CLK_EN 0 32 RSA_ACCELERATOR 2 1 SECURE_BOOT 3 1 SHA_ACCELERATOR 1 1 PERI_RST_EN DPORT_PERI_RST_EN 0x20 32 read-write n 0x0 0x0 AES_ACCELERATOR 0 1 DIGITAL_SIGNATURE 4 1 PERI_RST_EN 0 32 RSA_ACCELERATOR 2 1 SECURE_BOOT 3 1 SHA_ACCELERATOR 1 1 PRO_BB_INT_MAP DPORT_PRO_BB_INT_MAP 0x10C 32 read-write n 0x0 0x0 PRO_BB_INT_MAP 0 5 PRO_BOOT_REMAP_CTRL DPORT_PRO_BOOT_REMAP_CTRL 0x0 32 read-write n 0x0 0x0 PRO_BOOT_REMAP 0 1 PRO_BT_BB_INT_MAP DPORT_PRO_BT_BB_INT_MAP 0x114 32 read-write n 0x0 0x0 PRO_BT_BB_INT_MAP 0 5 PRO_BT_BB_NMI_MAP DPORT_PRO_BT_BB_NMI_MAP 0x118 32 read-write n 0x0 0x0 PRO_BT_BB_NMI_MAP 0 5 PRO_BT_MAC_INT_MAP DPORT_PRO_BT_MAC_INT_MAP 0x110 32 read-write n 0x0 0x0 PRO_BT_MAC_INT_MAP 0 5 PRO_CACHE_CTRL DPORT_PRO_CACHE_CTRL 0x40 32 read-write n 0x0 0x0 AHB_SPI_REQ 14 1 PRO_AHB_SPI_REQ 12 1 PRO_CACHE_ENABLE 3 1 PRO_CACHE_FLUSH_DONE 5 1 PRO_CACHE_FLUSH_ENA 4 1 PRO_CACHE_LOCK_0_EN 6 1 PRO_CACHE_LOCK_1_EN 7 1 PRO_CACHE_LOCK_2_EN 8 1 PRO_CACHE_LOCK_3_EN 9 1 PRO_CACHE_MODE 2 1 PRO_DRAM_HL 16 1 PRO_DRAM_SPLIT 11 1 PRO_SINGLE_IRAM_ENA 10 1 PRO_SLAVE_REQ 13 1 SLAVE_REQ 15 1 PRO_CACHE_CTRL1 DPORT_PRO_CACHE_CTRL1 0x44 32 read-write n 0x0 0x0 PRO_CACHE_MASK_DRAM1 3 1 PRO_CACHE_MASK_DROM0 4 1 PRO_CACHE_MASK_IRAM0 0 1 PRO_CACHE_MASK_IRAM1 1 1 PRO_CACHE_MASK_IROM0 2 1 PRO_CACHE_MASK_OPSDRAM 5 1 PRO_CACHE_MMU_IA_CLR 13 1 PRO_CMMU_FLASH_PAGE_MODE 9 2 PRO_CMMU_FORCE_ON 11 1 PRO_CMMU_PD 12 1 PRO_CMMU_SRAM_PAGE_MODE 6 3 PRO_CACHE_IA_INT_MAP DPORT_PRO_CACHE_IA_INT_MAP 0x214 32 read-write n 0x0 0x0 PRO_CACHE_IA_INT_MAP 0 5 PRO_CACHE_LOCK_0_ADDR DPORT_PRO_CACHE_LOCK_0_ADDR 0x48 32 read-write n 0x0 0x0 PRO_CACHE_LOCK_0_ADDR_MAX 18 4 PRO_CACHE_LOCK_0_ADDR_MIN 14 4 PRO_CACHE_LOCK_0_ADDR_PRE 0 14 PRO_CACHE_LOCK_1_ADDR DPORT_PRO_CACHE_LOCK_1_ADDR 0x4C 32 read-write n 0x0 0x0 PRO_CACHE_LOCK_1_ADDR_MAX 18 4 PRO_CACHE_LOCK_1_ADDR_MIN 14 4 PRO_CACHE_LOCK_1_ADDR_PRE 0 14 PRO_CACHE_LOCK_2_ADDR DPORT_PRO_CACHE_LOCK_2_ADDR 0x50 32 read-write n 0x0 0x0 PRO_CACHE_LOCK_2_ADDR_MAX 18 4 PRO_CACHE_LOCK_2_ADDR_MIN 14 4 PRO_CACHE_LOCK_2_ADDR_PRE 0 14 PRO_CACHE_LOCK_3_ADDR DPORT_PRO_CACHE_LOCK_3_ADDR 0x54 32 read-write n 0x0 0x0 PRO_CACHE_LOCK_3_ADDR_MAX 18 4 PRO_CACHE_LOCK_3_ADDR_MIN 14 4 PRO_CACHE_LOCK_3_ADDR_PRE 0 14 PRO_CAN_INT_MAP DPORT_PRO_CAN_INT_MAP 0x1B8 32 read-write n 0x0 0x0 PRO_CAN_INT_MAP 0 5 PRO_CPU_INTR_FROM_CPU_0_MAP DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x164 32 read-write n 0x0 0x0 PRO_CPU_INTR_FROM_CPU_0_MAP 0 5 PRO_CPU_INTR_FROM_CPU_1_MAP DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x168 32 read-write n 0x0 0x0 PRO_CPU_INTR_FROM_CPU_1_MAP 0 5 PRO_CPU_INTR_FROM_CPU_2_MAP DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x16C 32 read-write n 0x0 0x0 PRO_CPU_INTR_FROM_CPU_2_MAP 0 5 PRO_CPU_INTR_FROM_CPU_3_MAP DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x170 32 read-write n 0x0 0x0 PRO_CPU_INTR_FROM_CPU_3_MAP 0 5 PRO_CPU_RECORD_CTRL DPORT_PRO_CPU_RECORD_CTRL 0x440 32 read-write n 0x0 0x0 PRO_CPU_PDEBUG_ENABLE 8 1 PRO_CPU_RECORD_DISABLE 4 1 PRO_CPU_RECORD_ENABLE 0 1 PRO_CPU_RECORD_PDEBUGDATA DPORT_PRO_CPU_RECORD_PDEBUGDATA 0x454 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGDATA 0 32 PRO_CPU_RECORD_PDEBUGINST DPORT_PRO_CPU_RECORD_PDEBUGINST 0x44C 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGINST 0 32 PRO_CPU_RECORD_PDEBUGLS0ADDR DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR 0x460 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGLS0ADDR 0 32 PRO_CPU_RECORD_PDEBUGLS0DATA DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA 0x464 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGLS0DATA 0 32 PRO_CPU_RECORD_PDEBUGLS0STAT DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT 0x45C 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGLS0STAT 0 32 PRO_CPU_RECORD_PDEBUGPC DPORT_PRO_CPU_RECORD_PDEBUGPC 0x458 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGPC 0 32 PRO_CPU_RECORD_PDEBUGSTATUS DPORT_PRO_CPU_RECORD_PDEBUGSTATUS 0x450 32 read-write n 0x0 0x0 RECORD_PRO_PDEBUGSTATUS 0 8 PRO_CPU_RECORD_PID DPORT_PRO_CPU_RECORD_PID 0x448 32 read-write n 0x0 0x0 RECORD_PRO_PID 0 3 PRO_CPU_RECORD_STATUS DPORT_PRO_CPU_RECORD_STATUS 0x444 32 read-write n 0x0 0x0 PRO_CPU_RECORDING 0 1 PRO_DCACHE_DBUG0 DPORT_PRO_DCACHE_DBUG0 0x3F0 32 read-write n 0x0 0x0 PRO_CACHE_IA 1 6 PRO_CACHE_MMU_IA 0 1 PRO_CACHE_STATE 7 12 PRO_RX_END 23 1 PRO_SLAVE_WDATA_V 22 1 PRO_SLAVE_WR 21 1 PRO_TX_END 20 1 PRO_WR_BAK_TO_READ 19 1 PRO_DCACHE_DBUG1 DPORT_PRO_DCACHE_DBUG1 0x3F4 32 read-write n 0x0 0x0 PRO_CTAG_RAM_RDATA 0 32 PRO_DCACHE_DBUG2 DPORT_PRO_DCACHE_DBUG2 0x3F8 32 read-write n 0x0 0x0 PRO_CACHE_VADDR 0 27 PRO_DCACHE_DBUG3 DPORT_PRO_DCACHE_DBUG3 0x3FC 32 read-write n 0x0 0x0 PRO_CACHE_IRAM0_PID_ERROR 15 1 PRO_CPU_DISABLED_CACHE_IA 9 6 PRO_DCACHE_DBUG4 DPORT_PRO_DCACHE_DBUG4 0x400 32 read-write n 0x0 0x0 PRO_DRAM1ADDR0_IA 0 20 PRO_DCACHE_DBUG5 DPORT_PRO_DCACHE_DBUG5 0x404 32 read-write n 0x0 0x0 PRO_DROM0ADDR0_IA 0 20 PRO_DCACHE_DBUG6 DPORT_PRO_DCACHE_DBUG6 0x408 32 read-write n 0x0 0x0 PRO_IRAM0ADDR_IA 0 20 PRO_DCACHE_DBUG7 DPORT_PRO_DCACHE_DBUG7 0x40C 32 read-write n 0x0 0x0 PRO_IRAM1ADDR_IA 0 20 PRO_DCACHE_DBUG8 DPORT_PRO_DCACHE_DBUG8 0x410 32 read-write n 0x0 0x0 PRO_IROM0ADDR_IA 0 20 PRO_DCACHE_DBUG9 DPORT_PRO_DCACHE_DBUG9 0x414 32 read-write n 0x0 0x0 PRO_OPSDRAMADDR_IA 0 20 PRO_DPORT_APB_MASK0 DPORT_PRO_DPORT_APB_MASK0 0xC 32 read-write n 0x0 0x0 PRODPORT_APB_MASK0 0 32 PRO_DPORT_APB_MASK1 DPORT_PRO_DPORT_APB_MASK1 0x10 32 read-write n 0x0 0x0 PRODPORT_APB_MASK1 0 32 PRO_EFUSE_INT_MAP DPORT_PRO_EFUSE_INT_MAP 0x1B4 32 read-write n 0x0 0x0 PRO_EFUSE_INT_MAP 0 5 PRO_EMAC_INT_MAP DPORT_PRO_EMAC_INT_MAP 0x19C 32 read-write n 0x0 0x0 PRO_EMAC_INT_MAP 0 5 PRO_GPIO_INTERRUPT_MAP DPORT_PRO_GPIO_INTERRUPT_MAP 0x15C 32 read-write n 0x0 0x0 PRO_GPIO_INTERRUPT_PRO_MAP 0 5 PRO_GPIO_INTERRUPT_NMI_MAP DPORT_PRO_GPIO_INTERRUPT_NMI_MAP 0x160 32 read-write n 0x0 0x0 PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0 5 PRO_I2C_EXT0_INTR_MAP DPORT_PRO_I2C_EXT0_INTR_MAP 0x1C8 32 read-write n 0x0 0x0 PRO_I2C_EXT0_INTR_MAP 0 5 PRO_I2C_EXT1_INTR_MAP DPORT_PRO_I2C_EXT1_INTR_MAP 0x1CC 32 read-write n 0x0 0x0 PRO_I2C_EXT1_INTR_MAP 0 5 PRO_I2S0_INT_MAP DPORT_PRO_I2S0_INT_MAP 0x184 32 read-write n 0x0 0x0 PRO_I2S0_INT_MAP 0 5 PRO_I2S1_INT_MAP DPORT_PRO_I2S1_INT_MAP 0x188 32 read-write n 0x0 0x0 PRO_I2S1_INT_MAP 0 5 PRO_INTRUSION_CTRL DPORT_PRO_INTRUSION_CTRL 0x584 32 read-write n 0x0 0x0 PRO_INTRUSION_RECORD_RESET_N 0 1 PRO_INTRUSION_STATUS DPORT_PRO_INTRUSION_STATUS 0x588 32 read-write n 0x0 0x0 PRO_INTRUSION_RECORD 0 4 PRO_INTR_STATUS_0 DPORT_PRO_INTR_STATUS_0 0xEC 32 read-write n 0x0 0x0 PRO_INTR_STATUS_0 0 32 PRO_INTR_STATUS_1 DPORT_PRO_INTR_STATUS_1 0xF0 32 read-write n 0x0 0x0 PRO_INTR_STATUS_1 0 32 PRO_INTR_STATUS_2 DPORT_PRO_INTR_STATUS_2 0xF4 32 read-write n 0x0 0x0 PRO_INTR_STATUS_2 0 32 PRO_LEDC_INT_MAP DPORT_PRO_LEDC_INT_MAP 0x1B0 32 read-write n 0x0 0x0 PRO_LEDC_INT_MAP 0 5 PRO_MAC_INTR_MAP DPORT_PRO_MAC_INTR_MAP 0x104 32 read-write n 0x0 0x0 PRO_MAC_INTR_MAP 0 5 PRO_MAC_NMI_MAP DPORT_PRO_MAC_NMI_MAP 0x108 32 read-write n 0x0 0x0 PRO_MAC_NMI_MAP 0 5 PRO_MMU_IA_INT_MAP DPORT_PRO_MMU_IA_INT_MAP 0x20C 32 read-write n 0x0 0x0 PRO_MMU_IA_INT_MAP 0 5 PRO_MPU_IA_INT_MAP DPORT_PRO_MPU_IA_INT_MAP 0x210 32 read-write n 0x0 0x0 PRO_MPU_IA_INT_MAP 0 5 PRO_PCNT_INTR_MAP DPORT_PRO_PCNT_INTR_MAP 0x1C4 32 read-write n 0x0 0x0 PRO_PCNT_INTR_MAP 0 5 PRO_PWM0_INTR_MAP DPORT_PRO_PWM0_INTR_MAP 0x1A0 32 read-write n 0x0 0x0 PRO_PWM0_INTR_MAP 0 5 PRO_PWM1_INTR_MAP DPORT_PRO_PWM1_INTR_MAP 0x1A4 32 read-write n 0x0 0x0 PRO_PWM1_INTR_MAP 0 5 PRO_PWM2_INTR_MAP DPORT_PRO_PWM2_INTR_MAP 0x1A8 32 read-write n 0x0 0x0 PRO_PWM2_INTR_MAP 0 5 PRO_PWM3_INTR_MAP DPORT_PRO_PWM3_INTR_MAP 0x1AC 32 read-write n 0x0 0x0 PRO_PWM3_INTR_MAP 0 5 PRO_RMT_INTR_MAP DPORT_PRO_RMT_INTR_MAP 0x1C0 32 read-write n 0x0 0x0 PRO_RMT_INTR_MAP 0 5 PRO_RSA_INTR_MAP DPORT_PRO_RSA_INTR_MAP 0x1D0 32 read-write n 0x0 0x0 PRO_RSA_INTR_MAP 0 5 PRO_RTC_CORE_INTR_MAP DPORT_PRO_RTC_CORE_INTR_MAP 0x1BC 32 read-write n 0x0 0x0 PRO_RTC_CORE_INTR_MAP 0 5 PRO_RWBLE_IRQ_MAP DPORT_PRO_RWBLE_IRQ_MAP 0x120 32 read-write n 0x0 0x0 PRO_RWBLE_IRQ_MAP 0 5 PRO_RWBLE_NMI_MAP DPORT_PRO_RWBLE_NMI_MAP 0x128 32 read-write n 0x0 0x0 PRO_RWBLE_NMI_MAP 0 5 PRO_RWBT_IRQ_MAP DPORT_PRO_RWBT_IRQ_MAP 0x11C 32 read-write n 0x0 0x0 PRO_RWBT_IRQ_MAP 0 5 PRO_RWBT_NMI_MAP DPORT_PRO_RWBT_NMI_MAP 0x124 32 read-write n 0x0 0x0 PRO_RWBT_NMI_MAP 0 5 PRO_SDIO_HOST_INTERRUPT_MAP DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x198 32 read-write n 0x0 0x0 PRO_SDIO_HOST_INTERRUPT_MAP 0 5 PRO_SLC0_INTR_MAP DPORT_PRO_SLC0_INTR_MAP 0x12C 32 read-write n 0x0 0x0 PRO_SLC0_INTR_MAP 0 5 PRO_SLC1_INTR_MAP DPORT_PRO_SLC1_INTR_MAP 0x130 32 read-write n 0x0 0x0 PRO_SLC1_INTR_MAP 0 5 PRO_SPI1_DMA_INT_MAP DPORT_PRO_SPI1_DMA_INT_MAP 0x1D4 32 read-write n 0x0 0x0 PRO_SPI1_DMA_INT_MAP 0 5 PRO_SPI2_DMA_INT_MAP DPORT_PRO_SPI2_DMA_INT_MAP 0x1D8 32 read-write n 0x0 0x0 PRO_SPI2_DMA_INT_MAP 0 5 PRO_SPI3_DMA_INT_MAP DPORT_PRO_SPI3_DMA_INT_MAP 0x1DC 32 read-write n 0x0 0x0 PRO_SPI3_DMA_INT_MAP 0 5 PRO_SPI_INTR_0_MAP DPORT_PRO_SPI_INTR_0_MAP 0x174 32 read-write n 0x0 0x0 PRO_SPI_INTR_0_MAP 0 5 PRO_SPI_INTR_1_MAP DPORT_PRO_SPI_INTR_1_MAP 0x178 32 read-write n 0x0 0x0 PRO_SPI_INTR_1_MAP 0 5 PRO_SPI_INTR_2_MAP DPORT_PRO_SPI_INTR_2_MAP 0x17C 32 read-write n 0x0 0x0 PRO_SPI_INTR_2_MAP 0 5 PRO_SPI_INTR_3_MAP DPORT_PRO_SPI_INTR_3_MAP 0x180 32 read-write n 0x0 0x0 PRO_SPI_INTR_3_MAP 0 5 PRO_TG1_LACT_EDGE_INT_MAP DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x208 32 read-write n 0x0 0x0 PRO_TG1_LACT_EDGE_INT_MAP 0 5 PRO_TG1_LACT_LEVEL_INT_MAP DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x158 32 read-write n 0x0 0x0 PRO_TG1_LACT_LEVEL_INT_MAP 0 5 PRO_TG1_T0_EDGE_INT_MAP DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x1FC 32 read-write n 0x0 0x0 PRO_TG1_T0_EDGE_INT_MAP 0 5 PRO_TG1_T0_LEVEL_INT_MAP DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x14C 32 read-write n 0x0 0x0 PRO_TG1_T0_LEVEL_INT_MAP 0 5 PRO_TG1_T1_EDGE_INT_MAP DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x200 32 read-write n 0x0 0x0 PRO_TG1_T1_EDGE_INT_MAP 0 5 PRO_TG1_T1_LEVEL_INT_MAP DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x150 32 read-write n 0x0 0x0 PRO_TG1_T1_LEVEL_INT_MAP 0 5 PRO_TG1_WDT_EDGE_INT_MAP DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x204 32 read-write n 0x0 0x0 PRO_TG1_WDT_EDGE_INT_MAP 0 5 PRO_TG1_WDT_LEVEL_INT_MAP DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x154 32 read-write n 0x0 0x0 PRO_TG1_WDT_LEVEL_INT_MAP 0 5 PRO_TG_LACT_EDGE_INT_MAP DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x1F8 32 read-write n 0x0 0x0 PRO_TG_LACT_EDGE_INT_MAP 0 5 PRO_TG_LACT_LEVEL_INT_MAP DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x148 32 read-write n 0x0 0x0 PRO_TG_LACT_LEVEL_INT_MAP 0 5 PRO_TG_T0_EDGE_INT_MAP DPORT_PRO_TG_T0_EDGE_INT_MAP 0x1EC 32 read-write n 0x0 0x0 PRO_TG_T0_EDGE_INT_MAP 0 5 PRO_TG_T0_LEVEL_INT_MAP DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x13C 32 read-write n 0x0 0x0 PRO_TG_T0_LEVEL_INT_MAP 0 5 PRO_TG_T1_EDGE_INT_MAP DPORT_PRO_TG_T1_EDGE_INT_MAP 0x1F0 32 read-write n 0x0 0x0 PRO_TG_T1_EDGE_INT_MAP 0 5 PRO_TG_T1_LEVEL_INT_MAP DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x140 32 read-write n 0x0 0x0 PRO_TG_T1_LEVEL_INT_MAP 0 5 PRO_TG_WDT_EDGE_INT_MAP DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x1F4 32 read-write n 0x0 0x0 PRO_TG_WDT_EDGE_INT_MAP 0 5 PRO_TG_WDT_LEVEL_INT_MAP DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x144 32 read-write n 0x0 0x0 PRO_TG_WDT_LEVEL_INT_MAP 0 5 PRO_TIMER_INT1_MAP DPORT_PRO_TIMER_INT1_MAP 0x1E4 32 read-write n 0x0 0x0 PRO_TIMER_INT1_MAP 0 5 PRO_TIMER_INT2_MAP DPORT_PRO_TIMER_INT2_MAP 0x1E8 32 read-write n 0x0 0x0 PRO_TIMER_INT2_MAP 0 5 PRO_TRACEMEM_ENA DPORT_PRO_TRACEMEM_ENA 0x74 32 read-write n 0x0 0x0 PRO_TRACEMEM_ENA 0 1 PRO_UART1_INTR_MAP DPORT_PRO_UART1_INTR_MAP 0x190 32 read-write n 0x0 0x0 PRO_UART1_INTR_MAP 0 5 PRO_UART2_INTR_MAP DPORT_PRO_UART2_INTR_MAP 0x194 32 read-write n 0x0 0x0 PRO_UART2_INTR_MAP 0 5 PRO_UART_INTR_MAP DPORT_PRO_UART_INTR_MAP 0x18C 32 read-write n 0x0 0x0 PRO_UART_INTR_MAP 0 5 PRO_UHCI0_INTR_MAP DPORT_PRO_UHCI0_INTR_MAP 0x134 32 read-write n 0x0 0x0 PRO_UHCI0_INTR_MAP 0 5 PRO_UHCI1_INTR_MAP DPORT_PRO_UHCI1_INTR_MAP 0x138 32 read-write n 0x0 0x0 PRO_UHCI1_INTR_MAP 0 5 PRO_VECBASE_CTRL DPORT_PRO_VECBASE_CTRL 0x5AC 32 read-write n 0x0 0x0 PRO_OUT_VECBASE_SEL 0 2 PRO_VECBASE_SET DPORT_PRO_VECBASE_SET 0x5B0 32 read-write n 0x0 0x0 PRO_OUT_VECBASE_REG 0 22 PRO_WDG_INT_MAP DPORT_PRO_WDG_INT_MAP 0x1E0 32 read-write n 0x0 0x0 PRO_WDG_INT_MAP 0 5 ROM_FO_CTRL DPORT_ROM_FO_CTRL 0x94 32 read-write n 0x0 0x0 APP_ROM_FO 1 1 PRO_ROM_FO 0 1 SHARE_ROM_FO 2 6 ROM_MPU_ENA DPORT_ROM_MPU_ENA 0x88 32 read-write n 0x0 0x0 APP_ROM_MPU_ENA 2 1 PRO_ROM_MPU_ENA 1 1 SHARE_ROM_MPU_ENA 0 1 ROM_MPU_TABLE0 DPORT_ROM_MPU_TABLE0 0x494 32 read-write n 0x0 0x0 ROM_MPU_TABLE0 0 2 ROM_MPU_TABLE1 DPORT_ROM_MPU_TABLE1 0x498 32 read-write n 0x0 0x0 ROM_MPU_TABLE1 0 2 ROM_MPU_TABLE2 DPORT_ROM_MPU_TABLE2 0x49C 32 read-write n 0x0 0x0 ROM_MPU_TABLE2 0 2 ROM_MPU_TABLE3 DPORT_ROM_MPU_TABLE3 0x4A0 32 read-write n 0x0 0x0 ROM_MPU_TABLE3 0 2 ROM_PD_CTRL DPORT_ROM_PD_CTRL 0x90 32 read-write n 0x0 0x0 APP_ROM_PD 1 1 PRO_ROM_PD 0 1 SHARE_ROM_PD 2 6 RSA_PD_CTRL DPORT_RSA_PD_CTRL 0x490 32 read-write n 0x0 0x0 RSA_PD 0 1 SECURE_BOOT_CTRL DPORT_SECURE_BOOT_CTRL 0x5A4 32 read-write n 0x0 0x0 SW_BOOTLOADER_SEL 0 1 SHROM_MPU_TABLE0 DPORT_SHROM_MPU_TABLE0 0x4A4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE0 0 2 SHROM_MPU_TABLE1 DPORT_SHROM_MPU_TABLE1 0x4A8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE1 0 2 SHROM_MPU_TABLE10 DPORT_SHROM_MPU_TABLE10 0x4CC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE10 0 2 SHROM_MPU_TABLE11 DPORT_SHROM_MPU_TABLE11 0x4D0 32 read-write n 0x0 0x0 SHROM_MPU_TABLE11 0 2 SHROM_MPU_TABLE12 DPORT_SHROM_MPU_TABLE12 0x4D4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE12 0 2 SHROM_MPU_TABLE13 DPORT_SHROM_MPU_TABLE13 0x4D8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE13 0 2 SHROM_MPU_TABLE14 DPORT_SHROM_MPU_TABLE14 0x4DC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE14 0 2 SHROM_MPU_TABLE15 DPORT_SHROM_MPU_TABLE15 0x4E0 32 read-write n 0x0 0x0 SHROM_MPU_TABLE15 0 2 SHROM_MPU_TABLE16 DPORT_SHROM_MPU_TABLE16 0x4E4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE16 0 2 SHROM_MPU_TABLE17 DPORT_SHROM_MPU_TABLE17 0x4E8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE17 0 2 SHROM_MPU_TABLE18 DPORT_SHROM_MPU_TABLE18 0x4EC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE18 0 2 SHROM_MPU_TABLE19 DPORT_SHROM_MPU_TABLE19 0x4F0 32 read-write n 0x0 0x0 SHROM_MPU_TABLE19 0 2 SHROM_MPU_TABLE2 DPORT_SHROM_MPU_TABLE2 0x4AC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE2 0 2 SHROM_MPU_TABLE20 DPORT_SHROM_MPU_TABLE20 0x4F4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE20 0 2 SHROM_MPU_TABLE21 DPORT_SHROM_MPU_TABLE21 0x4F8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE21 0 2 SHROM_MPU_TABLE22 DPORT_SHROM_MPU_TABLE22 0x4FC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE22 0 2 SHROM_MPU_TABLE23 DPORT_SHROM_MPU_TABLE23 0x500 32 read-write n 0x0 0x0 SHROM_MPU_TABLE23 0 2 SHROM_MPU_TABLE3 DPORT_SHROM_MPU_TABLE3 0x4B0 32 read-write n 0x0 0x0 SHROM_MPU_TABLE3 0 2 SHROM_MPU_TABLE4 DPORT_SHROM_MPU_TABLE4 0x4B4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE4 0 2 SHROM_MPU_TABLE5 DPORT_SHROM_MPU_TABLE5 0x4B8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE5 0 2 SHROM_MPU_TABLE6 DPORT_SHROM_MPU_TABLE6 0x4BC 32 read-write n 0x0 0x0 SHROM_MPU_TABLE6 0 2 SHROM_MPU_TABLE7 DPORT_SHROM_MPU_TABLE7 0x4C0 32 read-write n 0x0 0x0 SHROM_MPU_TABLE7 0 2 SHROM_MPU_TABLE8 DPORT_SHROM_MPU_TABLE8 0x4C4 32 read-write n 0x0 0x0 SHROM_MPU_TABLE8 0 2 SHROM_MPU_TABLE9 DPORT_SHROM_MPU_TABLE9 0x4C8 32 read-write n 0x0 0x0 SHROM_MPU_TABLE9 0 2 SPI_DMA_CHAN_SEL DPORT_SPI_DMA_CHAN_SEL 0x5A8 32 read-write n 0x0 0x0 SPI1_DMA_CHAN_SEL 0 2 SPI2_DMA_CHAN_SEL 2 2 SPI3_DMA_CHAN_SEL 4 2 SRAM_FO_CTRL_0 DPORT_SRAM_FO_CTRL_0 0xA0 32 read-write n 0x0 0x0 SRAM_FO_0 0 32 SRAM_FO_CTRL_1 DPORT_SRAM_FO_CTRL_1 0xA4 32 read-write n 0x0 0x0 SRAM_FO_1 0 1 SRAM_PD_CTRL_0 DPORT_SRAM_PD_CTRL_0 0x98 32 read-write n 0x0 0x0 SRAM_PD_0 0 32 SRAM_PD_CTRL_1 DPORT_SRAM_PD_CTRL_1 0x9C 32 read-write n 0x0 0x0 SRAM_PD_1 0 1 TAG_FO_CTRL DPORT_TAG_FO_CTRL 0xAC 32 read-write n 0x0 0x0 APP_CACHE_TAG_FORCE_ON 8 1 APP_CACHE_TAG_PD 9 1 PRO_CACHE_TAG_FORCE_ON 0 1 PRO_CACHE_TAG_PD 1 1 TRACEMEM_MUX_MODE DPORT_TRACEMEM_MUX_MODE 0x70 32 read-write n 0x0 0x0 TRACEMEM_MUX_MODE 0 2 WIFI_BB_CFG DPORT_WIFI_BB_CFG 0x24 32 read-write n 0x0 0x0 WIFI_BB_CFG 0 32 WIFI_BB_CFG_2 DPORT_WIFI_BB_CFG_2 0x28 32 read-write n 0x0 0x0 WIFI_BB_CFG_2 0 32 WIFI_CLK_EN DPORT_WIFI_CLK_EN 0xCC 32 read-write n 0x0 0x0 WIFI_CLK_EN 0 32 EFUSE EFUSE 0x0 0x0 0x920 registers n EFUSE_INTR interrupt of efuse, level, not likely to use 44 BLK0_RDATA0 EFUSE_BLK0_RDATA0 0x0 32 read-write n 0x0 0x0 RD_EFUSE_RD_DIS 16 4 RD_FLASH_CRYPT_CNT 20 7 BLK0_RDATA1 EFUSE_BLK0_RDATA1 0x4 32 read-write n 0x0 0x0 RD_WIFI_MAC_CRC_LOW 0 32 BLK0_RDATA2 EFUSE_BLK0_RDATA2 0x8 32 read-write n 0x0 0x0 RD_WIFI_MAC_CRC_HIGH 0 24 BLK0_RDATA3 EFUSE_BLK0_RDATA3 0xC 32 read-write n 0x0 0x0 RD_CHIP_CPU_FREQ_LOW 12 1 RD_CHIP_CPU_FREQ_RATED 13 1 RD_CHIP_VER_32PAD 2 1 RD_CHIP_VER_DIS_APP_CPU 0 1 RD_CHIP_VER_DIS_BT 1 1 RD_CHIP_VER_DIS_CACHE 3 1 RD_CHIP_VER_PKG 9 3 RD_CHIP_VER_REV1 15 1 RD_SPI_PAD_CONFIG_HD 4 5 BLK0_RDATA4 EFUSE_BLK0_RDATA4 0x10 32 read-write n 0x0 0x0 RD_ADC_VREF 8 5 RD_CK8M_FREQ 0 8 RD_SDIO_DREFH 8 2 RD_SDIO_DREFL 12 2 RD_SDIO_DREFM 10 2 RD_SDIO_FORCE 16 1 RD_SDIO_TIEH 15 1 RD_XPD_SDIO_REG 14 1 BLK0_RDATA5 EFUSE_BLK0_RDATA5 0x14 32 read-write n 0x0 0x0 RD_FLASH_CRYPT_CONFIG 28 4 RD_INST_CONFIG 20 8 RD_SPI_PAD_CONFIG_CLK 0 5 RD_SPI_PAD_CONFIG_D 10 5 RD_SPI_PAD_CONFIG_Q 5 5 BLK0_RDATA6 EFUSE_BLK0_RDATA6 0x18 32 read-write n 0x0 0x0 RD_ABS_DONE_0 4 1 RD_ABS_DONE_1 5 1 RD_CODING_SCHEME 0 2 RD_CONSOLE_DEBUG_DISABLE 2 1 RD_DISABLE_DL_CACHE 9 1 RD_DISABLE_DL_DECRYPT 8 1 RD_DISABLE_DL_ENCRYPT 7 1 RD_DISABLE_JTAG 6 1 RD_DISABLE_SDIO_HOST 3 1 RD_KEY_STATUS 10 1 BLK0_WDATA0 EFUSE_BLK0_WDATA0 0x1C 32 read-write n 0x0 0x0 FLASH_CRYPT_CNT 20 7 RD_DIS 16 4 WR_DIS 0 16 BLK0_WDATA1 EFUSE_BLK0_WDATA1 0x20 32 read-write n 0x0 0x0 WIFI_MAC_CRC_LOW 0 32 BLK0_WDATA2 EFUSE_BLK0_WDATA2 0x24 32 read-write n 0x0 0x0 WIFI_MAC_CRC_HIGH 0 24 BLK0_WDATA3 EFUSE_BLK0_WDATA3 0x28 32 read-write n 0x0 0x0 CHIP_CPU_FREQ_LOW 12 1 CHIP_CPU_FREQ_RATED 13 1 CHIP_VER_32PAD 2 1 CHIP_VER_DIS_APP_CPU 0 1 CHIP_VER_DIS_BT 1 1 CHIP_VER_DIS_CACHE 3 1 CHIP_VER_PKG 9 3 CHIP_VER_REV1 15 1 SPI_PAD_CONFIG_HD 4 5 BLK0_WDATA4 EFUSE_BLK0_WDATA4 0x2C 32 read-write n 0x0 0x0 ADC_VREF 8 5 CK8M_FREQ 0 8 SDIO_DREFH 8 2 SDIO_DREFL 12 2 SDIO_DREFM 10 2 SDIO_FORCE 16 1 SDIO_TIEH 15 1 XPD_SDIO_REG 14 1 BLK0_WDATA5 EFUSE_BLK0_WDATA5 0x30 32 read-write n 0x0 0x0 FLASH_CRYPT_CONFIG 28 4 INST_CONFIG 20 8 SPI_PAD_CONFIG_CLK 0 5 SPI_PAD_CONFIG_D 10 5 SPI_PAD_CONFIG_Q 5 5 BLK0_WDATA6 EFUSE_BLK0_WDATA6 0x34 32 read-write n 0x0 0x0 ABS_DONE_0 4 1 ABS_DONE_1 5 1 CODING_SCHEME 0 2 CONSOLE_DEBUG_DISABLE 2 1 DISABLE_DL_CACHE 9 1 DISABLE_DL_DECRYPT 8 1 DISABLE_DL_ENCRYPT 7 1 DISABLE_JTAG 6 1 DISABLE_SDIO_HOST 3 1 KEY_STATUS 10 1 BLK1_RDATA0 EFUSE_BLK1_RDATA0 0x38 32 read-write n 0x0 0x0 BLK1_DOUT0 0 32 BLK1_RDATA1 EFUSE_BLK1_RDATA1 0x3C 32 read-write n 0x0 0x0 BLK1_DOUT1 0 32 BLK1_RDATA2 EFUSE_BLK1_RDATA2 0x40 32 read-write n 0x0 0x0 BLK1_DOUT2 0 32 BLK1_RDATA3 EFUSE_BLK1_RDATA3 0x44 32 read-write n 0x0 0x0 BLK1_DOUT3 0 32 BLK1_RDATA4 EFUSE_BLK1_RDATA4 0x48 32 read-write n 0x0 0x0 BLK1_DOUT4 0 32 BLK1_RDATA5 EFUSE_BLK1_RDATA5 0x4C 32 read-write n 0x0 0x0 BLK1_DOUT5 0 32 BLK1_RDATA6 EFUSE_BLK1_RDATA6 0x50 32 read-write n 0x0 0x0 BLK1_DOUT6 0 32 BLK1_RDATA7 EFUSE_BLK1_RDATA7 0x54 32 read-write n 0x0 0x0 BLK1_DOUT7 0 32 BLK1_WDATA0 EFUSE_BLK1_WDATA0 0x98 32 read-write n 0x0 0x0 BLK1_DIN0 0 32 BLK1_WDATA1 EFUSE_BLK1_WDATA1 0x9C 32 read-write n 0x0 0x0 BLK1_DIN1 0 32 BLK1_WDATA2 EFUSE_BLK1_WDATA2 0xA0 32 read-write n 0x0 0x0 BLK1_DIN2 0 32 BLK1_WDATA3 EFUSE_BLK1_WDATA3 0xA4 32 read-write n 0x0 0x0 BLK1_DIN3 0 32 BLK1_WDATA4 EFUSE_BLK1_WDATA4 0xA8 32 read-write n 0x0 0x0 BLK1_DIN4 0 32 BLK1_WDATA5 EFUSE_BLK1_WDATA5 0xAC 32 read-write n 0x0 0x0 BLK1_DIN5 0 32 BLK1_WDATA6 EFUSE_BLK1_WDATA6 0xB0 32 read-write n 0x0 0x0 BLK1_DIN6 0 32 BLK1_WDATA7 EFUSE_BLK1_WDATA7 0xB4 32 read-write n 0x0 0x0 BLK1_DIN7 0 32 BLK2_RDATA0 EFUSE_BLK2_RDATA0 0x58 32 read-write n 0x0 0x0 BLK2_DOUT0 0 32 BLK2_RDATA1 EFUSE_BLK2_RDATA1 0x5C 32 read-write n 0x0 0x0 BLK2_DOUT1 0 32 BLK2_RDATA2 EFUSE_BLK2_RDATA2 0x60 32 read-write n 0x0 0x0 BLK2_DOUT2 0 32 BLK2_RDATA3 EFUSE_BLK2_RDATA3 0x64 32 read-write n 0x0 0x0 BLK2_DOUT3 0 32 BLK2_RDATA4 EFUSE_BLK2_RDATA4 0x68 32 read-write n 0x0 0x0 BLK2_DOUT4 0 32 BLK2_RDATA5 EFUSE_BLK2_RDATA5 0x6C 32 read-write n 0x0 0x0 BLK2_DOUT5 0 32 BLK2_RDATA6 EFUSE_BLK2_RDATA6 0x70 32 read-write n 0x0 0x0 BLK2_DOUT6 0 32 BLK2_RDATA7 EFUSE_BLK2_RDATA7 0x74 32 read-write n 0x0 0x0 BLK2_DOUT7 0 32 BLK2_WDATA0 EFUSE_BLK2_WDATA0 0xB8 32 read-write n 0x0 0x0 BLK2_DIN0 0 32 BLK2_WDATA1 EFUSE_BLK2_WDATA1 0xBC 32 read-write n 0x0 0x0 BLK2_DIN1 0 32 BLK2_WDATA2 EFUSE_BLK2_WDATA2 0xC0 32 read-write n 0x0 0x0 BLK2_DIN2 0 32 BLK2_WDATA3 EFUSE_BLK2_WDATA3 0xC4 32 read-write n 0x0 0x0 BLK2_DIN3 0 32 BLK2_WDATA4 EFUSE_BLK2_WDATA4 0xC8 32 read-write n 0x0 0x0 BLK2_DIN4 0 32 BLK2_WDATA5 EFUSE_BLK2_WDATA5 0xCC 32 read-write n 0x0 0x0 BLK2_DIN5 0 32 BLK2_WDATA6 EFUSE_BLK2_WDATA6 0xD0 32 read-write n 0x0 0x0 BLK2_DIN6 0 32 BLK2_WDATA7 EFUSE_BLK2_WDATA7 0xD4 32 read-write n 0x0 0x0 BLK2_DIN7 0 32 BLK3_RDATA0 EFUSE_BLK3_RDATA0 0x78 32 read-write n 0x0 0x0 BLK3_DOUT0 0 32 BLK3_RDATA1 EFUSE_BLK3_RDATA1 0x7C 32 read-write n 0x0 0x0 BLK3_DOUT1 0 32 BLK3_RDATA2 EFUSE_BLK3_RDATA2 0x80 32 read-write n 0x0 0x0 BLK3_DOUT2 0 32 BLK3_RDATA3 EFUSE_BLK3_RDATA3 0x84 32 read-write n 0x0 0x0 BLK3_DOUT3 0 32 RD_ADC1_TP_HIGH 7 9 RD_ADC1_TP_LOW 0 7 RD_ADC2_TP_HIGH 23 9 RD_ADC2_TP_LOW 16 7 BLK3_RDATA4 EFUSE_BLK3_RDATA4 0x88 32 read-write n 0x0 0x0 BLK3_DOUT4 0 32 BLK3_RDATA5 EFUSE_BLK3_RDATA5 0x8C 32 read-write n 0x0 0x0 BLK3_DOUT5 0 32 BLK3_RDATA6 EFUSE_BLK3_RDATA6 0x90 32 read-write n 0x0 0x0 BLK3_DOUT6 0 32 BLK3_RDATA7 EFUSE_BLK3_RDATA7 0x94 32 read-write n 0x0 0x0 BLK3_DOUT7 0 32 BLK3_WDATA0 EFUSE_BLK3_WDATA0 0xD8 32 read-write n 0x0 0x0 BLK3_DIN0 0 32 BLK3_WDATA1 EFUSE_BLK3_WDATA1 0xDC 32 read-write n 0x0 0x0 BLK3_DIN1 0 32 BLK3_WDATA2 EFUSE_BLK3_WDATA2 0xE0 32 read-write n 0x0 0x0 BLK3_DIN2 0 32 BLK3_WDATA3 EFUSE_BLK3_WDATA3 0xE4 32 read-write n 0x0 0x0 ADC1_TP_HIGH 7 9 ADC1_TP_LOW 0 7 ADC2_TP_HIGH 23 9 ADC2_TP_LOW 16 7 BLK3_DIN3 0 32 BLK3_WDATA4 EFUSE_BLK3_WDATA4 0xE8 32 read-write n 0x0 0x0 BLK3_DIN4 0 32 BLK3_WDATA5 EFUSE_BLK3_WDATA5 0xEC 32 read-write n 0x0 0x0 BLK3_DIN5 0 32 BLK3_WDATA6 EFUSE_BLK3_WDATA6 0xF0 32 read-write n 0x0 0x0 BLK3_DIN6 0 32 BLK3_WDATA7 EFUSE_BLK3_WDATA7 0xF4 32 read-write n 0x0 0x0 BLK3_DIN7 0 32 CLK EFUSE_CLK 0xF8 32 read-write n 0x0 0x0 CLK_EN 16 1 CLK_SEL0 0 8 CLK_SEL1 8 8 CMD EFUSE_CMD 0x104 32 read-write n 0x0 0x0 PGM_CMD 1 1 READ_CMD 0 1 CONF EFUSE_CONF 0xFC 32 read-write n 0x0 0x0 FORCE_NO_WR_RD_DIS 16 1 OP_CODE 0 16 DAC_CONF EFUSE_DAC_CONF 0x118 32 read-write n 0x0 0x0 DAC_CLK_DIV 0 8 DAC_CLK_PAD_SEL 8 1 DATE EFUSE_DATE 0x1FC 32 read-write n 0x0 0x0 DATE 0 32 DEC_STATUS EFUSE_DEC_STATUS 0x11C 32 read-write n 0x0 0x0 DEC_WARNINGS 0 12 INT_CLR EFUSE_INT_CLR 0x114 32 read-write n 0x0 0x0 PGM_DONE_INT_CLR 1 1 READ_DONE_INT_CLR 0 1 INT_ENA EFUSE_INT_ENA 0x110 32 read-write n 0x0 0x0 PGM_DONE_INT_ENA 1 1 READ_DONE_INT_ENA 0 1 INT_RAW EFUSE_INT_RAW 0x108 32 read-write n 0x0 0x0 PGM_DONE_INT_RAW 1 1 READ_DONE_INT_RAW 0 1 INT_ST EFUSE_INT_ST 0x10C 32 read-write n 0x0 0x0 PGM_DONE_INT_ST 1 1 READ_DONE_INT_ST 0 1 STATUS EFUSE_STATUS 0x100 32 read-write n 0x0 0x0 DEBUG 0 32 EMAC EMAC 0x0 0x0 0x0 registers n ETH ETH 0x0 ETH_MAC_INTR interrupt of ethernet mac, level 38 ETH_MAC ETH_MAC 0x0 FE FE 0x0 0x0 0x0 registers n FE2 FE2 0x0 0x0 0x0 registers n FRC_TIMER FRC_TIMER 0x0 0x0 0x0 registers n GPIO GPIO 0x0 0x0 0x2E60 registers n GPIO_INTR interrupt of GPIO, level 22 GPIO_NMI interrupt of GPIO, NMI 23 ACPU_INT GPIO_ACPU_INT 0x60 32 read-write n 0x0 0x0 APPCPU_INT 0 32 ACPU_INT1 GPIO_ACPU_INT1 0x74 32 read-write n 0x0 0x0 APPCPU_INT_H 0 8 ACPU_NMI_INT GPIO_ACPU_NMI_INT 0x64 32 read-write n 0x0 0x0 APPCPU_NMI_INT 0 32 ACPU_NMI_INT1 GPIO_ACPU_NMI_INT1 0x78 32 read-write n 0x0 0x0 APPCPU_NMI_INT_H 0 8 BT_SELECT GPIO_BT_SELECT 0x0 32 read-write n 0x0 0x0 BT_SEL 0 32 cali_conf GPIO_cali_conf 0x128 32 read-write n 0x0 0x0 CALI_RTC_MAX 0 10 CALI_START 31 1 cali_data GPIO_cali_data 0x12C 32 read-write n 0x0 0x0 CALI_RDY_REAL 30 1 CALI_RDY_SYNC2 31 1 CALI_VALUE_SYNC2 0 20 CPUSDIO_INT GPIO_CPUSDIO_INT 0x70 32 read-write n 0x0 0x0 SDIO_INT 0 32 CPUSDIO_INT1 GPIO_CPUSDIO_INT1 0x84 32 read-write n 0x0 0x0 SDIO_INT_H 0 8 ENABLE GPIO_ENABLE 0x20 32 read-write n 0x0 0x0 ENABLE_DATA 0 32 ENABLE1 GPIO_ENABLE1 0x2C 32 read-write n 0x0 0x0 ENABLE1_DATA 0 8 ENABLE1_W1TC GPIO_ENABLE1_W1TC 0x34 32 read-write n 0x0 0x0 ENABLE1_DATA_W1TC 0 8 ENABLE1_W1TS GPIO_ENABLE1_W1TS 0x30 32 read-write n 0x0 0x0 ENABLE1_DATA_W1TS 0 8 ENABLE_W1TC GPIO_ENABLE_W1TC 0x28 32 read-write n 0x0 0x0 ENABLE_DATA_W1TC 0 32 ENABLE_W1TS GPIO_ENABLE_W1TS 0x24 32 read-write n 0x0 0x0 ENABLE_DATA_W1TS 0 32 FUNC0_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x260 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC0_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xA60 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC100_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xC808 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC101_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xCACC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC102_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xCD94 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC103_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xD060 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC104_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xD330 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC105_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xD604 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC106_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xD8DC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC107_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xDBB8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC108_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xDE98 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC109_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xE17C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC10_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xF1C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC10_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x3F1C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC110_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xE464 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC111_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xE750 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC112_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xEA40 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC113_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xED34 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC114_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xF02C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC115_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xF328 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC116_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xF628 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC117_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xF92C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC118_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xFC34 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC119_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xFF40 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC11_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1078 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC11_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x4478 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC120_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x10250 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC121_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x10564 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC122_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1087C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC123_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x10B98 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC124_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x10EB8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC125_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x111DC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC126_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x11504 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC127_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x11830 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC128_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x11B60 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC129_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x11E94 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC12_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x11D8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC12_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x49D8 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC130_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x121CC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC131_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x12508 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC132_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x12848 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC133_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x12B8C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC134_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x12ED4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC135_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x13220 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC136_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x13570 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC137_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x138C4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC138_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x13C1C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC139_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x13F78 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC13_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x133C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC13_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x4F3C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC140_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x142D8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC141_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1463C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC142_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x149A4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC143_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x14D10 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC144_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x15080 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC145_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x153F4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC146_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1576C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC147_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x15AE8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC148_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x15E68 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC149_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x161EC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC14_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x14A4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC14_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x54A4 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC150_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x16574 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC151_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x16900 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC152_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x16C90 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC153_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x17024 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC154_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x173BC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC155_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x17758 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC156_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x17AF8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC157_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x17E9C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC158_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x18244 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC159_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x185F0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC15_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1610 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC15_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x5A10 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC160_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x189A0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC161_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x18D54 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC162_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1910C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC163_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x194C8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC164_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x19888 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC165_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x19C4C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC166_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1A014 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC167_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1A3E0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC168_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1A7B0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC169_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1AB84 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC16_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1780 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC16_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x5F80 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC170_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1AF5C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC171_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1B338 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC172_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1B718 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC173_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1BAFC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC174_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1BEE4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC175_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1C2D0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC176_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1C6C0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC177_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1CAB4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC178_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1CEAC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC179_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1D2A8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC17_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x18F4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC17_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x64F4 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC180_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1D6A8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC181_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1DAAC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC182_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1DEB4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC183_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1E2C0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC184_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1E6D0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC185_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1EAE4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC186_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1EEFC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC187_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1F318 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC188_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1F738 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC189_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1FB5C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC18_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1A6C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC18_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x6A6C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC190_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1FF84 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC191_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x203B0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC192_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x207E0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC193_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x20C14 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC194_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2104C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC195_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x21488 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC196_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x218C8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC197_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x21D0C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC198_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x22154 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC199_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x225A0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC19_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1BE8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC19_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x6FE8 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC1_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x394 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC1_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xF94 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC200_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x229F0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC201_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x22E44 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC202_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2329C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC203_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x236F8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC204_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x23B58 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC205_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x23FBC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC206_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x24424 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC207_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x24890 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC208_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x24D00 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC209_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x25174 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC20_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1D68 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC20_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x7568 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC210_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x255EC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC211_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x25A68 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC212_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x25EE8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC213_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2636C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC214_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x267F4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC215_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x26C80 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC216_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x27110 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC217_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x275A4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC218_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x27A3C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC219_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x27ED8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC21_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x1EEC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC21_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x7AEC 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC220_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x28378 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC221_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2881C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC222_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x28CC4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC223_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x29170 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC224_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x29620 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC225_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x29AD4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC226_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x29F8C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC227_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2A448 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC228_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2A908 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC229_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2ADCC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC22_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2074 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC22_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x8074 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC230_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2B294 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC231_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2B760 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC232_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2BC30 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC233_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2C104 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC234_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2C5DC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC235_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2CAB8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC236_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2CF98 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC237_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2D47C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC238_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2D964 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC239_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2DE50 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC23_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2200 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC23_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x8600 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC240_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2E340 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC241_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2E834 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC242_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2ED2C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC243_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2F228 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC244_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2F728 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC245_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2FC2C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC246_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x30134 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC247_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x30640 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC248_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x30B50 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC249_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x31064 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC24_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2390 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC24_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x8B90 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC250_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3157C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC251_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x31A98 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC252_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x31FB8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC253_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x324DC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC254_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x32A04 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC255_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x32F30 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC25_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2524 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC25_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x9124 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC26_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x26BC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC26_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x96BC 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC27_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2858 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC27_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x9C58 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC28_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x29F8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC28_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xA1F8 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC29_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2B9C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC29_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xA79C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC2_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4CC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC2_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x14CC 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC30_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2D44 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC30_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xAD44 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC31_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x2EF0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC31_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xB2F0 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC32_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x30A0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC32_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xB8A0 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC33_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3254 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC33_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xBE54 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC34_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x340C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC34_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xC40C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC35_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x35C8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC35_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xC9C8 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC36_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3788 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC36_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xCF88 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC37_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x394C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC37_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xD54C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC38_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3B14 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC38_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xDB14 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC39_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3CE0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC39_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0xE0E0 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC3_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x608 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC3_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x1A08 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC40_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x3EB0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC41_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4084 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC42_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x425C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC43_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4438 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC44_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4618 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC45_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x47FC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC46_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x49E4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC47_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4BD0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC48_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4DC0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC49_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x4FB4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC4_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x748 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC4_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x1F48 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC50_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x51AC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC51_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x53A8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC52_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x55A8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC53_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x57AC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC54_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x59B4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC55_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x5BC0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC56_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x5DD0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC57_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x5FE4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC58_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x61FC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC59_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x6418 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC5_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x88C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC5_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x248C 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC60_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x6638 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC61_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x685C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC62_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x6A84 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC63_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x6CB0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC64_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x6EE0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC65_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x7114 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC66_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x734C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC67_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x7588 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC68_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x77C8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC69_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x7A0C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC6_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9D4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC6_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x29D4 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC70_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x7C54 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC71_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x7EA0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC72_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x80F0 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC73_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x8344 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC74_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x859C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC75_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x87F8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC76_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x8A58 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC77_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x8CBC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC78_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x8F24 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC79_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9190 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC7_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xB20 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC7_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x2F20 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC80_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9400 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC81_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9674 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC82_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x98EC 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC83_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9B68 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC84_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0x9DE8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC85_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xA06C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC86_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xA2F4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC87_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xA580 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC88_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xA810 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC89_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xAAA4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC8_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xC70 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC8_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x3470 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 FUNC90_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xAD3C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC91_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xAFD8 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC92_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xB278 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC93_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xB51C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC94_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xB7C4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC95_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xBA70 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC96_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xBD20 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC97_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xBFD4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC98_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xC28C 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC99_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xC548 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC9_IN_SEL_CFG GPIO_FUNC0_IN_SEL_CFG 0xDC4 32 read-write n 0x0 0x0 IN_INV_SEL 6 1 IN_SEL 0 6 SEL 7 1 FUNC9_OUT_SEL_CFG GPIO_FUNC0_OUT_SEL_CFG 0x39C4 32 read-write n 0x0 0x0 OEN_INV_SEL 11 1 OEN_SEL 10 1 OUT_INV_SEL 9 1 OUT_SEL 0 9 IN GPIO_IN 0x3C 32 read-write n 0x0 0x0 IN_DATA 0 32 IN1 GPIO_IN1 0x40 32 read-write n 0x0 0x0 IN1_DATA 0 8 OUT GPIO_OUT 0x4 32 read-write n 0x0 0x0 OUT_DATA 0 32 OUT1 GPIO_OUT1 0x10 32 read-write n 0x0 0x0 OUT1_DATA 0 8 OUT1_W1TC GPIO_OUT1_W1TC 0x18 32 read-write n 0x0 0x0 OUT1_DATA_W1TC 0 8 OUT1_W1TS GPIO_OUT1_W1TS 0x14 32 read-write n 0x0 0x0 OUT1_DATA_W1TS 0 8 OUT_W1TC GPIO_OUT_W1TC 0xC 32 read-write n 0x0 0x0 OUT_DATA_W1TC 0 32 OUT_W1TS GPIO_OUT_W1TS 0x8 32 read-write n 0x0 0x0 OUT_DATA_W1TS 0 32 PCPU_INT GPIO_PCPU_INT 0x68 32 read-write n 0x0 0x0 PROCPU_INT 0 32 PCPU_INT1 GPIO_PCPU_INT1 0x7C 32 read-write n 0x0 0x0 PROCPU_INT_H 0 8 PCPU_NMI_INT GPIO_PCPU_NMI_INT 0x6C 32 read-write n 0x0 0x0 PROCPU_NMI_INT 0 32 PCPU_NMI_INT1 GPIO_PCPU_NMI_INT1 0x80 32 read-write n 0x0 0x0 PROCPU_NMI_INT_H 0 8 PIN0 GPIO_PIN0 0x110 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN1 GPIO_PIN0 0x19C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN10 GPIO_PIN0 0x73C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN11 GPIO_PIN0 0x7F0 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN12 GPIO_PIN0 0x8A8 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN13 GPIO_PIN0 0x964 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN14 GPIO_PIN0 0xA24 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN15 GPIO_PIN0 0xAE8 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN16 GPIO_PIN0 0xBB0 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN17 GPIO_PIN0 0xC7C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN18 GPIO_PIN0 0xD4C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN19 GPIO_PIN0 0xE20 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN2 GPIO_PIN0 0x22C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN20 GPIO_PIN0 0xEF8 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN21 GPIO_PIN0 0xFD4 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN22 GPIO_PIN0 0x10B4 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN23 GPIO_PIN0 0x1198 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN24 GPIO_PIN0 0x1280 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN25 GPIO_PIN0 0x136C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN26 GPIO_PIN0 0x145C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN27 GPIO_PIN0 0x1550 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN28 GPIO_PIN0 0x1648 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN29 GPIO_PIN0 0x1744 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN3 GPIO_PIN0 0x2C0 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN30 GPIO_PIN0 0x1844 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN31 GPIO_PIN0 0x1948 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN32 GPIO_PIN0 0x1A50 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN33 GPIO_PIN0 0x1B5C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN34 GPIO_PIN0 0x1C6C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN35 GPIO_PIN0 0x1D80 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN36 GPIO_PIN0 0x1E98 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN37 GPIO_PIN0 0x1FB4 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN38 GPIO_PIN0 0x20D4 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN39 GPIO_PIN0 0x21F8 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN4 GPIO_PIN0 0x358 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN5 GPIO_PIN0 0x3F4 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN6 GPIO_PIN0 0x494 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN7 GPIO_PIN0 0x538 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN8 GPIO_PIN0 0x5E0 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN9 GPIO_PIN0 0x68C 32 read-write n 0x0 0x0 CONFIG 11 2 INT_ENA 13 5 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 SDIO_SELECT GPIO_SDIO_SELECT 0x1C 32 read-write n 0x0 0x0 SDIO_SEL 0 8 STATUS GPIO_STATUS 0x44 32 read-write n 0x0 0x0 STATUS_INT 0 32 STATUS1 GPIO_STATUS1 0x50 32 read-write n 0x0 0x0 STATUS1_INT 0 8 STATUS1_W1TC GPIO_STATUS1_W1TC 0x58 32 read-write n 0x0 0x0 STATUS1_INT_W1TC 0 8 STATUS1_W1TS GPIO_STATUS1_W1TS 0x54 32 read-write n 0x0 0x0 STATUS1_INT_W1TS 0 8 STATUS_W1TC GPIO_STATUS_W1TC 0x4C 32 read-write n 0x0 0x0 STATUS_INT_W1TC 0 32 STATUS_W1TS GPIO_STATUS_W1TS 0x48 32 read-write n 0x0 0x0 STATUS_INT_W1TS 0 32 STRAP GPIO_STRAP 0x38 32 read-write n 0x0 0x0 STRAPPING 0 16 GPIO_SD GPIO_SD 0x0 0x0 0x160 registers n SIGMADELTA0 GPIO_SIGMADELTA0 0x0 32 read-write n 0x0 0x0 SD0_IN 0 8 SD0_PRESCALE 8 8 SIGMADELTA1 GPIO_SIGMADELTA1 0x4 32 read-write n 0x0 0x0 SD1_IN 0 8 SD1_PRESCALE 8 8 SIGMADELTA2 GPIO_SIGMADELTA2 0x8 32 read-write n 0x0 0x0 SD2_IN 0 8 SD2_PRESCALE 8 8 SIGMADELTA3 GPIO_SIGMADELTA3 0xC 32 read-write n 0x0 0x0 SD3_IN 0 8 SD3_PRESCALE 8 8 SIGMADELTA4 GPIO_SIGMADELTA4 0x10 32 read-write n 0x0 0x0 SD4_IN 0 8 SD4_PRESCALE 8 8 SIGMADELTA5 GPIO_SIGMADELTA5 0x14 32 read-write n 0x0 0x0 SD5_IN 0 8 SD5_PRESCALE 8 8 SIGMADELTA6 GPIO_SIGMADELTA6 0x18 32 read-write n 0x0 0x0 SD6_IN 0 8 SD6_PRESCALE 8 8 SIGMADELTA7 GPIO_SIGMADELTA7 0x1C 32 read-write n 0x0 0x0 SD7_IN 0 8 SD7_PRESCALE 8 8 SIGMADELTA_CG GPIO_SIGMADELTA_CG 0x20 32 read-write n 0x0 0x0 SD_CLK_EN 31 1 SIGMADELTA_MISC GPIO_SIGMADELTA_MISC 0x24 32 read-write n 0x0 0x0 SPI_SWAP 31 1 SIGMADELTA_VERSION GPIO_SIGMADELTA_VERSION 0x28 32 read-write n 0x0 0x0 SD_DATE 0 28 HINF HINF 0x0 0x0 0x1A0 registers n CFG_DATA0 HINF_CFG_DATA0 0x0 32 read-write n 0x0 0x0 DEVICE_ID_FN1 16 16 USER_ID_FN1 0 16 CFG_DATA1 HINF_CFG_DATA1 0x4 32 read-write n 0x0 0x0 CD_DISABLE 8 1 EMP 10 1 FUNC1_EPS 9 1 FUNC2_EPS 28 1 HIGHSPEED_ENABLE 2 1 HIGHSPEED_MODE 3 1 IOENABLE1 11 1 IOENABLE2 7 1 SDIO20_CONF0 12 4 SDIO20_CONF1 29 3 SDIO_CD_ENABLE 4 1 SDIO_ENABLE 0 1 SDIO_INT_MASK 6 1 SDIO_IOREADY1 1 1 SDIO_IOREADY2 5 1 SDIO_VER 16 12 CFG_DATA16 HINF_CFG_DATA16 0x40 32 read-write n 0x0 0x0 DEVICE_ID_FN2 16 16 USER_ID_FN2 0 16 CFG_DATA7 HINF_CFG_DATA7 0x1C 32 read-write n 0x0 0x0 CHIP_STATE 8 8 PIN_STATE 0 8 SDIO_IOREADY0 17 1 SDIO_RST 16 1 CIS_CONF0 HINF_CIS_CONF0 0x20 32 read-write n 0x0 0x0 CIS_CONF_W0 0 32 CIS_CONF1 HINF_CIS_CONF1 0x24 32 read-write n 0x0 0x0 CIS_CONF_W1 0 32 CIS_CONF2 HINF_CIS_CONF2 0x28 32 read-write n 0x0 0x0 CIS_CONF_W2 0 32 CIS_CONF3 HINF_CIS_CONF3 0x2C 32 read-write n 0x0 0x0 CIS_CONF_W3 0 32 CIS_CONF4 HINF_CIS_CONF4 0x30 32 read-write n 0x0 0x0 CIS_CONF_W4 0 32 CIS_CONF5 HINF_CIS_CONF5 0x34 32 read-write n 0x0 0x0 CIS_CONF_W5 0 32 CIS_CONF6 HINF_CIS_CONF6 0x38 32 read-write n 0x0 0x0 CIS_CONF_W6 0 32 CIS_CONF7 HINF_CIS_CONF7 0x3C 32 read-write n 0x0 0x0 CIS_CONF_W7 0 32 DATE HINF_DATE 0xFC 32 read-write n 0x0 0x0 SDIO_DATE 0 32 I2C I2C 0x0 0x0 0x4C0 registers n PWM0_INTR interrupt of PWM0, level, Reserved 39 PWM1_INTR interrupt of PWM1, level, Reserved 40 PWM2_INTR interrupt of PWM2, level 41 PWM3_INTR interrupt of PWM3, level 42 I2C_EXT0_INTR interrupt of I2C controller0, level 49 I2C_EXT1_INTR interrupt of I2C controller1, level 50 COMD0 I2C_COMD0 0x58 32 read-write n 0x0 0x0 COMMAND0 0 14 COMMAND0_DONE 31 1 COMD1 I2C_COMD1 0x5C 32 read-write n 0x0 0x0 COMMAND1 0 14 COMMAND1_DONE 31 1 COMD10 I2C_COMD10 0x80 32 read-write n 0x0 0x0 COMMAND10 0 14 COMMAND10_DONE 31 1 COMD11 I2C_COMD11 0x84 32 read-write n 0x0 0x0 COMMAND11 0 14 COMMAND11_DONE 31 1 COMD12 I2C_COMD12 0x88 32 read-write n 0x0 0x0 COMMAND12 0 14 COMMAND12_DONE 31 1 COMD13 I2C_COMD13 0x8C 32 read-write n 0x0 0x0 COMMAND13 0 14 COMMAND13_DONE 31 1 COMD14 I2C_COMD14 0x90 32 read-write n 0x0 0x0 COMMAND14 0 14 COMMAND14_DONE 31 1 COMD15 I2C_COMD15 0x94 32 read-write n 0x0 0x0 COMMAND15 0 14 COMMAND15_DONE 31 1 COMD2 I2C_COMD2 0x60 32 read-write n 0x0 0x0 COMMAND2 0 14 COMMAND2_DONE 31 1 COMD3 I2C_COMD3 0x64 32 read-write n 0x0 0x0 COMMAND3 0 14 COMMAND3_DONE 31 1 COMD4 I2C_COMD4 0x68 32 read-write n 0x0 0x0 COMMAND4 0 14 COMMAND4_DONE 31 1 COMD5 I2C_COMD5 0x6C 32 read-write n 0x0 0x0 COMMAND5 0 14 COMMAND5_DONE 31 1 COMD6 I2C_COMD6 0x70 32 read-write n 0x0 0x0 COMMAND6 0 14 COMMAND6_DONE 31 1 COMD7 I2C_COMD7 0x74 32 read-write n 0x0 0x0 COMMAND7 0 14 COMMAND7_DONE 31 1 COMD8 I2C_COMD8 0x78 32 read-write n 0x0 0x0 COMMAND8 0 14 COMMAND8_DONE 31 1 COMD9 I2C_COMD9 0x7C 32 read-write n 0x0 0x0 COMMAND9 0 14 COMMAND9_DONE 31 1 CTR I2C_CTR 0x4 32 read-write n 0x0 0x0 CLK_EN 8 1 MS_MODE 4 1 RX_LSB_FIRST 7 1 SAMPLE_SCL_LEVEL 2 1 SCL_FORCE_OUT 1 1 SDA_FORCE_OUT 0 1 TRANS_START 5 1 TX_LSB_FIRST 6 1 DATA I2C_DATA 0x1C 32 read-write n 0x0 0x0 FIFO_RDATA 0 8 DATE I2C_DATE 0xF8 32 read-write n 0x0 0x0 DATE 0 32 FIFO_CONF I2C_FIFO_CONF 0x18 32 read-write n 0x0 0x0 FIFO_ADDR_CFG_EN 11 1 NONFIFO_EN 10 1 NONFIFO_RX_THRES 14 6 NONFIFO_TX_THRES 20 6 RXFIFO_FULL_THRHD 0 5 RX_FIFO_RST 12 1 TXFIFO_EMPTY_THRHD 5 5 TX_FIFO_RST 13 1 INT_CLR I2C_INT_CLR 0x24 32 read-write n 0x0 0x0 ACK_ERR_INT_CLR 10 1 ARBITRATION_LOST_INT_CLR 5 1 END_DETECT_INT_CLR 3 1 MASTER_TRAN_COMP_INT_CLR 6 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 2 1 RX_REC_FULL_INT_CLR 11 1 SLAVE_TRAN_COMP_INT_CLR 4 1 TIME_OUT_INT_CLR 8 1 TRANS_COMPLETE_INT_CLR 7 1 TRANS_START_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_SEND_EMPTY_INT_CLR 12 1 INT_ENA I2C_INT_ENA 0x28 32 read-write n 0x0 0x0 ACK_ERR_INT_ENA 10 1 ARBITRATION_LOST_INT_ENA 5 1 END_DETECT_INT_ENA 3 1 MASTER_TRAN_COMP_INT_ENA 6 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 2 1 RX_REC_FULL_INT_ENA 11 1 SLAVE_TRAN_COMP_INT_ENA 4 1 TIME_OUT_INT_ENA 8 1 TRANS_COMPLETE_INT_ENA 7 1 TRANS_START_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_SEND_EMPTY_INT_ENA 12 1 INT_RAW I2C_INT_RAW 0x20 32 read-write n 0x0 0x0 ACK_ERR_INT_RAW 10 1 ARBITRATION_LOST_INT_RAW 5 1 END_DETECT_INT_RAW 3 1 MASTER_TRAN_COMP_INT_RAW 6 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 2 1 RX_REC_FULL_INT_RAW 11 1 SLAVE_TRAN_COMP_INT_RAW 4 1 TIME_OUT_INT_RAW 8 1 TRANS_COMPLETE_INT_RAW 7 1 TRANS_START_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_SEND_EMPTY_INT_RAW 12 1 INT_STATUS I2C_INT_STATUS 0x2C 32 read-write n 0x0 0x0 ACK_ERR_INT_ST 10 1 ARBITRATION_LOST_INT_ST 5 1 END_DETECT_INT_ST 3 1 MASTER_TRAN_COMP_INT_ST 6 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 2 1 RX_REC_FULL_INT_ST 11 1 SLAVE_TRAN_COMP_INT_ST 4 1 TIME_OUT_INT_ST 8 1 TRANS_COMPLETE_INT_ST 7 1 TRANS_START_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_SEND_EMPTY_INT_ST 12 1 RXFIFO_ST I2C_RXFIFO_ST 0x14 32 read-write n 0x0 0x0 RXFIFO_END_ADDR 5 5 RXFIFO_START_ADDR 0 5 TXFIFO_END_ADDR 15 5 TXFIFO_START_ADDR 10 5 SCL_FILTER_CFG I2C_SCL_FILTER_CFG 0x50 32 read-write n 0x0 0x0 SCL_FILTER_EN 3 1 SCL_FILTER_THRES 0 3 SCL_HIGH_PERIOD I2C_SCL_HIGH_PERIOD 0x38 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_LOW_PERIOD I2C_SCL_LOW_PERIOD 0x0 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_RSTART_SETUP I2C_SCL_RSTART_SETUP 0x44 32 read-write n 0x0 0x0 TIME 0 10 SCL_START_HOLD I2C_SCL_START_HOLD 0x40 32 read-write n 0x0 0x0 TIME 0 10 SCL_STOP_HOLD I2C_SCL_STOP_HOLD 0x48 32 read-write n 0x0 0x0 TIME 0 14 SCL_STOP_SETUP I2C_SCL_STOP_SETUP 0x4C 32 read-write n 0x0 0x0 TIME 0 10 SDA_FILTER_CFG I2C_SDA_FILTER_CFG 0x54 32 read-write n 0x0 0x0 SDA_FILTER_EN 3 1 SDA_FILTER_THRES 0 3 SDA_HOLD I2C_SDA_HOLD 0x30 32 read-write n 0x0 0x0 TIME 0 10 SDA_SAMPLE I2C_SDA_SAMPLE 0x34 32 read-write n 0x0 0x0 TIME 0 10 SLAVE_ADDR I2C_SLAVE_ADDR 0x10 32 read-write n 0x0 0x0 ADDR_10BIT_EN 31 1 SLAVE_ADDR 0 15 SR I2C_SR 0x8 32 read-write n 0x0 0x0 ACK_REC 0 1 ARB_LOST 3 1 BUS_BUSY 4 1 BYTE_TRANS 6 1 RXFIFO_CNT 8 6 SCL_MAIN_STATE_LAST 24 3 SCL_STATE_LAST 28 3 SLAVE_ADDRESSED 5 1 SLAVE_RW 1 1 TIME_OUT 2 1 TXFIFO_CNT 18 6 TO I2C_TO 0xC 32 read-write n 0x0 0x0 TIME_OUT_REG 0 20 I2C0 I2C 0x0 0x0 0x4C0 registers n COMD0 I2C_COMD0 0x58 32 read-write n 0x0 0x0 COMMAND0 0 14 COMMAND0_DONE 31 1 COMD1 I2C_COMD1 0x5C 32 read-write n 0x0 0x0 COMMAND1 0 14 COMMAND1_DONE 31 1 COMD10 I2C_COMD10 0x80 32 read-write n 0x0 0x0 COMMAND10 0 14 COMMAND10_DONE 31 1 COMD11 I2C_COMD11 0x84 32 read-write n 0x0 0x0 COMMAND11 0 14 COMMAND11_DONE 31 1 COMD12 I2C_COMD12 0x88 32 read-write n 0x0 0x0 COMMAND12 0 14 COMMAND12_DONE 31 1 COMD13 I2C_COMD13 0x8C 32 read-write n 0x0 0x0 COMMAND13 0 14 COMMAND13_DONE 31 1 COMD14 I2C_COMD14 0x90 32 read-write n 0x0 0x0 COMMAND14 0 14 COMMAND14_DONE 31 1 COMD15 I2C_COMD15 0x94 32 read-write n 0x0 0x0 COMMAND15 0 14 COMMAND15_DONE 31 1 COMD2 I2C_COMD2 0x60 32 read-write n 0x0 0x0 COMMAND2 0 14 COMMAND2_DONE 31 1 COMD3 I2C_COMD3 0x64 32 read-write n 0x0 0x0 COMMAND3 0 14 COMMAND3_DONE 31 1 COMD4 I2C_COMD4 0x68 32 read-write n 0x0 0x0 COMMAND4 0 14 COMMAND4_DONE 31 1 COMD5 I2C_COMD5 0x6C 32 read-write n 0x0 0x0 COMMAND5 0 14 COMMAND5_DONE 31 1 COMD6 I2C_COMD6 0x70 32 read-write n 0x0 0x0 COMMAND6 0 14 COMMAND6_DONE 31 1 COMD7 I2C_COMD7 0x74 32 read-write n 0x0 0x0 COMMAND7 0 14 COMMAND7_DONE 31 1 COMD8 I2C_COMD8 0x78 32 read-write n 0x0 0x0 COMMAND8 0 14 COMMAND8_DONE 31 1 COMD9 I2C_COMD9 0x7C 32 read-write n 0x0 0x0 COMMAND9 0 14 COMMAND9_DONE 31 1 CTR I2C_CTR 0x4 32 read-write n 0x0 0x0 CLK_EN 8 1 MS_MODE 4 1 RX_LSB_FIRST 7 1 SAMPLE_SCL_LEVEL 2 1 SCL_FORCE_OUT 1 1 SDA_FORCE_OUT 0 1 TRANS_START 5 1 TX_LSB_FIRST 6 1 DATA I2C_DATA 0x1C 32 read-write n 0x0 0x0 FIFO_RDATA 0 8 DATE I2C_DATE 0xF8 32 read-write n 0x0 0x0 DATE 0 32 FIFO_CONF I2C_FIFO_CONF 0x18 32 read-write n 0x0 0x0 FIFO_ADDR_CFG_EN 11 1 NONFIFO_EN 10 1 NONFIFO_RX_THRES 14 6 NONFIFO_TX_THRES 20 6 RXFIFO_FULL_THRHD 0 5 RX_FIFO_RST 12 1 TXFIFO_EMPTY_THRHD 5 5 TX_FIFO_RST 13 1 INT_CLR I2C_INT_CLR 0x24 32 read-write n 0x0 0x0 ACK_ERR_INT_CLR 10 1 ARBITRATION_LOST_INT_CLR 5 1 END_DETECT_INT_CLR 3 1 MASTER_TRAN_COMP_INT_CLR 6 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 2 1 RX_REC_FULL_INT_CLR 11 1 SLAVE_TRAN_COMP_INT_CLR 4 1 TIME_OUT_INT_CLR 8 1 TRANS_COMPLETE_INT_CLR 7 1 TRANS_START_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_SEND_EMPTY_INT_CLR 12 1 INT_ENA I2C_INT_ENA 0x28 32 read-write n 0x0 0x0 ACK_ERR_INT_ENA 10 1 ARBITRATION_LOST_INT_ENA 5 1 END_DETECT_INT_ENA 3 1 MASTER_TRAN_COMP_INT_ENA 6 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 2 1 RX_REC_FULL_INT_ENA 11 1 SLAVE_TRAN_COMP_INT_ENA 4 1 TIME_OUT_INT_ENA 8 1 TRANS_COMPLETE_INT_ENA 7 1 TRANS_START_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_SEND_EMPTY_INT_ENA 12 1 INT_RAW I2C_INT_RAW 0x20 32 read-write n 0x0 0x0 ACK_ERR_INT_RAW 10 1 ARBITRATION_LOST_INT_RAW 5 1 END_DETECT_INT_RAW 3 1 MASTER_TRAN_COMP_INT_RAW 6 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 2 1 RX_REC_FULL_INT_RAW 11 1 SLAVE_TRAN_COMP_INT_RAW 4 1 TIME_OUT_INT_RAW 8 1 TRANS_COMPLETE_INT_RAW 7 1 TRANS_START_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_SEND_EMPTY_INT_RAW 12 1 INT_STATUS I2C_INT_STATUS 0x2C 32 read-write n 0x0 0x0 ACK_ERR_INT_ST 10 1 ARBITRATION_LOST_INT_ST 5 1 END_DETECT_INT_ST 3 1 MASTER_TRAN_COMP_INT_ST 6 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 2 1 RX_REC_FULL_INT_ST 11 1 SLAVE_TRAN_COMP_INT_ST 4 1 TIME_OUT_INT_ST 8 1 TRANS_COMPLETE_INT_ST 7 1 TRANS_START_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_SEND_EMPTY_INT_ST 12 1 RXFIFO_ST I2C_RXFIFO_ST 0x14 32 read-write n 0x0 0x0 RXFIFO_END_ADDR 5 5 RXFIFO_START_ADDR 0 5 TXFIFO_END_ADDR 15 5 TXFIFO_START_ADDR 10 5 SCL_FILTER_CFG I2C_SCL_FILTER_CFG 0x50 32 read-write n 0x0 0x0 SCL_FILTER_EN 3 1 SCL_FILTER_THRES 0 3 SCL_HIGH_PERIOD I2C_SCL_HIGH_PERIOD 0x38 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_LOW_PERIOD I2C_SCL_LOW_PERIOD 0x0 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_RSTART_SETUP I2C_SCL_RSTART_SETUP 0x44 32 read-write n 0x0 0x0 TIME 0 10 SCL_START_HOLD I2C_SCL_START_HOLD 0x40 32 read-write n 0x0 0x0 TIME 0 10 SCL_STOP_HOLD I2C_SCL_STOP_HOLD 0x48 32 read-write n 0x0 0x0 TIME 0 14 SCL_STOP_SETUP I2C_SCL_STOP_SETUP 0x4C 32 read-write n 0x0 0x0 TIME 0 10 SDA_FILTER_CFG I2C_SDA_FILTER_CFG 0x54 32 read-write n 0x0 0x0 SDA_FILTER_EN 3 1 SDA_FILTER_THRES 0 3 SDA_HOLD I2C_SDA_HOLD 0x30 32 read-write n 0x0 0x0 TIME 0 10 SDA_SAMPLE I2C_SDA_SAMPLE 0x34 32 read-write n 0x0 0x0 TIME 0 10 SLAVE_ADDR I2C_SLAVE_ADDR 0x10 32 read-write n 0x0 0x0 ADDR_10BIT_EN 31 1 SLAVE_ADDR 0 15 SR I2C_SR 0x8 32 read-write n 0x0 0x0 ACK_REC 0 1 ARB_LOST 3 1 BUS_BUSY 4 1 BYTE_TRANS 6 1 RXFIFO_CNT 8 6 SCL_MAIN_STATE_LAST 24 3 SCL_STATE_LAST 28 3 SLAVE_ADDRESSED 5 1 SLAVE_RW 1 1 TIME_OUT 2 1 TXFIFO_CNT 18 6 TO I2C_TO 0xC 32 read-write n 0x0 0x0 TIME_OUT_REG 0 20 I2C1 I2C 0x0 0x0 0x4C0 registers n COMD0 I2C_COMD0 0x58 32 read-write n 0x0 0x0 COMMAND0 0 14 COMMAND0_DONE 31 1 COMD1 I2C_COMD1 0x5C 32 read-write n 0x0 0x0 COMMAND1 0 14 COMMAND1_DONE 31 1 COMD10 I2C_COMD10 0x80 32 read-write n 0x0 0x0 COMMAND10 0 14 COMMAND10_DONE 31 1 COMD11 I2C_COMD11 0x84 32 read-write n 0x0 0x0 COMMAND11 0 14 COMMAND11_DONE 31 1 COMD12 I2C_COMD12 0x88 32 read-write n 0x0 0x0 COMMAND12 0 14 COMMAND12_DONE 31 1 COMD13 I2C_COMD13 0x8C 32 read-write n 0x0 0x0 COMMAND13 0 14 COMMAND13_DONE 31 1 COMD14 I2C_COMD14 0x90 32 read-write n 0x0 0x0 COMMAND14 0 14 COMMAND14_DONE 31 1 COMD15 I2C_COMD15 0x94 32 read-write n 0x0 0x0 COMMAND15 0 14 COMMAND15_DONE 31 1 COMD2 I2C_COMD2 0x60 32 read-write n 0x0 0x0 COMMAND2 0 14 COMMAND2_DONE 31 1 COMD3 I2C_COMD3 0x64 32 read-write n 0x0 0x0 COMMAND3 0 14 COMMAND3_DONE 31 1 COMD4 I2C_COMD4 0x68 32 read-write n 0x0 0x0 COMMAND4 0 14 COMMAND4_DONE 31 1 COMD5 I2C_COMD5 0x6C 32 read-write n 0x0 0x0 COMMAND5 0 14 COMMAND5_DONE 31 1 COMD6 I2C_COMD6 0x70 32 read-write n 0x0 0x0 COMMAND6 0 14 COMMAND6_DONE 31 1 COMD7 I2C_COMD7 0x74 32 read-write n 0x0 0x0 COMMAND7 0 14 COMMAND7_DONE 31 1 COMD8 I2C_COMD8 0x78 32 read-write n 0x0 0x0 COMMAND8 0 14 COMMAND8_DONE 31 1 COMD9 I2C_COMD9 0x7C 32 read-write n 0x0 0x0 COMMAND9 0 14 COMMAND9_DONE 31 1 CTR I2C_CTR 0x4 32 read-write n 0x0 0x0 CLK_EN 8 1 MS_MODE 4 1 RX_LSB_FIRST 7 1 SAMPLE_SCL_LEVEL 2 1 SCL_FORCE_OUT 1 1 SDA_FORCE_OUT 0 1 TRANS_START 5 1 TX_LSB_FIRST 6 1 DATA I2C_DATA 0x1C 32 read-write n 0x0 0x0 FIFO_RDATA 0 8 DATE I2C_DATE 0xF8 32 read-write n 0x0 0x0 DATE 0 32 FIFO_CONF I2C_FIFO_CONF 0x18 32 read-write n 0x0 0x0 FIFO_ADDR_CFG_EN 11 1 NONFIFO_EN 10 1 NONFIFO_RX_THRES 14 6 NONFIFO_TX_THRES 20 6 RXFIFO_FULL_THRHD 0 5 RX_FIFO_RST 12 1 TXFIFO_EMPTY_THRHD 5 5 TX_FIFO_RST 13 1 INT_CLR I2C_INT_CLR 0x24 32 read-write n 0x0 0x0 ACK_ERR_INT_CLR 10 1 ARBITRATION_LOST_INT_CLR 5 1 END_DETECT_INT_CLR 3 1 MASTER_TRAN_COMP_INT_CLR 6 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 2 1 RX_REC_FULL_INT_CLR 11 1 SLAVE_TRAN_COMP_INT_CLR 4 1 TIME_OUT_INT_CLR 8 1 TRANS_COMPLETE_INT_CLR 7 1 TRANS_START_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_SEND_EMPTY_INT_CLR 12 1 INT_ENA I2C_INT_ENA 0x28 32 read-write n 0x0 0x0 ACK_ERR_INT_ENA 10 1 ARBITRATION_LOST_INT_ENA 5 1 END_DETECT_INT_ENA 3 1 MASTER_TRAN_COMP_INT_ENA 6 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 2 1 RX_REC_FULL_INT_ENA 11 1 SLAVE_TRAN_COMP_INT_ENA 4 1 TIME_OUT_INT_ENA 8 1 TRANS_COMPLETE_INT_ENA 7 1 TRANS_START_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_SEND_EMPTY_INT_ENA 12 1 INT_RAW I2C_INT_RAW 0x20 32 read-write n 0x0 0x0 ACK_ERR_INT_RAW 10 1 ARBITRATION_LOST_INT_RAW 5 1 END_DETECT_INT_RAW 3 1 MASTER_TRAN_COMP_INT_RAW 6 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 2 1 RX_REC_FULL_INT_RAW 11 1 SLAVE_TRAN_COMP_INT_RAW 4 1 TIME_OUT_INT_RAW 8 1 TRANS_COMPLETE_INT_RAW 7 1 TRANS_START_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_SEND_EMPTY_INT_RAW 12 1 INT_STATUS I2C_INT_STATUS 0x2C 32 read-write n 0x0 0x0 ACK_ERR_INT_ST 10 1 ARBITRATION_LOST_INT_ST 5 1 END_DETECT_INT_ST 3 1 MASTER_TRAN_COMP_INT_ST 6 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 2 1 RX_REC_FULL_INT_ST 11 1 SLAVE_TRAN_COMP_INT_ST 4 1 TIME_OUT_INT_ST 8 1 TRANS_COMPLETE_INT_ST 7 1 TRANS_START_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_SEND_EMPTY_INT_ST 12 1 RXFIFO_ST I2C_RXFIFO_ST 0x14 32 read-write n 0x0 0x0 RXFIFO_END_ADDR 5 5 RXFIFO_START_ADDR 0 5 TXFIFO_END_ADDR 15 5 TXFIFO_START_ADDR 10 5 SCL_FILTER_CFG I2C_SCL_FILTER_CFG 0x50 32 read-write n 0x0 0x0 SCL_FILTER_EN 3 1 SCL_FILTER_THRES 0 3 SCL_HIGH_PERIOD I2C_SCL_HIGH_PERIOD 0x38 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_LOW_PERIOD I2C_SCL_LOW_PERIOD 0x0 32 read-write n 0x0 0x0 PERIOD 0 14 SCL_RSTART_SETUP I2C_SCL_RSTART_SETUP 0x44 32 read-write n 0x0 0x0 TIME 0 10 SCL_START_HOLD I2C_SCL_START_HOLD 0x40 32 read-write n 0x0 0x0 TIME 0 10 SCL_STOP_HOLD I2C_SCL_STOP_HOLD 0x48 32 read-write n 0x0 0x0 TIME 0 14 SCL_STOP_SETUP I2C_SCL_STOP_SETUP 0x4C 32 read-write n 0x0 0x0 TIME 0 10 SDA_FILTER_CFG I2C_SDA_FILTER_CFG 0x54 32 read-write n 0x0 0x0 SDA_FILTER_EN 3 1 SDA_FILTER_THRES 0 3 SDA_HOLD I2C_SDA_HOLD 0x30 32 read-write n 0x0 0x0 TIME 0 10 SDA_SAMPLE I2C_SDA_SAMPLE 0x34 32 read-write n 0x0 0x0 TIME 0 10 SLAVE_ADDR I2C_SLAVE_ADDR 0x10 32 read-write n 0x0 0x0 ADDR_10BIT_EN 31 1 SLAVE_ADDR 0 15 SR I2C_SR 0x8 32 read-write n 0x0 0x0 ACK_REC 0 1 ARB_LOST 3 1 BUS_BUSY 4 1 BYTE_TRANS 6 1 RXFIFO_CNT 8 6 SCL_MAIN_STATE_LAST 24 3 SCL_STATE_LAST 28 3 SLAVE_ADDRESSED 5 1 SLAVE_RW 1 1 TIME_OUT 2 1 TXFIFO_CNT 18 6 TO I2C_TO 0xC 32 read-write n 0x0 0x0 TIME_OUT_REG 0 20 I2S I2S 0x0 0x0 0x5A0 registers n I2S0_INTR interrupt of I2S0, level 32 I2S1_INTR interrupt of I2S1, level 33 AHB_TEST I2S_AHB_TEST 0x44 32 read-write n 0x0 0x0 AHB_TESTADDR 4 2 AHB_TESTMODE 0 3 CLKM_CONF I2S_CLKM_CONF 0xAC 32 read-write n 0x0 0x0 CLKA_ENA 21 1 CLKM_DIV_A 14 6 CLKM_DIV_B 8 6 CLKM_DIV_NUM 0 8 CLK_EN 20 1 CONF I2S_CONF 0x8 32 read-write n 0x0 0x0 RX_FIFO_RESET 3 1 RX_MONO 15 1 RX_MSB_RIGHT 17 1 RX_MSB_SHIFT 11 1 RX_RESET 1 1 RX_RIGHT_FIRST 9 1 RX_SHORT_SYNC 13 1 RX_SLAVE_MOD 7 1 RX_START 5 1 SIG_LOOPBACK 18 1 TX_FIFO_RESET 2 1 TX_MONO 14 1 TX_MSB_RIGHT 16 1 TX_MSB_SHIFT 10 1 TX_RESET 0 1 TX_RIGHT_FIRST 8 1 TX_SHORT_SYNC 12 1 TX_SLAVE_MOD 6 1 TX_START 4 1 CONF1 I2S_CONF1 0xA0 32 read-write n 0x0 0x0 RX_PCM_BYPASS 7 1 RX_PCM_CONF 4 3 TX_PCM_BYPASS 3 1 TX_PCM_CONF 0 3 TX_STOP_EN 8 1 TX_ZEROS_RM_EN 9 1 CONF2 I2S_CONF2 0xA8 32 read-write n 0x0 0x0 CAMERA_EN 0 1 DATA_ENABLE 4 1 DATA_ENABLE_TEST_EN 3 1 EXT_ADC_START_EN 6 1 INTER_VALID_EN 7 1 LCD_EN 5 1 LCD_TX_SDX2_EN 2 1 LCD_TX_WRX2_EN 1 1 CONF_CHAN I2S_CONF_CHAN 0x2C 32 read-write n 0x0 0x0 RX_CHAN_MOD 3 2 TX_CHAN_MOD 0 3 CONF_SIGLE_DATA I2S_CONF_SIGLE_DATA 0x28 32 read-write n 0x0 0x0 SIGLE_DATA 0 32 CVSD_CONF0 I2S_CVSD_CONF0 0x80 32 read-write n 0x0 0x0 CVSD_Y_MAX 0 16 CVSD_Y_MIN 16 16 CVSD_CONF1 I2S_CVSD_CONF1 0x84 32 read-write n 0x0 0x0 CVSD_SIGMA_MAX 0 16 CVSD_SIGMA_MIN 16 16 CVSD_CONF2 I2S_CVSD_CONF2 0x88 32 read-write n 0x0 0x0 CVSD_BETA 6 10 CVSD_H 16 3 CVSD_J 3 3 CVSD_K 0 3 DATE I2S_DATE 0xFC 32 read-write n 0x0 0x0 I2SDATE 0 32 ESCO_CONF0 I2S_ESCO_CONF0 0x98 32 read-write n 0x0 0x0 CVSD_DEC_RESET 10 1 CVSD_DEC_START 9 1 ESCO_CHAN_MOD 1 1 ESCO_CVSD_DEC_PACK_ERR 2 1 ESCO_CVSD_INF_EN 8 1 ESCO_CVSD_PACK_LEN_8K 3 5 ESCO_EN 0 1 PLC2DMA_EN 12 1 PLC_EN 11 1 FIFO_CONF I2S_FIFO_CONF 0x20 32 read-write n 0x0 0x0 DSCR_EN 12 1 RX_DATA_NUM 0 6 RX_FIFO_MOD 16 3 RX_FIFO_MOD_FORCE_EN 20 1 TX_DATA_NUM 6 6 TX_FIFO_MOD 13 3 TX_FIFO_MOD_FORCE_EN 19 1 INFIFO_POP I2S_INFIFO_POP 0x68 32 read-write n 0x0 0x0 INFIFO_POP 16 1 INFIFO_RDATA 0 12 INLINK_DSCR I2S_INLINK_DSCR 0x48 32 read-write n 0x0 0x0 INLINK_DSCR 0 32 INLINK_DSCR_BF0 I2S_INLINK_DSCR_BF0 0x4C 32 read-write n 0x0 0x0 INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 I2S_INLINK_DSCR_BF1 0x50 32 read-write n 0x0 0x0 INLINK_DSCR_BF1 0 32 INT_CLR I2S_INT_CLR 0x18 32 read-write n 0x0 0x0 IN_DONE_INT_CLR 8 1 IN_DSCR_EMPTY_INT_CLR 15 1 IN_DSCR_ERR_INT_CLR 13 1 IN_ERR_EOF_INT_CLR 10 1 IN_SUC_EOF_INT_CLR 9 1 OUT_DONE_INT_CLR 11 1 OUT_DSCR_ERR_INT_CLR 14 1 OUT_EOF_INT_CLR 12 1 OUT_TOTAL_EOF_INT_CLR 16 1 PUT_DATA_INT_CLR 1 1 RX_HUNG_INT_CLR 6 1 RX_REMPTY_INT_CLR 3 1 RX_WFULL_INT_CLR 2 1 TAKE_DATA_INT_CLR 0 1 TX_HUNG_INT_CLR 7 1 TX_REMPTY_INT_CLR 5 1 TX_WFULL_INT_CLR 4 1 INT_ENA I2S_INT_ENA 0x14 32 read-write n 0x0 0x0 IN_DONE_INT_ENA 8 1 IN_DSCR_EMPTY_INT_ENA 15 1 IN_DSCR_ERR_INT_ENA 13 1 IN_ERR_EOF_INT_ENA 10 1 IN_SUC_EOF_INT_ENA 9 1 OUT_DONE_INT_ENA 11 1 OUT_DSCR_ERR_INT_ENA 14 1 OUT_EOF_INT_ENA 12 1 OUT_TOTAL_EOF_INT_ENA 16 1 RX_HUNG_INT_ENA 6 1 RX_REMPTY_INT_ENA 3 1 RX_TAKE_DATA_INT_ENA 0 1 RX_WFULL_INT_ENA 2 1 TX_HUNG_INT_ENA 7 1 TX_PUT_DATA_INT_ENA 1 1 TX_REMPTY_INT_ENA 5 1 TX_WFULL_INT_ENA 4 1 INT_RAW I2S_INT_RAW 0xC 32 read-write n 0x0 0x0 IN_DONE_INT_RAW 8 1 IN_DSCR_EMPTY_INT_RAW 15 1 IN_DSCR_ERR_INT_RAW 13 1 IN_ERR_EOF_INT_RAW 10 1 IN_SUC_EOF_INT_RAW 9 1 OUT_DONE_INT_RAW 11 1 OUT_DSCR_ERR_INT_RAW 14 1 OUT_EOF_INT_RAW 12 1 OUT_TOTAL_EOF_INT_RAW 16 1 RX_HUNG_INT_RAW 6 1 RX_REMPTY_INT_RAW 3 1 RX_TAKE_DATA_INT_RAW 0 1 RX_WFULL_INT_RAW 2 1 TX_HUNG_INT_RAW 7 1 TX_PUT_DATA_INT_RAW 1 1 TX_REMPTY_INT_RAW 5 1 TX_WFULL_INT_RAW 4 1 INT_ST I2S_INT_ST 0x10 32 read-write n 0x0 0x0 IN_DONE_INT_ST 8 1 IN_DSCR_EMPTY_INT_ST 15 1 IN_DSCR_ERR_INT_ST 13 1 IN_ERR_EOF_INT_ST 10 1 IN_SUC_EOF_INT_ST 9 1 OUT_DONE_INT_ST 11 1 OUT_DSCR_ERR_INT_ST 14 1 OUT_EOF_INT_ST 12 1 OUT_TOTAL_EOF_INT_ST 16 1 RX_HUNG_INT_ST 6 1 RX_REMPTY_INT_ST 3 1 RX_TAKE_DATA_INT_ST 0 1 RX_WFULL_INT_ST 2 1 TX_HUNG_INT_ST 7 1 TX_PUT_DATA_INT_ST 1 1 TX_REMPTY_INT_ST 5 1 TX_WFULL_INT_ST 4 1 IN_EOF_DES_ADDR I2S_IN_EOF_DES_ADDR 0x3C 32 read-write n 0x0 0x0 IN_SUC_EOF_DES_ADDR 0 32 IN_LINK I2S_IN_LINK 0x34 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_PARK 31 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 LC_CONF I2S_LC_CONF 0x60 32 read-write n 0x0 0x0 AHBM_FIFO_RST 2 1 AHBM_RST 3 1 CHECK_OWNER 12 1 INDSCR_BURST_EN 10 1 IN_LOOP_TEST 5 1 IN_RST 0 1 MEM_TRANS_EN 13 1 OUTDSCR_BURST_EN 9 1 OUT_AUTO_WRBACK 6 1 OUT_DATA_BURST_EN 11 1 OUT_EOF_MODE 8 1 OUT_LOOP_TEST 4 1 OUT_NO_RESTART_CLR 7 1 OUT_RST 1 1 LC_HUNG_CONF I2S_LC_HUNG_CONF 0x74 32 read-write n 0x0 0x0 LC_FIFO_TIMEOUT 0 8 LC_FIFO_TIMEOUT_ENA 11 1 LC_FIFO_TIMEOUT_SHIFT 8 3 LC_STATE0 I2S_LC_STATE0 0x6C 32 read-write n 0x0 0x0 LC_STATE0 0 32 LC_STATE1 I2S_LC_STATE1 0x70 32 read-write n 0x0 0x0 LC_STATE1 0 32 OUTFIFO_PUSH I2S_OUTFIFO_PUSH 0x64 32 read-write n 0x0 0x0 OUTFIFO_PUSH 16 1 OUTFIFO_WDATA 0 9 OUTLINK_DSCR I2S_OUTLINK_DSCR 0x54 32 read-write n 0x0 0x0 OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 I2S_OUTLINK_DSCR_BF0 0x58 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 I2S_OUTLINK_DSCR_BF1 0x5C 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR I2S_OUT_EOF_BFR_DES_ADDR 0x40 32 read-write n 0x0 0x0 OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR I2S_OUT_EOF_DES_ADDR 0x38 32 read-write n 0x0 0x0 OUT_EOF_DES_ADDR 0 32 OUT_LINK I2S_OUT_LINK 0x30 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_PARK 31 1 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 PDM_CONF I2S_PDM_CONF 0xB4 32 read-write n 0x0 0x0 PCM2PDM_CONV_EN 2 1 PDM2PCM_CONV_EN 3 1 RX_PDM_EN 1 1 RX_PDM_SINC_DSR_16_EN 24 1 TX_PDM_EN 0 1 TX_PDM_HP_BYPASS 25 1 TX_PDM_HP_IN_SHIFT 16 2 TX_PDM_LP_IN_SHIFT 18 2 TX_PDM_PRESCALE 8 8 TX_PDM_SIGMADELTA_IN_SHIFT 22 2 TX_PDM_SINC_IN_SHIFT 20 2 TX_PDM_SINC_OSR2 4 4 PDM_FREQ_CONF I2S_PDM_FREQ_CONF 0xB8 32 read-write n 0x0 0x0 TX_PDM_FP 10 10 TX_PDM_FS 0 10 PD_CONF I2S_PD_CONF 0xA4 32 read-write n 0x0 0x0 FIFO_FORCE_PD 0 1 FIFO_FORCE_PU 1 1 PLC_MEM_FORCE_PD 2 1 PLC_MEM_FORCE_PU 3 1 PLC_CONF0 I2S_PLC_CONF0 0x8C 32 read-write n 0x0 0x0 GOOD_PACK_MAX 0 6 MAX_SLIDE_SAMPLE 12 8 N_ERR_SEG 6 3 N_MIN_ERR 25 3 PACK_LEN_8K 20 5 SHIFT_RATE 9 3 PLC_CONF1 I2S_PLC_CONF1 0x90 32 read-write n 0x0 0x0 BAD_CEF_ATTEN_PARA 0 8 BAD_CEF_ATTEN_PARA_SHIFT 8 4 BAD_OLA_WIN2_PARA 16 8 BAD_OLA_WIN2_PARA_SHIFT 12 4 SLIDE_WIN_LEN 24 8 PLC_CONF2 I2S_PLC_CONF2 0x94 32 read-write n 0x0 0x0 CVSD_SEG_MOD 0 2 MIN_PERIOD 2 5 RXEOF_NUM I2S_RXEOF_NUM 0x24 32 read-write n 0x0 0x0 RX_EOF_NUM 0 32 SAMPLE_RATE_CONF I2S_SAMPLE_RATE_CONF 0xB0 32 read-write n 0x0 0x0 RX_BCK_DIV_NUM 6 6 RX_BITS_MOD 18 6 TX_BCK_DIV_NUM 0 6 TX_BITS_MOD 12 6 SCO_CONF0 I2S_SCO_CONF0 0x9C 32 read-write n 0x0 0x0 CVSD_ENC_RESET 3 1 CVSD_ENC_START 2 1 SCO_NO_I2S_EN 1 1 SCO_WITH_I2S_EN 0 1 STATE I2S_STATE 0xBC 32 read-write n 0x0 0x0 RX_FIFO_RESET_BACK 2 1 TX_FIFO_RESET_BACK 1 1 TX_IDLE 0 1 TIMING I2S_TIMING 0x1C 32 read-write n 0x0 0x0 DATA_ENABLE_DELAY 22 2 RX_BCK_IN_DELAY 4 2 RX_BCK_OUT_DELAY 18 2 RX_DSYNC_SW 21 1 RX_SD_IN_DELAY 8 2 RX_WS_IN_DELAY 6 2 RX_WS_OUT_DELAY 16 2 TX_BCK_IN_DELAY 0 2 TX_BCK_IN_INV 24 1 TX_BCK_OUT_DELAY 10 2 TX_DSYNC_SW 20 1 TX_SD_OUT_DELAY 14 2 TX_WS_IN_DELAY 2 2 TX_WS_OUT_DELAY 12 2 I2S1 I2S1 0x0 0x0 0x0 registers n IO_MUX IO_MUX 0x0 0x0 0x0 registers n GPIO0 configures IO_MUX for GPIO0 0x44 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO16 configures IO_MUX for GPIO16 0x4C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO17 configures IO_MUX for GPIO17 0x50 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO18 configures IO_MUX for GPIO18 0x70 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO19 configures IO_MUX for GPIO19 0x74 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO2 configures IO_MUX for GPIO2 0x40 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO20 configures IO_MUX for GPIO20 0x78 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO21 configures IO_MUX for GPIO21 0x7C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO22 configures IO_MUX for GPIO22 0x80 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO23 configures IO_MUX for GPIO23 0x8C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO24 configures IO_MUX for GPIO24 0x90 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO25 configures IO_MUX for GPIO25 0x24 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO26 configures IO_MUX for GPIO26 0x28 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO27 configures IO_MUX for GPIO27 0x2C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO32 configures IO_MUX for GPIO32 0x1C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO33 configures IO_MUX for GPIO33 0x20 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO34 configures IO_MUX for GPIO34 0x14 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures drive strength during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO35 configures IO_MUX for GPIO35 0x18 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO36 configures IO_MUX for GPIO36 0x4 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO37 configures IO_MUX for GPIO37 0x8 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO38 configures IO_MUX for GPIO38 0xC 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO39 configures IO_MUX for GPIO39 0x10 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO4 configures IO_MUX for GPIO4 0x48 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 GPIO5 configures IO_MUX for GPIO5 0x6C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 MTCK configures IO_MUX for MTCK 0x38 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 MTDI configures IO_MUX for MTDI 0x34 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 MTDO configures IO_MUX for MTDO 0x3C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 MTMS configures IO_MUX for MTMS 0x30 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 PIN_CTRL configures clock source and clock output pins 0x0 32 read-write n 0x0 0x0 PIN_CTRL_CLK1 0 3 PIN_CTRL_CLK2 4 3 PIN_CTRL_CLK3 8 3 SD_CLK configures IO_MUX for SD_CLK 0x60 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 SD_CMD configures IO_MUX for SD_CMD 0x5C 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 SD_DATA0 configures IO_MUX for SD_DATA0 0x64 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 SD_DATA1 configures IO_MUX for SD_DATA1 0x68 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 SD_DATA2 configures IO_MUX for SD_DATA2 0x54 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 SD_DATA3 configures IO_MUX for SD_DATA3 0x58 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 U0RXD configures IO_MUX for U0RXD 0x84 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 U0TXD configures IO_MUX for U0TXD 0x88 32 read-write n 0x0 0x0 FUN_DRV configures drive strength 10 2 FUN_IE configures input enable 9 1 FUN_WPD configures pull down 7 1 FUN_WPU configures pull up 8 1 MCU_DRV configures drive strength during sleep mode 5 2 MCU_IE configures input enable during sleep mode 4 1 MCU_OE configures output enable during sleep mode 0 1 MCU_SEL configures IO_MUX function 12 2 MCU_WPD configures pull down during sleep mode 2 1 MCU_WPU configures pull up during sleep mode 3 1 SLP_SEL configures sleep mode selection 1 1 LEDC LEDC 0x0 0x0 0xCC0 registers n LEDC_INTR interrupt of LED PWM, level 43 CONF LEDC_CONF 0x190 32 read-write n 0x0 0x0 APB_CLK_SEL 0 1 DATE LEDC_DATE 0x1FC 32 read-write n 0x0 0x0 DATE 0 32 HSCH0_CONF0 LEDC_HSCH0_CONF0 0x0 32 read-write n 0x0 0x0 CLK_EN 31 1 IDLE_LV_HSCH0 3 1 SIG_OUT_EN_HSCH0 2 1 TIMER_SEL_HSCH0 0 2 HSCH0_CONF1 LEDC_HSCH0_CONF1 0xC 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH0 10 10 DUTY_INC_HSCH0 30 1 DUTY_NUM_HSCH0 20 10 DUTY_SCALE_HSCH0 0 10 DUTY_START_HSCH0 31 1 HSCH0_DUTY LEDC_HSCH0_DUTY 0x8 32 read-write n 0x0 0x0 DUTY_HSCH0 0 25 HSCH0_DUTY_R LEDC_HSCH0_DUTY_R 0x10 32 read-write n 0x0 0x0 DUTY_HSCH0 0 25 HSCH0_HPOINT LEDC_HSCH0_HPOINT 0x4 32 read-write n 0x0 0x0 HPOINT_HSCH0 0 20 HSCH1_CONF0 LEDC_HSCH1_CONF0 0x14 32 read-write n 0x0 0x0 IDLE_LV_HSCH1 3 1 SIG_OUT_EN_HSCH1 2 1 TIMER_SEL_HSCH1 0 2 HSCH1_CONF1 LEDC_HSCH1_CONF1 0x20 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH1 10 10 DUTY_INC_HSCH1 30 1 DUTY_NUM_HSCH1 20 10 DUTY_SCALE_HSCH1 0 10 DUTY_START_HSCH1 31 1 HSCH1_DUTY LEDC_HSCH1_DUTY 0x1C 32 read-write n 0x0 0x0 DUTY_HSCH1 0 25 HSCH1_DUTY_R LEDC_HSCH1_DUTY_R 0x24 32 read-write n 0x0 0x0 DUTY_HSCH1 0 25 HSCH1_HPOINT LEDC_HSCH1_HPOINT 0x18 32 read-write n 0x0 0x0 HPOINT_HSCH1 0 20 HSCH2_CONF0 LEDC_HSCH2_CONF0 0x28 32 read-write n 0x0 0x0 IDLE_LV_HSCH2 3 1 SIG_OUT_EN_HSCH2 2 1 TIMER_SEL_HSCH2 0 2 HSCH2_CONF1 LEDC_HSCH2_CONF1 0x34 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH2 10 10 DUTY_INC_HSCH2 30 1 DUTY_NUM_HSCH2 20 10 DUTY_SCALE_HSCH2 0 10 DUTY_START_HSCH2 31 1 HSCH2_DUTY LEDC_HSCH2_DUTY 0x30 32 read-write n 0x0 0x0 DUTY_HSCH2 0 25 HSCH2_DUTY_R LEDC_HSCH2_DUTY_R 0x38 32 read-write n 0x0 0x0 DUTY_HSCH2 0 25 HSCH2_HPOINT LEDC_HSCH2_HPOINT 0x2C 32 read-write n 0x0 0x0 HPOINT_HSCH2 0 20 HSCH3_CONF0 LEDC_HSCH3_CONF0 0x3C 32 read-write n 0x0 0x0 IDLE_LV_HSCH3 3 1 SIG_OUT_EN_HSCH3 2 1 TIMER_SEL_HSCH3 0 2 HSCH3_CONF1 LEDC_HSCH3_CONF1 0x48 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH3 10 10 DUTY_INC_HSCH3 30 1 DUTY_NUM_HSCH3 20 10 DUTY_SCALE_HSCH3 0 10 DUTY_START_HSCH3 31 1 HSCH3_DUTY LEDC_HSCH3_DUTY 0x44 32 read-write n 0x0 0x0 DUTY_HSCH3 0 25 HSCH3_DUTY_R LEDC_HSCH3_DUTY_R 0x4C 32 read-write n 0x0 0x0 DUTY_HSCH3 0 25 HSCH3_HPOINT LEDC_HSCH3_HPOINT 0x40 32 read-write n 0x0 0x0 HPOINT_HSCH3 0 20 HSCH4_CONF0 LEDC_HSCH4_CONF0 0x50 32 read-write n 0x0 0x0 IDLE_LV_HSCH4 3 1 SIG_OUT_EN_HSCH4 2 1 TIMER_SEL_HSCH4 0 2 HSCH4_CONF1 LEDC_HSCH4_CONF1 0x5C 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH4 10 10 DUTY_INC_HSCH4 30 1 DUTY_NUM_HSCH4 20 10 DUTY_SCALE_HSCH4 0 10 DUTY_START_HSCH4 31 1 HSCH4_DUTY LEDC_HSCH4_DUTY 0x58 32 read-write n 0x0 0x0 DUTY_HSCH4 0 25 HSCH4_DUTY_R LEDC_HSCH4_DUTY_R 0x60 32 read-write n 0x0 0x0 DUTY_HSCH4 0 25 HSCH4_HPOINT LEDC_HSCH4_HPOINT 0x54 32 read-write n 0x0 0x0 HPOINT_HSCH4 0 20 HSCH5_CONF0 LEDC_HSCH5_CONF0 0x64 32 read-write n 0x0 0x0 IDLE_LV_HSCH5 3 1 SIG_OUT_EN_HSCH5 2 1 TIMER_SEL_HSCH5 0 2 HSCH5_CONF1 LEDC_HSCH5_CONF1 0x70 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH5 10 10 DUTY_INC_HSCH5 30 1 DUTY_NUM_HSCH5 20 10 DUTY_SCALE_HSCH5 0 10 DUTY_START_HSCH5 31 1 HSCH5_DUTY LEDC_HSCH5_DUTY 0x6C 32 read-write n 0x0 0x0 DUTY_HSCH5 0 25 HSCH5_DUTY_R LEDC_HSCH5_DUTY_R 0x74 32 read-write n 0x0 0x0 DUTY_HSCH5 0 25 HSCH5_HPOINT LEDC_HSCH5_HPOINT 0x68 32 read-write n 0x0 0x0 HPOINT_HSCH5 0 20 HSCH6_CONF0 LEDC_HSCH6_CONF0 0x78 32 read-write n 0x0 0x0 IDLE_LV_HSCH6 3 1 SIG_OUT_EN_HSCH6 2 1 TIMER_SEL_HSCH6 0 2 HSCH6_CONF1 LEDC_HSCH6_CONF1 0x84 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH6 10 10 DUTY_INC_HSCH6 30 1 DUTY_NUM_HSCH6 20 10 DUTY_SCALE_HSCH6 0 10 DUTY_START_HSCH6 31 1 HSCH6_DUTY LEDC_HSCH6_DUTY 0x80 32 read-write n 0x0 0x0 DUTY_HSCH6 0 25 HSCH6_DUTY_R LEDC_HSCH6_DUTY_R 0x88 32 read-write n 0x0 0x0 DUTY_HSCH6 0 25 HSCH6_HPOINT LEDC_HSCH6_HPOINT 0x7C 32 read-write n 0x0 0x0 HPOINT_HSCH6 0 20 HSCH7_CONF0 LEDC_HSCH7_CONF0 0x8C 32 read-write n 0x0 0x0 IDLE_LV_HSCH7 3 1 SIG_OUT_EN_HSCH7 2 1 TIMER_SEL_HSCH7 0 2 HSCH7_CONF1 LEDC_HSCH7_CONF1 0x98 32 read-write n 0x0 0x0 DUTY_CYCLE_HSCH7 10 10 DUTY_INC_HSCH7 30 1 DUTY_NUM_HSCH7 20 10 DUTY_SCALE_HSCH7 0 10 DUTY_START_HSCH7 31 1 HSCH7_DUTY LEDC_HSCH7_DUTY 0x94 32 read-write n 0x0 0x0 DUTY_HSCH7 0 25 HSCH7_DUTY_R LEDC_HSCH7_DUTY_R 0x9C 32 read-write n 0x0 0x0 DUTY_HSCH7 0 25 HSCH7_HPOINT LEDC_HSCH7_HPOINT 0x90 32 read-write n 0x0 0x0 HPOINT_HSCH7 0 20 HSTIMER0_CONF LEDC_HSTIMER0_CONF 0x140 32 read-write n 0x0 0x0 DIV_NUM_HSTIMER0 5 18 HSTIMER0_LIM 0 5 HSTIMER0_PAUSE 23 1 HSTIMER0_RST 24 1 TICK_SEL_HSTIMER0 25 1 HSTIMER0_VALUE LEDC_HSTIMER0_VALUE 0x144 32 read-write n 0x0 0x0 HSTIMER0_CNT 0 20 HSTIMER1_CONF LEDC_HSTIMER1_CONF 0x148 32 read-write n 0x0 0x0 DIV_NUM_HSTIMER1 5 18 HSTIMER1_LIM 0 5 HSTIMER1_PAUSE 23 1 HSTIMER1_RST 24 1 TICK_SEL_HSTIMER1 25 1 HSTIMER1_VALUE LEDC_HSTIMER1_VALUE 0x14C 32 read-write n 0x0 0x0 HSTIMER1_CNT 0 20 HSTIMER2_CONF LEDC_HSTIMER2_CONF 0x150 32 read-write n 0x0 0x0 DIV_NUM_HSTIMER2 5 18 HSTIMER2_LIM 0 5 HSTIMER2_PAUSE 23 1 HSTIMER2_RST 24 1 TICK_SEL_HSTIMER2 25 1 HSTIMER2_VALUE LEDC_HSTIMER2_VALUE 0x154 32 read-write n 0x0 0x0 HSTIMER2_CNT 0 20 HSTIMER3_CONF LEDC_HSTIMER3_CONF 0x158 32 read-write n 0x0 0x0 DIV_NUM_HSTIMER3 5 18 HSTIMER3_LIM 0 5 HSTIMER3_PAUSE 23 1 HSTIMER3_RST 24 1 TICK_SEL_HSTIMER3 25 1 HSTIMER3_VALUE LEDC_HSTIMER3_VALUE 0x15C 32 read-write n 0x0 0x0 HSTIMER3_CNT 0 20 INT_CLR LEDC_INT_CLR 0x18C 32 read-write n 0x0 0x0 DUTY_CHNG_END_HSCH0_INT_CLR 8 1 DUTY_CHNG_END_HSCH1_INT_CLR 9 1 DUTY_CHNG_END_HSCH2_INT_CLR 10 1 DUTY_CHNG_END_HSCH3_INT_CLR 11 1 DUTY_CHNG_END_HSCH4_INT_CLR 12 1 DUTY_CHNG_END_HSCH5_INT_CLR 13 1 DUTY_CHNG_END_HSCH6_INT_CLR 14 1 DUTY_CHNG_END_HSCH7_INT_CLR 15 1 DUTY_CHNG_END_LSCH0_INT_CLR 16 1 DUTY_CHNG_END_LSCH1_INT_CLR 17 1 DUTY_CHNG_END_LSCH2_INT_CLR 18 1 DUTY_CHNG_END_LSCH3_INT_CLR 19 1 DUTY_CHNG_END_LSCH4_INT_CLR 20 1 DUTY_CHNG_END_LSCH5_INT_CLR 21 1 DUTY_CHNG_END_LSCH6_INT_CLR 22 1 DUTY_CHNG_END_LSCH7_INT_CLR 23 1 HSTIMER0_OVF_INT_CLR 0 1 HSTIMER1_OVF_INT_CLR 1 1 HSTIMER2_OVF_INT_CLR 2 1 HSTIMER3_OVF_INT_CLR 3 1 LSTIMER0_OVF_INT_CLR 4 1 LSTIMER1_OVF_INT_CLR 5 1 LSTIMER2_OVF_INT_CLR 6 1 LSTIMER3_OVF_INT_CLR 7 1 INT_ENA LEDC_INT_ENA 0x188 32 read-write n 0x0 0x0 DUTY_CHNG_END_HSCH0_INT_ENA 8 1 DUTY_CHNG_END_HSCH1_INT_ENA 9 1 DUTY_CHNG_END_HSCH2_INT_ENA 10 1 DUTY_CHNG_END_HSCH3_INT_ENA 11 1 DUTY_CHNG_END_HSCH4_INT_ENA 12 1 DUTY_CHNG_END_HSCH5_INT_ENA 13 1 DUTY_CHNG_END_HSCH6_INT_ENA 14 1 DUTY_CHNG_END_HSCH7_INT_ENA 15 1 DUTY_CHNG_END_LSCH0_INT_ENA 16 1 DUTY_CHNG_END_LSCH1_INT_ENA 17 1 DUTY_CHNG_END_LSCH2_INT_ENA 18 1 DUTY_CHNG_END_LSCH3_INT_ENA 19 1 DUTY_CHNG_END_LSCH4_INT_ENA 20 1 DUTY_CHNG_END_LSCH5_INT_ENA 21 1 DUTY_CHNG_END_LSCH6_INT_ENA 22 1 DUTY_CHNG_END_LSCH7_INT_ENA 23 1 HSTIMER0_OVF_INT_ENA 0 1 HSTIMER1_OVF_INT_ENA 1 1 HSTIMER2_OVF_INT_ENA 2 1 HSTIMER3_OVF_INT_ENA 3 1 LSTIMER0_OVF_INT_ENA 4 1 LSTIMER1_OVF_INT_ENA 5 1 LSTIMER2_OVF_INT_ENA 6 1 LSTIMER3_OVF_INT_ENA 7 1 INT_RAW LEDC_INT_RAW 0x180 32 read-write n 0x0 0x0 DUTY_CHNG_END_HSCH0_INT_RAW 8 1 DUTY_CHNG_END_HSCH1_INT_RAW 9 1 DUTY_CHNG_END_HSCH2_INT_RAW 10 1 DUTY_CHNG_END_HSCH3_INT_RAW 11 1 DUTY_CHNG_END_HSCH4_INT_RAW 12 1 DUTY_CHNG_END_HSCH5_INT_RAW 13 1 DUTY_CHNG_END_HSCH6_INT_RAW 14 1 DUTY_CHNG_END_HSCH7_INT_RAW 15 1 DUTY_CHNG_END_LSCH0_INT_RAW 16 1 DUTY_CHNG_END_LSCH1_INT_RAW 17 1 DUTY_CHNG_END_LSCH2_INT_RAW 18 1 DUTY_CHNG_END_LSCH3_INT_RAW 19 1 DUTY_CHNG_END_LSCH4_INT_RAW 20 1 DUTY_CHNG_END_LSCH5_INT_RAW 21 1 DUTY_CHNG_END_LSCH6_INT_RAW 22 1 DUTY_CHNG_END_LSCH7_INT_RAW 23 1 HSTIMER0_OVF_INT_RAW 0 1 HSTIMER1_OVF_INT_RAW 1 1 HSTIMER2_OVF_INT_RAW 2 1 HSTIMER3_OVF_INT_RAW 3 1 LSTIMER0_OVF_INT_RAW 4 1 LSTIMER1_OVF_INT_RAW 5 1 LSTIMER2_OVF_INT_RAW 6 1 LSTIMER3_OVF_INT_RAW 7 1 INT_ST LEDC_INT_ST 0x184 32 read-write n 0x0 0x0 DUTY_CHNG_END_HSCH0_INT_ST 8 1 DUTY_CHNG_END_HSCH1_INT_ST 9 1 DUTY_CHNG_END_HSCH2_INT_ST 10 1 DUTY_CHNG_END_HSCH3_INT_ST 11 1 DUTY_CHNG_END_HSCH4_INT_ST 12 1 DUTY_CHNG_END_HSCH5_INT_ST 13 1 DUTY_CHNG_END_HSCH6_INT_ST 14 1 DUTY_CHNG_END_HSCH7_INT_ST 15 1 DUTY_CHNG_END_LSCH0_INT_ST 16 1 DUTY_CHNG_END_LSCH1_INT_ST 17 1 DUTY_CHNG_END_LSCH2_INT_ST 18 1 DUTY_CHNG_END_LSCH3_INT_ST 19 1 DUTY_CHNG_END_LSCH4_INT_ST 20 1 DUTY_CHNG_END_LSCH5_INT_ST 21 1 DUTY_CHNG_END_LSCH6_INT_ST 22 1 DUTY_CHNG_END_LSCH7_INT_ST 23 1 HSTIMER0_OVF_INT_ST 0 1 HSTIMER1_OVF_INT_ST 1 1 HSTIMER2_OVF_INT_ST 2 1 HSTIMER3_OVF_INT_ST 3 1 LSTIMER0_OVF_INT_ST 4 1 LSTIMER1_OVF_INT_ST 5 1 LSTIMER2_OVF_INT_ST 6 1 LSTIMER3_OVF_INT_ST 7 1 LSCH0_CONF0 LEDC_LSCH0_CONF0 0xA0 32 read-write n 0x0 0x0 IDLE_LV_LSCH0 3 1 PARA_UP_LSCH0 4 1 SIG_OUT_EN_LSCH0 2 1 TIMER_SEL_LSCH0 0 2 LSCH0_CONF1 LEDC_LSCH0_CONF1 0xAC 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH0 10 10 DUTY_INC_LSCH0 30 1 DUTY_NUM_LSCH0 20 10 DUTY_SCALE_LSCH0 0 10 DUTY_START_LSCH0 31 1 LSCH0_DUTY LEDC_LSCH0_DUTY 0xA8 32 read-write n 0x0 0x0 DUTY_LSCH0 0 25 LSCH0_DUTY_R LEDC_LSCH0_DUTY_R 0xB0 32 read-write n 0x0 0x0 DUTY_LSCH0 0 25 LSCH0_HPOINT LEDC_LSCH0_HPOINT 0xA4 32 read-write n 0x0 0x0 HPOINT_LSCH0 0 20 LSCH1_CONF0 LEDC_LSCH1_CONF0 0xB4 32 read-write n 0x0 0x0 IDLE_LV_LSCH1 3 1 PARA_UP_LSCH1 4 1 SIG_OUT_EN_LSCH1 2 1 TIMER_SEL_LSCH1 0 2 LSCH1_CONF1 LEDC_LSCH1_CONF1 0xC0 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH1 10 10 DUTY_INC_LSCH1 30 1 DUTY_NUM_LSCH1 20 10 DUTY_SCALE_LSCH1 0 10 DUTY_START_LSCH1 31 1 LSCH1_DUTY LEDC_LSCH1_DUTY 0xBC 32 read-write n 0x0 0x0 DUTY_LSCH1 0 25 LSCH1_DUTY_R LEDC_LSCH1_DUTY_R 0xC4 32 read-write n 0x0 0x0 DUTY_LSCH1 0 25 LSCH1_HPOINT LEDC_LSCH1_HPOINT 0xB8 32 read-write n 0x0 0x0 HPOINT_LSCH1 0 20 LSCH2_CONF0 LEDC_LSCH2_CONF0 0xC8 32 read-write n 0x0 0x0 IDLE_LV_LSCH2 3 1 PARA_UP_LSCH2 4 1 SIG_OUT_EN_LSCH2 2 1 TIMER_SEL_LSCH2 0 2 LSCH2_CONF1 LEDC_LSCH2_CONF1 0xD4 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH2 10 10 DUTY_INC_LSCH2 30 1 DUTY_NUM_LSCH2 20 10 DUTY_SCALE_LSCH2 0 10 DUTY_START_LSCH2 31 1 LSCH2_DUTY LEDC_LSCH2_DUTY 0xD0 32 read-write n 0x0 0x0 DUTY_LSCH2 0 25 LSCH2_DUTY_R LEDC_LSCH2_DUTY_R 0xD8 32 read-write n 0x0 0x0 DUTY_LSCH2 0 25 LSCH2_HPOINT LEDC_LSCH2_HPOINT 0xCC 32 read-write n 0x0 0x0 HPOINT_LSCH2 0 20 LSCH3_CONF0 LEDC_LSCH3_CONF0 0xDC 32 read-write n 0x0 0x0 IDLE_LV_LSCH3 3 1 PARA_UP_LSCH3 4 1 SIG_OUT_EN_LSCH3 2 1 TIMER_SEL_LSCH3 0 2 LSCH3_CONF1 LEDC_LSCH3_CONF1 0xE8 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH3 10 10 DUTY_INC_LSCH3 30 1 DUTY_NUM_LSCH3 20 10 DUTY_SCALE_LSCH3 0 10 DUTY_START_LSCH3 31 1 LSCH3_DUTY LEDC_LSCH3_DUTY 0xE4 32 read-write n 0x0 0x0 DUTY_LSCH3 0 25 LSCH3_DUTY_R LEDC_LSCH3_DUTY_R 0xEC 32 read-write n 0x0 0x0 DUTY_LSCH3 0 25 LSCH3_HPOINT LEDC_LSCH3_HPOINT 0xE0 32 read-write n 0x0 0x0 HPOINT_LSCH3 0 20 LSCH4_CONF0 LEDC_LSCH4_CONF0 0xF0 32 read-write n 0x0 0x0 IDLE_LV_LSCH4 3 1 PARA_UP_LSCH4 4 1 SIG_OUT_EN_LSCH4 2 1 TIMER_SEL_LSCH4 0 2 LSCH4_CONF1 LEDC_LSCH4_CONF1 0xFC 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH4 10 10 DUTY_INC_LSCH4 30 1 DUTY_NUM_LSCH4 20 10 DUTY_SCALE_LSCH4 0 10 DUTY_START_LSCH4 31 1 LSCH4_DUTY LEDC_LSCH4_DUTY 0xF8 32 read-write n 0x0 0x0 DUTY_LSCH4 0 25 LSCH4_DUTY_R LEDC_LSCH4_DUTY_R 0x100 32 read-write n 0x0 0x0 DUTY_LSCH4 0 25 LSCH4_HPOINT LEDC_LSCH4_HPOINT 0xF4 32 read-write n 0x0 0x0 HPOINT_LSCH4 0 20 LSCH5_CONF0 LEDC_LSCH5_CONF0 0x104 32 read-write n 0x0 0x0 IDLE_LV_LSCH5 3 1 PARA_UP_LSCH5 4 1 SIG_OUT_EN_LSCH5 2 1 TIMER_SEL_LSCH5 0 2 LSCH5_CONF1 LEDC_LSCH5_CONF1 0x110 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH5 10 10 DUTY_INC_LSCH5 30 1 DUTY_NUM_LSCH5 20 10 DUTY_SCALE_LSCH5 0 10 DUTY_START_LSCH5 31 1 LSCH5_DUTY LEDC_LSCH5_DUTY 0x10C 32 read-write n 0x0 0x0 DUTY_LSCH5 0 25 LSCH5_DUTY_R LEDC_LSCH5_DUTY_R 0x114 32 read-write n 0x0 0x0 DUTY_LSCH5 0 25 LSCH5_HPOINT LEDC_LSCH5_HPOINT 0x108 32 read-write n 0x0 0x0 HPOINT_LSCH5 0 20 LSCH6_CONF0 LEDC_LSCH6_CONF0 0x118 32 read-write n 0x0 0x0 IDLE_LV_LSCH6 3 1 PARA_UP_LSCH6 4 1 SIG_OUT_EN_LSCH6 2 1 TIMER_SEL_LSCH6 0 2 LSCH6_CONF1 LEDC_LSCH6_CONF1 0x124 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH6 10 10 DUTY_INC_LSCH6 30 1 DUTY_NUM_LSCH6 20 10 DUTY_SCALE_LSCH6 0 10 DUTY_START_LSCH6 31 1 LSCH6_DUTY LEDC_LSCH6_DUTY 0x120 32 read-write n 0x0 0x0 DUTY_LSCH6 0 25 LSCH6_DUTY_R LEDC_LSCH6_DUTY_R 0x128 32 read-write n 0x0 0x0 DUTY_LSCH6 0 25 LSCH6_HPOINT LEDC_LSCH6_HPOINT 0x11C 32 read-write n 0x0 0x0 HPOINT_LSCH6 0 20 LSCH7_CONF0 LEDC_LSCH7_CONF0 0x12C 32 read-write n 0x0 0x0 IDLE_LV_LSCH7 3 1 PARA_UP_LSCH7 4 1 SIG_OUT_EN_LSCH7 2 1 TIMER_SEL_LSCH7 0 2 LSCH7_CONF1 LEDC_LSCH7_CONF1 0x138 32 read-write n 0x0 0x0 DUTY_CYCLE_LSCH7 10 10 DUTY_INC_LSCH7 30 1 DUTY_NUM_LSCH7 20 10 DUTY_SCALE_LSCH7 0 10 DUTY_START_LSCH7 31 1 LSCH7_DUTY LEDC_LSCH7_DUTY 0x134 32 read-write n 0x0 0x0 DUTY_LSCH7 0 25 LSCH7_DUTY_R LEDC_LSCH7_DUTY_R 0x13C 32 read-write n 0x0 0x0 DUTY_LSCH7 0 25 LSCH7_HPOINT LEDC_LSCH7_HPOINT 0x130 32 read-write n 0x0 0x0 HPOINT_LSCH7 0 20 LSTIMER0_CONF LEDC_LSTIMER0_CONF 0x160 32 read-write n 0x0 0x0 DIV_NUM_LSTIMER0 5 18 LSTIMER0_LIM 0 5 LSTIMER0_PARA_UP 26 1 LSTIMER0_PAUSE 23 1 LSTIMER0_RST 24 1 TICK_SEL_LSTIMER0 25 1 LSTIMER0_VALUE LEDC_LSTIMER0_VALUE 0x164 32 read-write n 0x0 0x0 LSTIMER0_CNT 0 20 LSTIMER1_CONF LEDC_LSTIMER1_CONF 0x168 32 read-write n 0x0 0x0 DIV_NUM_LSTIMER1 5 18 LSTIMER1_LIM 0 5 LSTIMER1_PARA_UP 26 1 LSTIMER1_PAUSE 23 1 LSTIMER1_RST 24 1 TICK_SEL_LSTIMER1 25 1 LSTIMER1_VALUE LEDC_LSTIMER1_VALUE 0x16C 32 read-write n 0x0 0x0 LSTIMER1_CNT 0 20 LSTIMER2_CONF LEDC_LSTIMER2_CONF 0x170 32 read-write n 0x0 0x0 DIV_NUM_LSTIMER2 5 18 LSTIMER2_LIM 0 5 LSTIMER2_PARA_UP 26 1 LSTIMER2_PAUSE 23 1 LSTIMER2_RST 24 1 TICK_SEL_LSTIMER2 25 1 LSTIMER2_VALUE LEDC_LSTIMER2_VALUE 0x174 32 read-write n 0x0 0x0 LSTIMER2_CNT 0 20 LSTIMER3_CONF LEDC_LSTIMER3_CONF 0x178 32 read-write n 0x0 0x0 DIV_NUM_LSTIMER3 5 18 LSTIMER3_LIM 0 5 LSTIMER3_PARA_UP 26 1 LSTIMER3_PAUSE 23 1 LSTIMER3_RST 24 1 TICK_SEL_LSTIMER3 25 1 LSTIMER3_VALUE LEDC_LSTIMER3_VALUE 0x17C 32 read-write n 0x0 0x0 LSTIMER3_CNT 0 20 MCPWM MCPWM 0x0 0x0 0x940 registers n CAP_CH0 MCPWM_CAP_CH0 0xFC 32 read-write n 0x0 0x0 CAP0_VALUE 0 32 CAP_CH0_CFG MCPWM_CAP_CH0_CFG 0xF0 32 read-write n 0x0 0x0 CAP0_EN 0 1 CAP0_IN_INVERT 11 1 CAP0_MODE 1 2 CAP0_PRESCALE 3 8 CAP0_SW 12 1 CAP_CH1 MCPWM_CAP_CH1 0x100 32 read-write n 0x0 0x0 CAP1_VALUE 0 32 CAP_CH1_CFG MCPWM_CAP_CH1_CFG 0xF4 32 read-write n 0x0 0x0 CAP1_EN 0 1 CAP1_IN_INVERT 11 1 CAP1_MODE 1 2 CAP1_PRESCALE 3 8 CAP1_SW 12 1 CAP_CH2 MCPWM_CAP_CH2 0x104 32 read-write n 0x0 0x0 CAP2_VALUE 0 32 CAP_CH2_CFG MCPWM_CAP_CH2_CFG 0xF8 32 read-write n 0x0 0x0 CAP2_EN 0 1 CAP2_IN_INVERT 11 1 CAP2_MODE 1 2 CAP2_PRESCALE 3 8 CAP2_SW 12 1 CAP_STATUS MCPWM_CAP_STATUS 0x108 32 read-write n 0x0 0x0 CAP0_EDGE 0 1 CAP1_EDGE 1 1 CAP2_EDGE 2 1 CAP_TIMER_CFG MCPWM_CAP_TIMER_CFG 0xE8 32 read-write n 0x0 0x0 CAP_SYNCI_EN 1 1 CAP_SYNCI_SEL 2 3 CAP_SYNC_SW 5 1 CAP_TIMER_EN 0 1 CAP_TIMER_PHASE MCPWM_CAP_TIMER_PHASE 0xEC 32 read-write n 0x0 0x0 CAP_PHASE 0 32 CARRIER0_CFG MCPWM_CARRIER0_CFG 0x64 32 read-write n 0x0 0x0 CARRIER0_DUTY 5 3 CARRIER0_EN 0 1 CARRIER0_IN_INVERT 13 1 CARRIER0_OSHWTH 8 4 CARRIER0_OUT_INVERT 12 1 CARRIER0_PRESCALE 1 4 CARRIER1_CFG MCPWM_CARRIER1_CFG 0x9C 32 read-write n 0x0 0x0 CARRIER1_DUTY 5 3 CARRIER1_EN 0 1 CARRIER1_IN_INVERT 13 1 CARRIER1_OSHWTH 8 4 CARRIER1_OUT_INVERT 12 1 CARRIER1_PRESCALE 1 4 CARRIER2_CFG MCPWM_CARRIER2_CFG 0xD4 32 read-write n 0x0 0x0 CARRIER2_DUTY 5 3 CARRIER2_EN 0 1 CARRIER2_IN_INVERT 13 1 CARRIER2_OSHWTH 8 4 CARRIER2_OUT_INVERT 12 1 CARRIER2_PRESCALE 1 4 CLK MCPWM_CLK 0x120 32 read-write n 0x0 0x0 CLK_EN 0 1 CLK_CFG MCPWM_CLK_CFG 0x0 32 read-write n 0x0 0x0 CLK_PRESCALE 0 8 DT0_CFG MCPWM_DT0_CFG 0x58 32 read-write n 0x0 0x0 DT0_A_OUTBYPASS 15 1 DT0_A_OUTSWAP 9 1 DT0_B_OUTBYPASS 16 1 DT0_B_OUTSWAP 10 1 DT0_CLK_SEL 17 1 DT0_DEB_MODE 8 1 DT0_FED_INSEL 12 1 DT0_FED_OUTINVERT 14 1 DT0_FED_UPMETHOD 0 4 DT0_RED_INSEL 11 1 DT0_RED_OUTINVERT 13 1 DT0_RED_UPMETHOD 4 4 DT0_FED_CFG MCPWM_DT0_FED_CFG 0x5C 32 read-write n 0x0 0x0 DT0_FED 0 16 DT0_RED_CFG MCPWM_DT0_RED_CFG 0x60 32 read-write n 0x0 0x0 DT0_RED 0 16 DT1_CFG MCPWM_DT1_CFG 0x90 32 read-write n 0x0 0x0 DT1_A_OUTBYPASS 15 1 DT1_A_OUTSWAP 9 1 DT1_B_OUTBYPASS 16 1 DT1_B_OUTSWAP 10 1 DT1_CLK_SEL 17 1 DT1_DEB_MODE 8 1 DT1_FED_INSEL 12 1 DT1_FED_OUTINVERT 14 1 DT1_FED_UPMETHOD 0 4 DT1_RED_INSEL 11 1 DT1_RED_OUTINVERT 13 1 DT1_RED_UPMETHOD 4 4 DT1_FED_CFG MCPWM_DT1_FED_CFG 0x94 32 read-write n 0x0 0x0 DT1_FED 0 16 DT1_RED_CFG MCPWM_DT1_RED_CFG 0x98 32 read-write n 0x0 0x0 DT1_RED 0 16 DT2_CFG MCPWM_DT2_CFG 0xC8 32 read-write n 0x0 0x0 DT2_A_OUTBYPASS 15 1 DT2_A_OUTSWAP 9 1 DT2_B_OUTBYPASS 16 1 DT2_B_OUTSWAP 10 1 DT2_CLK_SEL 17 1 DT2_DEB_MODE 8 1 DT2_FED_INSEL 12 1 DT2_FED_OUTINVERT 14 1 DT2_FED_UPMETHOD 0 4 DT2_RED_INSEL 11 1 DT2_RED_OUTINVERT 13 1 DT2_RED_UPMETHOD 4 4 DT2_FED_CFG MCPWM_DT2_FED_CFG 0xCC 32 read-write n 0x0 0x0 DT2_FED 0 16 DT2_RED_CFG MCPWM_DT2_RED_CFG 0xD0 32 read-write n 0x0 0x0 DT2_RED 0 16 FAULT_DETECT MCPWM_FAULT_DETECT 0xE4 32 read-write n 0x0 0x0 EVENT_F0 6 1 EVENT_F1 7 1 EVENT_F2 8 1 F0_EN 0 1 F0_POLE 3 1 F1_EN 1 1 F1_POLE 4 1 F2_EN 2 1 F2_POLE 5 1 FH0_CFG0 MCPWM_FH0_CFG0 0x68 32 read-write n 0x0 0x0 FH0_A_CBC_D 8 2 FH0_A_CBC_U 10 2 FH0_A_OST_D 12 2 FH0_A_OST_U 14 2 FH0_B_CBC_D 16 2 FH0_B_CBC_U 18 2 FH0_B_OST_D 20 2 FH0_B_OST_U 22 2 FH0_F0_CBC 3 1 FH0_F0_OST 7 1 FH0_F1_CBC 2 1 FH0_F1_OST 6 1 FH0_F2_CBC 1 1 FH0_F2_OST 5 1 FH0_SW_CBC 0 1 FH0_SW_OST 4 1 FH0_CFG1 MCPWM_FH0_CFG1 0x6C 32 read-write n 0x0 0x0 FH0_CBCPULSE 1 2 FH0_CLR_OST 0 1 FH0_FORCE_CBC 3 1 FH0_FORCE_OST 4 1 FH0_STATUS MCPWM_FH0_STATUS 0x70 32 read-write n 0x0 0x0 FH0_CBC_ON 0 1 FH0_OST_ON 1 1 FH1_CFG0 MCPWM_FH1_CFG0 0xA0 32 read-write n 0x0 0x0 FH1_A_CBC_D 8 2 FH1_A_CBC_U 10 2 FH1_A_OST_D 12 2 FH1_A_OST_U 14 2 FH1_B_CBC_D 16 2 FH1_B_CBC_U 18 2 FH1_B_OST_D 20 2 FH1_B_OST_U 22 2 FH1_F0_CBC 3 1 FH1_F0_OST 7 1 FH1_F1_CBC 2 1 FH1_F1_OST 6 1 FH1_F2_CBC 1 1 FH1_F2_OST 5 1 FH1_SW_CBC 0 1 FH1_SW_OST 4 1 FH1_CFG1 MCPWM_FH1_CFG1 0xA4 32 read-write n 0x0 0x0 FH1_CBCPULSE 1 2 FH1_CLR_OST 0 1 FH1_FORCE_CBC 3 1 FH1_FORCE_OST 4 1 FH1_STATUS MCPWM_FH1_STATUS 0xA8 32 read-write n 0x0 0x0 FH1_CBC_ON 0 1 FH1_OST_ON 1 1 FH2_CFG0 MCPWM_FH2_CFG0 0xD8 32 read-write n 0x0 0x0 FH2_A_CBC_D 8 2 FH2_A_CBC_U 10 2 FH2_A_OST_D 12 2 FH2_A_OST_U 14 2 FH2_B_CBC_D 16 2 FH2_B_CBC_U 18 2 FH2_B_OST_D 20 2 FH2_B_OST_U 22 2 FH2_F0_CBC 3 1 FH2_F0_OST 7 1 FH2_F1_CBC 2 1 FH2_F1_OST 6 1 FH2_F2_CBC 1 1 FH2_F2_OST 5 1 FH2_SW_CBC 0 1 FH2_SW_OST 4 1 FH2_CFG1 MCPWM_FH2_CFG1 0xDC 32 read-write n 0x0 0x0 FH2_CBCPULSE 1 2 FH2_CLR_OST 0 1 FH2_FORCE_CBC 3 1 FH2_FORCE_OST 4 1 FH2_STATUS MCPWM_FH2_STATUS 0xE0 32 read-write n 0x0 0x0 FH2_CBC_ON 0 1 FH2_OST_ON 1 1 GEN0_A MCPWM_GEN0_A 0x50 32 read-write n 0x0 0x0 GEN0_A_DT0 20 2 GEN0_A_DT1 22 2 GEN0_A_DTEA 16 2 GEN0_A_DTEB 18 2 GEN0_A_DTEP 14 2 GEN0_A_DTEZ 12 2 GEN0_A_UT0 8 2 GEN0_A_UT1 10 2 GEN0_A_UTEA 4 2 GEN0_A_UTEB 6 2 GEN0_A_UTEP 2 2 GEN0_A_UTEZ 0 2 GEN0_B MCPWM_GEN0_B 0x54 32 read-write n 0x0 0x0 GEN0_B_DT0 20 2 GEN0_B_DT1 22 2 GEN0_B_DTEA 16 2 GEN0_B_DTEB 18 2 GEN0_B_DTEP 14 2 GEN0_B_DTEZ 12 2 GEN0_B_UT0 8 2 GEN0_B_UT1 10 2 GEN0_B_UTEA 4 2 GEN0_B_UTEB 6 2 GEN0_B_UTEP 2 2 GEN0_B_UTEZ 0 2 GEN0_CFG0 MCPWM_GEN0_CFG0 0x48 32 read-write n 0x0 0x0 GEN0_CFG_UPMETHOD 0 4 GEN0_T0_SEL 4 3 GEN0_T1_SEL 7 3 GEN0_FORCE MCPWM_GEN0_FORCE 0x4C 32 read-write n 0x0 0x0 GEN0_A_CNTUFORCE_MODE 6 2 GEN0_A_NCIFORCE 10 1 GEN0_A_NCIFORCE_MODE 11 2 GEN0_B_CNTUFORCE_MODE 8 2 GEN0_B_NCIFORCE 13 1 GEN0_B_NCIFORCE_MODE 14 2 GEN0_CNTUFORCE_UPMETHOD 0 6 GEN0_STMP_CFG MCPWM_GEN0_STMP_CFG 0x3C 32 read-write n 0x0 0x0 GEN0_A_SHDW_FULL 8 1 GEN0_A_UPMETHOD 0 4 GEN0_B_SHDW_FULL 9 1 GEN0_B_UPMETHOD 4 4 GEN0_TSTMP_A MCPWM_GEN0_TSTMP_A 0x40 32 read-write n 0x0 0x0 GEN0_A 0 16 GEN0_TSTMP_B MCPWM_GEN0_TSTMP_B 0x44 32 read-write n 0x0 0x0 GEN0_B 0 16 GEN1_A MCPWM_GEN1_A 0x88 32 read-write n 0x0 0x0 GEN1_A_DT0 20 2 GEN1_A_DT1 22 2 GEN1_A_DTEA 16 2 GEN1_A_DTEB 18 2 GEN1_A_DTEP 14 2 GEN1_A_DTEZ 12 2 GEN1_A_UT0 8 2 GEN1_A_UT1 10 2 GEN1_A_UTEA 4 2 GEN1_A_UTEB 6 2 GEN1_A_UTEP 2 2 GEN1_A_UTEZ 0 2 GEN1_B MCPWM_GEN1_B 0x8C 32 read-write n 0x0 0x0 GEN1_B_DT0 20 2 GEN1_B_DT1 22 2 GEN1_B_DTEA 16 2 GEN1_B_DTEB 18 2 GEN1_B_DTEP 14 2 GEN1_B_DTEZ 12 2 GEN1_B_UT0 8 2 GEN1_B_UT1 10 2 GEN1_B_UTEA 4 2 GEN1_B_UTEB 6 2 GEN1_B_UTEP 2 2 GEN1_B_UTEZ 0 2 GEN1_CFG0 MCPWM_GEN1_CFG0 0x80 32 read-write n 0x0 0x0 GEN1_CFG_UPMETHOD 0 4 GEN1_T0_SEL 4 3 GEN1_T1_SEL 7 3 GEN1_FORCE MCPWM_GEN1_FORCE 0x84 32 read-write n 0x0 0x0 GEN1_A_CNTUFORCE_MODE 6 2 GEN1_A_NCIFORCE 10 1 GEN1_A_NCIFORCE_MODE 11 2 GEN1_B_CNTUFORCE_MODE 8 2 GEN1_B_NCIFORCE 13 1 GEN1_B_NCIFORCE_MODE 14 2 GEN1_CNTUFORCE_UPMETHOD 0 6 GEN1_STMP_CFG MCPWM_GEN1_STMP_CFG 0x74 32 read-write n 0x0 0x0 GEN1_A_SHDW_FULL 8 1 GEN1_A_UPMETHOD 0 4 GEN1_B_SHDW_FULL 9 1 GEN1_B_UPMETHOD 4 4 GEN1_TSTMP_A MCPWM_GEN1_TSTMP_A 0x78 32 read-write n 0x0 0x0 GEN1_A 0 16 GEN1_TSTMP_B MCPWM_GEN1_TSTMP_B 0x7C 32 read-write n 0x0 0x0 GEN1_B 0 16 GEN2_A MCPWM_GEN2_A 0xC0 32 read-write n 0x0 0x0 GEN2_A_DT0 20 2 GEN2_A_DT1 22 2 GEN2_A_DTEA 16 2 GEN2_A_DTEB 18 2 GEN2_A_DTEP 14 2 GEN2_A_DTEZ 12 2 GEN2_A_UT0 8 2 GEN2_A_UT1 10 2 GEN2_A_UTEA 4 2 GEN2_A_UTEB 6 2 GEN2_A_UTEP 2 2 GEN2_A_UTEZ 0 2 GEN2_B MCPWM_GEN2_B 0xC4 32 read-write n 0x0 0x0 GEN2_B_DT0 20 2 GEN2_B_DT1 22 2 GEN2_B_DTEA 16 2 GEN2_B_DTEB 18 2 GEN2_B_DTEP 14 2 GEN2_B_DTEZ 12 2 GEN2_B_UT0 8 2 GEN2_B_UT1 10 2 GEN2_B_UTEA 4 2 GEN2_B_UTEB 6 2 GEN2_B_UTEP 2 2 GEN2_B_UTEZ 0 2 GEN2_CFG0 MCPWM_GEN2_CFG0 0xB8 32 read-write n 0x0 0x0 GEN2_CFG_UPMETHOD 0 4 GEN2_T0_SEL 4 3 GEN2_T1_SEL 7 3 GEN2_FORCE MCPWM_GEN2_FORCE 0xBC 32 read-write n 0x0 0x0 GEN2_A_CNTUFORCE_MODE 6 2 GEN2_A_NCIFORCE 10 1 GEN2_A_NCIFORCE_MODE 11 2 GEN2_B_CNTUFORCE_MODE 8 2 GEN2_B_NCIFORCE 13 1 GEN2_B_NCIFORCE_MODE 14 2 GEN2_CNTUFORCE_UPMETHOD 0 6 GEN2_STMP_CFG MCPWM_GEN2_STMP_CFG 0xAC 32 read-write n 0x0 0x0 GEN2_A_SHDW_FULL 8 1 GEN2_A_UPMETHOD 0 4 GEN2_B_SHDW_FULL 9 1 GEN2_B_UPMETHOD 4 4 GEN2_TSTMP_A MCPWM_GEN2_TSTMP_A 0xB0 32 read-write n 0x0 0x0 GEN2_A 0 16 GEN2_TSTMP_B MCPWM_GEN2_TSTMP_B 0xB4 32 read-write n 0x0 0x0 GEN2_B 0 16 MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM 0x11C 32 read-write n 0x0 0x0 CAP0_INT_CLR 27 1 CAP1_INT_CLR 28 1 CAP2_INT_CLR 29 1 FAULT0_CLR_INT_CLR 12 1 FAULT0_INT_CLR 9 1 FAULT1_CLR_INT_CLR 13 1 FAULT1_INT_CLR 10 1 FAULT2_CLR_INT_CLR 14 1 FAULT2_INT_CLR 11 1 FH0_CBC_INT_CLR 21 1 FH0_OST_INT_CLR 24 1 FH1_CBC_INT_CLR 22 1 FH1_OST_INT_CLR 25 1 FH2_CBC_INT_CLR 23 1 FH2_OST_INT_CLR 26 1 OP0_TEA_INT_CLR 15 1 OP0_TEB_INT_CLR 18 1 OP1_TEA_INT_CLR 16 1 OP1_TEB_INT_CLR 19 1 OP2_TEA_INT_CLR 17 1 OP2_TEB_INT_CLR 20 1 TIMER0_STOP_INT_CLR 0 1 TIMER0_TEP_INT_CLR 6 1 TIMER0_TEZ_INT_CLR 3 1 TIMER1_STOP_INT_CLR 1 1 TIMER1_TEP_INT_CLR 7 1 TIMER1_TEZ_INT_CLR 4 1 TIMER2_STOP_INT_CLR 2 1 TIMER2_TEP_INT_CLR 8 1 TIMER2_TEZ_INT_CLR 5 1 MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM 0x110 32 read-write n 0x0 0x0 CAP0_INT_ENA 27 1 CAP1_INT_ENA 28 1 CAP2_INT_ENA 29 1 FAULT0_CLR_INT_ENA 12 1 FAULT0_INT_ENA 9 1 FAULT1_CLR_INT_ENA 13 1 FAULT1_INT_ENA 10 1 FAULT2_CLR_INT_ENA 14 1 FAULT2_INT_ENA 11 1 FH0_CBC_INT_ENA 21 1 FH0_OST_INT_ENA 24 1 FH1_CBC_INT_ENA 22 1 FH1_OST_INT_ENA 25 1 FH2_CBC_INT_ENA 23 1 FH2_OST_INT_ENA 26 1 OP0_TEA_INT_ENA 15 1 OP0_TEB_INT_ENA 18 1 OP1_TEA_INT_ENA 16 1 OP1_TEB_INT_ENA 19 1 OP2_TEA_INT_ENA 17 1 OP2_TEB_INT_ENA 20 1 TIMER0_STOP_INT_ENA 0 1 TIMER0_TEP_INT_ENA 6 1 TIMER0_TEZ_INT_ENA 3 1 TIMER1_STOP_INT_ENA 1 1 TIMER1_TEP_INT_ENA 7 1 TIMER1_TEZ_INT_ENA 4 1 TIMER2_STOP_INT_ENA 2 1 TIMER2_TEP_INT_ENA 8 1 TIMER2_TEZ_INT_ENA 5 1 MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM 0x114 32 read-write n 0x0 0x0 CAP0_INT_RAW 27 1 CAP1_INT_RAW 28 1 CAP2_INT_RAW 29 1 FAULT0_CLR_INT_RAW 12 1 FAULT0_INT_RAW 9 1 FAULT1_CLR_INT_RAW 13 1 FAULT1_INT_RAW 10 1 FAULT2_CLR_INT_RAW 14 1 FAULT2_INT_RAW 11 1 FH0_CBC_INT_RAW 21 1 FH0_OST_INT_RAW 24 1 FH1_CBC_INT_RAW 22 1 FH1_OST_INT_RAW 25 1 FH2_CBC_INT_RAW 23 1 FH2_OST_INT_RAW 26 1 OP0_TEA_INT_RAW 15 1 OP0_TEB_INT_RAW 18 1 OP1_TEA_INT_RAW 16 1 OP1_TEB_INT_RAW 19 1 OP2_TEA_INT_RAW 17 1 OP2_TEB_INT_RAW 20 1 TIMER0_STOP_INT_RAW 0 1 TIMER0_TEP_INT_RAW 6 1 TIMER0_TEZ_INT_RAW 3 1 TIMER1_STOP_INT_RAW 1 1 TIMER1_TEP_INT_RAW 7 1 TIMER1_TEZ_INT_RAW 4 1 TIMER2_STOP_INT_RAW 2 1 TIMER2_TEP_INT_RAW 8 1 TIMER2_TEZ_INT_RAW 5 1 MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM 0x118 32 read-write n 0x0 0x0 CAP0_INT_ST 27 1 CAP1_INT_ST 28 1 CAP2_INT_ST 29 1 FAULT0_CLR_INT_ST 12 1 FAULT0_INT_ST 9 1 FAULT1_CLR_INT_ST 13 1 FAULT1_INT_ST 10 1 FAULT2_CLR_INT_ST 14 1 FAULT2_INT_ST 11 1 FH0_CBC_INT_ST 21 1 FH0_OST_INT_ST 24 1 FH1_CBC_INT_ST 22 1 FH1_OST_INT_ST 25 1 FH2_CBC_INT_ST 23 1 FH2_OST_INT_ST 26 1 OP0_TEA_INT_ST 15 1 OP0_TEB_INT_ST 18 1 OP1_TEA_INT_ST 16 1 OP1_TEB_INT_ST 19 1 OP2_TEA_INT_ST 17 1 OP2_TEB_INT_ST 20 1 TIMER0_STOP_INT_ST 0 1 TIMER0_TEP_INT_ST 6 1 TIMER0_TEZ_INT_ST 3 1 TIMER1_STOP_INT_ST 1 1 TIMER1_TEP_INT_ST 7 1 TIMER1_TEZ_INT_ST 4 1 TIMER2_STOP_INT_ST 2 1 TIMER2_TEP_INT_ST 8 1 TIMER2_TEZ_INT_ST 5 1 OPERATOR_TIMERSEL MCPWM_OPERATOR_TIMERSEL 0x38 32 read-write n 0x0 0x0 OPERATOR0_TIMERSEL 0 2 OPERATOR1_TIMERSEL 2 2 OPERATOR2_TIMERSEL 4 2 TIMER0_CFG0 MCPWM_TIMER0_CFG0 0x4 32 read-write n 0x0 0x0 TIMER0_PERIOD 8 16 TIMER0_PERIOD_UPMETHOD 24 2 TIMER0_PRESCALE 0 8 TIMER0_CFG1 MCPWM_TIMER0_CFG1 0x8 32 read-write n 0x0 0x0 TIMER0_MOD 3 2 TIMER0_START 0 3 TIMER0_STATUS MCPWM_TIMER0_STATUS 0x10 32 read-write n 0x0 0x0 TIMER0_DIRECTION 16 1 TIMER0_VALUE 0 16 TIMER0_SYNC MCPWM_TIMER0_SYNC 0xC 32 read-write n 0x0 0x0 TIMER0_PHASE 4 17 TIMER0_SYNCI_EN 0 1 TIMER0_SYNCO_SEL 2 2 TIMER0_SYNC_SW 1 1 TIMER1_CFG0 MCPWM_TIMER1_CFG0 0x14 32 read-write n 0x0 0x0 TIMER1_PERIOD 8 16 TIMER1_PERIOD_UPMETHOD 24 2 TIMER1_PRESCALE 0 8 TIMER1_CFG1 MCPWM_TIMER1_CFG1 0x18 32 read-write n 0x0 0x0 TIMER1_MOD 3 2 TIMER1_START 0 3 TIMER1_STATUS MCPWM_TIMER1_STATUS 0x20 32 read-write n 0x0 0x0 TIMER1_DIRECTION 16 1 TIMER1_VALUE 0 16 TIMER1_SYNC MCPWM_TIMER1_SYNC 0x1C 32 read-write n 0x0 0x0 TIMER1_PHASE 4 17 TIMER1_SYNCI_EN 0 1 TIMER1_SYNCO_SEL 2 2 TIMER1_SYNC_SW 1 1 TIMER2_CFG0 MCPWM_TIMER2_CFG0 0x24 32 read-write n 0x0 0x0 TIMER2_PERIOD 8 16 TIMER2_PERIOD_UPMETHOD 24 2 TIMER2_PRESCALE 0 8 TIMER2_CFG1 MCPWM_TIMER2_CFG1 0x28 32 read-write n 0x0 0x0 TIMER2_MOD 3 2 TIMER2_START 0 3 TIMER2_STATUS MCPWM_TIMER2_STATUS 0x30 32 read-write n 0x0 0x0 TIMER2_DIRECTION 16 1 TIMER2_VALUE 0 16 TIMER2_SYNC MCPWM_TIMER2_SYNC 0x2C 32 read-write n 0x0 0x0 TIMER2_PHASE 4 17 TIMER2_SYNCI_EN 0 1 TIMER2_SYNCO_SEL 2 2 TIMER2_SYNC_SW 1 1 TIMER_SYNCI_CFG MCPWM_TIMER_SYNCI_CFG 0x34 32 read-write n 0x0 0x0 EXTERNAL_SYNCI0_INVERT 9 1 EXTERNAL_SYNCI1_INVERT 10 1 EXTERNAL_SYNCI2_INVERT 11 1 TIMER0_SYNCISEL 0 3 TIMER1_SYNCISEL 3 3 TIMER2_SYNCISEL 6 3 UPDATE_CFG MCPWM_UPDATE_CFG 0x10C 32 read-write n 0x0 0x0 GLOBAL_FORCE_UP 1 1 GLOBAL_UP_EN 0 1 OP0_FORCE_UP 3 1 OP0_UP_EN 2 1 OP1_FORCE_UP 5 1 OP1_UP_EN 4 1 OP2_FORCE_UP 7 1 OP2_UP_EN 6 1 VERSION MCPWM_VERSION 0x124 32 read-write n 0x0 0x0 DATE 0 28 NRX NRX 0x0 0x0 0x0 registers n PCNT PCNT 0x0 0x0 0x5C0 registers n PCNT_INTR interrupt of pluse count, level 48 CTRL PCNT_CTRL 0xB0 32 read-write n 0x0 0x0 CLK_EN 16 1 CNT_PAUSE_U0 1 1 CNT_PAUSE_U1 3 1 CNT_PAUSE_U2 5 1 CNT_PAUSE_U3 7 1 CNT_PAUSE_U4 9 1 CNT_PAUSE_U5 11 1 CNT_PAUSE_U6 13 1 CNT_PAUSE_U7 15 1 PLUS_CNT_RST_U0 0 1 PLUS_CNT_RST_U1 2 1 PLUS_CNT_RST_U2 4 1 PLUS_CNT_RST_U3 6 1 PLUS_CNT_RST_U4 8 1 PLUS_CNT_RST_U5 10 1 PLUS_CNT_RST_U6 12 1 PLUS_CNT_RST_U7 14 1 DATE PCNT_DATE 0xFC 32 read-write n 0x0 0x0 DATE 0 32 INT_CLR PCNT_INT_CLR 0x8C 32 read-write n 0x0 0x0 CNT_THR_EVENT_U0_INT_CLR 0 1 CNT_THR_EVENT_U1_INT_CLR 1 1 CNT_THR_EVENT_U2_INT_CLR 2 1 CNT_THR_EVENT_U3_INT_CLR 3 1 CNT_THR_EVENT_U4_INT_CLR 4 1 CNT_THR_EVENT_U5_INT_CLR 5 1 CNT_THR_EVENT_U6_INT_CLR 6 1 CNT_THR_EVENT_U7_INT_CLR 7 1 INT_ENA PCNT_INT_ENA 0x88 32 read-write n 0x0 0x0 CNT_THR_EVENT_U0_INT_ENA 0 1 CNT_THR_EVENT_U1_INT_ENA 1 1 CNT_THR_EVENT_U2_INT_ENA 2 1 CNT_THR_EVENT_U3_INT_ENA 3 1 CNT_THR_EVENT_U4_INT_ENA 4 1 CNT_THR_EVENT_U5_INT_ENA 5 1 CNT_THR_EVENT_U6_INT_ENA 6 1 CNT_THR_EVENT_U7_INT_ENA 7 1 INT_RAW PCNT_INT_RAW 0x80 32 read-write n 0x0 0x0 CNT_THR_EVENT_U0_INT_RAW 0 1 CNT_THR_EVENT_U1_INT_RAW 1 1 CNT_THR_EVENT_U2_INT_RAW 2 1 CNT_THR_EVENT_U3_INT_RAW 3 1 CNT_THR_EVENT_U4_INT_RAW 4 1 CNT_THR_EVENT_U5_INT_RAW 5 1 CNT_THR_EVENT_U6_INT_RAW 6 1 CNT_THR_EVENT_U7_INT_RAW 7 1 INT_ST PCNT_INT_ST 0x84 32 read-write n 0x0 0x0 CNT_THR_EVENT_U0_INT_ST 0 1 CNT_THR_EVENT_U1_INT_ST 1 1 CNT_THR_EVENT_U2_INT_ST 2 1 CNT_THR_EVENT_U3_INT_ST 3 1 CNT_THR_EVENT_U4_INT_ST 4 1 CNT_THR_EVENT_U5_INT_ST 5 1 CNT_THR_EVENT_U6_INT_ST 6 1 CNT_THR_EVENT_U7_INT_ST 7 1 U0_CNT PCNT_U0_CNT 0x60 32 read-write n 0x0 0x0 PLUS_CNT_U0 0 16 U0_CONF0 PCNT_U0_CONF0 0x0 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U0 20 2 CH0_LCTRL_MODE_U0 22 2 CH0_NEG_MODE_U0 16 2 CH0_POS_MODE_U0 18 2 CH1_HCTRL_MODE_U0 28 2 CH1_LCTRL_MODE_U0 30 2 CH1_NEG_MODE_U0 24 2 CH1_POS_MODE_U0 26 2 FILTER_EN_U0 10 1 FILTER_THRES_U0 0 10 THR_H_LIM_EN_U0 12 1 THR_L_LIM_EN_U0 13 1 THR_THRES0_EN_U0 14 1 THR_THRES1_EN_U0 15 1 THR_ZERO_EN_U0 11 1 U0_CONF1 PCNT_U0_CONF1 0x4 32 read-write n 0x0 0x0 CNT_THRES0_U0 0 16 CNT_THRES1_U0 16 16 U0_CONF2 PCNT_U0_CONF2 0x8 32 read-write n 0x0 0x0 CNT_H_LIM_U0 0 16 CNT_L_LIM_U0 16 16 U0_STATUS PCNT_U0_STATUS 0x90 32 read-write n 0x0 0x0 CORE_STATUS_U0 0 32 U1_CNT PCNT_U1_CNT 0x64 32 read-write n 0x0 0x0 PLUS_CNT_U1 0 16 U1_CONF0 PCNT_U1_CONF0 0xC 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U1 20 2 CH0_LCTRL_MODE_U1 22 2 CH0_NEG_MODE_U1 16 2 CH0_POS_MODE_U1 18 2 CH1_HCTRL_MODE_U1 28 2 CH1_LCTRL_MODE_U1 30 2 CH1_NEG_MODE_U1 24 2 CH1_POS_MODE_U1 26 2 FILTER_EN_U1 10 1 FILTER_THRES_U1 0 10 THR_H_LIM_EN_U1 12 1 THR_L_LIM_EN_U1 13 1 THR_THRES0_EN_U1 14 1 THR_THRES1_EN_U1 15 1 THR_ZERO_EN_U1 11 1 U1_CONF1 PCNT_U1_CONF1 0x10 32 read-write n 0x0 0x0 CNT_THRES0_U1 0 16 CNT_THRES1_U1 16 16 U1_CONF2 PCNT_U1_CONF2 0x14 32 read-write n 0x0 0x0 CNT_H_LIM_U1 0 16 CNT_L_LIM_U1 16 16 U1_STATUS PCNT_U1_STATUS 0x94 32 read-write n 0x0 0x0 CORE_STATUS_U1 0 32 U2_CNT PCNT_U2_CNT 0x68 32 read-write n 0x0 0x0 PLUS_CNT_U2 0 16 U2_CONF0 PCNT_U2_CONF0 0x18 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U2 20 2 CH0_LCTRL_MODE_U2 22 2 CH0_NEG_MODE_U2 16 2 CH0_POS_MODE_U2 18 2 CH1_HCTRL_MODE_U2 28 2 CH1_LCTRL_MODE_U2 30 2 CH1_NEG_MODE_U2 24 2 CH1_POS_MODE_U2 26 2 FILTER_EN_U2 10 1 FILTER_THRES_U2 0 10 THR_H_LIM_EN_U2 12 1 THR_L_LIM_EN_U2 13 1 THR_THRES0_EN_U2 14 1 THR_THRES1_EN_U2 15 1 THR_ZERO_EN_U2 11 1 U2_CONF1 PCNT_U2_CONF1 0x1C 32 read-write n 0x0 0x0 CNT_THRES0_U2 0 16 CNT_THRES1_U2 16 16 U2_CONF2 PCNT_U2_CONF2 0x20 32 read-write n 0x0 0x0 CNT_H_LIM_U2 0 16 CNT_L_LIM_U2 16 16 U2_STATUS PCNT_U2_STATUS 0x98 32 read-write n 0x0 0x0 CORE_STATUS_U2 0 32 U3_CNT PCNT_U3_CNT 0x6C 32 read-write n 0x0 0x0 PLUS_CNT_U3 0 16 U3_CONF0 PCNT_U3_CONF0 0x24 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U3 20 2 CH0_LCTRL_MODE_U3 22 2 CH0_NEG_MODE_U3 16 2 CH0_POS_MODE_U3 18 2 CH1_HCTRL_MODE_U3 28 2 CH1_LCTRL_MODE_U3 30 2 CH1_NEG_MODE_U3 24 2 CH1_POS_MODE_U3 26 2 FILTER_EN_U3 10 1 FILTER_THRES_U3 0 10 THR_H_LIM_EN_U3 12 1 THR_L_LIM_EN_U3 13 1 THR_THRES0_EN_U3 14 1 THR_THRES1_EN_U3 15 1 THR_ZERO_EN_U3 11 1 U3_CONF1 PCNT_U3_CONF1 0x28 32 read-write n 0x0 0x0 CNT_THRES0_U3 0 16 CNT_THRES1_U3 16 16 U3_CONF2 PCNT_U3_CONF2 0x2C 32 read-write n 0x0 0x0 CNT_H_LIM_U3 0 16 CNT_L_LIM_U3 16 16 U3_STATUS PCNT_U3_STATUS 0x9C 32 read-write n 0x0 0x0 CORE_STATUS_U3 0 32 U4_CNT PCNT_U4_CNT 0x70 32 read-write n 0x0 0x0 PLUS_CNT_U4 0 16 U4_CONF0 PCNT_U4_CONF0 0x30 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U4 20 2 CH0_LCTRL_MODE_U4 22 2 CH0_NEG_MODE_U4 16 2 CH0_POS_MODE_U4 18 2 CH1_HCTRL_MODE_U4 28 2 CH1_LCTRL_MODE_U4 30 2 CH1_NEG_MODE_U4 24 2 CH1_POS_MODE_U4 26 2 FILTER_EN_U4 10 1 FILTER_THRES_U4 0 10 THR_H_LIM_EN_U4 12 1 THR_L_LIM_EN_U4 13 1 THR_THRES0_EN_U4 14 1 THR_THRES1_EN_U4 15 1 THR_ZERO_EN_U4 11 1 U4_CONF1 PCNT_U4_CONF1 0x34 32 read-write n 0x0 0x0 CNT_THRES0_U4 0 16 CNT_THRES1_U4 16 16 U4_CONF2 PCNT_U4_CONF2 0x38 32 read-write n 0x0 0x0 CNT_H_LIM_U4 0 16 CNT_L_LIM_U4 16 16 U4_STATUS PCNT_U4_STATUS 0xA0 32 read-write n 0x0 0x0 CORE_STATUS_U4 0 32 U5_CNT PCNT_U5_CNT 0x74 32 read-write n 0x0 0x0 PLUS_CNT_U5 0 16 U5_CONF0 PCNT_U5_CONF0 0x3C 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U5 20 2 CH0_LCTRL_MODE_U5 22 2 CH0_NEG_MODE_U5 16 2 CH0_POS_MODE_U5 18 2 CH1_HCTRL_MODE_U5 28 2 CH1_LCTRL_MODE_U5 30 2 CH1_NEG_MODE_U5 24 2 CH1_POS_MODE_U5 26 2 FILTER_EN_U5 10 1 FILTER_THRES_U5 0 10 THR_H_LIM_EN_U5 12 1 THR_L_LIM_EN_U5 13 1 THR_THRES0_EN_U5 14 1 THR_THRES1_EN_U5 15 1 THR_ZERO_EN_U5 11 1 U5_CONF1 PCNT_U5_CONF1 0x40 32 read-write n 0x0 0x0 CNT_THRES0_U5 0 16 CNT_THRES1_U5 16 16 U5_CONF2 PCNT_U5_CONF2 0x44 32 read-write n 0x0 0x0 CNT_H_LIM_U5 0 16 CNT_L_LIM_U5 16 16 U5_STATUS PCNT_U5_STATUS 0xA4 32 read-write n 0x0 0x0 CORE_STATUS_U5 0 32 U6_CNT PCNT_U6_CNT 0x78 32 read-write n 0x0 0x0 PLUS_CNT_U6 0 16 U6_CONF0 PCNT_U6_CONF0 0x48 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U6 20 2 CH0_LCTRL_MODE_U6 22 2 CH0_NEG_MODE_U6 16 2 CH0_POS_MODE_U6 18 2 CH1_HCTRL_MODE_U6 28 2 CH1_LCTRL_MODE_U6 30 2 CH1_NEG_MODE_U6 24 2 CH1_POS_MODE_U6 26 2 FILTER_EN_U6 10 1 FILTER_THRES_U6 0 10 THR_H_LIM_EN_U6 12 1 THR_L_LIM_EN_U6 13 1 THR_THRES0_EN_U6 14 1 THR_THRES1_EN_U6 15 1 THR_ZERO_EN_U6 11 1 U6_CONF1 PCNT_U6_CONF1 0x4C 32 read-write n 0x0 0x0 CNT_THRES0_U6 0 16 CNT_THRES1_U6 16 16 U6_CONF2 PCNT_U6_CONF2 0x50 32 read-write n 0x0 0x0 CNT_H_LIM_U6 0 16 CNT_L_LIM_U6 16 16 U6_STATUS PCNT_U6_STATUS 0xA8 32 read-write n 0x0 0x0 CORE_STATUS_U6 0 32 U7_CNT PCNT_U7_CNT 0x7C 32 read-write n 0x0 0x0 PLUS_CNT_U7 0 16 U7_CONF0 PCNT_U7_CONF0 0x54 32 read-write n 0x0 0x0 CH0_HCTRL_MODE_U7 20 2 CH0_LCTRL_MODE_U7 22 2 CH0_NEG_MODE_U7 16 2 CH0_POS_MODE_U7 18 2 CH1_HCTRL_MODE_U7 28 2 CH1_LCTRL_MODE_U7 30 2 CH1_NEG_MODE_U7 24 2 CH1_POS_MODE_U7 26 2 FILTER_EN_U7 10 1 FILTER_THRES_U7 0 10 THR_H_LIM_EN_U7 12 1 THR_L_LIM_EN_U7 13 1 THR_THRES0_EN_U7 14 1 THR_THRES1_EN_U7 15 1 THR_ZERO_EN_U7 11 1 U7_CONF1 PCNT_U7_CONF1 0x58 32 read-write n 0x0 0x0 CNT_THRES0_U7 0 16 CNT_THRES1_U7 16 16 U7_CONF2 PCNT_U7_CONF2 0x5C 32 read-write n 0x0 0x0 CNT_H_LIM_U7 0 16 CNT_L_LIM_U7 16 16 U7_STATUS PCNT_U7_STATUS 0xAC 32 read-write n 0x0 0x0 CORE_STATUS_U7 0 32 PWM0 MCPWM 0x0 0x0 0x940 registers n CAP_CH0 MCPWM_CAP_CH0 0xFC 32 read-write n 0x0 0x0 CAP0_VALUE 0 32 CAP_CH0_CFG MCPWM_CAP_CH0_CFG 0xF0 32 read-write n 0x0 0x0 CAP0_EN 0 1 CAP0_IN_INVERT 11 1 CAP0_MODE 1 2 CAP0_PRESCALE 3 8 CAP0_SW 12 1 CAP_CH1 MCPWM_CAP_CH1 0x100 32 read-write n 0x0 0x0 CAP1_VALUE 0 32 CAP_CH1_CFG MCPWM_CAP_CH1_CFG 0xF4 32 read-write n 0x0 0x0 CAP1_EN 0 1 CAP1_IN_INVERT 11 1 CAP1_MODE 1 2 CAP1_PRESCALE 3 8 CAP1_SW 12 1 CAP_CH2 MCPWM_CAP_CH2 0x104 32 read-write n 0x0 0x0 CAP2_VALUE 0 32 CAP_CH2_CFG MCPWM_CAP_CH2_CFG 0xF8 32 read-write n 0x0 0x0 CAP2_EN 0 1 CAP2_IN_INVERT 11 1 CAP2_MODE 1 2 CAP2_PRESCALE 3 8 CAP2_SW 12 1 CAP_STATUS MCPWM_CAP_STATUS 0x108 32 read-write n 0x0 0x0 CAP0_EDGE 0 1 CAP1_EDGE 1 1 CAP2_EDGE 2 1 CAP_TIMER_CFG MCPWM_CAP_TIMER_CFG 0xE8 32 read-write n 0x0 0x0 CAP_SYNCI_EN 1 1 CAP_SYNCI_SEL 2 3 CAP_SYNC_SW 5 1 CAP_TIMER_EN 0 1 CAP_TIMER_PHASE MCPWM_CAP_TIMER_PHASE 0xEC 32 read-write n 0x0 0x0 CAP_PHASE 0 32 CARRIER0_CFG MCPWM_CARRIER0_CFG 0x64 32 read-write n 0x0 0x0 CARRIER0_DUTY 5 3 CARRIER0_EN 0 1 CARRIER0_IN_INVERT 13 1 CARRIER0_OSHWTH 8 4 CARRIER0_OUT_INVERT 12 1 CARRIER0_PRESCALE 1 4 CARRIER1_CFG MCPWM_CARRIER1_CFG 0x9C 32 read-write n 0x0 0x0 CARRIER1_DUTY 5 3 CARRIER1_EN 0 1 CARRIER1_IN_INVERT 13 1 CARRIER1_OSHWTH 8 4 CARRIER1_OUT_INVERT 12 1 CARRIER1_PRESCALE 1 4 CARRIER2_CFG MCPWM_CARRIER2_CFG 0xD4 32 read-write n 0x0 0x0 CARRIER2_DUTY 5 3 CARRIER2_EN 0 1 CARRIER2_IN_INVERT 13 1 CARRIER2_OSHWTH 8 4 CARRIER2_OUT_INVERT 12 1 CARRIER2_PRESCALE 1 4 CLK MCPWM_CLK 0x120 32 read-write n 0x0 0x0 CLK_EN 0 1 CLK_CFG MCPWM_CLK_CFG 0x0 32 read-write n 0x0 0x0 CLK_PRESCALE 0 8 DT0_CFG MCPWM_DT0_CFG 0x58 32 read-write n 0x0 0x0 DT0_A_OUTBYPASS 15 1 DT0_A_OUTSWAP 9 1 DT0_B_OUTBYPASS 16 1 DT0_B_OUTSWAP 10 1 DT0_CLK_SEL 17 1 DT0_DEB_MODE 8 1 DT0_FED_INSEL 12 1 DT0_FED_OUTINVERT 14 1 DT0_FED_UPMETHOD 0 4 DT0_RED_INSEL 11 1 DT0_RED_OUTINVERT 13 1 DT0_RED_UPMETHOD 4 4 DT0_FED_CFG MCPWM_DT0_FED_CFG 0x5C 32 read-write n 0x0 0x0 DT0_FED 0 16 DT0_RED_CFG MCPWM_DT0_RED_CFG 0x60 32 read-write n 0x0 0x0 DT0_RED 0 16 DT1_CFG MCPWM_DT1_CFG 0x90 32 read-write n 0x0 0x0 DT1_A_OUTBYPASS 15 1 DT1_A_OUTSWAP 9 1 DT1_B_OUTBYPASS 16 1 DT1_B_OUTSWAP 10 1 DT1_CLK_SEL 17 1 DT1_DEB_MODE 8 1 DT1_FED_INSEL 12 1 DT1_FED_OUTINVERT 14 1 DT1_FED_UPMETHOD 0 4 DT1_RED_INSEL 11 1 DT1_RED_OUTINVERT 13 1 DT1_RED_UPMETHOD 4 4 DT1_FED_CFG MCPWM_DT1_FED_CFG 0x94 32 read-write n 0x0 0x0 DT1_FED 0 16 DT1_RED_CFG MCPWM_DT1_RED_CFG 0x98 32 read-write n 0x0 0x0 DT1_RED 0 16 DT2_CFG MCPWM_DT2_CFG 0xC8 32 read-write n 0x0 0x0 DT2_A_OUTBYPASS 15 1 DT2_A_OUTSWAP 9 1 DT2_B_OUTBYPASS 16 1 DT2_B_OUTSWAP 10 1 DT2_CLK_SEL 17 1 DT2_DEB_MODE 8 1 DT2_FED_INSEL 12 1 DT2_FED_OUTINVERT 14 1 DT2_FED_UPMETHOD 0 4 DT2_RED_INSEL 11 1 DT2_RED_OUTINVERT 13 1 DT2_RED_UPMETHOD 4 4 DT2_FED_CFG MCPWM_DT2_FED_CFG 0xCC 32 read-write n 0x0 0x0 DT2_FED 0 16 DT2_RED_CFG MCPWM_DT2_RED_CFG 0xD0 32 read-write n 0x0 0x0 DT2_RED 0 16 FAULT_DETECT MCPWM_FAULT_DETECT 0xE4 32 read-write n 0x0 0x0 EVENT_F0 6 1 EVENT_F1 7 1 EVENT_F2 8 1 F0_EN 0 1 F0_POLE 3 1 F1_EN 1 1 F1_POLE 4 1 F2_EN 2 1 F2_POLE 5 1 FH0_CFG0 MCPWM_FH0_CFG0 0x68 32 read-write n 0x0 0x0 FH0_A_CBC_D 8 2 FH0_A_CBC_U 10 2 FH0_A_OST_D 12 2 FH0_A_OST_U 14 2 FH0_B_CBC_D 16 2 FH0_B_CBC_U 18 2 FH0_B_OST_D 20 2 FH0_B_OST_U 22 2 FH0_F0_CBC 3 1 FH0_F0_OST 7 1 FH0_F1_CBC 2 1 FH0_F1_OST 6 1 FH0_F2_CBC 1 1 FH0_F2_OST 5 1 FH0_SW_CBC 0 1 FH0_SW_OST 4 1 FH0_CFG1 MCPWM_FH0_CFG1 0x6C 32 read-write n 0x0 0x0 FH0_CBCPULSE 1 2 FH0_CLR_OST 0 1 FH0_FORCE_CBC 3 1 FH0_FORCE_OST 4 1 FH0_STATUS MCPWM_FH0_STATUS 0x70 32 read-write n 0x0 0x0 FH0_CBC_ON 0 1 FH0_OST_ON 1 1 FH1_CFG0 MCPWM_FH1_CFG0 0xA0 32 read-write n 0x0 0x0 FH1_A_CBC_D 8 2 FH1_A_CBC_U 10 2 FH1_A_OST_D 12 2 FH1_A_OST_U 14 2 FH1_B_CBC_D 16 2 FH1_B_CBC_U 18 2 FH1_B_OST_D 20 2 FH1_B_OST_U 22 2 FH1_F0_CBC 3 1 FH1_F0_OST 7 1 FH1_F1_CBC 2 1 FH1_F1_OST 6 1 FH1_F2_CBC 1 1 FH1_F2_OST 5 1 FH1_SW_CBC 0 1 FH1_SW_OST 4 1 FH1_CFG1 MCPWM_FH1_CFG1 0xA4 32 read-write n 0x0 0x0 FH1_CBCPULSE 1 2 FH1_CLR_OST 0 1 FH1_FORCE_CBC 3 1 FH1_FORCE_OST 4 1 FH1_STATUS MCPWM_FH1_STATUS 0xA8 32 read-write n 0x0 0x0 FH1_CBC_ON 0 1 FH1_OST_ON 1 1 FH2_CFG0 MCPWM_FH2_CFG0 0xD8 32 read-write n 0x0 0x0 FH2_A_CBC_D 8 2 FH2_A_CBC_U 10 2 FH2_A_OST_D 12 2 FH2_A_OST_U 14 2 FH2_B_CBC_D 16 2 FH2_B_CBC_U 18 2 FH2_B_OST_D 20 2 FH2_B_OST_U 22 2 FH2_F0_CBC 3 1 FH2_F0_OST 7 1 FH2_F1_CBC 2 1 FH2_F1_OST 6 1 FH2_F2_CBC 1 1 FH2_F2_OST 5 1 FH2_SW_CBC 0 1 FH2_SW_OST 4 1 FH2_CFG1 MCPWM_FH2_CFG1 0xDC 32 read-write n 0x0 0x0 FH2_CBCPULSE 1 2 FH2_CLR_OST 0 1 FH2_FORCE_CBC 3 1 FH2_FORCE_OST 4 1 FH2_STATUS MCPWM_FH2_STATUS 0xE0 32 read-write n 0x0 0x0 FH2_CBC_ON 0 1 FH2_OST_ON 1 1 GEN0_A MCPWM_GEN0_A 0x50 32 read-write n 0x0 0x0 GEN0_A_DT0 20 2 GEN0_A_DT1 22 2 GEN0_A_DTEA 16 2 GEN0_A_DTEB 18 2 GEN0_A_DTEP 14 2 GEN0_A_DTEZ 12 2 GEN0_A_UT0 8 2 GEN0_A_UT1 10 2 GEN0_A_UTEA 4 2 GEN0_A_UTEB 6 2 GEN0_A_UTEP 2 2 GEN0_A_UTEZ 0 2 GEN0_B MCPWM_GEN0_B 0x54 32 read-write n 0x0 0x0 GEN0_B_DT0 20 2 GEN0_B_DT1 22 2 GEN0_B_DTEA 16 2 GEN0_B_DTEB 18 2 GEN0_B_DTEP 14 2 GEN0_B_DTEZ 12 2 GEN0_B_UT0 8 2 GEN0_B_UT1 10 2 GEN0_B_UTEA 4 2 GEN0_B_UTEB 6 2 GEN0_B_UTEP 2 2 GEN0_B_UTEZ 0 2 GEN0_CFG0 MCPWM_GEN0_CFG0 0x48 32 read-write n 0x0 0x0 GEN0_CFG_UPMETHOD 0 4 GEN0_T0_SEL 4 3 GEN0_T1_SEL 7 3 GEN0_FORCE MCPWM_GEN0_FORCE 0x4C 32 read-write n 0x0 0x0 GEN0_A_CNTUFORCE_MODE 6 2 GEN0_A_NCIFORCE 10 1 GEN0_A_NCIFORCE_MODE 11 2 GEN0_B_CNTUFORCE_MODE 8 2 GEN0_B_NCIFORCE 13 1 GEN0_B_NCIFORCE_MODE 14 2 GEN0_CNTUFORCE_UPMETHOD 0 6 GEN0_STMP_CFG MCPWM_GEN0_STMP_CFG 0x3C 32 read-write n 0x0 0x0 GEN0_A_SHDW_FULL 8 1 GEN0_A_UPMETHOD 0 4 GEN0_B_SHDW_FULL 9 1 GEN0_B_UPMETHOD 4 4 GEN0_TSTMP_A MCPWM_GEN0_TSTMP_A 0x40 32 read-write n 0x0 0x0 GEN0_A 0 16 GEN0_TSTMP_B MCPWM_GEN0_TSTMP_B 0x44 32 read-write n 0x0 0x0 GEN0_B 0 16 GEN1_A MCPWM_GEN1_A 0x88 32 read-write n 0x0 0x0 GEN1_A_DT0 20 2 GEN1_A_DT1 22 2 GEN1_A_DTEA 16 2 GEN1_A_DTEB 18 2 GEN1_A_DTEP 14 2 GEN1_A_DTEZ 12 2 GEN1_A_UT0 8 2 GEN1_A_UT1 10 2 GEN1_A_UTEA 4 2 GEN1_A_UTEB 6 2 GEN1_A_UTEP 2 2 GEN1_A_UTEZ 0 2 GEN1_B MCPWM_GEN1_B 0x8C 32 read-write n 0x0 0x0 GEN1_B_DT0 20 2 GEN1_B_DT1 22 2 GEN1_B_DTEA 16 2 GEN1_B_DTEB 18 2 GEN1_B_DTEP 14 2 GEN1_B_DTEZ 12 2 GEN1_B_UT0 8 2 GEN1_B_UT1 10 2 GEN1_B_UTEA 4 2 GEN1_B_UTEB 6 2 GEN1_B_UTEP 2 2 GEN1_B_UTEZ 0 2 GEN1_CFG0 MCPWM_GEN1_CFG0 0x80 32 read-write n 0x0 0x0 GEN1_CFG_UPMETHOD 0 4 GEN1_T0_SEL 4 3 GEN1_T1_SEL 7 3 GEN1_FORCE MCPWM_GEN1_FORCE 0x84 32 read-write n 0x0 0x0 GEN1_A_CNTUFORCE_MODE 6 2 GEN1_A_NCIFORCE 10 1 GEN1_A_NCIFORCE_MODE 11 2 GEN1_B_CNTUFORCE_MODE 8 2 GEN1_B_NCIFORCE 13 1 GEN1_B_NCIFORCE_MODE 14 2 GEN1_CNTUFORCE_UPMETHOD 0 6 GEN1_STMP_CFG MCPWM_GEN1_STMP_CFG 0x74 32 read-write n 0x0 0x0 GEN1_A_SHDW_FULL 8 1 GEN1_A_UPMETHOD 0 4 GEN1_B_SHDW_FULL 9 1 GEN1_B_UPMETHOD 4 4 GEN1_TSTMP_A MCPWM_GEN1_TSTMP_A 0x78 32 read-write n 0x0 0x0 GEN1_A 0 16 GEN1_TSTMP_B MCPWM_GEN1_TSTMP_B 0x7C 32 read-write n 0x0 0x0 GEN1_B 0 16 GEN2_A MCPWM_GEN2_A 0xC0 32 read-write n 0x0 0x0 GEN2_A_DT0 20 2 GEN2_A_DT1 22 2 GEN2_A_DTEA 16 2 GEN2_A_DTEB 18 2 GEN2_A_DTEP 14 2 GEN2_A_DTEZ 12 2 GEN2_A_UT0 8 2 GEN2_A_UT1 10 2 GEN2_A_UTEA 4 2 GEN2_A_UTEB 6 2 GEN2_A_UTEP 2 2 GEN2_A_UTEZ 0 2 GEN2_B MCPWM_GEN2_B 0xC4 32 read-write n 0x0 0x0 GEN2_B_DT0 20 2 GEN2_B_DT1 22 2 GEN2_B_DTEA 16 2 GEN2_B_DTEB 18 2 GEN2_B_DTEP 14 2 GEN2_B_DTEZ 12 2 GEN2_B_UT0 8 2 GEN2_B_UT1 10 2 GEN2_B_UTEA 4 2 GEN2_B_UTEB 6 2 GEN2_B_UTEP 2 2 GEN2_B_UTEZ 0 2 GEN2_CFG0 MCPWM_GEN2_CFG0 0xB8 32 read-write n 0x0 0x0 GEN2_CFG_UPMETHOD 0 4 GEN2_T0_SEL 4 3 GEN2_T1_SEL 7 3 GEN2_FORCE MCPWM_GEN2_FORCE 0xBC 32 read-write n 0x0 0x0 GEN2_A_CNTUFORCE_MODE 6 2 GEN2_A_NCIFORCE 10 1 GEN2_A_NCIFORCE_MODE 11 2 GEN2_B_CNTUFORCE_MODE 8 2 GEN2_B_NCIFORCE 13 1 GEN2_B_NCIFORCE_MODE 14 2 GEN2_CNTUFORCE_UPMETHOD 0 6 GEN2_STMP_CFG MCPWM_GEN2_STMP_CFG 0xAC 32 read-write n 0x0 0x0 GEN2_A_SHDW_FULL 8 1 GEN2_A_UPMETHOD 0 4 GEN2_B_SHDW_FULL 9 1 GEN2_B_UPMETHOD 4 4 GEN2_TSTMP_A MCPWM_GEN2_TSTMP_A 0xB0 32 read-write n 0x0 0x0 GEN2_A 0 16 GEN2_TSTMP_B MCPWM_GEN2_TSTMP_B 0xB4 32 read-write n 0x0 0x0 GEN2_B 0 16 MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM 0x11C 32 read-write n 0x0 0x0 CAP0_INT_CLR 27 1 CAP1_INT_CLR 28 1 CAP2_INT_CLR 29 1 FAULT0_CLR_INT_CLR 12 1 FAULT0_INT_CLR 9 1 FAULT1_CLR_INT_CLR 13 1 FAULT1_INT_CLR 10 1 FAULT2_CLR_INT_CLR 14 1 FAULT2_INT_CLR 11 1 FH0_CBC_INT_CLR 21 1 FH0_OST_INT_CLR 24 1 FH1_CBC_INT_CLR 22 1 FH1_OST_INT_CLR 25 1 FH2_CBC_INT_CLR 23 1 FH2_OST_INT_CLR 26 1 OP0_TEA_INT_CLR 15 1 OP0_TEB_INT_CLR 18 1 OP1_TEA_INT_CLR 16 1 OP1_TEB_INT_CLR 19 1 OP2_TEA_INT_CLR 17 1 OP2_TEB_INT_CLR 20 1 TIMER0_STOP_INT_CLR 0 1 TIMER0_TEP_INT_CLR 6 1 TIMER0_TEZ_INT_CLR 3 1 TIMER1_STOP_INT_CLR 1 1 TIMER1_TEP_INT_CLR 7 1 TIMER1_TEZ_INT_CLR 4 1 TIMER2_STOP_INT_CLR 2 1 TIMER2_TEP_INT_CLR 8 1 TIMER2_TEZ_INT_CLR 5 1 MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM 0x110 32 read-write n 0x0 0x0 CAP0_INT_ENA 27 1 CAP1_INT_ENA 28 1 CAP2_INT_ENA 29 1 FAULT0_CLR_INT_ENA 12 1 FAULT0_INT_ENA 9 1 FAULT1_CLR_INT_ENA 13 1 FAULT1_INT_ENA 10 1 FAULT2_CLR_INT_ENA 14 1 FAULT2_INT_ENA 11 1 FH0_CBC_INT_ENA 21 1 FH0_OST_INT_ENA 24 1 FH1_CBC_INT_ENA 22 1 FH1_OST_INT_ENA 25 1 FH2_CBC_INT_ENA 23 1 FH2_OST_INT_ENA 26 1 OP0_TEA_INT_ENA 15 1 OP0_TEB_INT_ENA 18 1 OP1_TEA_INT_ENA 16 1 OP1_TEB_INT_ENA 19 1 OP2_TEA_INT_ENA 17 1 OP2_TEB_INT_ENA 20 1 TIMER0_STOP_INT_ENA 0 1 TIMER0_TEP_INT_ENA 6 1 TIMER0_TEZ_INT_ENA 3 1 TIMER1_STOP_INT_ENA 1 1 TIMER1_TEP_INT_ENA 7 1 TIMER1_TEZ_INT_ENA 4 1 TIMER2_STOP_INT_ENA 2 1 TIMER2_TEP_INT_ENA 8 1 TIMER2_TEZ_INT_ENA 5 1 MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM 0x114 32 read-write n 0x0 0x0 CAP0_INT_RAW 27 1 CAP1_INT_RAW 28 1 CAP2_INT_RAW 29 1 FAULT0_CLR_INT_RAW 12 1 FAULT0_INT_RAW 9 1 FAULT1_CLR_INT_RAW 13 1 FAULT1_INT_RAW 10 1 FAULT2_CLR_INT_RAW 14 1 FAULT2_INT_RAW 11 1 FH0_CBC_INT_RAW 21 1 FH0_OST_INT_RAW 24 1 FH1_CBC_INT_RAW 22 1 FH1_OST_INT_RAW 25 1 FH2_CBC_INT_RAW 23 1 FH2_OST_INT_RAW 26 1 OP0_TEA_INT_RAW 15 1 OP0_TEB_INT_RAW 18 1 OP1_TEA_INT_RAW 16 1 OP1_TEB_INT_RAW 19 1 OP2_TEA_INT_RAW 17 1 OP2_TEB_INT_RAW 20 1 TIMER0_STOP_INT_RAW 0 1 TIMER0_TEP_INT_RAW 6 1 TIMER0_TEZ_INT_RAW 3 1 TIMER1_STOP_INT_RAW 1 1 TIMER1_TEP_INT_RAW 7 1 TIMER1_TEZ_INT_RAW 4 1 TIMER2_STOP_INT_RAW 2 1 TIMER2_TEP_INT_RAW 8 1 TIMER2_TEZ_INT_RAW 5 1 MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM 0x118 32 read-write n 0x0 0x0 CAP0_INT_ST 27 1 CAP1_INT_ST 28 1 CAP2_INT_ST 29 1 FAULT0_CLR_INT_ST 12 1 FAULT0_INT_ST 9 1 FAULT1_CLR_INT_ST 13 1 FAULT1_INT_ST 10 1 FAULT2_CLR_INT_ST 14 1 FAULT2_INT_ST 11 1 FH0_CBC_INT_ST 21 1 FH0_OST_INT_ST 24 1 FH1_CBC_INT_ST 22 1 FH1_OST_INT_ST 25 1 FH2_CBC_INT_ST 23 1 FH2_OST_INT_ST 26 1 OP0_TEA_INT_ST 15 1 OP0_TEB_INT_ST 18 1 OP1_TEA_INT_ST 16 1 OP1_TEB_INT_ST 19 1 OP2_TEA_INT_ST 17 1 OP2_TEB_INT_ST 20 1 TIMER0_STOP_INT_ST 0 1 TIMER0_TEP_INT_ST 6 1 TIMER0_TEZ_INT_ST 3 1 TIMER1_STOP_INT_ST 1 1 TIMER1_TEP_INT_ST 7 1 TIMER1_TEZ_INT_ST 4 1 TIMER2_STOP_INT_ST 2 1 TIMER2_TEP_INT_ST 8 1 TIMER2_TEZ_INT_ST 5 1 OPERATOR_TIMERSEL MCPWM_OPERATOR_TIMERSEL 0x38 32 read-write n 0x0 0x0 OPERATOR0_TIMERSEL 0 2 OPERATOR1_TIMERSEL 2 2 OPERATOR2_TIMERSEL 4 2 TIMER0_CFG0 MCPWM_TIMER0_CFG0 0x4 32 read-write n 0x0 0x0 TIMER0_PERIOD 8 16 TIMER0_PERIOD_UPMETHOD 24 2 TIMER0_PRESCALE 0 8 TIMER0_CFG1 MCPWM_TIMER0_CFG1 0x8 32 read-write n 0x0 0x0 TIMER0_MOD 3 2 TIMER0_START 0 3 TIMER0_STATUS MCPWM_TIMER0_STATUS 0x10 32 read-write n 0x0 0x0 TIMER0_DIRECTION 16 1 TIMER0_VALUE 0 16 TIMER0_SYNC MCPWM_TIMER0_SYNC 0xC 32 read-write n 0x0 0x0 TIMER0_PHASE 4 17 TIMER0_SYNCI_EN 0 1 TIMER0_SYNCO_SEL 2 2 TIMER0_SYNC_SW 1 1 TIMER1_CFG0 MCPWM_TIMER1_CFG0 0x14 32 read-write n 0x0 0x0 TIMER1_PERIOD 8 16 TIMER1_PERIOD_UPMETHOD 24 2 TIMER1_PRESCALE 0 8 TIMER1_CFG1 MCPWM_TIMER1_CFG1 0x18 32 read-write n 0x0 0x0 TIMER1_MOD 3 2 TIMER1_START 0 3 TIMER1_STATUS MCPWM_TIMER1_STATUS 0x20 32 read-write n 0x0 0x0 TIMER1_DIRECTION 16 1 TIMER1_VALUE 0 16 TIMER1_SYNC MCPWM_TIMER1_SYNC 0x1C 32 read-write n 0x0 0x0 TIMER1_PHASE 4 17 TIMER1_SYNCI_EN 0 1 TIMER1_SYNCO_SEL 2 2 TIMER1_SYNC_SW 1 1 TIMER2_CFG0 MCPWM_TIMER2_CFG0 0x24 32 read-write n 0x0 0x0 TIMER2_PERIOD 8 16 TIMER2_PERIOD_UPMETHOD 24 2 TIMER2_PRESCALE 0 8 TIMER2_CFG1 MCPWM_TIMER2_CFG1 0x28 32 read-write n 0x0 0x0 TIMER2_MOD 3 2 TIMER2_START 0 3 TIMER2_STATUS MCPWM_TIMER2_STATUS 0x30 32 read-write n 0x0 0x0 TIMER2_DIRECTION 16 1 TIMER2_VALUE 0 16 TIMER2_SYNC MCPWM_TIMER2_SYNC 0x2C 32 read-write n 0x0 0x0 TIMER2_PHASE 4 17 TIMER2_SYNCI_EN 0 1 TIMER2_SYNCO_SEL 2 2 TIMER2_SYNC_SW 1 1 TIMER_SYNCI_CFG MCPWM_TIMER_SYNCI_CFG 0x34 32 read-write n 0x0 0x0 EXTERNAL_SYNCI0_INVERT 9 1 EXTERNAL_SYNCI1_INVERT 10 1 EXTERNAL_SYNCI2_INVERT 11 1 TIMER0_SYNCISEL 0 3 TIMER1_SYNCISEL 3 3 TIMER2_SYNCISEL 6 3 UPDATE_CFG MCPWM_UPDATE_CFG 0x10C 32 read-write n 0x0 0x0 GLOBAL_FORCE_UP 1 1 GLOBAL_UP_EN 0 1 OP0_FORCE_UP 3 1 OP0_UP_EN 2 1 OP1_FORCE_UP 5 1 OP1_UP_EN 4 1 OP2_FORCE_UP 7 1 OP2_UP_EN 6 1 VERSION MCPWM_VERSION 0x124 32 read-write n 0x0 0x0 DATE 0 28 PWM1 MCPWM 0x0 0x0 0x940 registers n CAP_CH0 MCPWM_CAP_CH0 0xFC 32 read-write n 0x0 0x0 CAP0_VALUE 0 32 CAP_CH0_CFG MCPWM_CAP_CH0_CFG 0xF0 32 read-write n 0x0 0x0 CAP0_EN 0 1 CAP0_IN_INVERT 11 1 CAP0_MODE 1 2 CAP0_PRESCALE 3 8 CAP0_SW 12 1 CAP_CH1 MCPWM_CAP_CH1 0x100 32 read-write n 0x0 0x0 CAP1_VALUE 0 32 CAP_CH1_CFG MCPWM_CAP_CH1_CFG 0xF4 32 read-write n 0x0 0x0 CAP1_EN 0 1 CAP1_IN_INVERT 11 1 CAP1_MODE 1 2 CAP1_PRESCALE 3 8 CAP1_SW 12 1 CAP_CH2 MCPWM_CAP_CH2 0x104 32 read-write n 0x0 0x0 CAP2_VALUE 0 32 CAP_CH2_CFG MCPWM_CAP_CH2_CFG 0xF8 32 read-write n 0x0 0x0 CAP2_EN 0 1 CAP2_IN_INVERT 11 1 CAP2_MODE 1 2 CAP2_PRESCALE 3 8 CAP2_SW 12 1 CAP_STATUS MCPWM_CAP_STATUS 0x108 32 read-write n 0x0 0x0 CAP0_EDGE 0 1 CAP1_EDGE 1 1 CAP2_EDGE 2 1 CAP_TIMER_CFG MCPWM_CAP_TIMER_CFG 0xE8 32 read-write n 0x0 0x0 CAP_SYNCI_EN 1 1 CAP_SYNCI_SEL 2 3 CAP_SYNC_SW 5 1 CAP_TIMER_EN 0 1 CAP_TIMER_PHASE MCPWM_CAP_TIMER_PHASE 0xEC 32 read-write n 0x0 0x0 CAP_PHASE 0 32 CARRIER0_CFG MCPWM_CARRIER0_CFG 0x64 32 read-write n 0x0 0x0 CARRIER0_DUTY 5 3 CARRIER0_EN 0 1 CARRIER0_IN_INVERT 13 1 CARRIER0_OSHWTH 8 4 CARRIER0_OUT_INVERT 12 1 CARRIER0_PRESCALE 1 4 CARRIER1_CFG MCPWM_CARRIER1_CFG 0x9C 32 read-write n 0x0 0x0 CARRIER1_DUTY 5 3 CARRIER1_EN 0 1 CARRIER1_IN_INVERT 13 1 CARRIER1_OSHWTH 8 4 CARRIER1_OUT_INVERT 12 1 CARRIER1_PRESCALE 1 4 CARRIER2_CFG MCPWM_CARRIER2_CFG 0xD4 32 read-write n 0x0 0x0 CARRIER2_DUTY 5 3 CARRIER2_EN 0 1 CARRIER2_IN_INVERT 13 1 CARRIER2_OSHWTH 8 4 CARRIER2_OUT_INVERT 12 1 CARRIER2_PRESCALE 1 4 CLK MCPWM_CLK 0x120 32 read-write n 0x0 0x0 CLK_EN 0 1 CLK_CFG MCPWM_CLK_CFG 0x0 32 read-write n 0x0 0x0 CLK_PRESCALE 0 8 DT0_CFG MCPWM_DT0_CFG 0x58 32 read-write n 0x0 0x0 DT0_A_OUTBYPASS 15 1 DT0_A_OUTSWAP 9 1 DT0_B_OUTBYPASS 16 1 DT0_B_OUTSWAP 10 1 DT0_CLK_SEL 17 1 DT0_DEB_MODE 8 1 DT0_FED_INSEL 12 1 DT0_FED_OUTINVERT 14 1 DT0_FED_UPMETHOD 0 4 DT0_RED_INSEL 11 1 DT0_RED_OUTINVERT 13 1 DT0_RED_UPMETHOD 4 4 DT0_FED_CFG MCPWM_DT0_FED_CFG 0x5C 32 read-write n 0x0 0x0 DT0_FED 0 16 DT0_RED_CFG MCPWM_DT0_RED_CFG 0x60 32 read-write n 0x0 0x0 DT0_RED 0 16 DT1_CFG MCPWM_DT1_CFG 0x90 32 read-write n 0x0 0x0 DT1_A_OUTBYPASS 15 1 DT1_A_OUTSWAP 9 1 DT1_B_OUTBYPASS 16 1 DT1_B_OUTSWAP 10 1 DT1_CLK_SEL 17 1 DT1_DEB_MODE 8 1 DT1_FED_INSEL 12 1 DT1_FED_OUTINVERT 14 1 DT1_FED_UPMETHOD 0 4 DT1_RED_INSEL 11 1 DT1_RED_OUTINVERT 13 1 DT1_RED_UPMETHOD 4 4 DT1_FED_CFG MCPWM_DT1_FED_CFG 0x94 32 read-write n 0x0 0x0 DT1_FED 0 16 DT1_RED_CFG MCPWM_DT1_RED_CFG 0x98 32 read-write n 0x0 0x0 DT1_RED 0 16 DT2_CFG MCPWM_DT2_CFG 0xC8 32 read-write n 0x0 0x0 DT2_A_OUTBYPASS 15 1 DT2_A_OUTSWAP 9 1 DT2_B_OUTBYPASS 16 1 DT2_B_OUTSWAP 10 1 DT2_CLK_SEL 17 1 DT2_DEB_MODE 8 1 DT2_FED_INSEL 12 1 DT2_FED_OUTINVERT 14 1 DT2_FED_UPMETHOD 0 4 DT2_RED_INSEL 11 1 DT2_RED_OUTINVERT 13 1 DT2_RED_UPMETHOD 4 4 DT2_FED_CFG MCPWM_DT2_FED_CFG 0xCC 32 read-write n 0x0 0x0 DT2_FED 0 16 DT2_RED_CFG MCPWM_DT2_RED_CFG 0xD0 32 read-write n 0x0 0x0 DT2_RED 0 16 FAULT_DETECT MCPWM_FAULT_DETECT 0xE4 32 read-write n 0x0 0x0 EVENT_F0 6 1 EVENT_F1 7 1 EVENT_F2 8 1 F0_EN 0 1 F0_POLE 3 1 F1_EN 1 1 F1_POLE 4 1 F2_EN 2 1 F2_POLE 5 1 FH0_CFG0 MCPWM_FH0_CFG0 0x68 32 read-write n 0x0 0x0 FH0_A_CBC_D 8 2 FH0_A_CBC_U 10 2 FH0_A_OST_D 12 2 FH0_A_OST_U 14 2 FH0_B_CBC_D 16 2 FH0_B_CBC_U 18 2 FH0_B_OST_D 20 2 FH0_B_OST_U 22 2 FH0_F0_CBC 3 1 FH0_F0_OST 7 1 FH0_F1_CBC 2 1 FH0_F1_OST 6 1 FH0_F2_CBC 1 1 FH0_F2_OST 5 1 FH0_SW_CBC 0 1 FH0_SW_OST 4 1 FH0_CFG1 MCPWM_FH0_CFG1 0x6C 32 read-write n 0x0 0x0 FH0_CBCPULSE 1 2 FH0_CLR_OST 0 1 FH0_FORCE_CBC 3 1 FH0_FORCE_OST 4 1 FH0_STATUS MCPWM_FH0_STATUS 0x70 32 read-write n 0x0 0x0 FH0_CBC_ON 0 1 FH0_OST_ON 1 1 FH1_CFG0 MCPWM_FH1_CFG0 0xA0 32 read-write n 0x0 0x0 FH1_A_CBC_D 8 2 FH1_A_CBC_U 10 2 FH1_A_OST_D 12 2 FH1_A_OST_U 14 2 FH1_B_CBC_D 16 2 FH1_B_CBC_U 18 2 FH1_B_OST_D 20 2 FH1_B_OST_U 22 2 FH1_F0_CBC 3 1 FH1_F0_OST 7 1 FH1_F1_CBC 2 1 FH1_F1_OST 6 1 FH1_F2_CBC 1 1 FH1_F2_OST 5 1 FH1_SW_CBC 0 1 FH1_SW_OST 4 1 FH1_CFG1 MCPWM_FH1_CFG1 0xA4 32 read-write n 0x0 0x0 FH1_CBCPULSE 1 2 FH1_CLR_OST 0 1 FH1_FORCE_CBC 3 1 FH1_FORCE_OST 4 1 FH1_STATUS MCPWM_FH1_STATUS 0xA8 32 read-write n 0x0 0x0 FH1_CBC_ON 0 1 FH1_OST_ON 1 1 FH2_CFG0 MCPWM_FH2_CFG0 0xD8 32 read-write n 0x0 0x0 FH2_A_CBC_D 8 2 FH2_A_CBC_U 10 2 FH2_A_OST_D 12 2 FH2_A_OST_U 14 2 FH2_B_CBC_D 16 2 FH2_B_CBC_U 18 2 FH2_B_OST_D 20 2 FH2_B_OST_U 22 2 FH2_F0_CBC 3 1 FH2_F0_OST 7 1 FH2_F1_CBC 2 1 FH2_F1_OST 6 1 FH2_F2_CBC 1 1 FH2_F2_OST 5 1 FH2_SW_CBC 0 1 FH2_SW_OST 4 1 FH2_CFG1 MCPWM_FH2_CFG1 0xDC 32 read-write n 0x0 0x0 FH2_CBCPULSE 1 2 FH2_CLR_OST 0 1 FH2_FORCE_CBC 3 1 FH2_FORCE_OST 4 1 FH2_STATUS MCPWM_FH2_STATUS 0xE0 32 read-write n 0x0 0x0 FH2_CBC_ON 0 1 FH2_OST_ON 1 1 GEN0_A MCPWM_GEN0_A 0x50 32 read-write n 0x0 0x0 GEN0_A_DT0 20 2 GEN0_A_DT1 22 2 GEN0_A_DTEA 16 2 GEN0_A_DTEB 18 2 GEN0_A_DTEP 14 2 GEN0_A_DTEZ 12 2 GEN0_A_UT0 8 2 GEN0_A_UT1 10 2 GEN0_A_UTEA 4 2 GEN0_A_UTEB 6 2 GEN0_A_UTEP 2 2 GEN0_A_UTEZ 0 2 GEN0_B MCPWM_GEN0_B 0x54 32 read-write n 0x0 0x0 GEN0_B_DT0 20 2 GEN0_B_DT1 22 2 GEN0_B_DTEA 16 2 GEN0_B_DTEB 18 2 GEN0_B_DTEP 14 2 GEN0_B_DTEZ 12 2 GEN0_B_UT0 8 2 GEN0_B_UT1 10 2 GEN0_B_UTEA 4 2 GEN0_B_UTEB 6 2 GEN0_B_UTEP 2 2 GEN0_B_UTEZ 0 2 GEN0_CFG0 MCPWM_GEN0_CFG0 0x48 32 read-write n 0x0 0x0 GEN0_CFG_UPMETHOD 0 4 GEN0_T0_SEL 4 3 GEN0_T1_SEL 7 3 GEN0_FORCE MCPWM_GEN0_FORCE 0x4C 32 read-write n 0x0 0x0 GEN0_A_CNTUFORCE_MODE 6 2 GEN0_A_NCIFORCE 10 1 GEN0_A_NCIFORCE_MODE 11 2 GEN0_B_CNTUFORCE_MODE 8 2 GEN0_B_NCIFORCE 13 1 GEN0_B_NCIFORCE_MODE 14 2 GEN0_CNTUFORCE_UPMETHOD 0 6 GEN0_STMP_CFG MCPWM_GEN0_STMP_CFG 0x3C 32 read-write n 0x0 0x0 GEN0_A_SHDW_FULL 8 1 GEN0_A_UPMETHOD 0 4 GEN0_B_SHDW_FULL 9 1 GEN0_B_UPMETHOD 4 4 GEN0_TSTMP_A MCPWM_GEN0_TSTMP_A 0x40 32 read-write n 0x0 0x0 GEN0_A 0 16 GEN0_TSTMP_B MCPWM_GEN0_TSTMP_B 0x44 32 read-write n 0x0 0x0 GEN0_B 0 16 GEN1_A MCPWM_GEN1_A 0x88 32 read-write n 0x0 0x0 GEN1_A_DT0 20 2 GEN1_A_DT1 22 2 GEN1_A_DTEA 16 2 GEN1_A_DTEB 18 2 GEN1_A_DTEP 14 2 GEN1_A_DTEZ 12 2 GEN1_A_UT0 8 2 GEN1_A_UT1 10 2 GEN1_A_UTEA 4 2 GEN1_A_UTEB 6 2 GEN1_A_UTEP 2 2 GEN1_A_UTEZ 0 2 GEN1_B MCPWM_GEN1_B 0x8C 32 read-write n 0x0 0x0 GEN1_B_DT0 20 2 GEN1_B_DT1 22 2 GEN1_B_DTEA 16 2 GEN1_B_DTEB 18 2 GEN1_B_DTEP 14 2 GEN1_B_DTEZ 12 2 GEN1_B_UT0 8 2 GEN1_B_UT1 10 2 GEN1_B_UTEA 4 2 GEN1_B_UTEB 6 2 GEN1_B_UTEP 2 2 GEN1_B_UTEZ 0 2 GEN1_CFG0 MCPWM_GEN1_CFG0 0x80 32 read-write n 0x0 0x0 GEN1_CFG_UPMETHOD 0 4 GEN1_T0_SEL 4 3 GEN1_T1_SEL 7 3 GEN1_FORCE MCPWM_GEN1_FORCE 0x84 32 read-write n 0x0 0x0 GEN1_A_CNTUFORCE_MODE 6 2 GEN1_A_NCIFORCE 10 1 GEN1_A_NCIFORCE_MODE 11 2 GEN1_B_CNTUFORCE_MODE 8 2 GEN1_B_NCIFORCE 13 1 GEN1_B_NCIFORCE_MODE 14 2 GEN1_CNTUFORCE_UPMETHOD 0 6 GEN1_STMP_CFG MCPWM_GEN1_STMP_CFG 0x74 32 read-write n 0x0 0x0 GEN1_A_SHDW_FULL 8 1 GEN1_A_UPMETHOD 0 4 GEN1_B_SHDW_FULL 9 1 GEN1_B_UPMETHOD 4 4 GEN1_TSTMP_A MCPWM_GEN1_TSTMP_A 0x78 32 read-write n 0x0 0x0 GEN1_A 0 16 GEN1_TSTMP_B MCPWM_GEN1_TSTMP_B 0x7C 32 read-write n 0x0 0x0 GEN1_B 0 16 GEN2_A MCPWM_GEN2_A 0xC0 32 read-write n 0x0 0x0 GEN2_A_DT0 20 2 GEN2_A_DT1 22 2 GEN2_A_DTEA 16 2 GEN2_A_DTEB 18 2 GEN2_A_DTEP 14 2 GEN2_A_DTEZ 12 2 GEN2_A_UT0 8 2 GEN2_A_UT1 10 2 GEN2_A_UTEA 4 2 GEN2_A_UTEB 6 2 GEN2_A_UTEP 2 2 GEN2_A_UTEZ 0 2 GEN2_B MCPWM_GEN2_B 0xC4 32 read-write n 0x0 0x0 GEN2_B_DT0 20 2 GEN2_B_DT1 22 2 GEN2_B_DTEA 16 2 GEN2_B_DTEB 18 2 GEN2_B_DTEP 14 2 GEN2_B_DTEZ 12 2 GEN2_B_UT0 8 2 GEN2_B_UT1 10 2 GEN2_B_UTEA 4 2 GEN2_B_UTEB 6 2 GEN2_B_UTEP 2 2 GEN2_B_UTEZ 0 2 GEN2_CFG0 MCPWM_GEN2_CFG0 0xB8 32 read-write n 0x0 0x0 GEN2_CFG_UPMETHOD 0 4 GEN2_T0_SEL 4 3 GEN2_T1_SEL 7 3 GEN2_FORCE MCPWM_GEN2_FORCE 0xBC 32 read-write n 0x0 0x0 GEN2_A_CNTUFORCE_MODE 6 2 GEN2_A_NCIFORCE 10 1 GEN2_A_NCIFORCE_MODE 11 2 GEN2_B_CNTUFORCE_MODE 8 2 GEN2_B_NCIFORCE 13 1 GEN2_B_NCIFORCE_MODE 14 2 GEN2_CNTUFORCE_UPMETHOD 0 6 GEN2_STMP_CFG MCPWM_GEN2_STMP_CFG 0xAC 32 read-write n 0x0 0x0 GEN2_A_SHDW_FULL 8 1 GEN2_A_UPMETHOD 0 4 GEN2_B_SHDW_FULL 9 1 GEN2_B_UPMETHOD 4 4 GEN2_TSTMP_A MCPWM_GEN2_TSTMP_A 0xB0 32 read-write n 0x0 0x0 GEN2_A 0 16 GEN2_TSTMP_B MCPWM_GEN2_TSTMP_B 0xB4 32 read-write n 0x0 0x0 GEN2_B 0 16 MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM 0x11C 32 read-write n 0x0 0x0 CAP0_INT_CLR 27 1 CAP1_INT_CLR 28 1 CAP2_INT_CLR 29 1 FAULT0_CLR_INT_CLR 12 1 FAULT0_INT_CLR 9 1 FAULT1_CLR_INT_CLR 13 1 FAULT1_INT_CLR 10 1 FAULT2_CLR_INT_CLR 14 1 FAULT2_INT_CLR 11 1 FH0_CBC_INT_CLR 21 1 FH0_OST_INT_CLR 24 1 FH1_CBC_INT_CLR 22 1 FH1_OST_INT_CLR 25 1 FH2_CBC_INT_CLR 23 1 FH2_OST_INT_CLR 26 1 OP0_TEA_INT_CLR 15 1 OP0_TEB_INT_CLR 18 1 OP1_TEA_INT_CLR 16 1 OP1_TEB_INT_CLR 19 1 OP2_TEA_INT_CLR 17 1 OP2_TEB_INT_CLR 20 1 TIMER0_STOP_INT_CLR 0 1 TIMER0_TEP_INT_CLR 6 1 TIMER0_TEZ_INT_CLR 3 1 TIMER1_STOP_INT_CLR 1 1 TIMER1_TEP_INT_CLR 7 1 TIMER1_TEZ_INT_CLR 4 1 TIMER2_STOP_INT_CLR 2 1 TIMER2_TEP_INT_CLR 8 1 TIMER2_TEZ_INT_CLR 5 1 MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM 0x110 32 read-write n 0x0 0x0 CAP0_INT_ENA 27 1 CAP1_INT_ENA 28 1 CAP2_INT_ENA 29 1 FAULT0_CLR_INT_ENA 12 1 FAULT0_INT_ENA 9 1 FAULT1_CLR_INT_ENA 13 1 FAULT1_INT_ENA 10 1 FAULT2_CLR_INT_ENA 14 1 FAULT2_INT_ENA 11 1 FH0_CBC_INT_ENA 21 1 FH0_OST_INT_ENA 24 1 FH1_CBC_INT_ENA 22 1 FH1_OST_INT_ENA 25 1 FH2_CBC_INT_ENA 23 1 FH2_OST_INT_ENA 26 1 OP0_TEA_INT_ENA 15 1 OP0_TEB_INT_ENA 18 1 OP1_TEA_INT_ENA 16 1 OP1_TEB_INT_ENA 19 1 OP2_TEA_INT_ENA 17 1 OP2_TEB_INT_ENA 20 1 TIMER0_STOP_INT_ENA 0 1 TIMER0_TEP_INT_ENA 6 1 TIMER0_TEZ_INT_ENA 3 1 TIMER1_STOP_INT_ENA 1 1 TIMER1_TEP_INT_ENA 7 1 TIMER1_TEZ_INT_ENA 4 1 TIMER2_STOP_INT_ENA 2 1 TIMER2_TEP_INT_ENA 8 1 TIMER2_TEZ_INT_ENA 5 1 MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM 0x114 32 read-write n 0x0 0x0 CAP0_INT_RAW 27 1 CAP1_INT_RAW 28 1 CAP2_INT_RAW 29 1 FAULT0_CLR_INT_RAW 12 1 FAULT0_INT_RAW 9 1 FAULT1_CLR_INT_RAW 13 1 FAULT1_INT_RAW 10 1 FAULT2_CLR_INT_RAW 14 1 FAULT2_INT_RAW 11 1 FH0_CBC_INT_RAW 21 1 FH0_OST_INT_RAW 24 1 FH1_CBC_INT_RAW 22 1 FH1_OST_INT_RAW 25 1 FH2_CBC_INT_RAW 23 1 FH2_OST_INT_RAW 26 1 OP0_TEA_INT_RAW 15 1 OP0_TEB_INT_RAW 18 1 OP1_TEA_INT_RAW 16 1 OP1_TEB_INT_RAW 19 1 OP2_TEA_INT_RAW 17 1 OP2_TEB_INT_RAW 20 1 TIMER0_STOP_INT_RAW 0 1 TIMER0_TEP_INT_RAW 6 1 TIMER0_TEZ_INT_RAW 3 1 TIMER1_STOP_INT_RAW 1 1 TIMER1_TEP_INT_RAW 7 1 TIMER1_TEZ_INT_RAW 4 1 TIMER2_STOP_INT_RAW 2 1 TIMER2_TEP_INT_RAW 8 1 TIMER2_TEZ_INT_RAW 5 1 MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM 0x118 32 read-write n 0x0 0x0 CAP0_INT_ST 27 1 CAP1_INT_ST 28 1 CAP2_INT_ST 29 1 FAULT0_CLR_INT_ST 12 1 FAULT0_INT_ST 9 1 FAULT1_CLR_INT_ST 13 1 FAULT1_INT_ST 10 1 FAULT2_CLR_INT_ST 14 1 FAULT2_INT_ST 11 1 FH0_CBC_INT_ST 21 1 FH0_OST_INT_ST 24 1 FH1_CBC_INT_ST 22 1 FH1_OST_INT_ST 25 1 FH2_CBC_INT_ST 23 1 FH2_OST_INT_ST 26 1 OP0_TEA_INT_ST 15 1 OP0_TEB_INT_ST 18 1 OP1_TEA_INT_ST 16 1 OP1_TEB_INT_ST 19 1 OP2_TEA_INT_ST 17 1 OP2_TEB_INT_ST 20 1 TIMER0_STOP_INT_ST 0 1 TIMER0_TEP_INT_ST 6 1 TIMER0_TEZ_INT_ST 3 1 TIMER1_STOP_INT_ST 1 1 TIMER1_TEP_INT_ST 7 1 TIMER1_TEZ_INT_ST 4 1 TIMER2_STOP_INT_ST 2 1 TIMER2_TEP_INT_ST 8 1 TIMER2_TEZ_INT_ST 5 1 OPERATOR_TIMERSEL MCPWM_OPERATOR_TIMERSEL 0x38 32 read-write n 0x0 0x0 OPERATOR0_TIMERSEL 0 2 OPERATOR1_TIMERSEL 2 2 OPERATOR2_TIMERSEL 4 2 TIMER0_CFG0 MCPWM_TIMER0_CFG0 0x4 32 read-write n 0x0 0x0 TIMER0_PERIOD 8 16 TIMER0_PERIOD_UPMETHOD 24 2 TIMER0_PRESCALE 0 8 TIMER0_CFG1 MCPWM_TIMER0_CFG1 0x8 32 read-write n 0x0 0x0 TIMER0_MOD 3 2 TIMER0_START 0 3 TIMER0_STATUS MCPWM_TIMER0_STATUS 0x10 32 read-write n 0x0 0x0 TIMER0_DIRECTION 16 1 TIMER0_VALUE 0 16 TIMER0_SYNC MCPWM_TIMER0_SYNC 0xC 32 read-write n 0x0 0x0 TIMER0_PHASE 4 17 TIMER0_SYNCI_EN 0 1 TIMER0_SYNCO_SEL 2 2 TIMER0_SYNC_SW 1 1 TIMER1_CFG0 MCPWM_TIMER1_CFG0 0x14 32 read-write n 0x0 0x0 TIMER1_PERIOD 8 16 TIMER1_PERIOD_UPMETHOD 24 2 TIMER1_PRESCALE 0 8 TIMER1_CFG1 MCPWM_TIMER1_CFG1 0x18 32 read-write n 0x0 0x0 TIMER1_MOD 3 2 TIMER1_START 0 3 TIMER1_STATUS MCPWM_TIMER1_STATUS 0x20 32 read-write n 0x0 0x0 TIMER1_DIRECTION 16 1 TIMER1_VALUE 0 16 TIMER1_SYNC MCPWM_TIMER1_SYNC 0x1C 32 read-write n 0x0 0x0 TIMER1_PHASE 4 17 TIMER1_SYNCI_EN 0 1 TIMER1_SYNCO_SEL 2 2 TIMER1_SYNC_SW 1 1 TIMER2_CFG0 MCPWM_TIMER2_CFG0 0x24 32 read-write n 0x0 0x0 TIMER2_PERIOD 8 16 TIMER2_PERIOD_UPMETHOD 24 2 TIMER2_PRESCALE 0 8 TIMER2_CFG1 MCPWM_TIMER2_CFG1 0x28 32 read-write n 0x0 0x0 TIMER2_MOD 3 2 TIMER2_START 0 3 TIMER2_STATUS MCPWM_TIMER2_STATUS 0x30 32 read-write n 0x0 0x0 TIMER2_DIRECTION 16 1 TIMER2_VALUE 0 16 TIMER2_SYNC MCPWM_TIMER2_SYNC 0x2C 32 read-write n 0x0 0x0 TIMER2_PHASE 4 17 TIMER2_SYNCI_EN 0 1 TIMER2_SYNCO_SEL 2 2 TIMER2_SYNC_SW 1 1 TIMER_SYNCI_CFG MCPWM_TIMER_SYNCI_CFG 0x34 32 read-write n 0x0 0x0 EXTERNAL_SYNCI0_INVERT 9 1 EXTERNAL_SYNCI1_INVERT 10 1 EXTERNAL_SYNCI2_INVERT 11 1 TIMER0_SYNCISEL 0 3 TIMER1_SYNCISEL 3 3 TIMER2_SYNCISEL 6 3 UPDATE_CFG MCPWM_UPDATE_CFG 0x10C 32 read-write n 0x0 0x0 GLOBAL_FORCE_UP 1 1 GLOBAL_UP_EN 0 1 OP0_FORCE_UP 3 1 OP0_UP_EN 2 1 OP1_FORCE_UP 5 1 OP1_UP_EN 4 1 OP2_FORCE_UP 7 1 OP2_UP_EN 6 1 VERSION MCPWM_VERSION 0x124 32 read-write n 0x0 0x0 DATE 0 28 PWM2 MCPWM 0x0 0x0 0x940 registers n CAP_CH0 MCPWM_CAP_CH0 0xFC 32 read-write n 0x0 0x0 CAP0_VALUE 0 32 CAP_CH0_CFG MCPWM_CAP_CH0_CFG 0xF0 32 read-write n 0x0 0x0 CAP0_EN 0 1 CAP0_IN_INVERT 11 1 CAP0_MODE 1 2 CAP0_PRESCALE 3 8 CAP0_SW 12 1 CAP_CH1 MCPWM_CAP_CH1 0x100 32 read-write n 0x0 0x0 CAP1_VALUE 0 32 CAP_CH1_CFG MCPWM_CAP_CH1_CFG 0xF4 32 read-write n 0x0 0x0 CAP1_EN 0 1 CAP1_IN_INVERT 11 1 CAP1_MODE 1 2 CAP1_PRESCALE 3 8 CAP1_SW 12 1 CAP_CH2 MCPWM_CAP_CH2 0x104 32 read-write n 0x0 0x0 CAP2_VALUE 0 32 CAP_CH2_CFG MCPWM_CAP_CH2_CFG 0xF8 32 read-write n 0x0 0x0 CAP2_EN 0 1 CAP2_IN_INVERT 11 1 CAP2_MODE 1 2 CAP2_PRESCALE 3 8 CAP2_SW 12 1 CAP_STATUS MCPWM_CAP_STATUS 0x108 32 read-write n 0x0 0x0 CAP0_EDGE 0 1 CAP1_EDGE 1 1 CAP2_EDGE 2 1 CAP_TIMER_CFG MCPWM_CAP_TIMER_CFG 0xE8 32 read-write n 0x0 0x0 CAP_SYNCI_EN 1 1 CAP_SYNCI_SEL 2 3 CAP_SYNC_SW 5 1 CAP_TIMER_EN 0 1 CAP_TIMER_PHASE MCPWM_CAP_TIMER_PHASE 0xEC 32 read-write n 0x0 0x0 CAP_PHASE 0 32 CARRIER0_CFG MCPWM_CARRIER0_CFG 0x64 32 read-write n 0x0 0x0 CARRIER0_DUTY 5 3 CARRIER0_EN 0 1 CARRIER0_IN_INVERT 13 1 CARRIER0_OSHWTH 8 4 CARRIER0_OUT_INVERT 12 1 CARRIER0_PRESCALE 1 4 CARRIER1_CFG MCPWM_CARRIER1_CFG 0x9C 32 read-write n 0x0 0x0 CARRIER1_DUTY 5 3 CARRIER1_EN 0 1 CARRIER1_IN_INVERT 13 1 CARRIER1_OSHWTH 8 4 CARRIER1_OUT_INVERT 12 1 CARRIER1_PRESCALE 1 4 CARRIER2_CFG MCPWM_CARRIER2_CFG 0xD4 32 read-write n 0x0 0x0 CARRIER2_DUTY 5 3 CARRIER2_EN 0 1 CARRIER2_IN_INVERT 13 1 CARRIER2_OSHWTH 8 4 CARRIER2_OUT_INVERT 12 1 CARRIER2_PRESCALE 1 4 CLK MCPWM_CLK 0x120 32 read-write n 0x0 0x0 CLK_EN 0 1 CLK_CFG MCPWM_CLK_CFG 0x0 32 read-write n 0x0 0x0 CLK_PRESCALE 0 8 DT0_CFG MCPWM_DT0_CFG 0x58 32 read-write n 0x0 0x0 DT0_A_OUTBYPASS 15 1 DT0_A_OUTSWAP 9 1 DT0_B_OUTBYPASS 16 1 DT0_B_OUTSWAP 10 1 DT0_CLK_SEL 17 1 DT0_DEB_MODE 8 1 DT0_FED_INSEL 12 1 DT0_FED_OUTINVERT 14 1 DT0_FED_UPMETHOD 0 4 DT0_RED_INSEL 11 1 DT0_RED_OUTINVERT 13 1 DT0_RED_UPMETHOD 4 4 DT0_FED_CFG MCPWM_DT0_FED_CFG 0x5C 32 read-write n 0x0 0x0 DT0_FED 0 16 DT0_RED_CFG MCPWM_DT0_RED_CFG 0x60 32 read-write n 0x0 0x0 DT0_RED 0 16 DT1_CFG MCPWM_DT1_CFG 0x90 32 read-write n 0x0 0x0 DT1_A_OUTBYPASS 15 1 DT1_A_OUTSWAP 9 1 DT1_B_OUTBYPASS 16 1 DT1_B_OUTSWAP 10 1 DT1_CLK_SEL 17 1 DT1_DEB_MODE 8 1 DT1_FED_INSEL 12 1 DT1_FED_OUTINVERT 14 1 DT1_FED_UPMETHOD 0 4 DT1_RED_INSEL 11 1 DT1_RED_OUTINVERT 13 1 DT1_RED_UPMETHOD 4 4 DT1_FED_CFG MCPWM_DT1_FED_CFG 0x94 32 read-write n 0x0 0x0 DT1_FED 0 16 DT1_RED_CFG MCPWM_DT1_RED_CFG 0x98 32 read-write n 0x0 0x0 DT1_RED 0 16 DT2_CFG MCPWM_DT2_CFG 0xC8 32 read-write n 0x0 0x0 DT2_A_OUTBYPASS 15 1 DT2_A_OUTSWAP 9 1 DT2_B_OUTBYPASS 16 1 DT2_B_OUTSWAP 10 1 DT2_CLK_SEL 17 1 DT2_DEB_MODE 8 1 DT2_FED_INSEL 12 1 DT2_FED_OUTINVERT 14 1 DT2_FED_UPMETHOD 0 4 DT2_RED_INSEL 11 1 DT2_RED_OUTINVERT 13 1 DT2_RED_UPMETHOD 4 4 DT2_FED_CFG MCPWM_DT2_FED_CFG 0xCC 32 read-write n 0x0 0x0 DT2_FED 0 16 DT2_RED_CFG MCPWM_DT2_RED_CFG 0xD0 32 read-write n 0x0 0x0 DT2_RED 0 16 FAULT_DETECT MCPWM_FAULT_DETECT 0xE4 32 read-write n 0x0 0x0 EVENT_F0 6 1 EVENT_F1 7 1 EVENT_F2 8 1 F0_EN 0 1 F0_POLE 3 1 F1_EN 1 1 F1_POLE 4 1 F2_EN 2 1 F2_POLE 5 1 FH0_CFG0 MCPWM_FH0_CFG0 0x68 32 read-write n 0x0 0x0 FH0_A_CBC_D 8 2 FH0_A_CBC_U 10 2 FH0_A_OST_D 12 2 FH0_A_OST_U 14 2 FH0_B_CBC_D 16 2 FH0_B_CBC_U 18 2 FH0_B_OST_D 20 2 FH0_B_OST_U 22 2 FH0_F0_CBC 3 1 FH0_F0_OST 7 1 FH0_F1_CBC 2 1 FH0_F1_OST 6 1 FH0_F2_CBC 1 1 FH0_F2_OST 5 1 FH0_SW_CBC 0 1 FH0_SW_OST 4 1 FH0_CFG1 MCPWM_FH0_CFG1 0x6C 32 read-write n 0x0 0x0 FH0_CBCPULSE 1 2 FH0_CLR_OST 0 1 FH0_FORCE_CBC 3 1 FH0_FORCE_OST 4 1 FH0_STATUS MCPWM_FH0_STATUS 0x70 32 read-write n 0x0 0x0 FH0_CBC_ON 0 1 FH0_OST_ON 1 1 FH1_CFG0 MCPWM_FH1_CFG0 0xA0 32 read-write n 0x0 0x0 FH1_A_CBC_D 8 2 FH1_A_CBC_U 10 2 FH1_A_OST_D 12 2 FH1_A_OST_U 14 2 FH1_B_CBC_D 16 2 FH1_B_CBC_U 18 2 FH1_B_OST_D 20 2 FH1_B_OST_U 22 2 FH1_F0_CBC 3 1 FH1_F0_OST 7 1 FH1_F1_CBC 2 1 FH1_F1_OST 6 1 FH1_F2_CBC 1 1 FH1_F2_OST 5 1 FH1_SW_CBC 0 1 FH1_SW_OST 4 1 FH1_CFG1 MCPWM_FH1_CFG1 0xA4 32 read-write n 0x0 0x0 FH1_CBCPULSE 1 2 FH1_CLR_OST 0 1 FH1_FORCE_CBC 3 1 FH1_FORCE_OST 4 1 FH1_STATUS MCPWM_FH1_STATUS 0xA8 32 read-write n 0x0 0x0 FH1_CBC_ON 0 1 FH1_OST_ON 1 1 FH2_CFG0 MCPWM_FH2_CFG0 0xD8 32 read-write n 0x0 0x0 FH2_A_CBC_D 8 2 FH2_A_CBC_U 10 2 FH2_A_OST_D 12 2 FH2_A_OST_U 14 2 FH2_B_CBC_D 16 2 FH2_B_CBC_U 18 2 FH2_B_OST_D 20 2 FH2_B_OST_U 22 2 FH2_F0_CBC 3 1 FH2_F0_OST 7 1 FH2_F1_CBC 2 1 FH2_F1_OST 6 1 FH2_F2_CBC 1 1 FH2_F2_OST 5 1 FH2_SW_CBC 0 1 FH2_SW_OST 4 1 FH2_CFG1 MCPWM_FH2_CFG1 0xDC 32 read-write n 0x0 0x0 FH2_CBCPULSE 1 2 FH2_CLR_OST 0 1 FH2_FORCE_CBC 3 1 FH2_FORCE_OST 4 1 FH2_STATUS MCPWM_FH2_STATUS 0xE0 32 read-write n 0x0 0x0 FH2_CBC_ON 0 1 FH2_OST_ON 1 1 GEN0_A MCPWM_GEN0_A 0x50 32 read-write n 0x0 0x0 GEN0_A_DT0 20 2 GEN0_A_DT1 22 2 GEN0_A_DTEA 16 2 GEN0_A_DTEB 18 2 GEN0_A_DTEP 14 2 GEN0_A_DTEZ 12 2 GEN0_A_UT0 8 2 GEN0_A_UT1 10 2 GEN0_A_UTEA 4 2 GEN0_A_UTEB 6 2 GEN0_A_UTEP 2 2 GEN0_A_UTEZ 0 2 GEN0_B MCPWM_GEN0_B 0x54 32 read-write n 0x0 0x0 GEN0_B_DT0 20 2 GEN0_B_DT1 22 2 GEN0_B_DTEA 16 2 GEN0_B_DTEB 18 2 GEN0_B_DTEP 14 2 GEN0_B_DTEZ 12 2 GEN0_B_UT0 8 2 GEN0_B_UT1 10 2 GEN0_B_UTEA 4 2 GEN0_B_UTEB 6 2 GEN0_B_UTEP 2 2 GEN0_B_UTEZ 0 2 GEN0_CFG0 MCPWM_GEN0_CFG0 0x48 32 read-write n 0x0 0x0 GEN0_CFG_UPMETHOD 0 4 GEN0_T0_SEL 4 3 GEN0_T1_SEL 7 3 GEN0_FORCE MCPWM_GEN0_FORCE 0x4C 32 read-write n 0x0 0x0 GEN0_A_CNTUFORCE_MODE 6 2 GEN0_A_NCIFORCE 10 1 GEN0_A_NCIFORCE_MODE 11 2 GEN0_B_CNTUFORCE_MODE 8 2 GEN0_B_NCIFORCE 13 1 GEN0_B_NCIFORCE_MODE 14 2 GEN0_CNTUFORCE_UPMETHOD 0 6 GEN0_STMP_CFG MCPWM_GEN0_STMP_CFG 0x3C 32 read-write n 0x0 0x0 GEN0_A_SHDW_FULL 8 1 GEN0_A_UPMETHOD 0 4 GEN0_B_SHDW_FULL 9 1 GEN0_B_UPMETHOD 4 4 GEN0_TSTMP_A MCPWM_GEN0_TSTMP_A 0x40 32 read-write n 0x0 0x0 GEN0_A 0 16 GEN0_TSTMP_B MCPWM_GEN0_TSTMP_B 0x44 32 read-write n 0x0 0x0 GEN0_B 0 16 GEN1_A MCPWM_GEN1_A 0x88 32 read-write n 0x0 0x0 GEN1_A_DT0 20 2 GEN1_A_DT1 22 2 GEN1_A_DTEA 16 2 GEN1_A_DTEB 18 2 GEN1_A_DTEP 14 2 GEN1_A_DTEZ 12 2 GEN1_A_UT0 8 2 GEN1_A_UT1 10 2 GEN1_A_UTEA 4 2 GEN1_A_UTEB 6 2 GEN1_A_UTEP 2 2 GEN1_A_UTEZ 0 2 GEN1_B MCPWM_GEN1_B 0x8C 32 read-write n 0x0 0x0 GEN1_B_DT0 20 2 GEN1_B_DT1 22 2 GEN1_B_DTEA 16 2 GEN1_B_DTEB 18 2 GEN1_B_DTEP 14 2 GEN1_B_DTEZ 12 2 GEN1_B_UT0 8 2 GEN1_B_UT1 10 2 GEN1_B_UTEA 4 2 GEN1_B_UTEB 6 2 GEN1_B_UTEP 2 2 GEN1_B_UTEZ 0 2 GEN1_CFG0 MCPWM_GEN1_CFG0 0x80 32 read-write n 0x0 0x0 GEN1_CFG_UPMETHOD 0 4 GEN1_T0_SEL 4 3 GEN1_T1_SEL 7 3 GEN1_FORCE MCPWM_GEN1_FORCE 0x84 32 read-write n 0x0 0x0 GEN1_A_CNTUFORCE_MODE 6 2 GEN1_A_NCIFORCE 10 1 GEN1_A_NCIFORCE_MODE 11 2 GEN1_B_CNTUFORCE_MODE 8 2 GEN1_B_NCIFORCE 13 1 GEN1_B_NCIFORCE_MODE 14 2 GEN1_CNTUFORCE_UPMETHOD 0 6 GEN1_STMP_CFG MCPWM_GEN1_STMP_CFG 0x74 32 read-write n 0x0 0x0 GEN1_A_SHDW_FULL 8 1 GEN1_A_UPMETHOD 0 4 GEN1_B_SHDW_FULL 9 1 GEN1_B_UPMETHOD 4 4 GEN1_TSTMP_A MCPWM_GEN1_TSTMP_A 0x78 32 read-write n 0x0 0x0 GEN1_A 0 16 GEN1_TSTMP_B MCPWM_GEN1_TSTMP_B 0x7C 32 read-write n 0x0 0x0 GEN1_B 0 16 GEN2_A MCPWM_GEN2_A 0xC0 32 read-write n 0x0 0x0 GEN2_A_DT0 20 2 GEN2_A_DT1 22 2 GEN2_A_DTEA 16 2 GEN2_A_DTEB 18 2 GEN2_A_DTEP 14 2 GEN2_A_DTEZ 12 2 GEN2_A_UT0 8 2 GEN2_A_UT1 10 2 GEN2_A_UTEA 4 2 GEN2_A_UTEB 6 2 GEN2_A_UTEP 2 2 GEN2_A_UTEZ 0 2 GEN2_B MCPWM_GEN2_B 0xC4 32 read-write n 0x0 0x0 GEN2_B_DT0 20 2 GEN2_B_DT1 22 2 GEN2_B_DTEA 16 2 GEN2_B_DTEB 18 2 GEN2_B_DTEP 14 2 GEN2_B_DTEZ 12 2 GEN2_B_UT0 8 2 GEN2_B_UT1 10 2 GEN2_B_UTEA 4 2 GEN2_B_UTEB 6 2 GEN2_B_UTEP 2 2 GEN2_B_UTEZ 0 2 GEN2_CFG0 MCPWM_GEN2_CFG0 0xB8 32 read-write n 0x0 0x0 GEN2_CFG_UPMETHOD 0 4 GEN2_T0_SEL 4 3 GEN2_T1_SEL 7 3 GEN2_FORCE MCPWM_GEN2_FORCE 0xBC 32 read-write n 0x0 0x0 GEN2_A_CNTUFORCE_MODE 6 2 GEN2_A_NCIFORCE 10 1 GEN2_A_NCIFORCE_MODE 11 2 GEN2_B_CNTUFORCE_MODE 8 2 GEN2_B_NCIFORCE 13 1 GEN2_B_NCIFORCE_MODE 14 2 GEN2_CNTUFORCE_UPMETHOD 0 6 GEN2_STMP_CFG MCPWM_GEN2_STMP_CFG 0xAC 32 read-write n 0x0 0x0 GEN2_A_SHDW_FULL 8 1 GEN2_A_UPMETHOD 0 4 GEN2_B_SHDW_FULL 9 1 GEN2_B_UPMETHOD 4 4 GEN2_TSTMP_A MCPWM_GEN2_TSTMP_A 0xB0 32 read-write n 0x0 0x0 GEN2_A 0 16 GEN2_TSTMP_B MCPWM_GEN2_TSTMP_B 0xB4 32 read-write n 0x0 0x0 GEN2_B 0 16 MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM 0x11C 32 read-write n 0x0 0x0 CAP0_INT_CLR 27 1 CAP1_INT_CLR 28 1 CAP2_INT_CLR 29 1 FAULT0_CLR_INT_CLR 12 1 FAULT0_INT_CLR 9 1 FAULT1_CLR_INT_CLR 13 1 FAULT1_INT_CLR 10 1 FAULT2_CLR_INT_CLR 14 1 FAULT2_INT_CLR 11 1 FH0_CBC_INT_CLR 21 1 FH0_OST_INT_CLR 24 1 FH1_CBC_INT_CLR 22 1 FH1_OST_INT_CLR 25 1 FH2_CBC_INT_CLR 23 1 FH2_OST_INT_CLR 26 1 OP0_TEA_INT_CLR 15 1 OP0_TEB_INT_CLR 18 1 OP1_TEA_INT_CLR 16 1 OP1_TEB_INT_CLR 19 1 OP2_TEA_INT_CLR 17 1 OP2_TEB_INT_CLR 20 1 TIMER0_STOP_INT_CLR 0 1 TIMER0_TEP_INT_CLR 6 1 TIMER0_TEZ_INT_CLR 3 1 TIMER1_STOP_INT_CLR 1 1 TIMER1_TEP_INT_CLR 7 1 TIMER1_TEZ_INT_CLR 4 1 TIMER2_STOP_INT_CLR 2 1 TIMER2_TEP_INT_CLR 8 1 TIMER2_TEZ_INT_CLR 5 1 MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM 0x110 32 read-write n 0x0 0x0 CAP0_INT_ENA 27 1 CAP1_INT_ENA 28 1 CAP2_INT_ENA 29 1 FAULT0_CLR_INT_ENA 12 1 FAULT0_INT_ENA 9 1 FAULT1_CLR_INT_ENA 13 1 FAULT1_INT_ENA 10 1 FAULT2_CLR_INT_ENA 14 1 FAULT2_INT_ENA 11 1 FH0_CBC_INT_ENA 21 1 FH0_OST_INT_ENA 24 1 FH1_CBC_INT_ENA 22 1 FH1_OST_INT_ENA 25 1 FH2_CBC_INT_ENA 23 1 FH2_OST_INT_ENA 26 1 OP0_TEA_INT_ENA 15 1 OP0_TEB_INT_ENA 18 1 OP1_TEA_INT_ENA 16 1 OP1_TEB_INT_ENA 19 1 OP2_TEA_INT_ENA 17 1 OP2_TEB_INT_ENA 20 1 TIMER0_STOP_INT_ENA 0 1 TIMER0_TEP_INT_ENA 6 1 TIMER0_TEZ_INT_ENA 3 1 TIMER1_STOP_INT_ENA 1 1 TIMER1_TEP_INT_ENA 7 1 TIMER1_TEZ_INT_ENA 4 1 TIMER2_STOP_INT_ENA 2 1 TIMER2_TEP_INT_ENA 8 1 TIMER2_TEZ_INT_ENA 5 1 MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM 0x114 32 read-write n 0x0 0x0 CAP0_INT_RAW 27 1 CAP1_INT_RAW 28 1 CAP2_INT_RAW 29 1 FAULT0_CLR_INT_RAW 12 1 FAULT0_INT_RAW 9 1 FAULT1_CLR_INT_RAW 13 1 FAULT1_INT_RAW 10 1 FAULT2_CLR_INT_RAW 14 1 FAULT2_INT_RAW 11 1 FH0_CBC_INT_RAW 21 1 FH0_OST_INT_RAW 24 1 FH1_CBC_INT_RAW 22 1 FH1_OST_INT_RAW 25 1 FH2_CBC_INT_RAW 23 1 FH2_OST_INT_RAW 26 1 OP0_TEA_INT_RAW 15 1 OP0_TEB_INT_RAW 18 1 OP1_TEA_INT_RAW 16 1 OP1_TEB_INT_RAW 19 1 OP2_TEA_INT_RAW 17 1 OP2_TEB_INT_RAW 20 1 TIMER0_STOP_INT_RAW 0 1 TIMER0_TEP_INT_RAW 6 1 TIMER0_TEZ_INT_RAW 3 1 TIMER1_STOP_INT_RAW 1 1 TIMER1_TEP_INT_RAW 7 1 TIMER1_TEZ_INT_RAW 4 1 TIMER2_STOP_INT_RAW 2 1 TIMER2_TEP_INT_RAW 8 1 TIMER2_TEZ_INT_RAW 5 1 MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM 0x118 32 read-write n 0x0 0x0 CAP0_INT_ST 27 1 CAP1_INT_ST 28 1 CAP2_INT_ST 29 1 FAULT0_CLR_INT_ST 12 1 FAULT0_INT_ST 9 1 FAULT1_CLR_INT_ST 13 1 FAULT1_INT_ST 10 1 FAULT2_CLR_INT_ST 14 1 FAULT2_INT_ST 11 1 FH0_CBC_INT_ST 21 1 FH0_OST_INT_ST 24 1 FH1_CBC_INT_ST 22 1 FH1_OST_INT_ST 25 1 FH2_CBC_INT_ST 23 1 FH2_OST_INT_ST 26 1 OP0_TEA_INT_ST 15 1 OP0_TEB_INT_ST 18 1 OP1_TEA_INT_ST 16 1 OP1_TEB_INT_ST 19 1 OP2_TEA_INT_ST 17 1 OP2_TEB_INT_ST 20 1 TIMER0_STOP_INT_ST 0 1 TIMER0_TEP_INT_ST 6 1 TIMER0_TEZ_INT_ST 3 1 TIMER1_STOP_INT_ST 1 1 TIMER1_TEP_INT_ST 7 1 TIMER1_TEZ_INT_ST 4 1 TIMER2_STOP_INT_ST 2 1 TIMER2_TEP_INT_ST 8 1 TIMER2_TEZ_INT_ST 5 1 OPERATOR_TIMERSEL MCPWM_OPERATOR_TIMERSEL 0x38 32 read-write n 0x0 0x0 OPERATOR0_TIMERSEL 0 2 OPERATOR1_TIMERSEL 2 2 OPERATOR2_TIMERSEL 4 2 TIMER0_CFG0 MCPWM_TIMER0_CFG0 0x4 32 read-write n 0x0 0x0 TIMER0_PERIOD 8 16 TIMER0_PERIOD_UPMETHOD 24 2 TIMER0_PRESCALE 0 8 TIMER0_CFG1 MCPWM_TIMER0_CFG1 0x8 32 read-write n 0x0 0x0 TIMER0_MOD 3 2 TIMER0_START 0 3 TIMER0_STATUS MCPWM_TIMER0_STATUS 0x10 32 read-write n 0x0 0x0 TIMER0_DIRECTION 16 1 TIMER0_VALUE 0 16 TIMER0_SYNC MCPWM_TIMER0_SYNC 0xC 32 read-write n 0x0 0x0 TIMER0_PHASE 4 17 TIMER0_SYNCI_EN 0 1 TIMER0_SYNCO_SEL 2 2 TIMER0_SYNC_SW 1 1 TIMER1_CFG0 MCPWM_TIMER1_CFG0 0x14 32 read-write n 0x0 0x0 TIMER1_PERIOD 8 16 TIMER1_PERIOD_UPMETHOD 24 2 TIMER1_PRESCALE 0 8 TIMER1_CFG1 MCPWM_TIMER1_CFG1 0x18 32 read-write n 0x0 0x0 TIMER1_MOD 3 2 TIMER1_START 0 3 TIMER1_STATUS MCPWM_TIMER1_STATUS 0x20 32 read-write n 0x0 0x0 TIMER1_DIRECTION 16 1 TIMER1_VALUE 0 16 TIMER1_SYNC MCPWM_TIMER1_SYNC 0x1C 32 read-write n 0x0 0x0 TIMER1_PHASE 4 17 TIMER1_SYNCI_EN 0 1 TIMER1_SYNCO_SEL 2 2 TIMER1_SYNC_SW 1 1 TIMER2_CFG0 MCPWM_TIMER2_CFG0 0x24 32 read-write n 0x0 0x0 TIMER2_PERIOD 8 16 TIMER2_PERIOD_UPMETHOD 24 2 TIMER2_PRESCALE 0 8 TIMER2_CFG1 MCPWM_TIMER2_CFG1 0x28 32 read-write n 0x0 0x0 TIMER2_MOD 3 2 TIMER2_START 0 3 TIMER2_STATUS MCPWM_TIMER2_STATUS 0x30 32 read-write n 0x0 0x0 TIMER2_DIRECTION 16 1 TIMER2_VALUE 0 16 TIMER2_SYNC MCPWM_TIMER2_SYNC 0x2C 32 read-write n 0x0 0x0 TIMER2_PHASE 4 17 TIMER2_SYNCI_EN 0 1 TIMER2_SYNCO_SEL 2 2 TIMER2_SYNC_SW 1 1 TIMER_SYNCI_CFG MCPWM_TIMER_SYNCI_CFG 0x34 32 read-write n 0x0 0x0 EXTERNAL_SYNCI0_INVERT 9 1 EXTERNAL_SYNCI1_INVERT 10 1 EXTERNAL_SYNCI2_INVERT 11 1 TIMER0_SYNCISEL 0 3 TIMER1_SYNCISEL 3 3 TIMER2_SYNCISEL 6 3 UPDATE_CFG MCPWM_UPDATE_CFG 0x10C 32 read-write n 0x0 0x0 GLOBAL_FORCE_UP 1 1 GLOBAL_UP_EN 0 1 OP0_FORCE_UP 3 1 OP0_UP_EN 2 1 OP1_FORCE_UP 5 1 OP1_UP_EN 4 1 OP2_FORCE_UP 7 1 OP2_UP_EN 6 1 VERSION MCPWM_VERSION 0x124 32 read-write n 0x0 0x0 DATE 0 28 PWM3 MCPWM 0x0 0x0 0x940 registers n CAP_CH0 MCPWM_CAP_CH0 0xFC 32 read-write n 0x0 0x0 CAP0_VALUE 0 32 CAP_CH0_CFG MCPWM_CAP_CH0_CFG 0xF0 32 read-write n 0x0 0x0 CAP0_EN 0 1 CAP0_IN_INVERT 11 1 CAP0_MODE 1 2 CAP0_PRESCALE 3 8 CAP0_SW 12 1 CAP_CH1 MCPWM_CAP_CH1 0x100 32 read-write n 0x0 0x0 CAP1_VALUE 0 32 CAP_CH1_CFG MCPWM_CAP_CH1_CFG 0xF4 32 read-write n 0x0 0x0 CAP1_EN 0 1 CAP1_IN_INVERT 11 1 CAP1_MODE 1 2 CAP1_PRESCALE 3 8 CAP1_SW 12 1 CAP_CH2 MCPWM_CAP_CH2 0x104 32 read-write n 0x0 0x0 CAP2_VALUE 0 32 CAP_CH2_CFG MCPWM_CAP_CH2_CFG 0xF8 32 read-write n 0x0 0x0 CAP2_EN 0 1 CAP2_IN_INVERT 11 1 CAP2_MODE 1 2 CAP2_PRESCALE 3 8 CAP2_SW 12 1 CAP_STATUS MCPWM_CAP_STATUS 0x108 32 read-write n 0x0 0x0 CAP0_EDGE 0 1 CAP1_EDGE 1 1 CAP2_EDGE 2 1 CAP_TIMER_CFG MCPWM_CAP_TIMER_CFG 0xE8 32 read-write n 0x0 0x0 CAP_SYNCI_EN 1 1 CAP_SYNCI_SEL 2 3 CAP_SYNC_SW 5 1 CAP_TIMER_EN 0 1 CAP_TIMER_PHASE MCPWM_CAP_TIMER_PHASE 0xEC 32 read-write n 0x0 0x0 CAP_PHASE 0 32 CARRIER0_CFG MCPWM_CARRIER0_CFG 0x64 32 read-write n 0x0 0x0 CARRIER0_DUTY 5 3 CARRIER0_EN 0 1 CARRIER0_IN_INVERT 13 1 CARRIER0_OSHWTH 8 4 CARRIER0_OUT_INVERT 12 1 CARRIER0_PRESCALE 1 4 CARRIER1_CFG MCPWM_CARRIER1_CFG 0x9C 32 read-write n 0x0 0x0 CARRIER1_DUTY 5 3 CARRIER1_EN 0 1 CARRIER1_IN_INVERT 13 1 CARRIER1_OSHWTH 8 4 CARRIER1_OUT_INVERT 12 1 CARRIER1_PRESCALE 1 4 CARRIER2_CFG MCPWM_CARRIER2_CFG 0xD4 32 read-write n 0x0 0x0 CARRIER2_DUTY 5 3 CARRIER2_EN 0 1 CARRIER2_IN_INVERT 13 1 CARRIER2_OSHWTH 8 4 CARRIER2_OUT_INVERT 12 1 CARRIER2_PRESCALE 1 4 CLK MCPWM_CLK 0x120 32 read-write n 0x0 0x0 CLK_EN 0 1 CLK_CFG MCPWM_CLK_CFG 0x0 32 read-write n 0x0 0x0 CLK_PRESCALE 0 8 DT0_CFG MCPWM_DT0_CFG 0x58 32 read-write n 0x0 0x0 DT0_A_OUTBYPASS 15 1 DT0_A_OUTSWAP 9 1 DT0_B_OUTBYPASS 16 1 DT0_B_OUTSWAP 10 1 DT0_CLK_SEL 17 1 DT0_DEB_MODE 8 1 DT0_FED_INSEL 12 1 DT0_FED_OUTINVERT 14 1 DT0_FED_UPMETHOD 0 4 DT0_RED_INSEL 11 1 DT0_RED_OUTINVERT 13 1 DT0_RED_UPMETHOD 4 4 DT0_FED_CFG MCPWM_DT0_FED_CFG 0x5C 32 read-write n 0x0 0x0 DT0_FED 0 16 DT0_RED_CFG MCPWM_DT0_RED_CFG 0x60 32 read-write n 0x0 0x0 DT0_RED 0 16 DT1_CFG MCPWM_DT1_CFG 0x90 32 read-write n 0x0 0x0 DT1_A_OUTBYPASS 15 1 DT1_A_OUTSWAP 9 1 DT1_B_OUTBYPASS 16 1 DT1_B_OUTSWAP 10 1 DT1_CLK_SEL 17 1 DT1_DEB_MODE 8 1 DT1_FED_INSEL 12 1 DT1_FED_OUTINVERT 14 1 DT1_FED_UPMETHOD 0 4 DT1_RED_INSEL 11 1 DT1_RED_OUTINVERT 13 1 DT1_RED_UPMETHOD 4 4 DT1_FED_CFG MCPWM_DT1_FED_CFG 0x94 32 read-write n 0x0 0x0 DT1_FED 0 16 DT1_RED_CFG MCPWM_DT1_RED_CFG 0x98 32 read-write n 0x0 0x0 DT1_RED 0 16 DT2_CFG MCPWM_DT2_CFG 0xC8 32 read-write n 0x0 0x0 DT2_A_OUTBYPASS 15 1 DT2_A_OUTSWAP 9 1 DT2_B_OUTBYPASS 16 1 DT2_B_OUTSWAP 10 1 DT2_CLK_SEL 17 1 DT2_DEB_MODE 8 1 DT2_FED_INSEL 12 1 DT2_FED_OUTINVERT 14 1 DT2_FED_UPMETHOD 0 4 DT2_RED_INSEL 11 1 DT2_RED_OUTINVERT 13 1 DT2_RED_UPMETHOD 4 4 DT2_FED_CFG MCPWM_DT2_FED_CFG 0xCC 32 read-write n 0x0 0x0 DT2_FED 0 16 DT2_RED_CFG MCPWM_DT2_RED_CFG 0xD0 32 read-write n 0x0 0x0 DT2_RED 0 16 FAULT_DETECT MCPWM_FAULT_DETECT 0xE4 32 read-write n 0x0 0x0 EVENT_F0 6 1 EVENT_F1 7 1 EVENT_F2 8 1 F0_EN 0 1 F0_POLE 3 1 F1_EN 1 1 F1_POLE 4 1 F2_EN 2 1 F2_POLE 5 1 FH0_CFG0 MCPWM_FH0_CFG0 0x68 32 read-write n 0x0 0x0 FH0_A_CBC_D 8 2 FH0_A_CBC_U 10 2 FH0_A_OST_D 12 2 FH0_A_OST_U 14 2 FH0_B_CBC_D 16 2 FH0_B_CBC_U 18 2 FH0_B_OST_D 20 2 FH0_B_OST_U 22 2 FH0_F0_CBC 3 1 FH0_F0_OST 7 1 FH0_F1_CBC 2 1 FH0_F1_OST 6 1 FH0_F2_CBC 1 1 FH0_F2_OST 5 1 FH0_SW_CBC 0 1 FH0_SW_OST 4 1 FH0_CFG1 MCPWM_FH0_CFG1 0x6C 32 read-write n 0x0 0x0 FH0_CBCPULSE 1 2 FH0_CLR_OST 0 1 FH0_FORCE_CBC 3 1 FH0_FORCE_OST 4 1 FH0_STATUS MCPWM_FH0_STATUS 0x70 32 read-write n 0x0 0x0 FH0_CBC_ON 0 1 FH0_OST_ON 1 1 FH1_CFG0 MCPWM_FH1_CFG0 0xA0 32 read-write n 0x0 0x0 FH1_A_CBC_D 8 2 FH1_A_CBC_U 10 2 FH1_A_OST_D 12 2 FH1_A_OST_U 14 2 FH1_B_CBC_D 16 2 FH1_B_CBC_U 18 2 FH1_B_OST_D 20 2 FH1_B_OST_U 22 2 FH1_F0_CBC 3 1 FH1_F0_OST 7 1 FH1_F1_CBC 2 1 FH1_F1_OST 6 1 FH1_F2_CBC 1 1 FH1_F2_OST 5 1 FH1_SW_CBC 0 1 FH1_SW_OST 4 1 FH1_CFG1 MCPWM_FH1_CFG1 0xA4 32 read-write n 0x0 0x0 FH1_CBCPULSE 1 2 FH1_CLR_OST 0 1 FH1_FORCE_CBC 3 1 FH1_FORCE_OST 4 1 FH1_STATUS MCPWM_FH1_STATUS 0xA8 32 read-write n 0x0 0x0 FH1_CBC_ON 0 1 FH1_OST_ON 1 1 FH2_CFG0 MCPWM_FH2_CFG0 0xD8 32 read-write n 0x0 0x0 FH2_A_CBC_D 8 2 FH2_A_CBC_U 10 2 FH2_A_OST_D 12 2 FH2_A_OST_U 14 2 FH2_B_CBC_D 16 2 FH2_B_CBC_U 18 2 FH2_B_OST_D 20 2 FH2_B_OST_U 22 2 FH2_F0_CBC 3 1 FH2_F0_OST 7 1 FH2_F1_CBC 2 1 FH2_F1_OST 6 1 FH2_F2_CBC 1 1 FH2_F2_OST 5 1 FH2_SW_CBC 0 1 FH2_SW_OST 4 1 FH2_CFG1 MCPWM_FH2_CFG1 0xDC 32 read-write n 0x0 0x0 FH2_CBCPULSE 1 2 FH2_CLR_OST 0 1 FH2_FORCE_CBC 3 1 FH2_FORCE_OST 4 1 FH2_STATUS MCPWM_FH2_STATUS 0xE0 32 read-write n 0x0 0x0 FH2_CBC_ON 0 1 FH2_OST_ON 1 1 GEN0_A MCPWM_GEN0_A 0x50 32 read-write n 0x0 0x0 GEN0_A_DT0 20 2 GEN0_A_DT1 22 2 GEN0_A_DTEA 16 2 GEN0_A_DTEB 18 2 GEN0_A_DTEP 14 2 GEN0_A_DTEZ 12 2 GEN0_A_UT0 8 2 GEN0_A_UT1 10 2 GEN0_A_UTEA 4 2 GEN0_A_UTEB 6 2 GEN0_A_UTEP 2 2 GEN0_A_UTEZ 0 2 GEN0_B MCPWM_GEN0_B 0x54 32 read-write n 0x0 0x0 GEN0_B_DT0 20 2 GEN0_B_DT1 22 2 GEN0_B_DTEA 16 2 GEN0_B_DTEB 18 2 GEN0_B_DTEP 14 2 GEN0_B_DTEZ 12 2 GEN0_B_UT0 8 2 GEN0_B_UT1 10 2 GEN0_B_UTEA 4 2 GEN0_B_UTEB 6 2 GEN0_B_UTEP 2 2 GEN0_B_UTEZ 0 2 GEN0_CFG0 MCPWM_GEN0_CFG0 0x48 32 read-write n 0x0 0x0 GEN0_CFG_UPMETHOD 0 4 GEN0_T0_SEL 4 3 GEN0_T1_SEL 7 3 GEN0_FORCE MCPWM_GEN0_FORCE 0x4C 32 read-write n 0x0 0x0 GEN0_A_CNTUFORCE_MODE 6 2 GEN0_A_NCIFORCE 10 1 GEN0_A_NCIFORCE_MODE 11 2 GEN0_B_CNTUFORCE_MODE 8 2 GEN0_B_NCIFORCE 13 1 GEN0_B_NCIFORCE_MODE 14 2 GEN0_CNTUFORCE_UPMETHOD 0 6 GEN0_STMP_CFG MCPWM_GEN0_STMP_CFG 0x3C 32 read-write n 0x0 0x0 GEN0_A_SHDW_FULL 8 1 GEN0_A_UPMETHOD 0 4 GEN0_B_SHDW_FULL 9 1 GEN0_B_UPMETHOD 4 4 GEN0_TSTMP_A MCPWM_GEN0_TSTMP_A 0x40 32 read-write n 0x0 0x0 GEN0_A 0 16 GEN0_TSTMP_B MCPWM_GEN0_TSTMP_B 0x44 32 read-write n 0x0 0x0 GEN0_B 0 16 GEN1_A MCPWM_GEN1_A 0x88 32 read-write n 0x0 0x0 GEN1_A_DT0 20 2 GEN1_A_DT1 22 2 GEN1_A_DTEA 16 2 GEN1_A_DTEB 18 2 GEN1_A_DTEP 14 2 GEN1_A_DTEZ 12 2 GEN1_A_UT0 8 2 GEN1_A_UT1 10 2 GEN1_A_UTEA 4 2 GEN1_A_UTEB 6 2 GEN1_A_UTEP 2 2 GEN1_A_UTEZ 0 2 GEN1_B MCPWM_GEN1_B 0x8C 32 read-write n 0x0 0x0 GEN1_B_DT0 20 2 GEN1_B_DT1 22 2 GEN1_B_DTEA 16 2 GEN1_B_DTEB 18 2 GEN1_B_DTEP 14 2 GEN1_B_DTEZ 12 2 GEN1_B_UT0 8 2 GEN1_B_UT1 10 2 GEN1_B_UTEA 4 2 GEN1_B_UTEB 6 2 GEN1_B_UTEP 2 2 GEN1_B_UTEZ 0 2 GEN1_CFG0 MCPWM_GEN1_CFG0 0x80 32 read-write n 0x0 0x0 GEN1_CFG_UPMETHOD 0 4 GEN1_T0_SEL 4 3 GEN1_T1_SEL 7 3 GEN1_FORCE MCPWM_GEN1_FORCE 0x84 32 read-write n 0x0 0x0 GEN1_A_CNTUFORCE_MODE 6 2 GEN1_A_NCIFORCE 10 1 GEN1_A_NCIFORCE_MODE 11 2 GEN1_B_CNTUFORCE_MODE 8 2 GEN1_B_NCIFORCE 13 1 GEN1_B_NCIFORCE_MODE 14 2 GEN1_CNTUFORCE_UPMETHOD 0 6 GEN1_STMP_CFG MCPWM_GEN1_STMP_CFG 0x74 32 read-write n 0x0 0x0 GEN1_A_SHDW_FULL 8 1 GEN1_A_UPMETHOD 0 4 GEN1_B_SHDW_FULL 9 1 GEN1_B_UPMETHOD 4 4 GEN1_TSTMP_A MCPWM_GEN1_TSTMP_A 0x78 32 read-write n 0x0 0x0 GEN1_A 0 16 GEN1_TSTMP_B MCPWM_GEN1_TSTMP_B 0x7C 32 read-write n 0x0 0x0 GEN1_B 0 16 GEN2_A MCPWM_GEN2_A 0xC0 32 read-write n 0x0 0x0 GEN2_A_DT0 20 2 GEN2_A_DT1 22 2 GEN2_A_DTEA 16 2 GEN2_A_DTEB 18 2 GEN2_A_DTEP 14 2 GEN2_A_DTEZ 12 2 GEN2_A_UT0 8 2 GEN2_A_UT1 10 2 GEN2_A_UTEA 4 2 GEN2_A_UTEB 6 2 GEN2_A_UTEP 2 2 GEN2_A_UTEZ 0 2 GEN2_B MCPWM_GEN2_B 0xC4 32 read-write n 0x0 0x0 GEN2_B_DT0 20 2 GEN2_B_DT1 22 2 GEN2_B_DTEA 16 2 GEN2_B_DTEB 18 2 GEN2_B_DTEP 14 2 GEN2_B_DTEZ 12 2 GEN2_B_UT0 8 2 GEN2_B_UT1 10 2 GEN2_B_UTEA 4 2 GEN2_B_UTEB 6 2 GEN2_B_UTEP 2 2 GEN2_B_UTEZ 0 2 GEN2_CFG0 MCPWM_GEN2_CFG0 0xB8 32 read-write n 0x0 0x0 GEN2_CFG_UPMETHOD 0 4 GEN2_T0_SEL 4 3 GEN2_T1_SEL 7 3 GEN2_FORCE MCPWM_GEN2_FORCE 0xBC 32 read-write n 0x0 0x0 GEN2_A_CNTUFORCE_MODE 6 2 GEN2_A_NCIFORCE 10 1 GEN2_A_NCIFORCE_MODE 11 2 GEN2_B_CNTUFORCE_MODE 8 2 GEN2_B_NCIFORCE 13 1 GEN2_B_NCIFORCE_MODE 14 2 GEN2_CNTUFORCE_UPMETHOD 0 6 GEN2_STMP_CFG MCPWM_GEN2_STMP_CFG 0xAC 32 read-write n 0x0 0x0 GEN2_A_SHDW_FULL 8 1 GEN2_A_UPMETHOD 0 4 GEN2_B_SHDW_FULL 9 1 GEN2_B_UPMETHOD 4 4 GEN2_TSTMP_A MCPWM_GEN2_TSTMP_A 0xB0 32 read-write n 0x0 0x0 GEN2_A 0 16 GEN2_TSTMP_B MCPWM_GEN2_TSTMP_B 0xB4 32 read-write n 0x0 0x0 GEN2_B 0 16 MCMCPWM_INT_CLR_MCPWM MCMCPWM_INT_CLR_MCPWM 0x11C 32 read-write n 0x0 0x0 CAP0_INT_CLR 27 1 CAP1_INT_CLR 28 1 CAP2_INT_CLR 29 1 FAULT0_CLR_INT_CLR 12 1 FAULT0_INT_CLR 9 1 FAULT1_CLR_INT_CLR 13 1 FAULT1_INT_CLR 10 1 FAULT2_CLR_INT_CLR 14 1 FAULT2_INT_CLR 11 1 FH0_CBC_INT_CLR 21 1 FH0_OST_INT_CLR 24 1 FH1_CBC_INT_CLR 22 1 FH1_OST_INT_CLR 25 1 FH2_CBC_INT_CLR 23 1 FH2_OST_INT_CLR 26 1 OP0_TEA_INT_CLR 15 1 OP0_TEB_INT_CLR 18 1 OP1_TEA_INT_CLR 16 1 OP1_TEB_INT_CLR 19 1 OP2_TEA_INT_CLR 17 1 OP2_TEB_INT_CLR 20 1 TIMER0_STOP_INT_CLR 0 1 TIMER0_TEP_INT_CLR 6 1 TIMER0_TEZ_INT_CLR 3 1 TIMER1_STOP_INT_CLR 1 1 TIMER1_TEP_INT_CLR 7 1 TIMER1_TEZ_INT_CLR 4 1 TIMER2_STOP_INT_CLR 2 1 TIMER2_TEP_INT_CLR 8 1 TIMER2_TEZ_INT_CLR 5 1 MCMCPWM_INT_ENA_MCPWM MCMCPWM_INT_ENA_MCPWM 0x110 32 read-write n 0x0 0x0 CAP0_INT_ENA 27 1 CAP1_INT_ENA 28 1 CAP2_INT_ENA 29 1 FAULT0_CLR_INT_ENA 12 1 FAULT0_INT_ENA 9 1 FAULT1_CLR_INT_ENA 13 1 FAULT1_INT_ENA 10 1 FAULT2_CLR_INT_ENA 14 1 FAULT2_INT_ENA 11 1 FH0_CBC_INT_ENA 21 1 FH0_OST_INT_ENA 24 1 FH1_CBC_INT_ENA 22 1 FH1_OST_INT_ENA 25 1 FH2_CBC_INT_ENA 23 1 FH2_OST_INT_ENA 26 1 OP0_TEA_INT_ENA 15 1 OP0_TEB_INT_ENA 18 1 OP1_TEA_INT_ENA 16 1 OP1_TEB_INT_ENA 19 1 OP2_TEA_INT_ENA 17 1 OP2_TEB_INT_ENA 20 1 TIMER0_STOP_INT_ENA 0 1 TIMER0_TEP_INT_ENA 6 1 TIMER0_TEZ_INT_ENA 3 1 TIMER1_STOP_INT_ENA 1 1 TIMER1_TEP_INT_ENA 7 1 TIMER1_TEZ_INT_ENA 4 1 TIMER2_STOP_INT_ENA 2 1 TIMER2_TEP_INT_ENA 8 1 TIMER2_TEZ_INT_ENA 5 1 MCMCPWM_INT_RAW_MCPWM MCMCPWM_INT_RAW_MCPWM 0x114 32 read-write n 0x0 0x0 CAP0_INT_RAW 27 1 CAP1_INT_RAW 28 1 CAP2_INT_RAW 29 1 FAULT0_CLR_INT_RAW 12 1 FAULT0_INT_RAW 9 1 FAULT1_CLR_INT_RAW 13 1 FAULT1_INT_RAW 10 1 FAULT2_CLR_INT_RAW 14 1 FAULT2_INT_RAW 11 1 FH0_CBC_INT_RAW 21 1 FH0_OST_INT_RAW 24 1 FH1_CBC_INT_RAW 22 1 FH1_OST_INT_RAW 25 1 FH2_CBC_INT_RAW 23 1 FH2_OST_INT_RAW 26 1 OP0_TEA_INT_RAW 15 1 OP0_TEB_INT_RAW 18 1 OP1_TEA_INT_RAW 16 1 OP1_TEB_INT_RAW 19 1 OP2_TEA_INT_RAW 17 1 OP2_TEB_INT_RAW 20 1 TIMER0_STOP_INT_RAW 0 1 TIMER0_TEP_INT_RAW 6 1 TIMER0_TEZ_INT_RAW 3 1 TIMER1_STOP_INT_RAW 1 1 TIMER1_TEP_INT_RAW 7 1 TIMER1_TEZ_INT_RAW 4 1 TIMER2_STOP_INT_RAW 2 1 TIMER2_TEP_INT_RAW 8 1 TIMER2_TEZ_INT_RAW 5 1 MCMCPWM_INT_ST_MCPWM MCMCPWM_INT_ST_MCPWM 0x118 32 read-write n 0x0 0x0 CAP0_INT_ST 27 1 CAP1_INT_ST 28 1 CAP2_INT_ST 29 1 FAULT0_CLR_INT_ST 12 1 FAULT0_INT_ST 9 1 FAULT1_CLR_INT_ST 13 1 FAULT1_INT_ST 10 1 FAULT2_CLR_INT_ST 14 1 FAULT2_INT_ST 11 1 FH0_CBC_INT_ST 21 1 FH0_OST_INT_ST 24 1 FH1_CBC_INT_ST 22 1 FH1_OST_INT_ST 25 1 FH2_CBC_INT_ST 23 1 FH2_OST_INT_ST 26 1 OP0_TEA_INT_ST 15 1 OP0_TEB_INT_ST 18 1 OP1_TEA_INT_ST 16 1 OP1_TEB_INT_ST 19 1 OP2_TEA_INT_ST 17 1 OP2_TEB_INT_ST 20 1 TIMER0_STOP_INT_ST 0 1 TIMER0_TEP_INT_ST 6 1 TIMER0_TEZ_INT_ST 3 1 TIMER1_STOP_INT_ST 1 1 TIMER1_TEP_INT_ST 7 1 TIMER1_TEZ_INT_ST 4 1 TIMER2_STOP_INT_ST 2 1 TIMER2_TEP_INT_ST 8 1 TIMER2_TEZ_INT_ST 5 1 OPERATOR_TIMERSEL MCPWM_OPERATOR_TIMERSEL 0x38 32 read-write n 0x0 0x0 OPERATOR0_TIMERSEL 0 2 OPERATOR1_TIMERSEL 2 2 OPERATOR2_TIMERSEL 4 2 TIMER0_CFG0 MCPWM_TIMER0_CFG0 0x4 32 read-write n 0x0 0x0 TIMER0_PERIOD 8 16 TIMER0_PERIOD_UPMETHOD 24 2 TIMER0_PRESCALE 0 8 TIMER0_CFG1 MCPWM_TIMER0_CFG1 0x8 32 read-write n 0x0 0x0 TIMER0_MOD 3 2 TIMER0_START 0 3 TIMER0_STATUS MCPWM_TIMER0_STATUS 0x10 32 read-write n 0x0 0x0 TIMER0_DIRECTION 16 1 TIMER0_VALUE 0 16 TIMER0_SYNC MCPWM_TIMER0_SYNC 0xC 32 read-write n 0x0 0x0 TIMER0_PHASE 4 17 TIMER0_SYNCI_EN 0 1 TIMER0_SYNCO_SEL 2 2 TIMER0_SYNC_SW 1 1 TIMER1_CFG0 MCPWM_TIMER1_CFG0 0x14 32 read-write n 0x0 0x0 TIMER1_PERIOD 8 16 TIMER1_PERIOD_UPMETHOD 24 2 TIMER1_PRESCALE 0 8 TIMER1_CFG1 MCPWM_TIMER1_CFG1 0x18 32 read-write n 0x0 0x0 TIMER1_MOD 3 2 TIMER1_START 0 3 TIMER1_STATUS MCPWM_TIMER1_STATUS 0x20 32 read-write n 0x0 0x0 TIMER1_DIRECTION 16 1 TIMER1_VALUE 0 16 TIMER1_SYNC MCPWM_TIMER1_SYNC 0x1C 32 read-write n 0x0 0x0 TIMER1_PHASE 4 17 TIMER1_SYNCI_EN 0 1 TIMER1_SYNCO_SEL 2 2 TIMER1_SYNC_SW 1 1 TIMER2_CFG0 MCPWM_TIMER2_CFG0 0x24 32 read-write n 0x0 0x0 TIMER2_PERIOD 8 16 TIMER2_PERIOD_UPMETHOD 24 2 TIMER2_PRESCALE 0 8 TIMER2_CFG1 MCPWM_TIMER2_CFG1 0x28 32 read-write n 0x0 0x0 TIMER2_MOD 3 2 TIMER2_START 0 3 TIMER2_STATUS MCPWM_TIMER2_STATUS 0x30 32 read-write n 0x0 0x0 TIMER2_DIRECTION 16 1 TIMER2_VALUE 0 16 TIMER2_SYNC MCPWM_TIMER2_SYNC 0x2C 32 read-write n 0x0 0x0 TIMER2_PHASE 4 17 TIMER2_SYNCI_EN 0 1 TIMER2_SYNCO_SEL 2 2 TIMER2_SYNC_SW 1 1 TIMER_SYNCI_CFG MCPWM_TIMER_SYNCI_CFG 0x34 32 read-write n 0x0 0x0 EXTERNAL_SYNCI0_INVERT 9 1 EXTERNAL_SYNCI1_INVERT 10 1 EXTERNAL_SYNCI2_INVERT 11 1 TIMER0_SYNCISEL 0 3 TIMER1_SYNCISEL 3 3 TIMER2_SYNCISEL 6 3 UPDATE_CFG MCPWM_UPDATE_CFG 0x10C 32 read-write n 0x0 0x0 GLOBAL_FORCE_UP 1 1 GLOBAL_UP_EN 0 1 OP0_FORCE_UP 3 1 OP0_UP_EN 2 1 OP1_FORCE_UP 5 1 OP1_UP_EN 4 1 OP2_FORCE_UP 7 1 OP2_UP_EN 6 1 VERSION MCPWM_VERSION 0x124 32 read-write n 0x0 0x0 DATE 0 28 RMT RMT 0x0 0x0 0x6C0 registers n RMT_INTR interrupt of remote controller, level 47 APB_CONF RMT_APB_CONF 0xF0 32 read-write n 0x0 0x0 APB_FIFO_MASK 0 1 MEM_TX_WRAP_EN 1 1 CH0ADDR RMT_CH0ADDR 0x80 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH0 0 32 CH0CARRIER_DUTY RMT_CH0CARRIER_DUTY 0xB0 32 read-write n 0x0 0x0 CARRIER_HIGH_CH0 16 16 CARRIER_LOW_CH0 0 16 CH0CONF0 RMT_CH0CONF0 0x20 32 read-write n 0x0 0x0 CARRIER_EN_CH0 28 1 CARRIER_OUT_LV_CH0 29 1 CLK_EN 31 1 DIV_CNT_CH0 0 8 IDLE_THRES_CH0 8 16 MEM_PD 30 1 MEM_SIZE_CH0 24 4 CH0CONF1 RMT_CH0CONF1 0x24 32 read-write n 0x0 0x0 APB_MEM_RST_CH0 4 1 IDLE_OUT_EN_CH0 19 1 IDLE_OUT_LV_CH0 18 1 MEM_OWNER_CH0 5 1 MEM_RD_RST_CH0 3 1 MEM_WR_RST_CH0 2 1 REF_ALWAYS_ON_CH0 17 1 REF_CNT_RST_CH0 16 1 RX_EN_CH0 1 1 RX_FILTER_EN_CH0 7 1 RX_FILTER_THRES_CH0 8 8 TX_CONTI_MODE_CH0 6 1 TX_START_CH0 0 1 CH0STATUS RMT_CH0STATUS 0x60 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH0 31 1 APB_MEM_WR_ERR_CH0 30 1 MEM_EMPTY_CH0 29 1 MEM_FULL_CH0 28 1 MEM_OWNER_ERR_CH0 27 1 MEM_RADDR_EX_CH0 12 10 MEM_WADDR_EX_CH0 0 10 STATE_CH0 24 3 STATUS_CH0 0 32 CH0_TX_LIM RMT_CH0_TX_LIM 0xD0 32 read-write n 0x0 0x0 TX_LIM_CH0 0 9 CH1ADDR RMT_CH1ADDR 0x84 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH1 0 32 CH1CARRIER_DUTY RMT_CH1CARRIER_DUTY 0xB4 32 read-write n 0x0 0x0 CARRIER_HIGH_CH1 16 16 CARRIER_LOW_CH1 0 16 CH1CONF0 RMT_CH1CONF0 0x28 32 read-write n 0x0 0x0 CARRIER_EN_CH1 28 1 CARRIER_OUT_LV_CH1 29 1 DIV_CNT_CH1 0 8 IDLE_THRES_CH1 8 16 MEM_SIZE_CH1 24 4 CH1CONF1 RMT_CH1CONF1 0x2C 32 read-write n 0x0 0x0 APB_MEM_RST_CH1 4 1 IDLE_OUT_EN_CH1 19 1 IDLE_OUT_LV_CH1 18 1 MEM_OWNER_CH1 5 1 MEM_RD_RST_CH1 3 1 MEM_WR_RST_CH1 2 1 REF_ALWAYS_ON_CH1 17 1 REF_CNT_RST_CH1 16 1 RX_EN_CH1 1 1 RX_FILTER_EN_CH1 7 1 RX_FILTER_THRES_CH1 8 8 TX_CONTI_MODE_CH1 6 1 TX_START_CH1 0 1 CH1STATUS RMT_CH1STATUS 0x64 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH1 31 1 APB_MEM_WR_ERR_CH1 30 1 MEM_EMPTY_CH1 29 1 MEM_FULL_CH1 28 1 MEM_OWNER_ERR_CH1 27 1 MEM_RADDR_EX_CH1 12 10 MEM_WADDR_EX_CH1 0 10 STATE_CH1 24 3 STATUS_CH1 0 32 CH1_TX_LIM RMT_CH1_TX_LIM 0xD4 32 read-write n 0x0 0x0 TX_LIM_CH1 0 9 CH2ADDR RMT_CH2ADDR 0x88 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH2 0 32 CH2CARRIER_DUTY RMT_CH2CARRIER_DUTY 0xB8 32 read-write n 0x0 0x0 CARRIER_HIGH_CH2 16 16 CARRIER_LOW_CH2 0 16 CH2CONF0 RMT_CH2CONF0 0x30 32 read-write n 0x0 0x0 CARRIER_EN_CH2 28 1 CARRIER_OUT_LV_CH2 29 1 DIV_CNT_CH2 0 8 IDLE_THRES_CH2 8 16 MEM_SIZE_CH2 24 4 CH2CONF1 RMT_CH2CONF1 0x34 32 read-write n 0x0 0x0 APB_MEM_RST_CH2 4 1 IDLE_OUT_EN_CH2 19 1 IDLE_OUT_LV_CH2 18 1 MEM_OWNER_CH2 5 1 MEM_RD_RST_CH2 3 1 MEM_WR_RST_CH2 2 1 REF_ALWAYS_ON_CH2 17 1 REF_CNT_RST_CH2 16 1 RX_EN_CH2 1 1 RX_FILTER_EN_CH2 7 1 RX_FILTER_THRES_CH2 8 8 TX_CONTI_MODE_CH2 6 1 TX_START_CH2 0 1 CH2STATUS RMT_CH2STATUS 0x68 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH2 31 1 APB_MEM_WR_ERR_CH2 30 1 MEM_EMPTY_CH2 29 1 MEM_FULL_CH2 28 1 MEM_OWNER_ERR_CH2 27 1 MEM_RADDR_EX_CH2 12 10 MEM_WADDR_EX_CH2 0 10 STATE_CH2 24 3 STATUS_CH2 0 32 CH2_TX_LIM RMT_CH2_TX_LIM 0xD8 32 read-write n 0x0 0x0 TX_LIM_CH2 0 9 CH3ADDR RMT_CH3ADDR 0x8C 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH3 0 32 CH3CARRIER_DUTY RMT_CH3CARRIER_DUTY 0xBC 32 read-write n 0x0 0x0 CARRIER_HIGH_CH3 16 16 CARRIER_LOW_CH3 0 16 CH3CONF0 RMT_CH3CONF0 0x38 32 read-write n 0x0 0x0 CARRIER_EN_CH3 28 1 CARRIER_OUT_LV_CH3 29 1 DIV_CNT_CH3 0 8 IDLE_THRES_CH3 8 16 MEM_SIZE_CH3 24 4 CH3CONF1 RMT_CH3CONF1 0x3C 32 read-write n 0x0 0x0 APB_MEM_RST_CH3 4 1 IDLE_OUT_EN_CH3 19 1 IDLE_OUT_LV_CH3 18 1 MEM_OWNER_CH3 5 1 MEM_RD_RST_CH3 3 1 MEM_WR_RST_CH3 2 1 REF_ALWAYS_ON_CH3 17 1 REF_CNT_RST_CH3 16 1 RX_EN_CH3 1 1 RX_FILTER_EN_CH3 7 1 RX_FILTER_THRES_CH3 8 8 TX_CONTI_MODE_CH3 6 1 TX_START_CH3 0 1 CH3STATUS RMT_CH3STATUS 0x6C 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH3 31 1 APB_MEM_WR_ERR_CH3 30 1 MEM_EMPTY_CH3 29 1 MEM_FULL_CH3 28 1 MEM_OWNER_ERR_CH3 27 1 MEM_RADDR_EX_CH3 12 10 MEM_WADDR_EX_CH3 0 10 STATE_CH3 24 3 STATUS_CH3 0 32 CH3_TX_LIM RMT_CH3_TX_LIM 0xDC 32 read-write n 0x0 0x0 TX_LIM_CH3 0 9 CH4ADDR RMT_CH4ADDR 0x90 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH4 0 32 CH4CARRIER_DUTY RMT_CH4CARRIER_DUTY 0xC0 32 read-write n 0x0 0x0 CARRIER_HIGH_CH4 16 16 CARRIER_LOW_CH4 0 16 CH4CONF0 RMT_CH4CONF0 0x40 32 read-write n 0x0 0x0 CARRIER_EN_CH4 28 1 CARRIER_OUT_LV_CH4 29 1 DIV_CNT_CH4 0 8 IDLE_THRES_CH4 8 16 MEM_SIZE_CH4 24 4 CH4CONF1 RMT_CH4CONF1 0x44 32 read-write n 0x0 0x0 APB_MEM_RST_CH4 4 1 IDLE_OUT_EN_CH4 19 1 IDLE_OUT_LV_CH4 18 1 MEM_OWNER_CH4 5 1 MEM_RD_RST_CH4 3 1 MEM_WR_RST_CH4 2 1 REF_ALWAYS_ON_CH4 17 1 REF_CNT_RST_CH4 16 1 RX_EN_CH4 1 1 RX_FILTER_EN_CH4 7 1 RX_FILTER_THRES_CH4 8 8 TX_CONTI_MODE_CH4 6 1 TX_START_CH4 0 1 CH4STATUS RMT_CH4STATUS 0x70 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH4 31 1 APB_MEM_WR_ERR_CH4 30 1 MEM_EMPTY_CH4 29 1 MEM_FULL_CH4 28 1 MEM_OWNER_ERR_CH4 27 1 MEM_RADDR_EX_CH4 12 10 MEM_WADDR_EX_CH4 0 10 STATE_CH4 24 3 STATUS_CH4 0 32 CH4_TX_LIM RMT_CH4_TX_LIM 0xE0 32 read-write n 0x0 0x0 TX_LIM_CH4 0 9 CH5ADDR RMT_CH5ADDR 0x94 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH5 0 32 CH5CARRIER_DUTY RMT_CH5CARRIER_DUTY 0xC4 32 read-write n 0x0 0x0 CARRIER_HIGH_CH5 16 16 CARRIER_LOW_CH5 0 16 CH5CONF0 RMT_CH5CONF0 0x48 32 read-write n 0x0 0x0 CARRIER_EN_CH5 28 1 CARRIER_OUT_LV_CH5 29 1 DIV_CNT_CH5 0 8 IDLE_THRES_CH5 8 16 MEM_SIZE_CH5 24 4 CH5CONF1 RMT_CH5CONF1 0x4C 32 read-write n 0x0 0x0 APB_MEM_RST_CH5 4 1 IDLE_OUT_EN_CH5 19 1 IDLE_OUT_LV_CH5 18 1 MEM_OWNER_CH5 5 1 MEM_RD_RST_CH5 3 1 MEM_WR_RST_CH5 2 1 REF_ALWAYS_ON_CH5 17 1 REF_CNT_RST_CH5 16 1 RX_EN_CH5 1 1 RX_FILTER_EN_CH5 7 1 RX_FILTER_THRES_CH5 8 8 TX_CONTI_MODE_CH5 6 1 TX_START_CH5 0 1 CH5STATUS RMT_CH5STATUS 0x74 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH5 31 1 APB_MEM_WR_ERR_CH5 30 1 MEM_EMPTY_CH5 29 1 MEM_FULL_CH5 28 1 MEM_OWNER_ERR_CH5 27 1 MEM_RADDR_EX_CH5 12 10 MEM_WADDR_EX_CH5 0 10 STATE_CH5 24 3 STATUS_CH5 0 32 CH5_TX_LIM RMT_CH5_TX_LIM 0xE4 32 read-write n 0x0 0x0 TX_LIM_CH5 0 9 CH6ADDR RMT_CH6ADDR 0x98 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH6 0 32 CH6CARRIER_DUTY RMT_CH6CARRIER_DUTY 0xC8 32 read-write n 0x0 0x0 CARRIER_HIGH_CH6 16 16 CARRIER_LOW_CH6 0 16 CH6CONF0 RMT_CH6CONF0 0x50 32 read-write n 0x0 0x0 CARRIER_EN_CH6 28 1 CARRIER_OUT_LV_CH6 29 1 DIV_CNT_CH6 0 8 IDLE_THRES_CH6 8 16 MEM_SIZE_CH6 24 4 CH6CONF1 RMT_CH6CONF1 0x54 32 read-write n 0x0 0x0 APB_MEM_RST_CH6 4 1 IDLE_OUT_EN_CH6 19 1 IDLE_OUT_LV_CH6 18 1 MEM_OWNER_CH6 5 1 MEM_RD_RST_CH6 3 1 MEM_WR_RST_CH6 2 1 REF_ALWAYS_ON_CH6 17 1 REF_CNT_RST_CH6 16 1 RX_EN_CH6 1 1 RX_FILTER_EN_CH6 7 1 RX_FILTER_THRES_CH6 8 8 TX_CONTI_MODE_CH6 6 1 TX_START_CH6 0 1 CH6STATUS RMT_CH6STATUS 0x78 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH6 31 1 APB_MEM_WR_ERR_CH6 30 1 MEM_EMPTY_CH6 29 1 MEM_FULL_CH6 28 1 MEM_OWNER_ERR_CH6 27 1 MEM_RADDR_EX_CH6 12 10 MEM_WADDR_EX_CH6 0 10 STATE_CH6 24 3 STATUS_CH6 0 32 CH6_TX_LIM RMT_CH6_TX_LIM 0xE8 32 read-write n 0x0 0x0 TX_LIM_CH6 0 9 CH7ADDR RMT_CH7ADDR 0x9C 32 read-write n 0x0 0x0 APB_MEM_ADDR_CH7 0 32 CH7CARRIER_DUTY RMT_CH7CARRIER_DUTY 0xCC 32 read-write n 0x0 0x0 CARRIER_HIGH_CH7 16 16 CARRIER_LOW_CH7 0 16 CH7CONF0 RMT_CH7CONF0 0x58 32 read-write n 0x0 0x0 CARRIER_EN_CH7 28 1 CARRIER_OUT_LV_CH7 29 1 DIV_CNT_CH7 0 8 IDLE_THRES_CH7 8 16 MEM_SIZE_CH7 24 4 CH7CONF1 RMT_CH7CONF1 0x5C 32 read-write n 0x0 0x0 APB_MEM_RST_CH7 4 1 IDLE_OUT_EN_CH7 19 1 IDLE_OUT_LV_CH7 18 1 MEM_OWNER_CH7 5 1 MEM_RD_RST_CH7 3 1 MEM_WR_RST_CH7 2 1 REF_ALWAYS_ON_CH7 17 1 REF_CNT_RST_CH7 16 1 RX_EN_CH7 1 1 RX_FILTER_EN_CH7 7 1 RX_FILTER_THRES_CH7 8 8 TX_CONTI_MODE_CH7 6 1 TX_START_CH7 0 1 CH7STATUS RMT_CH7STATUS 0x7C 32 read-write n 0x0 0x0 APB_MEM_RD_ERR_CH7 31 1 APB_MEM_WR_ERR_CH7 30 1 MEM_EMPTY_CH7 29 1 MEM_FULL_CH7 28 1 MEM_OWNER_ERR_CH7 27 1 MEM_RADDR_EX_CH7 12 10 MEM_WADDR_EX_CH7 0 10 STATE_CH7 24 3 STATUS_CH7 0 32 CH7_TX_LIM RMT_CH7_TX_LIM 0xEC 32 read-write n 0x0 0x0 TX_LIM_CH7 0 9 DATE RMT_DATE 0xFC 32 read-write n 0x0 0x0 DATE 0 32 INT_CLR RMT_INT_CLR 0xAC 32 read-write n 0x0 0x0 CH0_ERR_INT_CLR 2 1 CH0_RX_END_INT_CLR 1 1 CH0_TX_END_INT_CLR 0 1 CH0_TX_THR_EVENT_INT_CLR 24 1 CH1_ERR_INT_CLR 5 1 CH1_RX_END_INT_CLR 4 1 CH1_TX_END_INT_CLR 3 1 CH1_TX_THR_EVENT_INT_CLR 25 1 CH2_ERR_INT_CLR 8 1 CH2_RX_END_INT_CLR 7 1 CH2_TX_END_INT_CLR 6 1 CH2_TX_THR_EVENT_INT_CLR 26 1 CH3_ERR_INT_CLR 11 1 CH3_RX_END_INT_CLR 10 1 CH3_TX_END_INT_CLR 9 1 CH3_TX_THR_EVENT_INT_CLR 27 1 CH4_ERR_INT_CLR 14 1 CH4_RX_END_INT_CLR 13 1 CH4_TX_END_INT_CLR 12 1 CH4_TX_THR_EVENT_INT_CLR 28 1 CH5_ERR_INT_CLR 17 1 CH5_RX_END_INT_CLR 16 1 CH5_TX_END_INT_CLR 15 1 CH5_TX_THR_EVENT_INT_CLR 29 1 CH6_ERR_INT_CLR 20 1 CH6_RX_END_INT_CLR 19 1 CH6_TX_END_INT_CLR 18 1 CH6_TX_THR_EVENT_INT_CLR 30 1 CH7_ERR_INT_CLR 23 1 CH7_RX_END_INT_CLR 22 1 CH7_TX_END_INT_CLR 21 1 CH7_TX_THR_EVENT_INT_CLR 31 1 INT_ENA RMT_INT_ENA 0xA8 32 read-write n 0x0 0x0 CH0_ERR_INT_ENA 2 1 CH0_RX_END_INT_ENA 1 1 CH0_TX_END_INT_ENA 0 1 CH0_TX_THR_EVENT_INT_ENA 24 1 CH1_ERR_INT_ENA 5 1 CH1_RX_END_INT_ENA 4 1 CH1_TX_END_INT_ENA 3 1 CH1_TX_THR_EVENT_INT_ENA 25 1 CH2_ERR_INT_ENA 8 1 CH2_RX_END_INT_ENA 7 1 CH2_TX_END_INT_ENA 6 1 CH2_TX_THR_EVENT_INT_ENA 26 1 CH3_ERR_INT_ENA 11 1 CH3_RX_END_INT_ENA 10 1 CH3_TX_END_INT_ENA 9 1 CH3_TX_THR_EVENT_INT_ENA 27 1 CH4_ERR_INT_ENA 14 1 CH4_RX_END_INT_ENA 13 1 CH4_TX_END_INT_ENA 12 1 CH4_TX_THR_EVENT_INT_ENA 28 1 CH5_ERR_INT_ENA 17 1 CH5_RX_END_INT_ENA 16 1 CH5_TX_END_INT_ENA 15 1 CH5_TX_THR_EVENT_INT_ENA 29 1 CH6_ERR_INT_ENA 20 1 CH6_RX_END_INT_ENA 19 1 CH6_TX_END_INT_ENA 18 1 CH6_TX_THR_EVENT_INT_ENA 30 1 CH7_ERR_INT_ENA 23 1 CH7_RX_END_INT_ENA 22 1 CH7_TX_END_INT_ENA 21 1 CH7_TX_THR_EVENT_INT_ENA 31 1 INT_RAW RMT_INT_RAW 0xA0 32 read-write n 0x0 0x0 CH0_ERR_INT_RAW 2 1 CH0_RX_END_INT_RAW 1 1 CH0_TX_END_INT_RAW 0 1 CH0_TX_THR_EVENT_INT_RAW 24 1 CH1_ERR_INT_RAW 5 1 CH1_RX_END_INT_RAW 4 1 CH1_TX_END_INT_RAW 3 1 CH1_TX_THR_EVENT_INT_RAW 25 1 CH2_ERR_INT_RAW 8 1 CH2_RX_END_INT_RAW 7 1 CH2_TX_END_INT_RAW 6 1 CH2_TX_THR_EVENT_INT_RAW 26 1 CH3_ERR_INT_RAW 11 1 CH3_RX_END_INT_RAW 10 1 CH3_TX_END_INT_RAW 9 1 CH3_TX_THR_EVENT_INT_RAW 27 1 CH4_ERR_INT_RAW 14 1 CH4_RX_END_INT_RAW 13 1 CH4_TX_END_INT_RAW 12 1 CH4_TX_THR_EVENT_INT_RAW 28 1 CH5_ERR_INT_RAW 17 1 CH5_RX_END_INT_RAW 16 1 CH5_TX_END_INT_RAW 15 1 CH5_TX_THR_EVENT_INT_RAW 29 1 CH6_ERR_INT_RAW 20 1 CH6_RX_END_INT_RAW 19 1 CH6_TX_END_INT_RAW 18 1 CH6_TX_THR_EVENT_INT_RAW 30 1 CH7_ERR_INT_RAW 23 1 CH7_RX_END_INT_RAW 22 1 CH7_TX_END_INT_RAW 21 1 CH7_TX_THR_EVENT_INT_RAW 31 1 INT_ST RMT_INT_ST 0xA4 32 read-write n 0x0 0x0 CH0_ERR_INT_ST 2 1 CH0_RX_END_INT_ST 1 1 CH0_TX_END_INT_ST 0 1 CH0_TX_THR_EVENT_INT_ST 24 1 CH1_ERR_INT_ST 5 1 CH1_RX_END_INT_ST 4 1 CH1_TX_END_INT_ST 3 1 CH1_TX_THR_EVENT_INT_ST 25 1 CH2_ERR_INT_ST 8 1 CH2_RX_END_INT_ST 7 1 CH2_TX_END_INT_ST 6 1 CH2_TX_THR_EVENT_INT_ST 26 1 CH3_ERR_INT_ST 11 1 CH3_RX_END_INT_ST 10 1 CH3_TX_END_INT_ST 9 1 CH3_TX_THR_EVENT_INT_ST 27 1 CH4_ERR_INT_ST 14 1 CH4_RX_END_INT_ST 13 1 CH4_TX_END_INT_ST 12 1 CH4_TX_THR_EVENT_INT_ST 28 1 CH5_ERR_INT_ST 17 1 CH5_RX_END_INT_ST 16 1 CH5_TX_END_INT_ST 15 1 CH5_TX_THR_EVENT_INT_ST 29 1 CH6_ERR_INT_ST 20 1 CH6_RX_END_INT_ST 19 1 CH6_TX_END_INT_ST 18 1 CH6_TX_THR_EVENT_INT_ST 30 1 CH7_ERR_INT_ST 23 1 CH7_RX_END_INT_ST 22 1 CH7_TX_END_INT_ST 21 1 CH7_TX_THR_EVENT_INT_ST 31 1 RSA RSA 0x0 0x0 0x0 registers n RSA_INTR interrupt of RSA accelerator, level 51 RTCCNTL RTCCNTL 0x0 0x0 0x6A0 RTC CNTL registers n 0x200C6000 0x4 Internal I2C registers n RTC_CORE_INTR interrupt of rtc core, level, include rtc watchdog 46 ANA_CONF RTC_CNTL_ANA_CONF 0x30 32 read-write n 0x0 0x0 BBPLL_CAL_SLP_START 25 1 CKGEN_I2C_PU 30 1 PLLA_FORCE_PD 23 1 PLLA_FORCE_PU 24 1 PLL_I2C_PU 31 1 PVTMON_PU 26 1 RFRX_PBUS_PU 28 1 TXRF_I2C_PU 27 1 APLL APLL I2C Register 0x200C600C 32 read-write n 0x0 0x0 ADDR Address 8 8 BLOCK Block 0 8 BUSY Ready 25 1 DATA Data 16 8 WRITE Write 24 1 BIAS_CONF RTC_CNTL_BIAS_CONF 0x78 32 read-write n 0x0 0x0 DBG_ATTEN 24 2 DBIAS_SLP 22 3 DBIAS_WAK 25 3 DBOOST_FORCE_PD 28 1 DBOOST_FORCE_PU 29 1 DEC_HEARTBEAT_PERIOD 28 1 DEC_HEARTBEAT_WIDTH 30 1 DIG_DBIAS_SLP 8 3 DIG_DBIAS_WAK 11 3 ENB_SCK_XTAL 26 1 FORCE_PD 30 1 FORCE_PU 31 1 INC_HEARTBEAT_PERIOD 29 1 INC_HEARTBEAT_REFRESH 27 1 RST_BIAS_I2C 31 1 SCK_DCAP 14 8 SCK_DCAP_FORCE 7 1 BROWN_OUT RTC_CNTL_BROWN_OUT 0xD4 32 read-write n 0x0 0x0 BROWN_OUT_CLOSE_FLASH_ENA 14 1 BROWN_OUT_DET 31 1 BROWN_OUT_ENA 30 1 BROWN_OUT_PD_RF_ENA 15 1 BROWN_OUT_RST_ENA 26 1 BROWN_OUT_RST_WAIT 16 10 DBROWN_OUT_THRES 27 3 CLK_CONF RTC_CNTL_CLK_CONF 0x70 32 read-write n 0x0 0x0 ANA_CLK_RTC_SEL 30 2 ANA_CLK_RTC_SEL read-write SLOW_CK Select slow clock 0 CK_XTAL_32K Select XTAL_32K 1 CK8M_D256_OUT Internal 8 MHz RC oscillator, divided by 256 2 CK8M_DFREQ 17 8 CK8M_DFREQ_FORCE 11 1 CK8M_DIV 4 2 CK8M_DIV read-write div128 div128 0 div256 div256 1 div512 div512 2 div1024 div1024 3 CK8M_DIV_SEL 12 3 CK8M_FORCE_NOGATING 16 1 CK8M_FORCE_PD 25 1 CK8M_FORCE_PD read-write Clear Don't force power down 0 Force Force power down 1 CK8M_FORCE_PU 26 1 CK8M_FORCE_PU read-write Clear Don't force power up 0 Force Force power up 1 DIG_CLK8M_D256_EN 9 1 DIG_CLK8M_D256_EN read-write Disable Disable CK8M_D256_OUT 0 Enable Enable CK8M_D256_OUT for digital core (no relation to RTC core) 1 DIG_CLK8M_EN 10 1 DIG_CLK8M_EN read-write Disable Disable CK8M 0 Enable Enable CK8M for digital core (no relation to RTC core) 1 DIG_XTAL32K_EN 8 1 DIG_XTAL32K_EN read-write Disable Disable CK_XTAL_32K 0 Enable Enable CK_XTAL_32K for digital core(no relation to RTC core) 1 ENB_CK8M 6 1 ENB_CK8M_DIV 7 1 FAST_CLK_RTC_SEL 29 1 FAST_CLK_RTC_SEL read-write XTAL Select XTAL 0 CK8M Select CK8M 1 SOC_CLK_SEL 27 2 SOC_CLK_SEL read-write XTAL Select XTAL clock 0 PLL Select PLL clock 1 CK8M Select CK8M clock 2 APLL Select APLL clock 3 XTAL_FORCE_NOGATING 15 1 CNTL RTC Control Register 0x7C 32 read-write n 0x0 0x0 DBIAS_SLP RTC DBIAS during sleep 22 3 DBIAS_WAK RTC DBIAS during wakeup 25 3 DBIAS_WAK read-write BIAS_0V90 Core voltage 0.90V 0 BIAS_0V95 Core voltage 0.95V 1 BIAS_1V00 Core voltage 1.00V 2 BIAS_1V05 Core voltage 1.05V 3 BIAS_1V10 Core voltage 1.10V 4 BIAS_1V15 Core voltage 1.15V 5 BIAS_1V20 Core voltage 1.20V 6 BIAS_1V25 Core voltage 1.25V 7 DIG_DBIAS_SLP DBIAS during wakeup 8 3 DIG_DBIAS_WAK DBIAS during wakeup 11 3 FORCE_DBOOST_PD Force DBOOST power down 28 1 FORCE_DBOOST_PU Force DBOOST power up 29 1 FORCE_PD Force RTC power down (decrease voltage to 0.8V or lower) 30 1 FORCE_PU Force RTC power up 31 1 SCK_DCAP 150kHz oscillator tuning 14 8 SCK_DCAP_FORCE 150kHz tuning force 7 1 CPU_PERIOD_CONF RTC_CNTL_CPU_PERIOD_CONF 0x68 32 read-write n 0x0 0x0 CPUPERIOD_SEL 30 2 CPUSEL_CONF 29 1 DATE RTC_CNTL_DATE 0x13C 32 read-write n 0x0 0x0 CNTL_DATE 0 28 DIAG1 RTC_CNTL_DIAG1 0xC4 32 read-write n 0x0 0x0 LOW_POWER_DIAG1 0 32 DIG_ISO RTC_CNTL_DIG_ISO 0x88 32 read-write n 0x0 0x0 CLR_DG_PAD_AUTOHOLD 10 1 DG_PAD_AUTOHOLD 9 1 DG_PAD_AUTOHOLD_EN 11 1 DG_PAD_FORCE_HOLD 15 1 DG_PAD_FORCE_ISO 13 1 DG_PAD_FORCE_NOISO 12 1 DG_PAD_FORCE_UNHOLD 14 1 DG_WRAP_FORCE_ISO 30 1 DG_WRAP_FORCE_NOISO 31 1 DIG_ISO_FORCE_OFF 7 1 DIG_ISO_FORCE_ON 8 1 INTER_RAM0_FORCE_ISO 18 1 INTER_RAM0_FORCE_NOISO 19 1 INTER_RAM1_FORCE_ISO 20 1 INTER_RAM1_FORCE_NOISO 21 1 INTER_RAM2_FORCE_ISO 22 1 INTER_RAM2_FORCE_NOISO 23 1 INTER_RAM3_FORCE_ISO 24 1 INTER_RAM3_FORCE_NOISO 25 1 INTER_RAM4_FORCE_ISO 26 1 INTER_RAM4_FORCE_NOISO 27 1 ROM0_FORCE_ISO 16 1 ROM0_FORCE_NOISO 17 1 WIFI_FORCE_ISO 28 1 WIFI_FORCE_NOISO 29 1 DIG_PWC RTC_CNTL_DIG_PWC 0x84 32 read-write n 0x0 0x0 DG_WRAP_FORCE_PD 19 1 DG_WRAP_FORCE_PU 20 1 DG_WRAP_PD_EN 31 1 INTER_RAM0_FORCE_PD 7 1 INTER_RAM0_FORCE_PU 8 1 INTER_RAM0_PD_EN 25 1 INTER_RAM1_FORCE_PD 9 1 INTER_RAM1_FORCE_PU 10 1 INTER_RAM1_PD_EN 26 1 INTER_RAM2_FORCE_PD 11 1 INTER_RAM2_FORCE_PU 12 1 INTER_RAM2_PD_EN 27 1 INTER_RAM3_FORCE_PD 13 1 INTER_RAM3_FORCE_PU 14 1 INTER_RAM3_PD_EN 28 1 INTER_RAM4_FORCE_PD 15 1 INTER_RAM4_FORCE_PU 16 1 INTER_RAM4_PD_EN 29 1 LSLP_MEM_FORCE_PD 3 1 LSLP_MEM_FORCE_PU 4 1 ROM0_FORCE_PD 5 1 ROM0_FORCE_PU 6 1 ROM0_PD_EN 24 1 WIFI_FORCE_PD 17 1 WIFI_FORCE_PU 18 1 WIFI_PD_EN 30 1 EXT_WAKEUP1 RTC_CNTL_EXT_WAKEUP1 0xCC 32 read-write n 0x0 0x0 EXT_WAKEUP1_SEL 0 18 EXT_WAKEUP1_STATUS_CLR 18 1 EXT_WAKEUP1_STATUS RTC_CNTL_EXT_WAKEUP1_STATUS 0xD0 32 read-write n 0x0 0x0 EXT_WAKEUP1_STATUS 0 18 EXT_WAKEUP_CONF RTC_CNTL_EXT_WAKEUP_CONF 0x60 32 read-write n 0x0 0x0 EXT_WAKEUP0_LV 30 1 EXT_WAKEUP1_LV 31 1 EXT_XTL_CONF RTC_CNTL_EXT_XTL_CONF 0x5C 32 read-write n 0x0 0x0 XTL_EXT_CTR_EN 31 1 XTL_EXT_CTR_LV 30 1 HOLD_FORCE RTC_CNTL_HOLD_FORCE 0xC8 32 read-write n 0x0 0x0 ADC1_HOLD_FORCE 0 1 ADC2_HOLD_FORCE 1 1 PDAC1_HOLD_FORCE 2 1 PDAC2_HOLD_FORCE 3 1 SENSE1_HOLD_FORCE 4 1 SENSE2_HOLD_FORCE 5 1 SENSE3_HOLD_FORCE 6 1 SENSE4_HOLD_FORCE 7 1 TOUCH_PAD0_HOLD_FORCE 8 1 TOUCH_PAD1_HOLD_FORCE 9 1 TOUCH_PAD2_HOLD_FORCE 10 1 TOUCH_PAD3_HOLD_FORCE 11 1 TOUCH_PAD4_HOLD_FORCE 12 1 TOUCH_PAD5_HOLD_FORCE 13 1 TOUCH_PAD6_HOLD_FORCE 14 1 TOUCH_PAD7_HOLD_FORCE 15 1 X32N_HOLD_FORCE 17 1 X32P_HOLD_FORCE 16 1 INT_CLR RTC_CNTL_INT_CLR 0x48 32 read-write n 0x0 0x0 BROWN_OUT_INT_CLR 7 1 MAIN_TIMER_INT_CLR 8 1 SAR_INT_CLR 5 1 SDIO_IDLE_INT_CLR 2 1 SLP_REJECT_INT_CLR 1 1 SLP_WAKEUP_INT_CLR 0 1 TIME_VALID_INT_CLR 4 1 TOUCH_INT_CLR 6 1 WDT_INT_CLR 3 1 INT_ENA RTC_CNTL_INT_ENA 0x3C 32 read-write n 0x0 0x0 BROWN_OUT_INT_ENA 7 1 MAIN_TIMER_INT_ENA 8 1 SDIO_IDLE_INT_ENA 2 1 SLP_REJECT_INT_ENA 1 1 SLP_WAKEUP_INT_ENA 0 1 TIME_VALID_INT_ENA 4 1 TOUCH_INT_ENA 6 1 ULP_CP_INT_ENA 5 1 WDT_INT_ENA 3 1 INT_RAW RTC_CNTL_INT_RAW 0x40 32 read-write n 0x0 0x0 BROWN_OUT_INT_RAW 7 1 MAIN_TIMER_INT_RAW 8 1 SDIO_IDLE_INT_RAW 2 1 SLP_REJECT_INT_RAW 1 1 SLP_WAKEUP_INT_RAW 0 1 TIME_VALID_INT_RAW 4 1 TOUCH_INT_RAW 6 1 ULP_CP_INT_RAW 5 1 WDT_INT_RAW 3 1 INT_ST RTC_CNTL_INT_ST 0x44 32 read-write n 0x0 0x0 BROWN_OUT_INT_ST 7 1 MAIN_TIMER_INT_ST 8 1 SAR_INT_ST 5 1 SDIO_IDLE_INT_ST 2 1 SLP_REJECT_INT_ST 1 1 SLP_WAKEUP_INT_ST 0 1 TIME_VALID_INT_ST 4 1 TOUCH_INT_ST 6 1 WDT_INT_ST 3 1 OPTIONS0 RTC_CNTL_OPTIONS0 0x0 32 read-write n 0x0 0x0 ANALOG_FORCE_ISO 25 1 ANALOG_FORCE_NOISO 28 1 BBPLL_FORCE_PD 10 1 BBPLL_FORCE_PU 11 1 BBPLL_I2C_FORCE_PD 8 1 BBPLL_I2C_FORCE_PU 9 1 BB_I2C_FORCE_PD 6 1 BB_I2C_FORCE_PU 7 1 BIAS_CORE_FOLW_8M 20 1 BIAS_CORE_FORCE_PD 21 1 BIAS_CORE_FORCE_PU 22 1 BIAS_FORCE_NOSLEEP 16 1 BIAS_FORCE_SLEEP 15 1 BIAS_I2C_FOLW_8M 17 1 BIAS_I2C_FORCE_PD 18 1 BIAS_I2C_FORCE_PU 19 1 BIAS_SLEEP_FOLW_8M 14 1 DG_WRAP_FORCE_NORST 30 1 DG_WRAP_FORCE_RST 29 1 PLL_FORCE_ISO 24 1 PLL_FORCE_NOISO 27 1 SW_APPCPU_RST 4 1 SW_PROCPU_RST 5 1 SW_STALL_APPCPU_C0 0 2 SW_STALL_PROCPU_C0 2 2 SW_SYS_RST 31 1 XTL_FORCE_ISO 23 1 XTL_FORCE_NOISO 26 1 XTL_FORCE_PD 12 1 XTL_FORCE_PU 13 1 PLL PLL I2C Register 0x200C6010 32 read-write n 0x0 0x0 ADDR Address 8 8 BLOCK Block 0 8 BUSY Ready 25 1 DATA Data 16 8 WRITE Write 24 1 PWC RTC_CNTL_PWC 0x80 32 read-write n 0x0 0x0 FASTMEM_FOLW_CPU 6 1 FASTMEM_FORCE_ISO 1 1 FASTMEM_FORCE_LPD 7 1 FASTMEM_FORCE_LPU 8 1 FASTMEM_FORCE_NOISO 0 1 FASTMEM_FORCE_PD 12 1 FASTMEM_FORCE_PU 13 1 FASTMEM_PD_EN 14 1 FORCE_ISO 4 1 FORCE_NOISO 5 1 FORCE_PD 18 1 FORCE_PU 19 1 PD_EN 20 1 SLOWMEM_FOLW_CPU 9 1 SLOWMEM_FORCE_ISO 3 1 SLOWMEM_FORCE_LPD 10 1 SLOWMEM_FORCE_LPU 11 1 SLOWMEM_FORCE_NOISO 2 1 SLOWMEM_FORCE_PD 15 1 SLOWMEM_FORCE_PU 16 1 SLOWMEM_PD_EN 17 1 RESET_STATE RTC_CNTL_RESET_STATE 0x34 32 read-write n 0x0 0x0 APPCPU_STAT_VECTOR_SEL 12 1 PROCPU_STAT_VECTOR_SEL 13 1 RESET_CAUSE_APPCPU 6 6 RESET_CAUSE_PROCPU 0 6 SDIO_ACT_CONF RTC_CNTL_SDIO_ACT_CONF 0x6C 32 read-write n 0x0 0x0 SDIO_ACT_DNUM 22 10 SDIO_CONF RTC_CNTL_SDIO_CONF 0x74 32 read-write n 0x0 0x0 DREFH_SDIO 29 2 DREFL_SDIO 25 2 DREFM_SDIO 27 2 REG1P8_READY 24 1 SDIO_FORCE 22 1 SDIO_PD_EN 21 1 SDIO_TIEH 23 1 XPD_SDIO_REG 31 1 SLP_REJECT_CONF RTC_CNTL_SLP_REJECT_CONF 0x64 32 read-write n 0x0 0x0 DEEP_SLP_REJECT_EN 27 1 GPIO_REJECT_EN 24 1 LIGHT_SLP_REJECT_EN 26 1 REJECT_CAUSE 28 4 SDIO_REJECT_EN 25 1 SLP_TIMER0 RTC_CNTL_SLP_TIMER0 0x4 32 read-write n 0x0 0x0 SLP_VAL_LO 0 32 SLP_TIMER1 RTC_CNTL_SLP_TIMER1 0x8 32 read-write n 0x0 0x0 MAIN_TIMER_ALARM_EN 16 1 SLP_VAL_HI 0 16 STATE0 RTC_CNTL_STATE0 0x18 32 read-write n 0x0 0x0 APB2RTC_BRIDGE_SEL 22 1 SDIO_ACTIVE_IND 28 1 SLEEP_EN 31 1 SLP_REJECT 30 1 SLP_WAKEUP 29 1 TOUCH_SLP_TIMER_EN 23 1 TOUCH_WAKEUP_FORCE_EN 20 1 ULP_CP_SLP_TIMER_EN 24 1 ULP_CP_WAKEUP_FORCE_EN 21 1 STORE0 RTC_CNTL_STORE0 0x4C 32 read-write n 0x0 0x0 SCRATCH0 0 32 STORE1 RTC_CNTL_STORE1 0x50 32 read-write n 0x0 0x0 SCRATCH1 0 32 STORE2 RTC_CNTL_STORE2 0x54 32 read-write n 0x0 0x0 SCRATCH2 0 32 STORE3 RTC_CNTL_STORE3 0x58 32 read-write n 0x0 0x0 SCRATCH3 0 32 STORE4 RTC_CNTL_STORE4 0xB0 32 read-write n 0x0 0x0 SCRATCH4 0 32 STORE5 RTC_CNTL_STORE5 0xB4 32 read-write n 0x0 0x0 SCRATCH5 0 32 STORE6 RTC_CNTL_STORE6 0xB8 32 read-write n 0x0 0x0 SCRATCH6 0 32 STORE7 RTC_CNTL_STORE7 0xBC 32 read-write n 0x0 0x0 SCRATCH7 0 32 SW_CPU_STALL RTC_CNTL_SW_CPU_STALL 0xAC 32 read-write n 0x0 0x0 SW_STALL_APPCPU_C1 20 6 SW_STALL_PROCPU_C1 26 6 TEST_MUX RTC_CNTL_TEST_MUX 0xA8 32 read-write n 0x0 0x0 DTEST_RTC 30 2 ENT_RTC 29 1 TIME0 RTC_CNTL_TIME0 0x10 32 read-write n 0x0 0x0 TIME_LO 0 32 TIME1 RTC_CNTL_TIME1 0x14 32 read-write n 0x0 0x0 TIME_HI 0 16 TIMER1 RTC_CNTL_TIMER1 0x1C 32 read-write n 0x0 0x0 CK8M_WAIT 6 8 CPU_STALL_EN 0 1 CPU_STALL_WAIT 1 5 PLL_BUF_WAIT 24 8 XTL_BUF_WAIT 14 10 TIMER2 RTC_CNTL_TIMER2 0x20 32 read-write n 0x0 0x0 MIN_TIME_CK8M_OFF 24 8 ULPCP_TOUCH_START_WAIT 15 9 TIMER3 RTC_CNTL_TIMER3 0x24 32 read-write n 0x0 0x0 ROM_RAM_POWERUP_TIMER 25 7 ROM_RAM_WAIT_TIMER 16 9 WIFI_POWERUP_TIMER 9 7 WIFI_WAIT_TIMER 0 9 TIMER4 RTC_CNTL_TIMER4 0x28 32 read-write n 0x0 0x0 DG_WRAP_POWERUP_TIMER 25 7 DG_WRAP_WAIT_TIMER 16 9 POWERUP_TIMER 9 7 WAIT_TIMER 0 9 TIMER5 RTC_CNTL_TIMER5 0x2C 32 read-write n 0x0 0x0 MIN_SLP_VAL 8 8 RTCMEM_POWERUP_TIMER 25 7 RTCMEM_WAIT_TIMER 16 9 ULP_CP_SUBTIMER_PREDIV 0 8 TIME_UPDATE RTC_CNTL_TIME_UPDATE 0xC 32 read-write n 0x0 0x0 TIME_UPDATE 31 1 TIME_VALID 30 1 WAKEUP_STATE RTC_CNTL_WAKEUP_STATE 0x38 32 read-write n 0x0 0x0 GPIO_WAKEUP_FILTER 22 1 WAKEUP_CAUSE 0 11 WAKEUP_ENA 11 11 WDTCONFIG0 RTC_CNTL_WDTCONFIG0 0x8C 32 read-write n 0x0 0x0 WDT_APPCPU_RESET_EN 8 1 WDT_CPU_RESET_LENGTH 14 3 WDT_CPU_RESET_LENGTH read-write T100ns 100ns 0 T200ns 200ns 1 T300ns 300ns 2 T400ns 400ns 3 T500ns 500ns 4 T800ns 800ns 5 T1600ns 1600ns 6 T3200ns 3200ns 7 WDT_EDGE_INT_EN 18 1 WDT_EN 31 1 WDT_FLASHBOOT_MOD_EN 10 1 WDT_LEVEL_INT_EN 17 1 WDT_PAUSE_IN_SLP 7 1 WDT_PROCPU_RESET_EN 9 1 WDT_STG0 28 3 WDT_STG0 read-write Disable Disabled 0 Interrupt Trigger an interrupt 1 ResetCPU Reset CPU core 2 ResetSystem Reset System, but not RTC 3 ResetRTC Reset System & RTC 4 WDT_STG1 25 3 WDT_STG2 22 3 WDT_STG3 19 3 WDT_SYS_RESET_LENGTH 11 3 WDTCONFIG1 RTC_CNTL_WDTCONFIG1 0x90 32 read-write n 0x0 0x0 WDT_STG0_HOLD 0 32 WDTCONFIG2 RTC_CNTL_WDTCONFIG2 0x94 32 read-write n 0x0 0x0 WDT_STG1_HOLD 0 32 WDTCONFIG3 RTC_CNTL_WDTCONFIG3 0x98 32 read-write n 0x0 0x0 WDT_STG2_HOLD 0 32 WDTCONFIG4 RTC_CNTL_WDTCONFIG4 0x9C 32 read-write n 0x0 0x0 WDT_STG3_HOLD 0 32 WDTFEED RTC_CNTL_WDTFEED 0xA0 32 read-write n 0x0 0x0 WDT_FEED 31 1 WDTWPROTECT RTC_CNTL_WDTWPROTECT 0xA4 32 read-write n 0x0 0x0 WDT_WKEY 0 32 RTCIO RTCIO 0x0 0x0 0x660 registers n ADC_PAD RTC_IO_ADC_PAD 0x80 32 read-write n 0x0 0x0 ADC1_FUN_IE 23 1 ADC1_FUN_SEL 26 2 ADC1_HOLD 31 1 ADC1_MUX_SEL 29 1 ADC1_SLP_IE 24 1 ADC1_SLP_SEL 25 1 ADC2_FUN_IE 18 1 ADC2_FUN_SEL 21 2 ADC2_HOLD 30 1 ADC2_MUX_SEL 28 1 ADC2_SLP_IE 19 1 ADC2_SLP_SEL 20 1 DATE RTC_IO_DATE 0xC8 32 read-write n 0x0 0x0 IO_DATE 0 28 DIG_PAD_HOLD RTC_IO_DIG_PAD_HOLD 0x74 32 read-write n 0x0 0x0 DIG_PAD_HOLD 0 32 ENABLE RTC_GPIO_ENABLE 0xC 32 read-write n 0x0 0x0 ENABLE 14 18 ENABLE_W1TC RTC_GPIO_ENABLE_W1TC 0x14 32 read-write n 0x0 0x0 ENABLE_W1TC 14 18 ENABLE_W1TS RTC_GPIO_ENABLE_W1TS 0x10 32 read-write n 0x0 0x0 ENABLE_W1TS 14 18 EXT_WAKEUP0 RTC_IO_EXT_WAKEUP0 0xBC 32 read-write n 0x0 0x0 EXT_WAKEUP0_SEL 27 5 HALL_SENS RTC_IO_HALL_SENS 0x78 32 read-write n 0x0 0x0 HALL_PHASE 30 1 XPD_HALL 31 1 IN RTC_GPIO_IN 0x24 32 read-write n 0x0 0x0 IN_NEXT 14 18 OUT RTC_GPIO_OUT 0x0 32 read-write n 0x0 0x0 OUT_DATA 14 18 OUT_W1TC RTC_GPIO_OUT_W1TC 0x8 32 read-write n 0x0 0x0 OUT_DATA_W1TC 14 18 OUT_W1TS RTC_GPIO_OUT_W1TS 0x4 32 read-write n 0x0 0x0 OUT_DATA_W1TS 14 18 PAD_DAC1 RTC_IO_PAD_DAC1 0x84 32 read-write n 0x0 0x0 PDAC1_DAC 19 8 PDAC1_DAC_XPD_FORCE 10 1 PDAC1_DRV 30 2 PDAC1_FUN_IE 11 1 PDAC1_FUN_SEL 15 2 PDAC1_HOLD 29 1 PDAC1_MUX_SEL 17 1 PDAC1_RDE 28 1 PDAC1_RUE 27 1 PDAC1_SLP_IE 13 1 PDAC1_SLP_OE 12 1 PDAC1_SLP_SEL 14 1 PDAC1_XPD_DAC 18 1 PAD_DAC2 RTC_IO_PAD_DAC2 0x88 32 read-write n 0x0 0x0 PDAC2_DAC 19 8 PDAC2_DAC_XPD_FORCE 10 1 PDAC2_DRV 30 2 PDAC2_FUN_IE 11 1 PDAC2_FUN_SEL 15 2 PDAC2_HOLD 29 1 PDAC2_MUX_SEL 17 1 PDAC2_RDE 28 1 PDAC2_RUE 27 1 PDAC2_SLP_IE 13 1 PDAC2_SLP_OE 12 1 PDAC2_SLP_SEL 14 1 PDAC2_XPD_DAC 18 1 PIN0 RTC_GPIO_PIN0 0x50 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN1 RTC_GPIO_PIN0 0x7C 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN10 RTC_GPIO_PIN0 0x2BC 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN11 RTC_GPIO_PIN0 0x310 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN12 RTC_GPIO_PIN0 0x368 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN13 RTC_GPIO_PIN0 0x3C4 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN14 RTC_GPIO_PIN0 0x424 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN15 RTC_GPIO_PIN0 0x488 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN16 RTC_GPIO_PIN0 0x4F0 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN17 RTC_GPIO_PIN0 0x55C 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN2 RTC_GPIO_PIN0 0xAC 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN3 RTC_GPIO_PIN0 0xE0 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN4 RTC_GPIO_PIN0 0x118 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN5 RTC_GPIO_PIN0 0x154 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN6 RTC_GPIO_PIN0 0x194 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN7 RTC_GPIO_PIN0 0x1D8 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN8 RTC_GPIO_PIN0 0x220 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 PIN9 RTC_GPIO_PIN0 0x26C 32 read-write n 0x0 0x0 INT_TYPE 7 3 PAD_DRIVER 2 1 WAKEUP_ENABLE 10 1 RTC_DEBUG_SEL RTC_IO_RTC_DEBUG_SEL 0x70 32 read-write n 0x0 0x0 DEBUG_12M_NO_GATING 25 1 DEBUG_SEL0 0 5 DEBUG_SEL1 5 5 DEBUG_SEL2 10 5 DEBUG_SEL3 15 5 DEBUG_SEL4 20 5 SAR_I2C_IO RTC_IO_SAR_I2C_IO 0xC4 32 read-write n 0x0 0x0 SAR_DEBUG_BIT_SEL 23 5 SAR_I2C_SCL_SEL 28 2 SAR_I2C_SDA_SEL 30 2 SENSOR_PADS RTC_IO_SENSOR_PADS 0x7C 32 read-write n 0x0 0x0 SENSE1_FUN_IE 19 1 SENSE1_FUN_SEL 22 2 SENSE1_HOLD 31 1 SENSE1_MUX_SEL 27 1 SENSE1_SLP_IE 20 1 SENSE1_SLP_SEL 21 1 SENSE2_FUN_IE 14 1 SENSE2_FUN_SEL 17 2 SENSE2_HOLD 30 1 SENSE2_MUX_SEL 26 1 SENSE2_SLP_IE 15 1 SENSE2_SLP_SEL 16 1 SENSE3_FUN_IE 9 1 SENSE3_FUN_SEL 12 2 SENSE3_HOLD 29 1 SENSE3_MUX_SEL 25 1 SENSE3_SLP_IE 10 1 SENSE3_SLP_SEL 11 1 SENSE4_FUN_IE 4 1 SENSE4_FUN_SEL 7 2 SENSE4_HOLD 28 1 SENSE4_MUX_SEL 24 1 SENSE4_SLP_IE 5 1 SENSE4_SLP_SEL 6 1 STATUS RTC_GPIO_STATUS 0x18 32 read-write n 0x0 0x0 STATUS_INT 14 18 STATUS_W1TC RTC_GPIO_STATUS_W1TC 0x20 32 read-write n 0x0 0x0 STATUS_INT_W1TC 14 18 STATUS_W1TS RTC_GPIO_STATUS_W1TS 0x1C 32 read-write n 0x0 0x0 STATUS_INT_W1TS 14 18 TOUCH_CFG RTC_IO_TOUCH_CFG 0x90 32 read-write n 0x0 0x0 TOUCH_DCUR 23 2 TOUCH_DRANGE 25 2 TOUCH_DREFH 29 2 TOUCH_DREFL 27 2 TOUCH_XPD_BIAS 31 1 TOUCH_PAD0 RTC_IO_TOUCH_PAD0 0x94 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD1 RTC_IO_TOUCH_PAD1 0x98 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD2 RTC_IO_TOUCH_PAD2 0x9C 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD3 RTC_IO_TOUCH_PAD3 0xA0 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD4 RTC_IO_TOUCH_PAD4 0xA4 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD5 RTC_IO_TOUCH_PAD5 0xA8 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD6 RTC_IO_TOUCH_PAD6 0xAC 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD7 RTC_IO_TOUCH_PAD7 0xB0 32 read-write n 0x0 0x0 DAC 23 3 DRV 29 2 FUN_IE 13 1 FUN_SEL 17 2 HOLD 31 1 MUX_SEL 19 1 RDE 28 1 RUE 27 1 SLP_IE 15 1 SLP_OE 14 1 SLP_SEL 16 1 START 22 1 TIE_OPT 21 1 TO_GPIO 12 1 XPD 20 1 TOUCH_PAD8 RTC_IO_TOUCH_PAD8 0xB4 32 read-write n 0x0 0x0 DAC 23 3 START 22 1 TIE_OPT 21 1 TO_GPIO 19 1 XPD 20 1 TOUCH_PAD9 RTC_IO_TOUCH_PAD9 0xB8 32 read-write n 0x0 0x0 DAC 23 3 START 22 1 TIE_OPT 21 1 TO_GPIO 19 1 XPD 20 1 XTAL_32K_PAD RTC_IO_XTAL_32K_PAD 0x8C 32 read-write n 0x0 0x0 DAC_XTAL_32K 20 2 DBIAS_XTAL_32K 1 2 DRES_XTAL_32K 3 2 X32N_DRV 30 2 X32N_FUN_IE 11 1 X32N_FUN_SEL 15 2 X32N_HOLD 29 1 X32N_MUX_SEL 18 1 X32N_RDE 28 1 X32N_RUE 27 1 X32N_SLP_IE 13 1 X32N_SLP_OE 12 1 X32N_SLP_SEL 14 1 X32P_DRV 25 2 X32P_FUN_IE 5 1 X32P_FUN_SEL 9 2 X32P_HOLD 24 1 X32P_MUX_SEL 17 1 X32P_RDE 23 1 X32P_RUE 22 1 X32P_SLP_IE 7 1 X32P_SLP_OE 6 1 X32P_SLP_SEL 8 1 XPD_XTAL_32K 19 1 XTL_EXT_CTR RTC_IO_XTL_EXT_CTR 0xC0 32 read-write n 0x0 0x0 XTL_EXT_CTR_SEL 27 5 RTCMEM0 RTCMEM0 0x0 0x0 0x0 registers n RTCMEM1 RTCMEM1 0x0 0x0 0x0 registers n RTCMEM2 RTCMEM2 0x0 0x0 0x0 registers n RTC_I2C RTC_I2C 0x0 0x0 0x160 registers n CTRL RTC_I2C_CTRL 0x4 32 read-write n 0x0 0x0 MS_MODE 4 1 RX_LSB_FIRST 7 1 SCL_FORCE_OUT 1 1 SDA_FORCE_OUT 0 1 TRANS_START 5 1 TX_LSB_FIRST 6 1 DEBUG_STATUS RTC_I2C_DEBUG_STATUS 0x8 32 read-write n 0x0 0x0 ACK_VAL 0 1 ARB_LOST 3 1 BUS_BUSY 4 1 BYTE_TRANS 6 1 MAIN_STATE 25 3 SCL_STATE 28 3 SLAVE_ADDR_MATCH 5 1 SLAVE_RW 1 1 TIMED_OUT 2 1 INT_CLR RTC_I2C_INT_CLR 0x24 32 read-write n 0x0 0x0 ARBITRATION_LOST_INT_CLR 5 1 MASTER_TRANS_COMPLETE_INT_CLR 6 1 SLAVE_TRANS_COMPLETE_INT_CLR 4 1 TIME_OUT_INT_CLR 8 1 TRANS_COMPLETE_INT_CLR 7 1 INT_RAW RTC_I2C_INT_RAW 0x20 32 read-write n 0x0 0x0 ARBITRATION_LOST_INT_RAW 4 1 MASTER_TRANS_COMPLETE_INT_RAW 5 1 SLAVE_TRANS_COMPLETE_INT_RAW 3 1 TIME_OUT_INT_RAW 7 1 TRANS_COMPLETE_INT_RAW 6 1 SCL_HIGH_PERIOD RTC_I2C_SCL_HIGH_PERIOD 0x38 32 read-write n 0x0 0x0 SCL_HIGH_PERIOD 0 20 SCL_LOW_PERIOD RTC_I2C_SCL_LOW_PERIOD 0x0 32 read-write n 0x0 0x0 SCL_LOW_PERIOD 0 19 SCL_START_PERIOD RTC_I2C_SCL_START_PERIOD 0x40 32 read-write n 0x0 0x0 SCL_START_PERIOD 0 20 SCL_STOP_PERIOD RTC_I2C_SCL_STOP_PERIOD 0x44 32 read-write n 0x0 0x0 SCL_STOP_PERIOD 0 20 SDA_DUTY RTC_I2C_SDA_DUTY 0x30 32 read-write n 0x0 0x0 SDA_DUTY 0 20 SLAVE_ADDR RTC_I2C_SLAVE_ADDR 0x10 32 read-write n 0x0 0x0 SLAVE_ADDR 0 15 SLAVE_ADDR_10BIT 31 1 TIMEOUT RTC_I2C_TIMEOUT 0xC 32 read-write n 0x0 0x0 TIMEOUT 0 20 RW_BLE RW_BLE 0x0 RWBLE_INTR interrupt of RWBLE, level 7 RWBLE_NMI interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI 9 RW_BT RW_BT 0x0 RWBT_INTR interrupt of RWBT, level 6 RWBT_NMI interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI 8 SDIO SDIO 0x0 SDIO_HOST_INTR interrupt of SD/SDIO/MMC HOST, level 37 SDMMC SDMMC 0x0 0x0 0x0 registers n SENS SENS 0x0 0x0 0x540 registers n SARDATE SENS_SARDATE 0xFC 32 read-write n 0x0 0x0 SAR_DATE 0 28 SAR_ATTEN1 SENS_SAR_ATTEN1 0x34 32 read-write n 0x0 0x0 SAR1_ATTEN 0 32 SAR_ATTEN2 SENS_SAR_ATTEN2 0x38 32 read-write n 0x0 0x0 SAR2_ATTEN 0 32 SAR_DAC_CTRL1 SENS_SAR_DAC_CTRL1 0x98 32 read-write n 0x0 0x0 DAC_CLK_FORCE_HIGH 24 1 DAC_CLK_FORCE_LOW 23 1 DAC_CLK_INV 25 1 DAC_DIG_FORCE 22 1 DEBUG_BIT_SEL 17 5 SW_FSTEP 0 16 SW_TONE_EN 16 1 SAR_DAC_CTRL2 SENS_SAR_DAC_CTRL2 0x9C 32 read-write n 0x0 0x0 DAC_CW_EN1 24 1 DAC_CW_EN2 25 1 DAC_DC1 0 8 DAC_DC2 8 8 DAC_INV1 20 2 DAC_INV2 22 2 DAC_SCALE1 16 2 DAC_SCALE2 18 2 SAR_I2C_CTRL SENS_SAR_I2C_CTRL 0x50 32 read-write n 0x0 0x0 SAR_I2C_CTRL 0 28 SAR_I2C_START 28 1 SAR_I2C_START_FORCE 29 1 SAR_MEAS_CTRL SENS_SAR_MEAS_CTRL 0x10 32 read-write n 0x0 0x0 AMP_RST_FB_FSM 4 4 AMP_SHORT_REF_FSM 8 4 AMP_SHORT_REF_GND_FSM 12 4 SAR2_XPD_WAIT 24 8 SAR_RSTB_FSM 20 4 XPD_SAR_AMP_FSM 0 4 XPD_SAR_FSM 16 4 SAR_MEAS_CTRL2 SENS_SAR_MEAS_CTRL2 0xA0 32 read-write n 0x0 0x0 AMP_RST_FB_FORCE 13 2 AMP_RST_FB_FSM_IDLE 6 1 AMP_SHORT_REF_FORCE 15 2 AMP_SHORT_REF_FSM_IDLE 7 1 AMP_SHORT_REF_GND_FORCE 17 2 AMP_SHORT_REF_GND_FSM_IDLE 8 1 SAR1_DAC_XPD_FSM 0 4 SAR1_DAC_XPD_FSM_IDLE 4 1 SAR2_RSTB_FORCE 11 2 SAR_RSTB_FSM_IDLE 10 1 XPD_SAR_AMP_FSM_IDLE 5 1 XPD_SAR_FSM_IDLE 9 1 SAR_MEAS_START1 SENS_SAR_MEAS_START1 0x54 32 read-write n 0x0 0x0 MEAS1_DATA_SAR 0 16 MEAS1_DONE_SAR 16 1 MEAS1_START_FORCE 18 1 MEAS1_START_SAR 17 1 SAR1_EN_PAD 19 12 SAR1_EN_PAD_FORCE 31 1 SAR_MEAS_START2 SENS_SAR_MEAS_START2 0x94 32 read-write n 0x0 0x0 MEAS2_DATA_SAR 0 16 MEAS2_DONE_SAR 16 1 MEAS2_START_FORCE 18 1 MEAS2_START_SAR 17 1 SAR2_EN_PAD 19 12 SAR2_EN_PAD_FORCE 31 1 SAR_MEAS_WAIT1 SENS_SAR_MEAS_WAIT1 0x8 32 read-write n 0x0 0x0 SAR_AMP_WAIT1 0 16 SAR_AMP_WAIT2 16 16 SAR_MEAS_WAIT2 SENS_SAR_MEAS_WAIT2 0xC 32 read-write n 0x0 0x0 FORCE_XPD_AMP 16 2 FORCE_XPD_SAR 18 2 SAR2_RSTB_WAIT 20 8 SAR_AMP_WAIT3 0 16 SAR_MEM_WR_CTRL SENS_SAR_MEM_WR_CTRL 0x30 32 read-write n 0x0 0x0 MEM_WR_ADDR_INIT 0 11 MEM_WR_ADDR_SIZE 11 11 RTC_MEM_WR_OFFST_CLR 22 1 SAR_NOUSE SENS_SAR_NOUSE 0xF8 32 read-write n 0x0 0x0 SAR_NOUSE 0 32 SAR_READ_CTRL SENS_SAR_READ_CTRL 0x0 32 read-write n 0x0 0x0 SAR1_CLK_DIV 0 8 SAR1_CLK_GATED 18 1 SAR1_DATA_INV 28 1 SAR1_DIG_FORCE 27 1 SAR1_SAMPLE_BIT 16 2 SAR1_SAMPLE_CYCLE 8 8 SAR1_SAMPLE_NUM 19 8 SAR_READ_CTRL2 SENS_SAR_READ_CTRL2 0x90 32 read-write n 0x0 0x0 SAR2_CLK_DIV 0 8 SAR2_CLK_GATED 18 1 SAR2_DATA_INV 29 1 SAR2_DIG_FORCE 28 1 SAR2_PWDET_FORCE 27 1 SAR2_SAMPLE_BIT 16 2 SAR2_SAMPLE_CYCLE 8 8 SAR2_SAMPLE_NUM 19 8 SAR_READ_STATUS1 SENS_SAR_READ_STATUS1 0x4 32 read-write n 0x0 0x0 SAR1_READER_STATUS 0 32 SAR_READ_STATUS2 SENS_SAR_READ_STATUS2 0x14 32 read-write n 0x0 0x0 SAR2_READER_STATUS 0 32 SAR_SLAVE_ADDR1 SENS_SAR_SLAVE_ADDR1 0x3C 32 read-write n 0x0 0x0 I2C_SLAVE_ADDR0 11 11 I2C_SLAVE_ADDR1 0 11 MEAS_STATUS 22 8 SAR_SLAVE_ADDR2 SENS_SAR_SLAVE_ADDR2 0x40 32 read-write n 0x0 0x0 I2C_SLAVE_ADDR2 11 11 I2C_SLAVE_ADDR3 0 11 SAR_SLAVE_ADDR3 SENS_SAR_SLAVE_ADDR3 0x44 32 read-write n 0x0 0x0 I2C_SLAVE_ADDR4 11 11 I2C_SLAVE_ADDR5 0 11 TSENS_OUT 22 8 TSENS_RDY_OUT 30 1 SAR_SLAVE_ADDR4 SENS_SAR_SLAVE_ADDR4 0x48 32 read-write n 0x0 0x0 I2C_DONE 30 1 I2C_RDATA 22 8 I2C_SLAVE_ADDR6 11 11 I2C_SLAVE_ADDR7 0 11 SAR_START_FORCE SENS_SAR_START_FORCE 0x2C 32 read-write n 0x0 0x0 PC_INIT 11 11 SAR1_BIT_WIDTH 0 2 SAR1_STOP 23 1 SAR2_BIT_WIDTH 2 2 SAR2_EN_TEST 4 1 SAR2_PWDET_CCT 5 3 SAR2_PWDET_EN 24 1 SAR2_STOP 22 1 SARCLK_EN 10 1 ULP_CP_FORCE_START_TOP 8 1 ULP_CP_START_TOP 9 1 SAR_TOUCH_CTRL1 SENS_SAR_TOUCH_CTRL1 0x58 32 read-write n 0x0 0x0 HALL_PHASE_FORCE 27 1 TOUCH_MEAS_DELAY 0 16 TOUCH_OUT_1EN 25 1 TOUCH_OUT_SEL 24 1 TOUCH_XPD_WAIT 16 8 XPD_HALL_FORCE 26 1 SAR_TOUCH_CTRL2 SENS_SAR_TOUCH_CTRL2 0x84 32 read-write n 0x0 0x0 TOUCH_MEAS_DONE 10 1 TOUCH_MEAS_EN 0 10 TOUCH_MEAS_EN_CLR 30 1 TOUCH_SLEEP_CYCLES 14 16 TOUCH_START_EN 12 1 TOUCH_START_FORCE 13 1 TOUCH_START_FSM_EN 11 1 SAR_TOUCH_ENABLE SENS_SAR_TOUCH_ENABLE 0x8C 32 read-write n 0x0 0x0 TOUCH_PAD_OUTEN1 20 10 TOUCH_PAD_OUTEN2 10 10 TOUCH_PAD_WORKEN 0 10 SAR_TOUCH_OUT1 SENS_SAR_TOUCH_OUT1 0x70 32 read-write n 0x0 0x0 TOUCH_MEAS_OUT0 16 16 TOUCH_MEAS_OUT1 0 16 SAR_TOUCH_OUT2 SENS_SAR_TOUCH_OUT2 0x74 32 read-write n 0x0 0x0 TOUCH_MEAS_OUT2 16 16 TOUCH_MEAS_OUT3 0 16 SAR_TOUCH_OUT3 SENS_SAR_TOUCH_OUT3 0x78 32 read-write n 0x0 0x0 TOUCH_MEAS_OUT4 16 16 TOUCH_MEAS_OUT5 0 16 SAR_TOUCH_OUT4 SENS_SAR_TOUCH_OUT4 0x7C 32 read-write n 0x0 0x0 TOUCH_MEAS_OUT6 16 16 TOUCH_MEAS_OUT7 0 16 SAR_TOUCH_OUT5 SENS_SAR_TOUCH_OUT5 0x80 32 read-write n 0x0 0x0 TOUCH_MEAS_OUT8 16 16 TOUCH_MEAS_OUT9 0 16 SAR_TOUCH_THRES1 SENS_SAR_TOUCH_THRES1 0x5C 32 read-write n 0x0 0x0 TOUCH_OUT_TH0 16 16 TOUCH_OUT_TH1 0 16 SAR_TOUCH_THRES2 SENS_SAR_TOUCH_THRES2 0x60 32 read-write n 0x0 0x0 TOUCH_OUT_TH2 16 16 TOUCH_OUT_TH3 0 16 SAR_TOUCH_THRES3 SENS_SAR_TOUCH_THRES3 0x64 32 read-write n 0x0 0x0 TOUCH_OUT_TH4 16 16 TOUCH_OUT_TH5 0 16 SAR_TOUCH_THRES4 SENS_SAR_TOUCH_THRES4 0x68 32 read-write n 0x0 0x0 TOUCH_OUT_TH6 16 16 TOUCH_OUT_TH7 0 16 SAR_TOUCH_THRES5 SENS_SAR_TOUCH_THRES5 0x6C 32 read-write n 0x0 0x0 TOUCH_OUT_TH8 16 16 TOUCH_OUT_TH9 0 16 SAR_TSENS_CTRL SENS_SAR_TSENS_CTRL 0x4C 32 read-write n 0x0 0x0 TSENS_CLK_DIV 16 8 TSENS_CLK_GATED 14 1 TSENS_CLK_INV 13 1 TSENS_DUMP_OUT 26 1 TSENS_IN_INV 15 1 TSENS_POWER_UP 24 1 TSENS_POWER_UP_FORCE 25 1 TSENS_XPD_FORCE 12 1 TSENS_XPD_WAIT 0 12 ULP_CP_SLEEP_CYC0 SENS_ULP_CP_SLEEP_CYC0 0x18 32 read-write n 0x0 0x0 SLEEP_CYCLES_S0 0 32 ULP_CP_SLEEP_CYC1 SENS_ULP_CP_SLEEP_CYC1 0x1C 32 read-write n 0x0 0x0 SLEEP_CYCLES_S1 0 32 ULP_CP_SLEEP_CYC2 SENS_ULP_CP_SLEEP_CYC2 0x20 32 read-write n 0x0 0x0 SLEEP_CYCLES_S2 0 32 ULP_CP_SLEEP_CYC3 SENS_ULP_CP_SLEEP_CYC3 0x24 32 read-write n 0x0 0x0 SLEEP_CYCLES_S3 0 32 ULP_CP_SLEEP_CYC4 SENS_ULP_CP_SLEEP_CYC4 0x28 32 read-write n 0x0 0x0 SLEEP_CYCLES_S4 0 32 SHA SHA 0x0 0x0 0x0 registers n SLC SLC 0x0 0x0 0xA60 registers n SLC0_INTR interrupt of SLC0, level 10 SLC1_INTR interrupt of SLC1, level 11 0INT_CLR SLC_0INT_CLR 0x10 32 read-write n 0x0 0x0 CMD_DTC_INT_CLR 25 1 FRHOST_BIT0_INT_CLR 0 1 FRHOST_BIT1_INT_CLR 1 1 FRHOST_BIT2_INT_CLR 2 1 FRHOST_BIT3_INT_CLR 3 1 FRHOST_BIT4_INT_CLR 4 1 FRHOST_BIT5_INT_CLR 5 1 FRHOST_BIT6_INT_CLR 6 1 FRHOST_BIT7_INT_CLR 7 1 SLC0_HOST_RD_ACK_INT_CLR 22 1 SLC0_RX_DONE_INT_CLR 16 1 SLC0_RX_DSCR_ERR_INT_CLR 20 1 SLC0_RX_EOF_INT_CLR 17 1 SLC0_RX_QUICK_EOF_INT_CLR 26 1 SLC0_RX_START_INT_CLR 8 1 SLC0_RX_UDF_INT_CLR 10 1 SLC0_TOHOST_INT_CLR 18 1 SLC0_TOKEN0_1TO0_INT_CLR 12 1 SLC0_TOKEN1_1TO0_INT_CLR 13 1 SLC0_TX_DONE_INT_CLR 14 1 SLC0_TX_DSCR_EMPTY_INT_CLR 21 1 SLC0_TX_DSCR_ERR_INT_CLR 19 1 SLC0_TX_ERR_EOF_INT_CLR 24 1 SLC0_TX_OVF_INT_CLR 11 1 SLC0_TX_START_INT_CLR 9 1 SLC0_TX_SUC_EOF_INT_CLR 15 1 SLC0_WR_RETRY_DONE_INT_CLR 23 1 0INT_ENA SLC_0INT_ENA 0xC 32 read-write n 0x0 0x0 CMD_DTC_INT_ENA 25 1 FRHOST_BIT0_INT_ENA 0 1 FRHOST_BIT1_INT_ENA 1 1 FRHOST_BIT2_INT_ENA 2 1 FRHOST_BIT3_INT_ENA 3 1 FRHOST_BIT4_INT_ENA 4 1 FRHOST_BIT5_INT_ENA 5 1 FRHOST_BIT6_INT_ENA 6 1 FRHOST_BIT7_INT_ENA 7 1 SLC0_HOST_RD_ACK_INT_ENA 22 1 SLC0_RX_DONE_INT_ENA 16 1 SLC0_RX_DSCR_ERR_INT_ENA 20 1 SLC0_RX_EOF_INT_ENA 17 1 SLC0_RX_QUICK_EOF_INT_ENA 26 1 SLC0_RX_START_INT_ENA 8 1 SLC0_RX_UDF_INT_ENA 10 1 SLC0_TOHOST_INT_ENA 18 1 SLC0_TOKEN0_1TO0_INT_ENA 12 1 SLC0_TOKEN1_1TO0_INT_ENA 13 1 SLC0_TX_DONE_INT_ENA 14 1 SLC0_TX_DSCR_EMPTY_INT_ENA 21 1 SLC0_TX_DSCR_ERR_INT_ENA 19 1 SLC0_TX_ERR_EOF_INT_ENA 24 1 SLC0_TX_OVF_INT_ENA 11 1 SLC0_TX_START_INT_ENA 9 1 SLC0_TX_SUC_EOF_INT_ENA 15 1 SLC0_WR_RETRY_DONE_INT_ENA 23 1 0INT_ENA1 SLC_0INT_ENA1 0x140 32 read-write n 0x0 0x0 CMD_DTC_INT_ENA1 25 1 FRHOST_BIT0_INT_ENA1 0 1 FRHOST_BIT1_INT_ENA1 1 1 FRHOST_BIT2_INT_ENA1 2 1 FRHOST_BIT3_INT_ENA1 3 1 FRHOST_BIT4_INT_ENA1 4 1 FRHOST_BIT5_INT_ENA1 5 1 FRHOST_BIT6_INT_ENA1 6 1 FRHOST_BIT7_INT_ENA1 7 1 SLC0_HOST_RD_ACK_INT_ENA1 22 1 SLC0_RX_DONE_INT_ENA1 16 1 SLC0_RX_DSCR_ERR_INT_ENA1 20 1 SLC0_RX_EOF_INT_ENA1 17 1 SLC0_RX_QUICK_EOF_INT_ENA1 26 1 SLC0_RX_START_INT_ENA1 8 1 SLC0_RX_UDF_INT_ENA1 10 1 SLC0_TOHOST_INT_ENA1 18 1 SLC0_TOKEN0_1TO0_INT_ENA1 12 1 SLC0_TOKEN1_1TO0_INT_ENA1 13 1 SLC0_TX_DONE_INT_ENA1 14 1 SLC0_TX_DSCR_EMPTY_INT_ENA1 21 1 SLC0_TX_DSCR_ERR_INT_ENA1 19 1 SLC0_TX_ERR_EOF_INT_ENA1 24 1 SLC0_TX_OVF_INT_ENA1 11 1 SLC0_TX_START_INT_ENA1 9 1 SLC0_TX_SUC_EOF_INT_ENA1 15 1 SLC0_WR_RETRY_DONE_INT_ENA1 23 1 0INT_RAW SLC_0INT_RAW 0x4 32 read-write n 0x0 0x0 CMD_DTC_INT_RAW 25 1 FRHOST_BIT0_INT_RAW 0 1 FRHOST_BIT1_INT_RAW 1 1 FRHOST_BIT2_INT_RAW 2 1 FRHOST_BIT3_INT_RAW 3 1 FRHOST_BIT4_INT_RAW 4 1 FRHOST_BIT5_INT_RAW 5 1 FRHOST_BIT6_INT_RAW 6 1 FRHOST_BIT7_INT_RAW 7 1 SLC0_HOST_RD_ACK_INT_RAW 22 1 SLC0_RX_DONE_INT_RAW 16 1 SLC0_RX_DSCR_ERR_INT_RAW 20 1 SLC0_RX_EOF_INT_RAW 17 1 SLC0_RX_QUICK_EOF_INT_RAW 26 1 SLC0_RX_START_INT_RAW 8 1 SLC0_RX_UDF_INT_RAW 10 1 SLC0_TOHOST_INT_RAW 18 1 SLC0_TOKEN0_1TO0_INT_RAW 12 1 SLC0_TOKEN1_1TO0_INT_RAW 13 1 SLC0_TX_DONE_INT_RAW 14 1 SLC0_TX_DSCR_EMPTY_INT_RAW 21 1 SLC0_TX_DSCR_ERR_INT_RAW 19 1 SLC0_TX_ERR_EOF_INT_RAW 24 1 SLC0_TX_OVF_INT_RAW 11 1 SLC0_TX_START_INT_RAW 9 1 SLC0_TX_SUC_EOF_INT_RAW 15 1 SLC0_WR_RETRY_DONE_INT_RAW 23 1 0INT_ST SLC_0INT_ST 0x8 32 read-write n 0x0 0x0 CMD_DTC_INT_ST 25 1 FRHOST_BIT0_INT_ST 0 1 FRHOST_BIT1_INT_ST 1 1 FRHOST_BIT2_INT_ST 2 1 FRHOST_BIT3_INT_ST 3 1 FRHOST_BIT4_INT_ST 4 1 FRHOST_BIT5_INT_ST 5 1 FRHOST_BIT6_INT_ST 6 1 FRHOST_BIT7_INT_ST 7 1 SLC0_HOST_RD_ACK_INT_ST 22 1 SLC0_RX_DONE_INT_ST 16 1 SLC0_RX_DSCR_ERR_INT_ST 20 1 SLC0_RX_EOF_INT_ST 17 1 SLC0_RX_QUICK_EOF_INT_ST 26 1 SLC0_RX_START_INT_ST 8 1 SLC0_RX_UDF_INT_ST 10 1 SLC0_TOHOST_INT_ST 18 1 SLC0_TOKEN0_1TO0_INT_ST 12 1 SLC0_TOKEN1_1TO0_INT_ST 13 1 SLC0_TX_DONE_INT_ST 14 1 SLC0_TX_DSCR_EMPTY_INT_ST 21 1 SLC0_TX_DSCR_ERR_INT_ST 19 1 SLC0_TX_ERR_EOF_INT_ST 24 1 SLC0_TX_OVF_INT_ST 11 1 SLC0_TX_START_INT_ST 9 1 SLC0_TX_SUC_EOF_INT_ST 15 1 SLC0_WR_RETRY_DONE_INT_ST 23 1 0INT_ST1 SLC_0INT_ST1 0x13C 32 read-write n 0x0 0x0 CMD_DTC_INT_ST1 25 1 FRHOST_BIT0_INT_ST1 0 1 FRHOST_BIT1_INT_ST1 1 1 FRHOST_BIT2_INT_ST1 2 1 FRHOST_BIT3_INT_ST1 3 1 FRHOST_BIT4_INT_ST1 4 1 FRHOST_BIT5_INT_ST1 5 1 FRHOST_BIT6_INT_ST1 6 1 FRHOST_BIT7_INT_ST1 7 1 SLC0_HOST_RD_ACK_INT_ST1 22 1 SLC0_RX_DONE_INT_ST1 16 1 SLC0_RX_DSCR_ERR_INT_ST1 20 1 SLC0_RX_EOF_INT_ST1 17 1 SLC0_RX_QUICK_EOF_INT_ST1 26 1 SLC0_RX_START_INT_ST1 8 1 SLC0_RX_UDF_INT_ST1 10 1 SLC0_TOHOST_INT_ST1 18 1 SLC0_TOKEN0_1TO0_INT_ST1 12 1 SLC0_TOKEN1_1TO0_INT_ST1 13 1 SLC0_TX_DONE_INT_ST1 14 1 SLC0_TX_DSCR_EMPTY_INT_ST1 21 1 SLC0_TX_DSCR_ERR_INT_ST1 19 1 SLC0_TX_ERR_EOF_INT_ST1 24 1 SLC0_TX_OVF_INT_ST1 11 1 SLC0_TX_START_INT_ST1 9 1 SLC0_TX_SUC_EOF_INT_ST1 15 1 SLC0_WR_RETRY_DONE_INT_ST1 23 1 0RXFIFO_PUSH SLC_0RXFIFO_PUSH 0x28 32 read-write n 0x0 0x0 SLC0_RXFIFO_PUSH 16 1 SLC0_RXFIFO_WDATA 0 9 0RX_LINK SLC_0RX_LINK 0x3C 32 read-write n 0x0 0x0 SLC0_RXLINK_ADDR 0 20 SLC0_RXLINK_PARK 31 1 SLC0_RXLINK_RESTART 30 1 SLC0_RXLINK_START 29 1 SLC0_RXLINK_STOP 28 1 0TOKEN0 SLC_0TOKEN0 0x50 32 read-write n 0x0 0x0 SLC0_TOKEN0 16 12 SLC0_TOKEN0_INC 13 1 SLC0_TOKEN0_INC_MORE 14 1 SLC0_TOKEN0_WDATA 0 12 SLC0_TOKEN0_WR 12 1 0TOKEN1 SLC_0TOKEN1 0x54 32 read-write n 0x0 0x0 SLC0_TOKEN1 16 12 SLC0_TOKEN1_INC 13 1 SLC0_TOKEN1_INC_MORE 14 1 SLC0_TOKEN1_WDATA 0 12 SLC0_TOKEN1_WR 12 1 0TXFIFO_POP SLC_0TXFIFO_POP 0x34 32 read-write n 0x0 0x0 SLC0_TXFIFO_POP 16 1 SLC0_TXFIFO_RDATA 0 11 0TX_LINK SLC_0TX_LINK 0x40 32 read-write n 0x0 0x0 SLC0_TXLINK_ADDR 0 20 SLC0_TXLINK_PARK 31 1 SLC0_TXLINK_RESTART 30 1 SLC0_TXLINK_START 29 1 SLC0_TXLINK_STOP 28 1 0_DONE_DSCR_ADDR SLC_0_DONE_DSCR_ADDR 0x12C 32 read-write n 0x0 0x0 SLC0_RX_DONE_DSCR_ADDR 0 32 0_DSCR_CNT SLC_0_DSCR_CNT 0x134 32 read-write n 0x0 0x0 SLC0_RX_DSCR_CNT_LAT 0 10 SLC0_RX_GET_EOF_OCC 16 1 0_DSCR_REC_CONF SLC_0_DSCR_REC_CONF 0x118 32 read-write n 0x0 0x0 SLC0_RX_DSCR_REC_LIM 0 10 0_EOF_START_DES SLC_0_EOF_START_DES 0x124 32 read-write n 0x0 0x0 SLC0_EOF_START_DES_ADDR 0 32 0_LENGTH SLC_0_LENGTH 0xE8 32 read-write n 0x0 0x0 SLC0_LEN 0 20 0_LEN_CONF SLC_0_LEN_CONF 0xE4 32 read-write n 0x0 0x0 SLC0_LEN_INC 21 1 SLC0_LEN_INC_MORE 22 1 SLC0_LEN_WDATA 0 20 SLC0_LEN_WR 20 1 SLC0_RX_GET_USED_DSCR 25 1 SLC0_RX_NEW_PKT_IND 27 1 SLC0_RX_PACKET_LOAD_EN 23 1 SLC0_TX_GET_USED_DSCR 26 1 SLC0_TX_NEW_PKT_IND 28 1 SLC0_TX_PACKET_LOAD_EN 24 1 0_LEN_LIM_CONF SLC_0_LEN_LIM_CONF 0x138 32 read-write n 0x0 0x0 SLC0_LEN_LIM 0 20 0_PUSH_DSCR_ADDR SLC_0_PUSH_DSCR_ADDR 0x128 32 read-write n 0x0 0x0 SLC0_RX_PUSH_DSCR_ADDR 0 32 0_RXLINK_DSCR SLC_0_RXLINK_DSCR 0xA8 32 read-write n 0x0 0x0 SLC0_RXLINK_DSCR 0 32 0_RXLINK_DSCR_BF0 SLC_0_RXLINK_DSCR_BF0 0xAC 32 read-write n 0x0 0x0 SLC0_RXLINK_DSCR_BF0 0 32 0_RXLINK_DSCR_BF1 SLC_0_RXLINK_DSCR_BF1 0xB0 32 read-write n 0x0 0x0 SLC0_RXLINK_DSCR_BF1 0 32 0_RXPKTU_E_DSCR SLC_0_RXPKTU_E_DSCR 0x108 32 read-write n 0x0 0x0 SLC0_RX_PKT_END_DSCR_ADDR 0 32 0_RXPKTU_H_DSCR SLC_0_RXPKTU_H_DSCR 0x104 32 read-write n 0x0 0x0 SLC0_RX_PKT_START_DSCR_ADDR 0 32 0_RXPKT_E_DSCR SLC_0_RXPKT_E_DSCR 0xF8 32 read-write n 0x0 0x0 SLC0_RX_PKT_E_DSCR_ADDR 0 32 0_RXPKT_H_DSCR SLC_0_RXPKT_H_DSCR 0xF4 32 read-write n 0x0 0x0 SLC0_RX_PKT_H_DSCR_ADDR 0 32 0_STATE0 SLC_0_STATE0 0x64 32 read-write n 0x0 0x0 SLC0_STATE0 0 32 0_STATE1 SLC_0_STATE1 0x68 32 read-write n 0x0 0x0 SLC0_STATE1 0 32 0_SUB_START_DES SLC_0_SUB_START_DES 0x130 32 read-write n 0x0 0x0 SLC0_SUB_PAC_START_DSCR_ADDR 0 32 0_TO_EOF_BFR_DES_ADDR SLC_0_TO_EOF_BFR_DES_ADDR 0x80 32 read-write n 0x0 0x0 SLC0_TO_EOF_BFR_DES_ADDR 0 32 0_TO_EOF_DES_ADDR SLC_0_TO_EOF_DES_ADDR 0x78 32 read-write n 0x0 0x0 SLC0_TO_EOF_DES_ADDR 0 32 0_TXLINK_DSCR SLC_0_TXLINK_DSCR 0x9C 32 read-write n 0x0 0x0 SLC0_TXLINK_DSCR 0 32 0_TXLINK_DSCR_BF0 SLC_0_TXLINK_DSCR_BF0 0xA0 32 read-write n 0x0 0x0 SLC0_TXLINK_DSCR_BF0 0 32 0_TXLINK_DSCR_BF1 SLC_0_TXLINK_DSCR_BF1 0xA4 32 read-write n 0x0 0x0 SLC0_TXLINK_DSCR_BF1 0 32 0_TXPKTU_E_DSCR SLC_0_TXPKTU_E_DSCR 0x100 32 read-write n 0x0 0x0 SLC0_TX_PKT_END_DSCR_ADDR 0 32 0_TXPKTU_H_DSCR SLC_0_TXPKTU_H_DSCR 0xFC 32 read-write n 0x0 0x0 SLC0_TX_PKT_START_DSCR_ADDR 0 32 0_TXPKT_E_DSCR SLC_0_TXPKT_E_DSCR 0xF0 32 read-write n 0x0 0x0 SLC0_TX_PKT_E_DSCR_ADDR 0 32 0_TXPKT_H_DSCR SLC_0_TXPKT_H_DSCR 0xEC 32 read-write n 0x0 0x0 SLC0_TX_PKT_H_DSCR_ADDR 0 32 0_TX_EOF_DES_ADDR SLC_0_TX_EOF_DES_ADDR 0x7C 32 read-write n 0x0 0x0 SLC0_TX_SUC_EOF_DES_ADDR 0 32 0_TX_ERREOF_DES_ADDR SLC_0_TX_ERREOF_DES_ADDR 0xCC 32 read-write n 0x0 0x0 SLC0_TX_ERR_EOF_DES_ADDR 0 32 1INT_CLR SLC_1INT_CLR 0x20 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_CLR 2 1 FRHOST_BIT11_INT_CLR 3 1 FRHOST_BIT12_INT_CLR 4 1 FRHOST_BIT13_INT_CLR 5 1 FRHOST_BIT14_INT_CLR 6 1 FRHOST_BIT15_INT_CLR 7 1 FRHOST_BIT8_INT_CLR 0 1 FRHOST_BIT9_INT_CLR 1 1 SLC1_HOST_RD_ACK_INT_CLR 22 1 SLC1_RX_DONE_INT_CLR 16 1 SLC1_RX_DSCR_ERR_INT_CLR 20 1 SLC1_RX_EOF_INT_CLR 17 1 SLC1_RX_START_INT_CLR 8 1 SLC1_RX_UDF_INT_CLR 10 1 SLC1_TOHOST_INT_CLR 18 1 SLC1_TOKEN0_1TO0_INT_CLR 12 1 SLC1_TOKEN1_1TO0_INT_CLR 13 1 SLC1_TX_DONE_INT_CLR 14 1 SLC1_TX_DSCR_EMPTY_INT_CLR 21 1 SLC1_TX_DSCR_ERR_INT_CLR 19 1 SLC1_TX_ERR_EOF_INT_CLR 24 1 SLC1_TX_OVF_INT_CLR 11 1 SLC1_TX_START_INT_CLR 9 1 SLC1_TX_SUC_EOF_INT_CLR 15 1 SLC1_WR_RETRY_DONE_INT_CLR 23 1 1INT_ENA SLC_1INT_ENA 0x1C 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_ENA 2 1 FRHOST_BIT11_INT_ENA 3 1 FRHOST_BIT12_INT_ENA 4 1 FRHOST_BIT13_INT_ENA 5 1 FRHOST_BIT14_INT_ENA 6 1 FRHOST_BIT15_INT_ENA 7 1 FRHOST_BIT8_INT_ENA 0 1 FRHOST_BIT9_INT_ENA 1 1 SLC1_HOST_RD_ACK_INT_ENA 22 1 SLC1_RX_DONE_INT_ENA 16 1 SLC1_RX_DSCR_ERR_INT_ENA 20 1 SLC1_RX_EOF_INT_ENA 17 1 SLC1_RX_START_INT_ENA 8 1 SLC1_RX_UDF_INT_ENA 10 1 SLC1_TOHOST_INT_ENA 18 1 SLC1_TOKEN0_1TO0_INT_ENA 12 1 SLC1_TOKEN1_1TO0_INT_ENA 13 1 SLC1_TX_DONE_INT_ENA 14 1 SLC1_TX_DSCR_EMPTY_INT_ENA 21 1 SLC1_TX_DSCR_ERR_INT_ENA 19 1 SLC1_TX_ERR_EOF_INT_ENA 24 1 SLC1_TX_OVF_INT_ENA 11 1 SLC1_TX_START_INT_ENA 9 1 SLC1_TX_SUC_EOF_INT_ENA 15 1 SLC1_WR_RETRY_DONE_INT_ENA 23 1 1INT_ENA1 SLC_1INT_ENA1 0x148 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_ENA1 2 1 FRHOST_BIT11_INT_ENA1 3 1 FRHOST_BIT12_INT_ENA1 4 1 FRHOST_BIT13_INT_ENA1 5 1 FRHOST_BIT14_INT_ENA1 6 1 FRHOST_BIT15_INT_ENA1 7 1 FRHOST_BIT8_INT_ENA1 0 1 FRHOST_BIT9_INT_ENA1 1 1 SLC1_HOST_RD_ACK_INT_ENA1 22 1 SLC1_RX_DONE_INT_ENA1 16 1 SLC1_RX_DSCR_ERR_INT_ENA1 20 1 SLC1_RX_EOF_INT_ENA1 17 1 SLC1_RX_START_INT_ENA1 8 1 SLC1_RX_UDF_INT_ENA1 10 1 SLC1_TOHOST_INT_ENA1 18 1 SLC1_TOKEN0_1TO0_INT_ENA1 12 1 SLC1_TOKEN1_1TO0_INT_ENA1 13 1 SLC1_TX_DONE_INT_ENA1 14 1 SLC1_TX_DSCR_EMPTY_INT_ENA1 21 1 SLC1_TX_DSCR_ERR_INT_ENA1 19 1 SLC1_TX_ERR_EOF_INT_ENA1 24 1 SLC1_TX_OVF_INT_ENA1 11 1 SLC1_TX_START_INT_ENA1 9 1 SLC1_TX_SUC_EOF_INT_ENA1 15 1 SLC1_WR_RETRY_DONE_INT_ENA1 23 1 1INT_RAW SLC_1INT_RAW 0x14 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_RAW 2 1 FRHOST_BIT11_INT_RAW 3 1 FRHOST_BIT12_INT_RAW 4 1 FRHOST_BIT13_INT_RAW 5 1 FRHOST_BIT14_INT_RAW 6 1 FRHOST_BIT15_INT_RAW 7 1 FRHOST_BIT8_INT_RAW 0 1 FRHOST_BIT9_INT_RAW 1 1 SLC1_HOST_RD_ACK_INT_RAW 22 1 SLC1_RX_DONE_INT_RAW 16 1 SLC1_RX_DSCR_ERR_INT_RAW 20 1 SLC1_RX_EOF_INT_RAW 17 1 SLC1_RX_START_INT_RAW 8 1 SLC1_RX_UDF_INT_RAW 10 1 SLC1_TOHOST_INT_RAW 18 1 SLC1_TOKEN0_1TO0_INT_RAW 12 1 SLC1_TOKEN1_1TO0_INT_RAW 13 1 SLC1_TX_DONE_INT_RAW 14 1 SLC1_TX_DSCR_EMPTY_INT_RAW 21 1 SLC1_TX_DSCR_ERR_INT_RAW 19 1 SLC1_TX_ERR_EOF_INT_RAW 24 1 SLC1_TX_OVF_INT_RAW 11 1 SLC1_TX_START_INT_RAW 9 1 SLC1_TX_SUC_EOF_INT_RAW 15 1 SLC1_WR_RETRY_DONE_INT_RAW 23 1 1INT_ST SLC_1INT_ST 0x18 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_ST 2 1 FRHOST_BIT11_INT_ST 3 1 FRHOST_BIT12_INT_ST 4 1 FRHOST_BIT13_INT_ST 5 1 FRHOST_BIT14_INT_ST 6 1 FRHOST_BIT15_INT_ST 7 1 FRHOST_BIT8_INT_ST 0 1 FRHOST_BIT9_INT_ST 1 1 SLC1_HOST_RD_ACK_INT_ST 22 1 SLC1_RX_DONE_INT_ST 16 1 SLC1_RX_DSCR_ERR_INT_ST 20 1 SLC1_RX_EOF_INT_ST 17 1 SLC1_RX_START_INT_ST 8 1 SLC1_RX_UDF_INT_ST 10 1 SLC1_TOHOST_INT_ST 18 1 SLC1_TOKEN0_1TO0_INT_ST 12 1 SLC1_TOKEN1_1TO0_INT_ST 13 1 SLC1_TX_DONE_INT_ST 14 1 SLC1_TX_DSCR_EMPTY_INT_ST 21 1 SLC1_TX_DSCR_ERR_INT_ST 19 1 SLC1_TX_ERR_EOF_INT_ST 24 1 SLC1_TX_OVF_INT_ST 11 1 SLC1_TX_START_INT_ST 9 1 SLC1_TX_SUC_EOF_INT_ST 15 1 SLC1_WR_RETRY_DONE_INT_ST 23 1 1INT_ST1 SLC_1INT_ST1 0x144 32 read-write n 0x0 0x0 FRHOST_BIT10_INT_ST1 2 1 FRHOST_BIT11_INT_ST1 3 1 FRHOST_BIT12_INT_ST1 4 1 FRHOST_BIT13_INT_ST1 5 1 FRHOST_BIT14_INT_ST1 6 1 FRHOST_BIT15_INT_ST1 7 1 FRHOST_BIT8_INT_ST1 0 1 FRHOST_BIT9_INT_ST1 1 1 SLC1_HOST_RD_ACK_INT_ST1 22 1 SLC1_RX_DONE_INT_ST1 16 1 SLC1_RX_DSCR_ERR_INT_ST1 20 1 SLC1_RX_EOF_INT_ST1 17 1 SLC1_RX_START_INT_ST1 8 1 SLC1_RX_UDF_INT_ST1 10 1 SLC1_TOHOST_INT_ST1 18 1 SLC1_TOKEN0_1TO0_INT_ST1 12 1 SLC1_TOKEN1_1TO0_INT_ST1 13 1 SLC1_TX_DONE_INT_ST1 14 1 SLC1_TX_DSCR_EMPTY_INT_ST1 21 1 SLC1_TX_DSCR_ERR_INT_ST1 19 1 SLC1_TX_ERR_EOF_INT_ST1 24 1 SLC1_TX_OVF_INT_ST1 11 1 SLC1_TX_START_INT_ST1 9 1 SLC1_TX_SUC_EOF_INT_ST1 15 1 SLC1_WR_RETRY_DONE_INT_ST1 23 1 1RXFIFO_PUSH SLC_1RXFIFO_PUSH 0x2C 32 read-write n 0x0 0x0 SLC1_RXFIFO_PUSH 16 1 SLC1_RXFIFO_WDATA 0 9 1RX_LINK SLC_1RX_LINK 0x44 32 read-write n 0x0 0x0 SLC1_BT_PACKET 20 1 SLC1_RXLINK_ADDR 0 20 SLC1_RXLINK_PARK 31 1 SLC1_RXLINK_RESTART 30 1 SLC1_RXLINK_START 29 1 SLC1_RXLINK_STOP 28 1 1TOKEN0 SLC_1TOKEN0 0x58 32 read-write n 0x0 0x0 SLC1_TOKEN0 16 12 SLC1_TOKEN0_INC 13 1 SLC1_TOKEN0_INC_MORE 14 1 SLC1_TOKEN0_WDATA 0 12 SLC1_TOKEN0_WR 12 1 1TOKEN1 SLC_1TOKEN1 0x5C 32 read-write n 0x0 0x0 SLC1_TOKEN1 16 12 SLC1_TOKEN1_INC 13 1 SLC1_TOKEN1_INC_MORE 14 1 SLC1_TOKEN1_WDATA 0 12 SLC1_TOKEN1_WR 12 1 1TXFIFO_POP SLC_1TXFIFO_POP 0x38 32 read-write n 0x0 0x0 SLC1_TXFIFO_POP 16 1 SLC1_TXFIFO_RDATA 0 11 1TX_LINK SLC_1TX_LINK 0x48 32 read-write n 0x0 0x0 SLC1_TXLINK_ADDR 0 20 SLC1_TXLINK_PARK 31 1 SLC1_TXLINK_RESTART 30 1 SLC1_TXLINK_START 29 1 SLC1_TXLINK_STOP 28 1 1_RXLINK_DSCR SLC_1_RXLINK_DSCR 0xC0 32 read-write n 0x0 0x0 SLC1_RXLINK_DSCR 0 32 1_RXLINK_DSCR_BF0 SLC_1_RXLINK_DSCR_BF0 0xC4 32 read-write n 0x0 0x0 SLC1_RXLINK_DSCR_BF0 0 32 1_RXLINK_DSCR_BF1 SLC_1_RXLINK_DSCR_BF1 0xC8 32 read-write n 0x0 0x0 SLC1_RXLINK_DSCR_BF1 0 32 1_STATE0 SLC_1_STATE0 0x6C 32 read-write n 0x0 0x0 SLC1_STATE0 0 32 1_STATE1 SLC_1_STATE1 0x70 32 read-write n 0x0 0x0 SLC1_STATE1 0 32 1_TO_EOF_BFR_DES_ADDR SLC_1_TO_EOF_BFR_DES_ADDR 0x8C 32 read-write n 0x0 0x0 SLC1_TO_EOF_BFR_DES_ADDR 0 32 1_TO_EOF_DES_ADDR SLC_1_TO_EOF_DES_ADDR 0x84 32 read-write n 0x0 0x0 SLC1_TO_EOF_DES_ADDR 0 32 1_TXLINK_DSCR SLC_1_TXLINK_DSCR 0xB4 32 read-write n 0x0 0x0 SLC1_TXLINK_DSCR 0 32 1_TXLINK_DSCR_BF0 SLC_1_TXLINK_DSCR_BF0 0xB8 32 read-write n 0x0 0x0 SLC1_TXLINK_DSCR_BF0 0 32 1_TXLINK_DSCR_BF1 SLC_1_TXLINK_DSCR_BF1 0xBC 32 read-write n 0x0 0x0 SLC1_TXLINK_DSCR_BF1 0 32 1_TX_EOF_DES_ADDR SLC_1_TX_EOF_DES_ADDR 0x88 32 read-write n 0x0 0x0 SLC1_TX_SUC_EOF_DES_ADDR 0 32 1_TX_ERREOF_DES_ADDR SLC_1_TX_ERREOF_DES_ADDR 0xD0 32 read-write n 0x0 0x0 SLC1_TX_ERR_EOF_DES_ADDR 0 32 AHB_TEST SLC_AHB_TEST 0x90 32 read-write n 0x0 0x0 AHB_TESTADDR 4 2 AHB_TESTMODE 0 3 BRIDGE_CONF SLC_BRIDGE_CONF 0x74 32 read-write n 0x0 0x0 FIFO_MAP_ENA 8 4 HDA_MAP_128K 13 1 SLC0_TX_DUMMY_MODE 12 1 SLC1_TX_DUMMY_MODE 14 1 TXEOF_ENA 0 6 TX_PUSH_IDLE_NUM 16 16 CMD_INFOR0 SLC_CMD_INFOR0 0xDC 32 read-write n 0x0 0x0 CMD_CONTENT0 0 32 CMD_INFOR1 SLC_CMD_INFOR1 0xE0 32 read-write n 0x0 0x0 CMD_CONTENT1 0 32 CONF0 SLC_CONF0 0x0 32 read-write n 0x0 0x0 AHBM_FIFO_RST 2 1 AHBM_RST 3 1 SLC0_RXDATA_BURST_EN 9 1 SLC0_RXDSCR_BURST_EN 8 1 SLC0_RXLINK_AUTO_RET 10 1 SLC0_RX_AUTO_WRBACK 6 1 SLC0_RX_LOOP_TEST 5 1 SLC0_RX_NO_RESTART_CLR 7 1 SLC0_RX_RST 1 1 SLC0_TOKEN_AUTO_CLR 14 1 SLC0_TOKEN_SEL 15 1 SLC0_TXDATA_BURST_EN 13 1 SLC0_TXDSCR_BURST_EN 12 1 SLC0_TXLINK_AUTO_RET 11 1 SLC0_TX_LOOP_TEST 4 1 SLC0_TX_RST 0 1 SLC0_WR_RETRY_MASK_EN 18 1 SLC1_RXDATA_BURST_EN 25 1 SLC1_RXDSCR_BURST_EN 24 1 SLC1_RXLINK_AUTO_RET 26 1 SLC1_RX_AUTO_WRBACK 22 1 SLC1_RX_LOOP_TEST 21 1 SLC1_RX_NO_RESTART_CLR 23 1 SLC1_RX_RST 17 1 SLC1_TOKEN_AUTO_CLR 30 1 SLC1_TOKEN_SEL 31 1 SLC1_TXDATA_BURST_EN 29 1 SLC1_TXDSCR_BURST_EN 28 1 SLC1_TXLINK_AUTO_RET 27 1 SLC1_TX_LOOP_TEST 20 1 SLC1_TX_RST 16 1 SLC1_WR_RETRY_MASK_EN 19 1 CONF1 SLC_CONF1 0x60 32 read-write n 0x0 0x0 CLK_EN 22 1 CMD_HOLD_EN 3 1 HOST_INT_LEVEL_SEL 19 1 SLC0_CHECK_OWNER 0 1 SLC0_LEN_AUTO_CLR 4 1 SLC0_RX_CHECK_SUM_EN 2 1 SLC0_RX_STITCH_EN 6 1 SLC0_TX_CHECK_SUM_EN 1 1 SLC0_TX_STITCH_EN 5 1 SLC1_CHECK_OWNER 16 1 SLC1_RX_CHECK_SUM_EN 18 1 SLC1_RX_STITCH_EN 21 1 SLC1_TX_CHECK_SUM_EN 17 1 SLC1_TX_STITCH_EN 20 1 DATE SLC_DATE 0x1F8 32 read-write n 0x0 0x0 DATE 0 32 ID SLC_ID 0x1FC 32 read-write n 0x0 0x0 ID 0 32 INTVEC_TOHOST SLC_INTVEC_TOHOST 0x4C 32 read-write n 0x0 0x0 SLC0_TOHOST_INTVEC 0 8 SLC1_TOHOST_INTVEC 16 8 RX_DSCR_CONF SLC_RX_DSCR_CONF 0x98 32 read-write n 0x0 0x0 SLC0_INFOR_NO_REPLACE 1 1 SLC0_RD_RETRY_THRESHOLD 5 11 SLC0_RX_EOF_MODE 3 1 SLC0_RX_FILL_EN 4 1 SLC0_RX_FILL_MODE 2 1 SLC0_TOKEN_NO_REPLACE 0 1 SLC1_INFOR_NO_REPLACE 17 1 SLC1_RD_RETRY_THRESHOLD 21 11 SLC1_RX_EOF_MODE 19 1 SLC1_RX_FILL_EN 20 1 SLC1_RX_FILL_MODE 18 1 SLC1_TOKEN_NO_REPLACE 16 1 RX_STATUS SLC_RX_STATUS 0x24 32 read-write n 0x0 0x0 SLC0_RX_EMPTY 1 1 SLC0_RX_FULL 0 1 SLC1_RX_EMPTY 17 1 SLC1_RX_FULL 16 1 SDIO_CRC_ST0 SLC_SDIO_CRC_ST0 0x11C 32 read-write n 0x0 0x0 DAT0_CRC_ERR_CNT 0 8 DAT1_CRC_ERR_CNT 8 8 DAT2_CRC_ERR_CNT 16 8 DAT3_CRC_ERR_CNT 24 8 SDIO_CRC_ST1 SLC_SDIO_CRC_ST1 0x120 32 read-write n 0x0 0x0 CMD_CRC_ERR_CNT 0 8 ERR_CNT_CLR 31 1 SDIO_ST SLC_SDIO_ST 0x94 32 read-write n 0x0 0x0 BUS_ST 12 3 CMD_ST 0 3 FUNC1_ACC_STATE 16 5 FUNC2_ACC_STATE 24 5 FUNC_ST 4 4 SDIO_WAKEUP 8 1 SEQ_POSITION SLC_SEQ_POSITION 0x114 32 read-write n 0x0 0x0 SLC0_SEQ_POSITION 0 8 SLC1_SEQ_POSITION 8 8 TOKEN_LAT SLC_TOKEN_LAT 0xD4 32 read-write n 0x0 0x0 SLC0_TOKEN 0 12 SLC1_TOKEN 16 12 TX_DSCR_CONF SLC_TX_DSCR_CONF 0xD8 32 read-write n 0x0 0x0 WR_RETRY_THRESHOLD 0 11 TX_STATUS SLC_TX_STATUS 0x30 32 read-write n 0x0 0x0 SLC0_TX_EMPTY 1 1 SLC0_TX_FULL 0 1 SLC1_TX_EMPTY 17 1 SLC1_TX_FULL 16 1 SLCHOST SLCHOST 0x0 0x0 0x800 registers n HOST_SLC0HOST_FUNC1_INT_ENA HOST_SLC0HOST_FUNC1_INT_ENA 0xDC 32 read-write n 0x0 0x0 HOST_FN1_GPIO_SDIO_INT_ENA 25 1 HOST_FN1_SLC0HOST_RX_EOF_INT_ENA 13 1 HOST_FN1_SLC0HOST_RX_SOF_INT_ENA 12 1 HOST_FN1_SLC0HOST_RX_START_INT_ENA 14 1 HOST_FN1_SLC0HOST_TX_START_INT_ENA 15 1 HOST_FN1_SLC0_EXT_BIT0_INT_ENA 19 1 HOST_FN1_SLC0_EXT_BIT1_INT_ENA 20 1 HOST_FN1_SLC0_EXT_BIT2_INT_ENA 21 1 HOST_FN1_SLC0_EXT_BIT3_INT_ENA 22 1 HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA 24 1 HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA 23 1 HOST_FN1_SLC0_RX_PF_VALID_INT_ENA 18 1 HOST_FN1_SLC0_RX_UDF_INT_ENA 16 1 HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA 0 1 HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA 1 1 HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA 2 1 HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA 3 1 HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA 4 1 HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA 5 1 HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA 6 1 HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA 7 1 HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA 10 1 HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA 8 1 HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA 11 1 HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA 9 1 HOST_FN1_SLC0_TX_OVF_INT_ENA 17 1 HOST_SLC0HOST_FUNC2_INT_ENA HOST_SLC0HOST_FUNC2_INT_ENA 0xE4 32 read-write n 0x0 0x0 HOST_FN2_GPIO_SDIO_INT_ENA 25 1 HOST_FN2_SLC0HOST_RX_EOF_INT_ENA 13 1 HOST_FN2_SLC0HOST_RX_SOF_INT_ENA 12 1 HOST_FN2_SLC0HOST_RX_START_INT_ENA 14 1 HOST_FN2_SLC0HOST_TX_START_INT_ENA 15 1 HOST_FN2_SLC0_EXT_BIT0_INT_ENA 19 1 HOST_FN2_SLC0_EXT_BIT1_INT_ENA 20 1 HOST_FN2_SLC0_EXT_BIT2_INT_ENA 21 1 HOST_FN2_SLC0_EXT_BIT3_INT_ENA 22 1 HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA 24 1 HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA 23 1 HOST_FN2_SLC0_RX_PF_VALID_INT_ENA 18 1 HOST_FN2_SLC0_RX_UDF_INT_ENA 16 1 HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA 0 1 HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA 1 1 HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA 2 1 HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA 3 1 HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA 4 1 HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA 5 1 HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA 6 1 HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA 7 1 HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA 10 1 HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA 8 1 HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA 11 1 HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA 9 1 HOST_FN2_SLC0_TX_OVF_INT_ENA 17 1 HOST_SLC0HOST_INT_CLR HOST_SLC0HOST_INT_CLR 0xD4 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT_CLR 25 1 HOST_SLC0HOST_RX_EOF_INT_CLR 13 1 HOST_SLC0HOST_RX_SOF_INT_CLR 12 1 HOST_SLC0HOST_RX_START_INT_CLR 14 1 HOST_SLC0HOST_TX_START_INT_CLR 15 1 HOST_SLC0_EXT_BIT0_INT_CLR 19 1 HOST_SLC0_EXT_BIT1_INT_CLR 20 1 HOST_SLC0_EXT_BIT2_INT_CLR 21 1 HOST_SLC0_EXT_BIT3_INT_CLR 22 1 HOST_SLC0_HOST_RD_RETRY_INT_CLR 24 1 HOST_SLC0_RX_NEW_PACKET_INT_CLR 23 1 HOST_SLC0_RX_PF_VALID_INT_CLR 18 1 HOST_SLC0_RX_UDF_INT_CLR 16 1 HOST_SLC0_TOHOST_BIT0_INT_CLR 0 1 HOST_SLC0_TOHOST_BIT1_INT_CLR 1 1 HOST_SLC0_TOHOST_BIT2_INT_CLR 2 1 HOST_SLC0_TOHOST_BIT3_INT_CLR 3 1 HOST_SLC0_TOHOST_BIT4_INT_CLR 4 1 HOST_SLC0_TOHOST_BIT5_INT_CLR 5 1 HOST_SLC0_TOHOST_BIT6_INT_CLR 6 1 HOST_SLC0_TOHOST_BIT7_INT_CLR 7 1 HOST_SLC0_TOKEN0_0TO1_INT_CLR 10 1 HOST_SLC0_TOKEN0_1TO0_INT_CLR 8 1 HOST_SLC0_TOKEN1_0TO1_INT_CLR 11 1 HOST_SLC0_TOKEN1_1TO0_INT_CLR 9 1 HOST_SLC0_TX_OVF_INT_CLR 17 1 HOST_SLC0HOST_INT_ENA HOST_SLC0HOST_INT_ENA 0xEC 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT_ENA 25 1 HOST_SLC0HOST_RX_EOF_INT_ENA 13 1 HOST_SLC0HOST_RX_SOF_INT_ENA 12 1 HOST_SLC0HOST_RX_START_INT_ENA 14 1 HOST_SLC0HOST_TX_START_INT_ENA 15 1 HOST_SLC0_EXT_BIT0_INT_ENA 19 1 HOST_SLC0_EXT_BIT1_INT_ENA 20 1 HOST_SLC0_EXT_BIT2_INT_ENA 21 1 HOST_SLC0_EXT_BIT3_INT_ENA 22 1 HOST_SLC0_HOST_RD_RETRY_INT_ENA 24 1 HOST_SLC0_RX_NEW_PACKET_INT_ENA 23 1 HOST_SLC0_RX_PF_VALID_INT_ENA 18 1 HOST_SLC0_RX_UDF_INT_ENA 16 1 HOST_SLC0_TOHOST_BIT0_INT_ENA 0 1 HOST_SLC0_TOHOST_BIT1_INT_ENA 1 1 HOST_SLC0_TOHOST_BIT2_INT_ENA 2 1 HOST_SLC0_TOHOST_BIT3_INT_ENA 3 1 HOST_SLC0_TOHOST_BIT4_INT_ENA 4 1 HOST_SLC0_TOHOST_BIT5_INT_ENA 5 1 HOST_SLC0_TOHOST_BIT6_INT_ENA 6 1 HOST_SLC0_TOHOST_BIT7_INT_ENA 7 1 HOST_SLC0_TOKEN0_0TO1_INT_ENA 10 1 HOST_SLC0_TOKEN0_1TO0_INT_ENA 8 1 HOST_SLC0_TOKEN1_0TO1_INT_ENA 11 1 HOST_SLC0_TOKEN1_1TO0_INT_ENA 9 1 HOST_SLC0_TX_OVF_INT_ENA 17 1 HOST_SLC0HOST_INT_ENA1 HOST_SLC0HOST_INT_ENA1 0x114 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT_ENA1 25 1 HOST_SLC0HOST_RX_EOF_INT_ENA1 13 1 HOST_SLC0HOST_RX_SOF_INT_ENA1 12 1 HOST_SLC0HOST_RX_START_INT_ENA1 14 1 HOST_SLC0HOST_TX_START_INT_ENA1 15 1 HOST_SLC0_EXT_BIT0_INT_ENA1 19 1 HOST_SLC0_EXT_BIT1_INT_ENA1 20 1 HOST_SLC0_EXT_BIT2_INT_ENA1 21 1 HOST_SLC0_EXT_BIT3_INT_ENA1 22 1 HOST_SLC0_HOST_RD_RETRY_INT_ENA1 24 1 HOST_SLC0_RX_NEW_PACKET_INT_ENA1 23 1 HOST_SLC0_RX_PF_VALID_INT_ENA1 18 1 HOST_SLC0_RX_UDF_INT_ENA1 16 1 HOST_SLC0_TOHOST_BIT0_INT_ENA1 0 1 HOST_SLC0_TOHOST_BIT1_INT_ENA1 1 1 HOST_SLC0_TOHOST_BIT2_INT_ENA1 2 1 HOST_SLC0_TOHOST_BIT3_INT_ENA1 3 1 HOST_SLC0_TOHOST_BIT4_INT_ENA1 4 1 HOST_SLC0_TOHOST_BIT5_INT_ENA1 5 1 HOST_SLC0_TOHOST_BIT6_INT_ENA1 6 1 HOST_SLC0_TOHOST_BIT7_INT_ENA1 7 1 HOST_SLC0_TOKEN0_0TO1_INT_ENA1 10 1 HOST_SLC0_TOKEN0_1TO0_INT_ENA1 8 1 HOST_SLC0_TOKEN1_0TO1_INT_ENA1 11 1 HOST_SLC0_TOKEN1_1TO0_INT_ENA1 9 1 HOST_SLC0_TX_OVF_INT_ENA1 17 1 HOST_SLC0HOST_INT_RAW HOST_SLC0HOST_INT_RAW 0x50 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT_RAW 25 1 HOST_SLC0HOST_RX_EOF_INT_RAW 13 1 HOST_SLC0HOST_RX_SOF_INT_RAW 12 1 HOST_SLC0HOST_RX_START_INT_RAW 14 1 HOST_SLC0HOST_TX_START_INT_RAW 15 1 HOST_SLC0_EXT_BIT0_INT_RAW 19 1 HOST_SLC0_EXT_BIT1_INT_RAW 20 1 HOST_SLC0_EXT_BIT2_INT_RAW 21 1 HOST_SLC0_EXT_BIT3_INT_RAW 22 1 HOST_SLC0_HOST_RD_RETRY_INT_RAW 24 1 HOST_SLC0_RX_NEW_PACKET_INT_RAW 23 1 HOST_SLC0_RX_PF_VALID_INT_RAW 18 1 HOST_SLC0_RX_UDF_INT_RAW 16 1 HOST_SLC0_TOHOST_BIT0_INT_RAW 0 1 HOST_SLC0_TOHOST_BIT1_INT_RAW 1 1 HOST_SLC0_TOHOST_BIT2_INT_RAW 2 1 HOST_SLC0_TOHOST_BIT3_INT_RAW 3 1 HOST_SLC0_TOHOST_BIT4_INT_RAW 4 1 HOST_SLC0_TOHOST_BIT5_INT_RAW 5 1 HOST_SLC0_TOHOST_BIT6_INT_RAW 6 1 HOST_SLC0_TOHOST_BIT7_INT_RAW 7 1 HOST_SLC0_TOKEN0_0TO1_INT_RAW 10 1 HOST_SLC0_TOKEN0_1TO0_INT_RAW 8 1 HOST_SLC0_TOKEN1_0TO1_INT_RAW 11 1 HOST_SLC0_TOKEN1_1TO0_INT_RAW 9 1 HOST_SLC0_TX_OVF_INT_RAW 17 1 HOST_SLC0HOST_INT_ST HOST_SLC0HOST_INT_ST 0x58 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT_ST 25 1 HOST_SLC0HOST_RX_EOF_INT_ST 13 1 HOST_SLC0HOST_RX_SOF_INT_ST 12 1 HOST_SLC0HOST_RX_START_INT_ST 14 1 HOST_SLC0HOST_TX_START_INT_ST 15 1 HOST_SLC0_EXT_BIT0_INT_ST 19 1 HOST_SLC0_EXT_BIT1_INT_ST 20 1 HOST_SLC0_EXT_BIT2_INT_ST 21 1 HOST_SLC0_EXT_BIT3_INT_ST 22 1 HOST_SLC0_HOST_RD_RETRY_INT_ST 24 1 HOST_SLC0_RX_NEW_PACKET_INT_ST 23 1 HOST_SLC0_RX_PF_VALID_INT_ST 18 1 HOST_SLC0_RX_UDF_INT_ST 16 1 HOST_SLC0_TOHOST_BIT0_INT_ST 0 1 HOST_SLC0_TOHOST_BIT1_INT_ST 1 1 HOST_SLC0_TOHOST_BIT2_INT_ST 2 1 HOST_SLC0_TOHOST_BIT3_INT_ST 3 1 HOST_SLC0_TOHOST_BIT4_INT_ST 4 1 HOST_SLC0_TOHOST_BIT5_INT_ST 5 1 HOST_SLC0_TOHOST_BIT6_INT_ST 6 1 HOST_SLC0_TOHOST_BIT7_INT_ST 7 1 HOST_SLC0_TOKEN0_0TO1_INT_ST 10 1 HOST_SLC0_TOKEN0_1TO0_INT_ST 8 1 HOST_SLC0_TOKEN1_0TO1_INT_ST 11 1 HOST_SLC0_TOKEN1_1TO0_INT_ST 9 1 HOST_SLC0_TX_OVF_INT_ST 17 1 HOST_SLC0HOST_LEN_WD HOST_SLC0HOST_LEN_WD 0xFC 32 read-write n 0x0 0x0 HOST_SLC0HOST_LEN_WD 0 32 HOST_SLC0HOST_RX_INFOR HOST_SLC0HOST_RX_INFOR 0xF4 32 read-write n 0x0 0x0 HOST_SLC0HOST_RX_INFOR 0 20 HOST_SLC0HOST_TOKEN_RDATA HOST_SLC0HOST_TOKEN_RDATA 0x44 32 read-write n 0x0 0x0 HOST_HOSTSLC0_TOKEN1 16 12 HOST_SLC0_RX_PF_EOF 28 4 HOST_SLC0_RX_PF_VALID 12 1 HOST_SLC0_TOKEN0 0 12 HOST_SLC0HOST_TOKEN_WDATA HOST_SLC0HOST_TOKEN_WDATA 0xC8 32 read-write n 0x0 0x0 HOST_SLC0HOST_TOKEN0_WD 0 12 HOST_SLC0HOST_TOKEN1_WD 16 12 HOST_SLC0_HOST_PF HOST_SLC0_HOST_PF 0x48 32 read-write n 0x0 0x0 HOST_SLC0_PF_DATA 0 32 HOST_SLC1HOST_FUNC1_INT_ENA HOST_SLC1HOST_FUNC1_INT_ENA 0xE0 32 read-write n 0x0 0x0 HOST_FN1_SLC1HOST_RX_EOF_INT_ENA 13 1 HOST_FN1_SLC1HOST_RX_SOF_INT_ENA 12 1 HOST_FN1_SLC1HOST_RX_START_INT_ENA 14 1 HOST_FN1_SLC1HOST_TX_START_INT_ENA 15 1 HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 HOST_FN1_SLC1_EXT_BIT0_INT_ENA 19 1 HOST_FN1_SLC1_EXT_BIT1_INT_ENA 20 1 HOST_FN1_SLC1_EXT_BIT2_INT_ENA 21 1 HOST_FN1_SLC1_EXT_BIT3_INT_ENA 22 1 HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA 24 1 HOST_FN1_SLC1_RX_PF_VALID_INT_ENA 18 1 HOST_FN1_SLC1_RX_UDF_INT_ENA 16 1 HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA 0 1 HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA 1 1 HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA 2 1 HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA 3 1 HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA 4 1 HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA 5 1 HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA 6 1 HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA 7 1 HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA 10 1 HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA 8 1 HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA 11 1 HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA 9 1 HOST_FN1_SLC1_TX_OVF_INT_ENA 17 1 HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 HOST_SLC1HOST_FUNC2_INT_ENA HOST_SLC1HOST_FUNC2_INT_ENA 0xE8 32 read-write n 0x0 0x0 HOST_FN2_SLC1HOST_RX_EOF_INT_ENA 13 1 HOST_FN2_SLC1HOST_RX_SOF_INT_ENA 12 1 HOST_FN2_SLC1HOST_RX_START_INT_ENA 14 1 HOST_FN2_SLC1HOST_TX_START_INT_ENA 15 1 HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 HOST_FN2_SLC1_EXT_BIT0_INT_ENA 19 1 HOST_FN2_SLC1_EXT_BIT1_INT_ENA 20 1 HOST_FN2_SLC1_EXT_BIT2_INT_ENA 21 1 HOST_FN2_SLC1_EXT_BIT3_INT_ENA 22 1 HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA 24 1 HOST_FN2_SLC1_RX_PF_VALID_INT_ENA 18 1 HOST_FN2_SLC1_RX_UDF_INT_ENA 16 1 HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA 0 1 HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA 1 1 HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA 2 1 HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA 3 1 HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA 4 1 HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA 5 1 HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA 6 1 HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA 7 1 HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA 10 1 HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA 8 1 HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA 11 1 HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA 9 1 HOST_FN2_SLC1_TX_OVF_INT_ENA 17 1 HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 HOST_SLC1HOST_INT_CLR HOST_SLC1HOST_INT_CLR 0xD8 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_EOF_INT_CLR 13 1 HOST_SLC1HOST_RX_SOF_INT_CLR 12 1 HOST_SLC1HOST_RX_START_INT_CLR 14 1 HOST_SLC1HOST_TX_START_INT_CLR 15 1 HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR 25 1 HOST_SLC1_EXT_BIT0_INT_CLR 19 1 HOST_SLC1_EXT_BIT1_INT_CLR 20 1 HOST_SLC1_EXT_BIT2_INT_CLR 21 1 HOST_SLC1_EXT_BIT3_INT_CLR 22 1 HOST_SLC1_HOST_RD_RETRY_INT_CLR 24 1 HOST_SLC1_RX_PF_VALID_INT_CLR 18 1 HOST_SLC1_RX_UDF_INT_CLR 16 1 HOST_SLC1_TOHOST_BIT0_INT_CLR 0 1 HOST_SLC1_TOHOST_BIT1_INT_CLR 1 1 HOST_SLC1_TOHOST_BIT2_INT_CLR 2 1 HOST_SLC1_TOHOST_BIT3_INT_CLR 3 1 HOST_SLC1_TOHOST_BIT4_INT_CLR 4 1 HOST_SLC1_TOHOST_BIT5_INT_CLR 5 1 HOST_SLC1_TOHOST_BIT6_INT_CLR 6 1 HOST_SLC1_TOHOST_BIT7_INT_CLR 7 1 HOST_SLC1_TOKEN0_0TO1_INT_CLR 10 1 HOST_SLC1_TOKEN0_1TO0_INT_CLR 8 1 HOST_SLC1_TOKEN1_0TO1_INT_CLR 11 1 HOST_SLC1_TOKEN1_1TO0_INT_CLR 9 1 HOST_SLC1_TX_OVF_INT_CLR 17 1 HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR 23 1 HOST_SLC1HOST_INT_ENA HOST_SLC1HOST_INT_ENA 0xF0 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_EOF_INT_ENA 13 1 HOST_SLC1HOST_RX_SOF_INT_ENA 12 1 HOST_SLC1HOST_RX_START_INT_ENA 14 1 HOST_SLC1HOST_TX_START_INT_ENA 15 1 HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 HOST_SLC1_EXT_BIT0_INT_ENA 19 1 HOST_SLC1_EXT_BIT1_INT_ENA 20 1 HOST_SLC1_EXT_BIT2_INT_ENA 21 1 HOST_SLC1_EXT_BIT3_INT_ENA 22 1 HOST_SLC1_HOST_RD_RETRY_INT_ENA 24 1 HOST_SLC1_RX_PF_VALID_INT_ENA 18 1 HOST_SLC1_RX_UDF_INT_ENA 16 1 HOST_SLC1_TOHOST_BIT0_INT_ENA 0 1 HOST_SLC1_TOHOST_BIT1_INT_ENA 1 1 HOST_SLC1_TOHOST_BIT2_INT_ENA 2 1 HOST_SLC1_TOHOST_BIT3_INT_ENA 3 1 HOST_SLC1_TOHOST_BIT4_INT_ENA 4 1 HOST_SLC1_TOHOST_BIT5_INT_ENA 5 1 HOST_SLC1_TOHOST_BIT6_INT_ENA 6 1 HOST_SLC1_TOHOST_BIT7_INT_ENA 7 1 HOST_SLC1_TOKEN0_0TO1_INT_ENA 10 1 HOST_SLC1_TOKEN0_1TO0_INT_ENA 8 1 HOST_SLC1_TOKEN1_0TO1_INT_ENA 11 1 HOST_SLC1_TOKEN1_1TO0_INT_ENA 9 1 HOST_SLC1_TX_OVF_INT_ENA 17 1 HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 HOST_SLC1HOST_INT_ENA1 HOST_SLC1HOST_INT_ENA1 0x118 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_EOF_INT_ENA1 13 1 HOST_SLC1HOST_RX_SOF_INT_ENA1 12 1 HOST_SLC1HOST_RX_START_INT_ENA1 14 1 HOST_SLC1HOST_TX_START_INT_ENA1 15 1 HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 25 1 HOST_SLC1_EXT_BIT0_INT_ENA1 19 1 HOST_SLC1_EXT_BIT1_INT_ENA1 20 1 HOST_SLC1_EXT_BIT2_INT_ENA1 21 1 HOST_SLC1_EXT_BIT3_INT_ENA1 22 1 HOST_SLC1_HOST_RD_RETRY_INT_ENA1 24 1 HOST_SLC1_RX_PF_VALID_INT_ENA1 18 1 HOST_SLC1_RX_UDF_INT_ENA1 16 1 HOST_SLC1_TOHOST_BIT0_INT_ENA1 0 1 HOST_SLC1_TOHOST_BIT1_INT_ENA1 1 1 HOST_SLC1_TOHOST_BIT2_INT_ENA1 2 1 HOST_SLC1_TOHOST_BIT3_INT_ENA1 3 1 HOST_SLC1_TOHOST_BIT4_INT_ENA1 4 1 HOST_SLC1_TOHOST_BIT5_INT_ENA1 5 1 HOST_SLC1_TOHOST_BIT6_INT_ENA1 6 1 HOST_SLC1_TOHOST_BIT7_INT_ENA1 7 1 HOST_SLC1_TOKEN0_0TO1_INT_ENA1 10 1 HOST_SLC1_TOKEN0_1TO0_INT_ENA1 8 1 HOST_SLC1_TOKEN1_0TO1_INT_ENA1 11 1 HOST_SLC1_TOKEN1_1TO0_INT_ENA1 9 1 HOST_SLC1_TX_OVF_INT_ENA1 17 1 HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 23 1 HOST_SLC1HOST_INT_RAW HOST_SLC1HOST_INT_RAW 0x54 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_EOF_INT_RAW 13 1 HOST_SLC1HOST_RX_SOF_INT_RAW 12 1 HOST_SLC1HOST_RX_START_INT_RAW 14 1 HOST_SLC1HOST_TX_START_INT_RAW 15 1 HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW 25 1 HOST_SLC1_EXT_BIT0_INT_RAW 19 1 HOST_SLC1_EXT_BIT1_INT_RAW 20 1 HOST_SLC1_EXT_BIT2_INT_RAW 21 1 HOST_SLC1_EXT_BIT3_INT_RAW 22 1 HOST_SLC1_HOST_RD_RETRY_INT_RAW 24 1 HOST_SLC1_RX_PF_VALID_INT_RAW 18 1 HOST_SLC1_RX_UDF_INT_RAW 16 1 HOST_SLC1_TOHOST_BIT0_INT_RAW 0 1 HOST_SLC1_TOHOST_BIT1_INT_RAW 1 1 HOST_SLC1_TOHOST_BIT2_INT_RAW 2 1 HOST_SLC1_TOHOST_BIT3_INT_RAW 3 1 HOST_SLC1_TOHOST_BIT4_INT_RAW 4 1 HOST_SLC1_TOHOST_BIT5_INT_RAW 5 1 HOST_SLC1_TOHOST_BIT6_INT_RAW 6 1 HOST_SLC1_TOHOST_BIT7_INT_RAW 7 1 HOST_SLC1_TOKEN0_0TO1_INT_RAW 10 1 HOST_SLC1_TOKEN0_1TO0_INT_RAW 8 1 HOST_SLC1_TOKEN1_0TO1_INT_RAW 11 1 HOST_SLC1_TOKEN1_1TO0_INT_RAW 9 1 HOST_SLC1_TX_OVF_INT_RAW 17 1 HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW 23 1 HOST_SLC1HOST_INT_ST HOST_SLC1HOST_INT_ST 0x5C 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_EOF_INT_ST 13 1 HOST_SLC1HOST_RX_SOF_INT_ST 12 1 HOST_SLC1HOST_RX_START_INT_ST 14 1 HOST_SLC1HOST_TX_START_INT_ST 15 1 HOST_SLC1_BT_RX_NEW_PACKET_INT_ST 25 1 HOST_SLC1_EXT_BIT0_INT_ST 19 1 HOST_SLC1_EXT_BIT1_INT_ST 20 1 HOST_SLC1_EXT_BIT2_INT_ST 21 1 HOST_SLC1_EXT_BIT3_INT_ST 22 1 HOST_SLC1_HOST_RD_RETRY_INT_ST 24 1 HOST_SLC1_RX_PF_VALID_INT_ST 18 1 HOST_SLC1_RX_UDF_INT_ST 16 1 HOST_SLC1_TOHOST_BIT0_INT_ST 0 1 HOST_SLC1_TOHOST_BIT1_INT_ST 1 1 HOST_SLC1_TOHOST_BIT2_INT_ST 2 1 HOST_SLC1_TOHOST_BIT3_INT_ST 3 1 HOST_SLC1_TOHOST_BIT4_INT_ST 4 1 HOST_SLC1_TOHOST_BIT5_INT_ST 5 1 HOST_SLC1_TOHOST_BIT6_INT_ST 6 1 HOST_SLC1_TOHOST_BIT7_INT_ST 7 1 HOST_SLC1_TOKEN0_0TO1_INT_ST 10 1 HOST_SLC1_TOKEN0_1TO0_INT_ST 8 1 HOST_SLC1_TOKEN1_0TO1_INT_ST 11 1 HOST_SLC1_TOKEN1_1TO0_INT_ST 9 1 HOST_SLC1_TX_OVF_INT_ST 17 1 HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST 23 1 HOST_SLC1HOST_RX_INFOR HOST_SLC1HOST_RX_INFOR 0xF8 32 read-write n 0x0 0x0 HOST_SLC1HOST_RX_INFOR 0 20 HOST_SLC1HOST_TOKEN_RDATA HOST_SLC1HOST_TOKEN_RDATA 0xC4 32 read-write n 0x0 0x0 HOST_HOSTSLC1_TOKEN1 16 12 HOST_SLC1_RX_PF_EOF 28 4 HOST_SLC1_RX_PF_VALID 12 1 HOST_SLC1_TOKEN0 0 12 HOST_SLC1HOST_TOKEN_WDATA HOST_SLC1HOST_TOKEN_WDATA 0xCC 32 read-write n 0x0 0x0 HOST_SLC1HOST_TOKEN0_WD 0 12 HOST_SLC1HOST_TOKEN1_WD 16 12 HOST_SLC1_HOST_PF HOST_SLC1_HOST_PF 0x4C 32 read-write n 0x0 0x0 HOST_SLC1_PF_DATA 0 32 HOST_SLCHOSTDATE HOST_SLCHOSTDATE 0x178 32 read-write n 0x0 0x0 HOST_SLCHOST_DATE 0 32 HOST_SLCHOSTID HOST_SLCHOSTID 0x17C 32 read-write n 0x0 0x0 HOST_SLCHOST_ID 0 32 HOST_SLCHOST_CHECK_SUM0 HOST_SLCHOST_CHECK_SUM0 0xBC 32 read-write n 0x0 0x0 HOST_SLCHOST_CHECK_SUM0 0 32 HOST_SLCHOST_CHECK_SUM1 HOST_SLCHOST_CHECK_SUM1 0xC0 32 read-write n 0x0 0x0 HOST_SLCHOST_CHECK_SUM1 0 32 HOST_SLCHOST_CONF HOST_SLCHOST_CONF 0x1F0 32 read-write n 0x0 0x0 HOST_FRC_NEG_SAMP 10 5 HOST_FRC_POS_SAMP 15 5 HOST_FRC_QUICK_IN 20 5 HOST_FRC_SDIO11 0 5 HOST_FRC_SDIO20 5 5 HOST_HSPEED_CON_EN 27 1 HOST_SDIO20_INT_DELAY 25 1 HOST_SDIO_PAD_PULLUP 26 1 HOST_SLCHOST_CONF_W0 HOST_SLCHOST_CONF_W0 0x6C 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF0 0 8 HOST_SLCHOST_CONF1 8 8 HOST_SLCHOST_CONF2 16 8 HOST_SLCHOST_CONF3 24 8 HOST_SLCHOST_CONF_W1 HOST_SLCHOST_CONF_W1 0x70 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF4 0 8 HOST_SLCHOST_CONF5 8 8 HOST_SLCHOST_CONF6 16 8 HOST_SLCHOST_CONF7 24 8 HOST_SLCHOST_CONF_W10 HOST_SLCHOST_CONF_W10 0xA4 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF40 0 8 HOST_SLCHOST_CONF41 8 8 HOST_SLCHOST_CONF42 16 8 HOST_SLCHOST_CONF43 24 8 HOST_SLCHOST_CONF_W11 HOST_SLCHOST_CONF_W11 0xA8 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF44 0 8 HOST_SLCHOST_CONF45 8 8 HOST_SLCHOST_CONF46 16 8 HOST_SLCHOST_CONF47 24 8 HOST_SLCHOST_CONF_W12 HOST_SLCHOST_CONF_W12 0xAC 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF48 0 8 HOST_SLCHOST_CONF49 8 8 HOST_SLCHOST_CONF50 16 8 HOST_SLCHOST_CONF51 24 8 HOST_SLCHOST_CONF_W13 HOST_SLCHOST_CONF_W13 0xB0 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF52 0 8 HOST_SLCHOST_CONF53 8 8 HOST_SLCHOST_CONF54 16 8 HOST_SLCHOST_CONF55 24 8 HOST_SLCHOST_CONF_W14 HOST_SLCHOST_CONF_W14 0xB4 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF56 0 8 HOST_SLCHOST_CONF57 8 8 HOST_SLCHOST_CONF58 16 8 HOST_SLCHOST_CONF59 24 8 HOST_SLCHOST_CONF_W15 HOST_SLCHOST_CONF_W15 0xB8 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF60 0 8 HOST_SLCHOST_CONF61 8 8 HOST_SLCHOST_CONF62 16 8 HOST_SLCHOST_CONF63 24 8 HOST_SLCHOST_CONF_W2 HOST_SLCHOST_CONF_W2 0x74 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF10 16 8 HOST_SLCHOST_CONF11 24 8 HOST_SLCHOST_CONF8 0 8 HOST_SLCHOST_CONF9 8 8 HOST_SLCHOST_CONF_W3 HOST_SLCHOST_CONF_W3 0x78 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF12 0 8 HOST_SLCHOST_CONF13 8 8 HOST_SLCHOST_CONF14 16 8 HOST_SLCHOST_CONF15 24 8 HOST_SLCHOST_CONF_W4 HOST_SLCHOST_CONF_W4 0x7C 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF16 0 8 HOST_SLCHOST_CONF17 8 8 HOST_SLCHOST_CONF18 16 8 HOST_SLCHOST_CONF19 24 8 HOST_SLCHOST_CONF_W5 HOST_SLCHOST_CONF_W5 0x80 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF20 0 8 HOST_SLCHOST_CONF21 8 8 HOST_SLCHOST_CONF22 16 8 HOST_SLCHOST_CONF23 24 8 HOST_SLCHOST_CONF_W6 HOST_SLCHOST_CONF_W6 0x88 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF24 0 8 HOST_SLCHOST_CONF25 8 8 HOST_SLCHOST_CONF26 16 8 HOST_SLCHOST_CONF27 24 8 HOST_SLCHOST_CONF_W7 HOST_SLCHOST_CONF_W7 0x8C 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF28 0 8 HOST_SLCHOST_CONF29 8 8 HOST_SLCHOST_CONF30 16 8 HOST_SLCHOST_CONF31 24 8 HOST_SLCHOST_CONF_W8 HOST_SLCHOST_CONF_W8 0x9C 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF32 0 8 HOST_SLCHOST_CONF33 8 8 HOST_SLCHOST_CONF34 16 8 HOST_SLCHOST_CONF35 24 8 HOST_SLCHOST_CONF_W9 HOST_SLCHOST_CONF_W9 0xA0 32 read-write n 0x0 0x0 HOST_SLCHOST_CONF36 0 8 HOST_SLCHOST_CONF37 8 8 HOST_SLCHOST_CONF38 16 8 HOST_SLCHOST_CONF39 24 8 HOST_SLCHOST_FUNC2_0 HOST_SLCHOST_FUNC2_0 0x10 32 read-write n 0x0 0x0 HOST_SLC_FUNC2_INT 24 1 HOST_SLCHOST_FUNC2_1 HOST_SLCHOST_FUNC2_1 0x14 32 read-write n 0x0 0x0 HOST_SLC_FUNC2_INT_EN 0 1 HOST_SLCHOST_FUNC2_2 HOST_SLCHOST_FUNC2_2 0x20 32 read-write n 0x0 0x0 HOST_SLC_FUNC1_MDSTAT 0 1 HOST_SLCHOST_GPIO_IN0 HOST_SLCHOST_GPIO_IN0 0x3C 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_IN0 0 32 HOST_SLCHOST_GPIO_IN1 HOST_SLCHOST_GPIO_IN1 0x40 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_IN1 0 8 HOST_SLCHOST_GPIO_STATUS0 HOST_SLCHOST_GPIO_STATUS0 0x34 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT0 0 32 HOST_SLCHOST_GPIO_STATUS1 HOST_SLCHOST_GPIO_STATUS1 0x38 32 read-write n 0x0 0x0 HOST_GPIO_SDIO_INT1 0 8 HOST_SLCHOST_INF_ST HOST_SLCHOST_INF_ST 0x1F4 32 read-write n 0x0 0x0 HOST_SDIO20_MODE 0 5 HOST_SDIO_NEG_SAMP 5 5 HOST_SDIO_QUICK_IN 10 5 HOST_SLCHOST_PKT_LEN HOST_SLCHOST_PKT_LEN 0x60 32 read-write n 0x0 0x0 HOST_HOSTSLC0_LEN 0 20 HOST_HOSTSLC0_LEN_CHECK 20 12 HOST_SLCHOST_PKT_LEN0 HOST_SLCHOST_PKT_LEN0 0x90 32 read-write n 0x0 0x0 HOST_HOSTSLC0_LEN0 0 20 HOST_SLCHOST_PKT_LEN1 HOST_SLCHOST_PKT_LEN1 0x94 32 read-write n 0x0 0x0 HOST_HOSTSLC0_LEN1 0 20 HOST_SLCHOST_PKT_LEN2 HOST_SLCHOST_PKT_LEN2 0x98 32 read-write n 0x0 0x0 HOST_HOSTSLC0_LEN2 0 20 HOST_SLCHOST_RDCLR0 HOST_SLCHOST_RDCLR0 0x10C 32 read-write n 0x0 0x0 HOST_SLCHOST_SLC0_BIT6_CLRADDR 9 9 HOST_SLCHOST_SLC0_BIT7_CLRADDR 0 9 HOST_SLCHOST_RDCLR1 HOST_SLCHOST_RDCLR1 0x110 32 read-write n 0x0 0x0 HOST_SLCHOST_SLC1_BIT6_CLRADDR 9 9 HOST_SLCHOST_SLC1_BIT7_CLRADDR 0 9 HOST_SLCHOST_STATE_W0 HOST_SLCHOST_STATE_W0 0x64 32 read-write n 0x0 0x0 HOST_SLCHOST_STATE0 0 8 HOST_SLCHOST_STATE1 8 8 HOST_SLCHOST_STATE2 16 8 HOST_SLCHOST_STATE3 24 8 HOST_SLCHOST_STATE_W1 HOST_SLCHOST_STATE_W1 0x68 32 read-write n 0x0 0x0 HOST_SLCHOST_STATE4 0 8 HOST_SLCHOST_STATE5 8 8 HOST_SLCHOST_STATE6 16 8 HOST_SLCHOST_STATE7 24 8 HOST_SLCHOST_TOKEN_CON HOST_SLCHOST_TOKEN_CON 0xD0 32 read-write n 0x0 0x0 HOST_SLC0HOST_LEN_WR 8 1 HOST_SLC0HOST_TOKEN0_DEC 0 1 HOST_SLC0HOST_TOKEN0_WR 2 1 HOST_SLC0HOST_TOKEN1_DEC 1 1 HOST_SLC0HOST_TOKEN1_WR 3 1 HOST_SLC1HOST_TOKEN0_DEC 4 1 HOST_SLC1HOST_TOKEN0_WR 6 1 HOST_SLC1HOST_TOKEN1_DEC 5 1 HOST_SLC1HOST_TOKEN1_WR 7 1 HOST_SLC_APBWIN_CONF HOST_SLC_APBWIN_CONF 0x104 32 read-write n 0x0 0x0 HOST_SLC_APBWIN_ADDR 0 28 HOST_SLC_APBWIN_START 29 1 HOST_SLC_APBWIN_WR 28 1 HOST_SLC_APBWIN_RDATA HOST_SLC_APBWIN_RDATA 0x108 32 read-write n 0x0 0x0 HOST_SLC_APBWIN_RDATA 0 32 HOST_SLC_APBWIN_WDATA HOST_SLC_APBWIN_WDATA 0x100 32 read-write n 0x0 0x0 HOST_SLC_APBWIN_WDATA 0 32 SPI SPI 0x0 0x0 0x860 registers n SPI1_DMA_INTR interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this 52 SPI2_DMA_INTR interrupt of SPI2 DMA, level 53 SPI3_DMA_INTR interrupt of SPI3 DMA, level 54 CACHE_FCTRL SPI_CACHE_FCTRL 0x50 32 read-write n 0x0 0x0 CACHE_FLASH_PES_EN 3 1 CACHE_FLASH_USR_CMD 2 1 CACHE_REQ_EN 0 1 CACHE_USR_CMD_4BYTE 1 1 CACHE_SCTRL SPI_CACHE_SCTRL 0x54 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RCMD 5 1 CACHE_SRAM_USR_WCMD 28 1 SRAM_ADDR_BITLEN 22 6 SRAM_BYTES_LEN 6 8 SRAM_DUMMY_CYCLELEN 14 8 USR_RD_SRAM_DUMMY 4 1 USR_SRAM_DIO 1 1 USR_SRAM_QIO 2 1 USR_WR_SRAM_DUMMY 3 1 CLOCK SPI_CLOCK 0x18 32 read-write n 0x0 0x0 CLKCNT_H 6 6 CLKCNT_L 0 6 CLKCNT_N 12 6 CLKDIV_PRE 18 13 CLK_EQU_SYSCLK 31 1 CMD SPI_CMD 0x0 32 read-write n 0x0 0x0 FLASH_BE 23 1 FLASH_CE 22 1 FLASH_DP 21 1 FLASH_HPM 19 1 FLASH_PER 16 1 FLASH_PES 17 1 FLASH_PP 25 1 FLASH_RDID 28 1 FLASH_RDSR 27 1 FLASH_READ 31 1 FLASH_RES 20 1 FLASH_SE 24 1 FLASH_WRDI 29 1 FLASH_WREN 30 1 FLASH_WRSR 26 1 USR 18 1 CTRL SPI_CTRL 0x8 32 read-write n 0x0 0x0 FASTRD_MODE 13 1 FCS_CRC_EN 10 1 FREAD_DIO 23 1 FREAD_DUAL 14 1 FREAD_QIO 24 1 FREAD_QUAD 20 1 RD_BIT_ORDER 25 1 RESANDRES 15 1 TX_CRC_EN 11 1 WAIT_FLASH_IDLE_EN 12 1 WP_REG 21 1 WRSR_2B 22 1 WR_BIT_ORDER 26 1 CTRL1 SPI_CTRL1 0xC 32 read-write n 0x0 0x0 CS_HOLD_DELAY 28 4 CS_HOLD_DELAY_RES 16 12 CTRL2 SPI_CTRL2 0x14 32 read-write n 0x0 0x0 CK_OUT_HIGH_MODE 12 4 CK_OUT_LOW_MODE 8 4 CS_DELAY_MODE 26 2 CS_DELAY_NUM 28 4 HOLD_TIME 4 4 MISO_DELAY_MODE 16 2 MISO_DELAY_NUM 18 3 MOSI_DELAY_MODE 21 2 MOSI_DELAY_NUM 23 3 SETUP_TIME 0 4 DATE SPI_DATE 0x3FC 32 read-write n 0x0 0x0 DATE 0 28 DMA_CONF SPI_DMA_CONF 0x100 32 read-write n 0x0 0x0 AHBM_FIFO_RST 4 1 AHBM_RST 5 1 DMA_CONTINUE 16 1 DMA_RX_STOP 14 1 DMA_TX_STOP 15 1 INDSCR_BURST_EN 11 1 IN_LOOP_TEST 6 1 IN_RST 2 1 OUTDSCR_BURST_EN 10 1 OUT_AUTO_WRBACK 8 1 OUT_DATA_BURST_EN 12 1 OUT_EOF_MODE 9 1 OUT_LOOP_TEST 7 1 OUT_RST 3 1 DMA_INT_CLR SPI_DMA_INT_CLR 0x11C 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_CLR 0 1 INLINK_DSCR_ERROR_INT_CLR 2 1 IN_DONE_INT_CLR 3 1 IN_ERR_EOF_INT_CLR 4 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_DSCR_ERROR_INT_CLR 1 1 OUT_DONE_INT_CLR 6 1 OUT_EOF_INT_CLR 7 1 OUT_TOTAL_EOF_INT_CLR 8 1 DMA_INT_ENA SPI_DMA_INT_ENA 0x110 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ENA 0 1 INLINK_DSCR_ERROR_INT_ENA 2 1 IN_DONE_INT_ENA 3 1 IN_ERR_EOF_INT_ENA 4 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_DSCR_ERROR_INT_ENA 1 1 OUT_DONE_INT_ENA 6 1 OUT_EOF_INT_ENA 7 1 OUT_TOTAL_EOF_INT_ENA 8 1 DMA_INT_RAW SPI_DMA_INT_RAW 0x114 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_RAW 0 1 INLINK_DSCR_ERROR_INT_RAW 2 1 IN_DONE_INT_RAW 3 1 IN_ERR_EOF_INT_RAW 4 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_DSCR_ERROR_INT_RAW 1 1 OUT_DONE_INT_RAW 6 1 OUT_EOF_INT_RAW 7 1 OUT_TOTAL_EOF_INT_RAW 8 1 DMA_INT_ST SPI_DMA_INT_ST 0x118 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ST 0 1 INLINK_DSCR_ERROR_INT_ST 2 1 IN_DONE_INT_ST 3 1 IN_ERR_EOF_INT_ST 4 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_DSCR_ERROR_INT_ST 1 1 OUT_DONE_INT_ST 6 1 OUT_EOF_INT_ST 7 1 OUT_TOTAL_EOF_INT_ST 8 1 DMA_IN_LINK SPI_DMA_IN_LINK 0x108 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_OUT_LINK SPI_DMA_OUT_LINK 0x104 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_RSTATUS SPI_DMA_RSTATUS 0x148 32 read-write n 0x0 0x0 DMA_OUT_STATUS 0 32 DMA_STATUS SPI_DMA_STATUS 0x10C 32 read-write n 0x0 0x0 DMA_RX_EN 0 1 DMA_TX_EN 1 1 DMA_TSTATUS SPI_DMA_TSTATUS 0x14C 32 read-write n 0x0 0x0 DMA_IN_STATUS 0 32 EXT0 SPI_EXT0 0xF0 32 read-write n 0x0 0x0 T_PP_ENA 31 1 T_PP_SHIFT 16 4 T_PP_TIME 0 12 EXT1 SPI_EXT1 0xF4 32 read-write n 0x0 0x0 T_ERASE_ENA 31 1 T_ERASE_SHIFT 16 4 T_ERASE_TIME 0 12 EXT2 SPI_EXT2 0xF8 32 read-write n 0x0 0x0 ST 0 3 EXT3 SPI_EXT3 0xFC 32 read-write n 0x0 0x0 INT_HOLD_ENA 0 2 INLINK_DSCR SPI_INLINK_DSCR 0x128 32 read-write n 0x0 0x0 DMA_INLINK_DSCR 0 32 INLINK_DSCR_BF0 SPI_INLINK_DSCR_BF0 0x12C 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 SPI_INLINK_DSCR_BF1 0x130 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF1 0 32 IN_ERR_EOF_DES_ADDR SPI_IN_ERR_EOF_DES_ADDR 0x120 32 read-write n 0x0 0x0 DMA_IN_ERR_EOF_DES_ADDR 0 32 IN_SUC_EOF_DES_ADDR SPI_IN_SUC_EOF_DES_ADDR 0x124 32 read-write n 0x0 0x0 DMA_IN_SUC_EOF_DES_ADDR 0 32 MISO_DLEN SPI_MISO_DLEN 0x2C 32 read-write n 0x0 0x0 USR_MISO_DBITLEN 0 24 MOSI_DLEN SPI_MOSI_DLEN 0x28 32 read-write n 0x0 0x0 USR_MOSI_DBITLEN 0 24 OUTLINK_DSCR SPI_OUTLINK_DSCR 0x13C 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 SPI_OUTLINK_DSCR_BF0 0x140 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 SPI_OUTLINK_DSCR_BF1 0x144 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR SPI_OUT_EOF_BFR_DES_ADDR 0x134 32 read-write n 0x0 0x0 DMA_OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR SPI_OUT_EOF_DES_ADDR 0x138 32 read-write n 0x0 0x0 DMA_OUT_EOF_DES_ADDR 0 32 PIN SPI_PIN 0x34 32 read-write n 0x0 0x0 CK_DIS 5 1 CK_IDLE_EDGE 29 1 CS0_DIS 0 1 CS1_DIS 1 1 CS2_DIS 2 1 CS_KEEP_ACTIVE 30 1 MASTER_CK_SEL 11 3 MASTER_CS_POL 6 3 RD_STATUS SPI_RD_STATUS 0x10 32 read-write n 0x0 0x0 STATUS 0 16 STATUS_EXT 24 8 WB_MODE 16 8 SLAVE SPI_SLAVE 0x38 32 read-write n 0x0 0x0 CS_I_MODE 10 2 INT_EN 5 5 SLAVE_MODE 30 1 SLV_CMD_DEFINE 27 1 SLV_LAST_COMMAND 17 3 SLV_LAST_STATE 20 3 SLV_RD_BUF_DONE 0 1 SLV_RD_STA_DONE 2 1 SLV_WR_BUF_DONE 1 1 SLV_WR_RD_BUF_EN 29 1 SLV_WR_RD_STA_EN 28 1 SLV_WR_STA_DONE 3 1 SYNC_RESET 31 1 TRANS_CNT 23 4 TRANS_DONE 4 1 SLAVE1 SPI_SLAVE1 0x3C 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_EN 0 1 SLV_RDSTA_DUMMY_EN 2 1 SLV_RD_ADDR_BITLEN 10 6 SLV_STATUS_BITLEN 27 5 SLV_STATUS_FAST_EN 26 1 SLV_STATUS_READBACK 25 1 SLV_WRBUF_DUMMY_EN 1 1 SLV_WRSTA_DUMMY_EN 3 1 SLV_WR_ADDR_BITLEN 4 6 SLAVE2 SPI_SLAVE2 0x40 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_CYCLELEN 16 8 SLV_RDSTA_DUMMY_CYCLELEN 0 8 SLV_WRBUF_DUMMY_CYCLELEN 24 8 SLV_WRSTA_DUMMY_CYCLELEN 8 8 SLAVE3 SPI_SLAVE3 0x44 32 read-write n 0x0 0x0 SLV_RDBUF_CMD_VALUE 0 8 SLV_RDSTA_CMD_VALUE 16 8 SLV_WRBUF_CMD_VALUE 8 8 SLV_WRSTA_CMD_VALUE 24 8 SLV_RDBUF_DLEN SPI_SLV_RDBUF_DLEN 0x4C 32 read-write n 0x0 0x0 SLV_RDBUF_DBITLEN 0 24 SLV_RD_BIT SPI_SLV_RD_BIT 0x64 32 read-write n 0x0 0x0 SLV_RDATA_BIT 0 24 SLV_WRBUF_DLEN SPI_SLV_WRBUF_DLEN 0x48 32 read-write n 0x0 0x0 SLV_WRBUF_DBITLEN 0 24 SLV_WR_STATUS SPI_SLV_WR_STATUS 0x30 32 read-write n 0x0 0x0 SLV_WR_ST 0 32 SRAM_CMD SPI_SRAM_CMD 0x58 32 read-write n 0x0 0x0 SRAM_DIO 0 1 SRAM_QIO 1 1 SRAM_RSTIO 4 1 SRAM_DRD_CMD SPI_SRAM_DRD_CMD 0x5C 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RD_CMD_BITLEN 28 4 CACHE_SRAM_USR_RD_CMD_VALUE 0 16 SRAM_DWR_CMD SPI_SRAM_DWR_CMD 0x60 32 read-write n 0x0 0x0 CACHE_SRAM_USR_WR_CMD_BITLEN 28 4 CACHE_SRAM_USR_WR_CMD_VALUE 0 16 TX_CRC SPI_TX_CRC 0xC0 32 read-write n 0x0 0x0 TX_CRC_DATA 0 32 USER SPI_USER 0x1C 32 read-write n 0x0 0x0 CK_I_EDGE 6 1 CK_OUT_EDGE 7 1 CS_HOLD 4 1 CS_SETUP 5 1 DOUTDIN 0 1 FWRITE_DIO 14 1 FWRITE_DUAL 12 1 FWRITE_QIO 15 1 FWRITE_QUAD 13 1 RD_BYTE_ORDER 10 1 SIO 16 1 USR_ADDR 30 1 USR_ADDR_HOLD 21 1 USR_CMD_HOLD 22 1 USR_COMMAND 31 1 USR_DIN_HOLD 19 1 USR_DOUT_HOLD 18 1 USR_DUMMY 29 1 USR_DUMMY_HOLD 20 1 USR_DUMMY_IDLE 26 1 USR_HOLD_POL 17 1 USR_MISO 28 1 USR_MISO_HIGHPART 24 1 USR_MOSI 27 1 USR_MOSI_HIGHPART 25 1 USR_PREP_HOLD 23 1 WR_BYTE_ORDER 11 1 USER1 SPI_USER1 0x20 32 read-write n 0x0 0x0 USR_ADDR_BITLEN 26 6 USR_DUMMY_CYCLELEN 0 8 USER2 SPI_USER2 0x24 32 read-write n 0x0 0x0 USR_COMMAND_BITLEN 28 4 USR_COMMAND_VALUE 0 16 W0 SPI_W0 0x100 32 read-write n 0x0 0x0 BUF 0 32 W1 SPI_W0 0x184 32 read-write n 0x0 0x0 BUF 0 32 W10 SPI_W0 0x6DC 32 read-write n 0x0 0x0 BUF 0 32 W11 SPI_W0 0x788 32 read-write n 0x0 0x0 BUF 0 32 W12 SPI_W0 0x838 32 read-write n 0x0 0x0 BUF 0 32 W13 SPI_W0 0x8EC 32 read-write n 0x0 0x0 BUF 0 32 W14 SPI_W0 0x9A4 32 read-write n 0x0 0x0 BUF 0 32 W15 SPI_W0 0xA60 32 read-write n 0x0 0x0 BUF 0 32 W2 SPI_W0 0x20C 32 read-write n 0x0 0x0 BUF 0 32 W3 SPI_W0 0x298 32 read-write n 0x0 0x0 BUF 0 32 W4 SPI_W0 0x328 32 read-write n 0x0 0x0 BUF 0 32 W5 SPI_W0 0x3BC 32 read-write n 0x0 0x0 BUF 0 32 W6 SPI_W0 0x454 32 read-write n 0x0 0x0 BUF 0 32 W7 SPI_W0 0x4F0 32 read-write n 0x0 0x0 BUF 0 32 W8 SPI_W0 0x590 32 read-write n 0x0 0x0 BUF 0 32 W9 SPI_W0 0x634 32 read-write n 0x0 0x0 BUF 0 32 SPI0 SPI 0x0 0x0 0x860 registers n CACHE_FCTRL SPI_CACHE_FCTRL 0x50 32 read-write n 0x0 0x0 CACHE_FLASH_PES_EN 3 1 CACHE_FLASH_USR_CMD 2 1 CACHE_REQ_EN 0 1 CACHE_USR_CMD_4BYTE 1 1 CACHE_SCTRL SPI_CACHE_SCTRL 0x54 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RCMD 5 1 CACHE_SRAM_USR_WCMD 28 1 SRAM_ADDR_BITLEN 22 6 SRAM_BYTES_LEN 6 8 SRAM_DUMMY_CYCLELEN 14 8 USR_RD_SRAM_DUMMY 4 1 USR_SRAM_DIO 1 1 USR_SRAM_QIO 2 1 USR_WR_SRAM_DUMMY 3 1 CLOCK SPI_CLOCK 0x18 32 read-write n 0x0 0x0 CLKCNT_H 6 6 CLKCNT_L 0 6 CLKCNT_N 12 6 CLKDIV_PRE 18 13 CLK_EQU_SYSCLK 31 1 CMD SPI_CMD 0x0 32 read-write n 0x0 0x0 FLASH_BE 23 1 FLASH_CE 22 1 FLASH_DP 21 1 FLASH_HPM 19 1 FLASH_PER 16 1 FLASH_PES 17 1 FLASH_PP 25 1 FLASH_RDID 28 1 FLASH_RDSR 27 1 FLASH_READ 31 1 FLASH_RES 20 1 FLASH_SE 24 1 FLASH_WRDI 29 1 FLASH_WREN 30 1 FLASH_WRSR 26 1 USR 18 1 CTRL SPI_CTRL 0x8 32 read-write n 0x0 0x0 FASTRD_MODE 13 1 FCS_CRC_EN 10 1 FREAD_DIO 23 1 FREAD_DUAL 14 1 FREAD_QIO 24 1 FREAD_QUAD 20 1 RD_BIT_ORDER 25 1 RESANDRES 15 1 TX_CRC_EN 11 1 WAIT_FLASH_IDLE_EN 12 1 WP_REG 21 1 WRSR_2B 22 1 WR_BIT_ORDER 26 1 CTRL1 SPI_CTRL1 0xC 32 read-write n 0x0 0x0 CS_HOLD_DELAY 28 4 CS_HOLD_DELAY_RES 16 12 CTRL2 SPI_CTRL2 0x14 32 read-write n 0x0 0x0 CK_OUT_HIGH_MODE 12 4 CK_OUT_LOW_MODE 8 4 CS_DELAY_MODE 26 2 CS_DELAY_NUM 28 4 HOLD_TIME 4 4 MISO_DELAY_MODE 16 2 MISO_DELAY_NUM 18 3 MOSI_DELAY_MODE 21 2 MOSI_DELAY_NUM 23 3 SETUP_TIME 0 4 DATE SPI_DATE 0x3FC 32 read-write n 0x0 0x0 DATE 0 28 DMA_CONF SPI_DMA_CONF 0x100 32 read-write n 0x0 0x0 AHBM_FIFO_RST 4 1 AHBM_RST 5 1 DMA_CONTINUE 16 1 DMA_RX_STOP 14 1 DMA_TX_STOP 15 1 INDSCR_BURST_EN 11 1 IN_LOOP_TEST 6 1 IN_RST 2 1 OUTDSCR_BURST_EN 10 1 OUT_AUTO_WRBACK 8 1 OUT_DATA_BURST_EN 12 1 OUT_EOF_MODE 9 1 OUT_LOOP_TEST 7 1 OUT_RST 3 1 DMA_INT_CLR SPI_DMA_INT_CLR 0x11C 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_CLR 0 1 INLINK_DSCR_ERROR_INT_CLR 2 1 IN_DONE_INT_CLR 3 1 IN_ERR_EOF_INT_CLR 4 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_DSCR_ERROR_INT_CLR 1 1 OUT_DONE_INT_CLR 6 1 OUT_EOF_INT_CLR 7 1 OUT_TOTAL_EOF_INT_CLR 8 1 DMA_INT_ENA SPI_DMA_INT_ENA 0x110 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ENA 0 1 INLINK_DSCR_ERROR_INT_ENA 2 1 IN_DONE_INT_ENA 3 1 IN_ERR_EOF_INT_ENA 4 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_DSCR_ERROR_INT_ENA 1 1 OUT_DONE_INT_ENA 6 1 OUT_EOF_INT_ENA 7 1 OUT_TOTAL_EOF_INT_ENA 8 1 DMA_INT_RAW SPI_DMA_INT_RAW 0x114 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_RAW 0 1 INLINK_DSCR_ERROR_INT_RAW 2 1 IN_DONE_INT_RAW 3 1 IN_ERR_EOF_INT_RAW 4 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_DSCR_ERROR_INT_RAW 1 1 OUT_DONE_INT_RAW 6 1 OUT_EOF_INT_RAW 7 1 OUT_TOTAL_EOF_INT_RAW 8 1 DMA_INT_ST SPI_DMA_INT_ST 0x118 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ST 0 1 INLINK_DSCR_ERROR_INT_ST 2 1 IN_DONE_INT_ST 3 1 IN_ERR_EOF_INT_ST 4 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_DSCR_ERROR_INT_ST 1 1 OUT_DONE_INT_ST 6 1 OUT_EOF_INT_ST 7 1 OUT_TOTAL_EOF_INT_ST 8 1 DMA_IN_LINK SPI_DMA_IN_LINK 0x108 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_OUT_LINK SPI_DMA_OUT_LINK 0x104 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_RSTATUS SPI_DMA_RSTATUS 0x148 32 read-write n 0x0 0x0 DMA_OUT_STATUS 0 32 DMA_STATUS SPI_DMA_STATUS 0x10C 32 read-write n 0x0 0x0 DMA_RX_EN 0 1 DMA_TX_EN 1 1 DMA_TSTATUS SPI_DMA_TSTATUS 0x14C 32 read-write n 0x0 0x0 DMA_IN_STATUS 0 32 EXT0 SPI_EXT0 0xF0 32 read-write n 0x0 0x0 T_PP_ENA 31 1 T_PP_SHIFT 16 4 T_PP_TIME 0 12 EXT1 SPI_EXT1 0xF4 32 read-write n 0x0 0x0 T_ERASE_ENA 31 1 T_ERASE_SHIFT 16 4 T_ERASE_TIME 0 12 EXT2 SPI_EXT2 0xF8 32 read-write n 0x0 0x0 ST 0 3 EXT3 SPI_EXT3 0xFC 32 read-write n 0x0 0x0 INT_HOLD_ENA 0 2 INLINK_DSCR SPI_INLINK_DSCR 0x128 32 read-write n 0x0 0x0 DMA_INLINK_DSCR 0 32 INLINK_DSCR_BF0 SPI_INLINK_DSCR_BF0 0x12C 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 SPI_INLINK_DSCR_BF1 0x130 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF1 0 32 IN_ERR_EOF_DES_ADDR SPI_IN_ERR_EOF_DES_ADDR 0x120 32 read-write n 0x0 0x0 DMA_IN_ERR_EOF_DES_ADDR 0 32 IN_SUC_EOF_DES_ADDR SPI_IN_SUC_EOF_DES_ADDR 0x124 32 read-write n 0x0 0x0 DMA_IN_SUC_EOF_DES_ADDR 0 32 MISO_DLEN SPI_MISO_DLEN 0x2C 32 read-write n 0x0 0x0 USR_MISO_DBITLEN 0 24 MOSI_DLEN SPI_MOSI_DLEN 0x28 32 read-write n 0x0 0x0 USR_MOSI_DBITLEN 0 24 OUTLINK_DSCR SPI_OUTLINK_DSCR 0x13C 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 SPI_OUTLINK_DSCR_BF0 0x140 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 SPI_OUTLINK_DSCR_BF1 0x144 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR SPI_OUT_EOF_BFR_DES_ADDR 0x134 32 read-write n 0x0 0x0 DMA_OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR SPI_OUT_EOF_DES_ADDR 0x138 32 read-write n 0x0 0x0 DMA_OUT_EOF_DES_ADDR 0 32 PIN SPI_PIN 0x34 32 read-write n 0x0 0x0 CK_DIS 5 1 CK_IDLE_EDGE 29 1 CS0_DIS 0 1 CS1_DIS 1 1 CS2_DIS 2 1 CS_KEEP_ACTIVE 30 1 MASTER_CK_SEL 11 3 MASTER_CS_POL 6 3 RD_STATUS SPI_RD_STATUS 0x10 32 read-write n 0x0 0x0 STATUS 0 16 STATUS_EXT 24 8 WB_MODE 16 8 SLAVE SPI_SLAVE 0x38 32 read-write n 0x0 0x0 CS_I_MODE 10 2 INT_EN 5 5 SLAVE_MODE 30 1 SLV_CMD_DEFINE 27 1 SLV_LAST_COMMAND 17 3 SLV_LAST_STATE 20 3 SLV_RD_BUF_DONE 0 1 SLV_RD_STA_DONE 2 1 SLV_WR_BUF_DONE 1 1 SLV_WR_RD_BUF_EN 29 1 SLV_WR_RD_STA_EN 28 1 SLV_WR_STA_DONE 3 1 SYNC_RESET 31 1 TRANS_CNT 23 4 TRANS_DONE 4 1 SLAVE1 SPI_SLAVE1 0x3C 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_EN 0 1 SLV_RDSTA_DUMMY_EN 2 1 SLV_RD_ADDR_BITLEN 10 6 SLV_STATUS_BITLEN 27 5 SLV_STATUS_FAST_EN 26 1 SLV_STATUS_READBACK 25 1 SLV_WRBUF_DUMMY_EN 1 1 SLV_WRSTA_DUMMY_EN 3 1 SLV_WR_ADDR_BITLEN 4 6 SLAVE2 SPI_SLAVE2 0x40 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_CYCLELEN 16 8 SLV_RDSTA_DUMMY_CYCLELEN 0 8 SLV_WRBUF_DUMMY_CYCLELEN 24 8 SLV_WRSTA_DUMMY_CYCLELEN 8 8 SLAVE3 SPI_SLAVE3 0x44 32 read-write n 0x0 0x0 SLV_RDBUF_CMD_VALUE 0 8 SLV_RDSTA_CMD_VALUE 16 8 SLV_WRBUF_CMD_VALUE 8 8 SLV_WRSTA_CMD_VALUE 24 8 SLV_RDBUF_DLEN SPI_SLV_RDBUF_DLEN 0x4C 32 read-write n 0x0 0x0 SLV_RDBUF_DBITLEN 0 24 SLV_RD_BIT SPI_SLV_RD_BIT 0x64 32 read-write n 0x0 0x0 SLV_RDATA_BIT 0 24 SLV_WRBUF_DLEN SPI_SLV_WRBUF_DLEN 0x48 32 read-write n 0x0 0x0 SLV_WRBUF_DBITLEN 0 24 SLV_WR_STATUS SPI_SLV_WR_STATUS 0x30 32 read-write n 0x0 0x0 SLV_WR_ST 0 32 SRAM_CMD SPI_SRAM_CMD 0x58 32 read-write n 0x0 0x0 SRAM_DIO 0 1 SRAM_QIO 1 1 SRAM_RSTIO 4 1 SRAM_DRD_CMD SPI_SRAM_DRD_CMD 0x5C 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RD_CMD_BITLEN 28 4 CACHE_SRAM_USR_RD_CMD_VALUE 0 16 SRAM_DWR_CMD SPI_SRAM_DWR_CMD 0x60 32 read-write n 0x0 0x0 CACHE_SRAM_USR_WR_CMD_BITLEN 28 4 CACHE_SRAM_USR_WR_CMD_VALUE 0 16 TX_CRC SPI_TX_CRC 0xC0 32 read-write n 0x0 0x0 TX_CRC_DATA 0 32 USER SPI_USER 0x1C 32 read-write n 0x0 0x0 CK_I_EDGE 6 1 CK_OUT_EDGE 7 1 CS_HOLD 4 1 CS_SETUP 5 1 DOUTDIN 0 1 FWRITE_DIO 14 1 FWRITE_DUAL 12 1 FWRITE_QIO 15 1 FWRITE_QUAD 13 1 RD_BYTE_ORDER 10 1 SIO 16 1 USR_ADDR 30 1 USR_ADDR_HOLD 21 1 USR_CMD_HOLD 22 1 USR_COMMAND 31 1 USR_DIN_HOLD 19 1 USR_DOUT_HOLD 18 1 USR_DUMMY 29 1 USR_DUMMY_HOLD 20 1 USR_DUMMY_IDLE 26 1 USR_HOLD_POL 17 1 USR_MISO 28 1 USR_MISO_HIGHPART 24 1 USR_MOSI 27 1 USR_MOSI_HIGHPART 25 1 USR_PREP_HOLD 23 1 WR_BYTE_ORDER 11 1 USER1 SPI_USER1 0x20 32 read-write n 0x0 0x0 USR_ADDR_BITLEN 26 6 USR_DUMMY_CYCLELEN 0 8 USER2 SPI_USER2 0x24 32 read-write n 0x0 0x0 USR_COMMAND_BITLEN 28 4 USR_COMMAND_VALUE 0 16 W0 SPI_W0 0x100 32 read-write n 0x0 0x0 BUF 0 32 W1 SPI_W0 0x184 32 read-write n 0x0 0x0 BUF 0 32 W10 SPI_W0 0x6DC 32 read-write n 0x0 0x0 BUF 0 32 W11 SPI_W0 0x788 32 read-write n 0x0 0x0 BUF 0 32 W12 SPI_W0 0x838 32 read-write n 0x0 0x0 BUF 0 32 W13 SPI_W0 0x8EC 32 read-write n 0x0 0x0 BUF 0 32 W14 SPI_W0 0x9A4 32 read-write n 0x0 0x0 BUF 0 32 W15 SPI_W0 0xA60 32 read-write n 0x0 0x0 BUF 0 32 W2 SPI_W0 0x20C 32 read-write n 0x0 0x0 BUF 0 32 W3 SPI_W0 0x298 32 read-write n 0x0 0x0 BUF 0 32 W4 SPI_W0 0x328 32 read-write n 0x0 0x0 BUF 0 32 W5 SPI_W0 0x3BC 32 read-write n 0x0 0x0 BUF 0 32 W6 SPI_W0 0x454 32 read-write n 0x0 0x0 BUF 0 32 W7 SPI_W0 0x4F0 32 read-write n 0x0 0x0 BUF 0 32 W8 SPI_W0 0x590 32 read-write n 0x0 0x0 BUF 0 32 W9 SPI_W0 0x634 32 read-write n 0x0 0x0 BUF 0 32 SPI1 SPI 0x0 0x0 0x860 registers n CACHE_FCTRL SPI_CACHE_FCTRL 0x50 32 read-write n 0x0 0x0 CACHE_FLASH_PES_EN 3 1 CACHE_FLASH_USR_CMD 2 1 CACHE_REQ_EN 0 1 CACHE_USR_CMD_4BYTE 1 1 CACHE_SCTRL SPI_CACHE_SCTRL 0x54 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RCMD 5 1 CACHE_SRAM_USR_WCMD 28 1 SRAM_ADDR_BITLEN 22 6 SRAM_BYTES_LEN 6 8 SRAM_DUMMY_CYCLELEN 14 8 USR_RD_SRAM_DUMMY 4 1 USR_SRAM_DIO 1 1 USR_SRAM_QIO 2 1 USR_WR_SRAM_DUMMY 3 1 CLOCK SPI_CLOCK 0x18 32 read-write n 0x0 0x0 CLKCNT_H 6 6 CLKCNT_L 0 6 CLKCNT_N 12 6 CLKDIV_PRE 18 13 CLK_EQU_SYSCLK 31 1 CMD SPI_CMD 0x0 32 read-write n 0x0 0x0 FLASH_BE 23 1 FLASH_CE 22 1 FLASH_DP 21 1 FLASH_HPM 19 1 FLASH_PER 16 1 FLASH_PES 17 1 FLASH_PP 25 1 FLASH_RDID 28 1 FLASH_RDSR 27 1 FLASH_READ 31 1 FLASH_RES 20 1 FLASH_SE 24 1 FLASH_WRDI 29 1 FLASH_WREN 30 1 FLASH_WRSR 26 1 USR 18 1 CTRL SPI_CTRL 0x8 32 read-write n 0x0 0x0 FASTRD_MODE 13 1 FCS_CRC_EN 10 1 FREAD_DIO 23 1 FREAD_DUAL 14 1 FREAD_QIO 24 1 FREAD_QUAD 20 1 RD_BIT_ORDER 25 1 RESANDRES 15 1 TX_CRC_EN 11 1 WAIT_FLASH_IDLE_EN 12 1 WP_REG 21 1 WRSR_2B 22 1 WR_BIT_ORDER 26 1 CTRL1 SPI_CTRL1 0xC 32 read-write n 0x0 0x0 CS_HOLD_DELAY 28 4 CS_HOLD_DELAY_RES 16 12 CTRL2 SPI_CTRL2 0x14 32 read-write n 0x0 0x0 CK_OUT_HIGH_MODE 12 4 CK_OUT_LOW_MODE 8 4 CS_DELAY_MODE 26 2 CS_DELAY_NUM 28 4 HOLD_TIME 4 4 MISO_DELAY_MODE 16 2 MISO_DELAY_NUM 18 3 MOSI_DELAY_MODE 21 2 MOSI_DELAY_NUM 23 3 SETUP_TIME 0 4 DATE SPI_DATE 0x3FC 32 read-write n 0x0 0x0 DATE 0 28 DMA_CONF SPI_DMA_CONF 0x100 32 read-write n 0x0 0x0 AHBM_FIFO_RST 4 1 AHBM_RST 5 1 DMA_CONTINUE 16 1 DMA_RX_STOP 14 1 DMA_TX_STOP 15 1 INDSCR_BURST_EN 11 1 IN_LOOP_TEST 6 1 IN_RST 2 1 OUTDSCR_BURST_EN 10 1 OUT_AUTO_WRBACK 8 1 OUT_DATA_BURST_EN 12 1 OUT_EOF_MODE 9 1 OUT_LOOP_TEST 7 1 OUT_RST 3 1 DMA_INT_CLR SPI_DMA_INT_CLR 0x11C 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_CLR 0 1 INLINK_DSCR_ERROR_INT_CLR 2 1 IN_DONE_INT_CLR 3 1 IN_ERR_EOF_INT_CLR 4 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_DSCR_ERROR_INT_CLR 1 1 OUT_DONE_INT_CLR 6 1 OUT_EOF_INT_CLR 7 1 OUT_TOTAL_EOF_INT_CLR 8 1 DMA_INT_ENA SPI_DMA_INT_ENA 0x110 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ENA 0 1 INLINK_DSCR_ERROR_INT_ENA 2 1 IN_DONE_INT_ENA 3 1 IN_ERR_EOF_INT_ENA 4 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_DSCR_ERROR_INT_ENA 1 1 OUT_DONE_INT_ENA 6 1 OUT_EOF_INT_ENA 7 1 OUT_TOTAL_EOF_INT_ENA 8 1 DMA_INT_RAW SPI_DMA_INT_RAW 0x114 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_RAW 0 1 INLINK_DSCR_ERROR_INT_RAW 2 1 IN_DONE_INT_RAW 3 1 IN_ERR_EOF_INT_RAW 4 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_DSCR_ERROR_INT_RAW 1 1 OUT_DONE_INT_RAW 6 1 OUT_EOF_INT_RAW 7 1 OUT_TOTAL_EOF_INT_RAW 8 1 DMA_INT_ST SPI_DMA_INT_ST 0x118 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ST 0 1 INLINK_DSCR_ERROR_INT_ST 2 1 IN_DONE_INT_ST 3 1 IN_ERR_EOF_INT_ST 4 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_DSCR_ERROR_INT_ST 1 1 OUT_DONE_INT_ST 6 1 OUT_EOF_INT_ST 7 1 OUT_TOTAL_EOF_INT_ST 8 1 DMA_IN_LINK SPI_DMA_IN_LINK 0x108 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_OUT_LINK SPI_DMA_OUT_LINK 0x104 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_RSTATUS SPI_DMA_RSTATUS 0x148 32 read-write n 0x0 0x0 DMA_OUT_STATUS 0 32 DMA_STATUS SPI_DMA_STATUS 0x10C 32 read-write n 0x0 0x0 DMA_RX_EN 0 1 DMA_TX_EN 1 1 DMA_TSTATUS SPI_DMA_TSTATUS 0x14C 32 read-write n 0x0 0x0 DMA_IN_STATUS 0 32 EXT0 SPI_EXT0 0xF0 32 read-write n 0x0 0x0 T_PP_ENA 31 1 T_PP_SHIFT 16 4 T_PP_TIME 0 12 EXT1 SPI_EXT1 0xF4 32 read-write n 0x0 0x0 T_ERASE_ENA 31 1 T_ERASE_SHIFT 16 4 T_ERASE_TIME 0 12 EXT2 SPI_EXT2 0xF8 32 read-write n 0x0 0x0 ST 0 3 EXT3 SPI_EXT3 0xFC 32 read-write n 0x0 0x0 INT_HOLD_ENA 0 2 INLINK_DSCR SPI_INLINK_DSCR 0x128 32 read-write n 0x0 0x0 DMA_INLINK_DSCR 0 32 INLINK_DSCR_BF0 SPI_INLINK_DSCR_BF0 0x12C 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 SPI_INLINK_DSCR_BF1 0x130 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF1 0 32 IN_ERR_EOF_DES_ADDR SPI_IN_ERR_EOF_DES_ADDR 0x120 32 read-write n 0x0 0x0 DMA_IN_ERR_EOF_DES_ADDR 0 32 IN_SUC_EOF_DES_ADDR SPI_IN_SUC_EOF_DES_ADDR 0x124 32 read-write n 0x0 0x0 DMA_IN_SUC_EOF_DES_ADDR 0 32 MISO_DLEN SPI_MISO_DLEN 0x2C 32 read-write n 0x0 0x0 USR_MISO_DBITLEN 0 24 MOSI_DLEN SPI_MOSI_DLEN 0x28 32 read-write n 0x0 0x0 USR_MOSI_DBITLEN 0 24 OUTLINK_DSCR SPI_OUTLINK_DSCR 0x13C 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 SPI_OUTLINK_DSCR_BF0 0x140 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 SPI_OUTLINK_DSCR_BF1 0x144 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR SPI_OUT_EOF_BFR_DES_ADDR 0x134 32 read-write n 0x0 0x0 DMA_OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR SPI_OUT_EOF_DES_ADDR 0x138 32 read-write n 0x0 0x0 DMA_OUT_EOF_DES_ADDR 0 32 PIN SPI_PIN 0x34 32 read-write n 0x0 0x0 CK_DIS 5 1 CK_IDLE_EDGE 29 1 CS0_DIS 0 1 CS1_DIS 1 1 CS2_DIS 2 1 CS_KEEP_ACTIVE 30 1 MASTER_CK_SEL 11 3 MASTER_CS_POL 6 3 RD_STATUS SPI_RD_STATUS 0x10 32 read-write n 0x0 0x0 STATUS 0 16 STATUS_EXT 24 8 WB_MODE 16 8 SLAVE SPI_SLAVE 0x38 32 read-write n 0x0 0x0 CS_I_MODE 10 2 INT_EN 5 5 SLAVE_MODE 30 1 SLV_CMD_DEFINE 27 1 SLV_LAST_COMMAND 17 3 SLV_LAST_STATE 20 3 SLV_RD_BUF_DONE 0 1 SLV_RD_STA_DONE 2 1 SLV_WR_BUF_DONE 1 1 SLV_WR_RD_BUF_EN 29 1 SLV_WR_RD_STA_EN 28 1 SLV_WR_STA_DONE 3 1 SYNC_RESET 31 1 TRANS_CNT 23 4 TRANS_DONE 4 1 SLAVE1 SPI_SLAVE1 0x3C 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_EN 0 1 SLV_RDSTA_DUMMY_EN 2 1 SLV_RD_ADDR_BITLEN 10 6 SLV_STATUS_BITLEN 27 5 SLV_STATUS_FAST_EN 26 1 SLV_STATUS_READBACK 25 1 SLV_WRBUF_DUMMY_EN 1 1 SLV_WRSTA_DUMMY_EN 3 1 SLV_WR_ADDR_BITLEN 4 6 SLAVE2 SPI_SLAVE2 0x40 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_CYCLELEN 16 8 SLV_RDSTA_DUMMY_CYCLELEN 0 8 SLV_WRBUF_DUMMY_CYCLELEN 24 8 SLV_WRSTA_DUMMY_CYCLELEN 8 8 SLAVE3 SPI_SLAVE3 0x44 32 read-write n 0x0 0x0 SLV_RDBUF_CMD_VALUE 0 8 SLV_RDSTA_CMD_VALUE 16 8 SLV_WRBUF_CMD_VALUE 8 8 SLV_WRSTA_CMD_VALUE 24 8 SLV_RDBUF_DLEN SPI_SLV_RDBUF_DLEN 0x4C 32 read-write n 0x0 0x0 SLV_RDBUF_DBITLEN 0 24 SLV_RD_BIT SPI_SLV_RD_BIT 0x64 32 read-write n 0x0 0x0 SLV_RDATA_BIT 0 24 SLV_WRBUF_DLEN SPI_SLV_WRBUF_DLEN 0x48 32 read-write n 0x0 0x0 SLV_WRBUF_DBITLEN 0 24 SLV_WR_STATUS SPI_SLV_WR_STATUS 0x30 32 read-write n 0x0 0x0 SLV_WR_ST 0 32 SRAM_CMD SPI_SRAM_CMD 0x58 32 read-write n 0x0 0x0 SRAM_DIO 0 1 SRAM_QIO 1 1 SRAM_RSTIO 4 1 SRAM_DRD_CMD SPI_SRAM_DRD_CMD 0x5C 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RD_CMD_BITLEN 28 4 CACHE_SRAM_USR_RD_CMD_VALUE 0 16 SRAM_DWR_CMD SPI_SRAM_DWR_CMD 0x60 32 read-write n 0x0 0x0 CACHE_SRAM_USR_WR_CMD_BITLEN 28 4 CACHE_SRAM_USR_WR_CMD_VALUE 0 16 TX_CRC SPI_TX_CRC 0xC0 32 read-write n 0x0 0x0 TX_CRC_DATA 0 32 USER SPI_USER 0x1C 32 read-write n 0x0 0x0 CK_I_EDGE 6 1 CK_OUT_EDGE 7 1 CS_HOLD 4 1 CS_SETUP 5 1 DOUTDIN 0 1 FWRITE_DIO 14 1 FWRITE_DUAL 12 1 FWRITE_QIO 15 1 FWRITE_QUAD 13 1 RD_BYTE_ORDER 10 1 SIO 16 1 USR_ADDR 30 1 USR_ADDR_HOLD 21 1 USR_CMD_HOLD 22 1 USR_COMMAND 31 1 USR_DIN_HOLD 19 1 USR_DOUT_HOLD 18 1 USR_DUMMY 29 1 USR_DUMMY_HOLD 20 1 USR_DUMMY_IDLE 26 1 USR_HOLD_POL 17 1 USR_MISO 28 1 USR_MISO_HIGHPART 24 1 USR_MOSI 27 1 USR_MOSI_HIGHPART 25 1 USR_PREP_HOLD 23 1 WR_BYTE_ORDER 11 1 USER1 SPI_USER1 0x20 32 read-write n 0x0 0x0 USR_ADDR_BITLEN 26 6 USR_DUMMY_CYCLELEN 0 8 USER2 SPI_USER2 0x24 32 read-write n 0x0 0x0 USR_COMMAND_BITLEN 28 4 USR_COMMAND_VALUE 0 16 W0 SPI_W0 0x100 32 read-write n 0x0 0x0 BUF 0 32 W1 SPI_W0 0x184 32 read-write n 0x0 0x0 BUF 0 32 W10 SPI_W0 0x6DC 32 read-write n 0x0 0x0 BUF 0 32 W11 SPI_W0 0x788 32 read-write n 0x0 0x0 BUF 0 32 W12 SPI_W0 0x838 32 read-write n 0x0 0x0 BUF 0 32 W13 SPI_W0 0x8EC 32 read-write n 0x0 0x0 BUF 0 32 W14 SPI_W0 0x9A4 32 read-write n 0x0 0x0 BUF 0 32 W15 SPI_W0 0xA60 32 read-write n 0x0 0x0 BUF 0 32 W2 SPI_W0 0x20C 32 read-write n 0x0 0x0 BUF 0 32 W3 SPI_W0 0x298 32 read-write n 0x0 0x0 BUF 0 32 W4 SPI_W0 0x328 32 read-write n 0x0 0x0 BUF 0 32 W5 SPI_W0 0x3BC 32 read-write n 0x0 0x0 BUF 0 32 W6 SPI_W0 0x454 32 read-write n 0x0 0x0 BUF 0 32 W7 SPI_W0 0x4F0 32 read-write n 0x0 0x0 BUF 0 32 W8 SPI_W0 0x590 32 read-write n 0x0 0x0 BUF 0 32 W9 SPI_W0 0x634 32 read-write n 0x0 0x0 BUF 0 32 SPI2 SPI 0x0 0x0 0x860 registers n CACHE_FCTRL SPI_CACHE_FCTRL 0x50 32 read-write n 0x0 0x0 CACHE_FLASH_PES_EN 3 1 CACHE_FLASH_USR_CMD 2 1 CACHE_REQ_EN 0 1 CACHE_USR_CMD_4BYTE 1 1 CACHE_SCTRL SPI_CACHE_SCTRL 0x54 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RCMD 5 1 CACHE_SRAM_USR_WCMD 28 1 SRAM_ADDR_BITLEN 22 6 SRAM_BYTES_LEN 6 8 SRAM_DUMMY_CYCLELEN 14 8 USR_RD_SRAM_DUMMY 4 1 USR_SRAM_DIO 1 1 USR_SRAM_QIO 2 1 USR_WR_SRAM_DUMMY 3 1 CLOCK SPI_CLOCK 0x18 32 read-write n 0x0 0x0 CLKCNT_H 6 6 CLKCNT_L 0 6 CLKCNT_N 12 6 CLKDIV_PRE 18 13 CLK_EQU_SYSCLK 31 1 CMD SPI_CMD 0x0 32 read-write n 0x0 0x0 FLASH_BE 23 1 FLASH_CE 22 1 FLASH_DP 21 1 FLASH_HPM 19 1 FLASH_PER 16 1 FLASH_PES 17 1 FLASH_PP 25 1 FLASH_RDID 28 1 FLASH_RDSR 27 1 FLASH_READ 31 1 FLASH_RES 20 1 FLASH_SE 24 1 FLASH_WRDI 29 1 FLASH_WREN 30 1 FLASH_WRSR 26 1 USR 18 1 CTRL SPI_CTRL 0x8 32 read-write n 0x0 0x0 FASTRD_MODE 13 1 FCS_CRC_EN 10 1 FREAD_DIO 23 1 FREAD_DUAL 14 1 FREAD_QIO 24 1 FREAD_QUAD 20 1 RD_BIT_ORDER 25 1 RESANDRES 15 1 TX_CRC_EN 11 1 WAIT_FLASH_IDLE_EN 12 1 WP_REG 21 1 WRSR_2B 22 1 WR_BIT_ORDER 26 1 CTRL1 SPI_CTRL1 0xC 32 read-write n 0x0 0x0 CS_HOLD_DELAY 28 4 CS_HOLD_DELAY_RES 16 12 CTRL2 SPI_CTRL2 0x14 32 read-write n 0x0 0x0 CK_OUT_HIGH_MODE 12 4 CK_OUT_LOW_MODE 8 4 CS_DELAY_MODE 26 2 CS_DELAY_NUM 28 4 HOLD_TIME 4 4 MISO_DELAY_MODE 16 2 MISO_DELAY_NUM 18 3 MOSI_DELAY_MODE 21 2 MOSI_DELAY_NUM 23 3 SETUP_TIME 0 4 DATE SPI_DATE 0x3FC 32 read-write n 0x0 0x0 DATE 0 28 DMA_CONF SPI_DMA_CONF 0x100 32 read-write n 0x0 0x0 AHBM_FIFO_RST 4 1 AHBM_RST 5 1 DMA_CONTINUE 16 1 DMA_RX_STOP 14 1 DMA_TX_STOP 15 1 INDSCR_BURST_EN 11 1 IN_LOOP_TEST 6 1 IN_RST 2 1 OUTDSCR_BURST_EN 10 1 OUT_AUTO_WRBACK 8 1 OUT_DATA_BURST_EN 12 1 OUT_EOF_MODE 9 1 OUT_LOOP_TEST 7 1 OUT_RST 3 1 DMA_INT_CLR SPI_DMA_INT_CLR 0x11C 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_CLR 0 1 INLINK_DSCR_ERROR_INT_CLR 2 1 IN_DONE_INT_CLR 3 1 IN_ERR_EOF_INT_CLR 4 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_DSCR_ERROR_INT_CLR 1 1 OUT_DONE_INT_CLR 6 1 OUT_EOF_INT_CLR 7 1 OUT_TOTAL_EOF_INT_CLR 8 1 DMA_INT_ENA SPI_DMA_INT_ENA 0x110 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ENA 0 1 INLINK_DSCR_ERROR_INT_ENA 2 1 IN_DONE_INT_ENA 3 1 IN_ERR_EOF_INT_ENA 4 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_DSCR_ERROR_INT_ENA 1 1 OUT_DONE_INT_ENA 6 1 OUT_EOF_INT_ENA 7 1 OUT_TOTAL_EOF_INT_ENA 8 1 DMA_INT_RAW SPI_DMA_INT_RAW 0x114 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_RAW 0 1 INLINK_DSCR_ERROR_INT_RAW 2 1 IN_DONE_INT_RAW 3 1 IN_ERR_EOF_INT_RAW 4 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_DSCR_ERROR_INT_RAW 1 1 OUT_DONE_INT_RAW 6 1 OUT_EOF_INT_RAW 7 1 OUT_TOTAL_EOF_INT_RAW 8 1 DMA_INT_ST SPI_DMA_INT_ST 0x118 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ST 0 1 INLINK_DSCR_ERROR_INT_ST 2 1 IN_DONE_INT_ST 3 1 IN_ERR_EOF_INT_ST 4 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_DSCR_ERROR_INT_ST 1 1 OUT_DONE_INT_ST 6 1 OUT_EOF_INT_ST 7 1 OUT_TOTAL_EOF_INT_ST 8 1 DMA_IN_LINK SPI_DMA_IN_LINK 0x108 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_OUT_LINK SPI_DMA_OUT_LINK 0x104 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_RSTATUS SPI_DMA_RSTATUS 0x148 32 read-write n 0x0 0x0 DMA_OUT_STATUS 0 32 DMA_STATUS SPI_DMA_STATUS 0x10C 32 read-write n 0x0 0x0 DMA_RX_EN 0 1 DMA_TX_EN 1 1 DMA_TSTATUS SPI_DMA_TSTATUS 0x14C 32 read-write n 0x0 0x0 DMA_IN_STATUS 0 32 EXT0 SPI_EXT0 0xF0 32 read-write n 0x0 0x0 T_PP_ENA 31 1 T_PP_SHIFT 16 4 T_PP_TIME 0 12 EXT1 SPI_EXT1 0xF4 32 read-write n 0x0 0x0 T_ERASE_ENA 31 1 T_ERASE_SHIFT 16 4 T_ERASE_TIME 0 12 EXT2 SPI_EXT2 0xF8 32 read-write n 0x0 0x0 ST 0 3 EXT3 SPI_EXT3 0xFC 32 read-write n 0x0 0x0 INT_HOLD_ENA 0 2 INLINK_DSCR SPI_INLINK_DSCR 0x128 32 read-write n 0x0 0x0 DMA_INLINK_DSCR 0 32 INLINK_DSCR_BF0 SPI_INLINK_DSCR_BF0 0x12C 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 SPI_INLINK_DSCR_BF1 0x130 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF1 0 32 IN_ERR_EOF_DES_ADDR SPI_IN_ERR_EOF_DES_ADDR 0x120 32 read-write n 0x0 0x0 DMA_IN_ERR_EOF_DES_ADDR 0 32 IN_SUC_EOF_DES_ADDR SPI_IN_SUC_EOF_DES_ADDR 0x124 32 read-write n 0x0 0x0 DMA_IN_SUC_EOF_DES_ADDR 0 32 MISO_DLEN SPI_MISO_DLEN 0x2C 32 read-write n 0x0 0x0 USR_MISO_DBITLEN 0 24 MOSI_DLEN SPI_MOSI_DLEN 0x28 32 read-write n 0x0 0x0 USR_MOSI_DBITLEN 0 24 OUTLINK_DSCR SPI_OUTLINK_DSCR 0x13C 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 SPI_OUTLINK_DSCR_BF0 0x140 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 SPI_OUTLINK_DSCR_BF1 0x144 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR SPI_OUT_EOF_BFR_DES_ADDR 0x134 32 read-write n 0x0 0x0 DMA_OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR SPI_OUT_EOF_DES_ADDR 0x138 32 read-write n 0x0 0x0 DMA_OUT_EOF_DES_ADDR 0 32 PIN SPI_PIN 0x34 32 read-write n 0x0 0x0 CK_DIS 5 1 CK_IDLE_EDGE 29 1 CS0_DIS 0 1 CS1_DIS 1 1 CS2_DIS 2 1 CS_KEEP_ACTIVE 30 1 MASTER_CK_SEL 11 3 MASTER_CS_POL 6 3 RD_STATUS SPI_RD_STATUS 0x10 32 read-write n 0x0 0x0 STATUS 0 16 STATUS_EXT 24 8 WB_MODE 16 8 SLAVE SPI_SLAVE 0x38 32 read-write n 0x0 0x0 CS_I_MODE 10 2 INT_EN 5 5 SLAVE_MODE 30 1 SLV_CMD_DEFINE 27 1 SLV_LAST_COMMAND 17 3 SLV_LAST_STATE 20 3 SLV_RD_BUF_DONE 0 1 SLV_RD_STA_DONE 2 1 SLV_WR_BUF_DONE 1 1 SLV_WR_RD_BUF_EN 29 1 SLV_WR_RD_STA_EN 28 1 SLV_WR_STA_DONE 3 1 SYNC_RESET 31 1 TRANS_CNT 23 4 TRANS_DONE 4 1 SLAVE1 SPI_SLAVE1 0x3C 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_EN 0 1 SLV_RDSTA_DUMMY_EN 2 1 SLV_RD_ADDR_BITLEN 10 6 SLV_STATUS_BITLEN 27 5 SLV_STATUS_FAST_EN 26 1 SLV_STATUS_READBACK 25 1 SLV_WRBUF_DUMMY_EN 1 1 SLV_WRSTA_DUMMY_EN 3 1 SLV_WR_ADDR_BITLEN 4 6 SLAVE2 SPI_SLAVE2 0x40 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_CYCLELEN 16 8 SLV_RDSTA_DUMMY_CYCLELEN 0 8 SLV_WRBUF_DUMMY_CYCLELEN 24 8 SLV_WRSTA_DUMMY_CYCLELEN 8 8 SLAVE3 SPI_SLAVE3 0x44 32 read-write n 0x0 0x0 SLV_RDBUF_CMD_VALUE 0 8 SLV_RDSTA_CMD_VALUE 16 8 SLV_WRBUF_CMD_VALUE 8 8 SLV_WRSTA_CMD_VALUE 24 8 SLV_RDBUF_DLEN SPI_SLV_RDBUF_DLEN 0x4C 32 read-write n 0x0 0x0 SLV_RDBUF_DBITLEN 0 24 SLV_RD_BIT SPI_SLV_RD_BIT 0x64 32 read-write n 0x0 0x0 SLV_RDATA_BIT 0 24 SLV_WRBUF_DLEN SPI_SLV_WRBUF_DLEN 0x48 32 read-write n 0x0 0x0 SLV_WRBUF_DBITLEN 0 24 SLV_WR_STATUS SPI_SLV_WR_STATUS 0x30 32 read-write n 0x0 0x0 SLV_WR_ST 0 32 SRAM_CMD SPI_SRAM_CMD 0x58 32 read-write n 0x0 0x0 SRAM_DIO 0 1 SRAM_QIO 1 1 SRAM_RSTIO 4 1 SRAM_DRD_CMD SPI_SRAM_DRD_CMD 0x5C 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RD_CMD_BITLEN 28 4 CACHE_SRAM_USR_RD_CMD_VALUE 0 16 SRAM_DWR_CMD SPI_SRAM_DWR_CMD 0x60 32 read-write n 0x0 0x0 CACHE_SRAM_USR_WR_CMD_BITLEN 28 4 CACHE_SRAM_USR_WR_CMD_VALUE 0 16 TX_CRC SPI_TX_CRC 0xC0 32 read-write n 0x0 0x0 TX_CRC_DATA 0 32 USER SPI_USER 0x1C 32 read-write n 0x0 0x0 CK_I_EDGE 6 1 CK_OUT_EDGE 7 1 CS_HOLD 4 1 CS_SETUP 5 1 DOUTDIN 0 1 FWRITE_DIO 14 1 FWRITE_DUAL 12 1 FWRITE_QIO 15 1 FWRITE_QUAD 13 1 RD_BYTE_ORDER 10 1 SIO 16 1 USR_ADDR 30 1 USR_ADDR_HOLD 21 1 USR_CMD_HOLD 22 1 USR_COMMAND 31 1 USR_DIN_HOLD 19 1 USR_DOUT_HOLD 18 1 USR_DUMMY 29 1 USR_DUMMY_HOLD 20 1 USR_DUMMY_IDLE 26 1 USR_HOLD_POL 17 1 USR_MISO 28 1 USR_MISO_HIGHPART 24 1 USR_MOSI 27 1 USR_MOSI_HIGHPART 25 1 USR_PREP_HOLD 23 1 WR_BYTE_ORDER 11 1 USER1 SPI_USER1 0x20 32 read-write n 0x0 0x0 USR_ADDR_BITLEN 26 6 USR_DUMMY_CYCLELEN 0 8 USER2 SPI_USER2 0x24 32 read-write n 0x0 0x0 USR_COMMAND_BITLEN 28 4 USR_COMMAND_VALUE 0 16 W0 SPI_W0 0x100 32 read-write n 0x0 0x0 BUF 0 32 W1 SPI_W0 0x184 32 read-write n 0x0 0x0 BUF 0 32 W10 SPI_W0 0x6DC 32 read-write n 0x0 0x0 BUF 0 32 W11 SPI_W0 0x788 32 read-write n 0x0 0x0 BUF 0 32 W12 SPI_W0 0x838 32 read-write n 0x0 0x0 BUF 0 32 W13 SPI_W0 0x8EC 32 read-write n 0x0 0x0 BUF 0 32 W14 SPI_W0 0x9A4 32 read-write n 0x0 0x0 BUF 0 32 W15 SPI_W0 0xA60 32 read-write n 0x0 0x0 BUF 0 32 W2 SPI_W0 0x20C 32 read-write n 0x0 0x0 BUF 0 32 W3 SPI_W0 0x298 32 read-write n 0x0 0x0 BUF 0 32 W4 SPI_W0 0x328 32 read-write n 0x0 0x0 BUF 0 32 W5 SPI_W0 0x3BC 32 read-write n 0x0 0x0 BUF 0 32 W6 SPI_W0 0x454 32 read-write n 0x0 0x0 BUF 0 32 W7 SPI_W0 0x4F0 32 read-write n 0x0 0x0 BUF 0 32 W8 SPI_W0 0x590 32 read-write n 0x0 0x0 BUF 0 32 W9 SPI_W0 0x634 32 read-write n 0x0 0x0 BUF 0 32 SPI3 SPI 0x0 0x0 0x860 registers n CACHE_FCTRL SPI_CACHE_FCTRL 0x50 32 read-write n 0x0 0x0 CACHE_FLASH_PES_EN 3 1 CACHE_FLASH_USR_CMD 2 1 CACHE_REQ_EN 0 1 CACHE_USR_CMD_4BYTE 1 1 CACHE_SCTRL SPI_CACHE_SCTRL 0x54 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RCMD 5 1 CACHE_SRAM_USR_WCMD 28 1 SRAM_ADDR_BITLEN 22 6 SRAM_BYTES_LEN 6 8 SRAM_DUMMY_CYCLELEN 14 8 USR_RD_SRAM_DUMMY 4 1 USR_SRAM_DIO 1 1 USR_SRAM_QIO 2 1 USR_WR_SRAM_DUMMY 3 1 CLOCK SPI_CLOCK 0x18 32 read-write n 0x0 0x0 CLKCNT_H 6 6 CLKCNT_L 0 6 CLKCNT_N 12 6 CLKDIV_PRE 18 13 CLK_EQU_SYSCLK 31 1 CMD SPI_CMD 0x0 32 read-write n 0x0 0x0 FLASH_BE 23 1 FLASH_CE 22 1 FLASH_DP 21 1 FLASH_HPM 19 1 FLASH_PER 16 1 FLASH_PES 17 1 FLASH_PP 25 1 FLASH_RDID 28 1 FLASH_RDSR 27 1 FLASH_READ 31 1 FLASH_RES 20 1 FLASH_SE 24 1 FLASH_WRDI 29 1 FLASH_WREN 30 1 FLASH_WRSR 26 1 USR 18 1 CTRL SPI_CTRL 0x8 32 read-write n 0x0 0x0 FASTRD_MODE 13 1 FCS_CRC_EN 10 1 FREAD_DIO 23 1 FREAD_DUAL 14 1 FREAD_QIO 24 1 FREAD_QUAD 20 1 RD_BIT_ORDER 25 1 RESANDRES 15 1 TX_CRC_EN 11 1 WAIT_FLASH_IDLE_EN 12 1 WP_REG 21 1 WRSR_2B 22 1 WR_BIT_ORDER 26 1 CTRL1 SPI_CTRL1 0xC 32 read-write n 0x0 0x0 CS_HOLD_DELAY 28 4 CS_HOLD_DELAY_RES 16 12 CTRL2 SPI_CTRL2 0x14 32 read-write n 0x0 0x0 CK_OUT_HIGH_MODE 12 4 CK_OUT_LOW_MODE 8 4 CS_DELAY_MODE 26 2 CS_DELAY_NUM 28 4 HOLD_TIME 4 4 MISO_DELAY_MODE 16 2 MISO_DELAY_NUM 18 3 MOSI_DELAY_MODE 21 2 MOSI_DELAY_NUM 23 3 SETUP_TIME 0 4 DATE SPI_DATE 0x3FC 32 read-write n 0x0 0x0 DATE 0 28 DMA_CONF SPI_DMA_CONF 0x100 32 read-write n 0x0 0x0 AHBM_FIFO_RST 4 1 AHBM_RST 5 1 DMA_CONTINUE 16 1 DMA_RX_STOP 14 1 DMA_TX_STOP 15 1 INDSCR_BURST_EN 11 1 IN_LOOP_TEST 6 1 IN_RST 2 1 OUTDSCR_BURST_EN 10 1 OUT_AUTO_WRBACK 8 1 OUT_DATA_BURST_EN 12 1 OUT_EOF_MODE 9 1 OUT_LOOP_TEST 7 1 OUT_RST 3 1 DMA_INT_CLR SPI_DMA_INT_CLR 0x11C 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_CLR 0 1 INLINK_DSCR_ERROR_INT_CLR 2 1 IN_DONE_INT_CLR 3 1 IN_ERR_EOF_INT_CLR 4 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_DSCR_ERROR_INT_CLR 1 1 OUT_DONE_INT_CLR 6 1 OUT_EOF_INT_CLR 7 1 OUT_TOTAL_EOF_INT_CLR 8 1 DMA_INT_ENA SPI_DMA_INT_ENA 0x110 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ENA 0 1 INLINK_DSCR_ERROR_INT_ENA 2 1 IN_DONE_INT_ENA 3 1 IN_ERR_EOF_INT_ENA 4 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_DSCR_ERROR_INT_ENA 1 1 OUT_DONE_INT_ENA 6 1 OUT_EOF_INT_ENA 7 1 OUT_TOTAL_EOF_INT_ENA 8 1 DMA_INT_RAW SPI_DMA_INT_RAW 0x114 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_RAW 0 1 INLINK_DSCR_ERROR_INT_RAW 2 1 IN_DONE_INT_RAW 3 1 IN_ERR_EOF_INT_RAW 4 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_DSCR_ERROR_INT_RAW 1 1 OUT_DONE_INT_RAW 6 1 OUT_EOF_INT_RAW 7 1 OUT_TOTAL_EOF_INT_RAW 8 1 DMA_INT_ST SPI_DMA_INT_ST 0x118 32 read-write n 0x0 0x0 INLINK_DSCR_EMPTY_INT_ST 0 1 INLINK_DSCR_ERROR_INT_ST 2 1 IN_DONE_INT_ST 3 1 IN_ERR_EOF_INT_ST 4 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_DSCR_ERROR_INT_ST 1 1 OUT_DONE_INT_ST 6 1 OUT_EOF_INT_ST 7 1 OUT_TOTAL_EOF_INT_ST 8 1 DMA_IN_LINK SPI_DMA_IN_LINK 0x108 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_OUT_LINK SPI_DMA_OUT_LINK 0x104 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_RSTATUS SPI_DMA_RSTATUS 0x148 32 read-write n 0x0 0x0 DMA_OUT_STATUS 0 32 DMA_STATUS SPI_DMA_STATUS 0x10C 32 read-write n 0x0 0x0 DMA_RX_EN 0 1 DMA_TX_EN 1 1 DMA_TSTATUS SPI_DMA_TSTATUS 0x14C 32 read-write n 0x0 0x0 DMA_IN_STATUS 0 32 EXT0 SPI_EXT0 0xF0 32 read-write n 0x0 0x0 T_PP_ENA 31 1 T_PP_SHIFT 16 4 T_PP_TIME 0 12 EXT1 SPI_EXT1 0xF4 32 read-write n 0x0 0x0 T_ERASE_ENA 31 1 T_ERASE_SHIFT 16 4 T_ERASE_TIME 0 12 EXT2 SPI_EXT2 0xF8 32 read-write n 0x0 0x0 ST 0 3 EXT3 SPI_EXT3 0xFC 32 read-write n 0x0 0x0 INT_HOLD_ENA 0 2 INLINK_DSCR SPI_INLINK_DSCR 0x128 32 read-write n 0x0 0x0 DMA_INLINK_DSCR 0 32 INLINK_DSCR_BF0 SPI_INLINK_DSCR_BF0 0x12C 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF0 0 32 INLINK_DSCR_BF1 SPI_INLINK_DSCR_BF1 0x130 32 read-write n 0x0 0x0 DMA_INLINK_DSCR_BF1 0 32 IN_ERR_EOF_DES_ADDR SPI_IN_ERR_EOF_DES_ADDR 0x120 32 read-write n 0x0 0x0 DMA_IN_ERR_EOF_DES_ADDR 0 32 IN_SUC_EOF_DES_ADDR SPI_IN_SUC_EOF_DES_ADDR 0x124 32 read-write n 0x0 0x0 DMA_IN_SUC_EOF_DES_ADDR 0 32 MISO_DLEN SPI_MISO_DLEN 0x2C 32 read-write n 0x0 0x0 USR_MISO_DBITLEN 0 24 MOSI_DLEN SPI_MOSI_DLEN 0x28 32 read-write n 0x0 0x0 USR_MOSI_DBITLEN 0 24 OUTLINK_DSCR SPI_OUTLINK_DSCR 0x13C 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR 0 32 OUTLINK_DSCR_BF0 SPI_OUTLINK_DSCR_BF0 0x140 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF0 0 32 OUTLINK_DSCR_BF1 SPI_OUTLINK_DSCR_BF1 0x144 32 read-write n 0x0 0x0 DMA_OUTLINK_DSCR_BF1 0 32 OUT_EOF_BFR_DES_ADDR SPI_OUT_EOF_BFR_DES_ADDR 0x134 32 read-write n 0x0 0x0 DMA_OUT_EOF_BFR_DES_ADDR 0 32 OUT_EOF_DES_ADDR SPI_OUT_EOF_DES_ADDR 0x138 32 read-write n 0x0 0x0 DMA_OUT_EOF_DES_ADDR 0 32 PIN SPI_PIN 0x34 32 read-write n 0x0 0x0 CK_DIS 5 1 CK_IDLE_EDGE 29 1 CS0_DIS 0 1 CS1_DIS 1 1 CS2_DIS 2 1 CS_KEEP_ACTIVE 30 1 MASTER_CK_SEL 11 3 MASTER_CS_POL 6 3 RD_STATUS SPI_RD_STATUS 0x10 32 read-write n 0x0 0x0 STATUS 0 16 STATUS_EXT 24 8 WB_MODE 16 8 SLAVE SPI_SLAVE 0x38 32 read-write n 0x0 0x0 CS_I_MODE 10 2 INT_EN 5 5 SLAVE_MODE 30 1 SLV_CMD_DEFINE 27 1 SLV_LAST_COMMAND 17 3 SLV_LAST_STATE 20 3 SLV_RD_BUF_DONE 0 1 SLV_RD_STA_DONE 2 1 SLV_WR_BUF_DONE 1 1 SLV_WR_RD_BUF_EN 29 1 SLV_WR_RD_STA_EN 28 1 SLV_WR_STA_DONE 3 1 SYNC_RESET 31 1 TRANS_CNT 23 4 TRANS_DONE 4 1 SLAVE1 SPI_SLAVE1 0x3C 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_EN 0 1 SLV_RDSTA_DUMMY_EN 2 1 SLV_RD_ADDR_BITLEN 10 6 SLV_STATUS_BITLEN 27 5 SLV_STATUS_FAST_EN 26 1 SLV_STATUS_READBACK 25 1 SLV_WRBUF_DUMMY_EN 1 1 SLV_WRSTA_DUMMY_EN 3 1 SLV_WR_ADDR_BITLEN 4 6 SLAVE2 SPI_SLAVE2 0x40 32 read-write n 0x0 0x0 SLV_RDBUF_DUMMY_CYCLELEN 16 8 SLV_RDSTA_DUMMY_CYCLELEN 0 8 SLV_WRBUF_DUMMY_CYCLELEN 24 8 SLV_WRSTA_DUMMY_CYCLELEN 8 8 SLAVE3 SPI_SLAVE3 0x44 32 read-write n 0x0 0x0 SLV_RDBUF_CMD_VALUE 0 8 SLV_RDSTA_CMD_VALUE 16 8 SLV_WRBUF_CMD_VALUE 8 8 SLV_WRSTA_CMD_VALUE 24 8 SLV_RDBUF_DLEN SPI_SLV_RDBUF_DLEN 0x4C 32 read-write n 0x0 0x0 SLV_RDBUF_DBITLEN 0 24 SLV_RD_BIT SPI_SLV_RD_BIT 0x64 32 read-write n 0x0 0x0 SLV_RDATA_BIT 0 24 SLV_WRBUF_DLEN SPI_SLV_WRBUF_DLEN 0x48 32 read-write n 0x0 0x0 SLV_WRBUF_DBITLEN 0 24 SLV_WR_STATUS SPI_SLV_WR_STATUS 0x30 32 read-write n 0x0 0x0 SLV_WR_ST 0 32 SRAM_CMD SPI_SRAM_CMD 0x58 32 read-write n 0x0 0x0 SRAM_DIO 0 1 SRAM_QIO 1 1 SRAM_RSTIO 4 1 SRAM_DRD_CMD SPI_SRAM_DRD_CMD 0x5C 32 read-write n 0x0 0x0 CACHE_SRAM_USR_RD_CMD_BITLEN 28 4 CACHE_SRAM_USR_RD_CMD_VALUE 0 16 SRAM_DWR_CMD SPI_SRAM_DWR_CMD 0x60 32 read-write n 0x0 0x0 CACHE_SRAM_USR_WR_CMD_BITLEN 28 4 CACHE_SRAM_USR_WR_CMD_VALUE 0 16 TX_CRC SPI_TX_CRC 0xC0 32 read-write n 0x0 0x0 TX_CRC_DATA 0 32 USER SPI_USER 0x1C 32 read-write n 0x0 0x0 CK_I_EDGE 6 1 CK_OUT_EDGE 7 1 CS_HOLD 4 1 CS_SETUP 5 1 DOUTDIN 0 1 FWRITE_DIO 14 1 FWRITE_DUAL 12 1 FWRITE_QIO 15 1 FWRITE_QUAD 13 1 RD_BYTE_ORDER 10 1 SIO 16 1 USR_ADDR 30 1 USR_ADDR_HOLD 21 1 USR_CMD_HOLD 22 1 USR_COMMAND 31 1 USR_DIN_HOLD 19 1 USR_DOUT_HOLD 18 1 USR_DUMMY 29 1 USR_DUMMY_HOLD 20 1 USR_DUMMY_IDLE 26 1 USR_HOLD_POL 17 1 USR_MISO 28 1 USR_MISO_HIGHPART 24 1 USR_MOSI 27 1 USR_MOSI_HIGHPART 25 1 USR_PREP_HOLD 23 1 WR_BYTE_ORDER 11 1 USER1 SPI_USER1 0x20 32 read-write n 0x0 0x0 USR_ADDR_BITLEN 26 6 USR_DUMMY_CYCLELEN 0 8 USER2 SPI_USER2 0x24 32 read-write n 0x0 0x0 USR_COMMAND_BITLEN 28 4 USR_COMMAND_VALUE 0 16 W0 SPI_W0 0x100 32 read-write n 0x0 0x0 BUF 0 32 W1 SPI_W0 0x184 32 read-write n 0x0 0x0 BUF 0 32 W10 SPI_W0 0x6DC 32 read-write n 0x0 0x0 BUF 0 32 W11 SPI_W0 0x788 32 read-write n 0x0 0x0 BUF 0 32 W12 SPI_W0 0x838 32 read-write n 0x0 0x0 BUF 0 32 W13 SPI_W0 0x8EC 32 read-write n 0x0 0x0 BUF 0 32 W14 SPI_W0 0x9A4 32 read-write n 0x0 0x0 BUF 0 32 W15 SPI_W0 0xA60 32 read-write n 0x0 0x0 BUF 0 32 W2 SPI_W0 0x20C 32 read-write n 0x0 0x0 BUF 0 32 W3 SPI_W0 0x298 32 read-write n 0x0 0x0 BUF 0 32 W4 SPI_W0 0x328 32 read-write n 0x0 0x0 BUF 0 32 W5 SPI_W0 0x3BC 32 read-write n 0x0 0x0 BUF 0 32 W6 SPI_W0 0x454 32 read-write n 0x0 0x0 BUF 0 32 W7 SPI_W0 0x4F0 32 read-write n 0x0 0x0 BUF 0 32 W8 SPI_W0 0x590 32 read-write n 0x0 0x0 BUF 0 32 W9 SPI_W0 0x634 32 read-write n 0x0 0x0 BUF 0 32 SPI_ENCRYPT SPI_ENCRYPT 0x0 0x0 0x0 registers n SYSCON SYSCON 0x0 0x0 0x220 registers n APLL_TICK_CONF SYSCON_APLL_TICK_CONF 0x3C 32 read-write n 0x0 0x0 APLL_TICK_NUM 0 8 CK8M_TICK_CONF SYSCON_CK8M_TICK_CONF 0xC 32 read-write n 0x0 0x0 CK8M_TICK_NUM 0 8 DATE SYSCON_DATE 0x7C 32 read-write n 0x0 0x0 DATE 0 32 PLL_TICK_CONF SYSCON_PLL_TICK_CONF 0x8 32 read-write n 0x0 0x0 PLL_TICK_NUM 0 8 SARADC_CTRL SYSCON_SARADC_CTRL 0x10 32 read-write n 0x0 0x0 SARADC_DATA_SAR_SEL 25 1 SARADC_DATA_TO_I2S 26 1 SARADC_SAR1_PATT_LEN 15 4 SARADC_SAR1_PATT_P_CLEAR 23 1 SARADC_SAR2_MUX 2 1 SARADC_SAR2_PATT_LEN 19 4 SARADC_SAR2_PATT_P_CLEAR 24 1 SARADC_SAR_CLK_DIV 7 8 SARADC_SAR_CLK_GATED 6 1 SARADC_SAR_SEL 5 1 SARADC_START 1 1 SARADC_START_FORCE 0 1 SARADC_WORK_MODE 3 2 SARADC_CTRL2 SYSCON_SARADC_CTRL2 0x14 32 read-write n 0x0 0x0 SARADC_MAX_MEAS_NUM 1 8 SARADC_MEAS_NUM_LIMIT 0 1 SARADC_SAR1_INV 9 1 SARADC_SAR2_INV 10 1 SARADC_FSM SYSCON_SARADC_FSM 0x18 32 read-write n 0x0 0x0 SARADC_RSTB_WAIT 0 8 SARADC_SAMPLE_CYCLE 24 8 SARADC_STANDBY_WAIT 8 8 SARADC_START_WAIT 16 8 SARADC_SAR1_PATT_TAB1 SYSCON_SARADC_SAR1_PATT_TAB1 0x1C 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB1 0 32 SARADC_SAR1_PATT_TAB2 SYSCON_SARADC_SAR1_PATT_TAB2 0x20 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB2 0 32 SARADC_SAR1_PATT_TAB3 SYSCON_SARADC_SAR1_PATT_TAB3 0x24 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB3 0 32 SARADC_SAR1_PATT_TAB4 SYSCON_SARADC_SAR1_PATT_TAB4 0x28 32 read-write n 0x0 0x0 SARADC_SAR1_PATT_TAB4 0 32 SARADC_SAR2_PATT_TAB1 SYSCON_SARADC_SAR2_PATT_TAB1 0x2C 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB1 0 32 SARADC_SAR2_PATT_TAB2 SYSCON_SARADC_SAR2_PATT_TAB2 0x30 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB2 0 32 SARADC_SAR2_PATT_TAB3 SYSCON_SARADC_SAR2_PATT_TAB3 0x34 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB3 0 32 SARADC_SAR2_PATT_TAB4 SYSCON_SARADC_SAR2_PATT_TAB4 0x38 32 read-write n 0x0 0x0 SARADC_SAR2_PATT_TAB4 0 32 SYSCLK_CONF SYSCON_SYSCLK_CONF 0x0 32 read-write n 0x0 0x0 CLK_320M_EN 10 1 CLK_EN 11 1 PRE_DIV_CNT 0 10 QUICK_CLK_CHNG 13 1 RST_TICK_CNT 12 1 XTAL_TICK_CONF SYSCON_XTAL_TICK_CONF 0x4 32 read-write n 0x0 0x0 XTAL_TICK_NUM 0 8 TIMG TIMG 0x0 0x0 0x580 registers n TG0_T0_LEVEL_INTR interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission 14 TG0_T1_LEVEL_INTR interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission 15 TG0_WDT_LEVEL_INTR interrupt of TIMER_GROUP0, WATCHDOG, level 16 TG0_LACT_LEVEL_INTR interrupt of TIMER_GROUP0, LACT, level 17 TG1_T0_LEVEL_INTR interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission 18 TG1_T1_LEVEL_INTR interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission 19 TG1_WDT_LEVEL_INTR interrupt of TIMER_GROUP1, WATCHDOG, level 20 TG1_LACT_LEVEL_INTR interrupt of TIMER_GROUP1, LACT, level 21 TG0_T0_EDGE_INTR interrupt of TIMER_GROUP0, TIMER0, EDGE 58 TG0_T1_EDGE_INTR interrupt of TIMER_GROUP0, TIMER1, EDGE 59 TG0_WDT_EDGE_INTR interrupt of TIMER_GROUP0, WATCH DOG, EDGE 60 TG0_LACT_EDGE_INTR interrupt of TIMER_GROUP0, LACT, EDGE 61 TG1_T0_EDGE_INTR interrupt of TIMER_GROUP1, TIMER0, EDGE 62 TG1_T1_EDGE_INTR interrupt of TIMER_GROUP1, TIMER1, EDGE 63 TG1_WDT_EDGE_INTR interrupt of TIMER_GROUP1, WATCHDOG, EDGE 64 TG1_LACT_EDGE_INTR interrupt of TIMER_GROUP0, LACT, EDGE 65 INT_CLR_TIMERS TIMG_INT_CLR_TIMERS 0xA4 32 read-write n 0x0 0x0 LACT_INT_CLR 3 1 T0_INT_CLR 0 1 T1_INT_CLR 1 1 WDT_INT_CLR 2 1 INT_ENA_TIMERS TIMG_INT_ENA_TIMERS 0x98 32 read-write n 0x0 0x0 LACT_INT_ENA 3 1 T0_INT_ENA 0 1 T1_INT_ENA 1 1 WDT_INT_ENA 2 1 INT_RAW_TIMERS TIMG_INT_RAW_TIMERS 0x9C 32 read-write n 0x0 0x0 LACT_INT_RAW 3 1 T0_INT_RAW 0 1 T1_INT_RAW 1 1 WDT_INT_RAW 2 1 INT_ST_TIMERS TIMG_INT_ST_TIMERS 0xA0 32 read-write n 0x0 0x0 LACT_INT_ST 3 1 T0_INT_ST 0 1 T1_INT_ST 1 1 WDT_INT_ST 2 1 LACTALARMHI TIMG_LACTALARMHI 0x88 32 read-write n 0x0 0x0 LACT_ALARM_HI 0 32 LACTALARMLO TIMG_LACTALARMLO 0x84 32 read-write n 0x0 0x0 LACT_ALARM_LO 0 32 LACTCONFIG TIMG_LACTCONFIG 0x70 32 read-write n 0x0 0x0 LACT_ALARM_EN 10 1 LACT_AUTORELOAD 29 1 LACT_CPST_EN 8 1 LACT_DIVIDER 13 16 LACT_EDGE_INT_EN 12 1 LACT_EN 31 1 LACT_INCREASE 30 1 LACT_LAC_EN 9 1 LACT_LEVEL_INT_EN 11 1 LACT_RTC_ONLY 7 1 LACTHI TIMG_LACTHI 0x7C 32 read-write n 0x0 0x0 LACT_HI 0 32 LACTLO TIMG_LACTLO 0x78 32 read-write n 0x0 0x0 LACT_LO 0 32 LACTLOAD TIMG_LACTLOAD 0x94 32 read-write n 0x0 0x0 LACT_LOAD 0 32 LACTLOADHI TIMG_LACTLOADHI 0x90 32 read-write n 0x0 0x0 LACT_LOAD_HI 0 32 LACTLOADLO TIMG_LACTLOADLO 0x8C 32 read-write n 0x0 0x0 LACT_LOAD_LO 0 32 LACTRTC TIMG_LACTRTC 0x74 32 read-write n 0x0 0x0 LACT_RTC_STEP_LEN 6 26 LACTUPDATE TIMG_LACTUPDATE 0x80 32 read-write n 0x0 0x0 LACT_UPDATE 0 32 NTIMERS_DATE TIMG_NTIMERS_DATE 0xF8 32 read-write n 0x0 0x0 NTIMERS_DATE 0 28 RTCCALICFG TIMG_RTCCALICFG 0x68 32 read-write n 0x0 0x0 CLK_SEL 13 2 CLK_SEL read-write RTC_MUX Select RTC slow clock 0 CK8M_D256 Internal 8 MHz RC oscillator, divided by 256 1 XTAL32K Select XTAL_32K 2 MAX 16 15 RDY 15 1 START 31 1 START_CYCLING 12 1 RTCCALICFG1 TIMG_RTCCALICFG1 0x6C 32 read-write n 0x0 0x0 VALUE 7 25 T0ALARMHI TIMG_T0ALARMHI 0x14 32 read-write n 0x0 0x0 T0_ALARM_HI 0 32 T0ALARMLO TIMG_T0ALARMLO 0x10 32 read-write n 0x0 0x0 T0_ALARM_LO 0 32 T0CONFIG TIMG_T0CONFIG 0x0 32 read-write n 0x0 0x0 T0_ALARM_EN 10 1 T0_AUTORELOAD 29 1 T0_DIVIDER 13 16 T0_EDGE_INT_EN 12 1 T0_EN 31 1 T0_INCREASE 30 1 T0_LEVEL_INT_EN 11 1 T0HI TIMG_T0HI 0x8 32 read-write n 0x0 0x0 T0_HI 0 32 T0LO TIMG_T0LO 0x4 32 read-write n 0x0 0x0 T0_LO 0 32 T0LOAD TIMG_T0LOAD 0x20 32 read-write n 0x0 0x0 T0_LOAD 0 32 T0LOADHI TIMG_T0LOADHI 0x1C 32 read-write n 0x0 0x0 T0_LOAD_HI 0 32 T0LOADLO TIMG_T0LOADLO 0x18 32 read-write n 0x0 0x0 T0_LOAD_LO 0 32 T0UPDATE TIMG_T0UPDATE 0xC 32 read-write n 0x0 0x0 T0_UPDATE 0 32 T1ALARMHI TIMG_T1ALARMHI 0x38 32 read-write n 0x0 0x0 T1_ALARM_HI 0 32 T1ALARMLO TIMG_T1ALARMLO 0x34 32 read-write n 0x0 0x0 T1_ALARM_LO 0 32 T1CONFIG TIMG_T1CONFIG 0x24 32 read-write n 0x0 0x0 T1_ALARM_EN 10 1 T1_AUTORELOAD 29 1 T1_DIVIDER 13 16 T1_EDGE_INT_EN 12 1 T1_EN 31 1 T1_INCREASE 30 1 T1_LEVEL_INT_EN 11 1 T1HI TIMG_T1HI 0x2C 32 read-write n 0x0 0x0 T1_HI 0 32 T1LO TIMG_T1LO 0x28 32 read-write n 0x0 0x0 T1_LO 0 32 T1LOAD TIMG_T1LOAD 0x44 32 read-write n 0x0 0x0 T1_LOAD 0 32 T1LOADHI TIMG_T1LOADHI 0x40 32 read-write n 0x0 0x0 T1_LOAD_HI 0 32 T1LOADLO TIMG_T1LOADLO 0x3C 32 read-write n 0x0 0x0 T1_LOAD_LO 0 32 T1UPDATE TIMG_T1UPDATE 0x30 32 read-write n 0x0 0x0 T1_UPDATE 0 32 TIMGCLK TIMGCLK 0xFC 32 read-write n 0x0 0x0 CLK_EN 31 1 WDTCONFIG0 TIMG_WDTCONFIG0 0x48 32 read-write n 0x0 0x0 WDT_CPU_RESET_LENGTH 18 3 WDT_CPU_RESET_LENGTH read-write T100ns 100ns 0 T200ns 200ns 1 T300ns 300ns 2 T400ns 400ns 3 T500ns 500ns 4 T800ns 800ns 5 T1600ns 1600ns 6 T3200ns 3200ns 7 WDT_EDGE_INT_EN 22 1 WDT_EN 31 1 WDT_FLASHBOOT_MOD_EN 14 1 WDT_LEVEL_INT_EN 21 1 WDT_STG0 29 2 WDT_STG0 read-write Disable Disabled 0 Interrupt Trigger an interrupt 1 ResetCPU Reset CPU core 2 ResetSystem Reset System 3 WDT_STG1 27 2 WDT_STG2 25 2 WDT_STG3 23 2 WDT_SYS_RESET_LENGTH 15 3 WDTCONFIG1 TIMG_WDTCONFIG1 0x4C 32 read-write n 0x0 0x0 WDT_CLK_PRESCALE 16 16 WDTCONFIG2 TIMG_WDTCONFIG2 0x50 32 read-write n 0x0 0x0 WDT_STG0_HOLD 0 32 WDTCONFIG3 TIMG_WDTCONFIG3 0x54 32 read-write n 0x0 0x0 WDT_STG1_HOLD 0 32 WDTCONFIG4 TIMG_WDTCONFIG4 0x58 32 read-write n 0x0 0x0 WDT_STG2_HOLD 0 32 WDTCONFIG5 TIMG_WDTCONFIG5 0x5C 32 read-write n 0x0 0x0 WDT_STG3_HOLD 0 32 WDTFEED TIMG_WDTFEED 0x60 32 read-write n 0x0 0x0 WDT_FEED 0 32 WDTWPROTECT TIMG_WDTWPROTECT 0x64 32 read-write n 0x0 0x0 WDT_WKEY 0 32 TIMG0 TIMG 0x0 0x0 0x580 registers n INT_CLR_TIMERS TIMG_INT_CLR_TIMERS 0xA4 32 read-write n 0x0 0x0 LACT_INT_CLR 3 1 T0_INT_CLR 0 1 T1_INT_CLR 1 1 WDT_INT_CLR 2 1 INT_ENA_TIMERS TIMG_INT_ENA_TIMERS 0x98 32 read-write n 0x0 0x0 LACT_INT_ENA 3 1 T0_INT_ENA 0 1 T1_INT_ENA 1 1 WDT_INT_ENA 2 1 INT_RAW_TIMERS TIMG_INT_RAW_TIMERS 0x9C 32 read-write n 0x0 0x0 LACT_INT_RAW 3 1 T0_INT_RAW 0 1 T1_INT_RAW 1 1 WDT_INT_RAW 2 1 INT_ST_TIMERS TIMG_INT_ST_TIMERS 0xA0 32 read-write n 0x0 0x0 LACT_INT_ST 3 1 T0_INT_ST 0 1 T1_INT_ST 1 1 WDT_INT_ST 2 1 LACTALARMHI TIMG_LACTALARMHI 0x88 32 read-write n 0x0 0x0 LACT_ALARM_HI 0 32 LACTALARMLO TIMG_LACTALARMLO 0x84 32 read-write n 0x0 0x0 LACT_ALARM_LO 0 32 LACTCONFIG TIMG_LACTCONFIG 0x70 32 read-write n 0x0 0x0 LACT_ALARM_EN 10 1 LACT_AUTORELOAD 29 1 LACT_CPST_EN 8 1 LACT_DIVIDER 13 16 LACT_EDGE_INT_EN 12 1 LACT_EN 31 1 LACT_INCREASE 30 1 LACT_LAC_EN 9 1 LACT_LEVEL_INT_EN 11 1 LACT_RTC_ONLY 7 1 LACTHI TIMG_LACTHI 0x7C 32 read-write n 0x0 0x0 LACT_HI 0 32 LACTLO TIMG_LACTLO 0x78 32 read-write n 0x0 0x0 LACT_LO 0 32 LACTLOAD TIMG_LACTLOAD 0x94 32 read-write n 0x0 0x0 LACT_LOAD 0 32 LACTLOADHI TIMG_LACTLOADHI 0x90 32 read-write n 0x0 0x0 LACT_LOAD_HI 0 32 LACTLOADLO TIMG_LACTLOADLO 0x8C 32 read-write n 0x0 0x0 LACT_LOAD_LO 0 32 LACTRTC TIMG_LACTRTC 0x74 32 read-write n 0x0 0x0 LACT_RTC_STEP_LEN 6 26 LACTUPDATE TIMG_LACTUPDATE 0x80 32 read-write n 0x0 0x0 LACT_UPDATE 0 32 NTIMERS_DATE TIMG_NTIMERS_DATE 0xF8 32 read-write n 0x0 0x0 NTIMERS_DATE 0 28 RTCCALICFG TIMG_RTCCALICFG 0x68 32 read-write n 0x0 0x0 CLK_SEL 13 2 CLK_SEL read-write RTC_MUX Select RTC slow clock 0 CK8M_D256 Internal 8 MHz RC oscillator, divided by 256 1 XTAL32K Select XTAL_32K 2 MAX 16 15 RDY 15 1 START 31 1 START_CYCLING 12 1 RTCCALICFG1 TIMG_RTCCALICFG1 0x6C 32 read-write n 0x0 0x0 VALUE 7 25 T0ALARMHI TIMG_T0ALARMHI 0x14 32 read-write n 0x0 0x0 T0_ALARM_HI 0 32 T0ALARMLO TIMG_T0ALARMLO 0x10 32 read-write n 0x0 0x0 T0_ALARM_LO 0 32 T0CONFIG TIMG_T0CONFIG 0x0 32 read-write n 0x0 0x0 T0_ALARM_EN 10 1 T0_AUTORELOAD 29 1 T0_DIVIDER 13 16 T0_EDGE_INT_EN 12 1 T0_EN 31 1 T0_INCREASE 30 1 T0_LEVEL_INT_EN 11 1 T0HI TIMG_T0HI 0x8 32 read-write n 0x0 0x0 T0_HI 0 32 T0LO TIMG_T0LO 0x4 32 read-write n 0x0 0x0 T0_LO 0 32 T0LOAD TIMG_T0LOAD 0x20 32 read-write n 0x0 0x0 T0_LOAD 0 32 T0LOADHI TIMG_T0LOADHI 0x1C 32 read-write n 0x0 0x0 T0_LOAD_HI 0 32 T0LOADLO TIMG_T0LOADLO 0x18 32 read-write n 0x0 0x0 T0_LOAD_LO 0 32 T0UPDATE TIMG_T0UPDATE 0xC 32 read-write n 0x0 0x0 T0_UPDATE 0 32 T1ALARMHI TIMG_T1ALARMHI 0x38 32 read-write n 0x0 0x0 T1_ALARM_HI 0 32 T1ALARMLO TIMG_T1ALARMLO 0x34 32 read-write n 0x0 0x0 T1_ALARM_LO 0 32 T1CONFIG TIMG_T1CONFIG 0x24 32 read-write n 0x0 0x0 T1_ALARM_EN 10 1 T1_AUTORELOAD 29 1 T1_DIVIDER 13 16 T1_EDGE_INT_EN 12 1 T1_EN 31 1 T1_INCREASE 30 1 T1_LEVEL_INT_EN 11 1 T1HI TIMG_T1HI 0x2C 32 read-write n 0x0 0x0 T1_HI 0 32 T1LO TIMG_T1LO 0x28 32 read-write n 0x0 0x0 T1_LO 0 32 T1LOAD TIMG_T1LOAD 0x44 32 read-write n 0x0 0x0 T1_LOAD 0 32 T1LOADHI TIMG_T1LOADHI 0x40 32 read-write n 0x0 0x0 T1_LOAD_HI 0 32 T1LOADLO TIMG_T1LOADLO 0x3C 32 read-write n 0x0 0x0 T1_LOAD_LO 0 32 T1UPDATE TIMG_T1UPDATE 0x30 32 read-write n 0x0 0x0 T1_UPDATE 0 32 TIMGCLK TIMGCLK 0xFC 32 read-write n 0x0 0x0 CLK_EN 31 1 WDTCONFIG0 TIMG_WDTCONFIG0 0x48 32 read-write n 0x0 0x0 WDT_CPU_RESET_LENGTH 18 3 WDT_CPU_RESET_LENGTH read-write T100ns 100ns 0 T200ns 200ns 1 T300ns 300ns 2 T400ns 400ns 3 T500ns 500ns 4 T800ns 800ns 5 T1600ns 1600ns 6 T3200ns 3200ns 7 WDT_EDGE_INT_EN 22 1 WDT_EN 31 1 WDT_FLASHBOOT_MOD_EN 14 1 WDT_LEVEL_INT_EN 21 1 WDT_STG0 29 2 WDT_STG0 read-write Disable Disabled 0 Interrupt Trigger an interrupt 1 ResetCPU Reset CPU core 2 ResetSystem Reset System 3 WDT_STG1 27 2 WDT_STG2 25 2 WDT_STG3 23 2 WDT_SYS_RESET_LENGTH 15 3 WDTCONFIG1 TIMG_WDTCONFIG1 0x4C 32 read-write n 0x0 0x0 WDT_CLK_PRESCALE 16 16 WDTCONFIG2 TIMG_WDTCONFIG2 0x50 32 read-write n 0x0 0x0 WDT_STG0_HOLD 0 32 WDTCONFIG3 TIMG_WDTCONFIG3 0x54 32 read-write n 0x0 0x0 WDT_STG1_HOLD 0 32 WDTCONFIG4 TIMG_WDTCONFIG4 0x58 32 read-write n 0x0 0x0 WDT_STG2_HOLD 0 32 WDTCONFIG5 TIMG_WDTCONFIG5 0x5C 32 read-write n 0x0 0x0 WDT_STG3_HOLD 0 32 WDTFEED TIMG_WDTFEED 0x60 32 read-write n 0x0 0x0 WDT_FEED 0 32 WDTWPROTECT TIMG_WDTWPROTECT 0x64 32 read-write n 0x0 0x0 WDT_WKEY 0 32 TIMG1 TIMG 0x0 0x0 0x580 registers n INT_CLR_TIMERS TIMG_INT_CLR_TIMERS 0xA4 32 read-write n 0x0 0x0 LACT_INT_CLR 3 1 T0_INT_CLR 0 1 T1_INT_CLR 1 1 WDT_INT_CLR 2 1 INT_ENA_TIMERS TIMG_INT_ENA_TIMERS 0x98 32 read-write n 0x0 0x0 LACT_INT_ENA 3 1 T0_INT_ENA 0 1 T1_INT_ENA 1 1 WDT_INT_ENA 2 1 INT_RAW_TIMERS TIMG_INT_RAW_TIMERS 0x9C 32 read-write n 0x0 0x0 LACT_INT_RAW 3 1 T0_INT_RAW 0 1 T1_INT_RAW 1 1 WDT_INT_RAW 2 1 INT_ST_TIMERS TIMG_INT_ST_TIMERS 0xA0 32 read-write n 0x0 0x0 LACT_INT_ST 3 1 T0_INT_ST 0 1 T1_INT_ST 1 1 WDT_INT_ST 2 1 LACTALARMHI TIMG_LACTALARMHI 0x88 32 read-write n 0x0 0x0 LACT_ALARM_HI 0 32 LACTALARMLO TIMG_LACTALARMLO 0x84 32 read-write n 0x0 0x0 LACT_ALARM_LO 0 32 LACTCONFIG TIMG_LACTCONFIG 0x70 32 read-write n 0x0 0x0 LACT_ALARM_EN 10 1 LACT_AUTORELOAD 29 1 LACT_CPST_EN 8 1 LACT_DIVIDER 13 16 LACT_EDGE_INT_EN 12 1 LACT_EN 31 1 LACT_INCREASE 30 1 LACT_LAC_EN 9 1 LACT_LEVEL_INT_EN 11 1 LACT_RTC_ONLY 7 1 LACTHI TIMG_LACTHI 0x7C 32 read-write n 0x0 0x0 LACT_HI 0 32 LACTLO TIMG_LACTLO 0x78 32 read-write n 0x0 0x0 LACT_LO 0 32 LACTLOAD TIMG_LACTLOAD 0x94 32 read-write n 0x0 0x0 LACT_LOAD 0 32 LACTLOADHI TIMG_LACTLOADHI 0x90 32 read-write n 0x0 0x0 LACT_LOAD_HI 0 32 LACTLOADLO TIMG_LACTLOADLO 0x8C 32 read-write n 0x0 0x0 LACT_LOAD_LO 0 32 LACTRTC TIMG_LACTRTC 0x74 32 read-write n 0x0 0x0 LACT_RTC_STEP_LEN 6 26 LACTUPDATE TIMG_LACTUPDATE 0x80 32 read-write n 0x0 0x0 LACT_UPDATE 0 32 NTIMERS_DATE TIMG_NTIMERS_DATE 0xF8 32 read-write n 0x0 0x0 NTIMERS_DATE 0 28 RTCCALICFG TIMG_RTCCALICFG 0x68 32 read-write n 0x0 0x0 CLK_SEL 13 2 CLK_SEL read-write RTC_MUX Select RTC slow clock 0 CK8M_D256 Internal 8 MHz RC oscillator, divided by 256 1 XTAL32K Select XTAL_32K 2 MAX 16 15 RDY 15 1 START 31 1 START_CYCLING 12 1 RTCCALICFG1 TIMG_RTCCALICFG1 0x6C 32 read-write n 0x0 0x0 VALUE 7 25 T0ALARMHI TIMG_T0ALARMHI 0x14 32 read-write n 0x0 0x0 T0_ALARM_HI 0 32 T0ALARMLO TIMG_T0ALARMLO 0x10 32 read-write n 0x0 0x0 T0_ALARM_LO 0 32 T0CONFIG TIMG_T0CONFIG 0x0 32 read-write n 0x0 0x0 T0_ALARM_EN 10 1 T0_AUTORELOAD 29 1 T0_DIVIDER 13 16 T0_EDGE_INT_EN 12 1 T0_EN 31 1 T0_INCREASE 30 1 T0_LEVEL_INT_EN 11 1 T0HI TIMG_T0HI 0x8 32 read-write n 0x0 0x0 T0_HI 0 32 T0LO TIMG_T0LO 0x4 32 read-write n 0x0 0x0 T0_LO 0 32 T0LOAD TIMG_T0LOAD 0x20 32 read-write n 0x0 0x0 T0_LOAD 0 32 T0LOADHI TIMG_T0LOADHI 0x1C 32 read-write n 0x0 0x0 T0_LOAD_HI 0 32 T0LOADLO TIMG_T0LOADLO 0x18 32 read-write n 0x0 0x0 T0_LOAD_LO 0 32 T0UPDATE TIMG_T0UPDATE 0xC 32 read-write n 0x0 0x0 T0_UPDATE 0 32 T1ALARMHI TIMG_T1ALARMHI 0x38 32 read-write n 0x0 0x0 T1_ALARM_HI 0 32 T1ALARMLO TIMG_T1ALARMLO 0x34 32 read-write n 0x0 0x0 T1_ALARM_LO 0 32 T1CONFIG TIMG_T1CONFIG 0x24 32 read-write n 0x0 0x0 T1_ALARM_EN 10 1 T1_AUTORELOAD 29 1 T1_DIVIDER 13 16 T1_EDGE_INT_EN 12 1 T1_EN 31 1 T1_INCREASE 30 1 T1_LEVEL_INT_EN 11 1 T1HI TIMG_T1HI 0x2C 32 read-write n 0x0 0x0 T1_HI 0 32 T1LO TIMG_T1LO 0x28 32 read-write n 0x0 0x0 T1_LO 0 32 T1LOAD TIMG_T1LOAD 0x44 32 read-write n 0x0 0x0 T1_LOAD 0 32 T1LOADHI TIMG_T1LOADHI 0x40 32 read-write n 0x0 0x0 T1_LOAD_HI 0 32 T1LOADLO TIMG_T1LOADLO 0x3C 32 read-write n 0x0 0x0 T1_LOAD_LO 0 32 T1UPDATE TIMG_T1UPDATE 0x30 32 read-write n 0x0 0x0 T1_UPDATE 0 32 TIMGCLK TIMGCLK 0xFC 32 read-write n 0x0 0x0 CLK_EN 31 1 WDTCONFIG0 TIMG_WDTCONFIG0 0x48 32 read-write n 0x0 0x0 WDT_CPU_RESET_LENGTH 18 3 WDT_CPU_RESET_LENGTH read-write T100ns 100ns 0 T200ns 200ns 1 T300ns 300ns 2 T400ns 400ns 3 T500ns 500ns 4 T800ns 800ns 5 T1600ns 1600ns 6 T3200ns 3200ns 7 WDT_EDGE_INT_EN 22 1 WDT_EN 31 1 WDT_FLASHBOOT_MOD_EN 14 1 WDT_LEVEL_INT_EN 21 1 WDT_STG0 29 2 WDT_STG0 read-write Disable Disabled 0 Interrupt Trigger an interrupt 1 ResetCPU Reset CPU core 2 ResetSystem Reset System 3 WDT_STG1 27 2 WDT_STG2 25 2 WDT_STG3 23 2 WDT_SYS_RESET_LENGTH 15 3 WDTCONFIG1 TIMG_WDTCONFIG1 0x4C 32 read-write n 0x0 0x0 WDT_CLK_PRESCALE 16 16 WDTCONFIG2 TIMG_WDTCONFIG2 0x50 32 read-write n 0x0 0x0 WDT_STG0_HOLD 0 32 WDTCONFIG3 TIMG_WDTCONFIG3 0x54 32 read-write n 0x0 0x0 WDT_STG1_HOLD 0 32 WDTCONFIG4 TIMG_WDTCONFIG4 0x58 32 read-write n 0x0 0x0 WDT_STG2_HOLD 0 32 WDTCONFIG5 TIMG_WDTCONFIG5 0x5C 32 read-write n 0x0 0x0 WDT_STG3_HOLD 0 32 WDTFEED TIMG_WDTFEED 0x60 32 read-write n 0x0 0x0 WDT_FEED 0 32 WDTWPROTECT TIMG_WDTWPROTECT 0x64 32 read-write n 0x0 0x0 WDT_WKEY 0 32 UART UART 0x0 0x0 0x400 UART registers n 0x200C0000 0x4 TX FIFO n SPI0_INTR interrupt of SPI0, level, SPI0 is for Cache Access, do not use this 28 SPI1_INTR interrupt of SPI1, level, SPI1 is for flash read/write, do not use this 29 SPI2_INTR interrupt of SPI2, level 30 SPI3_INTR interrupt of SPI3, level 31 UART0_INTR interrupt of UART0, level 34 UART1_INTR interrupt of UART1, level 35 UART2_INTR interrupt of UART2, level 36 AT_CMD_CHAR UART_AT_CMD_CHAR 0x54 32 read-write n 0x0 0x0 AT_CMD_CHAR 0 8 CHAR_NUM 8 8 AT_CMD_GAPTOUT UART_AT_CMD_GAPTOUT 0x50 32 read-write n 0x0 0x0 RX_GAP_TOUT 0 24 AT_CMD_POSTCNT UART_AT_CMD_POSTCNT 0x4C 32 read-write n 0x0 0x0 POST_IDLE_NUM 0 24 AT_CMD_PRECNT UART_AT_CMD_PRECNT 0x48 32 read-write n 0x0 0x0 PRE_IDLE_NUM 0 24 AUTOBAUD UART_AUTOBAUD 0x18 32 read-write n 0x0 0x0 AUTOBAUD_EN 0 1 GLITCH_FILT 8 8 CLKDIV UART_CLKDIV 0x14 32 read-write n 0x0 0x0 CLKDIV 0 20 CLKDIV_FRAG 20 4 CONF0 UART_CONF0 0x20 32 read-write n 0x0 0x0 BIT_NUM 2 2 UART_BIT_NUM read-write DATA_BITS_5 5 data bits 0 DATA_BITS_6 6 data bits 1 DATA_BITS_7 7 data bits 2 DATA_BITS_8 8 data bits 3 CLK_EN 25 1 CTS_INV 20 1 DSR_INV 21 1 DTR_INV 24 1 ERR_WR_MASK 26 1 IRDA_DPLX 9 1 IRDA_EN 16 1 IRDA_RX_INV 13 1 IRDA_TX_EN 10 1 IRDA_TX_INV 12 1 IRDA_WCTL 11 1 LOOPBACK 14 1 PARITY 0 1 PARITY_EN 1 1 RTS_INV 23 1 RXD_INV 19 1 RXFIFO_RST 17 1 STOP_BIT_NUM 4 2 UART_STOP_BIT_NUM read-write STOP_BITS_1 1 stop bits 1 STOP_BITS_1p5 1.5 stop bits 2 STOP_BITS_2 2 stop bits 3 SW_DTR 7 1 SW_RTS 6 1 TICK_REF_ALWAYS_ON 27 1 TXD_BRK 8 1 TXD_INV 22 1 TXFIFO_RST 18 1 TX_FLOW_EN 15 1 CONF1 UART_CONF1 0x24 32 read-write n 0x0 0x0 RXFIFO_FULL_THRHD 0 7 RX_FLOW_EN 23 1 RX_FLOW_THRHD 16 7 RX_TOUT_EN 31 1 RX_TOUT_THRHD 24 7 TXFIFO_EMPTY_THRHD 8 7 DATE UART_DATE 0x78 32 read-write n 0x0 0x0 DATE 0 32 FLOW_CONF UART_FLOW_CONF 0x34 32 read-write n 0x0 0x0 FORCE_XOFF 3 1 FORCE_XON 2 1 SEND_XOFF 5 1 SEND_XON 4 1 SW_FLOW_CON_EN 0 1 XONOFF_DEL 1 1 HIGHPULSE UART_HIGHPULSE 0x2C 32 read-write n 0x0 0x0 HIGHPULSE_MIN_CNT 0 20 ID UART_ID 0x7C 32 read-write n 0x0 0x0 ID 0 32 IDLE_CONF UART_IDLE_CONF 0x40 32 read-write n 0x0 0x0 RX_IDLE_THRHD 0 10 TX_BRK_NUM 20 8 TX_IDLE_NUM 10 10 INT_CLR UART_INT_CLR 0x10 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_CLR 18 1 BRK_DET_INT_CLR 7 1 CTS_CHG_INT_CLR 6 1 DSR_CHG_INT_CLR 5 1 FRM_ERR_INT_CLR 3 1 GLITCH_DET_INT_CLR 11 1 PARITY_ERR_INT_CLR 2 1 RS485_CLASH_INT_CLR 17 1 RS485_FRM_ERR_INT_CLR 16 1 RS485_PARITY_ERR_INT_CLR 15 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 4 1 RXFIFO_TOUT_INT_CLR 8 1 SW_XOFF_INT_CLR 10 1 SW_XON_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_BRK_DONE_INT_CLR 12 1 TX_BRK_IDLE_DONE_INT_CLR 13 1 TX_DONE_INT_CLR 14 1 INT_ENA UART_INT_ENA 0xC 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ENA 18 1 BRK_DET_INT_ENA 7 1 CTS_CHG_INT_ENA 6 1 DSR_CHG_INT_ENA 5 1 FRM_ERR_INT_ENA 3 1 GLITCH_DET_INT_ENA 11 1 PARITY_ERR_INT_ENA 2 1 RS485_CLASH_INT_ENA 17 1 RS485_FRM_ERR_INT_ENA 16 1 RS485_PARITY_ERR_INT_ENA 15 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 4 1 RXFIFO_TOUT_INT_ENA 8 1 SW_XOFF_INT_ENA 10 1 SW_XON_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_BRK_DONE_INT_ENA 12 1 TX_BRK_IDLE_DONE_INT_ENA 13 1 TX_DONE_INT_ENA 14 1 INT_RAW UART_INT_RAW 0x4 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_RAW 18 1 BRK_DET_INT_RAW 7 1 CTS_CHG_INT_RAW 6 1 DSR_CHG_INT_RAW 5 1 FRM_ERR_INT_RAW 3 1 GLITCH_DET_INT_RAW 11 1 PARITY_ERR_INT_RAW 2 1 RS485_CLASH_INT_RAW 17 1 RS485_FRM_ERR_INT_RAW 16 1 RS485_PARITY_ERR_INT_RAW 15 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 4 1 RXFIFO_TOUT_INT_RAW 8 1 SW_XOFF_INT_RAW 10 1 SW_XON_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_BRK_DONE_INT_RAW 12 1 TX_BRK_IDLE_DONE_INT_RAW 13 1 TX_DONE_INT_RAW 14 1 INT_ST UART_INT_ST 0x8 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ST 18 1 BRK_DET_INT_ST 7 1 CTS_CHG_INT_ST 6 1 DSR_CHG_INT_ST 5 1 FRM_ERR_INT_ST 3 1 GLITCH_DET_INT_ST 11 1 PARITY_ERR_INT_ST 2 1 RS485_CLASH_INT_ST 17 1 RS485_FRM_ERR_INT_ST 16 1 RS485_PARITY_ERR_INT_ST 15 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 4 1 RXFIFO_TOUT_INT_ST 8 1 SW_XOFF_INT_ST 10 1 SW_XON_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_BRK_DONE_INT_ST 12 1 TX_BRK_IDLE_DONE_INT_ST 13 1 TX_DONE_INT_ST 14 1 LOWPULSE UART_LOWPULSE 0x28 32 read-write n 0x0 0x0 LOWPULSE_MIN_CNT 0 20 MEM_CNT_STATUS UART_MEM_CNT_STATUS 0x64 32 read-write n 0x0 0x0 RX_MEM_CNT 0 3 TX_MEM_CNT 3 3 MEM_CONF UART_MEM_CONF 0x58 32 read-write n 0x0 0x0 MEM_PD 0 1 RX_FLOW_THRHD_H3 15 3 RX_MEM_FULL_THRHD 25 3 RX_SIZE 3 4 RX_TOUT_THRHD_H3 18 3 TX_MEM_EMPTY_THRHD 28 3 TX_SIZE 7 4 XOFF_THRESHOLD_H2 23 2 XON_THRESHOLD_H2 21 2 MEM_RX_STATUS UART_MEM_RX_STATUS 0x60 32 read-write n 0x0 0x0 MEM_RX_RD_ADDR 2 11 MEM_RX_STATUS 0 24 MEM_RX_WR_ADDR 13 11 MEM_TX_STATUS UART_MEM_TX_STATUS 0x5C 32 read-write n 0x0 0x0 MEM_TX_STATUS 0 24 NEGPULSE UART_NEGPULSE 0x6C 32 read-write n 0x0 0x0 NEGEDGE_MIN_CNT 0 20 POSPULSE UART_POSPULSE 0x68 32 read-write n 0x0 0x0 POSEDGE_MIN_CNT 0 20 RS485_CONF UART_RS485_CONF 0x44 32 read-write n 0x0 0x0 DL0_EN 1 1 DL1_EN 2 1 RS485RXBY_TX_EN 4 1 RS485TX_RX_EN 3 1 RS485_EN 0 1 RS485_RX_DLY_NUM 5 1 RS485_TX_DLY_NUM 6 4 RXD_CNT UART_RXD_CNT 0x30 32 read-write n 0x0 0x0 RXD_EDGE_CNT 0 10 RX_FIFO UART_RX_FIFO 0x0 8 read-only n 0x0 0x0 DATA TX FIFO Data 0 8 SLEEP_CONF UART_SLEEP_CONF 0x38 32 read-write n 0x0 0x0 ACTIVE_THRESHOLD 0 10 STATUS UART_STATUS 0x1C 32 read-write n 0x0 0x0 CTSN 14 1 DSRN 13 1 DTRN 29 1 RTSN 30 1 RXD 15 1 RXFIFO_CNT 0 8 ST_URX_OUT 8 4 UART_ST_URX_OUT read-write RX_IDLE RX_IDLE 0 RX_STRT RX_STRT 1 RX_PRTY RX_PRTY 10 RX_STP1 RX_STP1 11 RX_STP2 RX_STP2 12 RX_DL1 RX_DL1 13 RX_DAT0 RX_DAT0 2 RX_DAT1 RX_DAT1 3 RX_DAT2 RX_DAT2 4 RX_DAT3 RX_DAT3 5 RX_DAT4 RX_DAT4 6 RX_DAT5 RX_DAT5 7 RX_DAT6 RX_DAT6 8 RX_DAT7 RX_DAT7 9 ST_UTX_OUT 24 4 UART_ST_UTX_OUT read-write TX_IDLE TX_IDLE 0 TX_STRT TX_STRT 1 TX_PRTY TX_PRTY 10 TX_STP1 TX_STP1 11 TX_STP2 TX_STP2 12 TX_DL1 TX_DL1 14 TX_DAT0 TX_DAT0 2 TX_DAT1 TX_DAT1 3 TX_DAT2 TX_DAT2 4 TX_DAT3 TX_DAT3 5 TX_DAT4 TX_DAT4 6 TX_DAT5 TX_DAT5 7 TX_DAT6 TX_DAT6 8 TX_DAT7 TX_DAT7 9 TXD 31 1 TXFIFO_CNT 16 8 SWFC_CONF UART_SWFC_CONF 0x3C 32 read-write n 0x0 0x0 XOFF_CHAR 24 8 XOFF_THRESHOLD 8 8 XON_CHAR 16 8 XON_THRESHOLD 0 8 TX_FIFO UART_TX_FIFO 0x200C0000 8 write-only n 0x0 0x0 DATA TX FIFO Data 0 8 UART0 UART 0x0 0x0 0x400 UART registers n 0x200C0000 0x4 TX FIFO n AT_CMD_CHAR UART_AT_CMD_CHAR 0x54 32 read-write n 0x0 0x0 AT_CMD_CHAR 0 8 CHAR_NUM 8 8 AT_CMD_GAPTOUT UART_AT_CMD_GAPTOUT 0x50 32 read-write n 0x0 0x0 RX_GAP_TOUT 0 24 AT_CMD_POSTCNT UART_AT_CMD_POSTCNT 0x4C 32 read-write n 0x0 0x0 POST_IDLE_NUM 0 24 AT_CMD_PRECNT UART_AT_CMD_PRECNT 0x48 32 read-write n 0x0 0x0 PRE_IDLE_NUM 0 24 AUTOBAUD UART_AUTOBAUD 0x18 32 read-write n 0x0 0x0 AUTOBAUD_EN 0 1 GLITCH_FILT 8 8 CLKDIV UART_CLKDIV 0x14 32 read-write n 0x0 0x0 CLKDIV 0 20 CLKDIV_FRAG 20 4 CONF0 UART_CONF0 0x20 32 read-write n 0x0 0x0 BIT_NUM 2 2 UART_BIT_NUM read-write DATA_BITS_5 5 data bits 0 DATA_BITS_6 6 data bits 1 DATA_BITS_7 7 data bits 2 DATA_BITS_8 8 data bits 3 CLK_EN 25 1 CTS_INV 20 1 DSR_INV 21 1 DTR_INV 24 1 ERR_WR_MASK 26 1 IRDA_DPLX 9 1 IRDA_EN 16 1 IRDA_RX_INV 13 1 IRDA_TX_EN 10 1 IRDA_TX_INV 12 1 IRDA_WCTL 11 1 LOOPBACK 14 1 PARITY 0 1 PARITY_EN 1 1 RTS_INV 23 1 RXD_INV 19 1 RXFIFO_RST 17 1 STOP_BIT_NUM 4 2 UART_STOP_BIT_NUM read-write STOP_BITS_1 1 stop bits 1 STOP_BITS_1p5 1.5 stop bits 2 STOP_BITS_2 2 stop bits 3 SW_DTR 7 1 SW_RTS 6 1 TICK_REF_ALWAYS_ON 27 1 TXD_BRK 8 1 TXD_INV 22 1 TXFIFO_RST 18 1 TX_FLOW_EN 15 1 CONF1 UART_CONF1 0x24 32 read-write n 0x0 0x0 RXFIFO_FULL_THRHD 0 7 RX_FLOW_EN 23 1 RX_FLOW_THRHD 16 7 RX_TOUT_EN 31 1 RX_TOUT_THRHD 24 7 TXFIFO_EMPTY_THRHD 8 7 DATE UART_DATE 0x78 32 read-write n 0x0 0x0 DATE 0 32 FLOW_CONF UART_FLOW_CONF 0x34 32 read-write n 0x0 0x0 FORCE_XOFF 3 1 FORCE_XON 2 1 SEND_XOFF 5 1 SEND_XON 4 1 SW_FLOW_CON_EN 0 1 XONOFF_DEL 1 1 HIGHPULSE UART_HIGHPULSE 0x2C 32 read-write n 0x0 0x0 HIGHPULSE_MIN_CNT 0 20 ID UART_ID 0x7C 32 read-write n 0x0 0x0 ID 0 32 IDLE_CONF UART_IDLE_CONF 0x40 32 read-write n 0x0 0x0 RX_IDLE_THRHD 0 10 TX_BRK_NUM 20 8 TX_IDLE_NUM 10 10 INT_CLR UART_INT_CLR 0x10 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_CLR 18 1 BRK_DET_INT_CLR 7 1 CTS_CHG_INT_CLR 6 1 DSR_CHG_INT_CLR 5 1 FRM_ERR_INT_CLR 3 1 GLITCH_DET_INT_CLR 11 1 PARITY_ERR_INT_CLR 2 1 RS485_CLASH_INT_CLR 17 1 RS485_FRM_ERR_INT_CLR 16 1 RS485_PARITY_ERR_INT_CLR 15 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 4 1 RXFIFO_TOUT_INT_CLR 8 1 SW_XOFF_INT_CLR 10 1 SW_XON_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_BRK_DONE_INT_CLR 12 1 TX_BRK_IDLE_DONE_INT_CLR 13 1 TX_DONE_INT_CLR 14 1 INT_ENA UART_INT_ENA 0xC 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ENA 18 1 BRK_DET_INT_ENA 7 1 CTS_CHG_INT_ENA 6 1 DSR_CHG_INT_ENA 5 1 FRM_ERR_INT_ENA 3 1 GLITCH_DET_INT_ENA 11 1 PARITY_ERR_INT_ENA 2 1 RS485_CLASH_INT_ENA 17 1 RS485_FRM_ERR_INT_ENA 16 1 RS485_PARITY_ERR_INT_ENA 15 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 4 1 RXFIFO_TOUT_INT_ENA 8 1 SW_XOFF_INT_ENA 10 1 SW_XON_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_BRK_DONE_INT_ENA 12 1 TX_BRK_IDLE_DONE_INT_ENA 13 1 TX_DONE_INT_ENA 14 1 INT_RAW UART_INT_RAW 0x4 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_RAW 18 1 BRK_DET_INT_RAW 7 1 CTS_CHG_INT_RAW 6 1 DSR_CHG_INT_RAW 5 1 FRM_ERR_INT_RAW 3 1 GLITCH_DET_INT_RAW 11 1 PARITY_ERR_INT_RAW 2 1 RS485_CLASH_INT_RAW 17 1 RS485_FRM_ERR_INT_RAW 16 1 RS485_PARITY_ERR_INT_RAW 15 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 4 1 RXFIFO_TOUT_INT_RAW 8 1 SW_XOFF_INT_RAW 10 1 SW_XON_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_BRK_DONE_INT_RAW 12 1 TX_BRK_IDLE_DONE_INT_RAW 13 1 TX_DONE_INT_RAW 14 1 INT_ST UART_INT_ST 0x8 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ST 18 1 BRK_DET_INT_ST 7 1 CTS_CHG_INT_ST 6 1 DSR_CHG_INT_ST 5 1 FRM_ERR_INT_ST 3 1 GLITCH_DET_INT_ST 11 1 PARITY_ERR_INT_ST 2 1 RS485_CLASH_INT_ST 17 1 RS485_FRM_ERR_INT_ST 16 1 RS485_PARITY_ERR_INT_ST 15 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 4 1 RXFIFO_TOUT_INT_ST 8 1 SW_XOFF_INT_ST 10 1 SW_XON_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_BRK_DONE_INT_ST 12 1 TX_BRK_IDLE_DONE_INT_ST 13 1 TX_DONE_INT_ST 14 1 LOWPULSE UART_LOWPULSE 0x28 32 read-write n 0x0 0x0 LOWPULSE_MIN_CNT 0 20 MEM_CNT_STATUS UART_MEM_CNT_STATUS 0x64 32 read-write n 0x0 0x0 RX_MEM_CNT 0 3 TX_MEM_CNT 3 3 MEM_CONF UART_MEM_CONF 0x58 32 read-write n 0x0 0x0 MEM_PD 0 1 RX_FLOW_THRHD_H3 15 3 RX_MEM_FULL_THRHD 25 3 RX_SIZE 3 4 RX_TOUT_THRHD_H3 18 3 TX_MEM_EMPTY_THRHD 28 3 TX_SIZE 7 4 XOFF_THRESHOLD_H2 23 2 XON_THRESHOLD_H2 21 2 MEM_RX_STATUS UART_MEM_RX_STATUS 0x60 32 read-write n 0x0 0x0 MEM_RX_RD_ADDR 2 11 MEM_RX_STATUS 0 24 MEM_RX_WR_ADDR 13 11 MEM_TX_STATUS UART_MEM_TX_STATUS 0x5C 32 read-write n 0x0 0x0 MEM_TX_STATUS 0 24 NEGPULSE UART_NEGPULSE 0x6C 32 read-write n 0x0 0x0 NEGEDGE_MIN_CNT 0 20 POSPULSE UART_POSPULSE 0x68 32 read-write n 0x0 0x0 POSEDGE_MIN_CNT 0 20 RS485_CONF UART_RS485_CONF 0x44 32 read-write n 0x0 0x0 DL0_EN 1 1 DL1_EN 2 1 RS485RXBY_TX_EN 4 1 RS485TX_RX_EN 3 1 RS485_EN 0 1 RS485_RX_DLY_NUM 5 1 RS485_TX_DLY_NUM 6 4 RXD_CNT UART_RXD_CNT 0x30 32 read-write n 0x0 0x0 RXD_EDGE_CNT 0 10 RX_FIFO UART_RX_FIFO 0x0 8 read-only n 0x0 0x0 DATA TX FIFO Data 0 8 SLEEP_CONF UART_SLEEP_CONF 0x38 32 read-write n 0x0 0x0 ACTIVE_THRESHOLD 0 10 STATUS UART_STATUS 0x1C 32 read-write n 0x0 0x0 CTSN 14 1 DSRN 13 1 DTRN 29 1 RTSN 30 1 RXD 15 1 RXFIFO_CNT 0 8 ST_URX_OUT 8 4 UART_ST_URX_OUT read-write RX_IDLE RX_IDLE 0 RX_STRT RX_STRT 1 RX_PRTY RX_PRTY 10 RX_STP1 RX_STP1 11 RX_STP2 RX_STP2 12 RX_DL1 RX_DL1 13 RX_DAT0 RX_DAT0 2 RX_DAT1 RX_DAT1 3 RX_DAT2 RX_DAT2 4 RX_DAT3 RX_DAT3 5 RX_DAT4 RX_DAT4 6 RX_DAT5 RX_DAT5 7 RX_DAT6 RX_DAT6 8 RX_DAT7 RX_DAT7 9 ST_UTX_OUT 24 4 UART_ST_UTX_OUT read-write TX_IDLE TX_IDLE 0 TX_STRT TX_STRT 1 TX_PRTY TX_PRTY 10 TX_STP1 TX_STP1 11 TX_STP2 TX_STP2 12 TX_DL1 TX_DL1 14 TX_DAT0 TX_DAT0 2 TX_DAT1 TX_DAT1 3 TX_DAT2 TX_DAT2 4 TX_DAT3 TX_DAT3 5 TX_DAT4 TX_DAT4 6 TX_DAT5 TX_DAT5 7 TX_DAT6 TX_DAT6 8 TX_DAT7 TX_DAT7 9 TXD 31 1 TXFIFO_CNT 16 8 SWFC_CONF UART_SWFC_CONF 0x3C 32 read-write n 0x0 0x0 XOFF_CHAR 24 8 XOFF_THRESHOLD 8 8 XON_CHAR 16 8 XON_THRESHOLD 0 8 TX_FIFO UART_TX_FIFO 0x200C0000 8 write-only n 0x0 0x0 DATA TX FIFO Data 0 8 UART1 UART 0x0 0x0 0x400 UART registers n 0x200C0000 0x4 TX FIFO n AT_CMD_CHAR UART_AT_CMD_CHAR 0x54 32 read-write n 0x0 0x0 AT_CMD_CHAR 0 8 CHAR_NUM 8 8 AT_CMD_GAPTOUT UART_AT_CMD_GAPTOUT 0x50 32 read-write n 0x0 0x0 RX_GAP_TOUT 0 24 AT_CMD_POSTCNT UART_AT_CMD_POSTCNT 0x4C 32 read-write n 0x0 0x0 POST_IDLE_NUM 0 24 AT_CMD_PRECNT UART_AT_CMD_PRECNT 0x48 32 read-write n 0x0 0x0 PRE_IDLE_NUM 0 24 AUTOBAUD UART_AUTOBAUD 0x18 32 read-write n 0x0 0x0 AUTOBAUD_EN 0 1 GLITCH_FILT 8 8 CLKDIV UART_CLKDIV 0x14 32 read-write n 0x0 0x0 CLKDIV 0 20 CLKDIV_FRAG 20 4 CONF0 UART_CONF0 0x20 32 read-write n 0x0 0x0 BIT_NUM 2 2 UART_BIT_NUM read-write DATA_BITS_5 5 data bits 0 DATA_BITS_6 6 data bits 1 DATA_BITS_7 7 data bits 2 DATA_BITS_8 8 data bits 3 CLK_EN 25 1 CTS_INV 20 1 DSR_INV 21 1 DTR_INV 24 1 ERR_WR_MASK 26 1 IRDA_DPLX 9 1 IRDA_EN 16 1 IRDA_RX_INV 13 1 IRDA_TX_EN 10 1 IRDA_TX_INV 12 1 IRDA_WCTL 11 1 LOOPBACK 14 1 PARITY 0 1 PARITY_EN 1 1 RTS_INV 23 1 RXD_INV 19 1 RXFIFO_RST 17 1 STOP_BIT_NUM 4 2 UART_STOP_BIT_NUM read-write STOP_BITS_1 1 stop bits 1 STOP_BITS_1p5 1.5 stop bits 2 STOP_BITS_2 2 stop bits 3 SW_DTR 7 1 SW_RTS 6 1 TICK_REF_ALWAYS_ON 27 1 TXD_BRK 8 1 TXD_INV 22 1 TXFIFO_RST 18 1 TX_FLOW_EN 15 1 CONF1 UART_CONF1 0x24 32 read-write n 0x0 0x0 RXFIFO_FULL_THRHD 0 7 RX_FLOW_EN 23 1 RX_FLOW_THRHD 16 7 RX_TOUT_EN 31 1 RX_TOUT_THRHD 24 7 TXFIFO_EMPTY_THRHD 8 7 DATE UART_DATE 0x78 32 read-write n 0x0 0x0 DATE 0 32 FLOW_CONF UART_FLOW_CONF 0x34 32 read-write n 0x0 0x0 FORCE_XOFF 3 1 FORCE_XON 2 1 SEND_XOFF 5 1 SEND_XON 4 1 SW_FLOW_CON_EN 0 1 XONOFF_DEL 1 1 HIGHPULSE UART_HIGHPULSE 0x2C 32 read-write n 0x0 0x0 HIGHPULSE_MIN_CNT 0 20 ID UART_ID 0x7C 32 read-write n 0x0 0x0 ID 0 32 IDLE_CONF UART_IDLE_CONF 0x40 32 read-write n 0x0 0x0 RX_IDLE_THRHD 0 10 TX_BRK_NUM 20 8 TX_IDLE_NUM 10 10 INT_CLR UART_INT_CLR 0x10 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_CLR 18 1 BRK_DET_INT_CLR 7 1 CTS_CHG_INT_CLR 6 1 DSR_CHG_INT_CLR 5 1 FRM_ERR_INT_CLR 3 1 GLITCH_DET_INT_CLR 11 1 PARITY_ERR_INT_CLR 2 1 RS485_CLASH_INT_CLR 17 1 RS485_FRM_ERR_INT_CLR 16 1 RS485_PARITY_ERR_INT_CLR 15 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 4 1 RXFIFO_TOUT_INT_CLR 8 1 SW_XOFF_INT_CLR 10 1 SW_XON_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_BRK_DONE_INT_CLR 12 1 TX_BRK_IDLE_DONE_INT_CLR 13 1 TX_DONE_INT_CLR 14 1 INT_ENA UART_INT_ENA 0xC 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ENA 18 1 BRK_DET_INT_ENA 7 1 CTS_CHG_INT_ENA 6 1 DSR_CHG_INT_ENA 5 1 FRM_ERR_INT_ENA 3 1 GLITCH_DET_INT_ENA 11 1 PARITY_ERR_INT_ENA 2 1 RS485_CLASH_INT_ENA 17 1 RS485_FRM_ERR_INT_ENA 16 1 RS485_PARITY_ERR_INT_ENA 15 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 4 1 RXFIFO_TOUT_INT_ENA 8 1 SW_XOFF_INT_ENA 10 1 SW_XON_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_BRK_DONE_INT_ENA 12 1 TX_BRK_IDLE_DONE_INT_ENA 13 1 TX_DONE_INT_ENA 14 1 INT_RAW UART_INT_RAW 0x4 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_RAW 18 1 BRK_DET_INT_RAW 7 1 CTS_CHG_INT_RAW 6 1 DSR_CHG_INT_RAW 5 1 FRM_ERR_INT_RAW 3 1 GLITCH_DET_INT_RAW 11 1 PARITY_ERR_INT_RAW 2 1 RS485_CLASH_INT_RAW 17 1 RS485_FRM_ERR_INT_RAW 16 1 RS485_PARITY_ERR_INT_RAW 15 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 4 1 RXFIFO_TOUT_INT_RAW 8 1 SW_XOFF_INT_RAW 10 1 SW_XON_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_BRK_DONE_INT_RAW 12 1 TX_BRK_IDLE_DONE_INT_RAW 13 1 TX_DONE_INT_RAW 14 1 INT_ST UART_INT_ST 0x8 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ST 18 1 BRK_DET_INT_ST 7 1 CTS_CHG_INT_ST 6 1 DSR_CHG_INT_ST 5 1 FRM_ERR_INT_ST 3 1 GLITCH_DET_INT_ST 11 1 PARITY_ERR_INT_ST 2 1 RS485_CLASH_INT_ST 17 1 RS485_FRM_ERR_INT_ST 16 1 RS485_PARITY_ERR_INT_ST 15 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 4 1 RXFIFO_TOUT_INT_ST 8 1 SW_XOFF_INT_ST 10 1 SW_XON_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_BRK_DONE_INT_ST 12 1 TX_BRK_IDLE_DONE_INT_ST 13 1 TX_DONE_INT_ST 14 1 LOWPULSE UART_LOWPULSE 0x28 32 read-write n 0x0 0x0 LOWPULSE_MIN_CNT 0 20 MEM_CNT_STATUS UART_MEM_CNT_STATUS 0x64 32 read-write n 0x0 0x0 RX_MEM_CNT 0 3 TX_MEM_CNT 3 3 MEM_CONF UART_MEM_CONF 0x58 32 read-write n 0x0 0x0 MEM_PD 0 1 RX_FLOW_THRHD_H3 15 3 RX_MEM_FULL_THRHD 25 3 RX_SIZE 3 4 RX_TOUT_THRHD_H3 18 3 TX_MEM_EMPTY_THRHD 28 3 TX_SIZE 7 4 XOFF_THRESHOLD_H2 23 2 XON_THRESHOLD_H2 21 2 MEM_RX_STATUS UART_MEM_RX_STATUS 0x60 32 read-write n 0x0 0x0 MEM_RX_RD_ADDR 2 11 MEM_RX_STATUS 0 24 MEM_RX_WR_ADDR 13 11 MEM_TX_STATUS UART_MEM_TX_STATUS 0x5C 32 read-write n 0x0 0x0 MEM_TX_STATUS 0 24 NEGPULSE UART_NEGPULSE 0x6C 32 read-write n 0x0 0x0 NEGEDGE_MIN_CNT 0 20 POSPULSE UART_POSPULSE 0x68 32 read-write n 0x0 0x0 POSEDGE_MIN_CNT 0 20 RS485_CONF UART_RS485_CONF 0x44 32 read-write n 0x0 0x0 DL0_EN 1 1 DL1_EN 2 1 RS485RXBY_TX_EN 4 1 RS485TX_RX_EN 3 1 RS485_EN 0 1 RS485_RX_DLY_NUM 5 1 RS485_TX_DLY_NUM 6 4 RXD_CNT UART_RXD_CNT 0x30 32 read-write n 0x0 0x0 RXD_EDGE_CNT 0 10 RX_FIFO UART_RX_FIFO 0x0 8 read-only n 0x0 0x0 DATA TX FIFO Data 0 8 SLEEP_CONF UART_SLEEP_CONF 0x38 32 read-write n 0x0 0x0 ACTIVE_THRESHOLD 0 10 STATUS UART_STATUS 0x1C 32 read-write n 0x0 0x0 CTSN 14 1 DSRN 13 1 DTRN 29 1 RTSN 30 1 RXD 15 1 RXFIFO_CNT 0 8 ST_URX_OUT 8 4 UART_ST_URX_OUT read-write RX_IDLE RX_IDLE 0 RX_STRT RX_STRT 1 RX_PRTY RX_PRTY 10 RX_STP1 RX_STP1 11 RX_STP2 RX_STP2 12 RX_DL1 RX_DL1 13 RX_DAT0 RX_DAT0 2 RX_DAT1 RX_DAT1 3 RX_DAT2 RX_DAT2 4 RX_DAT3 RX_DAT3 5 RX_DAT4 RX_DAT4 6 RX_DAT5 RX_DAT5 7 RX_DAT6 RX_DAT6 8 RX_DAT7 RX_DAT7 9 ST_UTX_OUT 24 4 UART_ST_UTX_OUT read-write TX_IDLE TX_IDLE 0 TX_STRT TX_STRT 1 TX_PRTY TX_PRTY 10 TX_STP1 TX_STP1 11 TX_STP2 TX_STP2 12 TX_DL1 TX_DL1 14 TX_DAT0 TX_DAT0 2 TX_DAT1 TX_DAT1 3 TX_DAT2 TX_DAT2 4 TX_DAT3 TX_DAT3 5 TX_DAT4 TX_DAT4 6 TX_DAT5 TX_DAT5 7 TX_DAT6 TX_DAT6 8 TX_DAT7 TX_DAT7 9 TXD 31 1 TXFIFO_CNT 16 8 SWFC_CONF UART_SWFC_CONF 0x3C 32 read-write n 0x0 0x0 XOFF_CHAR 24 8 XOFF_THRESHOLD 8 8 XON_CHAR 16 8 XON_THRESHOLD 0 8 TX_FIFO UART_TX_FIFO 0x200C0000 8 write-only n 0x0 0x0 DATA TX FIFO Data 0 8 UART2 UART 0x0 0x0 0x400 UART registers n 0x200C0000 0x4 TX FIFO n AT_CMD_CHAR UART_AT_CMD_CHAR 0x54 32 read-write n 0x0 0x0 AT_CMD_CHAR 0 8 CHAR_NUM 8 8 AT_CMD_GAPTOUT UART_AT_CMD_GAPTOUT 0x50 32 read-write n 0x0 0x0 RX_GAP_TOUT 0 24 AT_CMD_POSTCNT UART_AT_CMD_POSTCNT 0x4C 32 read-write n 0x0 0x0 POST_IDLE_NUM 0 24 AT_CMD_PRECNT UART_AT_CMD_PRECNT 0x48 32 read-write n 0x0 0x0 PRE_IDLE_NUM 0 24 AUTOBAUD UART_AUTOBAUD 0x18 32 read-write n 0x0 0x0 AUTOBAUD_EN 0 1 GLITCH_FILT 8 8 CLKDIV UART_CLKDIV 0x14 32 read-write n 0x0 0x0 CLKDIV 0 20 CLKDIV_FRAG 20 4 CONF0 UART_CONF0 0x20 32 read-write n 0x0 0x0 BIT_NUM 2 2 UART_BIT_NUM read-write DATA_BITS_5 5 data bits 0 DATA_BITS_6 6 data bits 1 DATA_BITS_7 7 data bits 2 DATA_BITS_8 8 data bits 3 CLK_EN 25 1 CTS_INV 20 1 DSR_INV 21 1 DTR_INV 24 1 ERR_WR_MASK 26 1 IRDA_DPLX 9 1 IRDA_EN 16 1 IRDA_RX_INV 13 1 IRDA_TX_EN 10 1 IRDA_TX_INV 12 1 IRDA_WCTL 11 1 LOOPBACK 14 1 PARITY 0 1 PARITY_EN 1 1 RTS_INV 23 1 RXD_INV 19 1 RXFIFO_RST 17 1 STOP_BIT_NUM 4 2 UART_STOP_BIT_NUM read-write STOP_BITS_1 1 stop bits 1 STOP_BITS_1p5 1.5 stop bits 2 STOP_BITS_2 2 stop bits 3 SW_DTR 7 1 SW_RTS 6 1 TICK_REF_ALWAYS_ON 27 1 TXD_BRK 8 1 TXD_INV 22 1 TXFIFO_RST 18 1 TX_FLOW_EN 15 1 CONF1 UART_CONF1 0x24 32 read-write n 0x0 0x0 RXFIFO_FULL_THRHD 0 7 RX_FLOW_EN 23 1 RX_FLOW_THRHD 16 7 RX_TOUT_EN 31 1 RX_TOUT_THRHD 24 7 TXFIFO_EMPTY_THRHD 8 7 DATE UART_DATE 0x78 32 read-write n 0x0 0x0 DATE 0 32 FLOW_CONF UART_FLOW_CONF 0x34 32 read-write n 0x0 0x0 FORCE_XOFF 3 1 FORCE_XON 2 1 SEND_XOFF 5 1 SEND_XON 4 1 SW_FLOW_CON_EN 0 1 XONOFF_DEL 1 1 HIGHPULSE UART_HIGHPULSE 0x2C 32 read-write n 0x0 0x0 HIGHPULSE_MIN_CNT 0 20 ID UART_ID 0x7C 32 read-write n 0x0 0x0 ID 0 32 IDLE_CONF UART_IDLE_CONF 0x40 32 read-write n 0x0 0x0 RX_IDLE_THRHD 0 10 TX_BRK_NUM 20 8 TX_IDLE_NUM 10 10 INT_CLR UART_INT_CLR 0x10 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_CLR 18 1 BRK_DET_INT_CLR 7 1 CTS_CHG_INT_CLR 6 1 DSR_CHG_INT_CLR 5 1 FRM_ERR_INT_CLR 3 1 GLITCH_DET_INT_CLR 11 1 PARITY_ERR_INT_CLR 2 1 RS485_CLASH_INT_CLR 17 1 RS485_FRM_ERR_INT_CLR 16 1 RS485_PARITY_ERR_INT_CLR 15 1 RXFIFO_FULL_INT_CLR 0 1 RXFIFO_OVF_INT_CLR 4 1 RXFIFO_TOUT_INT_CLR 8 1 SW_XOFF_INT_CLR 10 1 SW_XON_INT_CLR 9 1 TXFIFO_EMPTY_INT_CLR 1 1 TX_BRK_DONE_INT_CLR 12 1 TX_BRK_IDLE_DONE_INT_CLR 13 1 TX_DONE_INT_CLR 14 1 INT_ENA UART_INT_ENA 0xC 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ENA 18 1 BRK_DET_INT_ENA 7 1 CTS_CHG_INT_ENA 6 1 DSR_CHG_INT_ENA 5 1 FRM_ERR_INT_ENA 3 1 GLITCH_DET_INT_ENA 11 1 PARITY_ERR_INT_ENA 2 1 RS485_CLASH_INT_ENA 17 1 RS485_FRM_ERR_INT_ENA 16 1 RS485_PARITY_ERR_INT_ENA 15 1 RXFIFO_FULL_INT_ENA 0 1 RXFIFO_OVF_INT_ENA 4 1 RXFIFO_TOUT_INT_ENA 8 1 SW_XOFF_INT_ENA 10 1 SW_XON_INT_ENA 9 1 TXFIFO_EMPTY_INT_ENA 1 1 TX_BRK_DONE_INT_ENA 12 1 TX_BRK_IDLE_DONE_INT_ENA 13 1 TX_DONE_INT_ENA 14 1 INT_RAW UART_INT_RAW 0x4 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_RAW 18 1 BRK_DET_INT_RAW 7 1 CTS_CHG_INT_RAW 6 1 DSR_CHG_INT_RAW 5 1 FRM_ERR_INT_RAW 3 1 GLITCH_DET_INT_RAW 11 1 PARITY_ERR_INT_RAW 2 1 RS485_CLASH_INT_RAW 17 1 RS485_FRM_ERR_INT_RAW 16 1 RS485_PARITY_ERR_INT_RAW 15 1 RXFIFO_FULL_INT_RAW 0 1 RXFIFO_OVF_INT_RAW 4 1 RXFIFO_TOUT_INT_RAW 8 1 SW_XOFF_INT_RAW 10 1 SW_XON_INT_RAW 9 1 TXFIFO_EMPTY_INT_RAW 1 1 TX_BRK_DONE_INT_RAW 12 1 TX_BRK_IDLE_DONE_INT_RAW 13 1 TX_DONE_INT_RAW 14 1 INT_ST UART_INT_ST 0x8 32 read-write n 0x0 0x0 AT_CMD_CHAR_DET_INT_ST 18 1 BRK_DET_INT_ST 7 1 CTS_CHG_INT_ST 6 1 DSR_CHG_INT_ST 5 1 FRM_ERR_INT_ST 3 1 GLITCH_DET_INT_ST 11 1 PARITY_ERR_INT_ST 2 1 RS485_CLASH_INT_ST 17 1 RS485_FRM_ERR_INT_ST 16 1 RS485_PARITY_ERR_INT_ST 15 1 RXFIFO_FULL_INT_ST 0 1 RXFIFO_OVF_INT_ST 4 1 RXFIFO_TOUT_INT_ST 8 1 SW_XOFF_INT_ST 10 1 SW_XON_INT_ST 9 1 TXFIFO_EMPTY_INT_ST 1 1 TX_BRK_DONE_INT_ST 12 1 TX_BRK_IDLE_DONE_INT_ST 13 1 TX_DONE_INT_ST 14 1 LOWPULSE UART_LOWPULSE 0x28 32 read-write n 0x0 0x0 LOWPULSE_MIN_CNT 0 20 MEM_CNT_STATUS UART_MEM_CNT_STATUS 0x64 32 read-write n 0x0 0x0 RX_MEM_CNT 0 3 TX_MEM_CNT 3 3 MEM_CONF UART_MEM_CONF 0x58 32 read-write n 0x0 0x0 MEM_PD 0 1 RX_FLOW_THRHD_H3 15 3 RX_MEM_FULL_THRHD 25 3 RX_SIZE 3 4 RX_TOUT_THRHD_H3 18 3 TX_MEM_EMPTY_THRHD 28 3 TX_SIZE 7 4 XOFF_THRESHOLD_H2 23 2 XON_THRESHOLD_H2 21 2 MEM_RX_STATUS UART_MEM_RX_STATUS 0x60 32 read-write n 0x0 0x0 MEM_RX_RD_ADDR 2 11 MEM_RX_STATUS 0 24 MEM_RX_WR_ADDR 13 11 MEM_TX_STATUS UART_MEM_TX_STATUS 0x5C 32 read-write n 0x0 0x0 MEM_TX_STATUS 0 24 NEGPULSE UART_NEGPULSE 0x6C 32 read-write n 0x0 0x0 NEGEDGE_MIN_CNT 0 20 POSPULSE UART_POSPULSE 0x68 32 read-write n 0x0 0x0 POSEDGE_MIN_CNT 0 20 RS485_CONF UART_RS485_CONF 0x44 32 read-write n 0x0 0x0 DL0_EN 1 1 DL1_EN 2 1 RS485RXBY_TX_EN 4 1 RS485TX_RX_EN 3 1 RS485_EN 0 1 RS485_RX_DLY_NUM 5 1 RS485_TX_DLY_NUM 6 4 RXD_CNT UART_RXD_CNT 0x30 32 read-write n 0x0 0x0 RXD_EDGE_CNT 0 10 RX_FIFO UART_RX_FIFO 0x0 8 read-only n 0x0 0x0 DATA TX FIFO Data 0 8 SLEEP_CONF UART_SLEEP_CONF 0x38 32 read-write n 0x0 0x0 ACTIVE_THRESHOLD 0 10 STATUS UART_STATUS 0x1C 32 read-write n 0x0 0x0 CTSN 14 1 DSRN 13 1 DTRN 29 1 RTSN 30 1 RXD 15 1 RXFIFO_CNT 0 8 ST_URX_OUT 8 4 UART_ST_URX_OUT read-write RX_IDLE RX_IDLE 0 RX_STRT RX_STRT 1 RX_PRTY RX_PRTY 10 RX_STP1 RX_STP1 11 RX_STP2 RX_STP2 12 RX_DL1 RX_DL1 13 RX_DAT0 RX_DAT0 2 RX_DAT1 RX_DAT1 3 RX_DAT2 RX_DAT2 4 RX_DAT3 RX_DAT3 5 RX_DAT4 RX_DAT4 6 RX_DAT5 RX_DAT5 7 RX_DAT6 RX_DAT6 8 RX_DAT7 RX_DAT7 9 ST_UTX_OUT 24 4 UART_ST_UTX_OUT read-write TX_IDLE TX_IDLE 0 TX_STRT TX_STRT 1 TX_PRTY TX_PRTY 10 TX_STP1 TX_STP1 11 TX_STP2 TX_STP2 12 TX_DL1 TX_DL1 14 TX_DAT0 TX_DAT0 2 TX_DAT1 TX_DAT1 3 TX_DAT2 TX_DAT2 4 TX_DAT3 TX_DAT3 5 TX_DAT4 TX_DAT4 6 TX_DAT5 TX_DAT5 7 TX_DAT6 TX_DAT6 8 TX_DAT7 TX_DAT7 9 TXD 31 1 TXFIFO_CNT 16 8 SWFC_CONF UART_SWFC_CONF 0x3C 32 read-write n 0x0 0x0 XOFF_CHAR 24 8 XOFF_THRESHOLD 8 8 XON_CHAR 16 8 XON_THRESHOLD 0 8 TX_FIFO UART_TX_FIFO 0x200C0000 8 write-only n 0x0 0x0 DATA TX FIFO Data 0 8 UHCI UHCI 0x0 0x0 0x620 registers n UHCI0_INTR interrupt of UHCI0, level 12 UHCI1_INTR interrupt of UHCI1, level 13 AHB_TEST UHCI_AHB_TEST 0x48 32 read-write n 0x0 0x0 AHB_TESTADDR 4 2 AHB_TESTMODE 0 3 CONF0 UHCI_CONF0 0x0 32 read-write n 0x0 0x0 AHBM_FIFO_RST 2 1 AHBM_RST 3 1 CLK_EN 22 1 CRC_REC_EN 18 1 ENCODE_CRC_EN 21 1 HEAD_EN 17 1 INDSCR_BURST_EN 13 1 IN_LOOP_TEST 4 1 IN_RST 0 1 LEN_EOF_EN 20 1 MEM_TRANS_EN 15 1 OUTDSCR_BURST_EN 12 1 OUT_AUTO_WRBACK 6 1 OUT_DATA_BURST_EN 14 1 OUT_EOF_MODE 8 1 OUT_LOOP_TEST 5 1 OUT_NO_RESTART_CLR 7 1 OUT_RST 1 1 SEPER_EN 16 1 UART0_CE 9 1 UART1_CE 10 1 UART2_CE 11 1 UART_IDLE_EOF_EN 19 1 UART_RX_BRK_EOF_EN 23 1 CONF1 UHCI_CONF1 0x2C 32 read-write n 0x0 0x0 CHECK_OWNER 6 1 CHECK_SEQ_EN 1 1 CHECK_SUM_EN 0 1 CRC_DISABLE 2 1 DMA_INFIFO_FULL_THRS 9 12 SAVE_HEAD 3 1 SW_START 8 1 TX_ACK_NUM_RE 5 1 TX_CHECK_SUM_RE 4 1 WAIT_SW_START 7 1 DATE UHCI_DATE 0xFC 32 read-write n 0x0 0x0 DATE 0 32 DMA_IN_DSCR UHCI_DMA_IN_DSCR 0x4C 32 read-write n 0x0 0x0 INLINK_DSCR 0 32 DMA_IN_DSCR_BF0 UHCI_DMA_IN_DSCR_BF0 0x50 32 read-write n 0x0 0x0 INLINK_DSCR_BF0 0 32 DMA_IN_DSCR_BF1 UHCI_DMA_IN_DSCR_BF1 0x54 32 read-write n 0x0 0x0 INLINK_DSCR_BF1 0 32 DMA_IN_ERR_EOF_DES_ADDR UHCI_DMA_IN_ERR_EOF_DES_ADDR 0x40 32 read-write n 0x0 0x0 IN_ERR_EOF_DES_ADDR 0 32 DMA_IN_LINK UHCI_DMA_IN_LINK 0x28 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_PARK 31 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_IN_POP UHCI_DMA_IN_POP 0x20 32 read-write n 0x0 0x0 INFIFO_POP 16 1 INFIFO_RDATA 0 12 DMA_IN_STATUS UHCI_DMA_IN_STATUS 0x1C 32 read-write n 0x0 0x0 IN_EMPTY 1 1 IN_FULL 0 1 RX_ERR_CAUSE 4 3 DMA_IN_SUC_EOF_DES_ADDR UHCI_DMA_IN_SUC_EOF_DES_ADDR 0x3C 32 read-write n 0x0 0x0 IN_SUC_EOF_DES_ADDR 0 32 DMA_OUT_DSCR UHCI_DMA_OUT_DSCR 0x58 32 read-write n 0x0 0x0 OUTLINK_DSCR 0 32 DMA_OUT_DSCR_BF0 UHCI_DMA_OUT_DSCR_BF0 0x5C 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF0 0 32 DMA_OUT_DSCR_BF1 UHCI_DMA_OUT_DSCR_BF1 0x60 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF1 0 32 DMA_OUT_EOF_BFR_DES_ADDR UHCI_DMA_OUT_EOF_BFR_DES_ADDR 0x44 32 read-write n 0x0 0x0 OUT_EOF_BFR_DES_ADDR 0 32 DMA_OUT_EOF_DES_ADDR UHCI_DMA_OUT_EOF_DES_ADDR 0x38 32 read-write n 0x0 0x0 OUT_EOF_DES_ADDR 0 32 DMA_OUT_LINK UHCI_DMA_OUT_LINK 0x24 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_PARK 31 1 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_OUT_PUSH UHCI_DMA_OUT_PUSH 0x18 32 read-write n 0x0 0x0 OUTFIFO_PUSH 16 1 OUTFIFO_WDATA 0 9 DMA_OUT_STATUS UHCI_DMA_OUT_STATUS 0x14 32 read-write n 0x0 0x0 OUT_EMPTY 1 1 OUT_FULL 0 1 ESCAPE_CONF UHCI_ESCAPE_CONF 0x64 32 read-write n 0x0 0x0 RX_11_ESC_EN 6 1 RX_13_ESC_EN 7 1 RX_C0_ESC_EN 4 1 RX_DB_ESC_EN 5 1 TX_11_ESC_EN 2 1 TX_13_ESC_EN 3 1 TX_C0_ESC_EN 0 1 TX_DB_ESC_EN 1 1 ESC_CONF0 UHCI_ESC_CONF0 0xB0 32 read-write n 0x0 0x0 SEPER_CHAR 0 8 SEPER_ESC_CHAR0 8 8 SEPER_ESC_CHAR1 16 8 ESC_CONF1 UHCI_ESC_CONF1 0xB4 32 read-write n 0x0 0x0 ESC_SEQ0 0 8 ESC_SEQ0_CHAR0 8 8 ESC_SEQ0_CHAR1 16 8 ESC_CONF2 UHCI_ESC_CONF2 0xB8 32 read-write n 0x0 0x0 ESC_SEQ1 0 8 ESC_SEQ1_CHAR0 8 8 ESC_SEQ1_CHAR1 16 8 ESC_CONF3 UHCI_ESC_CONF3 0xBC 32 read-write n 0x0 0x0 ESC_SEQ2 0 8 ESC_SEQ2_CHAR0 8 8 ESC_SEQ2_CHAR1 16 8 HUNG_CONF UHCI_HUNG_CONF 0x68 32 read-write n 0x0 0x0 RXFIFO_TIMEOUT 12 8 RXFIFO_TIMEOUT_ENA 23 1 RXFIFO_TIMEOUT_SHIFT 20 3 TXFIFO_TIMEOUT 0 8 TXFIFO_TIMEOUT_ENA 11 1 TXFIFO_TIMEOUT_SHIFT 8 3 INT_CLR UHCI_INT_CLR 0x10 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_CLR 16 1 IN_DONE_INT_CLR 4 1 IN_DSCR_EMPTY_INT_CLR 11 1 IN_DSCR_ERR_INT_CLR 9 1 IN_ERR_EOF_INT_CLR 6 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_EOF_ERR_INT_CLR 12 1 OUT_DONE_INT_CLR 7 1 OUT_DSCR_ERR_INT_CLR 10 1 OUT_EOF_INT_CLR 8 1 OUT_TOTAL_EOF_INT_CLR 13 1 RX_HUNG_INT_CLR 2 1 RX_START_INT_CLR 0 1 SEND_A_Q_INT_CLR 15 1 SEND_S_Q_INT_CLR 14 1 TX_HUNG_INT_CLR 3 1 TX_START_INT_CLR 1 1 INT_ENA UHCI_INT_ENA 0xC 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ENA 16 1 IN_DONE_INT_ENA 4 1 IN_DSCR_EMPTY_INT_ENA 11 1 IN_DSCR_ERR_INT_ENA 9 1 IN_ERR_EOF_INT_ENA 6 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_EOF_ERR_INT_ENA 12 1 OUT_DONE_INT_ENA 7 1 OUT_DSCR_ERR_INT_ENA 10 1 OUT_EOF_INT_ENA 8 1 OUT_TOTAL_EOF_INT_ENA 13 1 RX_HUNG_INT_ENA 2 1 RX_START_INT_ENA 0 1 SEND_A_Q_INT_ENA 15 1 SEND_S_Q_INT_ENA 14 1 TX_HUNG_INT_ENA 3 1 TX_START_INT_ENA 1 1 INT_RAW UHCI_INT_RAW 0x4 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_RAW 16 1 IN_DONE_INT_RAW 4 1 IN_DSCR_EMPTY_INT_RAW 11 1 IN_DSCR_ERR_INT_RAW 9 1 IN_ERR_EOF_INT_RAW 6 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_EOF_ERR_INT_RAW 12 1 OUT_DONE_INT_RAW 7 1 OUT_DSCR_ERR_INT_RAW 10 1 OUT_EOF_INT_RAW 8 1 OUT_TOTAL_EOF_INT_RAW 13 1 RX_HUNG_INT_RAW 2 1 RX_START_INT_RAW 0 1 SEND_A_Q_INT_RAW 15 1 SEND_S_Q_INT_RAW 14 1 TX_HUNG_INT_RAW 3 1 TX_START_INT_RAW 1 1 INT_ST UHCI_INT_ST 0x8 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ST 16 1 IN_DONE_INT_ST 4 1 IN_DSCR_EMPTY_INT_ST 11 1 IN_DSCR_ERR_INT_ST 9 1 IN_ERR_EOF_INT_ST 6 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_EOF_ERR_INT_ST 12 1 OUT_DONE_INT_ST 7 1 OUT_DSCR_ERR_INT_ST 10 1 OUT_EOF_INT_ST 8 1 OUT_TOTAL_EOF_INT_ST 13 1 RX_HUNG_INT_ST 2 1 RX_START_INT_ST 0 1 SEND_A_Q_INT_ST 15 1 SEND_S_Q_INT_ST 14 1 TX_HUNG_INT_ST 3 1 TX_START_INT_ST 1 1 PKT_THRES UHCI_PKT_THRES 0xC0 32 read-write n 0x0 0x0 PKT_THRS 0 13 Q0_WORD0 UHCI_Q0_WORD0 0x78 32 read-write n 0x0 0x0 SEND_Q0_WORD0 0 32 Q0_WORD1 UHCI_Q0_WORD1 0x7C 32 read-write n 0x0 0x0 SEND_Q0_WORD1 0 32 Q1_WORD0 UHCI_Q1_WORD0 0x80 32 read-write n 0x0 0x0 SEND_Q1_WORD0 0 32 Q1_WORD1 UHCI_Q1_WORD1 0x84 32 read-write n 0x0 0x0 SEND_Q1_WORD1 0 32 Q2_WORD0 UHCI_Q2_WORD0 0x88 32 read-write n 0x0 0x0 SEND_Q2_WORD0 0 32 Q2_WORD1 UHCI_Q2_WORD1 0x8C 32 read-write n 0x0 0x0 SEND_Q2_WORD1 0 32 Q3_WORD0 UHCI_Q3_WORD0 0x90 32 read-write n 0x0 0x0 SEND_Q3_WORD0 0 32 Q3_WORD1 UHCI_Q3_WORD1 0x94 32 read-write n 0x0 0x0 SEND_Q3_WORD1 0 32 Q4_WORD0 UHCI_Q4_WORD0 0x98 32 read-write n 0x0 0x0 SEND_Q4_WORD0 0 32 Q4_WORD1 UHCI_Q4_WORD1 0x9C 32 read-write n 0x0 0x0 SEND_Q4_WORD1 0 32 Q5_WORD0 UHCI_Q5_WORD0 0xA0 32 read-write n 0x0 0x0 SEND_Q5_WORD0 0 32 Q5_WORD1 UHCI_Q5_WORD1 0xA4 32 read-write n 0x0 0x0 SEND_Q5_WORD1 0 32 Q6_WORD0 UHCI_Q6_WORD0 0xA8 32 read-write n 0x0 0x0 SEND_Q6_WORD0 0 32 Q6_WORD1 UHCI_Q6_WORD1 0xAC 32 read-write n 0x0 0x0 SEND_Q6_WORD1 0 32 QUICK_SENT UHCI_QUICK_SENT 0x74 32 read-write n 0x0 0x0 ALWAYS_SEND_EN 7 1 ALWAYS_SEND_NUM 4 3 SINGLE_SEND_EN 3 1 SINGLE_SEND_NUM 0 3 RX_HEAD UHCI_RX_HEAD 0x70 32 read-write n 0x0 0x0 RX_HEAD 0 32 STATE0 UHCI_STATE0 0x30 32 read-write n 0x0 0x0 STATE0 0 32 STATE1 UHCI_STATE1 0x34 32 read-write n 0x0 0x0 STATE1 0 32 UHCI0 UHCI 0x0 0x0 0x620 registers n AHB_TEST UHCI_AHB_TEST 0x48 32 read-write n 0x0 0x0 AHB_TESTADDR 4 2 AHB_TESTMODE 0 3 CONF0 UHCI_CONF0 0x0 32 read-write n 0x0 0x0 AHBM_FIFO_RST 2 1 AHBM_RST 3 1 CLK_EN 22 1 CRC_REC_EN 18 1 ENCODE_CRC_EN 21 1 HEAD_EN 17 1 INDSCR_BURST_EN 13 1 IN_LOOP_TEST 4 1 IN_RST 0 1 LEN_EOF_EN 20 1 MEM_TRANS_EN 15 1 OUTDSCR_BURST_EN 12 1 OUT_AUTO_WRBACK 6 1 OUT_DATA_BURST_EN 14 1 OUT_EOF_MODE 8 1 OUT_LOOP_TEST 5 1 OUT_NO_RESTART_CLR 7 1 OUT_RST 1 1 SEPER_EN 16 1 UART0_CE 9 1 UART1_CE 10 1 UART2_CE 11 1 UART_IDLE_EOF_EN 19 1 UART_RX_BRK_EOF_EN 23 1 CONF1 UHCI_CONF1 0x2C 32 read-write n 0x0 0x0 CHECK_OWNER 6 1 CHECK_SEQ_EN 1 1 CHECK_SUM_EN 0 1 CRC_DISABLE 2 1 DMA_INFIFO_FULL_THRS 9 12 SAVE_HEAD 3 1 SW_START 8 1 TX_ACK_NUM_RE 5 1 TX_CHECK_SUM_RE 4 1 WAIT_SW_START 7 1 DATE UHCI_DATE 0xFC 32 read-write n 0x0 0x0 DATE 0 32 DMA_IN_DSCR UHCI_DMA_IN_DSCR 0x4C 32 read-write n 0x0 0x0 INLINK_DSCR 0 32 DMA_IN_DSCR_BF0 UHCI_DMA_IN_DSCR_BF0 0x50 32 read-write n 0x0 0x0 INLINK_DSCR_BF0 0 32 DMA_IN_DSCR_BF1 UHCI_DMA_IN_DSCR_BF1 0x54 32 read-write n 0x0 0x0 INLINK_DSCR_BF1 0 32 DMA_IN_ERR_EOF_DES_ADDR UHCI_DMA_IN_ERR_EOF_DES_ADDR 0x40 32 read-write n 0x0 0x0 IN_ERR_EOF_DES_ADDR 0 32 DMA_IN_LINK UHCI_DMA_IN_LINK 0x28 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_PARK 31 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_IN_POP UHCI_DMA_IN_POP 0x20 32 read-write n 0x0 0x0 INFIFO_POP 16 1 INFIFO_RDATA 0 12 DMA_IN_STATUS UHCI_DMA_IN_STATUS 0x1C 32 read-write n 0x0 0x0 IN_EMPTY 1 1 IN_FULL 0 1 RX_ERR_CAUSE 4 3 DMA_IN_SUC_EOF_DES_ADDR UHCI_DMA_IN_SUC_EOF_DES_ADDR 0x3C 32 read-write n 0x0 0x0 IN_SUC_EOF_DES_ADDR 0 32 DMA_OUT_DSCR UHCI_DMA_OUT_DSCR 0x58 32 read-write n 0x0 0x0 OUTLINK_DSCR 0 32 DMA_OUT_DSCR_BF0 UHCI_DMA_OUT_DSCR_BF0 0x5C 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF0 0 32 DMA_OUT_DSCR_BF1 UHCI_DMA_OUT_DSCR_BF1 0x60 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF1 0 32 DMA_OUT_EOF_BFR_DES_ADDR UHCI_DMA_OUT_EOF_BFR_DES_ADDR 0x44 32 read-write n 0x0 0x0 OUT_EOF_BFR_DES_ADDR 0 32 DMA_OUT_EOF_DES_ADDR UHCI_DMA_OUT_EOF_DES_ADDR 0x38 32 read-write n 0x0 0x0 OUT_EOF_DES_ADDR 0 32 DMA_OUT_LINK UHCI_DMA_OUT_LINK 0x24 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_PARK 31 1 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_OUT_PUSH UHCI_DMA_OUT_PUSH 0x18 32 read-write n 0x0 0x0 OUTFIFO_PUSH 16 1 OUTFIFO_WDATA 0 9 DMA_OUT_STATUS UHCI_DMA_OUT_STATUS 0x14 32 read-write n 0x0 0x0 OUT_EMPTY 1 1 OUT_FULL 0 1 ESCAPE_CONF UHCI_ESCAPE_CONF 0x64 32 read-write n 0x0 0x0 RX_11_ESC_EN 6 1 RX_13_ESC_EN 7 1 RX_C0_ESC_EN 4 1 RX_DB_ESC_EN 5 1 TX_11_ESC_EN 2 1 TX_13_ESC_EN 3 1 TX_C0_ESC_EN 0 1 TX_DB_ESC_EN 1 1 ESC_CONF0 UHCI_ESC_CONF0 0xB0 32 read-write n 0x0 0x0 SEPER_CHAR 0 8 SEPER_ESC_CHAR0 8 8 SEPER_ESC_CHAR1 16 8 ESC_CONF1 UHCI_ESC_CONF1 0xB4 32 read-write n 0x0 0x0 ESC_SEQ0 0 8 ESC_SEQ0_CHAR0 8 8 ESC_SEQ0_CHAR1 16 8 ESC_CONF2 UHCI_ESC_CONF2 0xB8 32 read-write n 0x0 0x0 ESC_SEQ1 0 8 ESC_SEQ1_CHAR0 8 8 ESC_SEQ1_CHAR1 16 8 ESC_CONF3 UHCI_ESC_CONF3 0xBC 32 read-write n 0x0 0x0 ESC_SEQ2 0 8 ESC_SEQ2_CHAR0 8 8 ESC_SEQ2_CHAR1 16 8 HUNG_CONF UHCI_HUNG_CONF 0x68 32 read-write n 0x0 0x0 RXFIFO_TIMEOUT 12 8 RXFIFO_TIMEOUT_ENA 23 1 RXFIFO_TIMEOUT_SHIFT 20 3 TXFIFO_TIMEOUT 0 8 TXFIFO_TIMEOUT_ENA 11 1 TXFIFO_TIMEOUT_SHIFT 8 3 INT_CLR UHCI_INT_CLR 0x10 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_CLR 16 1 IN_DONE_INT_CLR 4 1 IN_DSCR_EMPTY_INT_CLR 11 1 IN_DSCR_ERR_INT_CLR 9 1 IN_ERR_EOF_INT_CLR 6 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_EOF_ERR_INT_CLR 12 1 OUT_DONE_INT_CLR 7 1 OUT_DSCR_ERR_INT_CLR 10 1 OUT_EOF_INT_CLR 8 1 OUT_TOTAL_EOF_INT_CLR 13 1 RX_HUNG_INT_CLR 2 1 RX_START_INT_CLR 0 1 SEND_A_Q_INT_CLR 15 1 SEND_S_Q_INT_CLR 14 1 TX_HUNG_INT_CLR 3 1 TX_START_INT_CLR 1 1 INT_ENA UHCI_INT_ENA 0xC 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ENA 16 1 IN_DONE_INT_ENA 4 1 IN_DSCR_EMPTY_INT_ENA 11 1 IN_DSCR_ERR_INT_ENA 9 1 IN_ERR_EOF_INT_ENA 6 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_EOF_ERR_INT_ENA 12 1 OUT_DONE_INT_ENA 7 1 OUT_DSCR_ERR_INT_ENA 10 1 OUT_EOF_INT_ENA 8 1 OUT_TOTAL_EOF_INT_ENA 13 1 RX_HUNG_INT_ENA 2 1 RX_START_INT_ENA 0 1 SEND_A_Q_INT_ENA 15 1 SEND_S_Q_INT_ENA 14 1 TX_HUNG_INT_ENA 3 1 TX_START_INT_ENA 1 1 INT_RAW UHCI_INT_RAW 0x4 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_RAW 16 1 IN_DONE_INT_RAW 4 1 IN_DSCR_EMPTY_INT_RAW 11 1 IN_DSCR_ERR_INT_RAW 9 1 IN_ERR_EOF_INT_RAW 6 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_EOF_ERR_INT_RAW 12 1 OUT_DONE_INT_RAW 7 1 OUT_DSCR_ERR_INT_RAW 10 1 OUT_EOF_INT_RAW 8 1 OUT_TOTAL_EOF_INT_RAW 13 1 RX_HUNG_INT_RAW 2 1 RX_START_INT_RAW 0 1 SEND_A_Q_INT_RAW 15 1 SEND_S_Q_INT_RAW 14 1 TX_HUNG_INT_RAW 3 1 TX_START_INT_RAW 1 1 INT_ST UHCI_INT_ST 0x8 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ST 16 1 IN_DONE_INT_ST 4 1 IN_DSCR_EMPTY_INT_ST 11 1 IN_DSCR_ERR_INT_ST 9 1 IN_ERR_EOF_INT_ST 6 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_EOF_ERR_INT_ST 12 1 OUT_DONE_INT_ST 7 1 OUT_DSCR_ERR_INT_ST 10 1 OUT_EOF_INT_ST 8 1 OUT_TOTAL_EOF_INT_ST 13 1 RX_HUNG_INT_ST 2 1 RX_START_INT_ST 0 1 SEND_A_Q_INT_ST 15 1 SEND_S_Q_INT_ST 14 1 TX_HUNG_INT_ST 3 1 TX_START_INT_ST 1 1 PKT_THRES UHCI_PKT_THRES 0xC0 32 read-write n 0x0 0x0 PKT_THRS 0 13 Q0_WORD0 UHCI_Q0_WORD0 0x78 32 read-write n 0x0 0x0 SEND_Q0_WORD0 0 32 Q0_WORD1 UHCI_Q0_WORD1 0x7C 32 read-write n 0x0 0x0 SEND_Q0_WORD1 0 32 Q1_WORD0 UHCI_Q1_WORD0 0x80 32 read-write n 0x0 0x0 SEND_Q1_WORD0 0 32 Q1_WORD1 UHCI_Q1_WORD1 0x84 32 read-write n 0x0 0x0 SEND_Q1_WORD1 0 32 Q2_WORD0 UHCI_Q2_WORD0 0x88 32 read-write n 0x0 0x0 SEND_Q2_WORD0 0 32 Q2_WORD1 UHCI_Q2_WORD1 0x8C 32 read-write n 0x0 0x0 SEND_Q2_WORD1 0 32 Q3_WORD0 UHCI_Q3_WORD0 0x90 32 read-write n 0x0 0x0 SEND_Q3_WORD0 0 32 Q3_WORD1 UHCI_Q3_WORD1 0x94 32 read-write n 0x0 0x0 SEND_Q3_WORD1 0 32 Q4_WORD0 UHCI_Q4_WORD0 0x98 32 read-write n 0x0 0x0 SEND_Q4_WORD0 0 32 Q4_WORD1 UHCI_Q4_WORD1 0x9C 32 read-write n 0x0 0x0 SEND_Q4_WORD1 0 32 Q5_WORD0 UHCI_Q5_WORD0 0xA0 32 read-write n 0x0 0x0 SEND_Q5_WORD0 0 32 Q5_WORD1 UHCI_Q5_WORD1 0xA4 32 read-write n 0x0 0x0 SEND_Q5_WORD1 0 32 Q6_WORD0 UHCI_Q6_WORD0 0xA8 32 read-write n 0x0 0x0 SEND_Q6_WORD0 0 32 Q6_WORD1 UHCI_Q6_WORD1 0xAC 32 read-write n 0x0 0x0 SEND_Q6_WORD1 0 32 QUICK_SENT UHCI_QUICK_SENT 0x74 32 read-write n 0x0 0x0 ALWAYS_SEND_EN 7 1 ALWAYS_SEND_NUM 4 3 SINGLE_SEND_EN 3 1 SINGLE_SEND_NUM 0 3 RX_HEAD UHCI_RX_HEAD 0x70 32 read-write n 0x0 0x0 RX_HEAD 0 32 STATE0 UHCI_STATE0 0x30 32 read-write n 0x0 0x0 STATE0 0 32 STATE1 UHCI_STATE1 0x34 32 read-write n 0x0 0x0 STATE1 0 32 UHCI1 UHCI 0x0 0x0 0x620 registers n AHB_TEST UHCI_AHB_TEST 0x48 32 read-write n 0x0 0x0 AHB_TESTADDR 4 2 AHB_TESTMODE 0 3 CONF0 UHCI_CONF0 0x0 32 read-write n 0x0 0x0 AHBM_FIFO_RST 2 1 AHBM_RST 3 1 CLK_EN 22 1 CRC_REC_EN 18 1 ENCODE_CRC_EN 21 1 HEAD_EN 17 1 INDSCR_BURST_EN 13 1 IN_LOOP_TEST 4 1 IN_RST 0 1 LEN_EOF_EN 20 1 MEM_TRANS_EN 15 1 OUTDSCR_BURST_EN 12 1 OUT_AUTO_WRBACK 6 1 OUT_DATA_BURST_EN 14 1 OUT_EOF_MODE 8 1 OUT_LOOP_TEST 5 1 OUT_NO_RESTART_CLR 7 1 OUT_RST 1 1 SEPER_EN 16 1 UART0_CE 9 1 UART1_CE 10 1 UART2_CE 11 1 UART_IDLE_EOF_EN 19 1 UART_RX_BRK_EOF_EN 23 1 CONF1 UHCI_CONF1 0x2C 32 read-write n 0x0 0x0 CHECK_OWNER 6 1 CHECK_SEQ_EN 1 1 CHECK_SUM_EN 0 1 CRC_DISABLE 2 1 DMA_INFIFO_FULL_THRS 9 12 SAVE_HEAD 3 1 SW_START 8 1 TX_ACK_NUM_RE 5 1 TX_CHECK_SUM_RE 4 1 WAIT_SW_START 7 1 DATE UHCI_DATE 0xFC 32 read-write n 0x0 0x0 DATE 0 32 DMA_IN_DSCR UHCI_DMA_IN_DSCR 0x4C 32 read-write n 0x0 0x0 INLINK_DSCR 0 32 DMA_IN_DSCR_BF0 UHCI_DMA_IN_DSCR_BF0 0x50 32 read-write n 0x0 0x0 INLINK_DSCR_BF0 0 32 DMA_IN_DSCR_BF1 UHCI_DMA_IN_DSCR_BF1 0x54 32 read-write n 0x0 0x0 INLINK_DSCR_BF1 0 32 DMA_IN_ERR_EOF_DES_ADDR UHCI_DMA_IN_ERR_EOF_DES_ADDR 0x40 32 read-write n 0x0 0x0 IN_ERR_EOF_DES_ADDR 0 32 DMA_IN_LINK UHCI_DMA_IN_LINK 0x28 32 read-write n 0x0 0x0 INLINK_ADDR 0 20 INLINK_AUTO_RET 20 1 INLINK_PARK 31 1 INLINK_RESTART 30 1 INLINK_START 29 1 INLINK_STOP 28 1 DMA_IN_POP UHCI_DMA_IN_POP 0x20 32 read-write n 0x0 0x0 INFIFO_POP 16 1 INFIFO_RDATA 0 12 DMA_IN_STATUS UHCI_DMA_IN_STATUS 0x1C 32 read-write n 0x0 0x0 IN_EMPTY 1 1 IN_FULL 0 1 RX_ERR_CAUSE 4 3 DMA_IN_SUC_EOF_DES_ADDR UHCI_DMA_IN_SUC_EOF_DES_ADDR 0x3C 32 read-write n 0x0 0x0 IN_SUC_EOF_DES_ADDR 0 32 DMA_OUT_DSCR UHCI_DMA_OUT_DSCR 0x58 32 read-write n 0x0 0x0 OUTLINK_DSCR 0 32 DMA_OUT_DSCR_BF0 UHCI_DMA_OUT_DSCR_BF0 0x5C 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF0 0 32 DMA_OUT_DSCR_BF1 UHCI_DMA_OUT_DSCR_BF1 0x60 32 read-write n 0x0 0x0 OUTLINK_DSCR_BF1 0 32 DMA_OUT_EOF_BFR_DES_ADDR UHCI_DMA_OUT_EOF_BFR_DES_ADDR 0x44 32 read-write n 0x0 0x0 OUT_EOF_BFR_DES_ADDR 0 32 DMA_OUT_EOF_DES_ADDR UHCI_DMA_OUT_EOF_DES_ADDR 0x38 32 read-write n 0x0 0x0 OUT_EOF_DES_ADDR 0 32 DMA_OUT_LINK UHCI_DMA_OUT_LINK 0x24 32 read-write n 0x0 0x0 OUTLINK_ADDR 0 20 OUTLINK_PARK 31 1 OUTLINK_RESTART 30 1 OUTLINK_START 29 1 OUTLINK_STOP 28 1 DMA_OUT_PUSH UHCI_DMA_OUT_PUSH 0x18 32 read-write n 0x0 0x0 OUTFIFO_PUSH 16 1 OUTFIFO_WDATA 0 9 DMA_OUT_STATUS UHCI_DMA_OUT_STATUS 0x14 32 read-write n 0x0 0x0 OUT_EMPTY 1 1 OUT_FULL 0 1 ESCAPE_CONF UHCI_ESCAPE_CONF 0x64 32 read-write n 0x0 0x0 RX_11_ESC_EN 6 1 RX_13_ESC_EN 7 1 RX_C0_ESC_EN 4 1 RX_DB_ESC_EN 5 1 TX_11_ESC_EN 2 1 TX_13_ESC_EN 3 1 TX_C0_ESC_EN 0 1 TX_DB_ESC_EN 1 1 ESC_CONF0 UHCI_ESC_CONF0 0xB0 32 read-write n 0x0 0x0 SEPER_CHAR 0 8 SEPER_ESC_CHAR0 8 8 SEPER_ESC_CHAR1 16 8 ESC_CONF1 UHCI_ESC_CONF1 0xB4 32 read-write n 0x0 0x0 ESC_SEQ0 0 8 ESC_SEQ0_CHAR0 8 8 ESC_SEQ0_CHAR1 16 8 ESC_CONF2 UHCI_ESC_CONF2 0xB8 32 read-write n 0x0 0x0 ESC_SEQ1 0 8 ESC_SEQ1_CHAR0 8 8 ESC_SEQ1_CHAR1 16 8 ESC_CONF3 UHCI_ESC_CONF3 0xBC 32 read-write n 0x0 0x0 ESC_SEQ2 0 8 ESC_SEQ2_CHAR0 8 8 ESC_SEQ2_CHAR1 16 8 HUNG_CONF UHCI_HUNG_CONF 0x68 32 read-write n 0x0 0x0 RXFIFO_TIMEOUT 12 8 RXFIFO_TIMEOUT_ENA 23 1 RXFIFO_TIMEOUT_SHIFT 20 3 TXFIFO_TIMEOUT 0 8 TXFIFO_TIMEOUT_ENA 11 1 TXFIFO_TIMEOUT_SHIFT 8 3 INT_CLR UHCI_INT_CLR 0x10 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_CLR 16 1 IN_DONE_INT_CLR 4 1 IN_DSCR_EMPTY_INT_CLR 11 1 IN_DSCR_ERR_INT_CLR 9 1 IN_ERR_EOF_INT_CLR 6 1 IN_SUC_EOF_INT_CLR 5 1 OUTLINK_EOF_ERR_INT_CLR 12 1 OUT_DONE_INT_CLR 7 1 OUT_DSCR_ERR_INT_CLR 10 1 OUT_EOF_INT_CLR 8 1 OUT_TOTAL_EOF_INT_CLR 13 1 RX_HUNG_INT_CLR 2 1 RX_START_INT_CLR 0 1 SEND_A_Q_INT_CLR 15 1 SEND_S_Q_INT_CLR 14 1 TX_HUNG_INT_CLR 3 1 TX_START_INT_CLR 1 1 INT_ENA UHCI_INT_ENA 0xC 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ENA 16 1 IN_DONE_INT_ENA 4 1 IN_DSCR_EMPTY_INT_ENA 11 1 IN_DSCR_ERR_INT_ENA 9 1 IN_ERR_EOF_INT_ENA 6 1 IN_SUC_EOF_INT_ENA 5 1 OUTLINK_EOF_ERR_INT_ENA 12 1 OUT_DONE_INT_ENA 7 1 OUT_DSCR_ERR_INT_ENA 10 1 OUT_EOF_INT_ENA 8 1 OUT_TOTAL_EOF_INT_ENA 13 1 RX_HUNG_INT_ENA 2 1 RX_START_INT_ENA 0 1 SEND_A_Q_INT_ENA 15 1 SEND_S_Q_INT_ENA 14 1 TX_HUNG_INT_ENA 3 1 TX_START_INT_ENA 1 1 INT_RAW UHCI_INT_RAW 0x4 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_RAW 16 1 IN_DONE_INT_RAW 4 1 IN_DSCR_EMPTY_INT_RAW 11 1 IN_DSCR_ERR_INT_RAW 9 1 IN_ERR_EOF_INT_RAW 6 1 IN_SUC_EOF_INT_RAW 5 1 OUTLINK_EOF_ERR_INT_RAW 12 1 OUT_DONE_INT_RAW 7 1 OUT_DSCR_ERR_INT_RAW 10 1 OUT_EOF_INT_RAW 8 1 OUT_TOTAL_EOF_INT_RAW 13 1 RX_HUNG_INT_RAW 2 1 RX_START_INT_RAW 0 1 SEND_A_Q_INT_RAW 15 1 SEND_S_Q_INT_RAW 14 1 TX_HUNG_INT_RAW 3 1 TX_START_INT_RAW 1 1 INT_ST UHCI_INT_ST 0x8 32 read-write n 0x0 0x0 DMA_INFIFO_FULL_WM_INT_ST 16 1 IN_DONE_INT_ST 4 1 IN_DSCR_EMPTY_INT_ST 11 1 IN_DSCR_ERR_INT_ST 9 1 IN_ERR_EOF_INT_ST 6 1 IN_SUC_EOF_INT_ST 5 1 OUTLINK_EOF_ERR_INT_ST 12 1 OUT_DONE_INT_ST 7 1 OUT_DSCR_ERR_INT_ST 10 1 OUT_EOF_INT_ST 8 1 OUT_TOTAL_EOF_INT_ST 13 1 RX_HUNG_INT_ST 2 1 RX_START_INT_ST 0 1 SEND_A_Q_INT_ST 15 1 SEND_S_Q_INT_ST 14 1 TX_HUNG_INT_ST 3 1 TX_START_INT_ST 1 1 PKT_THRES UHCI_PKT_THRES 0xC0 32 read-write n 0x0 0x0 PKT_THRS 0 13 Q0_WORD0 UHCI_Q0_WORD0 0x78 32 read-write n 0x0 0x0 SEND_Q0_WORD0 0 32 Q0_WORD1 UHCI_Q0_WORD1 0x7C 32 read-write n 0x0 0x0 SEND_Q0_WORD1 0 32 Q1_WORD0 UHCI_Q1_WORD0 0x80 32 read-write n 0x0 0x0 SEND_Q1_WORD0 0 32 Q1_WORD1 UHCI_Q1_WORD1 0x84 32 read-write n 0x0 0x0 SEND_Q1_WORD1 0 32 Q2_WORD0 UHCI_Q2_WORD0 0x88 32 read-write n 0x0 0x0 SEND_Q2_WORD0 0 32 Q2_WORD1 UHCI_Q2_WORD1 0x8C 32 read-write n 0x0 0x0 SEND_Q2_WORD1 0 32 Q3_WORD0 UHCI_Q3_WORD0 0x90 32 read-write n 0x0 0x0 SEND_Q3_WORD0 0 32 Q3_WORD1 UHCI_Q3_WORD1 0x94 32 read-write n 0x0 0x0 SEND_Q3_WORD1 0 32 Q4_WORD0 UHCI_Q4_WORD0 0x98 32 read-write n 0x0 0x0 SEND_Q4_WORD0 0 32 Q4_WORD1 UHCI_Q4_WORD1 0x9C 32 read-write n 0x0 0x0 SEND_Q4_WORD1 0 32 Q5_WORD0 UHCI_Q5_WORD0 0xA0 32 read-write n 0x0 0x0 SEND_Q5_WORD0 0 32 Q5_WORD1 UHCI_Q5_WORD1 0xA4 32 read-write n 0x0 0x0 SEND_Q5_WORD1 0 32 Q6_WORD0 UHCI_Q6_WORD0 0xA8 32 read-write n 0x0 0x0 SEND_Q6_WORD0 0 32 Q6_WORD1 UHCI_Q6_WORD1 0xAC 32 read-write n 0x0 0x0 SEND_Q6_WORD1 0 32 QUICK_SENT UHCI_QUICK_SENT 0x74 32 read-write n 0x0 0x0 ALWAYS_SEND_EN 7 1 ALWAYS_SEND_NUM 4 3 SINGLE_SEND_EN 3 1 SINGLE_SEND_NUM 0 3 RX_HEAD UHCI_RX_HEAD 0x70 32 read-write n 0x0 0x0 RX_HEAD 0 32 STATE0 UHCI_STATE0 0x30 32 read-write n 0x0 0x0 STATE0 0 32 STATE1 UHCI_STATE1 0x34 32 read-write n 0x0 0x0 STATE1 0 32 WDT WDT 0x0 WDT_INTR will be cancelled 55 WIFI_BB WIFI_BB 0x0 WIFI_BB_INTR interrupt of WiFi BB, level, we can do some calibration 2 WIFI_MAC WIFI_MAC 0x0 WIFI_MAC_INTR interrupt of WiFi MAC, level 0 WIFI_MAC_NMI interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI 1 XTENSA XTENSA 0x0 FROM_CPU_INTR0 interrupt0 generated from a CPU, level 24 FROM_CPU_INTR1 interrupt1 generated from a CPU, level 25 FROM_CPU_INTR2 interrupt2 generated from a CPU, level 26 FROM_CPU_INTR3 interrupt3 generated from a CPU, level 27 TIMER1_INTR will be cancelled 56 TIMER2_INTR will be cancelled 57 MMU_IA_INTR interrupt of MMU Invalid Access, LEVEL 66 MPU_IA_INTR interrupt of MPU Invalid Access, LEVEL 67 CACHE_IA_INTR interrupt of Cache Invalid Access, LEVEL 68 XTENSA_INTERNAL XTENSA_INTERNAL 0x0 INTERNAL_TIMER0_INTR Internal Timer 0 interrupt 69 INTERNAL_SOFTWARE_LEVEL_1_INTR Software Level 1 interrupt 70 INTERNAL_PROFILING_INTR Profiling interrupt 71 INTERNAL_TIMER1_INTR Internal Timer 1 interrupt 72 INTERNAL_TIMER2_INTR Internal Timer 1 interrupt 73 INTERNAL_SOFTWARE_LEVEL_3_INTR Software Level 3 interrupt 74