Infineon MB9AF11xL 2024.04.27 MB9AF11xL 8 32 ADC0 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x1 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC0 25 ADCEN A/D Operation Enable Setup Register 0x3C 8 read-write n 0x0 0x0 CYCLSL Basic cycle selection bit 4 1 read-write ENBL A/D operation enable bit 0 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write ADC1 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x1 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC1 26 ADCEN A/D Operation Enable Setup Register 0x3C 8 read-write n 0x0 0x0 CYCLSL Basic cycle selection bit 4 1 read-write ENBL A/D operation enable bit 0 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write BT0 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n BTIM0_7 31 PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT1 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT2 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT3 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT4 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT5 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT6 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT7 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x0 0x0 0x2 registers n BTSEL0123 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL01_ I/O select bits for Ch.0/Ch.1 8 3 read-write SEL23_ I/O select bits for Ch.2/Ch.3 12 3 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x0 0x0 0x2 registers n BTSEL4567 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL45_ I/O select bits for Ch.4/Ch.5 8 3 read-write SEL67_ I/O select bits for Ch.6/Ch.7 12 3 read-write CRC CRC Registers CRC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0x4 0x1 registers n 0x8 0x4 registers n 0xC 0x4 registers n CRCCR CRC Control Register 0x0 8 read-write n 0x0 0x0 CRC32 Byte-order setting bit 1 read-write CRCLSF Final XOR control bit 5 read-write CRCLTE CRC result bit-order setting bit 4 read-write FXOR Initialization bit 6 read-write INIT CRC mode selection bit 0 read-write LSBFST CRC result byte-order setting bit 3 read-write LTLEND Bit-order setting bit 2 read-write CRCIN Input Data Register 0x8 32 read-write n 0x0 0x0 D Input data 0 31 read-write CRCINIT Initial Value Register 0x4 32 read-write n 0x0 0x0 D Initial value 0 31 read-write CRCR CRC Register 0xC 32 read-only n 0x0 0x0 D CRC Data 0 31 read-only CRG Clock Unit Registers CRG 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x28 0x1 registers n 0x30 0x1 registers n 0x34 0x1 registers n 0x38 0x1 registers n 0x3C 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x1 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x1 registers n 0x60 0x1 registers n 0x64 0x1 registers n 0x68 0x1 registers n 0x8 0x6 registers n CSV 0 OSC_PLL_WC 24 APBC0_PSR APB0 Prescaler Register 0x14 8 read-write n 0x0 0x0 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write n 0x0 0x0 APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC1EN APB1 clock enable bit 7 read-write APBC1RST APB1 bus reset control bit 4 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write n 0x0 0x0 APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write APBC2EN APB2 clock enable bit 7 read-write APBC2RST APB2 bus reset control bit 4 read-write BSC_PSR Base Clock Prescaler Register 0x10 8 read-write n 0x0 0x0 BSR Base clock frequency division ratio setting bit 0 2 read-write CSV_CTL CSV control register 0x40 16 read-write n 0x0 0x0 FCD FCS count cycle setting bits 12 2 read-write FCSDE FCS function enable bit 8 read-write FCSRE FCS reset output enable bit 9 read-write MCSVE Main CSV function enable bit 0 read-write SCSVE Sub CSV function enable bit 1 read-write CSV_STR CSV status register 0x44 8 read-only n 0x0 0x0 MCMF Main clock failure detection flag 0 read-only SCMF Sub clock failure detection flag 1 read-only CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write n 0x0 0x0 MOWT Main clock stabilization wait time setup bit 0 3 read-write SOWT Sub clock stabilization wait time setup bit 4 2 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write n 0x0 0x0 DPHWBE HW-WDG debug mode break bit 7 read-write DPSWBE SW-WDG debug mode break bit 5 read-write FCSWD_CTL Frequency detection counter register 0x50 16 read-only n 0x0 0x0 FCSWH_CTL Frequency detection window setting register 0x48 16 read-write n 0x0 0x0 FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write n 0x0 0x0 INT_CLR Interrupt Clear Register 0x68 8 write-only n 0x0 0x0 FCSC Anomalous frequency detection interrupt cause clear bit 5 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 write-only INT_ENR Interrupt Enable Register 0x60 8 read-write n 0x0 0x0 FCSE Anomalous frequency detection interrupt enable bit 5 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 read-write INT_STR Interrupt Status Register 0x64 8 read-only n 0x0 0x0 FCSI Anomalous frequency detection interrupt status bit 5 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 read-only PLL_CTL1 PLL Control Register 1 0x38 8 read-write n 0x0 0x0 PLLK PLL input clock frequency division ratio setting bit 4 3 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write n 0x0 0x0 PLLN PLL feedback frequency division ratio setting bit 0 5 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write n 0x0 0x0 PINC PLL input clock select bit 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write RST_STR Reset Cause Register 0xC 16 read-only n 0x0 0x0 CSVR Clock failure detection reset flag 6 read-only FCSR Flag for anomalous frequency detection reset 7 read-only HWDG Hardware watchdog reset flag 5 read-only HWDT Hardware watchdog reset flag 5 read-only INITX INITX pin input reset flag 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 read-only SRST Software reset flag 8 read-only SWDG Software watchdog reset flag 4 read-only SWDT Software watchdog reset flag 4 read-only SCM_CTL System Clock Mode Control Register 0x0 8 read-write n 0x0 0x0 MOSCE Main clock oscillation enable bit 1 read-write PLLE PLL oscillation enable bit 4 read-write RCS Master clock switch control bits 5 2 read-write SOSCE Sub clock oscillation enable bit 3 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only n 0x0 0x0 MORDY Main clock oscillation stable bit 1 read-only PLRDY PLL oscillation stable bit 4 read-only RCM Master clock selection bits 5 2 read-only SORDY Sub clock oscillation stable bit 3 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write n 0x0 0x0 KEY Standby mode control write control bit 16 15 read-write SPL Standby pin level setting bit 4 read-write STM Standby mode selection bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write n 0x0 0x0 SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TESTB TEST bit 7 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write n 0x0 0x0 TTC Trace clock frequency division ratio setting bit 0 read-write CRTRIM CR Trimming Registers CRTRIM 0x0 0x0 0x1 registers n 0x4 0x2 registers n 0xC 0x4 registers n MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write n 0x0 0x0 TRD Frequency trimming setup bits 0 7 read-write MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write n 0x0 0x0 CSR High-speed CR oscillation frequency division ratio setting bits 0 1 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write n 0x0 0x0 TRMLCK Register write-protect bits 0 31 read-write DMAC DMAC Registers DMAC 0x0 0x0 0x4 registers n 0x10 0x80 registers n DMAC0 38 DMAC1 39 DMAC2 40 DMAC3 41 DMAC4 42 DMAC5 43 DMAC6 44 DMAC7 45 DMACA0 Configuration A Register 0x10 32 read-write n 0x0 0x0 BC Block Count 16 3 read-write EB Enable bit (individual-channel operation enable bit) 31 read-write IS Input Select 23 5 read-write PB Pause bit (individual-channel pause bit) 30 read-write ST Software Trigger 29 read-write TC Transfer Count 0 15 read-write DMACA1 Configuration A Register 1 0x20 read-write n 0x0 0x0 DMACA2 Configuration A Register 2 0x30 read-write n 0x0 0x0 DMACA3 Configuration A Register 3 0x40 read-write n 0x0 0x0 DMACA4 Configuration A Register 4 0x50 read-write n 0x0 0x0 DMACA5 Configuration A Register 5 0x60 read-write n 0x0 0x0 DMACA6 Configuration A Register 6 0x70 read-write n 0x0 0x0 DMACA7 Configuration A Register 7 0x80 read-write n 0x0 0x0 DMACB0 Configuration B Register 0x14 32 read-write n 0x0 0x0 CI Completion Interrupt (successful transfer completion interrupt enable) 19 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 read-write EM Enable bit Mask (EB bit clear mask) 0 read-write FD Fixed Destination 24 read-write FS Fixed Source 25 read-write MS Mode Select 28 1 read-write RC Reload Count (BC/TC reload) 23 read-write RD Reload Destination 21 read-write RS Reload Source 22 read-write SS Stop Status (stop status notification) 16 2 read-write TW Transfer Width 26 1 read-write DMACB1 Configuration B Register 1 0x24 read-write n 0x0 0x0 DMACB2 Configuration B Register 2 0x34 read-write n 0x0 0x0 DMACB3 Configuration B Register 3 0x44 read-write n 0x0 0x0 DMACB4 Configuration B Register 4 0x54 read-write n 0x0 0x0 DMACB5 Configuration B Register 5 0x64 read-write n 0x0 0x0 DMACB6 Configuration B Register 6 0x74 read-write n 0x0 0x0 DMACB7 Configuration B Register 7 0x84 read-write n 0x0 0x0 DMACDA0 Transfer Destination Address Register 0x1C 32 read-write n 0x0 0x0 DMACDA1 Transfer Destination Address Register 1 0x2C read-write n 0x0 0x0 DMACDA2 Transfer Destination Address Register 2 0x3C read-write n 0x0 0x0 DMACDA3 Transfer Destination Address Register 3 0x4C read-write n 0x0 0x0 DMACDA4 Transfer Destination Address Register 4 0x5C read-write n 0x0 0x0 DMACDA5 Transfer Destination Address Register 5 0x6C read-write n 0x0 0x0 DMACDA6 Transfer Destination Address Register 6 0x7C read-write n 0x0 0x0 DMACDA7 Transfer Destination Address Register 7 0x8C read-write n 0x0 0x0 DMACR Entire DMAC Configuration Register 0x0 32 read-write n 0x0 0x0 DE DMA Enable (all-channel operation enable bit) 31 read-write DH DMA Halt (All-channel pause bit) 24 3 read-write DS DMA Stop 30 read-write PR Priority Rotation 28 read-write DMACSA0 Transfer Source Address Register 0x18 32 read-write n 0x0 0x0 DMACSA1 Transfer Source Address Register 1 0x28 read-write n 0x0 0x0 DMACSA2 Transfer Source Address Register 2 0x38 read-write n 0x0 0x0 DMACSA3 Transfer Source Address Register 3 0x48 read-write n 0x0 0x0 DMACSA4 Transfer Source Address Register 4 0x58 read-write n 0x0 0x0 DMACSA5 Transfer Source Address Register 5 0x68 read-write n 0x0 0x0 DMACSA6 Transfer Source Address Register 6 0x78 read-write n 0x0 0x0 DMACSA7 Transfer Source Address Register 7 0x88 read-write n 0x0 0x0 DTIM Dual Timer DTIM 0x0 0x0 0x1C registers n 0x20 0x1C registers n DTIM_QDU 6 TIMER1BGLOAD Background Load Register 0x18 32 read-write n 0x0 0x0 TIMER1CONTROL Control Register 0x8 32 read-write n 0x0 0x0 IntEnable Interrupt enable bit 5 read-write OneShot One-shot mode bit 0 read-write TimerEn Enable bit 7 read-write TimerMode Mode bit 6 read-write TimerPre Prescale bits 2 1 read-write TimerSize Counter size bit 1 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only n 0x0 0x0 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write n 0x0 0x0 TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only n 0x0 0x0 TIMER1MIS Masked Interrupt Status bit 0 read-only TIMER1RIS Interrupt Status Register 0x10 32 read-only n 0x0 0x0 TIMER1RIS Interrupt Status Register bit 0 read-only TIMER1VALUE Value Register 0x4 32 read-only n 0x0 0x0 TIMER2BGLOAD Background Load Register 0x38 read-write n 0x0 0x0 TIMER2CONTROL Control Register 0x28 read-write n 0x0 0x0 TIMER2INTCLR Interrupt Clear Register 0x2C read-write n 0x0 0x0 TIMER2LOAD Load Register 0x20 read-write n 0x0 0x0 TIMER2MIS Masked Interrupt Status Register 0x34 read-write n 0x0 0x0 TIMER2RIS Interrupt Status Register 0x30 read-write n 0x0 0x0 TIMER2VALUE Value Register 0x24 read-write n 0x0 0x0 EXTI External Interrupt and NMI Control EXTI 0x0 0x0 0x2 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n EXTINT0_7 4 EXTINT8_15 5 EICL External Interrupt Clear Register 0x8 16 read-write n 0x0 0x0 ECL0 Bit0 of EICL 0 read-write ECL1 Bit1 of EICL 1 read-write ECL15 Bit15 of EICL 15 read-write ECL2 Bit2 of EICL 2 read-write ECL3 Bit3 of EICL 3 read-write ECL4 Bit4 of EICL 4 read-write ECL5 Bit5 of EICL 5 read-write ECL6 Bit6 of EICL 6 read-write EIRR External Interrupt Request Register 0x4 16 read-only n 0x0 0x0 ER0 Bit0 of EIRR 0 read-only ER1 Bit1 of EIRR 1 read-only ER15 Bit15 of EIRR 15 read-only ER2 Bit2 of EIRR 2 read-only ER3 Bit3 of EIRR 3 read-only ER4 Bit4 of EIRR 4 read-only ER5 Bit5 of EIRR 5 read-only ER6 Bit6 of EIRR 6 read-only ELVR External Interrupt Level Register 0xC 32 read-write n 0x0 0x0 LA0 Bit0 of ELVR 0 read-write LA1 Bit2 of ELVR 2 read-write LA15 Bit30 of ELVR 30 read-write LA2 Bit4 of ELVR 4 read-write LA3 Bit6 of ELVR 6 read-write LA4 Bit8 of ELVR 8 read-write LA5 Bit10 of ELVR 10 read-write LA6 Bit12 of ELVR 12 read-write LB0 Bit1 of ELVR 1 read-write LB1 Bit3 of ELVR 3 read-write LB15 Bit31 of ELVR 31 read-write LB2 Bit5 of ELVR 5 read-write LB3 Bit7 of ELVR 7 read-write LB4 Bit9 of ELVR 9 read-write LB5 Bit11 of ELVR 11 read-write LB6 Bit13 of ELVR 13 read-write ENIR Enable Interrupt Request Register 0x0 16 read-write n 0x0 0x0 EN0 Bit0 of ENIR 0 read-write EN1 Bit1 of ENIR 1 read-write EN15 Bit15 of ENIR 15 read-write EN2 Bit2 of ENIR 2 read-write EN3 Bit3 of ENIR 3 read-write EN4 Bit4 of ENIR 4 read-write EN5 Bit5 of ENIR 5 read-write EN6 Bit6 of ENIR 6 read-write NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write n 0x0 0x0 NCL NMI interrupt cause clear bit 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only n 0x0 0x0 NR NMI interrupt request detection bit 0 read-only FLASH_IF Flash Memory FLASH_IF 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x100 0x4 registers n CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only n 0x0 0x0 TRMM CR Trimming Data Mirror 0 9 read-only FASZR Flash Access Size Register 0x0 32 read-write n 0x0 0x0 ASZ Flash Access Size 0 1 read-write FRWTR Flash Read Wait Register 0x4 32 read-write n 0x0 0x0 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x8 32 read-only n 0x0 0x0 ERR Flash ECC Error 2 read-write HNG Flash Hang flag 1 read-only RDY Flash Rdy 0 read-only FSYNDN Flash Sync Down Register 0x10 32 read-write n 0x0 0x0 SD Flash Sync 0 2 read-write GPIO General-purpose I/O ports GPIO 0x0 0x0 0x630 registers n ADE Analog input setting register 0x500 32 read-write n 0x0 0x0 AN0 Bit0 of ADE 0 read-write AN1 Bit1 of ADE 1 read-write AN2 Bit2 of ADE 2 read-write AN3 Bit3 of ADE 3 read-write AN4 Bit4 of ADE 4 read-write AN5 Bit5 of ADE 5 read-write AN6 Bit6 of ADE 6 read-write AN7 Bit7 of ADE 7 read-write AN8 Bit8 of ADE 8 read-write AN9 Bit9 of ADE 9 read-write DDR0 Port input/output direction setting register 0 0x200 32 read-write n 0x0 0x0 P0 Bit0 of DDR0 0 read-write P1 Bit1 of DDR0 1 read-write P2 Bit2 of DDR0 2 read-write P3 Bit3 of DDR0 3 read-write P4 Bit4 of DDR0 4 read-write PA Bit10 of DDR0 10 read-write PB Bit11 of DDR0 11 read-write PC Bit12 of DDR0 12 read-write PD Bit13 of DDR0 13 read-write PE Bit14 of DDR0 14 read-write PF Bit15 of DDR0 15 read-write DDR1 Port input/output direction setting register 1 0x204 read-write n 0x0 0x0 DDR2 Port input/output direction setting register 2 0x208 read-write n 0x0 0x0 DDR3 Port input/output direction setting register 3 0x20C read-write n 0x0 0x0 DDR4 Port input/output direction setting register 4 0x210 read-write n 0x0 0x0 DDR5 Port input/output direction setting register 5 0x214 read-write n 0x0 0x0 DDR6 Port input/output direction setting register 6 0x218 read-write n 0x0 0x0 DDR8 Port input/output direction setting register 8 0x220 read-write n 0x0 0x0 DDRE Port input/output direction setting register E 0x238 read-write n 0x0 0x0 EPFR00 Extended pin function setting register 00 0x600 32 read-write n 0x0 0x0 CROUTE Internal high-speed CR oscillation output function select bit 1 1 read-write JTAGEN0B JTAG function select bit0 16 read-write JTAGEN1S JTAG function select bit1 17 read-write NMIS NMIX function select bit 0 read-write EPFR01 Extended pin function setting register 01 0x604 32 read-write n 0x0 0x0 DTTI0C DTTIX0 function select bit 12 read-write DTTI0S DTTIX0 input select bit 16 1 read-write FRCK0S FRCK0 input select bit 18 1 read-write IC00S IC00 input select bit 20 2 read-write IC01S IC01 input select bit 23 2 read-write IC02S IC02 input select bit 26 2 read-write IC03S IC03 input select bit 29 2 read-write RTO00E RTO00E output select bit 0 1 read-write RTO01E RTO01E output select bit 2 1 read-write RTO02E RTO02E output select bit 4 1 read-write RTO03E RTO03E output select bit 6 1 read-write RTO04E RTO04E output select bit 8 1 read-write RTO05E RTO05E output select bit 10 1 read-write EPFR02 Extended pin function setting register 02 0x608 32 read-write n 0x0 0x0 DTTI1C DTTIX1 function select bit 12 read-write DTTI1S DTTIX1 input select bit 16 1 read-write FRCK1S FRCK1 input select bit 18 1 read-write IC10S IC10 input select bit 20 2 read-write IC11S IC11 input select bit 23 2 read-write IC12S IC12 input select bit 26 2 read-write IC13S IC13 input select bit 29 2 read-write RTO10E RTO10E output select bit 0 1 read-write RTO11E RTO11E output select bit 2 1 read-write RTO12E RTO12E output select bit 4 1 read-write RTO13E RTO13E output select bit 6 1 read-write RTO14E RTO14E output select bit 8 1 read-write RTO15E RTO15E output select bit 10 1 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write n 0x0 0x0 TIOA0E TIOA0 output select bit 2 1 read-write TIOA1E TIOA1E output select bit 10 1 read-write TIOA1S TIOA1 input select bit 8 1 read-write TIOA2E TIOA2 output select bit 18 1 read-write TIOA3E TIOA3E output select bit 26 1 read-write TIOA3S TIOA3 input select bit 24 1 read-write TIOB0S TIOB0 input select bit 4 1 read-write TIOB1S TIOB1 input select bit 12 1 read-write TIOB2S TIOB2 input select bit 20 1 read-write TIOB3S TIOB3 input select bit 28 1 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write n 0x0 0x0 TIOA4E TIOA4 output select bit 2 1 read-write TIOA5E TIOA5E output select bit 10 1 read-write TIOA5S TIOA5 input select bit 8 1 read-write TIOA6E TIOA6 output select bit 18 1 read-write TIOA7E TIOA7E output select bit 26 1 read-write TIOA7S TIOA7 input select bit 24 1 read-write TIOB4S TIOB4 input select bit 4 1 read-write TIOB5S TIOB5 input select bit 12 1 read-write TIOB6S TIOB6 input select bit 20 1 read-write TIOB7S TIOB7 input select Bit 28 1 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write n 0x0 0x0 EINT00S External interrupt 0 input select bit 0 1 read-write EINT01S External interrupt 1 input select bit 2 1 read-write EINT02S External interrupt 2 input select bit 4 1 read-write EINT03S External interrupt 3 input select bit 6 1 read-write EINT04S External interrupt 4 input select bit 8 1 read-write EINT05S External interrupt 5 input select bit 10 1 read-write EINT06S External interrupt 6 input select bit 12 1 read-write EINT15S External interrupt 15 input select bit 30 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write n 0x0 0x0 SCK0B SCK0 input/output select bit 8 1 read-write SCK1B SCK1 input/output select bit 14 1 read-write SCK2B SCK2 input/output select bit 20 1 read-write SCK3B SCK3 input/output select bit 26 1 read-write SIN0S SIN0S input select bit 4 1 read-write SIN1S SIN1S input select bit 10 1 read-write SIN2S SIN2S input select bit 16 1 read-write SIN3S SIN3S input select bit 22 1 read-write SOT0B SOT0B input/output select bit 6 1 read-write SOT1B SCK1B input/output select bit 12 1 read-write SOT2B SOT2B input/output select bit 18 1 read-write SOT3B SOT3B input/output select bit 24 1 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write n 0x0 0x0 SCK4B SCK4 input/output select bit 8 1 read-write SCK5B SCK5 input/output select bit 14 1 read-write SCK6B SCK6 input/output select bit 20 1 read-write SCK7B SCK7 input/output select bit 26 1 read-write SIN4S SIN4S input select bit 4 1 read-write SIN5S SIN5S input select bit 10 1 read-write SIN6S SIN6S input select bit 16 1 read-write SIN7S SIN7S input select bit 22 1 read-write SOT4B SOT4B input/output select bit 6 1 read-write SOT5B SOT5B input/output select bit 12 1 read-write SOT6B SOT6B input/output select bit 18 1 read-write SOT7B SOT7B input/output select bit 24 1 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write n 0x0 0x0 ADTRG0S ADTRG0 input select bit 12 3 read-write ADTRG1S ADTRG1 input select bit 16 3 read-write ADTRG2S ADTRG2 input select bit 20 3 read-write QAIN0S QAIN0S input select bit 0 1 read-write QAIN1S QAIN1S input select bit 6 1 read-write QBIN0S QBIN0S input select bit 2 1 read-write QBIN1S QBIN1S input select bit 8 1 read-write QZIN0S QZIN0S input select bit 4 1 read-write QZIN1S QZIN1S input select bit 10 1 read-write PCR0 Pull-up Setting Register 0 0x100 read-write n 0x0 0x0 PCR1 Pull-up Setting Register 1 0x104 read-write n 0x0 0x0 PCR2 Pull-up Setting Register 2 0x108 read-write n 0x0 0x0 PCR3 Pull-up Setting Register 3 0x10C read-write n 0x0 0x0 PCR4 Pull-up Setting Register 4 0x110 read-write n 0x0 0x0 PCR5 Pull-up Setting Register 5 0x114 read-write n 0x0 0x0 PCR6 Pull-up Setting Register 6 0x118 read-write n 0x0 0x0 PCRE Pull-up Setting Register E 0x138 read-write n 0x0 0x0 PDIR0 Port input data register 0 0x300 read-write n 0x0 0x0 PDIR1 Port input data register 1 0x304 read-write n 0x0 0x0 PDIR2 Port input data register 2 0x308 read-write n 0x0 0x0 PDIR3 Port input data register 3 0x30C read-write n 0x0 0x0 PDIR4 Port input data register 4 0x310 read-write n 0x0 0x0 PDIR5 Port input data register 5 0x314 read-write n 0x0 0x0 PDIR6 Port input data register 6 0x318 read-write n 0x0 0x0 PDIR8 Port input data register 8 0x320 read-write n 0x0 0x0 PDIRE Port input data register E 0x338 read-write n 0x0 0x0 PDOR0 Port output data register 0 0x400 read-write n 0x0 0x0 PDOR1 Port output data register 1 0x404 read-write n 0x0 0x0 PDOR2 Port output data register 2 0x408 read-write n 0x0 0x0 PDOR3 Port output data register 3 0x40C read-write n 0x0 0x0 PDOR4 Port output data register 4 0x410 read-write n 0x0 0x0 PDOR5 Port output data register 5 0x414 read-write n 0x0 0x0 PDOR6 Port output data register 6 0x418 read-write n 0x0 0x0 PDOR8 Port output data register 8 0x420 read-write n 0x0 0x0 PDORE Port output data register E 0x438 read-write n 0x0 0x0 PFR0 Port function setting register 0 0x0 32 read-write n 0x0 0x0 P0 Bit0 of PFR0 0 read-write P1 Bit1 of PFR0 1 read-write P2 Bit2 of PFR0 2 read-write P3 Bit3 of PFR0 3 read-write P4 Bit4 of PFR0 4 read-write PA Bit10 of PFR0 10 read-write PB Bit11 of PFR0 11 read-write PC Bit12 of PFR0 12 read-write PD Bit13 of PFR0 13 read-write PE Bit14 of PFR0 14 read-write PF Bit15 of PFR0 15 read-write PFR1 Port function setting register 1 0x4 32 read-write n 0x0 0x0 P0 Bit0 of PFR1 0 read-write P1 Bit1 of PFR1 1 read-write P2 Bit2 of PFR1 2 read-write P3 Bit3 of PFR1 3 read-write P4 Bit4 of PFR1 4 read-write P5 Bit5 of PFR1 5 read-write P7 Bit7 of PFR1 7 read-write P8 Bit8 of PFR1 8 read-write P9 Bit9 of PFR1 9 read-write PFR2 Port function setting register 2 0x8 32 read-write n 0x0 0x0 P1 Bit1 of PFR2 1 read-write P2 Bit2 of PFR2 2 read-write P3 Bit3 of PFR2 3 read-write PFR3 Port function setting register 3 0xC 32 read-write n 0x0 0x0 P0 Bit0 of PFR3 0 read-write P1 Bit1 of PFR3 1 read-write P2 Bit2 of PFR3 2 read-write P3 Bit3 of PFR3 3 read-write P9 Bit9 of PFR3 9 read-write PA Bit10 of PFR3 10 read-write PB Bit11 of PFR3 11 read-write PC Bit12 of PFR3 12 read-write PD Bit13 of PFR3 13 read-write PE Bit14 of PFR3 14 read-write PF Bit15 of PFR3 15 read-write PFR4 Port function setting register 4 0x10 32 read-write n 0x0 0x0 P6 Bit6 of PFR4 6 read-write P7 Bit7 of PFR4 7 read-write P9 Bit9 of PFR4 9 read-write PA Bit10 of PFR4 10 read-write PB Bit11 of PFR4 11 read-write PC Bit12 of PFR4 12 read-write PD Bit13 of PFR4 13 read-write PE Bit14 of PFR4 14 read-write PFR5 Port function setting register 5 0x14 32 read-write n 0x0 0x0 P0 Bit0 of PFR5 0 read-write P1 Bit1 of PFR5 1 read-write P2 Bit2 of PFR5 2 read-write PFR6 Port function setting register 6 0x18 32 read-write n 0x0 0x0 P0 Bit0 of PFR6 0 read-write P1 Bit1 of PFR6 1 read-write P2 Bit2 of PFR6 2 read-write PFR8 Port function setting register 8 0x20 32 read-write n 0x0 0x0 P0 Bit0 of PFR8 0 read-write P1 Bit1 of PFR8 1 read-write PFRE Port function setting register E 0x38 32 read-write n 0x0 0x0 P0 Bit0 of PFRE 0 read-write P1 Bit1 of PFRE 1 read-write P2 Bit2 of PFRE 2 read-write SPSR Special port setting register 0x580 32 read-write n 0x0 0x0 MAINXC Main clock(oscillation) pin setting bit 2 read-write SUBXC Sub clock(oscillation) pin setting bit 0 read-write HWWDT Hardware Watchdog Timer HWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x1 registers n 0xC00 0x4 registers n WDG_CTL Hardware Watchdog Timer Control Register 0x8 32 read-write n 0x0 0x0 INTEN Hardware watchdog interrupt and counter enable bit 0 read-write RESEN Hardware watchdog reset enable bit 1 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write n 0x0 0x0 WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 1 read-only n 0x0 0x0 RIS Hardware watchdog interrupt status bit 0 read-only WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 INTREQ Interrupts INTREQ 0x0 0x0 0x4 registers n 0x10 0xC4 registers n 0xB 0x1 registers n DRQSEL DMA Request Selection Register 0x0 32 read-write n 0x0 0x0 ADCSCAN0 The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC. 5 read-write ADCSCAN1 The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC. 6 read-write ADCSCAN2 The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC. 7 read-write EXINT0 The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension). 28 read-write EXINT1 The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension). 29 read-write EXINT2 The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension). 30 read-write EXINT3 The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension). 31 read-write IRQ0BT0 The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC. 8 read-write IRQ0BT2 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 read-write IRQ0BT3 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 read-write IRQ0BT4 The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC. 10 read-write IRQ0BT6 The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC. 11 read-write MFS0RX The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 12 read-write MFS0TX The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 13 read-write MFS1RX The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 14 read-write MFS1TX The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 15 read-write MFS2RX The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 16 read-write MFS2TX The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 17 read-write MFS3RX The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 18 read-write MFS3TX The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 19 read-write MFS4RX The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 20 read-write MFS4TX The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 21 read-write MFS5RX The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 22 read-write MFS5TX The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 23 read-write MFS6RX The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 24 read-write MFS6TX The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 25 read-write MFS7RX The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 26 read-write MFS7TX The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 27 read-write EXC02MON EXC02 batch read register 0x10 32 read-write n 0x0 0x0 HWINT Hardware watchdog timer interrupt request 1 read-write NMI External NMIX pin interrupt request 0 read-write IRQ00MON IRQ00 Batch Read Register 0x14 32 read-write n 0x0 0x0 FCSINT Anomalous frequency detection by CSV interrupt request 0 read-write IRQ01MON IRQ01 Batch Read Register 0x18 32 read-write n 0x0 0x0 SWWDTINT Software watchdog timer interrupt request 0 read-write IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-write n 0x0 0x0 LVDINT Low voltage detection (LVD) interrupt request 0 read-write IRQ03MON IRQ03 Batch Read Register 0x20 32 read-write n 0x0 0x0 WAVE0INT0 DTIF (motor emergency stop) interrupt request in MFT unit 0 0 read-write WAVE0INT1 WFG timer 10 interrupt request in MFT unit 0 1 read-write WAVE0INT2 WFG timer 32 interrupt request in MFT unit 0 2 read-write WAVE0INT3 WFG timer 54 interrupt request in MFT unit 0 3 read-write IRQ04MON IRQ04 Batch Read Register 0x24 32 read-write n 0x0 0x0 EXTINT0 Interrupt request on external interrupt ch.0 0 read-write EXTINT1 Interrupt request on external interrupt ch.1 1 read-write EXTINT2 Interrupt request on external interrupt ch.2 2 read-write EXTINT3 Interrupt request on external interrupt ch.3 3 read-write EXTINT4 Interrupt request on external interrupt ch.4 4 read-write EXTINT5 Interrupt request on external interrupt ch.5 5 read-write EXTINT6 Interrupt request on external interrupt ch.6 6 read-write IRQ05MON IRQ05 Batch Read Register 0x28 32 read-write n 0x0 0x0 EXTINT15 Interrupt request on external interrupt ch.15 7 read-write IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-write n 0x0 0x0 QUD0INT0 PC match interrupt request on QPRC ch.0 2 read-write QUD0INT1 PC and RC match interrupt request on QPRC ch.0 3 read-write QUD0INT2 Overflow/underflow/zero index interrupt request on QPRC ch.0 4 read-write QUD0INT3 PC count invert interrupt request on QPRC ch.0 5 read-write QUD0INT4 Interrupt request detected RC out of range on QPRC ch.0 6 read-write QUD0INT5 PC match and RC match interrupt request on QPRC ch.0 7 read-write QUD1INT0 PC match interrupt request on QPRC ch.1 8 read-write QUD1INT1 PC and RC match interrupt request on QPRC ch.1 9 read-write QUD1INT2 Overflow/underflow/zero index interrupt request on QPRC ch.1 10 read-write QUD1INT3 PC count invert interrupt request on QPRC ch.1 11 read-write QUD1INT4 Interrupt request detected RC out of range on QPRC ch.1 12 read-write QUD1INT5 PC match and RC match interrupt request on QPRC ch.1 13 read-write TIMINT1 Dual timer 1 interrupt request 0 read-write TIMINT2 Dual timer 2 interrupt request 1 read-write IRQ07MON IRQ07 Batch Read Register 0x30 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.0 0 read-write IRQ08MON IRQ08 Batch Read Register 0x34 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.0 0 read-write MFSINT1 Status interrupt request on MFS ch.0 1 read-write IRQ09MON IRQ09 Batch Read Register 0x38 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.1 0 read-write IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.1 0 read-write MFSINT1 Status interrupt request on MFS ch.1 1 read-write IRQ11MON IRQ11 Batch Read Register 0x40 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.2 0 read-write IRQ12MON IRQ12 Batch Read Register 0x44 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.2 0 read-write MFSINT1 Status interrupt request on MFS ch.2 1 read-write IRQ13MON IRQ13 Batch Read Register 0x48 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.3 0 read-write IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.3 0 read-write MFSINT1 Status interrupt request on MFS ch.3 1 read-write IRQ15MON IRQ15 Batch Read Register 0x50 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.4 0 read-write IRQ16MON IRQ16 Batch Read Register 0x54 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.4 0 read-write MFSINT1 Status interrupt request on MFS ch.4 1 read-write IRQ17MON IRQ17 Batch Read Register 0x58 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.5 0 read-write IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.5 0 read-write MFSINT1 Status interrupt request on MFS ch.5 1 read-write IRQ19MON IRQ19 Batch Read Register 0x60 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.6 0 read-write IRQ20MON IRQ20 Batch Read Register 0x64 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.6 0 read-write MFSINT1 Status interrupt request on MFS ch.6 1 read-write IRQ21MON IRQ21 Batch Read Register 0x68 32 read-write n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.7 0 read-write IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-write n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.7 0 read-write MFSINT1 Status interrupt request on MFS ch.7 1 read-write IRQ23MON IRQ23 Batch Read Register 0x70 32 read-write n 0x0 0x0 PPGINT0 Interrupt request on PPG ch.0 0 read-write PPGINT1 Interrupt request on PPG ch.2 1 read-write PPGINT2 Interrupt request on PPG ch.4 2 read-write IRQ24MON IRQ24 Batch Read Register 0x74 32 read-write n 0x0 0x0 MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 read-write MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 read-write SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 read-write WCINT Watch counter interrupt request 4 read-write IRQ25MON IRQ25 Batch Read Register 0x78 32 read-write n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 read-write ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 read-write ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 read-write ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 read-write IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-write n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 1 0 read-write ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 1 1 read-write ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 1 2 read-write ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 1 3 read-write IRQ28MON IRQ28 Batch Read Register 0x84 32 read-write n 0x0 0x0 FRT0INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0 0 read-write FRT0INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0 1 read-write FRT0INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0 2 read-write FRT0INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0 3 read-write FRT0INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0 4 read-write FRT0INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0 5 read-write IRQ29MON IRQ29 Batch Read Register 0x88 32 read-write n 0x0 0x0 ICU0INT0 Interrupt request on the input capture ch.0 in the MFT unit 0 0 read-write ICU0INT1 Interrupt request on the input capture ch.1 in the MFT unit 0 1 read-write ICU0INT2 Interrupt request on the input capture ch.2 in the MFT unit 0 2 read-write ICU0INT3 Interrupt request on the input capture ch.3 in the MFT unit 0 3 read-write IRQ30MON IRQ30 Batch Read Register 0x8C 32 read-write n 0x0 0x0 OCU0INT0 Interrupt request on the output compare ch.0 in the MFT unit 0 0 read-write OCU0INT1 Interrupt request on the output compare ch.1 in the MFT unit 0 1 read-write OCU0INT2 Interrupt request on the output compare ch.2 in the MFT unit 0 2 read-write OCU0INT3 Interrupt request on the output compare ch.3 in the MFT unit 0 3 read-write OCU0INT4 Interrupt request on the output compare ch.4 in the MFT unit 0 4 read-write OCU0INT5 Interrupt request on the output compare ch.5 in the MFT unit 0 5 read-write IRQ31MON IRQ31 Batch Read Register 0x90 32 read-write n 0x0 0x0 BTINT0 IRQ0 interrupt request on the base timer ch.0 0 read-write BTINT1 IRQ1 interrupt request on the base timer ch.0 1 read-write BTINT10 IRQ0 interrupt request on the base timer ch.5 10 read-write BTINT11 IRQ1 interrupt request on the base timer ch.5 11 read-write BTINT12 IRQ0 interrupt request on the base timer ch.6 12 read-write BTINT13 IRQ1 interrupt request on the base timer ch.6 13 read-write BTINT14 IRQ0 interrupt request on the base timer ch.7 14 read-write BTINT15 IRQ1 interrupt request on the base timer ch.7 15 read-write BTINT2 IRQ0 interrupt request on the base timer ch.1 2 read-write BTINT3 IRQ1 interrupt request on the base timer ch.1 3 read-write BTINT4 IRQ0 interrupt request on the base timer ch.2 4 read-write BTINT5 IRQ1 interrupt request on the base timer ch.2 5 read-write BTINT6 IRQ0 interrupt request on the base timer ch.3 6 read-write BTINT7 IRQ1 interrupt request on the base timer ch.3 7 read-write BTINT8 IRQ0 interrupt request on the base timer ch.4 8 read-write BTINT9 IRQ1 interrupt request on the base timer ch.4 9 read-write IRQ38MON IRQ38 Batch Read Register 0xAC 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.0. 0 read-write IRQ39MON IRQ39 Batch Read Register 0xB0 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.1. 0 read-write IRQ40MON IRQ40 Batch Read Register 0xB4 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.2. 0 read-write IRQ41MON IRQ41 Batch Read Register 0xB8 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.3. 0 read-write IRQ42MON IRQ42 Batch Read Register 0xBC 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.4. 0 read-write IRQ43MON IRQ43 Batch Read Register 0xC0 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.5. 0 read-write IRQ44MON IRQ44 Batch Read Register 0xC4 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.6. 0 read-write IRQ45MON IRQ45 Batch Read Register 0xC8 32 read-write n 0x0 0x0 DMAINT Interrupt request on DMA ch.7. 0 read-write LVD Low-voltage Detection LVD 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x5 registers n LVD 2 CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write n 0x0 0x0 LVDCL Low-voltage detection interrupt clear bit 7 read-write CTL Low-voltage Detection Voltage Control Register 0x0 8 read-write n 0x0 0x0 LVDIE Low-voltage detection interrupt enable bit 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 3 read-write RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write n 0x0 0x0 LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write STR Low-voltage Detection Interrupt Register 0x4 8 read-only n 0x0 0x0 LVDIR Low-voltage detection interrupt bit 7 read-only STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only n 0x0 0x0 LVDIRDY Low-voltage detection interrupt status flag 7 read-only MFS0 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS0RX 7 MFS0TX 8 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS1 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS1RX 9 MFS1TX 10 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS2 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS2RX 11 MFS2TX 12 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS3 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS3RX 13 MFS3TX 14 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS4 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS4RX 15 MFS4TX 16 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS5 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS5RX 17 MFS5TX 18 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS6 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS6RX 19 MFS6TX 20 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS7 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS7RX 21 MFS7TX 22 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFT0 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n WFG 3 FRTIM 28 INCAP 29 OUTCOMP 30 ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE Generates interrupt when 1 is set to TCSA.ICLR 8 read-write IRQZE Generates interrupt, when 1 is set to TCSA.IRQZF 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 ICU ch.1,0 Connecting FRT Select Register 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 ICU ch.3,2 Connecting FRT Select Register 0x61 -1 read-write n 0x0 0x0 ICU_ICSA10 ICU ch.1,0 Control Register A 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 Generates interrupt, when 1 is set to ICSA.ICP0. 4 read-write ICE1 Generates interrupt, when 1 is set to ICSA.ICP1. 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 ICU ch.3,2 Control Register A 0x7C -1 read-write n 0x0 0x0 ICU_ICSB10 ICU ch.1,0 Control Register B 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 ICU ch.3,2 Control Register B 0x7D -1 read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 OCU ch.1,0 Connecting FRT Select Register 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 OCU ch.3,2 Connecting FRT Select Register 0x59 -1 read-write n 0x0 0x0 OCU_OCFS54 OCU ch.5,4 Connecting FRT Select Register 0x5C -1 read-write n 0x0 0x0 OCU_OCSA10 OCU ch.1,0 Control Register A 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 Generates interrupt, when 1 is set to OCSA.IOP0 4 read-write IOE1 Generates interrupt, when 1 is set to OCSA.IOP1 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 OCU ch.3,2 Control Register A 0x1C -1 read-write n 0x0 0x0 OCU_OCSA54 OCU ch.5,4 Control Register A 0x20 -1 read-write n 0x0 0x0 OCU_OCSB10 OCU ch.1,0 Control Register B 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 OCU ch.3,2 Control Register B 0x1D -1 read-write n 0x0 0x0 OCU_OCSB54 OCU ch.5,4 Control Register B 0x21 -1 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT1 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE Generates interrupt when 1 is set to TCSA.ICLR 8 read-write IRQZE Generates interrupt, when 1 is set to TCSA.IRQZF 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 ICU ch.1,0 Connecting FRT Select Register 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 ICU ch.3,2 Connecting FRT Select Register 0x61 -1 read-write n 0x0 0x0 ICU_ICSA10 ICU ch.1,0 Control Register A 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 Generates interrupt, when 1 is set to ICSA.ICP0. 4 read-write ICE1 Generates interrupt, when 1 is set to ICSA.ICP1. 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 ICU ch.3,2 Control Register A 0x7C -1 read-write n 0x0 0x0 ICU_ICSB10 ICU ch.1,0 Control Register B 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 ICU ch.3,2 Control Register B 0x7D -1 read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 OCU ch.1,0 Connecting FRT Select Register 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 OCU ch.3,2 Connecting FRT Select Register 0x59 -1 read-write n 0x0 0x0 OCU_OCFS54 OCU ch.5,4 Connecting FRT Select Register 0x5C -1 read-write n 0x0 0x0 OCU_OCSA10 OCU ch.1,0 Control Register A 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 Generates interrupt, when 1 is set to OCSA.IOP0 4 read-write IOE1 Generates interrupt, when 1 is set to OCSA.IOP1 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 OCU ch.3,2 Control Register A 0x1C -1 read-write n 0x0 0x0 OCU_OCSA54 OCU ch.5,4 Control Register A 0x20 -1 read-write n 0x0 0x0 OCU_OCSB10 OCU ch.1,0 Control Register B 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 OCU ch.3,2 Control Register B 0x1D -1 read-write n 0x0 0x0 OCU_OCSB54 OCU ch.5,4 Control Register B 0x21 -1 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT_PPG PPG Configuration MFT_PPG 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x100 0x2 registers n 0x104 0x2 registers n 0x14 0x1 registers n 0x20 0x2 registers n 0x200 0x2 registers n 0x204 0x2 registers n 0x208 0x2 registers n 0x20C 0x2 registers n 0x210 0x2 registers n 0x214 0x2 registers n 0x218 0x1 registers n 0x240 0x2 registers n 0x244 0x2 registers n 0x248 0x2 registers n 0x24C 0x2 registers n 0x250 0x2 registers n 0x254 0x2 registers n 0x258 0x1 registers n 0x28 0x2 registers n 0x280 0x2 registers n 0x284 0x2 registers n 0x288 0x2 registers n 0x28C 0x2 registers n 0x290 0x2 registers n 0x294 0x2 registers n 0x298 0x1 registers n 0x2C 0x1 registers n 0x2C0 0x2 registers n 0x2C4 0x2 registers n 0x2C8 0x2 registers n 0x2CC 0x2 registers n 0x2D0 0x2 registers n 0x2D4 0x2 registers n 0x2D8 0x1 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x8 0x2 registers n 0xC 0x1 registers n PPG 23 COMP0 PPG Compare Register 0 0x8 16 read-write n 0x0 0x0 COMP1 PPG Compare Register 1 0x28 read-write n 0x0 0x0 COMP2 PPG Compare Register 2 0xC 8 read-write n 0x0 0x0 COMP3 PPG Compare Register 3 0x2C read-write n 0x0 0x0 COMP4 PPG Compare Register 4 0x10 read-write n 0x0 0x0 COMP5 PPG Compare Register 5 0x30 read-write n 0x0 0x0 COMP6 PPG Compare Register 6 0x14 read-write n 0x0 0x0 COMP7 PPG Compare Register 7 0x34 read-write n 0x0 0x0 GATEC0 PPG Gate Function Control Registers 0 0x218 8 read-write n 0x0 0x0 EDGE0 Select Start Effective Level for PPG0 0 read-write EDGE2 Select Start Effective Level for PPG2 4 read-write STRG0 Select a trigger for PPG0 1 read-write STRG2 Select a trigger for PPG2 5 read-write GATEC12 PPG Gate Function Control Registers 12 0x2D8 8 read-write n 0x0 0x0 EDGE12 Select Start Effective Level for PPG12 0 read-write EDGE14 Select Start Effective Level for PPG14 4 read-write STRG12 Select a trigger for PPG12 1 read-write STRG14 Select a trigger for PPG14 5 read-write GATEC4 PPG Gate Function Control Registers 4 0x258 8 read-write n 0x0 0x0 EDGE4 Select Start Effective Level for PPG4 0 read-write EDGE6 Select Start Effective Level for PPG6 4 read-write STRG4 Select a trigger for PPG4 1 read-write STRG6 Select a trigger for PPG6 5 read-write GATEC8 PPG Gate Function Control Registers 8 0x298 8 read-write n 0x0 0x0 EDGE10 Select Start Effective Level for PPG10 4 read-write EDGE8 Select Start Effective Level for PPG8 0 read-write STRG10 Select a trigger for PPG10 5 read-write STRG8 Select a trigger for PPG8 1 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write n 0x0 0x0 INTM Interrupt Mode Select bit 5 read-write MD PPG Operation Mode Set bits 1 1 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 1 read-write PIE PPG Interrupt Enable bit 7 read-write PUF PPG Counter Underflow bit 6 read-write TTRG PPG start trigger select bit 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 read-write n 0x0 0x0 PPGC10 PPG Operation Mode Control Register 10 0x285 read-write n 0x0 0x0 PPGC11 PPG Operation Mode Control Register 11 0x284 read-write n 0x0 0x0 PPGC12 PPG Operation Mode Control Register 12 0x2C1 read-write n 0x0 0x0 PPGC13 PPG Operation Mode Control Register 13 0x2C0 read-write n 0x0 0x0 PPGC14 PPG Operation Mode Control Register 14 0x2C5 read-write n 0x0 0x0 PPGC15 PPG Operation Mode Control Register 15 0x2C4 read-write n 0x0 0x0 PPGC2 PPG Operation Mode Control Register 2 0x205 read-write n 0x0 0x0 PPGC3 PPG Operation Mode Control Register 3 0x204 read-write n 0x0 0x0 PPGC4 PPG Operation Mode Control Register 4 0x241 read-write n 0x0 0x0 PPGC5 PPG Operation Mode Control Register 5 0x240 read-write n 0x0 0x0 PPGC6 PPG Operation Mode Control Register 6 0x245 read-write n 0x0 0x0 PPGC7 PPG Operation Mode Control Register 7 0x244 read-write n 0x0 0x0 PPGC8 PPG Operation Mode Control Register 8 0x281 read-write n 0x0 0x0 PPGC9 PPG Operation Mode Control Register 9 0x280 read-write n 0x0 0x0 PRLH0 PPG0 Reload Registers High 0x209 8 read-write n 0x0 0x0 PRLH Reload Registers High 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D read-write n 0x0 0x0 PRLH10 PPG10 Reload Registers High 0x291 read-write n 0x0 0x0 PRLH11 PPG11 Reload Registers High 0x295 read-write n 0x0 0x0 PRLH12 PPG12 Reload Registers High 0x2C9 read-write n 0x0 0x0 PRLH13 PPG13 Reload Registers High 0x2CD read-write n 0x0 0x0 PRLH14 PPG14 Reload Registers High 0x2D1 read-write n 0x0 0x0 PRLH15 PPG15 Reload Registers High 0x2D5 read-write n 0x0 0x0 PRLH2 PPG2 Reload Registers High 0x211 read-write n 0x0 0x0 PRLH3 PPG3 Reload Registers High 0x215 read-write n 0x0 0x0 PRLH4 PPG4 Reload Registers High 0x249 read-write n 0x0 0x0 PRLH5 PPG5 Reload Registers High 0x24D read-write n 0x0 0x0 PRLH6 PPG6 Reload Registers High 0x251 read-write n 0x0 0x0 PRLH7 PPG7 Reload Registers High 0x255 read-write n 0x0 0x0 PRLH8 PPG8 Reload Registers High 0x289 read-write n 0x0 0x0 PRLH9 PPG9 Reload Registers High 0x28D read-write n 0x0 0x0 PRLL0 PPG0 Reload Registers Low 0x208 8 read-write n 0x0 0x0 PRLL Reload Registers Low 0 7 read-write PRLL1 PPG1 Reload Registers Low 0x20C read-write n 0x0 0x0 PRLL10 PPG10 Reload Registers Low 0x290 read-write n 0x0 0x0 PRLL11 PPG11 Reload Registers Low 0x294 read-write n 0x0 0x0 PRLL12 PPG12 Reload Registers Low 0x2C8 read-write n 0x0 0x0 PRLL13 PPG13 Reload Registers Low 0x2CC read-write n 0x0 0x0 PRLL14 PPG14 Reload Registers Low 0x2D0 read-write n 0x0 0x0 PRLL15 PPG15 Reload Registers Low 0x2D4 read-write n 0x0 0x0 PRLL2 PPG2 Reload Registers Low 0x210 read-write n 0x0 0x0 PRLL3 PPG3 Reload Registers Low 0x214 read-write n 0x0 0x0 PRLL4 PPG4 Reload Registers Low 0x248 read-write n 0x0 0x0 PRLL5 PPG5 Reload Registers Low 0x24C read-write n 0x0 0x0 PRLL6 PPG6 Reload Registers Low 0x250 read-write n 0x0 0x0 PRLL7 PPG7 Reload Registers Low 0x254 read-write n 0x0 0x0 PRLL8 PPG8 Reload Registers Low 0x288 read-write n 0x0 0x0 PRLL9 PPG9 Reload Registers Low 0x28C read-write n 0x0 0x0 REVC Output Reverse Register 0 0x104 16 read-write n 0x0 0x0 REV00 PPG0 Output Reverse Enable bit 0 read-write REV01 PPG1 Output Reverse Enable bit 1 read-write REV02 PPG2 Output Reverse Enable bit 2 read-write REV03 PPG3 Output Reverse Enable bit 3 read-write REV04 PPG4 Output Reverse Enable bit 4 read-write REV05 PPG5 Output Reverse Enable bit 5 read-write REV06 PPG6 Output Reverse Enable bit 6 read-write REV07 PPG7 Output Reverse Enable bit 7 read-write REV08 PPG8 Output Reverse Enable bit 8 read-write REV09 PPG9 Output Reverse Enable bit 9 read-write REV10 PPG10 Output Reverse Enable bit 10 read-write REV11 PPG11 Output Reverse Enable bit 11 read-write REV12 PPG12 Output Reverse Enable bit 12 read-write REV13 PPG13 Output Reverse Enable bit 13 read-write REV14 PPG14 Output Reverse Enable bit 14 read-write REV15 PPG15 Output Reverse Enable bit 15 read-write TRG PPG Start Register 0 0x100 16 read-write n 0x0 0x0 PEN00 PPG0 Start Trigger bit 0 read-write PEN01 PPG1 Start Trigger bit 1 read-write PEN02 PPG2 Start Trigger bit 2 read-write PEN03 PPG3 Start Trigger bit 3 read-write PEN04 PPG4 Start Trigger bit 4 read-write PEN05 PPG5 Start Trigger bit 5 read-write PEN06 PPG6 Start Trigger bit 6 read-write PEN07 PPG7 Start Trigger bit 7 read-write PEN08 PPG8 Start Trigger bit 8 read-write PEN09 PPG9 Start Trigger bit 9 read-write PEN10 PPG10 Start Trigger bit 10 read-write PEN11 PPG11 Start Trigger bit 11 read-write PEN12 PPG12 Start Trigger bit 12 read-write PEN13 PPG13 Start Trigger bit 13 read-write PEN14 PPG14 Start Trigger bit 14 read-write PEN15 PPG15 Start Trigger bit 15 read-write TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write n 0x0 0x0 CS0 8-bit UP counter clock select bits for comparison 10 1 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 read-write TRG0O PPG0 trigger stop bit 12 read-write TRG2O PPG2 trigger stop bit 13 read-write TRG4O PPG4 trigger stop bit 14 read-write TRG6O PPG6 trigger stop bit 15 read-write TTCR1 PPG Start Trigger Control Register 1 0x20 16 read-write n 0x0 0x0 CS1 8-bit UP counter clock select bits for comparison 10 1 read-write MONI1 8-bit UP counter operation state monitor bit for comparison 9 read-only STR1 8-bit UP counter operation enable bit for comparison 8 read-write TRG1O PPG1 trigger stop bit 12 read-write TRG3O PPG3 trigger stop bit 13 read-write TRG5O PPG5 trigger stop bit 14 read-write TRG7O PPG7 trigger stop bit 15 read-write QPRC0 Quadrature Position/Revolution Counter 0 QPRC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n QCR QPRC Control Register 0x18 16 read-write n 0x0 0x0 AES AIN detection edge selection bits 10 1 read-write BES BIN detection edge selection bits 12 1 read-write CGE Detection edge selection bits 14 1 read-write CGSC Count clear or gate selection bit 5 read-write PCM Position counter mode bits 0 1 read-write PCRM Position counter reset mask bits 8 1 read-write PSTP Position counter stop bit 4 read-write RCM Revolution counter mode bits 2 1 read-write RSEL Register function selection bit 6 read-write SWAP Swap bit 7 read-write QECR QPRC Extension Control Register 0x1C 16 read-write n 0x0 0x0 ORNGF Outrange interrupt request flag bit 1 read-write ORNGIE Outrange interrupt enable bit 2 read-write ORNGMD Outrange mode selection bit 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write n 0x0 0x0 CDCF Count inversion interrupt request flag bit 1 read-write CDCIE Count inversion interrupt enable bit 0 read-write DIROU Last position counter flow direction bit 3 read-only DIRPC Last position counter direction bit 2 read-only QPCNRCMF PC match and RC match interrupt request flag bit 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write n 0x0 0x0 OFDF Overflow interrupt request flag bit 6 read-write OUZIE Overflow, underflow, or zero index interrupt enable bit 4 read-write QPCMF PC match interrupt request flag bit 1 read-write QPCMIE PC match interrupt enable bit 0 read-write QPRCMF PC and RC match interrupt request flag bit 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 read-write UFDF Underflow interrupt request flag bit 5 read-write ZIIF Zero index interrupt request flag bit 7 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write n 0x0 0x0 QPCCR QPRC Position Counter Compare Register 0x8 16 read-write n 0x0 0x0 QPCR QPRC Position Count Register 0x0 16 read-write n 0x0 0x0 QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write n 0x0 0x0 QRCR QPRC Revolution Count Register 0x4 16 read-write n 0x0 0x0 QPRC1 Quadrature Position/Revolution Counter 0 QPRC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n QCR QPRC Control Register 0x18 16 read-write n 0x0 0x0 AES AIN detection edge selection bits 10 1 read-write BES BIN detection edge selection bits 12 1 read-write CGE Detection edge selection bits 14 1 read-write CGSC Count clear or gate selection bit 5 read-write PCM Position counter mode bits 0 1 read-write PCRM Position counter reset mask bits 8 1 read-write PSTP Position counter stop bit 4 read-write RCM Revolution counter mode bits 2 1 read-write RSEL Register function selection bit 6 read-write SWAP Swap bit 7 read-write QECR QPRC Extension Control Register 0x1C 16 read-write n 0x0 0x0 ORNGF Outrange interrupt request flag bit 1 read-write ORNGIE Outrange interrupt enable bit 2 read-write ORNGMD Outrange mode selection bit 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write n 0x0 0x0 CDCF Count inversion interrupt request flag bit 1 read-write CDCIE Count inversion interrupt enable bit 0 read-write DIROU Last position counter flow direction bit 3 read-only DIRPC Last position counter direction bit 2 read-only QPCNRCMF PC match and RC match interrupt request flag bit 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write n 0x0 0x0 OFDF Overflow interrupt request flag bit 6 read-write OUZIE Overflow, underflow, or zero index interrupt enable bit 4 read-write QPCMF PC match interrupt request flag bit 1 read-write QPCMIE PC match interrupt enable bit 0 read-write QPRCMF PC and RC match interrupt request flag bit 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 read-write UFDF Underflow interrupt request flag bit 5 read-write ZIIF Zero index interrupt request flag bit 7 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write n 0x0 0x0 QPCCR QPRC Position Counter Compare Register 0x8 16 read-write n 0x0 0x0 QPCR QPRC Position Count Register 0x0 16 read-write n 0x0 0x0 QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write n 0x0 0x0 QRCR QPRC Revolution Count Register 0x4 16 read-write n 0x0 0x0 SBSSR Software-based Simultaneous Startup Register SBSSR 0x0 0xFC 0x2 registers n BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only n 0x0 0x0 SSSR0 Bit0 of BTSSSR 0 write-only SSSR1 Bit1 of BTSSSR 1 write-only SSSR10 Bit10 of BTSSSR 10 write-only SSSR11 Bit11 of BTSSSR 11 write-only SSSR12 Bit12 of BTSSSR 12 write-only SSSR13 Bit13 of BTSSSR 13 write-only SSSR14 Bit14 of BTSSSR 14 write-only SSSR15 Bit15 of BTSSSR 15 write-only SSSR2 Bit2 of BTSSSR 2 write-only SSSR3 Bit3 of BTSSSR 3 write-only SSSR4 Bit4 of BTSSSR 4 write-only SSSR5 Bit5 of BTSSSR 5 write-only SSSR6 Bit6 of BTSSSR 6 write-only SSSR7 Bit7 of BTSSSR 7 write-only SSSR8 Bit8 of BTSSSR 8 write-only SSSR9 Bit9 of BTSSSR 9 write-only SWWDT Software Watchdog Timer SWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n 0xC00 0x4 registers n SWDT 1 WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write n 0x0 0x0 INTEN Interrupt and counter enable bit of the software watchdog 0 read-write RESEN Reset enable bit of the software watchdog 1 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write n 0x0 0x0 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Software watchdog interrupt status bit 0 read-only WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 WC Watch Counter WC 0x0 0x0 0x3 registers n 0x10 0x2 registers n 0x14 0x1 registers n CLK_EN Division Clock Enable Register 0x14 8 read-write n 0x0 0x0 CLK_EN Division clock enable bit 0 read-write CLK_EN_R Division clock enable read bit 1 read-write CLK_SEL Clock Selection Register 0x10 16 read-write n 0x0 0x0 SEL_IN Input clock selection bit 0 read-write SEL_OUT Output clock selection bit 8 read-write WCCR Watch Counter Control Register 0x2 8 read-write n 0x0 0x0 CS Count clock select bits 2 1 read-write WCEN Watch counter operation enable bit 7 read-write WCIE Interrupt request enable bit 1 read-write WCIF Interrupt request flag bit 0 read-write WCOP Watch counter operating state flag 6 read-only WCRD Watch Counter Read Register 0x0 8 read-only n 0x0 0x0 CTR counter value 0 5 read-only WCRL Watch Counter Reload Register 0x1 8 read-write n 0x0 0x0 RLC reload value 0 5 read-write