Infineon
S6E2G2xJ
2024.04.27
S6E2G2 Series package J
CM4
r0p1
little
true
true
4
false
8
32
ADC0
ADC0 Registers
ADC
0x0
0x0
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x5
registers
n
0x24
0x1
registers
n
0x26
0x4
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x1
registers
n
0x38
0x2
registers
n
0x3C
0x2
registers
n
0x40
0x4
registers
n
0x44
0x1
registers
n
0x48
0x1
registers
n
0x4C
0x2
registers
n
0x50
0x4
registers
n
0x8
0x2
registers
n
0xC
0x6
registers
n
ADC0
76
ADCEN
A/D Operation Enable Setup Register [BHW]
0x3C
16
read-write
n
0x0
0x0
ENBL
A/D operation enable bit
0
read-write
ENBLTIME
Operation enable state transition cycle selection bits
8
7
read-write
READY
A/D operation enable state bit
1
read-only
ADCR
A/D Control Register [BHW]
0x1
8
read-write
n
0x0
0x0
CMPIE
Conversion result comparison interrupt enable bit
1
read-write
CMPIF
Conversion result comparison interrupt request bit
5
read-write
OVRIE
FIFO overrun interrupt enable bit
0
read-write
PCIE
Priority conversion interrupt enable bit
2
read-write
PCIF
Priority conversion interrupt request bit
6
read-write
SCIE
Scan conversion interrupt enable bit
3
read-write
SCIF
Scan conversion interrupt request bit
7
read-write
ADCT
Frequency Division Ratio Setup Register [BHW]
0x34
8
read-write
n
0x0
0x0
CT
Frequency division ratio setting bits
0
7
read-write
ADSR
A/D Status Register [BHW]
0x0
8
read-write
n
0x0
0x0
ADSTP
A/D conversion forced stop bit
7
read-write
FDAS
FIFO data placement selection bit
6
read-write
PCNS
Priority conversion pending flag
2
read-only
PCS
Priority conversion status flag
1
read-only
SCS
Scan conversion status flag
0
read-only
ADSS01
Sampling Time Selection Register 0 and 1 [BHW]
0x2C
16
read-write
n
0x0
0x0
TS0
Bit0 of ADSS01
0
read-write
TS1
Bit1 of ADSS01
1
read-write
TS10
Bit10 of ADSS01
10
read-write
TS11
Bit11 of ADSS01
11
read-write
TS12
Bit12 of ADSS01
12
read-write
TS13
Bit13 of ADSS01
13
read-write
TS14
Bit14 of ADSS01
14
read-write
TS15
Bit15 of ADSS01
15
read-write
TS2
Bit2 of ADSS01
2
read-write
TS3
Bit3 of ADSS01
3
read-write
TS4
Bit4 of ADSS01
4
read-write
TS5
Bit5 of ADSS01
5
read-write
TS6
Bit6 of ADSS01
6
read-write
TS7
Bit7 of ADSS01
7
read-write
TS8
Bit8 of ADSS01
8
read-write
TS9
Bit9 of ADSS01
9
read-write
ADSS23
Sampling Time Selection Register 2 and 3 [BHW]
0x28
16
read-write
n
0x0
0x0
TS16
Bit0 of ADSS23
0
read-write
TS17
Bit1 of ADSS23
1
read-write
TS18
Bit2 of ADSS23
2
read-write
TS19
Bit3 of ADSS23
3
read-write
TS20
Bit4 of ADSS23
4
read-write
TS21
Bit5 of ADSS23
5
read-write
TS22
Bit6 of ADSS23
6
read-write
TS23
Bit7 of ADSS23
7
read-write
TS24
Bit8 of ADSS23
8
read-write
TS25
Bit9 of ADSS23
9
read-write
TS26
Bit10 of ADSS23
10
read-write
TS27
Bit11 of ADSS23
11
read-write
TS28
Bit12 of ADSS23
12
read-write
TS29
Bit13 of ADSS23
13
read-write
TS30
Bit14 of ADSS23
14
read-write
TS31
Bit15 of ADSS23
15
read-write
ADST01
Sampling Time Setup Register [BHW]
0x30
16
read-write
n
0x0
0x0
ST0
Sampling time setting bits
8
4
read-write
ST1
Sampling time setting bits
0
4
read-write
STX0
Sampling time N times setting bits
13
2
read-write
STX1
Sampling time N times setting bits
5
2
read-write
CALSR
Calibration Setting Register [BHW]
0x40
32
read-write
n
0x0
0x0
CLBEN
Calibration permission bit
8
read-write
OFST
Offset calibration value setting bits
0
7
read-write
CMPCR
A/D Comparison Control Register [BHW]
0x24
8
read-write
n
0x0
0x0
CCH
Comparison target analog input channel
0
4
read-write
CMD0
Comparison mode 0
5
read-write
CMD1
Comparison mode 1
6
read-write
CMPEN
Conversion result comparison function operation enable bit
7
read-write
CMPD
A/D Comparison Value Setup Register [BHW]
0x26
16
read-write
n
0x0
0x0
CMAD
A/D conversion result value setting bits
6
9
read-write
PCCR
Priority Conversion Control Register [BHW]
0x19
8
read-write
n
0x0
0x0
ESCE
External trigger analog input selection bit
3
read-write
PEEN
Priority conversion external start enable bit
2
read-write
PEMP
Priority conversion FIFO empty bit
7
read-only
PFCLR
Priority conversion FIFO clear bit
4
read-write
PFUL
Priority conversion FIFO full bit
6
read-only
PHEN
Priority conversion timer start enable bit
1
read-write
POVR
Priority conversion overrun flag
5
read-write
PSTR
Priority conversion start bit
0
read-write
PCFD
Priority Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
PCFD_FDAS1
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
20
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCFD_FDAS1
Priority Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
PCFD
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
16
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCIS
Priority Conversion Input Selection Register [BHW]
0x20
8
read-write
n
0x0
0x0
P1A
Priority level 1 analog input selection
0
2
read-write
P2A
Priority level 2 analog input selection
3
4
read-write
PFNS
Priority Conversion FIFO Stage Count Setup Register [BHW]
0x18
8
read-write
n
0x0
0x0
PFS
Priority conversion FIFO stage count setting bits
0
1
read-write
TEST
Test bits
4
1
read-only
PRTSL
Priority Conversion Timer Trigger Selection Register [BHW]
0x38
8
read-write
n
0x0
0x0
PRTSL
Priority conversion timer trigger selection bit
0
3
read-write
SCCR
Scan Conversion Control Register [BHW]
0x9
8
read-write
n
0x0
0x0
RPT
Scan conversion repeat bit
2
read-write
SEMP
Scan conversion FIFO empty bit
7
read-only
SFCLR
Scan conversion FIFO clear bit
4
read-write
SFUL
Scan conversion FIFO full bit
6
read-only
SHEN
Scan conversion timer start enable bit
1
read-write
SOVR
Scan conversion overrun flag
5
read-write
SSTR
Scan conversion start bit
0
read-write
SCFD
Scan Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
SCFD_FDAS1
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
20
11
read-only
SCFD_FDAS1
Scan Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
SCFD
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
16
11
read-only
SCIS01
Scan Conversion Input Selection Register 1 [BHW]
0x14
16
read-write
n
0x0
0x0
AN0
Bit0 of SCIS01
0
read-write
AN1
Bit1 of SCIS01
1
read-write
AN10
Bit10 of SCIS01
10
read-write
AN11
Bit11 of SCIS01
11
read-write
AN12
Bit12 of SCIS01
12
read-write
AN13
Bit13 of SCIS01
13
read-write
AN14
Bit14 of SCIS01
14
read-write
AN15
Bit15 of SCIS01
15
read-write
AN2
Bit2 of SCIS01
2
read-write
AN3
Bit3 of SCIS01
3
read-write
AN4
Bit4 of SCIS01
4
read-write
AN5
Bit5 of SCIS01
5
read-write
AN6
Bit6 of SCIS01
6
read-write
AN7
Bit7 of SCIS01
7
read-write
AN8
Bit8 of SCIS01
8
read-write
AN9
Bit9 of SCIS01
9
read-write
SCIS23
Scan Conversion Input Selection Register 2 and 3 [BHW]
0x10
16
read-write
n
0x0
0x0
AN16
Bit0 of SCIS23
0
read-write
AN17
Bit1 of SCIS23
1
read-write
AN18
Bit2 of SCIS23
2
read-write
AN19
Bit3 of SCIS23
3
read-write
AN20
Bit4 of SCIS23
4
read-write
AN21
Bit5 of SCIS23
5
read-write
AN22
Bit6 of SCIS23
6
read-write
AN23
Bit7 of SCIS23
7
read-write
AN24
Bit8 of SCIS23
8
read-write
AN25
Bit9 of SCIS23
9
read-write
AN26
Bit10 of SCIS23
10
read-write
AN27
Bit11 of SCIS23
11
read-write
AN28
Bit12 of SCIS23
12
read-write
AN29
Bit13 of SCIS23
13
read-write
AN30
Bit14 of SCIS23
14
read-write
AN31
Bit15 of SCIS23
15
read-write
SCTSL
Scan Conversion Timer Trigger Selection Register [BHW]
0x39
8
read-write
n
0x0
0x0
SCTSL
Scan conversion timer trigger selection bit
0
3
read-write
SFNS
Scan Conversion FIFO Stage Count Setup Register [BHW]
0x8
8
read-write
n
0x0
0x0
SFS
Scan conversion FIFO stage count setting bit
0
3
read-write
WCMPCR
Range Comparison Control Register [BHW]
0x4C
8
read-write
n
0x0
0x0
RCOCD
Continuous detection specification count/state indication bits
5
2
read-write
RCOE
Range comparison execution enable bit
2
read-write
RCOIE
Range comparison interrupt request enable bit
3
read-write
RCOIRS
Selection bit of within-range and out-of- range confirmation
4
read-write
WCMPDH
Upper Limit Setup Register [BHW]
0x52
16
read-write
n
0x0
0x0
CMHD
Upper limit threshold bits
6
9
read-write
WCMPDL
Lower Limit Threshold Setup Register [BHW]
0x50
16
read-write
n
0x0
0x0
CMLD
Lower limit threshold bits
6
9
read-write
WCMPSR
Range Comparison Channel Select Register [BHW]
0x4D
8
read-write
n
0x0
0x0
WCCH
Comparison target analog input channel
0
4
read-write
WCMD
Comparison mode select bit
5
read-write
WCMRCIF
Range Comparison Flag Register [BHW]
0x48
8
read-write
n
0x0
0x0
RCINT
Range comparison interrupt factor flag
0
read-write
WCMRCOT
Range Comparison Threshold Excess Flag Register [BHW]
0x44
8
read-write
n
0x0
0x0
RCOOF
Threshold excess flag bit
0
read-write
ADC1
ADC1 Registers
ADC
0x0
0x0
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x5
registers
n
0x24
0x1
registers
n
0x26
0x4
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x1
registers
n
0x38
0x2
registers
n
0x3C
0x2
registers
n
0x40
0x4
registers
n
0x44
0x1
registers
n
0x48
0x1
registers
n
0x4C
0x2
registers
n
0x50
0x4
registers
n
0x8
0x2
registers
n
0xC
0x6
registers
n
ADC1
77
ADCEN
A/D Operation Enable Setup Register [BHW]
0x3C
16
read-write
n
0x0
0x0
ENBL
A/D operation enable bit
0
read-write
ENBLTIME
Operation enable state transition cycle selection bits
8
7
read-write
READY
A/D operation enable state bit
1
read-only
ADCR
A/D Control Register [BHW]
0x1
8
read-write
n
0x0
0x0
CMPIE
Conversion result comparison interrupt enable bit
1
read-write
CMPIF
Conversion result comparison interrupt request bit
5
read-write
OVRIE
FIFO overrun interrupt enable bit
0
read-write
PCIE
Priority conversion interrupt enable bit
2
read-write
PCIF
Priority conversion interrupt request bit
6
read-write
SCIE
Scan conversion interrupt enable bit
3
read-write
SCIF
Scan conversion interrupt request bit
7
read-write
ADCT
Frequency Division Ratio Setup Register [BHW]
0x34
8
read-write
n
0x0
0x0
CT
Frequency division ratio setting bits
0
7
read-write
ADSR
A/D Status Register [BHW]
0x0
8
read-write
n
0x0
0x0
ADSTP
A/D conversion forced stop bit
7
read-write
FDAS
FIFO data placement selection bit
6
read-write
PCNS
Priority conversion pending flag
2
read-only
PCS
Priority conversion status flag
1
read-only
SCS
Scan conversion status flag
0
read-only
ADSS01
Sampling Time Selection Register 0 and 1 [BHW]
0x2C
16
read-write
n
0x0
0x0
TS0
Bit0 of ADSS01
0
read-write
TS1
Bit1 of ADSS01
1
read-write
TS10
Bit10 of ADSS01
10
read-write
TS11
Bit11 of ADSS01
11
read-write
TS12
Bit12 of ADSS01
12
read-write
TS13
Bit13 of ADSS01
13
read-write
TS14
Bit14 of ADSS01
14
read-write
TS15
Bit15 of ADSS01
15
read-write
TS2
Bit2 of ADSS01
2
read-write
TS3
Bit3 of ADSS01
3
read-write
TS4
Bit4 of ADSS01
4
read-write
TS5
Bit5 of ADSS01
5
read-write
TS6
Bit6 of ADSS01
6
read-write
TS7
Bit7 of ADSS01
7
read-write
TS8
Bit8 of ADSS01
8
read-write
TS9
Bit9 of ADSS01
9
read-write
ADSS23
Sampling Time Selection Register 2 and 3 [BHW]
0x28
16
read-write
n
0x0
0x0
TS16
Bit0 of ADSS23
0
read-write
TS17
Bit1 of ADSS23
1
read-write
TS18
Bit2 of ADSS23
2
read-write
TS19
Bit3 of ADSS23
3
read-write
TS20
Bit4 of ADSS23
4
read-write
TS21
Bit5 of ADSS23
5
read-write
TS22
Bit6 of ADSS23
6
read-write
TS23
Bit7 of ADSS23
7
read-write
TS24
Bit8 of ADSS23
8
read-write
TS25
Bit9 of ADSS23
9
read-write
TS26
Bit10 of ADSS23
10
read-write
TS27
Bit11 of ADSS23
11
read-write
TS28
Bit12 of ADSS23
12
read-write
TS29
Bit13 of ADSS23
13
read-write
TS30
Bit14 of ADSS23
14
read-write
TS31
Bit15 of ADSS23
15
read-write
ADST01
Sampling Time Setup Register [BHW]
0x30
16
read-write
n
0x0
0x0
ST0
Sampling time setting bits
8
4
read-write
ST1
Sampling time setting bits
0
4
read-write
STX0
Sampling time N times setting bits
13
2
read-write
STX1
Sampling time N times setting bits
5
2
read-write
CALSR
Calibration Setting Register [BHW]
0x40
32
read-write
n
0x0
0x0
CLBEN
Calibration permission bit
8
read-write
OFST
Offset calibration value setting bits
0
7
read-write
CMPCR
A/D Comparison Control Register [BHW]
0x24
8
read-write
n
0x0
0x0
CCH
Comparison target analog input channel
0
4
read-write
CMD0
Comparison mode 0
5
read-write
CMD1
Comparison mode 1
6
read-write
CMPEN
Conversion result comparison function operation enable bit
7
read-write
CMPD
A/D Comparison Value Setup Register [BHW]
0x26
16
read-write
n
0x0
0x0
CMAD
A/D conversion result value setting bits
6
9
read-write
PCCR
Priority Conversion Control Register [BHW]
0x19
8
read-write
n
0x0
0x0
ESCE
External trigger analog input selection bit
3
read-write
PEEN
Priority conversion external start enable bit
2
read-write
PEMP
Priority conversion FIFO empty bit
7
read-only
PFCLR
Priority conversion FIFO clear bit
4
read-write
PFUL
Priority conversion FIFO full bit
6
read-only
PHEN
Priority conversion timer start enable bit
1
read-write
POVR
Priority conversion overrun flag
5
read-write
PSTR
Priority conversion start bit
0
read-write
PCFD
Priority Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
PCFD_FDAS1
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
20
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCFD_FDAS1
Priority Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
PCFD
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
16
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCIS
Priority Conversion Input Selection Register [BHW]
0x20
8
read-write
n
0x0
0x0
P1A
Priority level 1 analog input selection
0
2
read-write
P2A
Priority level 2 analog input selection
3
4
read-write
PFNS
Priority Conversion FIFO Stage Count Setup Register [BHW]
0x18
8
read-write
n
0x0
0x0
PFS
Priority conversion FIFO stage count setting bits
0
1
read-write
TEST
Test bits
4
1
read-only
PRTSL
Priority Conversion Timer Trigger Selection Register [BHW]
0x38
8
read-write
n
0x0
0x0
PRTSL
Priority conversion timer trigger selection bit
0
3
read-write
SCCR
Scan Conversion Control Register [BHW]
0x9
8
read-write
n
0x0
0x0
RPT
Scan conversion repeat bit
2
read-write
SEMP
Scan conversion FIFO empty bit
7
read-only
SFCLR
Scan conversion FIFO clear bit
4
read-write
SFUL
Scan conversion FIFO full bit
6
read-only
SHEN
Scan conversion timer start enable bit
1
read-write
SOVR
Scan conversion overrun flag
5
read-write
SSTR
Scan conversion start bit
0
read-write
SCFD
Scan Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
SCFD_FDAS1
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
20
11
read-only
SCFD_FDAS1
Scan Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
SCFD
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
16
11
read-only
SCIS01
Scan Conversion Input Selection Register 1 [BHW]
0x14
16
read-write
n
0x0
0x0
AN0
Bit0 of SCIS01
0
read-write
AN1
Bit1 of SCIS01
1
read-write
AN10
Bit10 of SCIS01
10
read-write
AN11
Bit11 of SCIS01
11
read-write
AN12
Bit12 of SCIS01
12
read-write
AN13
Bit13 of SCIS01
13
read-write
AN14
Bit14 of SCIS01
14
read-write
AN15
Bit15 of SCIS01
15
read-write
AN2
Bit2 of SCIS01
2
read-write
AN3
Bit3 of SCIS01
3
read-write
AN4
Bit4 of SCIS01
4
read-write
AN5
Bit5 of SCIS01
5
read-write
AN6
Bit6 of SCIS01
6
read-write
AN7
Bit7 of SCIS01
7
read-write
AN8
Bit8 of SCIS01
8
read-write
AN9
Bit9 of SCIS01
9
read-write
SCIS23
Scan Conversion Input Selection Register 2 and 3 [BHW]
0x10
16
read-write
n
0x0
0x0
AN16
Bit0 of SCIS23
0
read-write
AN17
Bit1 of SCIS23
1
read-write
AN18
Bit2 of SCIS23
2
read-write
AN19
Bit3 of SCIS23
3
read-write
AN20
Bit4 of SCIS23
4
read-write
AN21
Bit5 of SCIS23
5
read-write
AN22
Bit6 of SCIS23
6
read-write
AN23
Bit7 of SCIS23
7
read-write
AN24
Bit8 of SCIS23
8
read-write
AN25
Bit9 of SCIS23
9
read-write
AN26
Bit10 of SCIS23
10
read-write
AN27
Bit11 of SCIS23
11
read-write
AN28
Bit12 of SCIS23
12
read-write
AN29
Bit13 of SCIS23
13
read-write
AN30
Bit14 of SCIS23
14
read-write
AN31
Bit15 of SCIS23
15
read-write
SCTSL
Scan Conversion Timer Trigger Selection Register [BHW]
0x39
8
read-write
n
0x0
0x0
SCTSL
Scan conversion timer trigger selection bit
0
3
read-write
SFNS
Scan Conversion FIFO Stage Count Setup Register [BHW]
0x8
8
read-write
n
0x0
0x0
SFS
Scan conversion FIFO stage count setting bit
0
3
read-write
WCMPCR
Range Comparison Control Register [BHW]
0x4C
8
read-write
n
0x0
0x0
RCOCD
Continuous detection specification count/state indication bits
5
2
read-write
RCOE
Range comparison execution enable bit
2
read-write
RCOIE
Range comparison interrupt request enable bit
3
read-write
RCOIRS
Selection bit of within-range and out-of- range confirmation
4
read-write
WCMPDH
Upper Limit Setup Register [BHW]
0x52
16
read-write
n
0x0
0x0
CMHD
Upper limit threshold bits
6
9
read-write
WCMPDL
Lower Limit Threshold Setup Register [BHW]
0x50
16
read-write
n
0x0
0x0
CMLD
Lower limit threshold bits
6
9
read-write
WCMPSR
Range Comparison Channel Select Register [BHW]
0x4D
8
read-write
n
0x0
0x0
WCCH
Comparison target analog input channel
0
4
read-write
WCMD
Comparison mode select bit
5
read-write
WCMRCIF
Range Comparison Flag Register [BHW]
0x48
8
read-write
n
0x0
0x0
RCINT
Range comparison interrupt factor flag
0
read-write
WCMRCOT
Range Comparison Threshold Excess Flag Register [BHW]
0x44
8
read-write
n
0x0
0x0
RCOOF
Threshold excess flag bit
0
read-write
ADC2
ADC2 Registers
ADC
0x0
0x0
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x5
registers
n
0x24
0x1
registers
n
0x26
0x4
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x1
registers
n
0x38
0x2
registers
n
0x3C
0x2
registers
n
0x40
0x4
registers
n
0x44
0x1
registers
n
0x48
0x1
registers
n
0x4C
0x2
registers
n
0x50
0x4
registers
n
0x8
0x2
registers
n
0xC
0x6
registers
n
ADC2
111
ADCEN
A/D Operation Enable Setup Register [BHW]
0x3C
16
read-write
n
0x0
0x0
ENBL
A/D operation enable bit
0
read-write
ENBLTIME
Operation enable state transition cycle selection bits
8
7
read-write
READY
A/D operation enable state bit
1
read-only
ADCR
A/D Control Register [BHW]
0x1
8
read-write
n
0x0
0x0
CMPIE
Conversion result comparison interrupt enable bit
1
read-write
CMPIF
Conversion result comparison interrupt request bit
5
read-write
OVRIE
FIFO overrun interrupt enable bit
0
read-write
PCIE
Priority conversion interrupt enable bit
2
read-write
PCIF
Priority conversion interrupt request bit
6
read-write
SCIE
Scan conversion interrupt enable bit
3
read-write
SCIF
Scan conversion interrupt request bit
7
read-write
ADCT
Frequency Division Ratio Setup Register [BHW]
0x34
8
read-write
n
0x0
0x0
CT
Frequency division ratio setting bits
0
7
read-write
ADSR
A/D Status Register [BHW]
0x0
8
read-write
n
0x0
0x0
ADSTP
A/D conversion forced stop bit
7
read-write
FDAS
FIFO data placement selection bit
6
read-write
PCNS
Priority conversion pending flag
2
read-only
PCS
Priority conversion status flag
1
read-only
SCS
Scan conversion status flag
0
read-only
ADSS01
Sampling Time Selection Register 0 and 1 [BHW]
0x2C
16
read-write
n
0x0
0x0
TS0
Bit0 of ADSS01
0
read-write
TS1
Bit1 of ADSS01
1
read-write
TS10
Bit10 of ADSS01
10
read-write
TS11
Bit11 of ADSS01
11
read-write
TS12
Bit12 of ADSS01
12
read-write
TS13
Bit13 of ADSS01
13
read-write
TS14
Bit14 of ADSS01
14
read-write
TS15
Bit15 of ADSS01
15
read-write
TS2
Bit2 of ADSS01
2
read-write
TS3
Bit3 of ADSS01
3
read-write
TS4
Bit4 of ADSS01
4
read-write
TS5
Bit5 of ADSS01
5
read-write
TS6
Bit6 of ADSS01
6
read-write
TS7
Bit7 of ADSS01
7
read-write
TS8
Bit8 of ADSS01
8
read-write
TS9
Bit9 of ADSS01
9
read-write
ADSS23
Sampling Time Selection Register 2 and 3 [BHW]
0x28
16
read-write
n
0x0
0x0
TS16
Bit0 of ADSS23
0
read-write
TS17
Bit1 of ADSS23
1
read-write
TS18
Bit2 of ADSS23
2
read-write
TS19
Bit3 of ADSS23
3
read-write
TS20
Bit4 of ADSS23
4
read-write
TS21
Bit5 of ADSS23
5
read-write
TS22
Bit6 of ADSS23
6
read-write
TS23
Bit7 of ADSS23
7
read-write
TS24
Bit8 of ADSS23
8
read-write
TS25
Bit9 of ADSS23
9
read-write
TS26
Bit10 of ADSS23
10
read-write
TS27
Bit11 of ADSS23
11
read-write
TS28
Bit12 of ADSS23
12
read-write
TS29
Bit13 of ADSS23
13
read-write
TS30
Bit14 of ADSS23
14
read-write
TS31
Bit15 of ADSS23
15
read-write
ADST01
Sampling Time Setup Register [BHW]
0x30
16
read-write
n
0x0
0x0
ST0
Sampling time setting bits
8
4
read-write
ST1
Sampling time setting bits
0
4
read-write
STX0
Sampling time N times setting bits
13
2
read-write
STX1
Sampling time N times setting bits
5
2
read-write
CALSR
Calibration Setting Register [BHW]
0x40
32
read-write
n
0x0
0x0
CLBEN
Calibration permission bit
8
read-write
OFST
Offset calibration value setting bits
0
7
read-write
CMPCR
A/D Comparison Control Register [BHW]
0x24
8
read-write
n
0x0
0x0
CCH
Comparison target analog input channel
0
4
read-write
CMD0
Comparison mode 0
5
read-write
CMD1
Comparison mode 1
6
read-write
CMPEN
Conversion result comparison function operation enable bit
7
read-write
CMPD
A/D Comparison Value Setup Register [BHW]
0x26
16
read-write
n
0x0
0x0
CMAD
A/D conversion result value setting bits
6
9
read-write
PCCR
Priority Conversion Control Register [BHW]
0x19
8
read-write
n
0x0
0x0
ESCE
External trigger analog input selection bit
3
read-write
PEEN
Priority conversion external start enable bit
2
read-write
PEMP
Priority conversion FIFO empty bit
7
read-only
PFCLR
Priority conversion FIFO clear bit
4
read-write
PFUL
Priority conversion FIFO full bit
6
read-only
PHEN
Priority conversion timer start enable bit
1
read-write
POVR
Priority conversion overrun flag
5
read-write
PSTR
Priority conversion start bit
0
read-write
PCFD
Priority Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
PCFD_FDAS1
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
20
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCFD_FDAS1
Priority Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
PCFD
0x1C
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
PC
Conversion input channel bits
0
4
read-only
PD
Priority conversion result
16
11
read-only
RS
Scan conversion start factor
8
2
read-only
PCIS
Priority Conversion Input Selection Register [BHW]
0x20
8
read-write
n
0x0
0x0
P1A
Priority level 1 analog input selection
0
2
read-write
P2A
Priority level 2 analog input selection
3
4
read-write
PFNS
Priority Conversion FIFO Stage Count Setup Register [BHW]
0x18
8
read-write
n
0x0
0x0
PFS
Priority conversion FIFO stage count setting bits
0
1
read-write
TEST
Test bits
4
1
read-only
PRTSL
Priority Conversion Timer Trigger Selection Register [BHW]
0x38
8
read-write
n
0x0
0x0
PRTSL
Priority conversion timer trigger selection bit
0
3
read-write
SCCR
Scan Conversion Control Register [BHW]
0x9
8
read-write
n
0x0
0x0
RPT
Scan conversion repeat bit
2
read-write
SEMP
Scan conversion FIFO empty bit
7
read-only
SFCLR
Scan conversion FIFO clear bit
4
read-write
SFUL
Scan conversion FIFO full bit
6
read-only
SHEN
Scan conversion timer start enable bit
1
read-write
SOVR
Scan conversion overrun flag
5
read-write
SSTR
Scan conversion start bit
0
read-write
SCFD
Scan Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
SCFD_FDAS1
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
20
11
read-only
SCFD_FDAS1
Scan Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
SCFD
0xC
32
read-only
n
0x0
0x0
INVL
A/D conversion result disable bit
12
read-only
RS
Scan conversion start factor
8
1
read-only
SC
Conversion input channel bits
0
4
read-only
SD
Scan conversion result
16
11
read-only
SCIS01
Scan Conversion Input Selection Register 1 [BHW]
0x14
16
read-write
n
0x0
0x0
AN0
Bit0 of SCIS01
0
read-write
AN1
Bit1 of SCIS01
1
read-write
AN10
Bit10 of SCIS01
10
read-write
AN11
Bit11 of SCIS01
11
read-write
AN12
Bit12 of SCIS01
12
read-write
AN13
Bit13 of SCIS01
13
read-write
AN14
Bit14 of SCIS01
14
read-write
AN15
Bit15 of SCIS01
15
read-write
AN2
Bit2 of SCIS01
2
read-write
AN3
Bit3 of SCIS01
3
read-write
AN4
Bit4 of SCIS01
4
read-write
AN5
Bit5 of SCIS01
5
read-write
AN6
Bit6 of SCIS01
6
read-write
AN7
Bit7 of SCIS01
7
read-write
AN8
Bit8 of SCIS01
8
read-write
AN9
Bit9 of SCIS01
9
read-write
SCIS23
Scan Conversion Input Selection Register 2 and 3 [BHW]
0x10
16
read-write
n
0x0
0x0
AN16
Bit0 of SCIS23
0
read-write
AN17
Bit1 of SCIS23
1
read-write
AN18
Bit2 of SCIS23
2
read-write
AN19
Bit3 of SCIS23
3
read-write
AN20
Bit4 of SCIS23
4
read-write
AN21
Bit5 of SCIS23
5
read-write
AN22
Bit6 of SCIS23
6
read-write
AN23
Bit7 of SCIS23
7
read-write
AN24
Bit8 of SCIS23
8
read-write
AN25
Bit9 of SCIS23
9
read-write
AN26
Bit10 of SCIS23
10
read-write
AN27
Bit11 of SCIS23
11
read-write
AN28
Bit12 of SCIS23
12
read-write
AN29
Bit13 of SCIS23
13
read-write
AN30
Bit14 of SCIS23
14
read-write
AN31
Bit15 of SCIS23
15
read-write
SCTSL
Scan Conversion Timer Trigger Selection Register [BHW]
0x39
8
read-write
n
0x0
0x0
SCTSL
Scan conversion timer trigger selection bit
0
3
read-write
SFNS
Scan Conversion FIFO Stage Count Setup Register [BHW]
0x8
8
read-write
n
0x0
0x0
SFS
Scan conversion FIFO stage count setting bit
0
3
read-write
WCMPCR
Range Comparison Control Register [BHW]
0x4C
8
read-write
n
0x0
0x0
RCOCD
Continuous detection specification count/state indication bits
5
2
read-write
RCOE
Range comparison execution enable bit
2
read-write
RCOIE
Range comparison interrupt request enable bit
3
read-write
RCOIRS
Selection bit of within-range and out-of- range confirmation
4
read-write
WCMPDH
Upper Limit Setup Register [BHW]
0x52
16
read-write
n
0x0
0x0
CMHD
Upper limit threshold bits
6
9
read-write
WCMPDL
Lower Limit Threshold Setup Register [BHW]
0x50
16
read-write
n
0x0
0x0
CMLD
Lower limit threshold bits
6
9
read-write
WCMPSR
Range Comparison Channel Select Register [BHW]
0x4D
8
read-write
n
0x0
0x0
WCCH
Comparison target analog input channel
0
4
read-write
WCMD
Comparison mode select bit
5
read-write
WCMRCIF
Range Comparison Flag Register [BHW]
0x48
8
read-write
n
0x0
0x0
RCINT
Range comparison interrupt factor flag
0
read-write
WCMRCOT
Range Comparison Threshold Excess Flag Register [BHW]
0x44
8
read-write
n
0x0
0x0
RCOOF
Threshold excess flag bit
0
read-write
BT0
Base Timer 0
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT0
39
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT1
Base Timer 1
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT1
40
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT10
Base Timer 10
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT10
100
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT11
Base Timer 11
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT11
101
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT12
Base Timer 12
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT12_15
102
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT13
Base Timer 13
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT14
Base Timer 14
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT15
Base Timer 15
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT2
Base Timer 2
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT2
41
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT3
Base Timer 3
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT3
42
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT4
Base Timer 4
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT4
43
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT5
Base Timer 5
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT5
44
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT6
Base Timer 6
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT6
45
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT7
Base Timer 7
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT7
46
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT8
Base Timer 8
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT8
98
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BT9
Base Timer 9
BT
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BT9
99
PPG_PRLH
HIGH Width Reload Register [HW]
PPG
0x4
16
read-write
n
0x0
0x0
PPG_PRLL
LOW Width Reload Register [HW]
PPG
0x0
16
read-write
n
0x0
0x0
PPG_STC
Status Control Register [BHW]
PPG
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PPG_TMCR
Timer Control Register [BHW]
PPG
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PPG_TMCR2
Timer Control Register 2 [BHW]
PPG
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PPG_TMR
Timer Register [BHW]
PPG
0x8
16
read-only
n
0x0
0x0
PWC_DTBF
Data Buffer Register [HW]
PWC
0x4
16
read-only
n
0x0
0x0
PWC_STC
Status Control Register [BHW]
PWC
0x10
8
read-write
n
0x0
0x0
EDIE
Measurement completion interrupt request enable bit
6
read-write
EDIR
Measurement completion interrupt request bit
2
read-only
ERR
Error flag bit
7
read-only
OVIE
Overflow interrupt request enable bit
4
read-write
OVIR
Overflow interrupt request bit
0
read-write
PWC_TMCR
Timer Control Register [BHW]
PWC
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Measurement edge selection bits
8
2
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
T32
32-bit timer selection bit
7
read-write
PWC_TMCR2
Timer Control Register 2 [BHW]
PWC
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_PCSR
PWM Cycle Set Register [HW]
PWM
0x0
16
read-write
n
0x0
0x0
PWM_PDUT
PWM Duty Set Register [HW]
PWM
0x4
16
read-write
n
0x0
0x0
PWM_STC
Status Control Register [BHW]
PWM
0x10
8
read-write
n
0x0
0x0
DTIE
Duty match interrupt request enable bit
5
read-write
DTIR
Duty match interrupt request bit
1
read-write
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
PWM_TMCR
Timer Control Register [BHW]
PWM
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Count operation enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
PMSK
Pulse output mask bit
10
read-write
RTGEN
Restart enable bit
11
read-write
STRG
Software trigger bit
0
read-write
PWM_TMCR2
Timer Control Register 2 [BHW]
PWM
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
PWM_TMR
Timer Register [HW]
PWM
0x8
16
read-only
n
0x0
0x0
RT_PCSR
Cycle Set Register [HW]
RT
0x0
16
read-write
n
0x0
0x0
RT_STC
Status Control Register [BHW]
RT
0x10
8
read-write
n
0x0
0x0
TGIE
Trigger interrupt request enable bit
6
read-write
TGIR
Trigger interrupt request bit
2
read-write
UDIE
Underflow interrupt request enable bit
4
read-write
UDIR
Underflow interrupt request bit
0
read-write
RT_TMCR
Timer Control Register [BHW]
RT
0xC
16
read-write
n
0x0
0x0
CKS
Count clock selection bit
12
2
read-write
CTEN
Timer enable bit
1
read-write
EGS
Trigger input edge selection bits
8
1
read-write
FMD
Timer function selection bits
4
2
read-write
MDSE
Mode selection bit
2
read-write
OSEL
Output polarity specification bit
3
read-write
STRG
Software trigger bit
0
read-write
T32
32-bit timer selection bit
7
read-write
RT_TMCR2
Timer Control Register 2 [BHW]
RT
0x11
8
read-write
n
0x0
0x0
CKS3
Count clock selection bit
0
read-write
GATE
Gate Input Enable bit
7
read-write
RT_TMR
Timer Register [HW]
RT
0x8
16
read-only
n
0x0
0x0
BTIOSEL03
Base Timer I/O Select
BTIOSEL03
0x0
0x1
0x1
registers
n
BTSEL0123
I/O Select Register [BHW]
0x1
8
read-write
n
0x0
0x0
SEL01
I/O select bits for Ch.0/Ch.1
0
3
read-write
SEL23
I/O select bits for Ch.2/Ch.3
4
3
read-write
BTIOSEL47
Base Timer I/O Select
BTIOSEL47
0x0
0x1
0x1
registers
n
BTSEL4567
I/O Select Register [BHW]
0x1
8
read-write
n
0x0
0x0
SEL45
I/O select bits for Ch.4/Ch.5
0
3
read-write
SEL67
I/O select bits for Ch.6/Ch.7
4
3
read-write
BTIOSEL8B
Base Timer I/O Select
BTIOSEL8B
0x0
0x1
0x1
registers
n
BTSEL89AB
I/O Select Register [BHW]
0x1
8
read-write
n
0x0
0x0
SEL89
I/O select bits for Ch.8/Ch.9
0
3
read-write
SELAB
I/O select bits for Ch.A/Ch.B
4
3
read-write
BTIOSELCF
Base Timer I/O Select
BTIOSELCF
0x0
0x1
0x1
registers
n
BTSELCDEF
I/O Select Register [BHW]
0x1
8
read-write
n
0x0
0x0
SELCD
I/O select bits for Ch.C/Ch.D
0
3
read-write
SELEF
I/O select bits for Ch.E/Ch.F
4
3
read-write
CLK_GATING
Peripheral Clock Gating
CLK_GATING
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
CKEN0
Peripheral Function Clock Control Register 0 [BHW]
0x0
32
read-write
n
0x0
0x0
ADCCK0
Settings for operation clock supplying and gating to A/D converter unit 0
16
read-write
ADCCK1
Settings for operation clock supplying and gating to A/D converter unit 1
17
read-write
ADCCK2
Settings for operation clock supplying and gating to A/D converter unit 2
18
read-write
ADCCK3
Settings for operation clock supplying and gating to A/D converter unit 3
19
read-write
DMACK
Supplying and gating settings of DMAC operation clock
24
read-write
EXBCK
Settings for operation clock supplying and gating of external bus interface function
26
read-write
GIOCK
Settings for operation clock supplying and gating to GPIO function
28
read-write
MFSCK0
Settings for operation clock supply and gating to multi-function serial interface ch.0
0
read-write
MFSCK1
Settings for operation clock supply and gating to multi-function serial interface ch.1
1
read-write
MFSCK10
Settings for operation clock supply and gating to multi-function serial interface ch.10
10
read-write
MFSCK11
Settings for operation clock supply and gating to multi-function serial interface ch.11
11
read-write
MFSCK12
Settings for operation clock supply and gating to multi-function serial interface ch.12
12
read-write
MFSCK13
Settings for operation clock supply and gating to multi-function serial interface ch.13
13
read-write
MFSCK14
Settings for operation clock supply and gating to multi-function serial interface ch.14
14
read-write
MFSCK15
Settings for operation clock supply and gating to multi-function serial interface ch.15
15
read-write
MFSCK2
Settings for operation clock supply and gating to multi-function serial interface ch.2
2
read-write
MFSCK3
Settings for operation clock supply and gating to multi-function serial interface ch.3
3
read-write
MFSCK4
Settings for operation clock supply and gating to multi-function serial interface ch.4
4
read-write
MFSCK5
Settings for operation clock supply and gating to multi-function serial interface ch.5
5
read-write
MFSCK6
Settings for operation clock supply and gating to multi-function serial interface ch.6
6
read-write
MFSCK7
Settings for operation clock supply and gating to multi-function serial interface ch.7
7
read-write
MFSCK8
Settings for operation clock supply and gating to multi-function serial interface ch.8
8
read-write
MFSCK9
Settings for operation clock supply and gating to multi-function serial interface ch.9
9
read-write
CKEN1
Peripheral Function Clock Control Register 1 [BHW]
0x10
32
read-write
n
0x0
0x0
BTMCK0
Settings operation clock supply and gating to base timer 0/1/2/3
0
read-write
BTMCK1
Settings operation clock supply and gating to base timer 4/5/6/7
1
read-write
BTMCK2
Settings operation clock supply and gating to base timer 8/9/10/11
2
read-write
BTMCK3
Settings operation clock supply and gating to base timer 12/13/14/15
3
read-write
MFTCK0
Settings for operation clock supply and gating of multi-function timer 0 and PPG 0/2/4/6
8
read-write
MFTCK1
Settings for operation clock supply and gating of multi-function timer 1 and PPG 8/10/12/14
9
read-write
MFTCK2
Settings for operation clock supply and gating of multi-function timer 2 and PPG 16/18/20/22
10
read-write
MFTCK3
Settings for operation clock supply and gating of multi-function timer 3 and PPG 24/26/28/30
11
read-write
QDUCK0
Reset control of quad counter unit 0
16
read-write
QDUCK1
Reset control of quad counter unit 1
17
read-write
QDUCK2
Reset control of quad counter unit 2
18
read-write
QDUCK3
Reset control of quad counter unit 3
19
read-write
CKEN2
Peripheral Function Clock Control Register 2 [BHW]
0x20
32
read-write
n
0x0
0x0
CANCK0
Settings for clock supply and gating to CAN controller ch.0
4
read-write
CANCK1
Settings for clock supply and gating to CAN controller ch.1
5
read-write
CANCK2
Settings for clock supply and gating to CAN controller ch.2/CAN-FD controller
6
read-write
CECCK0
Settings for operation clock supply and gating to HDMI-CEC/Remote Control Reception ch.0
24
read-write
CECCK1
Settings for operation clock supply and gating to HDMI-CEC/Remote Control Reception ch.1
25
read-write
HSSPICK
Settings for operation clock supply and gating to Hi-Speed Quad SPI
28
read-write
I2SCK0
Settings for operation clock supply and gating of I2S Interface ch.0
16
read-write
I2SCK1
Settings for operation clock supply and gating of I2S Interface ch.1
17
read-write
ICCCK0
Settings for operation clock supply and gating of IC Card Interface ch.0
12
read-write
ICCCK1
Settings for operation clock supply and gating of IC Card Interface ch.1
13
read-write
IISCCK0
Settings for operation clock supply and gating of MFS I2S Interface ch.0
14
read-write
IISCCK1
Settings for operation clock supply and gating of MFS I2S Interface ch.1
15
read-write
PCRCCK
Settings for operation clock supply and gating to Programmable-CRC
20
read-write
SDCCK
Settings for operation clock supply and gating to SD card interface
8
read-write
USBCK0
Settings for operation clock supply and gating of USB(function/host) ch.0
0
read-write
USBCK1
Settings for operation clock supply and gating of USB(function/host) ch.1
1
read-write
MRST0
Peripheral Function Reset Control Register 0 [BHW]
0x4
32
read-write
n
0x0
0x0
ADCRST0
Reset control of A/D converter unit 0
16
read-write
ADCRST1
Reset control of A/D converter unit 1
17
read-write
ADCRST2
Reset control of A/D converter unit 2
18
read-write
ADCRST3
Reset control of A/D converter unit 3
19
read-write
DMARST
Reset control of DMAC
24
read-write
EXBRST
Reset control for external bus interface
26
read-write
MFSRST0
Control of software reset of multi-function serial interface ch.0
0
read-write
MFSRST1
Control of software reset of multi-function serial interface ch.1
1
read-write
MFSRST10
Control of software reset of multi-function serial interface ch.10
10
read-write
MFSRST11
Control of software reset of multi-function serial interface ch.11
11
read-write
MFSRST12
Control of software reset of multi-function serial interface ch.12
12
read-write
MFSRST13
Control of software reset of multi-function serial interface ch.13
13
read-write
MFSRST14
Control of software reset of multi-function serial interface ch.14
14
read-write
MFSRST15
Control of software reset of multi-function serial interface ch.15
15
read-write
MFSRST2
Control of software reset of multi-function serial interface ch.2
2
read-write
MFSRST3
Control of software reset of multi-function serial interface ch.3
3
read-write
MFSRST4
Control of software reset of multi-function serial interface ch.4
4
read-write
MFSRST5
Control of software reset of multi-function serial interface ch.5
5
read-write
MFSRST6
Control of software reset of multi-function serial interface ch.6
6
read-write
MFSRST7
Control of software reset of multi-function serial interface ch.7
7
read-write
MFSRST8
Control of software reset of multi-function serial interface ch.8
8
read-write
MFSRST9
Control of software reset of multi-function serial interface ch.9
9
read-write
MRST1
Peripheral Function Reset Control Register 1 [BHW]
0x14
32
read-write
n
0x0
0x0
BTMRST0
Reset control of base timer 0/1/2/3
0
read-write
BTMRST1
Reset control of base timer 4/5/6/7
1
read-write
BTMRST2
Reset control of base timer 8/9/10/11
2
read-write
BTMRST3
Reset control of base timer 12/13/14/15
3
read-write
MFTRST0
Control of multi-function timer 0 and PPG 0/2/4/6 reset control
8
read-write
MFTRST1
Control of multi-function timer 1 and PPG 8/10/12/14 reset control
9
read-write
MFTRST2
Control of multi-function timer 2 and PPG 16/18/20/22 reset control
10
read-write
MFTRST3
Control of multi-function timer 3 and PPG 24/26/28/30 reset control
11
read-write
QDURST0
Reset control of quad counter unit 0
16
read-write
QDURST1
Reset control of quad counter unit 1
17
read-write
QDURST2
Reset control of quad counter unit 2
18
read-write
QDURST3
Reset control of quad counter unit 3
19
read-write
MRST2
Peripheral Function Reset Control Register 2 [BHW]
0x24
32
read-write
n
0x0
0x0
CANRST0
Reset control of CAN controller ch.0
4
read-write
CANRST1
Reset control of CAN controller ch.1
5
read-write
CANRST2
Reset control of CAN controller ch.2/CAN-FD controller
6
read-write
CECRST0
Reset control of HDMI-CEC/Remote Control Reception ch.0
24
read-write
CECRST1
Reset control of HDMI-CEC/Remote Control Reception ch.1
25
read-write
HSSPIRST
Reset control of Hi-Speed SPI controller
28
read-write
I2SRST0
Reset control of I2S Interface ch.0
16
read-write
I2SRST1
Reset control of I2S Interface ch.1
17
read-write
ICCRST0
Reset control of IC Card Interface ch.0
12
read-write
ICCRST1
Reset control of IC Card Interface ch.1
13
read-write
IISCRST0
Reset control of MFS I2S Interface ch.0
14
read-write
IISCRST1
Reset control of MFS I2S Interface ch.1
15
read-write
PCRCRST
Reset control of Programmable-CRC
20
read-write
SDCRST
Reset control of SD card interface
8
read-write
USBRST0
Reset control of USB (function/host) ch.0
0
read-write
USBRST1
Reset control of USB (function/host) ch.1
1
read-write
CRC
CRC Registers
CRC
0x0
0x0
0x1
registers
n
0x4
0x4
registers
n
0x8
0x4
registers
n
0xC
0x4
registers
n
CRCCR
CRC Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
CRC32
CRC mode selection bit
1
read-write
CRCLSF
CRC result bit-order setting bit
5
read-write
CRCLTE
CRC result byte-order setting bit
4
read-write
FXOR
Final XOR control bit
6
read-write
INIT
Initialization bit
0
read-write
LSBFST
Bit-order setting bit
3
read-write
LTLEND
Byte-order setting bit
2
read-write
CRCIN
Input Data Register [BHW]
0x8
32
read-write
n
0x0
0x0
D
Input data
0
31
read-write
CRCINIT
Initial Value Register [BHW]
0x4
32
read-write
n
0x0
0x0
D
Initial value
0
31
read-write
CRCR
CRC Register [BHW]
0xC
32
read-only
n
0x0
0x0
D
CRC Data
0
31
read-only
CRG
Clock Unit Registers
CRG
0x0
0x0
0x24
registers
n
0x28
0x4
registers
n
0x30
0x28
registers
n
0x60
0xC
registers
n
0x74
0x4
registers
n
CSV
0
TIM
59
APBC0_PSR
APB0 Prescaler Register [W]
0x14
32
read-write
n
0x0
0x0
APBC0
APB0 bus clock frequency division ratio setting bit
0
1
read-write
APBC1_PSR
APB1 Prescaler Register [W]
0x18
32
read-write
n
0x0
0x0
APBC1
APB1 bus clock frequency division ratio setting bit
0
1
read-write
APBC1EN
APB1 clock enable bit
7
read-write
APBC1RST
APB1 bus reset control bit
4
read-write
APBC2_PSR
APB2 Prescaler Register [W]
0x1C
32
read-write
n
0x0
0x0
APBC2
APB2 bus clock frequency division ratio setting bit
0
1
read-write
APBC2EN
APB2 clock enable bit
7
read-write
APBC2RST
APB2 bus reset control bit
4
read-write
BSC_PSR
Base Clock Prescaler Register [W]
0x10
32
read-write
n
0x0
0x0
BSR
Base clock frequency division ratio setting bit
0
2
read-write
CSV_CTL
CSV control register [W]
0x40
32
read-write
n
0x0
0x0
FCD
FCS count cycle setting bits
12
2
read-write
FCSDE
FCS function enable bit
8
read-write
FCSRE
FCS reset output enable bit
9
read-write
MCSVE
Main CSV function enable bit
0
read-write
SCSVE
Sub CSV function enable bit
1
read-write
CSV_STR
CSV status register [W]
0x44
32
read-only
n
0x0
0x0
MCMF
Main clock failure detection flag
0
read-only
SCMF
Sub clock failure detection flag
1
read-only
CSW_TMR
Clock Stabilization Wait Time Register [W]
0x30
32
read-write
n
0x0
0x0
MOWT
Main clock stabilization wait time setup bit
0
3
read-write
SOWT
Sub clock stabilization wait time setup bit
4
3
read-write
DBWDT_CTL
Debug Break Watchdog Timer Control Register [W]
0x54
32
read-write
n
0x0
0x0
DPHWBE
HW-WDG debug mode break bit
7
read-write
DPSWBE
SW-WDG debug mode break bit
5
read-write
FCSWD_CTL
Frequency detection counter register [W]
0x50
32
read-only
n
0x0
0x0
FWD
Frequency detection count data
0
15
read-only
FCSWH_CTL
Frequency detection window setting register [W]
0x48
32
read-write
n
0x0
0x0
FWH
Frequency detection window setting bits (Upper)
0
15
read-write
FCSWL_CTL
Frequency detection window setting register [W]
0x4C
32
read-write
n
0x0
0x0
FWL
Frequency detection window setting bits (Lower)
0
15
read-write
INT_CLR
Interrupt Clear Register [W]
0x68
32
write-only
n
0x0
0x0
FCSC
Anomalous frequency detection interrupt cause clear bit
5
write-only
MCSC
Main oscillation stabilization completion interrupt cause clear bit
0
write-only
PCSC
PLL oscillation stabilization completion interrupt cause clear bit
2
write-only
SCSC
Sub oscillation stabilization completion interrupt cause clear bit
1
write-only
INT_ENR
Interrupt Enable Register [W]
0x60
32
read-write
n
0x0
0x0
FCSE
Anomalous frequency detection interrupt enable bit
5
read-write
MCSE
Main oscillation stabilization completion interrupt enable bit
0
read-write
PCSE
PLL oscillation stabilization completion interrupt enable bit
2
read-write
SCSE
Sub oscillation stabilization completion interrupt enable bit
1
read-write
INT_STR
Interrupt Status Register [W]
0x64
32
read-only
n
0x0
0x0
FCSI
Anomalous frequency detection interrupt status bit
5
read-only
MCSI
Main oscillation stabilization completion interrupt status bit
0
read-only
PCSI
PLL oscillation stabilization completion interrupt status bit
2
read-only
SCSI
Sub oscillation stabilization completion interrupt status bit
1
read-only
PLLCG_CTL
PLL Clock Gear Control Register [W]
0x74
32
read-write
n
0x0
0x0
PLLCGEN
PLL clock gear enable bit
0
read-write
PLLCGLP
PLL clock gear step loop configuration bits
16
7
read-write
PLLCGSSN
PLL clock gear start step number configuration bits
8
5
read-write
PLLCGSTP
PLL clock gear step configuration bits
14
1
read-write
PLLCGSTR
PLL clock gear start bit
1
read-write
PLLCGSTS
PLL clock gear start bits
6
1
read-write
PLL_CTL1
PLL Control Register 1 [W]
0x38
32
read-write
n
0x0
0x0
PLLK
PLL input clock frequency division ratio setting bit
4
3
read-write
PLLM
PLL VCO clock frequency division ratio setting bit
0
3
read-write
PLL_CTL2
PLL Control Register 2 [W]
0x3C
32
read-write
n
0x0
0x0
PLLN
PLL feedback frequency division ratio setting bit
0
5
read-write
PSW_TMR
PLL Clock Stabilization Wait Time Setup Register [W]
0x34
32
read-write
n
0x0
0x0
PINC
PLL input clock select bit
4
read-write
POWT
PLL clock stabilization wait time setup bit
0
2
read-write
RST_STR
Reset Cause Register [W]
0xC
32
read-only
n
0x0
0x0
CSVR
Clock failure detection reset flag
6
read-only
FCSR
Flag for anomalous frequency detection reset
7
read-only
HWDT
Hardware watchdog reset flag
5
read-only
INITX
INITX pin input reset flag
1
read-only
PONR
Power-on reset/low-voltage detection reset flag
0
read-only
SRST
Software reset flag
8
read-only
SWDT
Software watchdog reset flag
4
read-only
SCM_CTL
System Clock Mode Control Register [W]
0x0
32
read-write
n
0x0
0x0
MOSCE
Main clock oscillation enable bit
1
read-write
PLLE
PLL oscillation enable bit
4
read-write
RCS
Master clock switch control bits
5
2
read-write
SOSCE
Sub clock oscillation enable bit
3
read-write
SCM_STR
System Clock Mode Status Register [W]
0x4
32
read-only
n
0x0
0x0
MORDY
Main clock oscillation stable bit
1
read-only
PLRDY
PLL oscillation stable bit
4
read-only
RCM
Master clock selection bits
5
2
read-only
SORDY
Sub clock oscillation stable bit
3
read-only
STB_CTL
Standby Mode Control Register [W]
0x8
32
read-write
n
0x0
0x0
DSTM
Deep standby mode select bit
2
read-write
KEY
Standby mode control write control bit
16
15
read-write
SPL
Standby pin level setting bit
4
read-write
STM
Standby mode selection bit
0
1
read-write
SWC_PSR
Software Watchdog Clock Prescaler Register [W]
0x20
32
read-write
n
0x0
0x0
SWDS
Software watchdog clock frequency division ratio setting bit
0
1
read-write
TTC_PSR
Trace Clock Prescaler Register [W]
0x28
32
read-write
n
0x0
0x0
TTC
Trace clock frequency division ratio setting bit
0
1
read-write
CRTRIM
CR Trimming Registers
CRTRIM
0x0
0x0
0x1
registers
n
0x4
0x4
registers
n
0x8
0x4
registers
n
0xC
0x4
registers
n
MCR_FTRM
High-speed CR oscillation Frequency Trimming Register [BHW]
0x4
32
read-write
n
0x0
0x0
TRD
Frequency trimming setup bits
0
9
read-write
MCR_PSR
High-speed CR oscillation Frequency Division Setup Register [BHW]
0x0
8
read-write
n
0x0
0x0
CSR
High-speed CR oscillation frequency division ratio setting bits
0
2
read-write
MCR_RLR
High-Speed CR Oscillation Register Write-Protect Register [W]
0xC
32
read-write
n
0x0
0x0
TRMLCK
Register write-protect bits
0
31
read-write
MCR_TTRM
High-speed CR oscillation Temperature Trimming Register [BHW]
0x8
32
read-write
n
0x0
0x0
TRT
Temperature trimming setup bits
0
4
read-write
DMAC
DMAC Registers
DMAC
0x0
0x0
0x4
registers
n
0x10
0x80
registers
n
DMAC0
83
DMAC1
84
DMAC2
85
DMAC3
86
DMAC4
87
DMAC5
88
DMAC6
89
DMAC7
90
DMACA0
Configuration A Register [BHW]
0x10
32
read-write
n
0x0
0x0
BC
Block Count
16
3
read-write
EB
Enable bit (individual-channel operation enable bit)
31
read-write
IS
Input Select
23
5
read-write
PB
Pause bit (individual-channel pause bit)
30
read-write
ST
Software Trigger
29
read-write
TC
Transfer Count
0
15
read-write
DMACA1
Configuration A Register 1 [BHW]
0x20
read-write
n
0x0
0x0
DMACA2
Configuration A Register 2 [BHW]
0x30
read-write
n
0x0
0x0
DMACA3
Configuration A Register 3 [BHW]
0x40
read-write
n
0x0
0x0
DMACA4
Configuration A Register 4 [BHW]
0x50
read-write
n
0x0
0x0
DMACA5
Configuration A Register 5 [BHW]
0x60
read-write
n
0x0
0x0
DMACA6
Configuration A Register 6 [BHW]
0x70
read-write
n
0x0
0x0
DMACA7
Configuration A Register 7 [BHW]
0x80
read-write
n
0x0
0x0
DMACB0
Configuration B Register [BHW]
0x14
32
read-write
n
0x0
0x0
CI
Completion Interrupt (successful transfer completion interrupt enable)
19
read-write
EI
Error Interrupt (unsuccessful transfer completion interrupt enable)
20
read-write
EM
Enable bit Mask (EB bit clear mask)
0
read-write
FD
Fixed Destination
24
read-write
FS
Fixed Source
25
read-write
MS
Mode Select
28
1
read-write
RC
Reload Count (BC/TC reload)
23
read-write
RD
Reload Destination
21
read-write
RS
Reload Source
22
read-write
SS
Stop Status (stop status notification)
16
2
read-write
TW
Transfer Width
26
1
read-write
DMACB1
Configuration B Register 1 [BHW]
0x24
read-write
n
0x0
0x0
DMACB2
Configuration B Register 2 [BHW]
0x34
read-write
n
0x0
0x0
DMACB3
Configuration B Register 3 [BHW]
0x44
read-write
n
0x0
0x0
DMACB4
Configuration B Register 4 [BHW]
0x54
read-write
n
0x0
0x0
DMACB5
Configuration B Register 5 [BHW]
0x64
read-write
n
0x0
0x0
DMACB6
Configuration B Register 6 [BHW]
0x74
read-write
n
0x0
0x0
DMACB7
Configuration B Register 7 [BHW]
0x84
read-write
n
0x0
0x0
DMACDA0
Transfer Destination Address Register 0 [BHW]
0x1C
32
read-write
n
0x0
0x0
DMACDA1
Transfer Destination Address Register 1 [BHW]
0x2C
read-write
n
0x0
0x0
DMACDA2
Transfer Destination Address Register 2 [BHW]
0x3C
read-write
n
0x0
0x0
DMACDA3
Transfer Destination Address Register 3 [BHW]
0x4C
read-write
n
0x0
0x0
DMACDA4
Transfer Destination Address Register 4 [BHW]
0x5C
read-write
n
0x0
0x0
DMACDA5
Transfer Destination Address Register 5 [BHW]
0x6C
read-write
n
0x0
0x0
DMACDA6
Transfer Destination Address Register 6 [BHW]
0x7C
read-write
n
0x0
0x0
DMACDA7
Transfer Destination Address Register 7 [BHW]
0x8C
read-write
n
0x0
0x0
DMACR
Entire DMAC Configuration Register [BHW]
0x0
32
read-write
n
0x0
0x0
DE
DMA Enable (all-channel operation enable bit)
31
read-write
DH
DMA Halt (All-channel pause bit)
24
3
read-write
DS
DMA Stop
30
read-write
PR
Priority Rotation
28
read-write
DMACSA0
Transfer Source Address Register 0 [BHW]
0x18
32
read-write
n
0x0
0x0
DMACSA1
Transfer Source Address Register 1 [BHW]
0x28
read-write
n
0x0
0x0
DMACSA2
Transfer Source Address Register 2 [BHW]
0x38
read-write
n
0x0
0x0
DMACSA3
Transfer Source Address Register 3 [BHW]
0x48
read-write
n
0x0
0x0
DMACSA4
Transfer Source Address Register 4 [BHW]
0x58
read-write
n
0x0
0x0
DMACSA5
Transfer Source Address Register 5 [BHW]
0x68
read-write
n
0x0
0x0
DMACSA6
Transfer Source Address Register 6 [BHW]
0x78
read-write
n
0x0
0x0
DMACSA7
Transfer Source Address Register 7 [BHW]
0x88
read-write
n
0x0
0x0
DS
Low Power Consumption Mode
DS
0x0
0x4
0x1
registers
n
0x700
0x1
registers
n
0x704
0x1
registers
n
0x708
0x2
registers
n
0x70C
0x2
registers
n
0x710
0x1
registers
n
0x714
0x1
registers
n
0x800
0x10
registers
n
BUR01
Backup Registers from 1 [BHW]
0x800
8
read-write
n
0x0
0x0
BUR02
Backup Registers from 2 [BHW]
0x801
8
read-write
n
0x0
0x0
BUR03
Backup Registers from 3 [BHW]
0x802
8
read-write
n
0x0
0x0
BUR04
Backup Registers from 4 [BHW]
0x803
8
read-write
n
0x0
0x0
BUR05
Backup Registers from 5 [BHW]
0x804
8
read-write
n
0x0
0x0
BUR06
Backup Registers from 6 [BHW]
0x805
8
read-write
n
0x0
0x0
BUR07
Backup Registers from 7 [BHW]
0x806
8
read-write
n
0x0
0x0
BUR08
Backup Registers from 8 [BHW]
0x807
8
read-write
n
0x0
0x0
BUR09
Backup Registers from 9 [BHW]
0x808
8
read-write
n
0x0
0x0
BUR10
Backup Registers from 10 [BHW]
0x809
8
read-write
n
0x0
0x0
BUR11
Backup Registers from 11 [BHW]
0x80A
8
read-write
n
0x0
0x0
BUR12
Backup Registers from 12 [BHW]
0x80B
8
read-write
n
0x0
0x0
BUR13
Backup Registers from 13 [BHW]
0x80C
8
read-write
n
0x0
0x0
BUR14
Backup Registers from 14 [BHW]
0x80D
8
read-write
n
0x0
0x0
BUR15
Backup Registers from 15 [BHW]
0x80E
8
read-write
n
0x0
0x0
BUR16
Backup Registers from 16 [BHW]
0x80F
8
read-write
n
0x0
0x0
DSRAMR
Deep Standby RAM Retention Register [BHW]
0x714
8
read-write
n
0x0
0x0
SRAMR
On-chip SRAM retention control bits
0
1
read-write
PMD_CTL
RTC Mode Control Register [BHW]
0x700
8
read-write
n
0x0
0x0
RTCE
RTC mode control bit
0
read-write
RCK_CTL
Sub Clock Control Register [BHW]
0x4
8
read-write
n
0x0
0x0
CECCKE
CEC clock control bit
1
read-write
RTCCKE
RTC clock control bit
0
read-write
WIER
Deep Standby Return Enable Register [BHW]
0x70C
16
read-write
n
0x0
0x0
WLVDE
LVD interrupt return enable bit
1
read-write
WRTCE
RTC interrupt return enable bit
0
read-write
WUI1E
WKUP pin input return enable bit 1
3
read-write
WUI2E
WKUP pin input return enable bit 2
4
read-write
WUI3E
WKUP pin input return enable bit 3
5
read-write
WUI4E
WKUP pin input return enable bit 4
6
read-write
WUI5E
WKUP pin input return enable bit 5
7
read-write
WIFSR
Deep Standby Return Cause Register 2 [BHW]
0x708
16
read-only
n
0x0
0x0
WLVDI
LVD interrupt return bit
1
read-only
WRTCI
RTC interrupt return bit
0
read-only
WUI0
WKUP pin input return bit 0
2
read-only
WUI1
WKUP pin input return bit 1
3
read-only
WUI2
WKUP pin input return bit 2
4
read-only
WUI3
WKUP pin input return bit 3
5
read-only
WUI4
WKUP pin input return bit 4
6
read-only
WUI5
WKUP pin input return bit 5
7
read-only
WILVR
WKUP Pin Input Level Register [BHW]
0x710
8
read-write
n
0x0
0x0
WUI1LV
WKUP pin input level select bit 1
0
read-write
WUI2LV
WKUP pin input level select bit 2
1
read-write
WUI3LV
WKUP pin input level select bit 3
2
read-write
WUI4LV
WKUP pin input level select bit 4
3
read-write
WUI5LV
WKUP pin input level select bit 5
4
read-write
WRFSR
Deep Standby Return Cause Register 1 [BHW]
0x704
8
read-only
n
0x0
0x0
WINITX
INITX pin input reset return bit
0
read-only
WLVDH
Low-voltage detection reset return bit
1
read-only
DSTC
DSTC registers
DSTC
0x0
0x0
0xB0
registers
n
DSTC
91
DSTC_HW
112
CFG
Configuration Register [B]
0x9
8
read-write
n
0x0
0x0
ERINTE
Error interrupt enable
1
read-write
ESTE
Error stop enable
3
read-write
RBDIS
Read skip buffer disable
2
read-write
SWINTE
Software interrupt enable
0
read-write
SWPR
Software transfer priority
4
2
read-write
CMD
Command Register [B]
0x8
8
read-write
n
0x0
0x0
DESTP
Descriptor top address Register [BHW]
0x0
32
read-write
n
0x0
0x0
DQMSK0
DMA request mask Register 0 [BHW]
0x70
32
read-only
n
0x0
0x0
DQMSK1
DMA request mask Register 1 [BHW]
0x74
read-write
n
0x0
0x0
DQMSK2
DMA request mask Register 2 [BHW]
0x78
read-write
n
0x0
0x0
DQMSK3
DMA request mask Register 3 [BHW]
0x7C
read-write
n
0x0
0x0
DQMSK4
DMA request mask Register 4 [BHW]
0x80
read-write
n
0x0
0x0
DQMSK5
DMA request mask Register 5 [BHW]
0x84
read-write
n
0x0
0x0
DQMSK6
DMA request mask Register 6 [BHW]
0x88
read-write
n
0x0
0x0
DQMSK7
DMA request mask Register 7 [BHW]
0x8C
read-write
n
0x0
0x0
DQMSKCLR0
DMA request mask clear Register 0 [BHW]
0x90
32
write-only
n
0x0
0x0
DQMSKCLR1
DMA request mask clear Register 1 [BHW]
0x94
read-write
n
0x0
0x0
DQMSKCLR2
DMA request mask clear Register 2 [BHW]
0x98
read-write
n
0x0
0x0
DQMSKCLR3
DMA request mask clear Register 3 [BHW]
0x9C
read-write
n
0x0
0x0
DQMSKCLR4
DMA request mask clear Register 4 [BHW]
0xA0
read-write
n
0x0
0x0
DQMSKCLR5
DMA request mask clear Register 5 [BHW]
0xA4
read-write
n
0x0
0x0
DQMSKCLR6
DMA request mask clear Register 6 [BHW]
0xA8
read-write
n
0x0
0x0
DQMSKCLR7
DMA request mask clear Register 7 [BHW]
0xAC
read-write
n
0x0
0x0
DREQENB0
DMA request enable Register 0 [BHW]
0x10
32
read-write
n
0x0
0x0
DREQENB1
DMA request enable Register 1 [BHW]
0x14
read-write
n
0x0
0x0
DREQENB2
DMA request enable Register 2 [BHW]
0x18
read-write
n
0x0
0x0
DREQENB3
DMA request enable Register 3 [BHW]
0x1C
read-write
n
0x0
0x0
DREQENB4
DMA request enable Register 4 [BHW]
0x20
read-write
n
0x0
0x0
DREQENB5
DMA request enable Register 5 [BHW]
0x24
read-write
n
0x0
0x0
DREQENB6
DMA request enable Register 6 [BHW]
0x28
read-write
n
0x0
0x0
DREQENB7
DMA request enable Register 7 [BHW]
0x2C
read-write
n
0x0
0x0
HWDESP
Hardware DES pointer Register [BHW]
0x4
32
read-write
n
0x0
0x0
CHANNEL
CHANNEL
0
7
read-write
HWDESP
HWDESP
16
13
read-write
HWINT0
Hardware transfer interrupt Register 0 [BHW]
0x30
32
read-only
n
0x0
0x0
HWINT1
Hardware transfer interrupt Register 1 [BHW]
0x34
read-write
n
0x0
0x0
HWINT2
Hardware transfer interrupt Register 2 [BHW]
0x38
read-write
n
0x0
0x0
HWINT3
Hardware transfer interrupt Register 3 [BHW]
0x3C
read-write
n
0x0
0x0
HWINT4
Hardware transfer interrupt Register 4 [BHW]
0x40
read-write
n
0x0
0x0
HWINT5
Hardware transfer interrupt Register 5 [BHW]
0x44
read-write
n
0x0
0x0
HWINT6
Hardware transfer interrupt Register 6 [BHW]
0x48
read-write
n
0x0
0x0
HWINT7
Hardware transfer interrupt Register 7 [BHW]
0x4C
read-write
n
0x0
0x0
HWINTCLR0
Hardware transfer interrupt clear Register 0 [BHW]
0x50
32
write-only
n
0x0
0x0
HWINTCLR1
Hardware transfer interrupt clear Register 1 [BHW]
0x54
read-write
n
0x0
0x0
HWINTCLR2
Hardware transfer interrupt clear Register 2 [BHW]
0x58
read-write
n
0x0
0x0
HWINTCLR3
Hardware transfer interrupt clear Register 3 [BHW]
0x5C
read-write
n
0x0
0x0
HWINTCLR4
Hardware transfer interrupt clear Register 4 [BHW]
0x60
read-write
n
0x0
0x0
HWINTCLR5
Hardware transfer interrupt clear Register 5 [BHW]
0x64
read-write
n
0x0
0x0
HWINTCLR6
Hardware transfer interrupt clear Register 6 [BHW]
0x68
read-write
n
0x0
0x0
HWINTCLR7
Hardware transfer interrupt clear Register 7 [BHW]
0x6C
read-write
n
0x0
0x0
MONERS
Transfer Error Status Monitor Register [BHW]
0xC
32
read-only
n
0x0
0x0
DER
Double error
3
read-only
ECH
Error hardware channel
8
7
read-only
EDESP
Error DES pointer
16
13
read-only
EHS
Error hardware software
6
read-only
EST
Error status
0
2
read-only
ESTOP
Error stop
4
read-only
SWTR
Software trigger Register [H]
0xA
16
read-write
n
0x0
0x0
SWDESP
Software DES pointer
0
13
read-write
SWREQ
Software request
14
read-only
SWST
Software status
15
read-only
DT
Dual Timer
DT
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
DT
47
TIMER1BGLOAD
Background Load Register [W]
0x18
32
read-write
n
0x0
0x0
TIMER1CONTROL
Control Register [W]
0x8
32
read-write
n
0x0
0x0
INTENABLE
Interrupt enable bit
5
read-write
ONESHOT
One-shot mode bit
0
read-write
TIMEREN
Enable bit
7
read-write
TIMERMODE
Mode bit
6
read-write
TIMERPRE
Prescale bits
2
1
read-write
TIMERSIZE
Counter size bit
1
read-write
TIMER1INTCLR
Interrupt Clear Register [W]
0xC
32
write-only
n
0x0
0x0
TIMER1LOAD
Load Register [W]
0x0
32
read-write
n
0x0
0x0
TIMER1MIS
Masked Interrupt Status Register [W]
0x14
32
read-only
n
0x0
0x0
TIMER1MIS
Masked Interrupt Status bit
0
read-only
TIMER1RIS
Interrupt Status Register [W]
0x10
32
read-only
n
0x0
0x0
TIMER1RIS
Interrupt Status Register bit
0
read-only
TIMER1VALUE
Value Register [W]
0x4
32
read-only
n
0x0
0x0
TIMER2BGLOAD
Background Load Register [W]
0x38
read-write
n
0x0
0x0
TIMER2CONTROL
Control Register [W]
0x28
read-write
n
0x0
0x0
TIMER2INTCLR
Interrupt Clear Register [W]
0x2C
read-write
n
0x0
0x0
TIMER2LOAD
Load Register [W]
0x20
read-write
n
0x0
0x0
TIMER2MIS
Masked Interrupt Status Register [W]
0x34
32
read-only
n
0x0
0x0
TIMER2MIS
Masked Interrupt Status bit
0
read-only
TIMER2RIS
Interrupt Status Register [W]
0x30
32
read-only
n
0x0
0x0
TIMER2RIS
Interrupt Status Register bit
0
read-only
TIMER2VALUE
Value Register [W]
0x24
read-write
n
0x0
0x0
ECC_CAPTURE
ECC Capture Address
ECC_CAPTURE
0x0
0x0
0x4
registers
n
FERRAD
Flash ECC Error Address Capture Register [W]
0x0
32
read-only
n
0x0
0x0
ERRAD
Flash ECC Error Address Capture
0
22
read-only
ETHERNET_CONTROL
Ethernet system control
ETHERNET_CONTROL
0x0
0x0
0x4
registers
n
0x8
0x4
registers
n
ETH_CLKG
Clock Gating Register [BHW]
0x8
32
read-write
n
0x0
0x0
MACEN
Select the system clock supply to Ethernet-MAC
0
1
read-write
ETH_MODE
Mode Select Register [BHW]
0x0
32
read-write
n
0x0
0x0
IFMODE
Mode selector
0
read-write
PPSSEL
Select either of the system time counter pulse outputs of the Ethernet-MAC PTP function to output to E_PPS0_PPS1 pin
28
read-write
RST0
reset signal against Ethernet-MAC (ch.0)
8
read-write
RST1
reset signal against Ethernet-MAC (ch.1)
9
read-write
ETHERNET_MAC0
Ethernet-MAC 0
ETHERNET_MAC
0x0
0x0
0x20
registers
n
0x100
0x78
registers
n
0x1000
0x28
registers
n
0x102C
0x4
registers
n
0x1048
0x10
registers
n
0x180
0x60
registers
n
0x200
0x4
registers
n
0x208
0x4
registers
n
0x210
0x38
registers
n
0x250
0x38
registers
n
0x28
0x98
registers
n
0x700
0x38
registers
n
0x800
0x80
registers
n
0xD8
0x4
registers
n
ETHER0
82
AHBSR
AHB Status Register [BHW]
0x102C
32
read-only
n
0x0
0x0
AHBS
AHB Status
0
read-only
ATNR
Auxiliary Time Stamp - Nanoseconds Register [BHW]
0x730
32
read-only
n
0x0
0x0
ATN
ATN
0
30
read-only
ATSR
Auxiliary Time Stamp - Seconds Register [BHW]
0x734
32
read-only
n
0x0
0x0
ATS
ATS
0
31
read-only
BMR
Bus Mode Register [BHW]
0x1000
32
read-write
n
0x0
0x0
AAL
Address-Aligned Beats
25
read-write
ATDS
Alternate Descriptor Size
7
read-write
DA
DMA Arbitration scheme
1
read-write
DSL
Descriptor Skip Length
2
4
read-write
FB
Fixed Burst
16
read-write
MB
Mixed Burst
26
read-write
PBL
Programmable Burst Length
8
5
read-write
PR
Rx:Tx priority ratio
14
1
read-write
RPBL
RxDMA PBL
17
5
read-write
SWR
Software Reset
0
read-write
TXPR
Transmit Priority
27
read-write
USP
Use Separate PBL
23
read-write
_8XPBL
8xPBL Mode
24
read-write
CHRBAR
Current Host Receive Buffer Address Register [BHW]
0x1054
32
read-only
n
0x0
0x0
HRBAR
Host Receive Buffer Address Register
0
31
read-only
CHRDR
Current Host Receive Descriptor Register [BHW]
0x104C
32
read-only
n
0x0
0x0
HRDAP
Host Receive Descriptor Address Pointer
0
31
read-only
CHTBAR
Current Host Transmit Buffer Address Register [BHW]
0x1050
32
read-only
n
0x0
0x0
HTBAR
Host Transmit Buffer Address Register
0
31
read-only
CHTDR
Current Host Transmit Descriptor Register [BHW]
0x1048
32
read-only
n
0x0
0x0
HTDAP
Host Transmit Descriptor Address Pointer
0
31
read-only
FCR
Flow Control Register [BHW]
0x18
32
read-write
n
0x0
0x0
DZPQ
Disable Zero-Quanta Pause
7
read-write
FCB_BPA
Flow Control Busy/Backpressure Activate
0
read-write
PLT
Pause Low Threshold
4
1
read-write
PT
Pause Time
16
15
read-write
RFE
Receive Flow Control Enable
2
read-write
TFE
Transmit Flow Control Enable
1
read-write
UP
Unicast Pause Frame detect
3
read-write
GAR
GMII/MII Address Register [BHW]
0x10
32
read-write
n
0x0
0x0
CR
Application Clock Range
2
3
read-write
GB
GMII/MII Busy
0
read-write
GR
GMII Register
6
4
read-write
GW
GMII/MII Write
1
read-write
PA
Physical Layer Address
11
4
read-write
GDR
GMII/MII Data Register [BHW]
0x14
32
read-write
n
0x0
0x0
GD
GMII/MII Data Register
0
15
read-write
IER
Interrupt Enable Register [BHW]
0x101C
32
read-write
n
0x0
0x0
AIE
Abnormal Interrupt Summary Enable
15
read-write
ERE
Early Receive Interrupt Enable
14
read-write
ETE
Early Transmit Interrupt Enable
10
read-write
FBE
Fatal Bus Error Enable
13
read-write
NIE
Normal Interrupt Summary Enable
16
read-write
OVE
Receive Overflow Enable
4
read-only
RIE
Receive Interrupt Enable
6
read-write
RSE
Receive Process Stopped Enable
8
read-write
RUE
Receive Buffer Unavailable Enable
7
read-write
RWE
Receive Watchdog Timeout Enable
9
read-write
TIE
Transmit Interrupt
0
read-write
TJE
Transmit Jabber Timeout
3
read-write
TSE
Transmit Process Stopped
1
read-write
TUE
Transmit Buffer Unavailable
2
read-write
UNE
Transmit underflow Enable
5
read-write
IMR
Interrupt Mask Register [BHW]
0x3C
32
read-write
n
0x0
0x0
LPIIM
LPI Interrupt Mask
10
read-write
PIM
PMT Interrupt Mask
3
read-write
RGIM
RGMII Interrupt Mask
0
read-write
TSIM
Time Stamp Interrupt Mask
9
read-write
ISR
Interrupt Status Register [BHW]
0x38
32
read-only
n
0x0
0x0
COIS
MMC Receive Checksum Offload Interrupt Status
7
read-only
LPIIS
LPI Interrupt Status
10
read-only
MIS
MMC Interrupt Status
4
read-only
PIS
PMT Interrupt Status
3
read-only
RGIS
RGMII Interrupt Status
0
read-only
RIS
MMC Receive Interrupt Status
5
read-only
TIS
MMC Transmit Interrupt Status
6
read-only
TSIS
Time Stamp Interrupt Status
9
read-only
LPICSR
LPI Control and Status Register [BHW]
0x30
32
read-write
n
0x0
0x0
LPIEN
LPI Enable
16
read-write
LPITXA
LPI TX Automate
19
read-write
PLS
PHY Link Status
17
read-write
PLSEN
PHY Link Status Enable
18
read-write
RLPIEN
Receive LPI Entry
2
read-only
RLPIEX
Receive LPI Exit
3
read-only
RLPIST
Receive LPI State
9
read-only
TLPIEN
Transmit LPI Entry
0
read-only
TLPIEX
Transmit LPI Exit
1
read-only
TLPIST
Transmit LPI State
8
read-only
LPITCR
LPI Timers Control Register [BHW]
0x34
32
read-write
n
0x0
0x0
LIT
LPI LS TIMER
16
9
read-write
TWT
LPI TW TIMER
0
15
read-write
MAR0H
MAC Address0 Register (High) [BHW]
0x40
32
read-write
n
0x0
0x0
A0
MAC Address0
0
15
read-write
MO
Must be one
31
read-only
MAR0L
MAC Address0 Register (Low) [BHW]
0x44
32
read-write
n
0x0
0x0
A0
MAC Address0
0
31
read-write
MAR10H
MAC Address10 Register -High [BHW]
0x90
read-write
n
0x0
0x0
MAR10L
MAC Address10 Register -Low [BHW]
0x94
read-write
n
0x0
0x0
MAR11H
MAC Address11 Register -High [BHW]
0x98
read-write
n
0x0
0x0
MAR11L
MAC Address11 Register -Low [BHW]
0x9C
read-write
n
0x0
0x0
MAR12H
MAC Address12 Register -High [BHW]
0xA0
read-write
n
0x0
0x0
MAR12L
MAC Address12 Register -Low [BHW]
0xA4
read-write
n
0x0
0x0
MAR13H
MAC Address13 Register -High [BHW]
0xA8
read-write
n
0x0
0x0
MAR13L
MAC Address13 Register -Low [BHW]
0xAC
read-write
n
0x0
0x0
MAR14H
MAC Address14 Register -High [BHW]
0xB0
read-write
n
0x0
0x0
MAR14L
MAC Address14 Register -Low [BHW]
0xB4
read-write
n
0x0
0x0
MAR15H
MAC Address15 Register -High [BHW]
0xB8
read-write
n
0x0
0x0
MAR15L
MAC Address15 Register -Low [BHW]
0xBC
read-write
n
0x0
0x0
MAR16H
MAC Address16 Register -High [BHW]
0x800
read-write
n
0x0
0x0
MAR16L
MAC Address16 Register -Low [BHW]
0x804
read-write
n
0x0
0x0
MAR17H
MAC Address17 Register -High [BHW]
0x808
read-write
n
0x0
0x0
MAR17L
MAC Address17 Register -Low [BHW]
0x80C
read-write
n
0x0
0x0
MAR18H
MAC Address18 Register -High [BHW]
0x810
read-write
n
0x0
0x0
MAR18L
MAC Address18 Register -Low [BHW]
0x814
read-write
n
0x0
0x0
MAR19H
MAC Address19 Register -High [BHW]
0x818
read-write
n
0x0
0x0
MAR19L
MAC Address19 Register -Low [BHW]
0x81C
read-write
n
0x0
0x0
MAR1H
MAC Address1 Register -High [BHW]
0x48
32
read-write
n
0x0
0x0
A
MAC Address
0
15
read-write
AE
Address Enable
31
read-write
MBC
Mask Byte Control
24
5
read-write
SA
Source Address
30
read-write
MAR1L
MAC Address1 Register -Low [BHW]
0x4C
32
read-write
n
0x0
0x0
A
MAC Address
0
31
read-write
MAR20H
MAC Address20 Register -High [BHW]
0x820
read-write
n
0x0
0x0
MAR20L
MAC Address20 Register -Low [BHW]
0x824
read-write
n
0x0
0x0
MAR21H
MAC Address21 Register -High [BHW]
0x828
read-write
n
0x0
0x0
MAR21L
MAC Address21 Register -Low [BHW]
0x82C
read-write
n
0x0
0x0
MAR22H
MAC Address22 Register -High [BHW]
0x830
read-write
n
0x0
0x0
MAR22L
MAC Address22 Register -Low [BHW]
0x834
read-write
n
0x0
0x0
MAR23H
MAC Address23 Register -High [BHW]
0x838
read-write
n
0x0
0x0
MAR23L
MAC Address23 Register -Low [BHW]
0x83C
read-write
n
0x0
0x0
MAR24H
MAC Address24 Register -High [BHW]
0x840
read-write
n
0x0
0x0
MAR24L
MAC Address24 Register -Low [BHW]
0x844
read-write
n
0x0
0x0
MAR25H
MAC Address25 Register -High [BHW]
0x848
read-write
n
0x0
0x0
MAR25L
MAC Address25 Register -Low [BHW]
0x84C
read-write
n
0x0
0x0
MAR26H
MAC Address26 Register -High [BHW]
0x850
read-write
n
0x0
0x0
MAR26L
MAC Address26 Register -Low [BHW]
0x854
read-write
n
0x0
0x0
MAR27H
MAC Address27 Register -High [BHW]
0x858
read-write
n
0x0
0x0
MAR27L
MAC Address27 Register -Low [BHW]
0x85C
read-write
n
0x0
0x0
MAR28H
MAC Address28 Register -High [BHW]
0x860
read-write
n
0x0
0x0
MAR28L
MAC Address28 Register -Low [BHW]
0x864
read-write
n
0x0
0x0
MAR29H
MAC Address29 Register -High [BHW]
0x868
read-write
n
0x0
0x0
MAR29L
MAC Address29 Register -Low [BHW]
0x86C
read-write
n
0x0
0x0
MAR2H
MAC Address2 Register -High [BHW]
0x50
read-write
n
0x0
0x0
MAR2L
MAC Address2 Register -Low [BHW]
0x54
read-write
n
0x0
0x0
MAR30H
MAC Address30 Register -High [BHW]
0x870
read-write
n
0x0
0x0
MAR30L
MAC Address30 Register -Low [BHW]
0x874
read-write
n
0x0
0x0
MAR31H
MAC Address31 Register -High [BHW]
0x878
read-write
n
0x0
0x0
MAR31L
MAC Address31 Register -Low [BHW]
0x87C
read-write
n
0x0
0x0
MAR3H
MAC Address3 Register -High [BHW]
0x58
read-write
n
0x0
0x0
MAR3L
MAC Address3 Register -Low [BHW]
0x5C
read-write
n
0x0
0x0
MAR4H
MAC Address4 Register -High [BHW]
0x60
read-write
n
0x0
0x0
MAR4L
MAC Address4 Register -Low [BHW]
0x64
read-write
n
0x0
0x0
MAR5H
MAC Address5 Register -High [BHW]
0x68
read-write
n
0x0
0x0
MAR5L
MAC Address5 Register -Low [BHW]
0x6C
read-write
n
0x0
0x0
MAR6H
MAC Address6 Register -High [BHW]
0x70
read-write
n
0x0
0x0
MAR6L
MAC Address6 Register -Low [BHW]
0x74
read-write
n
0x0
0x0
MAR7H
MAC Address7 Register -High [BHW]
0x78
read-write
n
0x0
0x0
MAR7L
MAC Address7 Register -Low [BHW]
0x7C
read-write
n
0x0
0x0
MAR8H
MAC Address8 Register -High [BHW]
0x80
read-write
n
0x0
0x0
MAR8L
MAC Address8 Register -Low [BHW]
0x84
read-write
n
0x0
0x0
MAR9H
MAC Address9 Register -High [BHW]
0x88
read-write
n
0x0
0x0
MAR9L
MAC Address9 Register -Low [BHW]
0x8C
read-write
n
0x0
0x0
MCR
MAC Configuration Register [BHW]
0x0
32
read-write
n
0x0
0x0
ACS
Automatic Pad/CRC Stripping
7
read-write
BE
Frame Burst Enable
21
read-write
BL
Back-off Limit
5
1
read-write
CST
CRC stripping for Type frames
25
read-write
DC
Deferral Check
4
read-write
DCRS
Disable Carrier Sense During Transaction
16
read-write
DM
Duplex mode
11
read-write
DO
Disable Receive Own
13
read-write
DR
Disable Retry
9
read-write
FES
Speed
14
read-write
IFG
Inter-Frame GAP
17
2
read-write
IPC
Checksum Offload
10
read-write
JD
Jabber Disable
22
read-write
JE
Jumbo Frame Enable
20
read-write
LM
Loop-back Mode
12
read-write
LUD
Link Up/Down in RGMII
8
read-write
PS
Port Select
15
read-write
RE
Receiver Enable
2
read-write
TC
Transmit Configuration in RGMII
24
read-write
TE
Transmitter Enable
3
read-write
WD
Watchdog Disable
23
read-write
MFBOCR
Missed Frame and Buffer Overflow Counter Register [BHW]
0x1020
32
read-only
n
0x0
0x0
NMFF
Number of Missed frame by Ethernet-MAC
17
10
read-only
NMFH
Number of Missed frame by HOST
0
15
read-only
ONMFF
Overflow NMFF
28
read-only
ONMFH
Overflow NMFH
16
read-only
MFFR
MAC Frame Filter Register [BHW]
0x4
32
read-write
n
0x0
0x0
DAIF
DA Inverse Filtering
3
read-write
DB
Disable Broadcast Frames
5
read-write
HMC
Hash Multicast
2
read-write
HPF
Hash or Perfect Filter
10
read-write
HUC
Hash Unicast
1
read-write
PCF
Pass Control Frames
6
1
read-write
PM
Pass All Multicast
4
read-write
PR
Promiscuous Mode
0
read-write
RA
Receive All
31
read-write
SAF
Source Address Filter
9
read-write
SAIF
Source Address Inverse Filter
8
read-write
MHTRH
MAC Hash Table Register (High) [BHW]
0x8
32
read-write
n
0x0
0x0
HTH
the upper 32 bits of the hash table in the HTH
0
31
read-write
MHTRL
MAC Hash Table Register (Low) [BHW]
0xC
32
read-write
n
0x0
0x0
HTL
the lower 32 bits of the hash table in the HTL
0
31
read-write
MMC_CNTL
MMC Control Register [BHW]
0x100
32
read-write
n
0x0
0x0
B
Bits of MMC_CNTL
0
5
read-write
MMC_INTR_MASK_RX
MMC Receive Interrupt Mask Register [BHW]
0x10C
32
read-write
n
0x0
0x0
B
Bits of MMC_INTR_MASK_RX
0
23
read-write
MMC_INTR_MASK_TX
MMC Transmit Interrupt Mask Register [BHW]
0x110
32
read-write
n
0x0
0x0
B
Bits of MMC_INTR_MASK_TX
0
24
read-write
MMC_INTR_RX
Receive Interrupt Register [BHW]
0x104
32
read-only
n
0x0
0x0
B
Bits of MMC_INTR_RX
0
23
read-write
MMC_INTR_TX
MMC Transmit Interrupt Register [BHW]
0x108
32
read-only
n
0x0
0x0
B
Bits of MMC_INTR_TX
0
24
read-write
MMC_IPC_INTR_MASK_RX
MMC Receive Checksum Offload Interrupt Mask Register [BHW]
0x200
32
read-write
n
0x0
0x0
BH
Higher bits of MMC_IPC_INTR_MASK_RX
16
13
read-write
BL
Lower bits of MMC_IPC_INTR_MASK_RX
0
13
read-write
MMC_IPC_INTR_RX
MMC Receive Checksum Offload Interrupt Register [BHW]
0x208
32
read-only
n
0x0
0x0
BH
Higher bits of MMC_IPC_INTR_RX
16
13
read-write
BL
Lower bits of MMC_IPC_INTR_RX
0
13
read-write
OMR
Operation Mode Register [BHW]
0x1018
32
read-write
n
0x0
0x0
DFF
Disable Flushing of Received Frames
24
read-write
DT
Disable Dropping of TCP/IP Checksum Error Frames
26
read-write
FEF
Forward Error Frames
7
read-write
FTF
Flush Transmit FIFO
20
read-write
FUF
Forward Undersized Good Frames
6
read-write
OSF
Operate on Second Frame
2
read-write
RSF
Receive Store and Forward
25
read-write
RTC
Receive Threshold Control
3
1
read-write
SR
Start/Stop Receive
1
read-write
ST
Start/Stop Transmission Command
13
read-write
TSF
Transmit Store Forward
21
read-write
TTC
Transmit Threshold Control
14
2
read-write
PMTR
PMT Register [BHW]
0x2C
32
read-write
n
0x0
0x0
GU
Global Unicast
9
read-write
MPE
Magic Packet Enable
1
read-write
MPR
Magic Packet Received
5
read-only
PD
Power Down
0
read-write
RWFFRPR
Remote Wake-up Frame Filter Register Pointer Reset
31
read-write
WFE
Wake-Up Frame Enable
2
read-write
WPR
Wake Up Frame Receive
6
read-only
PPSCR
PPS Control Register [BHW]
0x72C
32
read-write
n
0x0
0x0
PPSCTRL
Controls the frequency of the PPS output
0
3
read-write
RDLAR
Receive Descriptor List Address Register) [BHW]
0x100C
32
read-write
n
0x0
0x0
SRL
Start of Receive List
2
29
read-write
RGSR
RGMII Status Register) [BHW]
0xD8
32
read-only
n
0x0
0x0
LM
Link Mode
0
read-only
LS
Link Status
3
read-only
LSP
Link Speed
1
1
read-only
RIWTR
Receive Interrupt Watchdog Timer Register [BHW]
0x1024
32
read-write
n
0x0
0x0
RIWT
RI Watchdog Timer count
0
7
read-only
RPDR
Receive Poll Demand Register [BHW]
0x1008
32
read-write
n
0x0
0x0
RPD
Receive Poll Demand
0
31
read-write
RWFFR
Remote Wake-up Frame Filter Register [BHW]
0x28
32
read-write
n
0x0
0x0
RWFFR
Remote Wake-up Frame Filter Register
0
31
read-write
RX1024TOMAXOCTETS_GB
Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes exclusive of preamble [BHW]
0x1C0
32
read-only
n
0x0
0x0
RX128TO255OCTETS_GB
Number of good and bad frames received with length between 128 and 255 (inclusive) bytes exclusive of preamble. [BHW]
0x1B4
32
read-only
n
0x0
0x0
RX256TO511OCTETS_GB
Number of good and bad frames received with length between 256 and 511 (inclusive) bytes exclusive of preamble. [BHW]
0x1B8
32
read-only
n
0x0
0x0
RX512TO1023OCTETS_GB
Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes exclusive of preamble. [BHW]
0x1BC
32
read-only
n
0x0
0x0
RX64OCTETS_GB
Number of good and bad frames received with length 64 bytes exclusive of preamble [BHW]
0x1AC
32
read-only
n
0x0
0x0
RX65TO127OCTETS_GB
Number of good and bad frames received with length between 65 and 127 (inclusive) bytes exclusive of preamble. [BHW]
0x1B0
32
read-only
n
0x0
0x0
RXALLIGNMENTERROR
Number of frames received with alignment (dribble) error. Valid only in 10/100 mode [BHW]
0x198
32
read-only
n
0x0
0x0
RXBROADCASTFRAMES_G
Number of good broadcast frames received [BHW]
0x18C
32
read-only
n
0x0
0x0
RXCRCERROR
Number of frames received with CRC error[BHW]
0x194
32
read-only
n
0x0
0x0
RXFIFOOVERFLOW
Number of missed received frames due to FIFO overflow [BHW]
0x1D4
32
read-only
n
0x0
0x0
RXFRAMECOUNT_GB
Number of good and bad frames received [BHW]
0x180
32
read-only
n
0x0
0x0
RXICMP_ERR_FRMS
Number of good IP datagrams whose ICMP payload has a checksum error [BHW]
0x244
32
read-only
n
0x0
0x0
RXICMP_ERR_OCTETS
Number of bytes received in an ICMP segment with checksum errors [BHW]
0x284
32
read-only
n
0x0
0x0
RXICMP_GD_FRMS
Number of good IP datagrams with a good ICMP payload [BHW]
0x240
32
read-only
n
0x0
0x0
RXICMP_GD_OCTETS
Number of bytes received in a good ICMP segment [BHW]
0x280
32
read-only
n
0x0
0x0
RXIPV4_FRAG_FRMS
Number of good IPv4 datagrams with fragmentation [BHW]
0x21C
32
read-only
n
0x0
0x0
RXIPV4_FRAG_OCTETS
Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header's Length field is used to update this counter [BHW]
0x25C
32
read-only
n
0x0
0x0
RXIPV4_GD_FRMS
Number of good IPv4 datagrams received with the TCP/UDP or ICMP payload [BHW]
0x210
32
read-only
n
0x0
0x0
RXIPV4_GD_OCTETS
Number of bytes received in good IPv4 datagrams encapsulating TCP/UDP or ICMP data. (Ethernet header/FCS/pad or IP pad bytes are not included in this counter or in the octet counters listed below). [BHW]
0x250
32
read-only
n
0x0
0x0
RXIPV4_HDRERR_FRMS
Number of IPv4 datagrams received with header errors (checksum/length or version mismatch) [BHW]
0x214
32
read-only
n
0x0
0x0
RXIPV4_HDRERR_OCTETS
Number of bytes received in IPv4 datagrams with header errors (checksum/length version mismatch). The value in the Length field of IPv4 header is used to update this counter [BHW]
0x254
32
read-only
n
0x0
0x0
RXIPV4_NOPAY_FRMS
Number of IPv4 datagram frames received that did not have a TCP/UDP or ICMP payload processed by the Checksum engine [BHW]
0x218
32
read-only
n
0x0
0x0
RXIPV4_NOPAY_OCTETS
Number of bytes received in IPv4 datagrams that did not have a TCP/UDP or ICMP payload. The value in the IPv4 header's Length field is used to update this counter [BHW]
0x258
32
read-only
n
0x0
0x0
RXIPV4_UDSBL_FRMS
Number of good IPv4 datagrams received that had a UDP payload with checksum disabled [BHW]
0x220
32
read-only
n
0x0
0x0
RXIPV4_UDSBL_OCTETS
Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes [BHW]
0x260
32
read-only
n
0x0
0x0
RXIPV6_GD_FRMS
Number of good IPv6 datagrams received with TCP/UDP or ICMP payloads [BHW]
0x224
32
read-only
n
0x0
0x0
RXIPV6_GD_OCTETS
Number of bytes received in good IPv6 datagrams encapsulating TCP/UDP or ICMPv6 data [BHW]
0x264
32
read-only
n
0x0
0x0
RXIPV6_HDRERR_FRMS
Number of IPv6 datagrams received with header errors (length or version mismatch) [BHW]
0x228
32
read-only
n
0x0
0x0
RXIPV6_HDRERR_OCTETS
Number of bytes received in IPv6 datagrams with header errors (length/version mismatch). The value in the IPv6 header's Length field is used to update this counter. [BHW]
0x268
32
read-only
n
0x0
0x0
RXIPV6_NOPAY_FRMS
Number of IPv6 datagram frames received that did not have a TCP/UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers [BHW]
0x22C
32
read-only
n
0x0
0x0
RXIPV6_NOPAY_OCTETS
Number of bytes received in IPv6 datagrams that did not have a TCP/UDP or ICMP payload. The value in the IPv6 header's Length field is used to update this counter [BHW]
0x26C
32
read-only
n
0x0
0x0
RXJABBERERROR
Number of frames received with length greater than 1518 bytes with CRC error [BHW]
0x1A0
32
read-only
n
0x0
0x0
RXLENGTHERROR
Number of frames received with length error (Length type field is not the frame size) for all frames with valid length field [BHW]
0x1C8
32
read-only
n
0x0
0x0
RXMULTICASTFRAMES_G
Number of good multicast frames received [BHW]
0x190
32
read-only
n
0x0
0x0
RXOCTETCOUNT_G
Number of bytes received (exclusive of preamble) only in good frames [BHW]
0x188
32
read-only
n
0x0
0x0
RXOCTETCOUNT_GB
Number of bytes received (exclusive of preamble) in good and bad frames. [BHW]
0x184
32
read-only
n
0x0
0x0
RXOUTOFRANGETYPE
Number of frames received with length/type field not equal to the valid frame size (Greater than 1500) [BHW]
0x1CC
32
read-only
n
0x0
0x0
RXOVERSIZE_G
Number of frames received with length greater than the maxsize without error [BHW]
0x1A8
32
read-only
n
0x0
0x0
RXPAUSEFRAMES
Number of good and valid PAUSE frames received [BHW]
0x1D0
32
read-only
n
0x0
0x0
RXRUNTERROR
Number of frames received with runt (64 bytes and CRC error) error [BHW]
0x19C
32
read-only
n
0x0
0x0
RXTCP_ERR_FRMS
Number of good IP datagrams whose TCP payload has a checksum error [BHW]
0x23C
32
read-only
n
0x0
0x0
RXTCP_ERR_OCTETS
Number of bytes received in a TCP segment with checksum errors [BHW]
0x27C
32
read-only
n
0x0
0x0
RXTCP_GD_FRMS
Number of good IP datagrams with a good TCP payload [BHW]
0x238
32
read-only
n
0x0
0x0
RXTCP_GD_OCTETS
Number of bytes received in a good TCP segment [BHW]
0x278
32
read-only
n
0x0
0x0
RXUDP_ERR_FRMS
Number of good IP datagrams whose UDP payload has a checksum error [BHW]
0x234
32
read-only
n
0x0
0x0
RXUDP_ERR_OCTETS
Number of bytes received in a UDP segment that had checksum errors [BHW]
0x274
32
read-only
n
0x0
0x0
RXUDP_GD_FRMS
Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented [BHW]
0x230
32
read-only
n
0x0
0x0
RXUDP_GD_OCTETS
Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes [BHW]
0x270
32
read-only
n
0x0
0x0
RXUNDERSIZE_G
Number of frames received with length less than 64 bytes without any errors. [BHW]
0x1A4
32
read-only
n
0x0
0x0
RXUNICASTFRAMES_G
Number of good unicast frames received [BHW]
0x1C4
32
read-only
n
0x0
0x0
RXVLANFRAMES_GB
Number of good and bad VLAN frames received [BHW]
0x1D8
32
read-only
n
0x0
0x0
RXWATCHDOGERROR
Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2048 bytes) [BHW]
0x1DC
32
read-only
n
0x0
0x0
SR
Status Register [BHW]
0x1014
32
read-write
n
0x0
0x0
AIS
Abnormal Interrupt Summary
15
read-only
EB
Error Bits
23
2
read-only
ERI
Early Receive Interrupt
14
read-only
ETI
Early Transmit Interrupt
10
read-only
FBI
Fatal Bus Error Interrupt
13
read-only
GLI
GMAC Line interface Interrupt
26
read-only
GLPII
GMAC LPI Interrupt
30
read-only
GMI
GMAC MMC Interrupt
27
read-only
GPI
GMAC PMT Interrupt
28
read-only
NIS
Normal Interrupt Summary
16
read-only
OVF
Receive Overflow
4
read-only
RI
Receive Interrupt
6
read-only
RPS
Receive process Stopped
8
read-only
RS
Receive Process State
17
2
read-only
RU
Receive Buffer Unavailable
7
read-only
RWT
Receive Watchdog Timeout
9
read-only
TI
Transmit Interrupt
0
read-only
TJT
Transmit Jabber Timeout
3
read-only
TPS
Transmit Process Stopped
1
read-only
TS
Transmit Process State
20
2
read-only
TTI
Time-Stamp Trigger Interrupt
29
read-only
TU
Transmit Buffer Unavailable
2
read-only
UNF
Transmit underflow
5
read-only
SSIR
Sub-Second Increment Register [BHW]
0x704
32
read-write
n
0x0
0x0
SSINC
Sub-Second Increment Value
0
7
read-write
STHWSR
System Time - Higher Word Seconds Register [BHW]
0x724
32
read-write
n
0x0
0x0
TSHWR
Time Stamp Higher Word Register
0
15
read-write
STNR
System Time - Nanoseconds Register [BHW]
0x70C
32
read-only
n
0x0
0x0
TSSS
Time Stamp Sub-Seconds
0
30
read-only
STNUR
System Time - Nanoseconds Update Register [BHW]
0x714
32
read-write
n
0x0
0x0
ADDSUB
Add or Subtract Time
31
read-write
TSSS
Time Stamp Sub-Seconds
0
30
read-write
STSR
System Time - Seconds Register [BHW]
0x708
32
read-only
n
0x0
0x0
TSS
Time Stamp Second
0
31
read-only
STSUR
System Time - Seconds Update Register [BHW]
0x710
32
read-write
n
0x0
0x0
TSS
Time Stamp Second
0
31
read-write
TDLAR
Transmit Descriptor List Address Register [BHW]
0x1010
32
read-write
n
0x0
0x0
STL
Start of Transmit List
2
29
read-write
TPDR
Transmit Poll Demand Register) [BHW]
0x1004
32
read-write
n
0x0
0x0
TPD
Transmit Poll Demand
0
31
read-write
TSAR
Time Stamp Addend Register [BHW]
0x718
32
read-write
n
0x0
0x0
TSAR
Time Stamp Addend Register
0
31
read-write
TSCR
Time Stamp Control Register [BHW]
0x700
32
read-write
n
0x0
0x0
ATSFC
Auxiliary Snapshot FIFO Clear
24
read-write
TARU
Addend Register Update
5
read-write
TETSEM
Enable Time Stamp Snapshot for Event Messages
14
read-write
TETSP
Enable Time Stamp Snapshot for PTP over Ethernet frames
11
read-write
TFCU
Time Stamp Fine or Coarse Update
1
read-write
TITE
Time Stamp Interrupt Trigger Enable
4
read-write
TSDB
Time Stamp Digital or Binary rollover control
9
read-write
TSE
Time Stamp Enable
0
read-write
TSEA
Enable Time Stamp for All Frames
8
read-write
TSENMF
Enable MAC address for PTP frame filtering
18
read-write
TSI
Time Stamp Initialize
2
read-write
TSIP4E
Enable Time Stamp Snapshot for IPv4 frames
13
read-write
TSIP6E
Enable Time Stamp Snapshot for IPv6 frames
12
read-write
TSMRM
Enable Snapshot for Messages Relevant to Master
15
read-write
TSPS
SelectPTP packets for taking snapshots
16
1
read-write
TSU
Time Stamp Update
3
read-write
TSV2E
Enable PTP packet snooping for version 2 format
10
read-write
TSR
Time Stamp Status Register [BHW]
0x728
32
read-only
n
0x0
0x0
ATSNS
Auxiliary Time Stamp Number of Snapshots
25
2
read-only
ATSSTM
Auxiliary Time Stamp Snapshot Trigger Missed
24
read-only
ATSTS
Auxiliary Time Stamp Trigger Snapshot
2
read-only
TRGTER
Timestamp Target Time Error
3
read-only
TSSOVF
Time Stamp Seconds Overflow
0
read-only
TSTART
Time Stamp Target Time Reached
1
read-only
TTNR
Target Time Nanoseconds Register [BHW]
0x720
32
read-write
n
0x0
0x0
TSTR
Target Time Stamp Nanoseconds Register
0
30
read-write
TTSR
Target Time Seconds Register [BHW]
0x71C
32
read-write
n
0x0
0x0
TSTR
Target Time Stamp Seconds Register
0
31
read-write
TX1024TOMAXOCTETS_GB
Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes exclusive of preamble and retried frames [BHW]
0x138
32
read-only
n
0x0
0x0
TX128TO255OCTETS_GB
Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried frames [BHW]
0x12C
32
read-only
n
0x0
0x0
TX256TO511OCTETS_GB
Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried frames [BHW]
0x130
32
read-only
n
0x0
0x0
TX512TO1023OCTETS_GB
Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried frames [BHW]
0x134
32
read-only
n
0x0
0x0
TX64OCTETS_GB
Number of good and bad frames transmitted with length of 64 bytes exclusive of preamble and retried frames [BHW]
0x124
32
read-only
n
0x0
0x0
TX65TO127OCTETS_GB
Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried frames [BHW]
0x128
32
read-only
n
0x0
0x0
TXBROADCASTFRAMES_G
Number of good broadcast frames transmitted [BHW]
0x11C
32
read-only
n
0x0
0x0
TXBROADCASTFRAMES_GB
Number of good and bad broadcast frames transmitted [BHW]
0x144
32
read-only
n
0x0
0x0
TXCARRIERERROR
Number of frames aborted due to carrier sense error (no carrier or loss of carrier). [BHW]
0x160
32
read-only
n
0x0
0x0
TXDEFERRED
Number of successfully transmitted frames after a deferral in Half-duplex mode [BHW]
0x154
32
read-only
n
0x0
0x0
TXEXECESSDEF_G
Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times) [BHW]
0x16C
32
read-only
n
0x0
0x0
TXEXESSCOL
Number of frames aborted due to excessive (16) collision errors [BHW]
0x15C
32
read-only
n
0x0
0x0
TXFRAMECOUNT_G
Number of good frames transmitted [BHW]
0x168
32
read-only
n
0x0
0x0
TXFRAMECOUNT_GB
Number of good and bad frames transmitted exclusive of retried frames [BHW]
0x118
32
read-only
n
0x0
0x0
TXLATECOL
Number of frames aborted due to late collision error [BHW]
0x158
32
read-only
n
0x0
0x0
TXMULTICASTFRAMES_G
Number of good multicast frames transmitted[BHW]
0x120
32
read-only
n
0x0
0x0
TXMULTICASTFRAMES_GB
Number of good and bad multicast frames transmitted [BHW]
0x140
32
read-only
n
0x0
0x0
TXMULTICOL_G
Number of successfully transmitted frames after more than a single collision in Half-duplex mode [BHW]
0x150
32
read-only
n
0x0
0x0
TXOCTETCOUNT_G
Number of bytes transmitted (exclusive of preamble) in good frames only [BHW]
0x164
32
read-only
n
0x0
0x0
TXOCTETCOUNT_GB
Number of bytes transmitted (exclusive of preamble and retried bytes) in good and bad frames [BHW]
0x114
32
read-only
n
0x0
0x0
TXPAUSEFRAMES
Number of good PAUSE frames transmitted [BHW]
0x170
32
read-only
n
0x0
0x0
TXSINGLECOL_G
Number of successfully transmitted frames after a single collision in Half-duplex mode [BHW]
0x14C
32
read-only
n
0x0
0x0
TXUNDERFLOWERROR
Number of frames aborted due to frame underflow error [BHW]
0x148
32
read-only
n
0x0
0x0
TXUNICASTFRAMES_GB
Number of good and bad unicast frames transmitted [BHW]
0x13C
32
read-only
n
0x0
0x0
TXVLANFRAMES_G
Number of good VLAN frames transmitted exclusive of retried frames [BHW]
0x174
32
read-only
n
0x0
0x0
VTR
VLAN TAG Register [BHW]
0x1C
32
read-write
n
0x0
0x0
ETV
Enable 12-Bit VLAN Tag Comparison
16
read-write
VL
VLAN Tag Identifier
0
15
read-write
EXBUS
External Bus Interface
EXBUS
0x0
0x0
0x2C
registers
n
0x100
0x14
registers
n
0x200
0x4
registers
n
0x300
0x14
registers
n
EXTBUS_ERR
49
AMODE
Access Mode Register [W]
0x310
32
read-write
n
0x0
0x0
WAEN
WAEN
0
read-write
AREA0
Area Register 0 [W]
0x40
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA1
Area Register 1 [W]
0x44
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA2
Area Register 2 [W]
0x48
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA3
Area Register 3 [W]
0x4C
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA4
Area Register 4 [W]
0x50
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA5
Area Register 5 [W]
0x54
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA6
Area Register 6 [W]
0x58
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
AREA7
Area Register 7 [W]
0x5C
32
read-write
n
0x0
0x0
ADDR
Address
0
7
read-write
MASK
address mask
16
6
read-write
ATIM0
ALE Timing Register 0 [W]
0x60
32
read-write
n
0x0
0x0
ALC
Address Latch Cycle
0
3
read-write
ALES
Address Latch Enable Setup cycle
4
3
read-write
ALEW
Address Latch Enable Width
8
3
read-write
ATIM1
ALE Timing Register 1 [W]
0x64
read-write
n
0x0
0x0
ATIM2
ALE Timing Register 2 [W]
0x68
read-write
n
0x0
0x0
ATIM3
ALE Timing Register 3 [W]
0x6C
read-write
n
0x0
0x0
ATIM4
ALE Timing Register 4 [W]
0x70
read-write
n
0x0
0x0
ATIM5
ALE Timing Register 5 [W]
0x74
read-write
n
0x0
0x0
ATIM6
ALE Timing Register 6 [W]
0x78
read-write
n
0x0
0x0
ATIM7
ALE Timing Register 7 [W]
0x7C
read-write
n
0x0
0x0
DCLKR
Division Clock Register [W]
0x300
32
read-write
n
0x0
0x0
MCLKON
MCLK ON
4
read-write
MDIV
MCLK Division Ratio Setup
0
3
read-write
ESCLR
Error Status Clear Register [W]
0x30C
32
write-only
n
0x0
0x0
WERRCLR
Write Error Clear
0
write-only
EST
Error Status Register [W]
0x304
32
read-only
n
0x0
0x0
WERR
WERR
0
read-only
MEMCERR
Memory Controller Register [W]
0x200
32
read-write
n
0x0
0x0
SDER
SDRAM Error
1
read-write
SDION
SDRAM error Interrupt ON
3
read-write
SFER
SRAM/Flash Error
0
read-write
SFION
SRAM/Flash error Interrupt ON
2
read-write
MODE0
Mode Register 0 [W]
0x0
32
read-write
n
0x0
0x0
ALEINV
set up the polarity of the ALE signal
9
read-write
MOEXEUP
select how to set the MOEX width
13
read-write
MPXCSOF
select a CS assertion from the start of accessing to the end of address output
12
read-write
MPXDOFF
select whether or not the address is output to the data lines in multiplex mode
11
read-write
MPXMODE
select operation bus mode
8
read-write
NAND
NAND Flash memory mode
4
read-write
PAGE
NOR Flash memory page access mode
5
read-write
RBMON
Read Byte Mask ON
2
read-write
RDY
control the external RDY function
6
read-write
SHRTDOUT
select to which idle cycle the write data output is extended
7
read-write
WDTH
specify Data Width
0
1
read-write
WEOFF
disable the write enable signal (MWEX) operation
3
read-write
MODE1
Mode Register 1 [W]
0x4
read-write
n
0x0
0x0
MODE2
Mode Register 2 [W]
0x8
read-write
n
0x0
0x0
MODE3
Mode Register 3 [W]
0xC
read-write
n
0x0
0x0
MODE4
Mode Register 4 [W]
0x10
read-write
n
0x0
0x0
MODE5
Mode Register 5 [W]
0x14
read-write
n
0x0
0x0
MODE6
Mode Register 6 [W]
0x18
read-write
n
0x0
0x0
MODE7
Mode Register 7 [W]
0x1C
read-write
n
0x0
0x0
PWRDWN
Power Down Count Register [W]
0x108
32
read-write
n
0x0
0x0
PDC
Power Down Count
0
15
read-write
REFTIM
Refresh Timer Register [W]
0x104
32
read-write
n
0x0
0x0
NREF
Number of Refresh
16
7
read-write
PREF
Pre-Refresh
24
read-write
REFC
Refresh Count
0
15
read-write
SDCMD
SDRAM Command Register [W]
0x110
32
read-write
n
0x0
0x0
PEND
Pend
31
read-only
SDAD
SDRAM ADress
0
15
read-write
SDCAS
SDRAM CAS
17
read-write
SDCKE
SDRAM CKE
20
read-write
SDCS
SDRAM Chip Select
19
read-write
SDRAS
SDRAM RAS
18
read-write
SDWE
SDRAM Write Enable
16
read-write
SDMODE
SDRAM Mode Register [W]
0x100
32
read-write
n
0x0
0x0
BASEL
Bank Address Select
12
3
read-write
CASEL
Column Address Select
4
1
read-write
MSDCLKOFF
MSDCLK OFF
16
read-write
PDON
Power Down ON
1
read-write
RASEL
Row Address Select
8
3
read-write
ROFF
Refresh OFF
2
read-write
SDON
SDRAM ON
0
read-write
SDTIM
SDRAM Timing Register [W]
0x10C
32
read-write
n
0x0
0x0
BOFF
Buffer readout bit
31
read-write
CL
CAS Latency
0
1
read-write
TDPL
Data-in to Precharge Lead Time
24
1
read-write
TRAS
RAS active time
16
3
read-write
TRC
RAS Cycle time
4
3
read-write
TRCD
RAS-CAS Delay
12
3
read-write
TREFC
Refresh Cycle time
20
3
read-write
TRP
RAS Precharge time
8
3
read-write
TIM0
Timing Register 0 [W]
0x20
32
read-write
n
0x0
0x0
FRADC
First Read Address Cycle
8
3
read-write
RACC
Read Access Cycle
0
3
read-write
RADC
Read Address Setup cycle
4
3
read-write
RIDLC
Read Idle Cycle
12
3
read-write
WACC
Write Access Cycle
16
3
read-write
WADC
Write Address Setup cycle
20
3
read-write
WIDLC
Write Idle Cycle
28
3
read-write
WWEC
Write Enable Cycle
24
3
read-write
TIM1
Timing Register 1 [W]
0x24
read-write
n
0x0
0x0
TIM2
Timing Register 2 [W]
0x28
read-write
n
0x0
0x0
TIM3
Timing Register 3 [W]
0x2C
read-write
n
0x0
0x0
TIM4
Timing Register 4 [W]
0x30
read-write
n
0x0
0x0
TIM5
Timing Register 5 [W]
0x34
read-write
n
0x0
0x0
TIM6
Timing Register 6 [W]
0x38
read-write
n
0x0
0x0
TIM7
Timing Register 7 [W]
0x3C
read-write
n
0x0
0x0
WEAD
Write Error Address Register [W]
0x308
32
read-only
n
0x0
0x0
ADDR
ADDR
0
31
read-only
EXTI
External Interrupt and NMI Control
EXTI
0x0
0x0
0x4
registers
n
0x10
0x4
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x4
registers
n
0x4
0x4
registers
n
0x8
0x4
registers
n
0xC
0x4
registers
n
EXINT0
11
EXINT1
12
EXINT2
13
EXINT3
14
EXINT4
15
EXINT5
16
EXINT6
17
EXINT7
18
EXINT8
51
EXINT9
52
EXINT10
53
EXINT11
54
EXINT12
55
EXINT13
56
EXINT14
57
EXINT15
58
EXINT16_19
92
EXINT20_23
93
EXINT24_27
94
EXINT28_31
95
EICL
External Interrupt Factor Clear Register [BHW]
0x8
32
read-write
n
0x0
0x0
ECL0
External interrupt Ch.0 factor clear bit
0
read-write
ECL1
External interrupt Ch.1 factor clear bit
1
read-write
ECL10
External interrupt Ch.10 factor clear bit
10
read-write
ECL11
External interrupt Ch.11 factor clear bit
11
read-write
ECL12
External interrupt Ch.12 factor clear bit
12
read-write
ECL13
External interrupt Ch.13 factor clear bit
13
read-write
ECL14
External interrupt Ch.14 factor clear bit
14
read-write
ECL15
External interrupt Ch.15 factor clear bit
15
read-write
ECL16
External interrupt Ch.16 factor clear bit
16
read-write
ECL17
External interrupt Ch.17 factor clear bit
17
read-write
ECL18
External interrupt Ch.18 factor clear bit
18
read-write
ECL19
External interrupt Ch.19 factor clear bit
19
read-write
ECL2
External interrupt Ch.2 factor clear bit
2
read-write
ECL20
External interrupt Ch.20 factor clear bit
20
read-write
ECL21
External interrupt Ch.21 factor clear bit
21
read-write
ECL22
External interrupt Ch.22 factor clear bit
22
read-write
ECL23
External interrupt Ch.23 factor clear bit
23
read-write
ECL24
External interrupt Ch.24 factor clear bit
24
read-write
ECL25
External interrupt Ch.25 factor clear bit
25
read-write
ECL26
External interrupt Ch.26 factor clear bit
26
read-write
ECL27
External interrupt Ch.27 factor clear bit
27
read-write
ECL28
External interrupt Ch.28 factor clear bit
28
read-write
ECL29
External interrupt Ch.29 factor clear bit
29
read-write
ECL3
External interrupt Ch.3 factor clear bit
3
read-write
ECL30
External interrupt Ch.30 factor clear bit
30
read-write
ECL31
External interrupt Ch.31 factor clear bit
31
read-write
ECL4
External interrupt Ch.4 factor clear bit
4
read-write
ECL5
External interrupt Ch.5 factor clear bit
5
read-write
ECL6
External interrupt Ch.6 factor clear bit
6
read-write
ECL7
External interrupt Ch.7 factor clear bit
7
read-write
ECL8
External interrupt Ch.8 factor clear bit
8
read-write
ECL9
External interrupt Ch.9 factor clear bit
9
read-write
EIRR
External Interrupt Factor Register [BHW]
0x4
32
read-only
n
0x0
0x0
ER0
External interrupt Ch.0 request detection bit
0
read-only
ER1
External interrupt Ch.1 request detection bit
1
read-only
ER10
External interrupt Ch.10 request detection bit
10
read-only
ER11
External interrupt Ch.11 request detection bit
11
read-only
ER12
External interrupt Ch.12 request detection bit
12
read-only
ER13
External interrupt Ch.13 request detection bit
13
read-only
ER14
External interrupt Ch.14 request detection bit
14
read-only
ER15
External interrupt Ch.15 request detection bit
15
read-only
ER16
External interrupt Ch.16 request detection bit
16
read-only
ER17
External interrupt Ch.17 request detection bit
17
read-only
ER18
External interrupt Ch.18 request detection bit
18
read-only
ER19
External interrupt Ch.19 request detection bit
19
read-only
ER2
External interrupt Ch.2 request detection bit
2
read-only
ER20
External interrupt Ch.20 request detection bit
20
read-only
ER21
External interrupt Ch.21 request detection bit
21
read-only
ER22
External interrupt Ch.22 request detection bit
22
read-only
ER23
External interrupt Ch.23 request detection bit
23
read-only
ER24
External interrupt Ch.24 request detection bit
24
read-only
ER25
External interrupt Ch.25 request detection bit
25
read-only
ER26
External interrupt Ch.26 request detection bit
26
read-only
ER27
External interrupt Ch.27 request detection bit
27
read-only
ER28
External interrupt Ch.28 request detection bit
28
read-only
ER29
External interrupt Ch.29 request detection bit
29
read-only
ER3
External interrupt Ch.3 request detection bit
3
read-only
ER30
External interrupt Ch.30 request detection bit
30
read-only
ER31
External interrupt Ch.31 request detection bit
31
read-only
ER4
External interrupt Ch.4 request detection bit
4
read-only
ER5
External interrupt Ch.5 request detection bit
5
read-only
ER6
External interrupt Ch.6 request detection bit
6
read-only
ER7
External interrupt Ch.7 request detection bit
7
read-only
ER8
External interrupt Ch.8 request detection bit
8
read-only
ER9
External interrupt Ch.9 request detection bit
9
read-only
ELVR
External Interrupt Factor Level Register [BHW]
0xC
32
read-write
n
0x0
0x0
LA0
External interrupt request detection level selection bit for INT0
0
read-write
LA1
External interrupt request detection level selection bit for INT1
2
read-write
LA10
External interrupt request detection level selection bit for INT10
20
read-write
LA11
External interrupt request detection level selection bit for INT11
22
read-write
LA12
External interrupt request detection level selection bit for INT12
24
read-write
LA13
External interrupt request detection level selection bit for INT13
26
read-write
LA14
External interrupt request detection level selection bit for INT14
28
read-write
LA15
External interrupt request detection level selection bit for INT15
30
read-write
LA2
External interrupt request detection level selection bit for INT2
4
read-write
LA3
External interrupt request detection level selection bit for INT3
6
read-write
LA4
External interrupt request detection level selection bit for INT4
8
read-write
LA5
External interrupt request detection level selection bit for INT5
10
read-write
LA6
External interrupt request detection level selection bit for INT6
12
read-write
LA7
External interrupt request detection level selection bit for INT7
14
read-write
LA8
External interrupt request detection level selection bit for INT8
16
read-write
LA9
External interrupt request detection level selection bit for INT9
18
read-write
LB0
External interrupt request detection level selection bit for INT0
1
read-write
LB1
External interrupt request detection level selection bit for INT1
3
read-write
LB10
External interrupt request detection level selection bit for INT10
21
read-write
LB11
External interrupt request detection level selection bit for INT11
23
read-write
LB12
External interrupt request detection level selection bit for INT12
25
read-write
LB13
External interrupt request detection level selection bit for INT13
27
read-write
LB14
External interrupt request detection level selection bit for INT14
29
read-write
LB15
External interrupt request detection level selection bit for INT15
31
read-write
LB2
External interrupt request detection level selection bit for INT2
5
read-write
LB3
External interrupt request detection level selection bit for INT3
7
read-write
LB4
External interrupt request detection level selection bit for INT4
9
read-write
LB5
External interrupt request detection level selection bit for INT5
11
read-write
LB6
External interrupt request detection level selection bit for INT6
13
read-write
LB7
External interrupt request detection level selection bit for INT7
15
read-write
LB8
External interrupt request detection level selection bit for INT8
17
read-write
LB9
External interrupt request detection level selection bit for INT9
19
read-write
ELVR1
External Interrupt Factor Level Register 1 [BHW]
0x10
32
read-write
n
0x0
0x0
LA16
External interrupt request detection level selection bit for INT16
0
read-write
LA17
External interrupt request detection level selection bit for INT17
2
read-write
LA18
External interrupt request detection level selection bit for INT18
4
read-write
LA19
External interrupt request detection level selection bit for INT19
6
read-write
LA20
External interrupt request detection level selection bit for INT20
8
read-write
LA21
External interrupt request detection level selection bit for INT21
10
read-write
LA22
External interrupt request detection level selection bit for INT22
12
read-write
LA23
External interrupt request detection level selection bit for INT23
14
read-write
LA24
External interrupt request detection level selection bit for INT24
16
read-write
LA25
External interrupt request detection level selection bit for INT25
18
read-write
LA26
External interrupt request detection level selection bit for INT26
20
read-write
LA27
External interrupt request detection level selection bit for INT27
22
read-write
LA28
External interrupt request detection level selection bit for INT28
24
read-write
LA29
External interrupt request detection level selection bit for INT29
26
read-write
LA30
External interrupt request detection level selection bit for INT30
28
read-write
LA31
External interrupt request detection level selection bit for INT31
30
read-write
LB16
External interrupt request detection level selection bit for INT16
1
read-write
LB17
External interrupt request detection level selection bit for INT17
3
read-write
LB18
External interrupt request detection level selection bit for INT18
5
read-write
LB19
External interrupt request detection level selection bit for INT19
7
read-write
LB20
External interrupt request detection level selection bit for INT20
9
read-write
LB21
External interrupt request detection level selection bit for INT21
11
read-write
LB22
External interrupt request detection level selection bit for INT22
13
read-write
LB23
External interrupt request detection level selection bit for INT23
15
read-write
LB24
External interrupt request detection level selection bit for INT24
17
read-write
LB25
External interrupt request detection level selection bit for INT25
19
read-write
LB26
External interrupt request detection level selection bit for INT26
21
read-write
LB27
External interrupt request detection level selection bit for INT27
23
read-write
LB28
External interrupt request detection level selection bit for INT28
25
read-write
LB29
External interrupt request detection level selection bit for INT29
27
read-write
LB30
External interrupt request detection level selection bit for INT30
29
read-write
LB31
External interrupt request detection level selection bit for INT31
31
read-write
ELVR2
External Interrupt Factor Level Register 2 [BHW]
0x1C
32
read-write
n
0x0
0x0
LC0
External interrupt request detection level selection bit for INT0
0
read-write
LC1
External interrupt request detection level selection bit for INT1
1
read-write
LC10
External interrupt request detection level selection bit for INT10
10
read-write
LC11
External interrupt request detection level selection bit for INT11
11
read-write
LC12
External interrupt request detection level selection bit for INT12
12
read-write
LC13
External interrupt request detection level selection bit for INT13
13
read-write
LC14
External interrupt request detection level selection bit for INT14
14
read-write
LC15
External interrupt request detection level selection bit for INT15
15
read-write
LC16
External interrupt request detection level selection bit for INT16
16
read-write
LC17
External interrupt request detection level selection bit for INT17
17
read-write
LC18
External interrupt request detection level selection bit for INT18
18
read-write
LC19
External interrupt request detection level selection bit for INT19
19
read-write
LC2
External interrupt request detection level selection bit for INT2
2
read-write
LC20
External interrupt request detection level selection bit for INT20
20
read-write
LC21
External interrupt request detection level selection bit for INT21
21
read-write
LC22
External interrupt request detection level selection bit for INT22
22
read-write
LC23
External interrupt request detection level selection bit for INT23
23
read-write
LC24
External interrupt request detection level selection bit for INT24
24
read-write
LC25
External interrupt request detection level selection bit for INT25
25
read-write
LC26
External interrupt request detection level selection bit for INT26
26
read-write
LC27
External interrupt request detection level selection bit for INT27
27
read-write
LC28
External interrupt request detection level selection bit for INT28
28
read-write
LC29
External interrupt request detection level selection bit for INT29
29
read-write
LC3
External interrupt request detection level selection bit for INT3
3
read-write
LC30
External interrupt request detection level selection bit for INT30
30
read-write
LC31
External interrupt request detection level selection bit for INT31
31
read-write
LC4
External interrupt request detection level selection bit for INT4
4
read-write
LC5
External interrupt request detection level selection bit for INT5
5
read-write
LC6
External interrupt request detection level selection bit for INT6
6
read-write
LC7
External interrupt request detection level selection bit for INT7
7
read-write
LC8
External interrupt request detection level selection bit for INT8
8
read-write
LC9
External interrupt request detection level selection bit for INT9
9
read-write
ENIR
External Interrupt Enable Register [BHW]
0x0
32
read-write
n
0x0
0x0
EN0
External interrupt Ch.0 enable bit
0
read-write
EN1
External interrupt Ch.1 enable bit
1
read-write
EN10
External interrupt Ch.10 enable bit
10
read-write
EN11
External interrupt Ch.11 enable bit
11
read-write
EN12
External interrupt Ch.12 enable bit
12
read-write
EN13
External interrupt Ch.13 enable bit
13
read-write
EN14
External interrupt Ch.14 enable bit
14
read-write
EN15
External interrupt Ch.15 enable bit
15
read-write
EN16
External interrupt Ch.16 enable bit
16
read-write
EN17
External interrupt Ch.17 enable bit
17
read-write
EN18
External interrupt Ch.18 enable bit
18
read-write
EN19
External interrupt Ch.19 enable bit
19
read-write
EN2
External interrupt Ch.2 enable bit
2
read-write
EN20
External interrupt Ch.20 enable bit
20
read-write
EN21
External interrupt Ch.21 enable bit
21
read-write
EN22
External interrupt Ch.22 enable bit
22
read-write
EN23
External interrupt Ch.23 enable bit
23
read-write
EN24
External interrupt Ch.24 enable bit
24
read-write
EN25
External interrupt Ch.25 enable bit
25
read-write
EN26
External interrupt Ch.26 enable bit
26
read-write
EN27
External interrupt Ch.27 enable bit
27
read-write
EN28
External interrupt Ch.28 enable bit
28
read-write
EN29
External interrupt Ch.29 enable bit
29
read-write
EN3
External interrupt Ch.3 enable bit
3
read-write
EN30
External interrupt Ch.30 enable bit
30
read-write
EN31
External interrupt Ch.31 enable bit
31
read-write
EN4
External interrupt Ch.4 enable bit
4
read-write
EN5
External interrupt Ch.5 enable bit
5
read-write
EN6
External interrupt Ch.6 enable bit
6
read-write
EN7
External interrupt Ch.7 enable bit
7
read-write
EN8
External interrupt Ch.8 enable bit
8
read-write
EN9
External interrupt Ch.9 enable bit
9
read-write
NMICL
Non Maskable Interrupt Factor Clear Register [BHW]
0x18
16
read-write
n
0x0
0x0
NCL
NMI interrupt factor clear bit
0
read-write
NMIRR
Non Maskable Interrupt Factor Register [BHW]
0x14
16
read-only
n
0x0
0x0
NR
NMI interrupt request detection bit
0
read-only
FLASH_IF
Flash Memory
FLASH_IF
0x0
0x0
0xC
registers
n
0x10
0x8
registers
n
0x100
0x4
registers
n
0x110
0x10
registers
n
0x20
0xC
registers
n
FLASHIF
119
CRTRMM
CR Trimming Data Mirror Register [BHW]
0x100
32
read-only
n
0x0
0x0
TRMM
CR Trimming Data Mirror
0
9
read-only
TTRMM
Temperature CR Trimming Data Mirror
16
4
read-only
FASZR
Flash Access Size Register [BHW]
0x0
32
read-write
n
0x0
0x0
ASZ
Access Size
0
1
read-write
FBFCR
Flash Buffer Control Register [BHW]
0x14
32
read-write
n
0x0
0x0
BE
Buffer Enable
0
read-write
BS
Buffer Status
1
read-only
FGPDM1
Flash General Purpose Data Mirror Register1 [BHW]
0x110
32
read-only
n
0x0
0x0
GPD1
General Purpose Data1
0
31
read-only
FGPDM2
Flash General Purpose Data Mirror Register2 [BHW]
0x114
32
read-only
n
0x0
0x0
GPD2
General Purpose Data2
0
31
read-only
FGPDM3
Flash General Purpose Data Mirror Register3 [BHW]
0x118
32
read-only
n
0x0
0x0
GPD3
General Purpose Data3
0
31
read-only
FGPDM4
Flash General Purpose Data Mirror Register4 [BHW]
0x11C
32
read-only
n
0x0
0x0
GPD4
General Purpose Data4
0
31
read-only
FICLR
Flash Interrupt Clear Register [BHW]
0x28
32
read-write
n
0x0
0x0
ERRIC
Flash ECC Error Interrupt Clear
2
read-write
HNGIC
Flash HANG Interrupt Clear
1
read-write
RDYIC
Flash RDY Interrupt Clear
0
read-write
FICR
Flash Interrupt Control Register [BHW]
0x20
32
read-write
n
0x0
0x0
ERRIE
Flash ECC Error Interrupt Enable
2
read-write
HNGIE
Flash HANG Interrupt Enable
1
read-write
RDYIE
Flash RDY Interrupt Enable
0
read-write
FISR
Flash Interrupt Status Register [BHW]
0x24
32
read-only
n
0x0
0x0
ERRIF
Flash ECC Error Interrupt Flag
2
read-only
HNGIF
Flash HANG Interrupt Flag
1
read-only
RDYIF
Flash RDY Interrupt Flag
0
read-only
FRWTR
Flash Read Wait Register [BHW]
0x4
32
read-write
n
0x0
0x0
RWT
Read Wait Cycle
0
1
read-write
FSTR
Flash Status Register [BHW]
0x8
32
read-write
n
0x0
0x0
ERR
Flash ECC Error
2
read-write
HNG
Flash Hang
1
read-only
RDY
Flash Rdy
0
read-only
FSYNDN
Flash Sync Down Register [BHW]
0x10
32
read-write
n
0x0
0x0
SD
Sync Down
0
2
read-write
GPIO
GPIO
GPIO
0x0
0x0
0x40
registers
n
0x100
0x20
registers
n
0x124
0x1C
registers
n
0x200
0x40
registers
n
0x300
0x40
registers
n
0x400
0x40
registers
n
0x500
0x4
registers
n
0x580
0x4
registers
n
0x600
0x6C
registers
n
0x684
0x4
registers
n
0x68C
0x4
registers
n
0x700
0x80
registers
n
ADE
Analog Input Setting Register [BHW]
0x500
32
read-write
n
0x0
0x0
AN00
Analog Input Ch.0 Setting Register
0
read-write
AN01
Analog Input Ch.1 Setting Register
1
read-write
AN02
Analog Input Ch.2 Setting Register
2
read-write
AN03
Analog Input Ch.3 Setting Register
3
read-write
AN04
Analog Input Ch.4 Setting Register
4
read-write
AN05
Analog Input Ch.5 Setting Register
5
read-write
AN06
Analog Input Ch.6 Setting Register
6
read-write
AN07
Analog Input Ch.7 Setting Register
7
read-write
AN08
Analog Input Ch.8 Setting Register
8
read-write
AN09
Analog Input Ch.9 Setting Register
9
read-write
AN10
Analog Input Ch.10 Setting Register
10
read-write
AN11
Analog Input Ch.11 Setting Register
11
read-write
AN12
Analog Input Ch.12 Setting Register
12
read-write
AN13
Analog Input Ch.13 Setting Register
13
read-write
AN14
Analog Input Ch.14 Setting Register
14
read-write
AN15
Analog Input Ch.15 Setting Register
15
read-write
AN16
Analog Input Ch.16 Setting Register
16
read-write
AN17
Analog Input Ch.17 Setting Register
17
read-write
AN18
Analog Input Ch.18 Setting Register
18
read-write
AN19
Analog Input Ch.19 Setting Register
19
read-write
AN20
Analog Input Ch.20 Setting Register
20
read-write
AN21
Analog Input Ch.21 Setting Register
21
read-write
AN22
Analog Input Ch.22 Setting Register
22
read-write
AN23
Analog Input Ch.23 Setting Register
23
read-write
AN24
Analog Input Ch.24 Setting Register
24
read-write
AN25
Analog Input Ch.25 Setting Register
25
read-write
AN26
Analog Input Ch.26 Setting Register
26
read-write
AN27
Analog Input Ch.27 Setting Register
27
read-write
AN28
Analog Input Ch.28 Setting Register
28
read-write
AN29
Analog Input Ch.29 Setting Register
29
read-write
AN30
Analog Input Ch.30 Setting Register
30
read-write
AN31
Analog Input Ch.31 Setting Register
31
read-write
DDR0
Port input/output Direction Setting Register 0 [BHW]
0x200
32
read-write
n
0x0
0x0
P0
Bit0 of DDR0
0
read-write
P1
Bit1 of DDR0
1
read-write
P2
Bit2 of DDR0
2
read-write
P3
Bit3 of DDR0
3
read-write
P4
Bit4 of DDR0
4
read-write
P8
Bit8 of DDR0
8
read-write
P9
Bit9 of DDR0
9
read-write
PA
Bit10 of DDR0
10
read-write
DDR1
Port input/output Direction Setting Register 1 [BHW]
0x204
32
read-write
n
0x0
0x0
P0
Bit0 of DDR1
0
read-write
P1
Bit1 of DDR1
1
read-write
P2
Bit2 of DDR1
2
read-write
P3
Bit3 of DDR1
3
read-write
P4
Bit4 of DDR1
4
read-write
P5
Bit5 of DDR1
5
read-write
P6
Bit6 of DDR1
6
read-write
P7
Bit7 of DDR1
7
read-write
P8
Bit8 of DDR1
8
read-write
P9
Bit9 of DDR1
9
read-write
PA
Bit10 of DDR1
10
read-write
PB
Bit11 of DDR1
11
read-write
PC
Bit12 of DDR1
12
read-write
PD
Bit13 of DDR1
13
read-write
PE
Bit14 of DDR1
14
read-write
PF
Bit15 of DDR1
15
read-write
DDR2
Port input/output Direction Setting Register 2 [BHW]
0x208
32
read-write
n
0x0
0x0
P0
Bit0 of DDR2
0
read-write
P1
Bit1 of DDR2
1
read-write
P2
Bit2 of DDR2
2
read-write
P3
Bit3 of DDR2
3
read-write
P4
Bit4 of DDR2
4
read-write
P5
Bit5 of DDR2
5
read-write
P6
Bit6 of DDR2
6
read-write
P7
Bit7 of DDR2
7
read-write
P8
Bit8 of DDR2
8
read-write
P9
Bit9 of DDR2
9
read-write
PA
Bit10 of DDR2
10
read-write
DDR3
Port input/output Direction Setting Register 3 [BHW]
0x20C
32
read-write
n
0x0
0x0
P0
Bit0 of DDR3
0
read-write
P1
Bit1 of DDR3
1
read-write
P2
Bit2 of DDR3
2
read-write
P3
Bit3 of DDR3
3
read-write
P4
Bit4 of DDR3
4
read-write
P5
Bit5 of DDR3
5
read-write
P6
Bit6 of DDR3
6
read-write
P7
Bit7 of DDR3
7
read-write
P8
Bit8 of DDR3
8
read-write
P9
Bit9 of DDR3
9
read-write
PA
Bit10 of DDR3
10
read-write
PB
Bit11 of DDR3
11
read-write
PC
Bit12 of DDR3
12
read-write
PD
Bit13 of DDR3
13
read-write
PE
Bit14 of DDR3
14
read-write
DDR4
Port input/output Direction Setting Register 4 [BHW]
0x210
32
read-write
n
0x0
0x0
P0
Bit0 of DDR4
0
read-write
P1
Bit1 of DDR4
1
read-write
P2
Bit2 of DDR4
2
read-write
P3
Bit3 of DDR4
3
read-write
P4
Bit4 of DDR4
4
read-write
P5
Bit5 of DDR4
5
read-write
P6
Bit6 of DDR4
6
read-write
P7
Bit7 of DDR4
7
read-write
P8
Bit8 of DDR4
8
read-write
P9
Bit9 of DDR4
9
read-write
PA
Bit10 of DDR4
10
read-write
PB
Bit11 of DDR4
11
read-write
PC
Bit12 of DDR4
12
read-write
PD
Bit13 of DDR4
13
read-write
PE
Bit14 of DDR4
14
read-write
DDR5
Port input/output Direction Setting Register 5 [BHW]
0x214
32
read-write
n
0x0
0x0
P0
Bit0 of DDR5
0
read-write
P1
Bit1 of DDR5
1
read-write
P2
Bit2 of DDR5
2
read-write
PD
Bit13 of DDR5
13
read-write
PE
Bit14 of DDR5
14
read-write
PF
Bit15 of DDR5
15
read-write
DDR6
Port input/output Direction Setting Register 6 [BHW]
0x218
32
read-write
n
0x0
0x0
P0
Bit0 of DDR6
0
read-write
P1
Bit1 of DDR6
1
read-write
P2
Bit2 of DDR6
2
read-write
P3
Bit3 of DDR6
3
read-write
P4
Bit4 of DDR6
4
read-write
P5
Bit5 of DDR6
5
read-write
PE
Bit14 of DDR6
14
read-write
DDR7
Port input/output Direction Setting Register 7 [BHW]
0x21C
32
read-write
n
0x0
0x0
P0
Bit0 of DDR7
0
read-write
P1
Bit1 of DDR7
1
read-write
P2
Bit2 of DDR7
2
read-write
P3
Bit3 of DDR7
3
read-write
P4
Bit4 of DDR7
4
read-write
P5
Bit5 of DDR7
5
read-write
P6
Bit6 of DDR7
6
read-write
P7
Bit7 of DDR7
7
read-write
P8
Bit8 of DDR7
8
read-write
P9
Bit9 of DDR7
9
read-write
PA
Bit10 of DDR7
10
read-write
DDR8
Port input/output Direction Setting Register 8 [BHW]
0x220
32
read-write
n
0x0
0x0
P0
Bit0 of DDR8
0
read-write
P1
Bit1 of DDR8
1
read-write
P2
Bit2 of DDR8
2
read-write
P3
Bit3 of DDR8
3
read-write
DDR9
Port input/output Direction Setting Register 9 [BHW]
0x224
32
read-write
n
0x0
0x0
P0
Bit0 of DDR9
0
read-write
P1
Bit1 of DDR9
1
read-write
P2
Bit2 of DDR9
2
read-write
P3
Bit3 of DDR9
3
read-write
P4
Bit4 of DDR9
4
read-write
P5
Bit5 of DDR9
5
read-write
DDRA
Port input/output Direction Setting Register A [BHW]
0x228
32
read-write
n
0x0
0x0
P0
Bit0 of DDRA
0
read-write
P1
Bit1 of DDRA
1
read-write
P2
Bit2 of DDRA
2
read-write
P3
Bit3 of DDRA
3
read-write
P4
Bit4 of DDRA
4
read-write
P5
Bit5 of DDRA
5
read-write
P6
Bit6 of DDRA
6
read-write
P7
Bit7 of DDRA
7
read-write
P8
Bit8 of DDRA
8
read-write
P9
Bit9 of DDRA
9
read-write
PA
Bit10 of DDRA
10
read-write
PB
Bit11 of DDRA
11
read-write
PC
Bit12 of DDRA
12
read-write
PD
Bit13 of DDRA
13
read-write
PE
Bit14 of DDRA
14
read-write
PF
Bit15 of DDRA
15
read-write
DDRB
Port input/output Direction Setting Register B [BHW]
0x22C
32
read-write
n
0x0
0x0
P0
Bit0 of DDRB
0
read-write
P1
Bit1 of DDRB
1
read-write
P2
Bit2 of DDRB
2
read-write
P3
Bit3 of DDRB
3
read-write
P4
Bit4 of DDRB
4
read-write
P5
Bit5 of DDRB
5
read-write
P6
Bit6 of DDRB
6
read-write
P7
Bit7 of DDRB
7
read-write
DDRC
Port input/output Direction Setting Register C [BHW]
0x230
32
read-write
n
0x0
0x0
P0
Bit0 of DDRC
0
read-write
P1
Bit1 of DDRC
1
read-write
P2
Bit2 of DDRC
2
read-write
P3
Bit3 of DDRC
3
read-write
P4
Bit4 of DDRC
4
read-write
P5
Bit5 of DDRC
5
read-write
P6
Bit6 of DDRC
6
read-write
P7
Bit7 of DDRC
7
read-write
P8
Bit8 of DDRC
8
read-write
P9
Bit9 of DDRC
9
read-write
PA
Bit10 of DDRC
10
read-write
PB
Bit11 of DDRC
11
read-write
PC
Bit12 of DDRC
12
read-write
PD
Bit13 of DDRC
13
read-write
PE
Bit14 of DDRC
14
read-write
PF
Bit15 of DDRC
15
read-write
DDRD
Port input/output Direction Setting Register D [BHW]
0x234
32
read-write
n
0x0
0x0
P0
Bit0 of DDRD
0
read-write
P1
Bit1 of DDRD
1
read-write
P2
Bit2 of DDRD
2
read-write
DDRE
Port input/output Direction Setting Register E [BHW]
0x238
32
read-write
n
0x0
0x0
P0
Bit0 of DDRE
0
read-write
P2
Bit2 of DDRE
2
read-write
P3
Bit3 of DDRE
3
read-write
DDRF
Port input/output Direction Setting Register F [BHW]
0x23C
32
read-write
n
0x0
0x0
P0
Bit0 of DDRF
0
read-write
P1
Bit1 of DDRF
1
read-write
P2
Bit2 of DDRF
2
read-write
P3
Bit3 of DDRF
3
read-write
P4
Bit4 of DDRF
4
read-write
P5
Bit5 of DDRF
5
read-write
P6
Bit6 of DDRF
6
read-write
P7
Bit7 of DDRF
7
read-write
EPFR00
Extended Pin Function Setting Register 00 [BHW]
0x600
32
read-write
n
0x0
0x0
CROUTE
Internal high-speed CR Oscillation Output Function Select bit
1
1
read-write
JTAGEN0B
JTAG Function Select bit 0
16
read-write
JTAGEN1S
JTAG Function Select bit 1
17
read-write
NMIS
NMIX Function Select bit
0
read-write
RTCCOE
RTC clock output select bit
4
1
read-write
SUBOUTE
Sub clock divide output function select bit
6
1
read-write
TRC0E
TRACED Function Select bit 0
24
read-write
TRC1E
TRACED Function Select bit 1
25
read-write
TRC2E
TRACED Function Select bit 2
26
read-write
TRC3E
TRACED Function Select bit 3
27
read-write
USBP0E
USB ch.0 Function Select bit 1
9
read-write
USBP1E
USB ch.1 Function Select bit 1
13
read-write
EPFR01
Extended Pin Function Setting Register 01 [BHW]
0x604
32
read-write
n
0x0
0x0
DTTI0C
DTTIX0 Function Select bit
12
read-write
DTTI0S
DTTIX0 Input Select bits
16
1
read-write
FRCK0S
FRCK0 Input Select bits
18
1
read-write
IC00S
IC00 Input Select bits
20
2
read-write
IC01S
IC01 Input Select bits
23
2
read-write
IC02S
IC02 Input Select bits
26
2
read-write
IC03S
IC03 Input Select bits
29
2
read-write
RTO00E
RTO00 Output Select bits
0
1
read-write
RTO01E
RTO01 Output Select bits
2
1
read-write
RTO02E
RTO02 Output Select bits
4
1
read-write
RTO03E
RTO03 Output Select bits
6
1
read-write
RTO04E
RTO04 Output Select bits
8
1
read-write
RTO05E
RTO05 Output Select bits
10
1
read-write
EPFR02
Extended Pin Function Setting Register 02 [BHW]
0x608
32
read-write
n
0x0
0x0
DTTI1C
DTTIX1 Function Select bit
12
read-write
DTTI1S
DTTIX1 Input Select bits
16
1
read-write
FRCK1S
FRCK1 Input Select bits
18
1
read-write
IC10S
IC13 Input Select bits
20
2
read-write
IC11S
IC13 Input Select bits
23
2
read-write
IC12S
IC13 Input Select bits
26
2
read-write
IC13S
IC13 Input Select bits
29
2
read-write
RTO10E
RTO10 Output Select bits
0
1
read-write
RTO11E
RTO11 Output Select bits
2
1
read-write
RTO12E
RTO12 Output Select bits
4
1
read-write
RTO13E
RTO13 Output Select bits
6
1
read-write
RTO14E
RTO14 Output Select bits
8
1
read-write
RTO15E
RTO15 Output Select bits
10
1
read-write
EPFR03
Extended Pin Function Setting Register 03 [BHW]
0x60C
32
read-write
n
0x0
0x0
DTTI2C
DTTIX2 Function Select bit
12
read-write
DTTI2S
DTTIX2 Input Select bits
16
1
read-write
FRCK2S
FRCK2 Input Select bits
18
1
read-write
IC20S
IC23 Input Select bits
20
2
read-write
IC21S
IC23 Input Select bits
23
2
read-write
IC22S
IC23 Input Select bits
26
2
read-write
IC23S
IC23 Input Select bits
29
2
read-write
RTO20E
RTO20 Output Select bits
0
1
read-write
RTO21E
RTO21 Output Select bits
2
1
read-write
RTO22E
RTO22 Output Select bits
4
1
read-write
RTO23E
RTO23 Output Select bits
6
1
read-write
RTO24E
RTO24 Output Select bits
8
1
read-write
RTO25E
RTO25 Output Select bits
10
1
read-write
EPFR04
Extended Pin Function Setting Register 04 [BHW]
0x610
32
read-write
n
0x0
0x0
TIOA0E
TIOA0 Output Select bits
2
1
read-write
TIOA1E
TIOA1 Output Select bits
10
1
read-write
TIOA1S
TIOA1 Input Select bits
8
1
read-write
TIOA2E
TIOA2 Output Select bits
18
1
read-write
TIOA3E
TIOA3 Output Select bits
26
1
read-write
TIOA3S
TIOA3 Input Select bits
24
1
read-write
TIOB0S
TIOB0 Input Select bits
4
2
read-write
TIOB1S
TIOB1 Input Select bits
12
1
read-write
TIOB2S
TIOB2 Input Select bits
20
1
read-write
TIOB3S
TIOB3 Input Select bits
28
1
read-write
EPFR05
Extended Pin Function Setting Register 05 [BHW]
0x614
32
read-write
n
0x0
0x0
TIOA4E
TIOA4 Output Select bits
2
1
read-write
TIOA5E
TIOA5 Output Select bits
10
1
read-write
TIOA5S
TIOA5 Input Select bits
8
1
read-write
TIOA6E
TIOA6 Output Select bits
18
1
read-write
TIOA7E
TIOA7 Output Select bits
26
1
read-write
TIOA7S
TIOA7 Input Select bits
24
1
read-write
TIOB4S
TIOB4 Input Select bits
4
1
read-write
TIOB5S
TIOB5 Input Select bits
12
1
read-write
TIOB6S
TIOB6 Input Select bits
20
1
read-write
TIOB7S
TIOB7 Input Select bits
28
1
read-write
EPFR06
Extended Pin Function Setting Register 06 [BHW]
0x618
32
read-write
n
0x0
0x0
EINT00S
External Interrupt 00 Input Select bits
0
1
read-write
EINT01S
External Interrupt 01 Input Select bits
2
1
read-write
EINT02S
External Interrupt 02 Input Select bits
4
1
read-write
EINT03S
External Interrupt 03 Input Select bits
6
1
read-write
EINT04S
External Interrupt 04 Input Select bits
8
1
read-write
EINT05S
External Interrupt 05 Input Select bits
10
1
read-write
EINT06S
External Interrupt 06 Input Select bits
12
1
read-write
EINT07S
External Interrupt 07 Input Select bits
14
1
read-write
EINT08S
External Interrupt 08 Input Select bits
16
1
read-write
EINT09S
External Interrupt 09 Input Select bits
18
1
read-write
EINT10S
External Interrupt 10 Input Select bits
20
1
read-write
EINT11S
External Interrupt 11 Input Select bits
22
1
read-write
EINT12S
External Interrupt 12 Input Select bits
24
1
read-write
EINT13S
External Interrupt 13 Input Select bits
26
1
read-write
EINT14S
External Interrupt 14 Input Select bits
28
1
read-write
EINT15S
External Interrupt 15 Input Select bits
30
1
read-write
EPFR07
Extended Pin Function Setting Register 07 [BHW]
0x61C
32
read-write
n
0x0
0x0
SCK0B
SCK0 Input/Output Select bits
8
1
read-write
SCK1B
SCK1 Input/Output Select bits
14
1
read-write
SCK2B
SCK2 Input/Output Select bits
20
1
read-write
SCK3B
SCK3 Input/Output Select bits
26
1
read-write
SIN0S
SIN0 Input Select bits
4
1
read-write
SIN1S
SIN1 Input Select bits
10
1
read-write
SIN2S
SIN2 Input Select bits
16
1
read-write
SIN3S
SIN3 Input Select bits
22
1
read-write
SOT0B
SOT0 Input/Output Select bits
6
1
read-write
SOT1B
SOT1 Input/Output Select bits
12
1
read-write
SOT2B
SOT2 Input/Output Select bits
18
1
read-write
SOT3B
SOT3 Input/Output Select bits
24
1
read-write
EPFR08
Extended Pin Function Setting Register 08 [BHW]
0x620
32
read-write
n
0x0
0x0
CTS4S
CTS4 Input/Output Select bits
2
1
read-write
CTS5S
CTS5 Input/Output Select bits
30
1
read-write
RTS4E
RTS4 Input/Output Select bits
0
1
read-write
RTS5E
RTS5 Input/Output Select bits
28
1
read-write
SCK4B
SCK4 Input/Output Select bits
8
1
read-write
SCK5B
SCK5 Input/Output Select bits
14
1
read-write
SCK6B
SCK6 Input/Output Select bits
20
1
read-write
SCK7B
SCK7 Input/Output Select bits
26
1
read-write
SIN4S
SIN4 Input Select bits
4
1
read-write
SIN5S
SIN5 Input Select bits
10
1
read-write
SIN6S
SIN6 Input Select bits
16
1
read-write
SIN7S
SIN7 Input Select bits
22
1
read-write
SOT4B
SOT4 Input/Output Select bits
6
1
read-write
SOT5B
SOT5 Input/Output Select bits
12
1
read-write
SOT6B
SOT6 Input/Output Select bits
18
1
read-write
SOT7B
SOT7 Input/Output Select bits
24
1
read-write
EPFR09
Extended Pin Function Setting Register 09 [BHW]
0x624
32
read-write
n
0x0
0x0
ADTRG0S
ADTRG0 Input Select bits
12
3
read-write
ADTRG1S
ADTRG1 Input Select bits
16
3
read-write
ADTRG2S
ADTRG2 Input Select bits
20
3
read-write
CRX0S
CRX0S Input Select bits
24
1
read-write
CRX1S
CRX1S Input Select bits
28
1
read-write
CTX0E
CTX0E Output Select bits
26
1
read-write
CTX1E
CTX1E Output Select bits
30
1
read-write
QAIN0S
QAIN0S Input Select bits
0
1
read-write
QAIN1S
QAIN1S Input Select bits
6
1
read-write
QBIN0S
QBIN0S Input Select bits
2
1
read-write
QBIN1S
QBIN1S Input Select bits
8
1
read-write
QZIN0S
QZIN0S Input Select bits
4
1
read-write
QZIN1S
QZIN1S Input Select bits
10
1
read-write
EPFR10
Extended Pin Function Setting Register 10 [BHW]
0x628
32
read-write
n
0x0
0x0
UEA08E
UEA08E Output Select bit
15
read-write
UEA09E
UEA09E Output Select bit
16
read-write
UEA10E
UEA10E Output Select bit
17
read-write
UEA11E
UEA11E Output Select bit
18
read-write
UEA12E
UEA12E Output Select bit
19
read-write
UEA13E
UEA13E Output Select bit
20
read-write
UEA14E
UEA14E Output Select bit
21
read-write
UEA15E
UEA15E Output Select bit
22
read-write
UEA16E
UEA16E Output Select bit
23
read-write
UEA17E
UEA17E Output Select bit
24
read-write
UEA18E
UEA18E Output Select bit
25
read-write
UEA19E
UEA19E Output Select bit
26
read-write
UEA20E
UEA20E Output Select bit
27
read-write
UEA21E
UEA21E Output Select bit
28
read-write
UEA22E
UEA22E Output Select bit
29
read-write
UEA23E
UEA23E Output Select bit
30
read-write
UEA24E
UEA24E Output Select bit
31
read-write
UEAOOE
UEAOOE Output Select bit
14
read-write
UECLKE
UECLKE Output Select bit
2
read-write
UECS1E
UECS1E Output Select bit
7
read-write
UECS2E
UECS2E Output Select bit
8
read-write
UECS3E
UECS3E Output Select bit
9
read-write
UECS4E
UECS4E Output Select bit
10
read-write
UECS5E
UECS5E Output Select bit
11
read-write
UECS6E
UECS6E Output Select bit
12
read-write
UECS7E
UECS7E Output Select bit
13
read-write
UEDEFB
UEDEFB Input/Output Select bit
0
read-write
UEDQME
UEDQME Output Select bit
4
read-write
UEDTHB
UEDTHB Input/Output Select bit
1
read-write
UEFLSE
UEFLSE Output Select bit
6
read-write
UEOEXE
UEOEXE Output Select bit
5
read-write
UEWEXE
UEWEXE Output Select bit
3
read-write
EPFR11
Extended Pin Function Setting Register 11 [BHW]
0x62C
32
read-write
n
0x0
0x0
UEA01E
UEA01E Output Select bit
2
read-write
UEA02E
UEA02E Output Select bit
3
read-write
UEA03E
UEA03E Output Select bit
4
read-write
UEA04E
UEA04E Output Select bit
5
read-write
UEA05E
UEA05E Output Select bit
6
read-write
UEA06E
UEA06E Output Select bit
7
read-write
UEA07E
UEA07E Output Select bit
8
read-write
UEALEE
UEALEE Output Select bit
0
read-write
UECS0E
UECS0E Output Select bit
1
read-write
UED00B
UED00B Input/Output Select bit
9
read-write
UED01B
UED01B Input/Output Select bit
10
read-write
UED02B
UED02B Input/Output Select bit
11
read-write
UED03B
UED03B Input/Output Select bit
12
read-write
UED04B
UED04B Input/Output Select bit
13
read-write
UED05B
UED05B Input/Output Select bit
14
read-write
UED06B
UED06B Input/Output Select bit
15
read-write
UED07B
UED07B Input/Output Select bit
16
read-write
UED08B
UED08B Input/Output Select bit
17
read-write
UED09B
UED09B Input/Output Select bit
18
read-write
UED10B
UED10B Input/Output Select bit
19
read-write
UED11B
UED11B Input/Output Select bit
20
read-write
UED12B
UED12B Input/Output Select bit
21
read-write
UED13B
UED13B Input/Output Select bit
22
read-write
UED14B
UED14B Input/Output Select bit
23
read-write
UED15B
UED15B Input/Output Select bit
24
read-write
UERLC
UERLC relocation select bit
25
read-write
EPFR12
Extended Pin Function Setting Register 12 [BHW]
0x630
32
read-write
n
0x0
0x0
TIOA10E
TIOA10 Output Select bits
18
1
read-write
TIOA11E
TIOA11 Output Select bits
26
1
read-write
TIOA11S
TIOA11 Input Select bits
24
1
read-write
TIOA8E
TIOA8 Output Select bits
2
1
read-write
TIOA9E
TIOA9 Output Select bits
10
1
read-write
TIOA9S
TIOA9 Input Select bits
8
1
read-write
TIOB10S
TIOB10 Input Select bits
20
1
read-write
TIOB11S
TIOB11 Input Select bits
28
1
read-write
TIOB8S
TIOB8 Input Select bits
4
1
read-write
TIOB9S
TIOB9 Input Select bits
12
1
read-write
EPFR13
Extended Pin Function Setting Register 13 [BHW]
0x634
32
read-write
n
0x0
0x0
TIOA12E
TIOA12 Output Select bits
2
1
read-write
TIOA13E
TIOA13 Output Select bits
10
1
read-write
TIOA13S
TIOA13 Input Select bits
8
1
read-write
TIOA14E
TIOA14 Output Select bits
18
1
read-write
TIOA15E
TIOA15 Output Select bits
26
1
read-write
TIOA15S
TIOA15 Input Select bits
24
1
read-write
TIOB12S
TIOB12 Input Select bits
4
1
read-write
TIOB13S
TIOB13 Input Select bits
12
1
read-write
TIOB14S
TIOB14 Input Select bits
20
1
read-write
TIOB15S
TIOB15 Input Select bits
28
1
read-write
EPFR14
Extended Pin Function Setting Register 14 [BHW]
0x638
32
read-write
n
0x0
0x0
E_CKE
E_COUT Output Select bit
26
read-write
E_MC0E
E_MDC0 Output Select bit
22
read-write
E_MC1B
E_MDC1 I/O Select bit
23
read-write
E_MD0B
E_MDO0 I/O Select bit
24
read-write
E_MD1B
E_MDO1 I/O Select bit
25
read-write
E_PSE
PPS0_PPS1 Output Select bit for Ethernet-MAC
27
read-write
E_SPLC
Input cutoff Select bit in Standby of input Pin for Ethernet-MAC
28
1
read-write
E_TD0E
E_TX00/E_TX01 Output Select bit
18
read-write
E_TD1E
E_TX02_TX10/E_TX03_TX11 Output Select bit
19
read-write
E_TE0E
E_TXEN0 Output Select bit
20
read-write
E_TE1E
E_TXER0_TXEN1 Output Select bit
21
read-write
QAIN2S
QDU-ch.2 AIN Input Pin bits
0
1
read-write
QBIN2S
QDU-ch.2 BIN Input Pin bits
2
1
read-write
QZIN2S
QDU-ch.2 ZIN Input Pin bits
4
1
read-write
EPFR15
Extended Pin Function Setting Register 15 [BHW]
0x63C
32
read-write
n
0x0
0x0
EINT16S
External Interrupt 16 Input Select bits
0
1
read-write
EINT17S
External Interrupt 17 Input Select bits
2
1
read-write
EINT18S
External Interrupt 18 Input Select bits
4
1
read-write
EINT19S
External Interrupt 19 Input Select bits
6
1
read-write
EINT20S
External Interrupt 20 Input Select bits
8
1
read-write
EINT21S
External Interrupt 21 Input Select bits
10
1
read-write
EINT22S
External Interrupt 22 Input Select bits
12
1
read-write
EINT23S
External Interrupt 23 Input Select bits
14
1
read-write
EINT24S
External Interrupt 24 Input Select bits
16
1
read-write
EINT25S
External Interrupt 25 Input Select bits
18
1
read-write
EINT26S
External Interrupt 26 Input Select bits
20
1
read-write
EINT27S
External Interrupt 27 Input Select bits
22
1
read-write
EINT28S
External Interrupt 28 Input Select bits
24
1
read-write
EINT29S
External Interrupt 29 Input Select bits
26
1
read-write
EINT30S
External Interrupt 30 Input Select bits
28
1
read-write
EINT31S
External Interrupt 31 Input Select bits
30
1
read-write
EPFR16
Extended Pin Function Setting Register 16 [BHW]
0x640
32
read-write
n
0x0
0x0
SCK10B
SCK10 Input/Output Select bits
20
1
read-write
SCK11B
SCK11 Input/Output Select bits
26
1
read-write
SCK8B
SCK8 Input/Output Select bits
8
1
read-write
SCK9B
SCK9 Input/Output Select bits
14
1
read-write
SCS6B
SCS6 Select bits
0
1
read-write
SCS7B
SCS7 Input/Output Select bits
2
1
read-write
SFMPAC
MFS ch.A I2C FastMode+ Select bit
28
read-write
SFMPBC
MFS ch.B I2C FastMode+ Select bit
29
read-write
SIN10S
SIN10 Input Select bits
16
1
read-write
SIN11S
SIN11 Input Select bits
22
1
read-write
SIN8S
SIN8 Input Select bits
4
1
read-write
SIN9S
SIN9 Input Select bits
10
1
read-write
SOT10B
SOT10 Input/Output Select bits
18
1
read-write
SOT11B
SOT11 Input/Output Select bits
24
1
read-write
SOT8B
SOT8 Input/Output Select bits
6
1
read-write
SOT9B
SOT9 Input/Output Select bits
12
1
read-write
EPFR17
Extended Pin Function Setting Register 17 [BHW]
0x644
32
read-write
n
0x0
0x0
SCK12B
SCK12 Input/Output Select bits
8
1
read-write
SCK13B
SCK13 Input/Output Select bits
14
1
read-write
SCK14B
SCK14 Input/Output Select bits
20
1
read-write
SCK15B
SCK15 Input/Output Select bits
26
1
read-write
SIN12S
SIN12 Input Select bits
4
1
read-write
SIN13S
SIN13 Input Select bits
10
1
read-write
SIN14S
SIN14 Input Select bits
16
1
read-write
SIN15S
SIN15 Input Select bits
22
1
read-write
SOT12B
SOT12 Input/Output Select bits
6
1
read-write
SOT13B
SOT13 Input/Output Select bits
12
1
read-write
SOT14B
SOT14 Input/Output Select bits
18
1
read-write
SOT15B
SOT15 Input/Output Select bits
24
1
read-write
EPFR18
Extended Pin Function Setting Register 18 [BHW]
0x648
32
read-write
n
0x0
0x0
QAIN3S
QDU-ch3 AIN input select bits
4
1
read-write
QBIN3S
QDU-ch3 BIN input select bits
6
1
read-write
QZIN3S
QDU-ch3 ZIN input select bits
8
1
read-write
SDCDS
S_CD input select bits
26
1
read-write
SDCLKE
S_CLK output select bits
14
1
read-write
SDCMDB
S_CMD input/output select bits
16
1
read-write
SDDATA0B
SDDATA0 input/output select bits
18
1
read-write
SDDATA1B
SDDATA1 input/output select bits
20
1
read-write
SDDATA2B
SDDATA2 input/output select bits
22
1
read-write
SDDATA3B
SDDATA3 input/output select bits
24
1
read-write
SDWPS
S_WP input select bits
28
1
read-write
EPFR19
Extended Pin Function Setting Register 19 [BHW]
0x64C
32
read-write
n
0x0
0x0
EPFR20
Extended Pin Function Setting Register 20 [BHW]
0x650
32
read-write
n
0x0
0x0
UECASE
UECASE output select bit
3
read-write
UECSXE
UECSXE output select bit
5
read-write
UED16B
UED16B input/output select bit
9
read-write
UED17B
UED17B input/output select bit
10
read-write
UED18B
UED18B input/output select bit
11
read-write
UED19B
UED19B input/output select bit
12
read-write
UED20B
UED20B input/output select bit
13
read-write
UED21B
UED21B input/output select bit
14
read-write
UED22B
UED22B input/output select bit
15
read-write
UED23B
UED23B input/output select bit
16
read-write
UED24B
UED24B input/output select bit
17
read-write
UED25B
UED25B input/output select bit
18
read-write
UED26B
UED26B input/output select bit
19
read-write
UED27B
UED27B input/output select bit
20
read-write
UED28B
UED28B input/output select bit
21
read-write
UED29B
UED29B input/output select bit
22
read-write
UED30B
UED30B input/output select bit
23
read-write
UED31B
UED31B input/output select bit
24
read-write
UEDQM2E
UEDQM2E output select bit
6
read-write
UEDQM3E
UEDQM3E output select bit
7
read-write
UEDTHHB
UEDTHHB input/output select bit
8
read-write
UEDWEXE
UEDWEXE output select bit
4
read-write
UERASE
UERASE output select bit
2
read-write
UESMCEE
UESMCEE output select bit
1
read-write
UESMCKE
UESMCKE output select bit
0
read-write
EPFR21
Extended Pin Function Setting Register 21 [BHW]
0x654
32
read-write
n
0x0
0x0
EPFR22
Extended Pin Function Setting Register 22 [BHW]
0x658
32
read-write
n
0x0
0x0
EPFR23
Extended Pin Function Setting Register 23 [BHW]
0x65C
32
read-write
n
0x0
0x0
SCS60E
SCS60 Input Select bits
0
1
read-write
SCS61E
SCS61 Input Select bits
2
1
read-write
SCS62E
SCS62 Input Select bits
4
1
read-write
SCS63E
SCS63 Input Select bits
6
1
read-write
SCS70E
SCS70 Input Select bits
8
1
read-write
SCS71E
SCS71 Input Select bits
10
1
read-write
SCS72E
SCS72 Input Select bits
12
1
read-write
SCS73E
SCS73 Input Select bits
14
1
read-write
EPFR24
Extended Pin Function Setting Register 24 [BHW]
0x660
32
read-write
n
0x0
0x0
I2SM4_MCLK0E
I2SMCLK0 Output Select bits
2
1
read-write
I2SM4_MCLK0S
I2SMCLK0 Input Select bits
0
1
read-write
I2SM4_MCLK1E
I2SMCLK1 Output Select bits
18
1
read-write
I2SM4_MCLK1S
I2SMCLK1 Input Select bits
16
1
read-write
I2SM4_SCK0B
I2SCK0 Input/Output Select bits
4
1
read-write
I2SM4_SCK1B
I2SCK1 Input/Output Select bits
20
1
read-write
I2SM4_SDI0S
I2SDI0 Input Select bits
8
1
read-write
I2SM4_SDI1S
I2SDI1 Input Select bits
24
1
read-write
I2SM4_SDO0E
I2SDO0 Output Select bits
10
1
read-write
I2SM4_SDO1E
I2SDO1 Output Select bits
26
1
read-write
I2SM4_WS0B
I2SWS0 Input/Output Select bits
6
1
read-write
I2SM4_WS1B
I2SWS1 Input/Output Select bits
22
1
read-write
EPFR25
Extended Pin Function Setting Register 25 [BHW]
0x664
32
read-write
n
0x0
0x0
MCRX2S
RX2 Input Select bits
0
1
read-write
MCTX2E
TX2 Output Select bits
2
1
read-write
EPFR26
Extended Pin Function Setting Register 26 [BHW]
0x668
32
read-write
n
0x0
0x0
Q_CS0E
Q_CS0 Input Select bits
2
1
read-write
Q_CS1E
Q_CS1 Input Select bits
4
1
read-write
Q_CS2E
Q_CS2 Input Select bits
6
1
read-write
Q_CS3E
Q_CS3 Input Select bits
8
1
read-write
Q_IO0B
Q_IO0 Input Select bits
10
1
read-write
Q_IO1B
Q_IO1 Input Select bits
12
1
read-write
Q_IO2B
Q_IO2 Input Select bits
14
1
read-write
Q_IO3B
Q_IO3 Input Select bits
16
1
read-write
Q_SCKB
Q_SCK Input Select bits
0
1
read-write
EPFR33
Extended Pin Function Setting Regster 33 [BHW]
0x684
32
read-write
n
0x0
0x0
CIN0S
IC0_CIN Input Select bits
0
1
read-write
CIN1S
IC1_CIN Input Select bits
16
1
read-write
CLK0E
IC0_CLK Output Select bits
10
1
read-write
CLK1E
IC1_CLK Oputput Select bits
26
1
read-write
DATA0B
IC0_DATA Input/Output Select bits
2
1
read-write
DATA1B
IC1_DATA Input/Output Select bits
18
1
read-write
RST0E
IC0_RST Output Select bits
4
1
read-write
RST1E
IC1_RST Output Select bits
20
1
read-write
VCC0E
IC0_VCC Output Select bits
8
1
read-write
VCC1E
IC1_VCC Output Select bits
24
1
read-write
VPEN0E
IC0_VPEN Output Select bits
6
1
read-write
VPEN1E
IC1_VPEN Output Select bits
22
1
read-write
EPFR35
Extended Pin Function Setting Regster 35 [BHW]
0x68C
32
read-write
n
0x0
0x0
MCK1E
MI2SMCK1 Output Select bits
18
1
read-write
MCK1S
MI2SMCK1 Input Select bits
16
1
read-write
SCK1B
MI2SCK1 Output Select bits
20
1
read-write
SDI1S
MI2SDI1 Input Select bits
24
1
read-write
SDO1E
MI2SDO1 Output Select bits
26
1
read-write
WS1B
MI2SWS1 Output Select bits
22
1
read-write
PCR0
Pull-up Setting Register 0 [BHW]
0x100
32
read-write
n
0x0
0x0
P0
Bit0 of PCR0
0
read-write
P1
Bit1 of PCR0
1
read-write
P2
Bit2 of PCR0
2
read-write
P3
Bit3 of PCR0
3
read-write
P4
Bit4 of PCR0
4
read-write
P8
Bit8 of PCR0
8
read-write
P9
Bit9 of PCR0
9
read-write
PA
Bit10 of PCR0
10
read-write
PCR1
Pull-up Setting Register 1 [BHW]
0x104
32
read-write
n
0x0
0x0
P0
Bit0 of PCR1
0
read-write
P1
Bit1 of PCR1
1
read-write
P2
Bit2 of PCR1
2
read-write
P3
Bit3 of PCR1
3
read-write
P4
Bit4 of PCR1
4
read-write
P5
Bit5 of PCR1
5
read-write
P6
Bit6 of PCR1
6
read-write
P7
Bit7 of PCR1
7
read-write
P8
Bit8 of PCR1
8
read-write
P9
Bit9 of PCR1
9
read-write
PA
Bit10 of PCR1
10
read-write
PB
Bit11 of PCR1
11
read-write
PC
Bit12 of PCR1
12
read-write
PD
Bit13 of PCR1
13
read-write
PE
Bit14 of PCR1
14
read-write
PF
Bit15 of PCR1
15
read-write
PCR2
Pull-up Setting Register 2 [BHW]
0x108
32
read-write
n
0x0
0x0
P0
Bit0 of PCR2
0
read-write
P1
Bit1 of PCR2
1
read-write
P2
Bit2 of PCR2
2
read-write
P3
Bit3 of PCR2
3
read-write
P4
Bit4 of PCR2
4
read-write
P5
Bit5 of PCR2
5
read-write
P6
Bit6 of PCR2
6
read-write
P7
Bit7 of PCR2
7
read-write
P8
Bit8 of PCR2
8
read-write
P9
Bit9 of PCR2
9
read-write
PA
Bit10 of PCR2
10
read-write
PCR3
Pull-up Setting Register 3 [BHW]
0x10C
32
read-write
n
0x0
0x0
P0
Bit0 of PCR3
0
read-write
P1
Bit1 of PCR3
1
read-write
P2
Bit2 of PCR3
2
read-write
P3
Bit3 of PCR3
3
read-write
P4
Bit4 of PCR3
4
read-write
P5
Bit5 of PCR3
5
read-write
P6
Bit6 of PCR3
6
read-write
P7
Bit7 of PCR3
7
read-write
P8
Bit8 of PCR3
8
read-write
P9
Bit9 of PCR3
9
read-write
PA
Bit10 of PCR3
10
read-write
PB
Bit11 of PCR3
11
read-write
PC
Bit12 of PCR3
12
read-write
PD
Bit13 of PCR3
13
read-write
PE
Bit14 of PCR3
14
read-write
PCR4
Pull-up Setting Register 4 [BHW]
0x110
32
read-write
n
0x0
0x0
P0
Bit0 of PCR4
0
read-write
P1
Bit1 of PCR4
1
read-write
P2
Bit2 of PCR4
2
read-write
P3
Bit3 of PCR4
3
read-write
P4
Bit4 of PCR4
4
read-write
P5
Bit5 of PCR4
5
read-write
P6
Bit6 of PCR4
6
read-write
P7
Bit7 of PCR4
7
read-write
P8
Bit8 of PCR4
8
read-write
P9
Bit9 of PCR4
9
read-write
PA
Bit10 of PCR4
10
read-write
PB
Bit11 of PCR4
11
read-write
PC
Bit12 of PCR4
12
read-write
PD
Bit13 of PCR4
13
read-write
PE
Bit14 of PCR4
14
read-write
PCR5
Pull-up Setting Register 5 [BHW]
0x114
32
read-write
n
0x0
0x0
P0
Bit0 of PCR5
0
read-write
P1
Bit1 of PCR5
1
read-write
P2
Bit2 of PCR5
2
read-write
PD
Bit13 of PCR5
13
read-write
PE
Bit14 of PCR5
14
read-write
PF
Bit15 of PCR5
15
read-write
PCR6
Pull-up Setting Register 6 [BHW]
0x118
32
read-write
n
0x0
0x0
P0
Bit0 of PCR6
0
read-write
P1
Bit1 of PCR6
1
read-write
P2
Bit2 of PCR6
2
read-write
P3
Bit3 of PCR6
3
read-write
P4
Bit4 of PCR6
4
read-write
P5
Bit5 of PCR6
5
read-write
PE
Bit14 of PCR6
14
read-write
PCR7
Pull-up Setting Register 7 [BHW]
0x11C
32
read-write
n
0x0
0x0
P0
Bit0 of PCR7
0
read-write
P1
Bit1 of PCR7
1
read-write
P2
Bit2 of PCR7
2
read-write
P3
Bit3 of PCR7
3
read-write
P4
Bit4 of PCR7
4
read-write
P5
Bit5 of PCR7
5
read-write
P6
Bit6 of PCR7
6
read-write
P7
Bit7 of PCR7
7
read-write
P8
Bit8 of PCR7
8
read-write
P9
Bit9 of PCR7
9
read-write
PA
Bit10 of PCR7
10
read-write
PCR9
Pull-up Setting Register 9 [BHW]
0x124
32
read-write
n
0x0
0x0
P0
Bit0 of PCR9
0
read-write
P1
Bit1 of PCR9
1
read-write
P2
Bit2 of PCR9
2
read-write
P3
Bit3 of PCR9
3
read-write
P4
Bit4 of PCR9
4
read-write
P5
Bit5 of PCR9
5
read-write
PCRA
Pull-up Setting Register A [BHW]
0x128
32
read-write
n
0x0
0x0
P0
Bit0 of PCRA
0
read-write
P1
Bit1 of PCRA
1
read-write
P2
Bit2 of PCRA
2
read-write
P3
Bit3 of PCRA
3
read-write
P4
Bit4 of PCRA
4
read-write
P5
Bit5 of PCRA
5
read-write
P6
Bit6 of PCRA
6
read-write
P7
Bit7 of PCRA
7
read-write
P8
Bit8 of PCRA
8
read-write
P9
Bit9 of PCRA
9
read-write
PA
Bit10 of PCRA
10
read-write
PB
Bit11 of PCRA
11
read-write
PC
Bit12 of PCRA
12
read-write
PD
Bit13 of PCRA
13
read-write
PE
Bit14 of PCRA
14
read-write
PF
Bit15 of PCRA
15
read-write
PCRB
Pull-up Setting Register B [BHW]
0x12C
32
read-write
n
0x0
0x0
P0
Bit0 of PCRB
0
read-write
P1
Bit1 of PCRB
1
read-write
P2
Bit2 of PCRB
2
read-write
P3
Bit3 of PCRB
3
read-write
P4
Bit4 of PCRB
4
read-write
P5
Bit5 of PCRB
5
read-write
P6
Bit6 of PCRB
6
read-write
P7
Bit7 of PCRB
7
read-write
PCRC
Pull-up Setting Register C [BHW]
0x130
32
read-write
n
0x0
0x0
P0
Bit0 of PCRC
0
read-write
P1
Bit1 of PCRC
1
read-write
P2
Bit2 of PCRC
2
read-write
P3
Bit3 of PCRC
3
read-write
P4
Bit4 of PCRC
4
read-write
P5
Bit5 of PCRC
5
read-write
P6
Bit6 of PCRC
6
read-write
P7
Bit7 of PCRC
7
read-write
P8
Bit8 of PCRC
8
read-write
P9
Bit9 of PCRC
9
read-write
PA
Bit10 of PCRC
10
read-write
PB
Bit11 of PCRC
11
read-write
PC
Bit12 of PCRC
12
read-write
PD
Bit13 of PCRC
13
read-write
PE
Bit14 of PCRC
14
read-write
PF
Bit15 of PCRC
15
read-write
PCRD
Pull-up Setting Register D [BHW]
0x134
32
read-write
n
0x0
0x0
P0
Bit0 of PCRD
0
read-write
P1
Bit1 of PCRD
1
read-write
P2
Bit2 of PCRD
2
read-write
PCRE
Pull-up Setting Register E [BHW]
0x138
32
read-write
n
0x0
0x0
P0
Bit0 of PCRE
0
read-write
P2
Bit2 of PCRE
2
read-write
P3
Bit3 of PCRE
3
read-write
PCRF
Pull-up Setting Register F [BHW]
0x13C
32
read-write
n
0x0
0x0
P0
Bit0 of PCRF
0
read-write
P1
Bit1 of PCRF
1
read-write
P2
Bit2 of PCRF
2
read-write
P3
Bit3 of PCRF
3
read-write
P4
Bit4 of PCRF
4
read-write
P5
Bit5 of PCRF
5
read-write
P6
Bit6 of PCRF
6
read-write
P7
Bit7 of PCRF
7
read-write
PDIR0
Port Input Data Register 0 [BHW]
0x300
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR0
0
read-write
P1
Bit1 of PDIR0
1
read-write
P2
Bit2 of PDIR0
2
read-write
P3
Bit3 of PDIR0
3
read-write
P4
Bit4 of PDIR0
4
read-write
P8
Bit8 of PDIR0
8
read-write
P9
Bit9 of PDIR0
9
read-write
PA
Bit10 of PDIR0
10
read-write
PDIR1
Port Input Data Register 1 [BHW]
0x304
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR1
0
read-write
P1
Bit1 of PDIR1
1
read-write
P2
Bit2 of PDIR1
2
read-write
P3
Bit3 of PDIR1
3
read-write
P4
Bit4 of PDIR1
4
read-write
P5
Bit5 of PDIR1
5
read-write
P6
Bit6 of PDIR1
6
read-write
P7
Bit7 of PDIR1
7
read-write
P8
Bit8 of PDIR1
8
read-write
P9
Bit9 of PDIR1
9
read-write
PA
Bit10 of PDIR1
10
read-write
PB
Bit11 of PDIR1
11
read-write
PC
Bit12 of PDIR1
12
read-write
PD
Bit13 of PDIR1
13
read-write
PE
Bit14 of PDIR1
14
read-write
PF
Bit15 of PDIR1
15
read-write
PDIR2
Port Input Data Register 2 [BHW]
0x308
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR2
0
read-write
P1
Bit1 of PDIR2
1
read-write
P2
Bit2 of PDIR2
2
read-write
P3
Bit3 of PDIR2
3
read-write
P4
Bit4 of PDIR2
4
read-write
P5
Bit5 of PDIR2
5
read-write
P6
Bit6 of PDIR2
6
read-write
P7
Bit7 of PDIR2
7
read-write
P8
Bit8 of PDIR2
8
read-write
P9
Bit9 of PDIR2
9
read-write
PA
Bit10 of PDIR2
10
read-write
PDIR3
Port Input Data Register 3 [BHW]
0x30C
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR3
0
read-write
P1
Bit1 of PDIR3
1
read-write
P2
Bit2 of PDIR3
2
read-write
P3
Bit3 of PDIR3
3
read-write
P4
Bit4 of PDIR3
4
read-write
P5
Bit5 of PDIR3
5
read-write
P6
Bit6 of PDIR3
6
read-write
P7
Bit7 of PDIR3
7
read-write
P8
Bit8 of PDIR3
8
read-write
P9
Bit9 of PDIR3
9
read-write
PA
Bit10 of PDIR3
10
read-write
PB
Bit11 of PDIR3
11
read-write
PC
Bit12 of PDIR3
12
read-write
PD
Bit13 of PDIR3
13
read-write
PE
Bit14 of PDIR3
14
read-write
PDIR4
Port Input Data Register 4 [BHW]
0x310
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR4
0
read-write
P1
Bit1 of PDIR4
1
read-write
P2
Bit2 of PDIR4
2
read-write
P3
Bit3 of PDIR4
3
read-write
P4
Bit4 of PDIR4
4
read-write
P5
Bit5 of PDIR4
5
read-write
P6
Bit6 of PDIR4
6
read-write
P7
Bit7 of PDIR4
7
read-write
P8
Bit8 of PDIR4
8
read-write
P9
Bit9 of PDIR4
9
read-write
PA
Bit10 of PDIR4
10
read-write
PB
Bit11 of PDIR4
11
read-write
PC
Bit12 of PDIR4
12
read-write
PD
Bit13 of PDIR4
13
read-write
PE
Bit14 of PDIR4
14
read-write
PDIR5
Port Input Data Register 5 [BHW]
0x314
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR5
0
read-write
P1
Bit1 of PDIR5
1
read-write
P2
Bit2 of PDIR5
2
read-write
PD
Bit13 of PDIR5
13
read-write
PE
Bit14 of PDIR5
14
read-write
PF
Bit15 of PDIR5
15
read-write
PDIR6
Port Input Data Register 6 [BHW]
0x318
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR6
0
read-write
P1
Bit1 of PDIR6
1
read-write
P2
Bit2 of PDIR6
2
read-write
P3
Bit3 of PDIR6
3
read-write
P4
Bit4 of PDIR6
4
read-write
P5
Bit5 of PDIR6
5
read-write
PE
Bit14 of PDIR6
14
read-write
PDIR7
Port Input Data Register 7 [BHW]
0x31C
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR7
0
read-write
P1
Bit1 of PDIR7
1
read-write
P2
Bit2 of PDIR7
2
read-write
P3
Bit3 of PDIR7
3
read-write
P4
Bit4 of PDIR7
4
read-write
P5
Bit5 of PDIR7
5
read-write
P6
Bit6 of PDIR7
6
read-write
P7
Bit7 of PDIR7
7
read-write
P8
Bit8 of PDIR7
8
read-write
P9
Bit9 of PDIR7
9
read-write
PA
Bit10 of PDIR7
10
read-write
PDIR8
Port Input Data Register 8 [BHW]
0x320
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR8
0
read-write
P1
Bit1 of PDIR8
1
read-write
P2
Bit2 of PDIR8
2
read-write
P3
Bit3 of PDIR8
3
read-write
PDIR9
Port Input Data Register 9 [BHW]
0x324
32
read-only
n
0x0
0x0
P0
Bit0 of PDIR9
0
read-write
P1
Bit1 of PDIR9
1
read-write
P2
Bit2 of PDIR9
2
read-write
P3
Bit3 of PDIR9
3
read-write
P4
Bit4 of PDIR9
4
read-write
P5
Bit5 of PDIR9
5
read-write
PDIRA
Port Input Data Register A [BHW]
0x328
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRA
0
read-write
P1
Bit1 of PDIRA
1
read-write
P2
Bit2 of PDIRA
2
read-write
P3
Bit3 of PDIRA
3
read-write
P4
Bit4 of PDIRA
4
read-write
P5
Bit5 of PDIRA
5
read-write
P6
Bit6 of PDIRA
6
read-write
P7
Bit7 of PDIRA
7
read-write
P8
Bit8 of PDIRA
8
read-write
P9
Bit9 of PDIRA
9
read-write
PA
Bit10 of PDIRA
10
read-write
PB
Bit11 of PDIRA
11
read-write
PC
Bit12 of PDIRA
12
read-write
PD
Bit13 of PDIRA
13
read-write
PE
Bit14 of PDIRA
14
read-write
PF
Bit15 of PDIRA
15
read-write
PDIRB
Port Input Data Register B [BHW]
0x32C
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRB
0
read-write
P1
Bit1 of PDIRB
1
read-write
P2
Bit2 of PDIRB
2
read-write
P3
Bit3 of PDIRB
3
read-write
P4
Bit4 of PDIRB
4
read-write
P5
Bit5 of PDIRB
5
read-write
P6
Bit6 of PDIRB
6
read-write
P7
Bit7 of PDIRB
7
read-write
PDIRC
Port Input Data Register C [BHW]
0x330
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRC
0
read-write
P1
Bit1 of PDIRC
1
read-write
P2
Bit2 of PDIRC
2
read-write
P3
Bit3 of PDIRC
3
read-write
P4
Bit4 of PDIRC
4
read-write
P5
Bit5 of PDIRC
5
read-write
P6
Bit6 of PDIRC
6
read-write
P7
Bit7 of PDIRC
7
read-write
P8
Bit8 of PDIRC
8
read-write
P9
Bit9 of PDIRC
9
read-write
PA
Bit10 of PDIRC
10
read-write
PB
Bit11 of PDIRC
11
read-write
PC
Bit12 of PDIRC
12
read-write
PD
Bit13 of PDIRC
13
read-write
PE
Bit14 of PDIRC
14
read-write
PF
Bit15 of PDIRC
15
read-write
PDIRD
Port Input Data Register D [BHW]
0x334
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRD
0
read-write
P1
Bit1 of PDIRD
1
read-write
P2
Bit2 of PDIRD
2
read-write
PDIRE
Port Input Data Register E [BHW]
0x338
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRE
0
read-write
P2
Bit2 of PDIRE
2
read-write
P3
Bit3 of PDIRE
3
read-write
PDIRF
Port Input Data Register F [BHW]
0x33C
32
read-only
n
0x0
0x0
P0
Bit0 of PDIRF
0
read-write
P1
Bit1 of PDIRF
1
read-write
P2
Bit2 of PDIRF
2
read-write
P3
Bit3 of PDIRF
3
read-write
P4
Bit4 of PDIRF
4
read-write
P5
Bit5 of PDIRF
5
read-write
P6
Bit6 of PDIRF
6
read-write
P7
Bit7 of PDIRF
7
read-write
PDOR0
Port Output Data Register 0 [BHW]
0x400
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR0
0
read-write
P1
Bit1 of PDOR0
1
read-write
P2
Bit2 of PDOR0
2
read-write
P3
Bit3 of PDOR0
3
read-write
P4
Bit4 of PDOR0
4
read-write
P8
Bit8 of PDOR0
8
read-write
P9
Bit9 of PDOR0
9
read-write
PA
Bit10 of PDOR0
10
read-write
PDOR1
Port Output Data Register 1 [BHW]
0x404
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR1
0
read-write
P1
Bit1 of PDOR1
1
read-write
P2
Bit2 of PDOR1
2
read-write
P3
Bit3 of PDOR1
3
read-write
P4
Bit4 of PDOR1
4
read-write
P5
Bit5 of PDOR1
5
read-write
P6
Bit6 of PDOR1
6
read-write
P7
Bit7 of PDOR1
7
read-write
P8
Bit8 of PDOR1
8
read-write
P9
Bit9 of PDOR1
9
read-write
PA
Bit10 of PDOR1
10
read-write
PB
Bit11 of PDOR1
11
read-write
PC
Bit12 of PDOR1
12
read-write
PD
Bit13 of PDOR1
13
read-write
PE
Bit14 of PDOR1
14
read-write
PF
Bit15 of PDOR1
15
read-write
PDOR2
Port Output Data Register 2 [BHW]
0x408
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR2
0
read-write
P1
Bit1 of PDOR2
1
read-write
P2
Bit2 of PDOR2
2
read-write
P3
Bit3 of PDOR2
3
read-write
P4
Bit4 of PDOR2
4
read-write
P5
Bit5 of PDOR2
5
read-write
P6
Bit6 of PDOR2
6
read-write
P7
Bit7 of PDOR2
7
read-write
P8
Bit8 of PDOR2
8
read-write
P9
Bit9 of PDOR2
9
read-write
PA
Bit10 of PDOR2
10
read-write
PDOR3
Port Output Data Register 3 [BHW]
0x40C
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR3
0
read-write
P1
Bit1 of PDOR3
1
read-write
P2
Bit2 of PDOR3
2
read-write
P3
Bit3 of PDOR3
3
read-write
P4
Bit4 of PDOR3
4
read-write
P5
Bit5 of PDOR3
5
read-write
P6
Bit6 of PDOR3
6
read-write
P7
Bit7 of PDOR3
7
read-write
P8
Bit8 of PDOR3
8
read-write
P9
Bit9 of PDOR3
9
read-write
PA
Bit10 of PDOR3
10
read-write
PB
Bit11 of PDOR3
11
read-write
PC
Bit12 of PDOR3
12
read-write
PD
Bit13 of PDOR3
13
read-write
PE
Bit14 of PDOR3
14
read-write
PDOR4
Port Output Data Register 4 [BHW]
0x410
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR4
0
read-write
P1
Bit1 of PDOR4
1
read-write
P2
Bit2 of PDOR4
2
read-write
P3
Bit3 of PDOR4
3
read-write
P4
Bit4 of PDOR4
4
read-write
P5
Bit5 of PDOR4
5
read-write
P6
Bit6 of PDOR4
6
read-write
P7
Bit7 of PDOR4
7
read-write
P8
Bit8 of PDOR4
8
read-write
P9
Bit9 of PDOR4
9
read-write
PA
Bit10 of PDOR4
10
read-write
PB
Bit11 of PDOR4
11
read-write
PC
Bit12 of PDOR4
12
read-write
PD
Bit13 of PDOR4
13
read-write
PE
Bit14 of PDOR4
14
read-write
PDOR5
Port Output Data Register 5 [BHW]
0x414
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR5
0
read-write
P1
Bit1 of PDOR5
1
read-write
P2
Bit2 of PDOR5
2
read-write
PD
Bit13 of PDOR5
13
read-write
PE
Bit14 of PDOR5
14
read-write
PF
Bit15 of PDOR5
15
read-write
PDOR6
Port Output Data Register 6 [BHW]
0x418
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR6
0
read-write
P1
Bit1 of PDOR6
1
read-write
P2
Bit2 of PDOR6
2
read-write
P3
Bit3 of PDOR6
3
read-write
P4
Bit4 of PDOR6
4
read-write
P5
Bit5 of PDOR6
5
read-write
PE
Bit14 of PDOR6
14
read-write
PDOR7
Port Output Data Register 7 [BHW]
0x41C
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR7
0
read-write
P1
Bit1 of PDOR7
1
read-write
P2
Bit2 of PDOR7
2
read-write
P3
Bit3 of PDOR7
3
read-write
P4
Bit4 of PDOR7
4
read-write
P5
Bit5 of PDOR7
5
read-write
P6
Bit6 of PDOR7
6
read-write
P7
Bit7 of PDOR7
7
read-write
P8
Bit8 of PDOR7
8
read-write
P9
Bit9 of PDOR7
9
read-write
PA
Bit10 of PDOR7
10
read-write
PDOR8
Port Output Data Register 8 [BHW]
0x420
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR8
0
read-write
P1
Bit1 of PDOR8
1
read-write
P2
Bit2 of PDOR8
2
read-write
P3
Bit3 of PDOR8
3
read-write
PDOR9
Port Output Data Register 9 [BHW]
0x424
32
read-write
n
0x0
0x0
P0
Bit0 of PDOR9
0
read-write
P1
Bit1 of PDOR9
1
read-write
P2
Bit2 of PDOR9
2
read-write
P3
Bit3 of PDOR9
3
read-write
P4
Bit4 of PDOR9
4
read-write
P5
Bit5 of PDOR9
5
read-write
PDORA
Port Output Data Register A [BHW]
0x428
32
read-write
n
0x0
0x0
P0
Bit0 of PDORA
0
read-write
P1
Bit1 of PDORA
1
read-write
P2
Bit2 of PDORA
2
read-write
P3
Bit3 of PDORA
3
read-write
P4
Bit4 of PDORA
4
read-write
P5
Bit5 of PDORA
5
read-write
P6
Bit6 of PDORA
6
read-write
P7
Bit7 of PDORA
7
read-write
P8
Bit8 of PDORA
8
read-write
P9
Bit9 of PDORA
9
read-write
PA
Bit10 of PDORA
10
read-write
PB
Bit11 of PDORA
11
read-write
PC
Bit12 of PDORA
12
read-write
PD
Bit13 of PDORA
13
read-write
PE
Bit14 of PDORA
14
read-write
PF
Bit15 of PDORA
15
read-write
PDORB
Port Output Data Register B [BHW]
0x42C
32
read-write
n
0x0
0x0
P0
Bit0 of PDORB
0
read-write
P1
Bit1 of PDORB
1
read-write
P2
Bit2 of PDORB
2
read-write
P3
Bit3 of PDORB
3
read-write
P4
Bit4 of PDORB
4
read-write
P5
Bit5 of PDORB
5
read-write
P6
Bit6 of PDORB
6
read-write
P7
Bit7 of PDORB
7
read-write
PDORC
Port Output Data Register C [BHW]
0x430
32
read-write
n
0x0
0x0
P0
Bit0 of PDORC
0
read-write
P1
Bit1 of PDORC
1
read-write
P2
Bit2 of PDORC
2
read-write
P3
Bit3 of PDORC
3
read-write
P4
Bit4 of PDORC
4
read-write
P5
Bit5 of PDORC
5
read-write
P6
Bit6 of PDORC
6
read-write
P7
Bit7 of PDORC
7
read-write
P8
Bit8 of PDORC
8
read-write
P9
Bit9 of PDORC
9
read-write
PA
Bit10 of PDORC
10
read-write
PB
Bit11 of PDORC
11
read-write
PC
Bit12 of PDORC
12
read-write
PD
Bit13 of PDORC
13
read-write
PE
Bit14 of PDORC
14
read-write
PF
Bit15 of PDORC
15
read-write
PDORD
Port Output Data Register D [BHW]
0x434
32
read-write
n
0x0
0x0
P0
Bit0 of PDORD
0
read-write
P1
Bit1 of PDORD
1
read-write
P2
Bit2 of PDORD
2
read-write
PDORE
Port Output Data Register E [BHW]
0x438
32
read-write
n
0x0
0x0
P0
Bit0 of PDORE
0
read-write
P2
Bit2 of PDORE
2
read-write
P3
Bit3 of PDORE
3
read-write
PDORF
Port Output Data Register F [BHW]
0x43C
32
read-write
n
0x0
0x0
P0
Bit0 of PDORF
0
read-write
P1
Bit1 of PDORF
1
read-write
P2
Bit2 of PDORF
2
read-write
P3
Bit3 of PDORF
3
read-write
P4
Bit4 of PDORF
4
read-write
P5
Bit5 of PDORF
5
read-write
P6
Bit6 of PDORF
6
read-write
P7
Bit7 of PDORF
7
read-write
PDSR0
Port Driver capability Select Register 0 [BHW]
0x740
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR0
0
read-write
P1
Bit1 of PDSR0
1
read-write
P2
Bit2 of PDSR0
2
read-write
P3
Bit3 of PDSR0
3
read-write
P4
Bit4 of PDSR0
4
read-write
P8
Bit8 of PDSR0
8
read-write
P9
Bit9 of PDSR0
9
read-write
PA
Bit10 of PDSR0
10
read-write
PDSR1
Port Driver capability Select Register 1 [BHW]
0x744
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR1
0
read-write
P1
Bit1 of PDSR1
1
read-write
P2
Bit2 of PDSR1
2
read-write
P3
Bit3 of PDSR1
3
read-write
P4
Bit4 of PDSR1
4
read-write
P5
Bit5 of PDSR1
5
read-write
P6
Bit6 of PDSR1
6
read-write
P7
Bit7 of PDSR1
7
read-write
P8
Bit8 of PDSR1
8
read-write
P9
Bit9 of PDSR1
9
read-write
PA
Bit10 of PDSR1
10
read-write
PB
Bit11 of PDSR1
11
read-write
PC
Bit12 of PDSR1
12
read-write
PD
Bit13 of PDSR1
13
read-write
PE
Bit14 of PDSR1
14
read-write
PF
Bit15 of PDSR1
15
read-write
PDSR2
Port Driver capability Select Register 2 [BHW]
0x748
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR2
0
read-write
P1
Bit1 of PDSR2
1
read-write
P2
Bit2 of PDSR2
2
read-write
P3
Bit3 of PDSR2
3
read-write
P4
Bit4 of PDSR2
4
read-write
P5
Bit5 of PDSR2
5
read-write
P6
Bit6 of PDSR2
6
read-write
P7
Bit7 of PDSR2
7
read-write
P8
Bit8 of PDSR2
8
read-write
P9
Bit9 of PDSR2
9
read-write
PA
Bit10 of PDSR2
10
read-write
PDSR3
Port Driver capability Select Register 3 [BHW]
0x74C
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR3
0
read-write
P1
Bit1 of PDSR3
1
read-write
P2
Bit2 of PDSR3
2
read-write
P3
Bit3 of PDSR3
3
read-write
P4
Bit4 of PDSR3
4
read-write
P5
Bit5 of PDSR3
5
read-write
P6
Bit6 of PDSR3
6
read-write
P7
Bit7 of PDSR3
7
read-write
P8
Bit8 of PDSR3
8
read-write
P9
Bit9 of PDSR3
9
read-write
PA
Bit10 of PDSR3
10
read-write
PB
Bit11 of PDSR3
11
read-write
PC
Bit12 of PDSR3
12
read-write
PD
Bit13 of PDSR3
13
read-write
PE
Bit14 of PDSR3
14
read-write
PDSR4
Port Driver capability Select Register 4 [BHW]
0x750
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR4
0
read-write
P1
Bit1 of PDSR4
1
read-write
P2
Bit2 of PDSR4
2
read-write
P3
Bit3 of PDSR4
3
read-write
P4
Bit4 of PDSR4
4
read-write
P5
Bit5 of PDSR4
5
read-write
P6
Bit6 of PDSR4
6
read-write
P7
Bit7 of PDSR4
7
read-write
P8
Bit8 of PDSR4
8
read-write
P9
Bit9 of PDSR4
9
read-write
PA
Bit10 of PDSR4
10
read-write
PB
Bit11 of PDSR4
11
read-write
PC
Bit12 of PDSR4
12
read-write
PD
Bit13 of PDSR4
13
read-write
PE
Bit14 of PDSR4
14
read-write
PDSR5
Port Driver capability Select Register 5 [BHW]
0x754
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR5
0
read-write
P1
Bit1 of PDSR5
1
read-write
P2
Bit2 of PDSR5
2
read-write
PD
Bit13 of PDSR5
13
read-write
PE
Bit14 of PDSR5
14
read-write
PF
Bit15 of PDSR5
15
read-write
PDSR6
Port Driver capability Select Register 6 [BHW]
0x758
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR6
0
read-write
P1
Bit1 of PDSR6
1
read-write
P2
Bit2 of PDSR6
2
read-write
P3
Bit3 of PDSR6
3
read-write
P4
Bit4 of PDSR6
4
read-write
P5
Bit5 of PDSR6
5
read-write
PE
Bit14 of PDSR6
14
read-write
PDSR7
Port Driver capability Select Register 7 [BHW]
0x75C
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR7
0
read-write
P1
Bit1 of PDSR7
1
read-write
P2
Bit2 of PDSR7
2
read-write
P3
Bit3 of PDSR7
3
read-write
P4
Bit4 of PDSR7
4
read-write
P5
Bit5 of PDSR7
5
read-write
P6
Bit6 of PDSR7
6
read-write
P7
Bit7 of PDSR7
7
read-write
P8
Bit8 of PDSR7
8
read-write
P9
Bit9 of PDSR7
9
read-write
PA
Bit10 of PDSR7
10
read-write
PDSR8
Port Driver capability Select Register 8 [BHW]
0x760
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR8
0
read-write
P1
Bit1 of PDSR8
1
read-write
P2
Bit2 of PDSR8
2
read-write
P3
Bit3 of PDSR8
3
read-write
PDSR9
Port Driver capability Select Register 9 [BHW]
0x764
32
read-write
n
0x0
0x0
P0
Bit0 of PDSR9
0
read-write
P1
Bit1 of PDSR9
1
read-write
P2
Bit2 of PDSR9
2
read-write
P3
Bit3 of PDSR9
3
read-write
P4
Bit4 of PDSR9
4
read-write
P5
Bit5 of PDSR9
5
read-write
PDSRA
Port Driver capability Select Register A [BHW]
0x768
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRA
0
read-write
P1
Bit1 of PDSRA
1
read-write
P2
Bit2 of PDSRA
2
read-write
P3
Bit3 of PDSRA
3
read-write
P4
Bit4 of PDSRA
4
read-write
P5
Bit5 of PDSRA
5
read-write
P6
Bit6 of PDSRA
6
read-write
P7
Bit7 of PDSRA
7
read-write
P8
Bit8 of PDSRA
8
read-write
P9
Bit9 of PDSRA
9
read-write
PA
Bit10 of PDSRA
10
read-write
PB
Bit11 of PDSRA
11
read-write
PC
Bit12 of PDSRA
12
read-write
PD
Bit13 of PDSRA
13
read-write
PE
Bit14 of PDSRA
14
read-write
PF
Bit15 of PDSRA
15
read-write
PDSRB
Port Driver capability Select Register B [BHW]
0x76C
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRB
0
read-write
P1
Bit1 of PDSRB
1
read-write
P2
Bit2 of PDSRB
2
read-write
P3
Bit3 of PDSRB
3
read-write
P4
Bit4 of PDSRB
4
read-write
P5
Bit5 of PDSRB
5
read-write
P6
Bit6 of PDSRB
6
read-write
P7
Bit7 of PDSRB
7
read-write
PDSRC
Port Driver capability Select Register C [BHW]
0x770
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRC
0
read-write
P1
Bit1 of PDSRC
1
read-write
P2
Bit2 of PDSRC
2
read-write
P3
Bit3 of PDSRC
3
read-write
P4
Bit4 of PDSRC
4
read-write
P5
Bit5 of PDSRC
5
read-write
P6
Bit6 of PDSRC
6
read-write
P7
Bit7 of PDSRC
7
read-write
P8
Bit8 of PDSRC
8
read-write
P9
Bit9 of PDSRC
9
read-write
PA
Bit10 of PDSRC
10
read-write
PB
Bit11 of PDSRC
11
read-write
PC
Bit12 of PDSRC
12
read-write
PD
Bit13 of PDSRC
13
read-write
PE
Bit14 of PDSRC
14
read-write
PF
Bit15 of PDSRC
15
read-write
PDSRD
Port Driver capability Select Register D [BHW]
0x774
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRD
0
read-write
P1
Bit1 of PDSRD
1
read-write
P2
Bit2 of PDSRD
2
read-write
PDSRE
Port Driver capability Select Register E [BHW]
0x778
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRE
0
read-write
P2
Bit2 of PDSRE
2
read-write
P3
Bit3 of PDSRE
3
read-write
PDSRF
Port Driver capability Select Register F [BHW]
0x77C
32
read-write
n
0x0
0x0
P0
Bit0 of PDSRF
0
read-write
P1
Bit1 of PDSRF
1
read-write
P2
Bit2 of PDSRF
2
read-write
P3
Bit3 of PDSRF
3
read-write
P4
Bit4 of PDSRF
4
read-write
P5
Bit5 of PDSRF
5
read-write
P6
Bit6 of PDSRF
6
read-write
P7
Bit7 of PDSRF
7
read-write
PFR0
Port Function Setting Register 0 [BHW]
0x0
32
read-write
n
0x0
0x0
P0
Bit0 of PFR0
0
read-write
P1
Bit1 of PFR0
1
read-write
P2
Bit2 of PFR0
2
read-write
P3
Bit3 of PFR0
3
read-write
P4
Bit4 of PFR0
4
read-write
P8
Bit8 of PFR0
8
read-write
P9
Bit9 of PFR0
9
read-write
PA
Bit10 of PFR0
10
read-write
PFR1
Port Function Setting Register 1 [BHW]
0x4
32
read-write
n
0x0
0x0
P0
Bit0 of PFR1
0
read-write
P1
Bit1 of PFR1
1
read-write
P2
Bit2 of PFR1
2
read-write
P3
Bit3 of PFR1
3
read-write
P4
Bit4 of PFR1
4
read-write
P5
Bit5 of PFR1
5
read-write
P6
Bit6 of PFR1
6
read-write
P7
Bit7 of PFR1
7
read-write
P8
Bit8 of PFR1
8
read-write
P9
Bit9 of PFR1
9
read-write
PA
Bit10 of PFR1
10
read-write
PB
Bit11 of PFR1
11
read-write
PC
Bit12 of PFR1
12
read-write
PD
Bit13 of PFR1
13
read-write
PE
Bit14 of PFR1
14
read-write
PF
Bit15 of PFR1
15
read-write
PFR2
Port Function Setting Register 2 [BHW]
0x8
32
read-write
n
0x0
0x0
P0
Bit0 of PFR2
0
read-write
P1
Bit1 of PFR2
1
read-write
P2
Bit2 of PFR2
2
read-write
P3
Bit3 of PFR2
3
read-write
P4
Bit4 of PFR2
4
read-write
P5
Bit5 of PFR2
5
read-write
P6
Bit6 of PFR2
6
read-write
P7
Bit7 of PFR2
7
read-write
P8
Bit8 of PFR2
8
read-write
P9
Bit9 of PFR2
9
read-write
PA
Bit10 of PFR2
10
read-write
PFR3
Port Function Setting Register 3 [BHW]
0xC
32
read-write
n
0x0
0x0
P0
Bit0 of PFR3
0
read-write
P1
Bit1 of PFR3
1
read-write
P2
Bit2 of PFR3
2
read-write
P3
Bit3 of PFR3
3
read-write
P4
Bit4 of PFR3
4
read-write
P5
Bit5 of PFR3
5
read-write
P6
Bit6 of PFR3
6
read-write
P7
Bit7 of PFR3
7
read-write
P8
Bit8 of PFR3
8
read-write
P9
Bit9 of PFR3
9
read-write
PA
Bit10 of PFR3
10
read-write
PB
Bit11 of PFR3
11
read-write
PC
Bit12 of PFR3
12
read-write
PD
Bit13 of PFR3
13
read-write
PE
Bit14 of PFR3
14
read-write
PFR4
Port Function Setting Register 4 [BHW]
0x10
32
read-write
n
0x0
0x0
P0
Bit0 of PFR4
0
read-write
P1
Bit1 of PFR4
1
read-write
P2
Bit2 of PFR4
2
read-write
P3
Bit3 of PFR4
3
read-write
P4
Bit4 of PFR4
4
read-write
P5
Bit5 of PFR4
5
read-write
P6
Bit6 of PFR4
6
read-write
P7
Bit7 of PFR4
7
read-write
P8
Bit8 of PFR4
8
read-write
P9
Bit9 of PFR4
9
read-write
PA
Bit10 of PFR4
10
read-write
PB
Bit11 of PFR4
11
read-write
PC
Bit12 of PFR4
12
read-write
PD
Bit13 of PFR4
13
read-write
PE
Bit14 of PFR4
14
read-write
PFR5
Port Function Setting Register 5 [BHW]
0x14
32
read-write
n
0x0
0x0
P0
Bit0 of PFR5
0
read-write
P1
Bit1 of PFR5
1
read-write
P2
Bit2 of PFR5
2
read-write
PD
Bit13 of PFR5
13
read-write
PE
Bit14 of PFR5
14
read-write
PF
Bit15 of PFR5
15
read-write
PFR6
Port Function Setting Register 6 [BHW]
0x18
32
read-write
n
0x0
0x0
P0
Bit0 of PFR6
0
read-write
P1
Bit1 of PFR6
1
read-write
P2
Bit2 of PFR6
2
read-write
P3
Bit3 of PFR6
3
read-write
P4
Bit4 of PFR6
4
read-write
P5
Bit5 of PFR6
5
read-write
PE
Bit14 of PFR6
14
read-write
PFR7
Port Function Setting Register 7 [BHW]
0x1C
32
read-write
n
0x0
0x0
P0
Bit0 of PFR7
0
read-write
P1
Bit1 of PFR7
1
read-write
P2
Bit2 of PFR7
2
read-write
P3
Bit3 of PFR7
3
read-write
P4
Bit4 of PFR7
4
read-write
P5
Bit5 of PFR7
5
read-write
P6
Bit6 of PFR7
6
read-write
P7
Bit7 of PFR7
7
read-write
P8
Bit8 of PFR7
8
read-write
P9
Bit9 of PFR7
9
read-write
PA
Bit10 of PFR7
10
read-write
PFR8
Port Function Setting Register 8 [BHW]
0x20
32
read-write
n
0x0
0x0
P0
Bit0 of PFR8
0
read-write
P1
Bit1 of PFR8
1
read-write
P2
Bit2 of PFR8
2
read-write
P3
Bit3 of PFR8
3
read-write
PFR9
Port Function Setting Register 9 [BHW]
0x24
32
read-write
n
0x0
0x0
P0
Bit0 of PFR9
0
read-write
P1
Bit1 of PFR9
1
read-write
P2
Bit2 of PFR9
2
read-write
P3
Bit3 of PFR9
3
read-write
P4
Bit4 of PFR9
4
read-write
P5
Bit5 of PFR9
5
read-write
PFRA
Port Function Setting Register A [BHW]
0x28
32
read-write
n
0x0
0x0
P0
Bit0 of PFRA
0
read-write
P1
Bit1 of PFRA
1
read-write
P2
Bit2 of PFRA
2
read-write
P3
Bit3 of PFRA
3
read-write
P4
Bit4 of PFRA
4
read-write
P5
Bit5 of PFRA
5
read-write
P6
Bit6 of PFRA
6
read-write
P7
Bit7 of PFRA
7
read-write
P8
Bit8 of PFRA
8
read-write
P9
Bit9 of PFRA
9
read-write
PA
Bit10 of PFRA
10
read-write
PB
Bit11 of PFRA
11
read-write
PC
Bit12 of PFRA
12
read-write
PD
Bit13 of PFRA
13
read-write
PE
Bit14 of PFRA
14
read-write
PF
Bit15 of PFRA
15
read-write
PFRB
Port Function Setting Register B [BHW]
0x2C
32
read-write
n
0x0
0x0
P0
Bit0 of PFRB
0
read-write
P1
Bit1 of PFRB
1
read-write
P2
Bit2 of PFRB
2
read-write
P3
Bit3 of PFRB
3
read-write
P4
Bit4 of PFRB
4
read-write
P5
Bit5 of PFRB
5
read-write
P6
Bit6 of PFRB
6
read-write
P7
Bit7 of PFRB
7
read-write
PFRC
Port Function Setting Register C [BHW]
0x30
32
read-write
n
0x0
0x0
P0
Bit0 of PFRC
0
read-write
P1
Bit1 of PFRC
1
read-write
P2
Bit2 of PFRC
2
read-write
P3
Bit3 of PFRC
3
read-write
P4
Bit4 of PFRC
4
read-write
P5
Bit5 of PFRC
5
read-write
P6
Bit6 of PFRC
6
read-write
P7
Bit7 of PFRC
7
read-write
P8
Bit8 of PFRC
8
read-write
P9
Bit9 of PFRC
9
read-write
PA
Bit10 of PFRC
10
read-write
PB
Bit11 of PFRC
11
read-write
PC
Bit12 of PFRC
12
read-write
PD
Bit13 of PFRC
13
read-write
PE
Bit14 of PFRC
14
read-write
PF
Bit15 of PFRC
15
read-write
PFRD
Port Function Setting Register D [BHW]
0x34
32
read-write
n
0x0
0x0
P0
Bit0 of PFRD
0
read-write
P1
Bit1 of PFRD
1
read-write
P2
Bit2 of PFRD
2
read-write
PFRE
Port Function Setting Register E [BHW]
0x38
32
read-write
n
0x0
0x0
P0
Bit0 of PFRE
0
read-write
P2
Bit2 of PFRE
2
read-write
P3
Bit3 of PFRE
3
read-write
PFRF
Port Function Setting Register F [BHW]
0x3C
32
read-write
n
0x0
0x0
P0
Bit0 of PFRF
0
read-write
P1
Bit1 of PFRF
1
read-write
P2
Bit2 of PFRF
2
read-write
P3
Bit3 of PFRF
3
read-write
P4
Bit4 of PFRF
4
read-write
P5
Bit5 of PFRF
5
read-write
P6
Bit6 of PFRF
6
read-write
P7
Bit7 of PFRF
7
read-write
PZR0
Port Pseudo Open Drain Setting Register 0 [BHW]
0x700
32
read-write
n
0x0
0x0
P0
Bit0 of PZR0
0
read-write
P1
Bit1 of PZR0
1
read-write
P2
Bit2 of PZR0
2
read-write
P3
Bit3 of PZR0
3
read-write
P4
Bit4 of PZR0
4
read-write
P8
Bit8 of PZR0
8
read-write
P9
Bit9 of PZR0
9
read-write
PA
Bit10 of PZR0
10
read-write
PZR1
Port Pseudo Open Drain Setting Register 1 [BHW]
0x704
32
read-write
n
0x0
0x0
P0
Bit0 of PZR1
0
read-write
P1
Bit1 of PZR1
1
read-write
P2
Bit2 of PZR1
2
read-write
P3
Bit3 of PZR1
3
read-write
P4
Bit4 of PZR1
4
read-write
P5
Bit5 of PZR1
5
read-write
P6
Bit6 of PZR1
6
read-write
P7
Bit7 of PZR1
7
read-write
P8
Bit8 of PZR1
8
read-write
P9
Bit9 of PZR1
9
read-write
PA
Bit10 of PZR1
10
read-write
PB
Bit11 of PZR1
11
read-write
PC
Bit12 of PZR1
12
read-write
PD
Bit13 of PZR1
13
read-write
PE
Bit14 of PZR1
14
read-write
PF
Bit15 of PZR1
15
read-write
PZR2
Port Pseudo Open Drain Setting Register 2 [BHW]
0x708
32
read-write
n
0x0
0x0
P0
Bit0 of PZR2
0
read-write
P1
Bit1 of PZR2
1
read-write
P2
Bit2 of PZR2
2
read-write
P3
Bit3 of PZR2
3
read-write
P4
Bit4 of PZR2
4
read-write
P5
Bit5 of PZR2
5
read-write
P6
Bit6 of PZR2
6
read-write
P7
Bit7 of PZR2
7
read-write
P8
Bit8 of PZR2
8
read-write
P9
Bit9 of PZR2
9
read-write
PA
Bit10 of PZR2
10
read-write
PZR3
Port Pseudo Open Drain Setting Register 3 [BHW]
0x70C
32
read-write
n
0x0
0x0
P0
Bit0 of PZR3
0
read-write
P1
Bit1 of PZR3
1
read-write
P2
Bit2 of PZR3
2
read-write
P3
Bit3 of PZR3
3
read-write
P4
Bit4 of PZR3
4
read-write
P5
Bit5 of PZR3
5
read-write
P6
Bit6 of PZR3
6
read-write
P7
Bit7 of PZR3
7
read-write
P8
Bit8 of PZR3
8
read-write
P9
Bit9 of PZR3
9
read-write
PA
Bit10 of PZR3
10
read-write
PB
Bit11 of PZR3
11
read-write
PC
Bit12 of PZR3
12
read-write
PD
Bit13 of PZR3
13
read-write
PE
Bit14 of PZR3
14
read-write
PZR4
Port Pseudo Open Drain Setting Register 4 [BHW]
0x710
32
read-write
n
0x0
0x0
P0
Bit0 of PZR4
0
read-write
P1
Bit1 of PZR4
1
read-write
P2
Bit2 of PZR4
2
read-write
P3
Bit3 of PZR4
3
read-write
P4
Bit4 of PZR4
4
read-write
P5
Bit5 of PZR4
5
read-write
P6
Bit6 of PZR4
6
read-write
P7
Bit7 of PZR4
7
read-write
P8
Bit8 of PZR4
8
read-write
P9
Bit9 of PZR4
9
read-write
PA
Bit10 of PZR4
10
read-write
PB
Bit11 of PZR4
11
read-write
PC
Bit12 of PZR4
12
read-write
PD
Bit13 of PZR4
13
read-write
PE
Bit14 of PZR4
14
read-write
PZR5
Port Pseudo Open Drain Setting Register 5 [BHW]
0x714
32
read-write
n
0x0
0x0
P0
Bit0 of PZR5
0
read-write
P1
Bit1 of PZR5
1
read-write
P2
Bit2 of PZR5
2
read-write
PD
Bit13 of PZR5
13
read-write
PE
Bit14 of PZR5
14
read-write
PF
Bit15 of PZR5
15
read-write
PZR6
Port Pseudo Open Drain Setting Register 6 [BHW]
0x718
32
read-write
n
0x0
0x0
P0
Bit0 of PZR6
0
read-write
P1
Bit1 of PZR6
1
read-write
P2
Bit2 of PZR6
2
read-write
P3
Bit3 of PZR6
3
read-write
P4
Bit4 of PZR6
4
read-write
P5
Bit5 of PZR6
5
read-write
PE
Bit14 of PZR6
14
read-write
PZR7
Port Pseudo Open Drain Setting Register 7 [BHW]
0x71C
32
read-write
n
0x0
0x0
P0
Bit0 of PZR7
0
read-write
P1
Bit1 of PZR7
1
read-write
P2
Bit2 of PZR7
2
read-write
P3
Bit3 of PZR7
3
read-write
P4
Bit4 of PZR7
4
read-write
P5
Bit5 of PZR7
5
read-write
P6
Bit6 of PZR7
6
read-write
P7
Bit7 of PZR7
7
read-write
P8
Bit8 of PZR7
8
read-write
P9
Bit9 of PZR7
9
read-write
PA
Bit10 of PZR7
10
read-write
PZR8
Port Pseudo Open Drain Setting Register 8 [BHW]
0x720
32
read-write
n
0x0
0x0
P0
Bit0 of PZR8
0
read-write
P1
Bit1 of PZR8
1
read-write
P2
Bit2 of PZR8
2
read-write
P3
Bit3 of PZR8
3
read-write
PZR9
Port Pseudo Open Drain Setting Register 9 [BHW]
0x724
32
read-write
n
0x0
0x0
P0
Bit0 of PZR9
0
read-write
P1
Bit1 of PZR9
1
read-write
P2
Bit2 of PZR9
2
read-write
P3
Bit3 of PZR9
3
read-write
P4
Bit4 of PZR9
4
read-write
P5
Bit5 of PZR9
5
read-write
PZRA
Port Pseudo Open Drain Setting Register A [BHW]
0x728
32
read-write
n
0x0
0x0
P0
Bit0 of PZRA
0
read-write
P1
Bit1 of PZRA
1
read-write
P2
Bit2 of PZRA
2
read-write
P3
Bit3 of PZRA
3
read-write
P4
Bit4 of PZRA
4
read-write
P5
Bit5 of PZRA
5
read-write
P6
Bit6 of PZRA
6
read-write
P7
Bit7 of PZRA
7
read-write
P8
Bit8 of PZRA
8
read-write
P9
Bit9 of PZRA
9
read-write
PA
Bit10 of PZRA
10
read-write
PB
Bit11 of PZRA
11
read-write
PC
Bit12 of PZRA
12
read-write
PD
Bit13 of PZRA
13
read-write
PE
Bit14 of PZRA
14
read-write
PF
Bit15 of PZRA
15
read-write
PZRB
Port Pseudo Open Drain Setting Register B [BHW]
0x72C
32
read-write
n
0x0
0x0
P0
Bit0 of PZRB
0
read-write
P1
Bit1 of PZRB
1
read-write
P2
Bit2 of PZRB
2
read-write
P3
Bit3 of PZRB
3
read-write
P4
Bit4 of PZRB
4
read-write
P5
Bit5 of PZRB
5
read-write
P6
Bit6 of PZRB
6
read-write
P7
Bit7 of PZRB
7
read-write
PZRC
Port Pseudo Open Drain Setting Register C [BHW]
0x730
32
read-write
n
0x0
0x0
P0
Bit0 of PZRC
0
read-write
P1
Bit1 of PZRC
1
read-write
P2
Bit2 of PZRC
2
read-write
P3
Bit3 of PZRC
3
read-write
P4
Bit4 of PZRC
4
read-write
P5
Bit5 of PZRC
5
read-write
P6
Bit6 of PZRC
6
read-write
P7
Bit7 of PZRC
7
read-write
P8
Bit8 of PZRC
8
read-write
P9
Bit9 of PZRC
9
read-write
PA
Bit10 of PZRC
10
read-write
PB
Bit11 of PZRC
11
read-write
PC
Bit12 of PZRC
12
read-write
PD
Bit13 of PZRC
13
read-write
PE
Bit14 of PZRC
14
read-write
PF
Bit15 of PZRC
15
read-write
PZRD
Port Pseudo Open Drain Setting Register D [BHW]
0x734
32
read-write
n
0x0
0x0
P0
Bit0 of PZRD
0
read-write
P1
Bit1 of PZRD
1
read-write
P2
Bit2 of PZRD
2
read-write
PZRE
Port Pseudo Open Drain Setting Register E [BHW]
0x738
32
read-write
n
0x0
0x0
P0
Bit0 of PZRE
0
read-write
P2
Bit2 of PZRE
2
read-write
P3
Bit3 of PZRE
3
read-write
PZRF
Port Pseudo Open Drain Setting Register F [BHW]
0x73C
32
read-write
n
0x0
0x0
P0
Bit0 of PZRF
0
read-write
P1
Bit1 of PZRF
1
read-write
P2
Bit2 of PZRF
2
read-write
P3
Bit3 of PZRF
3
read-write
P4
Bit4 of PZRF
4
read-write
P5
Bit5 of PZRF
5
read-write
P6
Bit6 of PZRF
6
read-write
P7
Bit7 of PZRF
7
read-write
SPSR
Special Port Setting Register [BHW]
0x580
32
read-write
n
0x0
0x0
MAINXC
Main Clock (Oscillation) Pin Setting bits
2
1
read-write
SUBXC
Sub Clock (Oscillation) Pin Setting Register
0
1
read-write
USB0C
USB (ch.0) Pin Setting bit
4
read-write
USB1C
USB (ch.1) Pin Setting bit
5
read-write
HWWDT
Hardware Watchdog Timer
HWWDT
0x0
0x0
0x4
registers
n
0x10
0x4
registers
n
0x4
0x4
registers
n
0x8
0x4
registers
n
0xC
0x4
registers
n
0xC00
0x4
registers
n
WDG_CTL
Hardware Watchdog Timer Control Register [W]
0x8
32
read-write
n
0x0
0x0
INTEN
Hardware watchdog interrupt and counter enable bit
0
read-write
RESEN
Hardware watchdog reset enable bit
1
read-write
WDG_ICL
Hardware Watchdog Timer Clear Register [W]
0xC
32
read-write
n
0x0
0x0
WDG_LCK
Hardware Watchdog Timer Lock Register [W]
0xC00
32
read-write
n
0x0
0x0
WDG_LDR
Hardware Watchdog Timer Load Register [W]
0x0
32
read-write
n
0x0
0x0
WDG_RIS
Hardware Watchdog Timer Interrupt Status Register [W]
0x10
32
read-only
n
0x0
0x0
RIS
Hardware watchdog interrupt status bit
0
read-only
WDG_VLR
Hardware Watchdog Timer Value Register [W]
0x4
32
read-only
n
0x0
0x0
INTREQ
Interrupts
INTREQ
0x0
0x0
0x4
registers
n
0x10
0x1
registers
n
0x110
0x20
registers
n
0x14
0x1
registers
n
0x200
0x204
registers
n
IRQ003SEL
3
IRQ004SEL
4
IRQ005SEL
5
IRQ006SEL
6
IRQ007SEL
7
IRQ008SEL
8
IRQ009SEL
9
IRQ010SEL
10
DRQSEL
DMA Request Selection Register [BHW]
0x0
32
read-write
n
0x0
0x0
ADCSCAN0
A/D converter unit 0 scan conversion interrupt
5
read-write
ADCSCAN1
A/D converter unit 1 scan conversion interrupt
6
read-write
ADCSCAN2
A/D converter unit 2 scan conversion interrupt
7
read-write
EXINT0
External pin interrupt ch.0
28
read-write
EXINT1
External pin interrupt ch.1
29
read-write
EXINT2
External pin interrupt ch.2
30
read-write
EXINT3
External pin interrupt ch.3
31
read-write
IRQ0BT0
Base timer ch.6 source 0 (IRQ0) interrupt
8
read-write
IRQ0BT2
Base timer ch.2 source 0 (IRQ0) interrupt
9
read-write
IRQ0BT4
Base timer ch.4 source 0 (IRQ0) interrupt
10
read-write
IRQ0BT6
Base timer ch.6 source 0 (IRQ0) interrupt
11
read-write
MFS0RX
MFS ch.0 reception interrupt
12
read-write
MFS0TX
MFS ch.0 transmission interrupt
13
read-write
MFS1RX
MFS ch.1 reception interrupt
14
read-write
MFS1TX
MFS ch.1 transmission interrupt
15
read-write
MFS2RX
MFS ch.2 reception interrupt
16
read-write
MFS2TX
MFS ch.2 transmission interrupt
17
read-write
MFS3RX
MFS ch.3 reception interrupt
18
read-write
MFS3TX
MFS ch.3 transmission interrupt
19
read-write
MFS4RX
MFS ch.4 reception interrupt
20
read-write
MFS4TX
MFS ch.4 transmission interrupt
21
read-write
MFS5RX
MFS ch.5 reception interrupt
22
read-write
MFS5TX
MFS ch.5 transmission interrupt
23
read-write
MFS6RX
MFS ch.6 reception interrupt
24
read-write
MFS6TX
MFS ch.6 transmission interrupt
25
read-write
MFS7RX
MFS ch.7 reception interrupt
26
read-write
MFS7TX
MFS ch.7 transmission interrupt
27
read-write
USBEP1
USB ch.0 function endpoint 1 DRQ interrupt
0
read-write
USBEP2
USB ch.0 function endpoint 2 DRQ interrupt
1
read-write
USBEP3
USB ch.0 function endpoint 3 DRQ interrupt
2
read-write
USBEP4
USB ch.0 function endpoint 4 DRQ interrupt
3
read-write
USBEP5
USB ch.0 function endpoint 5 DRQ interrupt
4
read-write
EXC02MON
EXC02 batch read register [BHW]
0x200
32
read-only
n
0x0
0x0
HWINT
Interrupt request of the hardware watchdog timer
1
read-only
NMI
Interrupt request of the NMIX external pin
0
read-only
IRQ000MON
IRQ000 Batch Read Register [BHW]
0x204
32
read-only
n
0x0
0x0
FCSINT
Interrupt request of the anomalous frequency detected by the CSV
0
read-only
IRQ001MON
IRQ001 Batch Read Register [BHW]
0x208
32
read-only
n
0x0
0x0
SWWDTINT
interrupt request of the software watchdog timer
0
read-only
IRQ002MON
IRQ002 Batch Read Register [BHW]
0x20C
32
read-only
n
0x0
0x0
LVDINT
Low-voltage detection (LVD) interrupt request
0
read-only
IRQ003MON
IRQ003 Batch Read Register [BHW]
0x210
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ003SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ003SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ003SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ003SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ003SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ003SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ003SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ003SEL Register
7
read-only
IRQ003SEL
Relocate Interrupt Selection Register (IRQ003) [BHW]
0x110
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ004MON
IRQ004 Batch Read Register [BHW]
0x214
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ004SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ004SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ004SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ004SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ004SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ004SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ004SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ004SEL Register
7
read-only
IRQ004SEL
Relocate Interrupt Selection Register (IRQ004) [BHW]
0x114
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ005MON
IRQ005 Batch Read Register [BHW]
0x218
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ005SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ005SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ005SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ005SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ005SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ005SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ005SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ005SEL Register
7
read-only
IRQ005SEL
Relocate Interrupt Selection Register (IRQ005) [BHW]
0x118
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ006MON
IRQ006 Batch Read Register [BHW]
0x21C
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ006SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ006SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ006SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ006SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ006SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ006SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ006SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ006SEL Register
7
read-only
IRQ006SEL
Relocate Interrupt Selection Register (IRQ006) [BHW]
0x11C
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ007MON
IRQ007 Batch Read Register [BHW]
0x220
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ007SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ007SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ007SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ007SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ007SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ007SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ007SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ007SEL Register
7
read-only
IRQ007SEL
Relocate Interrupt Selection Register (IRQ007) [BHW]
0x120
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ008MON
IRQ008 Batch Read Register [BHW]
0x224
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ008SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ008SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ008SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ008SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ008SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ008SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ008SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ008SEL Register
7
read-only
IRQ008SEL
Relocate Interrupt Selection Register (IRQ008) [BHW]
0x124
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ009MON
IRQ009 Batch Read Register [BHW]
0x228
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ009SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ009SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ009SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ009SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ009SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ009SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ009SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ009SEL Register
7
read-only
IRQ009SEL
Relocate Interrupt Selection Register (IRQ009) [BHW]
0x128
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ010MON
IRQ010 Batch Read Register [BHW]
0x22C
32
read-only
n
0x0
0x0
IRQBIT0
interrupt request of the interrupt selected in bit0 of IRQ010SEL Register
0
read-only
IRQBIT1
interrupt request of the interrupt selected in bit1 of IRQ010SEL Register
1
read-only
IRQBIT2
interrupt request of the interrupt selected in bit2 of IRQ010SEL Register
2
read-only
IRQBIT3
interrupt request of the interrupt selected in bit3 of IRQ010SEL Register
3
read-only
IRQBIT4
interrupt request of the interrupt selected in bit4 of IRQ010SEL Register
4
read-only
IRQBIT5
interrupt request of the interrupt selected in bit5 of IRQ010SEL Register
5
read-only
IRQBIT6
interrupt request of the interrupt selected in bit6 of IRQ010SEL Register
6
read-only
IRQBIT7
interrupt request of the interrupt selected in bit7 of IRQ010SEL Register
7
read-only
IRQ010SEL
Relocate Interrupt Selection Register (IRQ010) [BHW]
0x12C
32
read-write
n
0x0
0x0
SELBIT0
Bit0 of the interrupt source is moved to bit0 of the relocate interrupt
16
read-write
SELBIT1
Bit1 of the interrupt source is moved to bit1 of the relocate interrupt
17
read-write
SELBIT10
Bit10 of the interrupt source is moved to bit10 of the relocate interrupt
26
read-write
SELBIT11
Bit11 of the interrupt source is moved to bit11 of the relocate interrupt
27
read-write
SELBIT12
Bit12 of the interrupt source is moved to bit12 of the relocate interrupt
28
read-write
SELBIT13
Bit13 of the interrupt source is moved to bit13 of the relocate interrupt
29
read-write
SELBIT14
Bit14 of the interrupt source is moved to bit14 of the relocate interrupt
30
read-write
SELBIT15
Bit15 of the interrupt source is moved to bit15 of the relocate interrupt
31
read-write
SELBIT2
Bit2 of the interrupt source is moved to bit2 of the relocate interrupt
18
read-write
SELBIT3
Bit3 of the interrupt source is moved to bit3 of the relocate interrupt
19
read-write
SELBIT4
Bit4 of the interrupt source is moved to bit4 of the relocate interrupt
20
read-write
SELBIT5
Bit5 of the interrupt source is moved to bit5 of the relocate interrupt
21
read-write
SELBIT6
Bit6 of the interrupt source is moved to bit6 of the relocate interrupt
22
read-write
SELBIT7
Bit7 of the interrupt source is moved to bit7 of the relocate interrupt
23
read-write
SELBIT8
Bit8 of the interrupt source is moved to bit8 of the relocate interrupt
24
read-write
SELBIT9
Bit9 of the interrupt source is moved to bit9 of the relocate interrupt
25
read-write
SELIRQ
specify the IRQ no. of a peripheral interrupt to be relocated
0
7
read-write
IRQ011MON
IRQ011 Batch Read Register [BHW]
0x230
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.0
0
read-only
IRQ012MON
IRQ012 Batch Read Register [BHW]
0x234
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.1
0
read-only
IRQ013MON
IRQ013 Batch Read Register [BHW]
0x238
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.2
0
read-only
IRQ014MON
IRQ014 Batch Read Register [BHW]
0x23C
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.3
0
read-only
IRQ015MON
IRQ015 Batch Read Register [BHW]
0x240
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.4
0
read-only
IRQ016MON
IRQ016 Batch Read Register [BHW]
0x244
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.5
0
read-only
IRQ017MON
IRQ017 Batch Read Register [BHW]
0x248
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.6
0
read-only
IRQ018MON
IRQ018 Batch Read Register [BHW]
0x24C
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.7
0
read-only
IRQ019MON
IRQ019 Batch Read Register [BHW]
0x250
32
read-only
n
0x0
0x0
QPRCINT0
PC match interrupt request of QPRC ch.0
0
read-only
QPRCINT1
PC and RC match interrupt request of QPRC ch.0
1
read-only
QPRCINT2
Overflow / underflow / zero index interrupt request of QPRC ch.0
2
read-only
QPRCINT3
Count inversion interrupt request of QPRC ch.0
3
read-only
QPRCINT4
Out-of-range interrupt request of QPRC ch.0
4
read-only
QPRCINT5
PC match and RC match interrupt request of QPRC ch.0
5
read-only
IRQ020MON
IRQ020 Batch Read Register [BHW]
0x254
32
read-only
n
0x0
0x0
QPRCINT0
PC match interrupt request of QPRC ch.1
0
read-only
QPRCINT1
PC and RC match interrupt request of QPRC ch.1
1
read-only
QPRCINT2
Overflow / underflow / zero index interrupt request of QPRC ch.1
2
read-only
QPRCINT3
Count inversion interrupt request of QPRC ch.1
3
read-only
QPRCINT4
Out-of-range interrupt request of QPRC ch.1
4
read-only
QPRCINT5
PC match and RC match interrupt request of QPRC ch.1
5
read-only
IRQ021MON
IRQ021 Batch Read Register [BHW]
0x258
32
read-only
n
0x0
0x0
WAVEINT0
Interrupt request of the DTIF (motor emergency stop) of the MFT unit 0
0
read-only
WAVEINT1
Interrupt request of WFG timer 10 of the MFT unit 0
1
read-only
WAVEINT2
Interrupt request of WFG timer 32 of the MFT unit 0
2
read-only
WAVEINT3
Interrupt request of WFG timer 54 of the MFT unit 0
3
read-only
IRQ022MON
IRQ022 Batch Read Register [BHW]
0x25C
32
read-only
n
0x0
0x0
WAVEINT0
Interrupt request of the DTIF (motor emergency stop) of the MFT unit 1
0
read-only
WAVEINT1
Interrupt request of WFG timer 10 of the MFT unit 1
1
read-only
WAVEINT2
Interrupt request of WFG timer 32 of the MFT unit 1
2
read-only
WAVEINT3
Interrupt request of WFG timer 54 of the MFT unit 1
3
read-only
IRQ023MON
IRQ023 Batch Read Register [BHW]
0x260
32
read-only
n
0x0
0x0
WAVEINT0
Interrupt request of the DTIF (motor emergency stop) of the MFT unit 2
0
read-only
WAVEINT1
Interrupt request of WFG timer 10 of the MFT unit 2
1
read-only
WAVEINT2
Interrupt request of WFG timer 32 of the MFT unit 2
2
read-only
WAVEINT3
Interrupt request of WFG timer 54 of the MFT unit 2
3
read-only
IRQ024MON
IRQ024 Batch Read Register [BHW]
0x264
32
read-only
n
0x0
0x0
FRT_PEAK_INT0
FRT ch.0 peak value detection interrupt request of the MFT unit 0
0
read-only
FRT_PEAK_INT1
FRT ch.1 peak value detection interrupt request of the MFT unit 0
1
read-only
FRT_PEAK_INT2
FRT ch.2 peak value detection interrupt request of the MFT unit 0
2
read-only
IRQ025MON
IRQ025 Batch Read Register [BHW]
0x268
32
read-only
n
0x0
0x0
FRT_ZERO_INT0
FRT ch.0 zero detection interrupt request of the MFT unit 0
0
read-only
FRT_ZERO_INT1
FRT ch.1 zero detection interrupt request of the MFT unit 0
1
read-only
FRT_ZERO_INT2
FRT ch.2 zero detection interrupt request of the MFT unit 0
2
read-only
IRQ026MON
IRQ026 Batch Read Register [BHW]
0x26C
32
read-only
n
0x0
0x0
ICUINT0
ICU ch.0 input edge detection interrupt request of the MFT unit 0
0
read-only
ICUINT1
ICU ch.1 input edge detection interrupt request of the MFT unit 0
1
read-only
ICUINT2
ICU ch.2 input edge detection interrupt request of the MFT unit 0
2
read-only
ICUINT3
ICU ch.3 input edge detection interrupt request of the MFT unit 0
3
read-only
IRQ027MON
IRQ027 Batch Read Register [BHW]
0x270
32
read-only
n
0x0
0x0
OCUINT0
OCU ch.0 match detection interrupt request of the MFT unit 0
0
read-only
OCUINT1
OCU ch.1 match detection interrupt request of the MFT unit 0
1
read-only
OCUINT2
OCU ch.2 match detection interrupt request of the MFT unit 0
2
read-only
OCUINT3
OCU ch.3 match detection interrupt request of the MFT unit 0
3
read-only
OCUINT4
OCU ch.4 match detection interrupt request of the MFT unit 0
4
read-only
OCUINT5
OCU ch.5 match detection interrupt request of the MFT unit 0
5
read-only
IRQ028MON
IRQ028 Batch Read Register [BHW]
0x274
32
read-only
n
0x0
0x0
FRT_PEAK_INT0
FRT ch.0 peak value detection interrupt request of the MFT unit 1
0
read-only
FRT_PEAK_INT1
FRT ch.1 peak value detection interrupt request of the MFT unit 1
1
read-only
FRT_PEAK_INT2
FRT ch.2 peak value detection interrupt request of the MFT unit 1
2
read-only
IRQ029MON
IRQ029 Batch Read Register [BHW]
0x278
32
read-only
n
0x0
0x0
FRT_ZERO_INT0
FRT ch.0 zero detection interrupt request of the MFT unit 1
0
read-only
FRT_ZERO_INT1
FRT ch.1 zero detection interrupt request of the MFT unit 1
1
read-only
FRT_ZERO_INT2
FRT ch.2 zero detection interrupt request of the MFT unit 1
2
read-only
IRQ030MON
IRQ030 Batch Read Register [BHW]
0x27C
32
read-only
n
0x0
0x0
ICUINT0
ICU ch.0 input edge detection interrupt request of the MFT unit 1
0
read-only
ICUINT1
ICU ch.1 input edge detection interrupt request of the MFT unit 1
1
read-only
ICUINT2
ICU ch.2 input edge detection interrupt request of the MFT unit 1
2
read-only
ICUINT3
ICU ch.3 input edge detection interrupt request of the MFT unit 1
3
read-only
IRQ031MON
IRQ031 Batch Read Register [BHW]
0x280
32
read-only
n
0x0
0x0
OCUINT0
OCU ch.0 match detection interrupt request of the MFT unit 1
0
read-only
OCUINT1
OCU ch.1 match detection interrupt request of the MFT unit 1
1
read-only
OCUINT2
OCU ch.2 match detection interrupt request of the MFT unit 1
2
read-only
OCUINT3
OCU ch.3 match detection interrupt request of the MFT unit 1
3
read-only
OCUINT4
OCU ch.4 match detection interrupt request of the MFT unit 1
4
read-only
OCUINT5
OCU ch.5 match detection interrupt request of the MFT unit 1
5
read-only
IRQ032MON
IRQ032 Batch Read Register [BHW]
0x284
32
read-only
n
0x0
0x0
FRT_PEAK_INT0
FRT ch.0 peak value detection interrupt request of the MFT unit 2
0
read-only
FRT_PEAK_INT1
FRT ch.1 peak value detection interrupt request of the MFT unit 2
1
read-only
FRT_PEAK_INT2
FRT ch.2 peak value detection interrupt request of the MFT unit 2
2
read-only
IRQ033MON
IRQ033 Batch Read Register [BHW]
0x288
32
read-only
n
0x0
0x0
FRT_ZERO_INT0
FRT ch.0 zero detection interrupt request of the MFT unit 2
0
read-only
FRT_ZERO_INT1
FRT ch.1 zero detection interrupt request of the MFT unit 2
1
read-only
FRT_ZERO_INT2
FRT ch.2 zero detection interrupt request of the MFT unit 2
2
read-only
IRQ034MON
IRQ034 Batch Read Register [BHW]
0x28C
32
read-only
n
0x0
0x0
ICUINT0
ICU ch.0 input edge detection interrupt request of the MFT unit 2
0
read-only
ICUINT1
ICU ch.1 input edge detection interrupt request of the MFT unit 2
1
read-only
ICUINT2
ICU ch.2 input edge detection interrupt request of the MFT unit 2
2
read-only
ICUINT3
ICU ch.3 input edge detection interrupt request of the MFT unit 2
3
read-only
IRQ035MON
IRQ035 Batch Read Register [BHW]
0x290
32
read-only
n
0x0
0x0
OCUINT0
OCU ch.0 match detection interrupt request of the MFT unit 2
0
read-only
OCUINT1
OCU ch.1 match detection interrupt request of the MFT unit 2
1
read-only
OCUINT2
OCU ch.2 match detection interrupt request of the MFT unit 2
2
read-only
OCUINT3
OCU ch.3 match detection interrupt request of the MFT unit 2
3
read-only
OCUINT4
OCU ch.4 match detection interrupt request of the MFT unit 2
4
read-only
OCUINT5
OCU ch.5 match detection interrupt request of the MFT unit 2
5
read-only
IRQ036MON
IRQ036 Batch Read Register [BHW]
0x294
32
read-only
n
0x0
0x0
PPGINT0
Interrupt request of the PPG ch.0
0
read-only
PPGINT1
Interrupt request of the PPG ch.2
1
read-only
PPGINT2
Interrupt request of the PPG ch.4
2
read-only
IRQ037MON
IRQ037 Batch Read Register [BHW]
0x298
32
read-only
n
0x0
0x0
PPGINT0
Interrupt request of the PPG ch.8
0
read-only
PPGINT1
Interrupt request of the PPG ch.10
1
read-only
PPGINT2
Interrupt request of the PPG ch.12
2
read-only
IRQ038MON
IRQ038 Batch Read Register [BHW]
0x29C
32
read-only
n
0x0
0x0
PPGINT0
Interrupt request of the PPG ch.16
0
read-only
PPGINT1
Interrupt request of the PPG ch.18
1
read-only
PPGINT2
Interrupt request of the PPG ch.20
2
read-only
IRQ039MON
IRQ039 Batch Read Register [BHW]
0x2A0
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.0
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.0
1
read-only
IRQ040MON
IRQ040 Batch Read Register [BHW]
0x2A4
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.1
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.1
1
read-only
IRQ041MON
IRQ041 Batch Read Register [BHW]
0x2A8
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.2
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.2
1
read-only
IRQ042MON
IRQ042 Batch Read Register [BHW]
0x2AC
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.3
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.3
1
read-only
IRQ043MON
IRQ043 Batch Read Register [BHW]
0x2B0
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.4
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.4
1
read-only
IRQ044MON
IRQ044 Batch Read Register [BHW]
0x2B4
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.5
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.5
1
read-only
IRQ045MON
IRQ045 Batch Read Register [BHW]
0x2B8
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.6
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.6
1
read-only
IRQ046MON
IRQ046 Batch Read Register [BHW]
0x2BC
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.7
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.7
1
read-only
IRQ047MON
IRQ047 Batch Read Register [BHW]
0x2C0
32
read-only
n
0x0
0x0
TIMINT1
Dual timer TIMINT1 interrupt request
0
read-only
TIMINT2
Dual timer TIMINT2 interrupt request
1
read-only
IRQ048MON
IRQ048 Batch Read Register [BHW]
0x2C4
32
read-only
n
0x0
0x0
WCINT
Interrupt request of the watch counter
0
read-only
IRQ049MON
IRQ049 Batch Read Register [BHW]
0x2C8
32
read-only
n
0x0
0x0
BMEMCS
External bus output error interrupt request
0
read-only
IRQ050MON
IRQ050 Batch Read Register [BHW]
0x2CC
32
read-only
n
0x0
0x0
RTCINT
Interrupt request of the RTC$
0
read-only
IRQ051MON
IRQ051 Batch Read Register [BHW]
0x2D0
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.8
0
read-only
IRQ052MON
IRQ052 Batch Read Register [BHW]
0x2D4
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.9
0
read-only
IRQ053MON
IRQ053 Batch Read Register [BHW]
0x2D8
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.10
0
read-only
IRQ054MON
IRQ054 Batch Read Register [BHW]
0x2DC
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.11
0
read-only
IRQ055MON
IRQ055 Batch Read Register [BHW]
0x2E0
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.12
0
read-only
IRQ056MON
IRQ056 Batch Read Register [BHW]
0x2E4
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.13
0
read-only
IRQ057MON
IRQ057 Batch Read Register [BHW]
0x2E8
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.14
0
read-only
IRQ058MON
IRQ058 Batch Read Register [BHW]
0x2EC
32
read-only
n
0x0
0x0
EXTINT
Interrupt request of the external pin interrupt ch.15
0
read-only
IRQ059MON
IRQ059 Batch Read Register [BHW]
0x2F0
32
read-only
n
0x0
0x0
IPLLINT
PLL of I2S oscillation stabilization wait completion interrupt
4
read-only
MOSCINT
Main clock oscillation stabilization wait completion interrupt
0
read-only
MPLLINT
Main PLL oscillation stabilization wait completion interrupt
2
read-only
SOSCINT
Sub clock oscillation stabilization wait completion interrupt
1
read-only
UPLLINT
PLL of USB / Ethernet oscillation stabilization wait completion interrupt
3
read-only
IRQ060MON
IRQ060 Batch Read Register [BHW]
0x2F4
32
read-only
n
0x0
0x0
MFSINT0_RX
Reception interrupt request of the MFS ch.0
0
read-only
IRQ061MON
IRQ061 Batch Read Register [BHW]
0x2F8
32
read-only
n
0x0
0x0
MFSINT0_STATUS
Status interrupt request of the MFS ch.0
1
read-only
MFSINT0_TX
Transmission interrupt request of the MFS ch.0
0
read-only
IRQ062MON
IRQ062 Batch Read Register [BHW]
0x2FC
32
read-only
n
0x0
0x0
MFSINT1_RX
Reception interrupt request of the MFS ch.1
0
read-only
IRQ063MON
IRQ063 Batch Read Register [BHW]
0x300
32
read-only
n
0x0
0x0
MFSINT1_STATUS
Status interrupt request of the MFS ch.1
1
read-only
MFSINT1_TX
Transmission interrupt request of the MFS ch.1
0
read-only
IRQ064MON
IRQ064 Batch Read Register [BHW]
0x304
32
read-only
n
0x0
0x0
MFSINT2_RX
Reception interrupt request of the MFS ch.2
0
read-only
IRQ065MON
IRQ065 Batch Read Register [BHW]
0x308
32
read-only
n
0x0
0x0
MFSINT2_STATUS
Status interrupt request of the MFS ch.2
1
read-only
MFSINT2_TX
Transmission interrupt request of the MFS ch.2
0
read-only
IRQ066MON
IRQ066 Batch Read Register [BHW]
0x30C
32
read-only
n
0x0
0x0
MFSINT3_RX
Reception interrupt request of the MFS ch.3
0
read-only
IRQ067MON
IRQ067 Batch Read Register [BHW]
0x310
32
read-only
n
0x0
0x0
MFSINT3_STATUS
Status interrupt request of the MFS ch.3
1
read-only
MFSINT3_TX
Transmission interrupt request of the MFS ch.3
0
read-only
IRQ068MON
IRQ068 Batch Read Register [BHW]
0x314
32
read-only
n
0x0
0x0
MFSINT4_RX
Reception interrupt request of the MFS ch.4
0
read-only
IRQ069MON
IRQ069 Batch Read Register [BHW]
0x318
32
read-only
n
0x0
0x0
MFSINT4_STATUS
Status interrupt request of the MFS ch.4
1
read-only
MFSINT4_TX
Transmission interrupt request of the MFS ch.4
0
read-only
IRQ070MON
IRQ070 Batch Read Register [BHW]
0x31C
32
read-only
n
0x0
0x0
MFSINT5_RX
Reception interrupt request of the MFS ch.5
0
read-only
IRQ071MON
IRQ071 Batch Read Register [BHW]
0x320
32
read-only
n
0x0
0x0
MFSINT5_STATUS
Status interrupt request of the MFS ch.5
1
read-only
MFSINT5_TX
Transmission interrupt request of the MFS ch.5
0
read-only
IRQ072MON
IRQ072 Batch Read Register [BHW]
0x324
32
read-only
n
0x0
0x0
MFSINT6_RX
Reception interrupt request of the MFS ch.6
0
read-only
IRQ073MON
IRQ073 Batch Read Register [BHW]
0x328
32
read-only
n
0x0
0x0
MFSINT6_STATUS
Status interrupt request of the MFS ch.6
1
read-only
MFSINT6_TX
Transmission interrupt request of the MFS ch.6
0
read-only
IRQ074MON
IRQ074 Batch Read Register [BHW]
0x32C
32
read-only
n
0x0
0x0
MFSINT7_RX
Reception interrupt request of the MFS ch.7
0
read-only
IRQ075MON
IRQ075 Batch Read Register [BHW]
0x330
32
read-only
n
0x0
0x0
MFSINT7_STATUS
Status interrupt request of the MFS ch.7
1
read-only
MFSINT7_TX
Transmission interrupt request of the MFS ch.7
0
read-only
IRQ076MON
IRQ076 Batch Read Register [BHW]
0x334
32
read-only
n
0x0
0x0
ADCINT0
Priority conversion interrupt request of the A/D converter unit 0
0
read-only
ADCINT1
Scan conversion interrupt request of the A/D converter unit 0
1
read-only
ADCINT2
FIFO overrun interrupt request of the A/D converter unit 0
2
read-only
ADCINT3
Conversion result comparison interrupt request of the A/D converter unit 0
3
read-only
ADCINT4
Range comparison result interrupt request of the A/D converter unit 0
4
read-only
IRQ077MON
IRQ077 Batch Read Register [BHW]
0x338
32
read-only
n
0x0
0x0
ADCINT0
Priority conversion interrupt request of the A/D converter unit 1
0
read-only
ADCINT1
Scan conversion interrupt request of the A/D converter unit 1
1
read-only
ADCINT2
FIFO overrun interrupt request of the A/D converter unit 1
2
read-only
ADCINT3
Conversion result comparison interrupt request of the A/D converter unit 1
3
read-only
ADCINT4
Range comparison result interrupt request of the A/D converter unit 1
4
read-only
IRQ078MON
IRQ078 Batch Read Register [BHW]
0x33C
32
read-only
n
0x0
0x0
USB_DRQ_INT0
Endpoint 1 DRQ interrupt request of the USB ch.0
0
read-only
USB_DRQ_INT1
Endpoint 2 DRQ interrupt request of the USB ch.0
1
read-only
USB_DRQ_INT2
Endpoint 3 DRQ interrupt request of the USB ch.0
2
read-only
USB_DRQ_INT3
Endpoint 4 DRQ interrupt request of the USB ch.0
3
read-only
USB_DRQ_INT4
Endpoint 5 DRQ interrupt request of the USB ch.0
4
read-only
IRQ079MON
IRQ079 Batch Read Register [BHW]
0x340
32
read-only
n
0x0
0x0
USB_INT0
Endpoint 0 DRQI interrupt request of the USB ch.0
0
read-only
USB_INT1
Endpoint 0 DRQO interrupt request of the USB ch.0
1
read-only
USB_INT2
SUSP/SOF/BRST/CONF/WKUP interrupt request of the USB ch.0
2
read-only
USB_INT3
SPK interrupt request of the USB ch.0
3
read-only
USB_INT4
DIRQ/URPIRQ/RWKIRQ/CNNIRQ interrupt request of the USB ch.0
4
read-only
USB_INT5
SOFIRQ/CMPIRQ interrupt request of the USB ch.0
5
read-only
IRQ080MON
IRQ080 Batch Read Register [BHW]
0x344
32
read-only
n
0x0
0x0
CANINT
Interrupt request of the CAN ch.0
0
read-only
IRQ081MON
IRQ081 Batch Read Register [BHW]
0x348
32
read-only
n
0x0
0x0
CAN0INT
CAN-FD 0 interrupt request
3
read-only
CAN1INT
CAN-FD 1 interrupt request
4
read-only
CANDEINT
Double bit error interrupt request of the CAN-FD
1
read-only
CANINT
Interrupt request of the CAN ch.1
0
read-only
CANSEINT
Single bit error interrupt request of the CAN-FD
2
read-only
IRQ082MON
IRQ082 Batch Read Register [BHW]
0x34C
32
read-only
n
0x0
0x0
MACLPI
LPI interrupt request of the Ethernet MAC
2
read-only
MACPMT
PMT interrupt request of the Ethernet MAC
1
read-only
MACSBD
SBD interrupt request of the Ethernet MAC
0
read-only
IRQ083MON
IRQ083 Batch Read Register [BHW]
0x350
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.0
0
read-only
IRQ084MON
IRQ084 Batch Read Register [BHW]
0x354
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.1
0
read-only
IRQ085MON
IRQ085 Batch Read Register [BHW]
0x358
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.2
0
read-only
IRQ086MON
IRQ086 Batch Read Register [BHW]
0x35C
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.3
0
read-only
IRQ087MON
IRQ087 Batch Read Register [BHW]
0x360
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.4
0
read-only
IRQ088MON
IRQ088 Batch Read Register [BHW]
0x364
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.5
0
read-only
IRQ089MON
IRQ089 Batch Read Register [BHW]
0x368
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.6
0
read-only
IRQ090MON
IRQ090 Batch Read Register [BHW]
0x36C
32
read-only
n
0x0
0x0
DMACINT
Interrupt request of the DMAC ch.7
0
read-only
IRQ091MON
IRQ091 Batch Read Register [BHW]
0x370
32
read-only
n
0x0
0x0
DSTCINT0
DSTC SWINT interrupt request
0
read-only
DSTCINT1
DSTC ERINT interrupt request
1
read-only
IRQ092MON
IRQ092 Batch Read Register [BHW]
0x374
32
read-only
n
0x0
0x0
EXTINT0
Interrupt request of the external pin interrupt ch.16
0
read-only
EXTINT1
Interrupt request of the external pin interrupt ch.17
1
read-only
EXTINT2
Interrupt request of the external pin interrupt ch.18
2
read-only
EXTINT3
Interrupt request of the external pin interrupt ch.19
3
read-only
IRQ093MON
IRQ093 Batch Read Register [BHW]
0x378
32
read-only
n
0x0
0x0
EXTINT0
Interrupt request of the external pin interrupt ch.20
0
read-only
EXTINT1
Interrupt request of the external pin interrupt ch.21
1
read-only
EXTINT2
Interrupt request of the external pin interrupt ch.22
2
read-only
EXTINT3
Interrupt request of the external pin interrupt ch.23
3
read-only
IRQ094MON
IRQ094 Batch Read Register [BHW]
0x37C
32
read-only
n
0x0
0x0
EXTINT0
Interrupt request of the external pin interrupt ch.24
0
read-only
EXTINT1
Interrupt request of the external pin interrupt ch.25
1
read-only
EXTINT2
Interrupt request of the external pin interrupt ch.26
2
read-only
EXTINT3
Interrupt request of the external pin interrupt ch.27
3
read-only
IRQ095MON
IRQ095 Batch Read Register [BHW]
0x380
32
read-only
n
0x0
0x0
EXTINT0
Interrupt request of the external pin interrupt ch.28
0
read-only
EXTINT1
Interrupt request of the external pin interrupt ch.29
1
read-only
EXTINT2
Interrupt request of the external pin interrupt ch.30
2
read-only
EXTINT3
Interrupt request of the external pin interrupt ch.31
3
read-only
IRQ096MON
IRQ096 Batch Read Register [BHW]
0x384
32
read-only
n
0x0
0x0
QPRCINT0
PC match interrupt request of QPRC ch.2
0
read-only
QPRCINT1
PC and RC match interrupt request of QPRC ch.2
1
read-only
QPRCINT2
Overflow / underflow / zero index interrupt request of QPRC ch.2
2
read-only
QPRCINT3
Count inversion interrupt request of QPRC ch.2
3
read-only
QPRCINT4
Out-of-range interrupt request of QPRC ch.2
4
read-only
QPRCINT5
PC match and RC match interrupt request of QPRC ch.2
5
read-only
IRQ097MON
IRQ097 Batch Read Register [BHW]
0x388
32
read-only
n
0x0
0x0
QPRCINT0
PC match interrupt request of QPRC ch.3
0
read-only
QPRCINT1
PC and RC match interrupt request of QPRC ch.3
1
read-only
QPRCINT2
Overflow / underflow / zero index interrupt request of QPRC ch.3
2
read-only
QPRCINT3
Count inversion interrupt request of QPRC ch.3
3
read-only
QPRCINT4
Out-of-range interrupt request of QPRC ch.3
4
read-only
QPRCINT5
PC match and RC match interrupt request of QPRC ch.3
5
read-only
IRQ098MON
IRQ098 Batch Read Register [BHW]
0x38C
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.8
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.8
1
read-only
IRQ099MON
IRQ099 Batch Read Register [BHW]
0x390
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.9
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.9
1
read-only
IRQ100MON
IRQ100 Batch Read Register [BHW]
0x394
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.10
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.10
1
read-only
IRQ101MON
IRQ101 Batch Read Register [BHW]
0x398
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.11
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.11
1
read-only
IRQ102MON
IRQ102 Batch Read Register [BHW]
0x39C
32
read-only
n
0x0
0x0
BTINT0
Interrupt request of source 0 (IRQ0) of the base timer ch.12
0
read-only
BTINT1
Interrupt request of source 1 (IRQ1) of the base timer ch.12
1
read-only
BTINT2
Interrupt request of source 0 (IRQ0) of the base timer ch.13
2
read-only
BTINT3
Interrupt request of source 1 (IRQ1) of the base timer ch.13
3
read-only
BTINT4
Interrupt request of source 0 (IRQ0) of the base timer ch.14
4
read-only
BTINT5
Interrupt request of source 1 (IRQ1) of the base timer ch.14
5
read-only
BTINT6
Interrupt request of source 0 (IRQ0) of the base timer ch.15
6
read-only
BTINT7
Interrupt request of source 1 (IRQ1) of the base timer ch.15
7
read-only
IRQ103MON
IRQ103 Batch Read Register [BHW]
0x3A0
32
read-only
n
0x0
0x0
MFSINT8_RX
Reception interrupt request of the MFS ch.8
0
read-only
IRQ104MON
IRQ104 Batch Read Register [BHW]
0x3A4
32
read-only
n
0x0
0x0
MFSINT8_STATUS
Status interrupt request of the MFS ch.8
1
read-only
MFSINT8_TX
Transmission interrupt request of the MFS ch.8
0
read-only
IRQ105MON
IRQ105 Batch Read Register [BHW]
0x3A8
32
read-only
n
0x0
0x0
MFSINT9_RX
Reception interrupt request of the MFS ch.9
0
read-only
IRQ106MON
IRQ106 Batch Read Register [BHW]
0x3AC
32
read-only
n
0x0
0x0
MFSINT9_STATUS
Status interrupt request of the MFS ch.9
1
read-only
MFSINT9_TX
Transmission interrupt request of the MFS ch.9
0
read-only
IRQ107MON
IRQ107 Batch Read Register [BHW]
0x3B0
32
read-only
n
0x0
0x0
MFSINT10_RX
Reception interrupt request of the MFS ch.10
0
read-only
IRQ108MON
IRQ108 Batch Read Register [BHW]
0x3B4
32
read-only
n
0x0
0x0
MFSINT10_STATUS
Status interrupt request of the MFS ch.10
1
read-only
MFSINT10_TX
Transmission interrupt request of the MFS ch.10
0
read-only
IRQ109MON
IRQ109 Batch Read Register [BHW]
0x3B8
32
read-only
n
0x0
0x0
MFSINT11_RX
Reception interrupt request of the MFS ch.11
0
read-only
IRQ110MON
IRQ110 Batch Read Register [BHW]
0x3BC
32
read-only
n
0x0
0x0
MFSINT11_STATUS
Status interrupt request of the MFS ch.11
1
read-only
MFSINT11_TX
Transmission interrupt request of the MFS ch.11
0
read-only
IRQ111MON
IRQ111 Batch Read Register [BHW]
0x3C0
32
read-only
n
0x0
0x0
ADCINT0
Priority conversion interrupt request of the A/D converter unit 2
0
read-only
ADCINT1
Scan conversion interrupt request of the A/D converter unit 2
1
read-only
ADCINT2
FIFO overrun interrupt request of the A/D converter unit 2
2
read-only
ADCINT3
Conversion result comparison interrupt request of the A/D converter unit 2
3
read-only
ADCINT4
Range comparison result interrupt request of the A/D converter unit 2
4
read-only
IRQ112MON
IRQ112 Batch Read Register [BHW]
0x3C4
32
read-only
n
0x0
0x0
CANDINT
Interrupt request of DSTC transfer end interrupt of CAN-FD
5
read-only
HSSPIDINT0
Interrupt request of DSTC transfer end interrupt of Quad SPI(reception)
2
read-only
HSSPIDINT1
Interrupt request of DSTC transfer end interrupt of Quad SPI(transmission)
3
read-only
I2SDINT0
Interrupt request of DSTC transfer end interrupt of I2S(reception)
0
read-only
I2SDINT1
Interrupt request of DSTC transfer end interrupt of I2S(transmission)
1
read-only
PCRCDINT
Interrupt request of DSTC transfer end interrupt of Programmable CRC
4
read-only
IRQ113MON
IRQ113 Batch Read Register [BHW]
0x3C8
32
read-only
n
0x0
0x0
RCEC0INT
HDMI-CEC remote control reception ch.0 interrupt request
5
read-only
USB_DRQ_INT0
Endpoint 1 DRQ interrupt request of the USB ch.1
0
read-only
USB_DRQ_INT1
Endpoint 2 DRQ interrupt request of the USB ch.1
1
read-only
USB_DRQ_INT2
Endpoint 3 DRQ interrupt request of the USB ch.1
2
read-only
USB_DRQ_INT3
Endpoint 4 DRQ interrupt request of the USB ch.1
3
read-only
USB_DRQ_INT4
Endpoint 5 DRQ interrupt request of the USB ch.1
4
read-only
IRQ114MON
IRQ114 Batch Read Register [BHW]
0x3CC
32
read-only
n
0x0
0x0
RCEC1INT
HDMI-CEC remote control reception ch.1 interrupt request
6
read-only
USB_INT0
Endpoint 0 DRQI interrupt request of the USB ch.1
0
read-only
USB_INT1
Endpoint 0 DRQO interrupt request of the USB ch.1
1
read-only
USB_INT2
SUSP/SOF/BRST/CONF/WKUP interrupt request of the USB ch.1
2
read-only
USB_INT3
SPK interrupt request of the USB ch.1
3
read-only
USB_INT4
DIRQ/URPIRQ/RWKIRQ/CNNIRQ interrupt request of the USB ch.1
4
read-only
USB_INT5
SOFIRQ/CMPIRQ interrupt request of the USB ch.1
5
read-only
IRQ115MON
IRQ115 Batch Read Register [BHW]
0x3D0
32
read-only
n
0x0
0x0
HSSPIINT0
Interrupt request of reception interrupt of Hi-Speed Quad SPI
0
read-only
HSSPIINT1
Interrupt request of transmission interrupt of Hi-Speed Quad SPI
1
read-only
HSSPIINT2
Interrupt request of fault detection interrupt of Hi-Speed Quad SPI
2
read-only
IRQ116MON
IRQ116 Batch Read Register [BHW]
0x3D4
32
read-only
n
0x0
0x0
IRQ117MON
IRQ117 Batch Read Register [BHW]
0x3D8
32
read-only
n
0x0
0x0
I2SINT
Interrupt request of I2S
0
read-only
PCRC
Interrupt request of Programmable CRC
1
read-only
IRQ118MON
IRQ118 Batch Read Register [BHW]
0x3DC
32
read-only
n
0x0
0x0
SDINT0
Interrupt request of aggregation of all SD I/F interrupt sources
0
read-only
SDINT1
SD card interrupt request
1
read-only
IRQ119MON
IRQ119 Batch Read Register [BHW]
0x3E0
32
read-only
n
0x0
0x0
FLINT
Interrupt request of the Flash I/F
0
read-only
IRQ120MON
IRQ120 Batch Read Register [BHW]
0x3E4
32
read-only
n
0x0
0x0
MFSINT12_RX
Reception interrupt request of the MFS ch.12
0
read-only
IRQ121MON
IRQ121 Batch Read Register [BHW]
0x3E8
32
read-only
n
0x0
0x0
MFSINT12_STATUS
Status interrupt request of the MFS ch.12
1
read-only
MFSINT12_TX
Transmission interrupt request of the MFS ch.12
0
read-only
IRQ122MON
IRQ122 Batch Read Register [BHW]
0x3EC
32
read-only
n
0x0
0x0
MFSINT13_RX
Reception interrupt request of the MFS ch.13
0
read-only
IRQ123MON
IRQ123 Batch Read Register [BHW]
0x3F0
32
read-only
n
0x0
0x0
MFSINT13_STATUS
Status interrupt request of the MFS ch.13
1
read-only
MFSINT13_TX
Transmission interrupt request of the MFS ch.13
0
read-only
IRQ124MON
IRQ124 Batch Read Register [BHW]
0x3F4
32
read-only
n
0x0
0x0
MFSINT14_RX
Reception interrupt request of the MFS ch.14
0
read-only
IRQ125MON
IRQ125 Batch Read Register [BHW]
0x3F8
32
read-only
n
0x0
0x0
MFSINT14_STATUS
Status interrupt request of the MFS ch.14
1
read-only
MFSINT14_TX
Transmission interrupt request of the MFS ch.14
0
read-only
IRQ126MON
IRQ126 Batch Read Register [BHW]
0x3FC
32
read-only
n
0x0
0x0
MFSINT15_RX
Reception interrupt request of the MFS ch.15
0
read-only
IRQ127MON
IRQ127 Batch Read Register [BHW]
0x400
32
read-only
n
0x0
0x0
MFSINT15_STATUS
Status interrupt request of the MFS ch.15
1
read-only
MFSINT15_TX
Transmission interrupt request of the MFS ch.15
0
read-only
ODDPKS
USB ch.0 Odd Packet Size DMA Enable Register [B]
0x10
8
read-write
n
0x0
0x0
ODDPKS0
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP1DT
0
read-write
ODDPKS1
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP2DT
1
read-write
ODDPKS2
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP3DT
2
read-write
ODDPKS3
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP4DT
3
read-write
ODDPKS4
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP5DT
4
read-write
ODDPKS1
USB ch.1 Odd Packet Size DMA Enable Register [B]
0x14
8
read-write
n
0x0
0x0
ODDPKS10
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP1DT
0
read-write
ODDPKS11
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP2DT
1
read-write
ODDPKS12
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP3DT
2
read-write
ODDPKS13
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP4DT
3
read-write
ODDPKS14
The bit width of the last transfer data is converted to Byte if the transfer destination address of DMAC is USB.EP5DT
4
read-write
LSCRP
Low-speed CR Prescaler
LSCRP
0x0
0x0
0x1
registers
n
LCR_PRSLD
Low-speed CR Prescaler Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
LCR_PRSLD
Low-speed CR Prescaler Load
0
5
read-write
LVD
Low-voltage Detection
LVD
0x0
0x0
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
0xC
0x5
registers
n
LVD
2
CLR
Low-voltage Detection Interrupt Factor Clear Register [BHW]
0x8
8
read-write
n
0x0
0x0
LVDCL
Low-voltage detection interrupt factor clear bit
7
read-write
CTL
Low-voltage Detection Voltage Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
LVDIE
Low-voltage detection interrupt enable bit
7
read-write
SVHI
Low-voltage detection interrupt voltage setting bits
2
4
read-write
RLR
Low-voltage Detection Voltage Protection Register [W]
0xC
32
read-write
n
0x0
0x0
LVDLCK
Low-voltage Detection Voltage Control Register protection bits
0
31
read-write
STR
Low-voltage Detection Interrupt Factor Register [BHW]
0x4
8
read-only
n
0x0
0x0
LVDIR
Low-voltage detection interrupt factor bit
7
read-only
STR2
Low-voltage Detection Circuit Status Register [BHW]
0x10
8
read-only
n
0x0
0x0
LVDIRDY
Low-voltage detection interrupt status flag
7
read-only
MFS0
Multi-function Serial Interface 0
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS0_RX
60
MFS0_TX
61
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS1
Multi-function Serial Interface 1
MFS
0x0
0x0
0x44
registers
n
MFS1_RX
62
MFS1_TX
63
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
I2S_ESCR
Extended Communication Control Register [BHW]
I2S
0x4
8
read-write
n
0x0
0x0
L
Data length select bits
0
2
read-write
L3
Data length select bit 3
6
read-write
SOP
Serial output pin set bit
7
read-write
I2S_FBYTE1
FIFO Byte Register 1 [BHW]
I2S
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2S_FBYTE2
FIFO Byte Register 2 [BHW]
I2S
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2S_FCR
FIFO Control Register 0 [BHW]
I2S
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FSEL
FIFO select bit
8
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2S_RDR
Received Data Register [HW]
I2S
0x8
32
read-only
n
0x0
0x0
I2S_SCR
Serial Control Register [BHW]
I2S
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
I2S_SMR
Serial Mode Register [BHW]
I2S
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Oeration mode set bits
5
2
read-write
SOE
Serial data output enable bit
0
read-write
I2S_SSR
Serial Status Register [BHW]
I2S
0x5
8
read-write
n
0x0
0x0
AWC
FIFO access width set
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TDRE
Transmit data empty flag bit
1
read-only
I2S_TDR
Transmit Data Register [HW]
I2S
0x8
32
write-only
n
0x0
0x0
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS2
Multi-function Serial Interface 2
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS2_RX
64
MFS2_TX
65
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS3
Multi-function Serial Interface 3
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS3_RX
66
MFS3_TX
67
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS4
Multi-function Serial Interface 4
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS4_RX
68
MFS4_TX
69
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS5
Multi-function Serial Interface 5
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS5_RX
70
MFS5_TX
71
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS6
Multi-function Serial Interface 6
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS6_RX
72
MFS6_TX
73
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS7
Multi-function Serial Interface 7
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS7_RX
74
MFS7_TX
75
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS8
Multi-function Serial Interface 8
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS8_RX
103
MFS8_TX
104
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFS9
Multi-function Serial Interface 9
MFS
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x1
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
MFS9_RX
105
MFS9_TX
106
CSIO_BGR
Baud Rate Generator Registers [BHW]
CSIO
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
CSIO_ESCR
Extended Communication Control Register [BHW]
CSIO
0x4
8
read-write
n
0x0
0x0
CSFE
Serial Chip Select Format enable bit
5
read-write
L
Data length select bits
0
2
read-write
L3
Bit3 of Data length select bits
6
read-write
SOP
Serial output pin set bit
7
read-write
WT
Data transmit/received wait select bits
3
1
read-write
CSIO_FBYTE1
FIFO Byte Register 1 [BHW]
CSIO
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FBYTE2
FIFO Byte Register 2 [BHW]
CSIO
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
CSIO_FCR
FIFO Control Register [BHW]
CSIO
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
CSIO_RDR
Received Data Register [HW]
CSIO
0x8
16
read-only
n
0x0
0x0
D
Data
0
15
read-only
CSIO_SACSR
Serial Support Control Register [BHW]
CSIO
0x24
16
read-write
n
0x0
0x0
CSE
Chip Select Error Flag
11
read-write
CSEIE
Chip Select Error Interupt Enable bit
12
read-write
TBEEN
Transfer Byte Error Enable bit
13
read-write
TDIV
Timer Operation Clock Division bit
1
3
read-write
TINT
Timer Interrupt Flag
8
read-write
TINTE
Timer Interrupt Enable bit
7
read-write
TMRE
Serial Timer Enable bit
0
read-write
TSYNE
Synchronous Transmission Enable bit
6
read-write
CSIO_SCR
Serial Control Register [BHW]
CSIO
0x1
8
read-write
n
0x0
0x0
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data received enable bit
1
read-write
SPI
SPI corresponding bit
5
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
CSIO_SCSCR
Serial Chip Select Control Status Register [BHW]
CSIO
0x30
16
read-write
n
0x0
0x0
CDIV
Serial Chip Select Timing Operation Clock Division bit
6
2
read-write
CSEN0
Serial Chip Select Enable bit with SCS0 pin
1
read-write
CSEN1
Serial Chip Select Enable bit with SCS1 pin
2
read-write
CSEN2
Serial Chip Select Enable bit with SCS2 pin
3
read-write
CSEN3
Serial Chip Select Enable bit with SCS3 pin
4
read-write
CSLVL
Serial Chip Select Level Setting bit
5
read-write
CSOE
Serial Chip Select Output Enable bit
0
read-write
SCAM
Serial Chip Select Active Hold bit
9
read-write
SCD
Serial Chip Select Active Display bit
10
1
read-write
SED
Serial Chip Select Active End bit
12
1
read-write
SST
Serial Chip Select Active Start bit
14
1
read-write
CSIO_SCSFR0
Serial Chip Select Format Register 0 [BHW]
CSIO
0x34
8
read-write
n
0x0
0x0
CS1CSLVL
Serial Chip Select 1 Level Setting bit
7
read-write
CS1L
Transfer direction select bit of Serial Chip Select 1
0
4
read-write
CS1SCINV
Serial Clock Invert bit of Serial Chip Select 1
6
read-write
CS1SPI
SPI corresponding bit of Serial Chip Select 1
5
read-write
CSIO_SCSFR1
Serial Chip Select Format Register 1 [BHW]
CSIO
0x35
8
read-write
n
0x0
0x0
CS2CSLVL
Serial Chip Select 2 Level Setting bit
7
read-write
CS2L
Transfer direction select bit of Serial Chip Select 2
0
4
read-write
CS2SCINV
Serial Clock Invert bit of Serial Chip Select 2
6
read-write
CS2SPI
SPI corresponding bit of Serial Chip Select 2
5
read-write
CSIO_SCSFR2
Serial Chip Select Format Register 2 [BHW]
CSIO
0x38
8
read-write
n
0x0
0x0
CS3CSLVL
Serial Chip Select 3 Level Setting bit
7
read-write
CS3L
Transfer direction select bit of Serial Chip Select 3
0
4
read-write
CS3SCINV
Serial Clock Invert bit of Serial Chip Select 3
6
read-write
CS3SPI
SPI corresponding bit of Serial Chip Select 3
5
read-write
CSIO_SCSTR0
Serial Chip Select Timing Register 0 [BHW]
CSIO
0x1C
8
read-write
n
0x0
0x0
CSHD
Serial Chip Select Hold Delay bits
0
7
read-write
CSIO_SCSTR1
Serial Chip Select Timing Register 1 [BHW]
CSIO
0x1D
8
read-write
n
0x0
0x0
CSSU
Serial Chip Select Setup Delay bits
0
7
read-write
CSIO_SCSTR32
Serial Chip Select Timing Registers 2/3 [BHW]
CSIO
0x20
16
read-write
n
0x0
0x0
CSDS
Serial Chip Deselect bits
0
15
read-write
CSIO_SMR
Serial Mode Register [BHW]
CSIO
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bits
5
2
read-write
SCINV
Serial clock invert bit
3
read-write
SCKE
Master mode serial clock output enable bit
1
read-write
SOE
Serial data output enable bit
0
read-write
CSIO_SSR
Serial Status Register [BHW]
CSIO
0x5
8
read-write
n
0x0
0x0
AWC
Access Width Control bit
4
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
CSIO_STMCR
Serial Timer Comparison Register [BHW]
CSIO
0x2C
16
read-write
n
0x0
0x0
TC
Compare bits
0
15
read-write
CSIO_STMR
Serial Timer Register [BHW]
CSIO
0x28
16
read-only
n
0x0
0x0
TM
Timer Data bits
0
15
read-only
CSIO_TBYTE0
Transfer Byte Register 0 [BHW]
CSIO
0x3C
8
read-write
n
0x0
0x0
CSIO_TBYTE1
Transfer Byte Register 1 [BHW]
CSIO
0x3D
8
read-write
n
0x0
0x0
CSIO_TBYTE2
Transfer Byte Register 2 [BHW]
CSIO
0x40
8
read-write
n
0x0
0x0
CSIO_TBYTE3
Transfer Byte Register 3 [BHW]
CSIO
0x41
8
read-write
n
0x0
0x0
CSIO_TDR
Transmit Data Register [HW]
CSIO
0x8
16
write-only
n
0x0
0x0
D
Data
0
15
write-only
I2C_BGR
Baud Rate Generator Registers [BHW]
I2C
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
I2C_EIBCR
Extension I2C Bus Control Register [BHW]
I2C
0x1D
8
read-write
n
0x0
0x0
BEC
Bus error control bit
0
read-write
SCLC
SCL output control bit
2
read-write
SCLS
SCL status bit
4
read-only
SDAC
SDA output control bit
3
read-write
SDAS
SDA status bit
5
read-only
SOCE
Serial output enabled bit
1
read-write
I2C_FBYTE1
FIFO Byte Register 1 [BHW]
I2C
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FBYTE2
FIFO Byte Register 2 [BHW]
I2C
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
I2C_FCR
FIFO Control Register [BHW]
I2C
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
I2C_IBCR
I2C Bus Control Register [BHW]
I2C
0x1
8
read-write
n
0x0
0x0
ACKE
Data byte acknowledge enable bit
5
read-write
ACT_SCC
Operation flag/iteration start condition generation bit
6
read-write
BER
Bus error flag bit
1
read-only
CNDE
Condition detection interrupt enable bit
3
read-write
INT
interrupt flag bit
0
read-write
INTE
Interrupt enable bit
2
read-write
MSS
Master/slave select bit
7
read-write
WSEL
Wait selection bit
4
read-write
I2C_IBSR
I2C Bus Status Register [BHW]
I2C
0x4
8
read-write
n
0x0
0x0
AL
Arbitration lost bit
3
read-only
BB
Bus state bit
0
read-only
FBT
First byte bit
7
read-only
RACK
Acknowledge flag bit
6
read-only
RSA
Reserved address detection bit
5
read-only
RSC
Iteration start condition check bit
2
read-write
SPC
Stop condition check bit
1
read-write
TRX
Data direction bit
4
read-only
I2C_ISBA
7-bit Slave Address Register [BHW]
I2C
0x10
8
read-write
n
0x0
0x0
SA
7-bit slave address
0
6
read-write
SAEN
Slave address enable bit
7
read-write
I2C_ISMK
7-bit Slave Address Mask Register [BHW]
I2C
0x11
8
read-write
n
0x0
0x0
EN
I2C interface operation enable bit
7
read-write
SM
Slave address mask bits
0
6
read-write
I2C_NFCR
Noise Filter Control Register [BHW]
I2C
0x1C
8
read-write
n
0x0
0x0
NFT
Noise Filter Time Select bits
0
4
read-write
I2C_RDR
Received Data Register [HW]
I2C
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
I2C_SMR
Serial Mode Register [BHW]
I2C
0x0
8
read-write
n
0x0
0x0
MD
operation mode set bits
5
2
read-write
RIE
Received interrupt enable bit
3
read-write
TIE
Transmit interrupt enable bit
2
read-write
I2C_SSR
Serial Status Register [BHW]
I2C
0x5
8
read-write
n
0x0
0x0
DMA
DMA mode enable bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit (Effective only when DMA mode is enabled)
0
read-only
TBIE
Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
4
read-write
TDRE
Transmit data empty flag bit
1
read-only
TSET
Transmit empty flag set bit
6
read-write
I2C_TDR
Transmit Data Register [HW]
I2C
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
LIN_BGR
Baud Rate Generator Registers [BHW]
LIN
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
LIN_ESCR
Extended Communication Control Register [BHW]
LIN
0x4
8
read-write
n
0x0
0x0
DEL
LIN Break delimiter length select bits (valid in master mode only)
0
1
read-write
ESBL
Extended stop bit length select bit
6
read-write
LBIE
LIN Break field detect interrupt enable bit
4
read-write
LBL
LIN Break field length select bits (valid in master mode only)
2
1
read-write
LIN_FBYTE1
FIFO Byte Register 1 [BHW]
LIN
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FBYTE2
FIFO Byte Register 2 [BHW]
LIN
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
LIN_FCR
FIFO Control Register [BHW]
LIN
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
LIN_RDR
Received Data Register [HW]
LIN
0x8
16
read-only
n
0x0
0x0
D
Data
0
7
read-only
LIN_SCR
Serial Control Register [BHW]
LIN
0x1
8
read-write
n
0x0
0x0
LBR
LIN Break Field setting bit (valid in master mode only)
5
read-write
MS
Master/Slave function select bit
6
read-write
RIE
Received interrupt enable bit
4
read-write
RXE
Data reception enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Data transmission enable bit
0
read-write
UPCL
Programmable clear bit
7
read-write
LIN_SMR
Serial Mode Register [BHW]
LIN
0x0
8
read-write
n
0x0
0x0
MD
Operation mode setting bits
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
WUCR
Wake-up control bit
4
read-write
LIN_SSR
Serial Status Register [BHW]
LIN
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
LBD
LIN Break field detection flag bit
5
read-write
ORE
Overrun error flag bit
3
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received Error flag clear bit
7
read-write
TBI
Transmit bus idle flag bit
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
LIN_TDR
Transmit Data Register [HW]
LIN
0x8
16
write-only
n
0x0
0x0
D
Data
0
7
write-only
UART_BGR
Baud Rate Generator Registers [BHW]
UART
0xC
16
read-write
n
0x0
0x0
BGR
Baud Rate Generator Register
0
14
read-write
EXT
External clock select bit
15
read-write
UART_ESCR
Extended Communication Control Register [BHW]
UART
0x4
8
read-write
n
0x0
0x0
ESBL
Extension stop bit length select bit
6
read-write
FLWEN
Flow control enable bit
7
read-write
INV
Inverted serial data format bit
5
read-write
L
Data length select bit
0
2
read-write
P
Parity select bit (only functions in operation mode 0)
3
read-write
PEN
Parity enable bit (only functions in operation mode 0)
4
read-write
UART_FBYTE1
FIFO Byte Register 1 [BHW]
UART
0x18
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FBYTE2
FIFO Byte Register 2 [BHW]
UART
0x19
8
read-write
n
0x0
0x0
FD
data count in FIFO
0
7
read-write
UART_FCR
FIFO Control Register [BHW]
UART
0x14
16
read-write
n
0x0
0x0
FCL1
FIFO1 reset bit
2
read-write
FCL2
FIFO2 reset bit
3
read-write
FDRQ
Transmit FIFO data request bit
10
read-write
FE1
FIFO1 operation enable bit
0
read-write
FE2
FIFO2 operation enable bit
1
read-write
FLD
FIFO pointer reload bit
5
read-write
FLST
FIFO re-transmit data lost flag bit
6
read-only
FLSTE
Re-transmission data lost detect enable bit
12
read-write
FRIIE
Received FIFO idle detection enable bit
11
read-write
FSEL
FIFO select bit
8
read-write
FSET
FIFO pointer save bit
4
read-write
FTIE
Transmit FIFO interrupt enable bit
9
read-write
UART_RDR
Received Data Register [HW]
UART
0x8
16
read-only
n
0x0
0x0
D
Data
0
8
read-only
UART_SCR
Serial Control Register [BHW]
UART
0x1
8
read-write
n
0x0
0x0
RIE
Received interrupt enable bit
4
read-write
RXE
Received operation enable bit
1
read-write
TBIE
Transmit bus idle interrupt enable bit
2
read-write
TIE
Transmit interrupt enable bit
3
read-write
TXE
Transmission operation enable bit
0
read-write
UPCL
Programmable Clear bit
7
read-write
UART_SMR
Serial Mode Register [BHW]
UART
0x0
8
read-write
n
0x0
0x0
BDS
Transfer direction select bit
2
read-write
MD
Operation mode set bit
5
2
read-write
SBL
Stop bit length select bit
3
read-write
SOE
Serial data output enable bit
0
read-write
UART_SSR
Serial Status Register [BHW]
UART
0x5
8
read-write
n
0x0
0x0
FRE
Framing error flag bit
4
read-only
ORE
Overrun error flag bit
3
read-only
PE
Parity error flag bit (only functions in operation mode 0)
5
read-only
RDRF
Received data full flag bit
2
read-only
REC
Received error flag clear bit
7
read-write
TBI
Transmit bus idle flag
0
read-only
TDRE
Transmit data empty flag bit
1
read-only
UART_TDR
Transmit Data Register [HW]
UART
0x8
16
write-only
n
0x0
0x0
D
Data
0
8
write-only
MFSI2SA
I2S0 Registers
MFSI2S
0x0
0x0
0x2
registers
n
0x4
0x2
registers
n
0x8
0x1
registers
n
0x9
0x1
registers
n
CNTLREG
Control Register [BHW]
0x0
16
read-write
n
0x0
0x0
CKOE
I2SCK and I2SWS output enable bit
6
read-write
FRAML
Frame length select bit
0
read-write
FSPL
I2SWS polarity set bit
4
read-write
I2SEN
I2S mode enable bit
5
read-write
I2SMOD
I2S mode select bit
3
read-write
I2SRUN
I2S clock generate enable bit
10
read-write
MSKB
Mask bit output bit
8
read-write
I2SCLK
I2S Clock Register [BHW]
0x4
16
read-write
n
0x0
0x0
I2SDIV
I2S clock division set bit
0
7
read-write
MCKIE
Main clock input enable bit
15
read-write
MCKOE
Main clock output enable bit
14
read-write
I2SRST
I2S Reset Register [BHW]
0x8
8
write-only
n
0x0
0x0
I2SRST
I2S software reset bit
0
7
write-only
I2SST
I2S Status Register [BHW]
0x9
8
read-only
n
0x0
0x0
BUSY
Bus busy indication for transmit bit
1
read-only
CKSTP
Clock stop indication bit
0
read-only
MFT0
Multifunction Timer 0
MFT
0x0
0x102
0x2
registers
n
0x106
0x2
registers
n
0x10A
0x2
registers
n
0x10E
0x2
registers
n
0x112
0x2
registers
n
0x116
0xE
registers
n
0x125
0x1
registers
n
0x128
0x2
registers
n
0x12C
0x6
registers
n
0x134
0x6
registers
n
0x13C
0x4
registers
n
0x142
0x2
registers
n
0x146
0x6
registers
n
0x14E
0x2
registers
n
0x152
0x6
registers
n
0x15A
0x2
registers
n
0x15E
0xD
registers
n
0x16C
0x2
registers
n
0x170
0x3
registers
n
0x176
0x2
registers
n
0x17A
0x2
registers
n
0x17E
0x2
registers
n
0x182
0x4
registers
n
0x188
0x2
registers
n
0x18E
0x6
registers
n
0x196
0x6
registers
n
0x19E
0x8
registers
n
0x1A8
0x2
registers
n
0x1AC
0x2
registers
n
0x1B0
0x2
registers
n
0x1B4
0x2
registers
n
0x1BA
0x2
registers
n
0x1BE
0x2
registers
n
0x1C2
0x2
registers
n
0x1C6
0x2
registers
n
0x1CA
0x2
registers
n
0x1CE
0x4
registers
n
0x1D4
0x3
registers
n
0x1D8
0x3
registers
n
0x1DC
0x3
registers
n
0x1E0
0x3
registers
n
0x1E4
0x3
registers
n
0x1E8
0x3
registers
n
0x1EC
0x1
registers
n
MFT0_WFG_DTIF
21
MFT0_FRT_PEAK
24
MFT0_FRT_ZERO
25
MFT0_ICU
26
MFT0_OCU
27
ADCMP_ACFS10
ADCMP ch.0/1 Connecting FRT Select Register [BHW]
ADCMP
0x170
8
read-write
n
0x0
0x0
FSA0
specify the FRT to be connected to ADCMP ch.(0)
0
3
read-write
FSA1
specify the FRT to be connected to ADCMP ch.(1)
4
3
read-write
ADCMP_ACFS32
ADCMP ch.2/3 Connecting FRT Select Register [BHW]
ADCMP
0x171
8
read-write
n
0x0
0x0
FSA2
specify the FRT to be connected to ADCMP ch.(2)
0
3
read-write
FSA3
specify the FRT to be connected to ADCMP ch.(3)
4
3
read-write
ADCMP_ACFS54
ADCMP ch.4/5 Connecting FRT Select Register [BHW]
ADCMP
0x172
8
read-write
n
0x0
0x0
FSA4
specify the FRT to be connected to ADCMP ch.(4)
0
3
read-write
FSA5
specify the FRT to be connected to ADCMP ch.(5)
4
3
read-write
ADCMP_ACMC0
ADCMP ch.0 Mask Compare Value Storage Register [BHW]
ADCMP
0x1D6
8
read-write
n
0x0
0x0
AMC
specifies the value to be compared with the FRT interrupt mask counter
0
3
read-write
MPCE
specifies whether a comparison is performed with the FRT peak interrupt mask counter
7
read-write
MZCE
specifies whether a comparison is performed with the FRT zero interrupt mask counter
6
read-write
ADCMP_ACMC1
ADCMP ch.1 Mask Compare Value Storage Register [BHW]
ADCMP
0x1DA
-1
read-write
n
0x0
0x0
ADCMP_ACMC2
ADCMP ch.2 Mask Compare Value Storage Register [BHW]
ADCMP
0x1DE
-1
read-write
n
0x0
0x0
ADCMP_ACMC3
ADCMP ch.3 Mask Compare Value Storage Register [BHW]
ADCMP
0x1E2
-1
read-write
n
0x0
0x0
ADCMP_ACMC4
ADCMP ch.4 Mask Compare Value Storage Register [BHW]
ADCMP
0x1E6
-1
read-write
n
0x0
0x0
ADCMP_ACMC5
ADCMP ch.5 Mask Compare Value Storage Register [BHW]
ADCMP
0x1EA
-1
read-write
n
0x0
0x0
ADCMP_ACMP0
ADCMP ch.0 Compare Value Store Register [HW]
ADCMP
0x1BA
16
read-write
n
0x0
0x0
ACMP
0
0
15
read-write
ADCMP_ACMP1
ADCMP ch.1 Compare Value Store Register [HW]
ADCMP
0x1BE
-1
read-write
n
0x0
0x0
ADCMP_ACMP2
ADCMP ch.2 Compare Value Store Register [HW]
ADCMP
0x1C2
-1
read-write
n
0x0
0x0
ADCMP_ACMP3
ADCMP ch.3 Compare Value Store Register [HW]
ADCMP
0x1C6
-1
read-write
n
0x0
0x0
ADCMP_ACMP4
ADCMP ch.4 Compare Value Store Register [HW]
ADCMP
0x1CA
-1
read-write
n
0x0
0x0
ADCMP_ACMP5
ADCMP ch.5 Compare Value Store Register [HW]
ADCMP
0x1CE
-1
read-write
n
0x0
0x0
ADCMP_ACSA
ADCMP Control Register A [BHW]
ADCMP
0x1D0
16
read-write
n
0x0
0x0
CE10
enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products
0
1
read-write
CE32
enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products
2
1
read-write
CE54
enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products
4
1
read-write
SEL10
selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products
8
1
read-write
SEL32
selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products
10
1
read-write
SEL54
selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products
12
1
read-write
ADCMP_ACSC0
ADCMP ch.0 Control Register C [BHW]
ADCMP
0x1D4
8
read-write
n
0x0
0x0
ADSEL
specify the destinations of ADC start signals that are output by ADCMP
2
2
read-write
APBM
sets the linked transfer with the FRT interrupt mask counter
5
read-write
BUFE
select enable/disable and transfer timing for buffer function of the ACMP register
0
1
read-write
ADCMP_ACSC1
ADCMP ch.1 Control Register C [BHW]
ADCMP
0x1D8
-1
read-write
n
0x0
0x0
ADCMP_ACSC2
ADCMP ch.2 Control Register C [BHW]
ADCMP
0x1DC
-1
read-write
n
0x0
0x0
ADCMP_ACSC3
ADCMP ch.3 Control Register C [BHW]
ADCMP
0x1E0
-1
read-write
n
0x0
0x0
ADCMP_ACSC4
ADCMP ch.4 Control Register C [BHW]
ADCMP
0x1E4
-1
read-write
n
0x0
0x0
ADCMP_ACSC5
ADCMP ch.5 Control Register C [BHW]
ADCMP
0x1E8
-1
read-write
n
0x0
0x0
ADCMP_ACSD0
ADCMP ch.0 Control Register D [BHW]
ADCMP
0x1D5
8
read-write
n
0x0
0x0
AMOD
selects operation mode for ADCMP
0
read-write
DE
enables/disables the operation of the ADCMP that is counting down for the connected FRT
4
read-write
OCUS
selects the OCU OCCP register that will become the start for offset start
1
read-write
PE
enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT
5
read-write
UE
enables/disables the operation of the ADCMP that is counting up for the connected FRT
6
read-write
ZE
enables/disables the operation of the ADCMP when the FRT is 0x0000
7
read-write
ADCMP_ACSD1
ADCMP ch.1 Control Register D [BHW]
ADCMP
0x1D9
-1
read-write
n
0x0
0x0
ADCMP_ACSD2
ADCMP ch.2 Control Register D [BHW]
ADCMP
0x1DD
-1
read-write
n
0x0
0x0
ADCMP_ACSD3
ADCMP ch.3 Control Register D [BHW]
ADCMP
0x1E1
-1
read-write
n
0x0
0x0
ADCMP_ACSD4
ADCMP ch.4 Control Register D [BHW]
ADCMP
0x1E5
-1
read-write
n
0x0
0x0
ADCMP_ACSD5
ADCMP ch.5 Control Register D [BHW]
ADCMP
0x1E9
-1
read-write
n
0x0
0x0
FRT_TCAL
FRT Simultaneous Start Control Register [W]
FRT
0x164
32
read-write
n
0x0
0x0
SCLR00
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit0
16
write-only
SCLR01
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit0
17
write-only
SCLR02
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit0
18
write-only
SCLR10
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit1
19
write-only
SCLR11
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit1
20
write-only
SCLR12
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit1
21
write-only
SCLR20
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit2
22
write-only
SCLR21
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit2
23
write-only
SCLR22
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit2
24
write-only
STOP00
Mirror register of the STOP bit located in TCSA0 register of MFT-unit0
0
read-write
STOP01
Mirror register of the STOP bit located in TCSA1 register of MFT-unit0
1
read-write
STOP02
Mirror register of the STOP bit located in TCSA2 register of MFT-unit0
2
read-write
STOP10
Mirror register of the STOP bit located in TCSA0 register of MFT-unit1
3
read-write
STOP11
Mirror register of the STOP bit located in TCSA1 register of MFT-unit1
4
read-write
STOP12
Mirror register of the STOP bit located in TCSA2 register of MFT-unit1
5
read-write
STOP20
Mirror register of the STOP bit located in TCSA0 register of MFT-unit2
6
read-write
STOP21
Mirror register of the STOP bit located in TCSA1 register of MFT-unit2
7
read-write
STOP22
Mirror register of the STOP bit located in TCSA2 register of MFT-unit2
8
read-write
FRT_TCCP0
FRT-ch.0 Cycle Setting Register [HW]
FRT
0x142
16
read-write
n
0x0
0x0
TCCP
Count Cycle Setting Bits
0
15
read-write
FRT_TCCP1
FRT-ch.1 Cycle Setting Register [HW]
FRT
0x14E
-1
read-write
n
0x0
0x0
FRT_TCCP2
FRT-ch.2 Cycle Setting Register [HW]
FRT
0x15A
-1
read-write
n
0x0
0x0
FRT_TCDT0
FRT-ch.0 Count Value Register [HW]
FRT
0x146
16
read-write
n
0x0
0x0
FRT_TCDT1
FRT-ch.1 Count Value Register [HW]
FRT
0x152
-1
read-write
n
0x0
0x0
FRT_TCDT2
FRT-ch.2 Count Value Register [HW]
FRT
0x15E
-1
read-write
n
0x0
0x0
FRT_TCSA0
FRT-ch.0 Control Register A [BHW]
FRT
0x148
16
read-write
n
0x0
0x0
BFE
Enables TCCP's buffer function
7
read-write
CLK
FRT clock cycle
0
3
read-write
ECKE
Uses an external input clock (FRCK) as FRT's count clock
15
read-write
ICLR
interrupt flag
9
read-write
ICRE
Generates interrupt when TCSA.ICLR is set to 1
8
read-write
IRQZE
Generates interrupt when TCSA.IRQZF is set to 1
13
read-write
IRQZF
zero interrupt flag
14
read-write
MODE
FRT's count mode
5
read-write
SCLR
FRT operation state initialization request
4
write-only
STOP
Puts FRT in stopping state
6
read-write
FRT_TCSA1
FRT-ch.1 Control Register A [BHW]
FRT
0x154
-1
read-write
n
0x0
0x0
FRT_TCSA2
FRT-ch.2 Control Register A [BHW]
FRT
0x160
-1
read-write
n
0x0
0x0
FRT_TCSC0
FRT-ch.0 Control Register C [HW]
FRT
0x14A
16
read-write
n
0x0
0x0
MSPC
Current counter value of a Peak value detection mask counter
12
3
read-only
MSPI
Masked Peak value detection number
4
3
read-write
MSZC
Current counter value of a Zero value detection mask counter
8
3
read-only
MSZI
Masked Zero value detection number
0
3
read-write
FRT_TCSC1
FRT-ch.1 Control Register C [HW]
FRT
0x156
-1
read-write
n
0x0
0x0
FRT_TCSC2
FRT-ch.2 Control Register C [HW]
FRT
0x162
-1
read-write
n
0x0
0x0
FRT_TCSD
FRT Control Register D [BHW]
FRT
0x1EC
8
read-write
n
0x0
0x0
OFMD1
selects the count mode with offset for FRT ch.1
0
read-write
OFMD2
selects the count mode with offset for FRT ch.2
1
read-write
ICU_ICCP0
ICU-ch.0 Capture Value Store Register [HW]
ICU
0x176
16
read-only
n
0x0
0x0
ICU_ICCP1
ICU-ch.1 Capture Value Store Register [HW]
ICU
0x17A
-1
read-write
n
0x0
0x0
ICU_ICCP2
ICU-ch.2 Capture Value Store Register [HW]
ICU
0x17E
-1
read-write
n
0x0
0x0
ICU_ICCP3
ICU-ch.3 Capture Value Store Register [HW]
ICU
0x182
-1
read-write
n
0x0
0x0
ICU_ICFS10
ICU ch.0/1 Connecting FRT Select Register [BHW]
ICU
0x16C
8
read-write
n
0x0
0x0
FSI0
Connects FRT ch.x to ICU ch.(0)
0
3
read-write
FSI1
Connects FRT ch.x to ICU ch.(1)
4
3
read-write
ICU_ICFS32
ICU ch.2/3 Connecting FRT Select Register [BHW]
ICU
0x16D
8
read-write
n
0x0
0x0
FSI2
Connects FRT ch.x to ICU ch.(2)
0
3
read-write
FSI3
Connects FRT ch.x to ICU ch.(3)
4
3
read-write
ICU_ICSA10
ICU ch.0/1 Control Register A [BHW]
ICU
0x184
8
read-write
n
0x0
0x0
EG0
enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
0
1
read-write
EG1
enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
2
1
read-write
ICE0
Generates interrupt when ICSA.ICP0 is set to 1
4
read-write
ICE1
Generates interrupt when ICSA.ICP1 is set to 1
5
read-write
ICP0
Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
6
read-write
ICP1
Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
7
read-write
ICU_ICSA32
ICU ch.2/3 Control Register A [BHW]
ICU
0x188
8
read-write
n
0x0
0x0
EG2
enables/disables the operation of ICU-ch.(2) and selects a valid edge(s)
0
1
read-write
EG3
enables/disables the operation of ICU-ch.(3) and selects a valid edge(s)
2
1
read-write
ICE2
Generates interrupt when ICSA.ICP2 is set to 1
4
read-write
ICE3
Generates interrupt when ICSA.ICP3 is set to 1
5
read-write
ICP2
Indicates that a valid edge has been detected at ICU ch.(2) and the capture operation has been performed
6
read-write
ICP3
Indicates that a valid edge has been detected at ICU ch.(3) and the capture operation has been performed
7
read-write
ICU_ICSB10
ICU ch.0/1 Control Register B [BHW]
ICU
0x185
8
read-only
n
0x0
0x0
IEI0
indicates the latest valid edge of ICU ch.(0)
0
read-only
IEI1
indicates the latest valid edge of ICU ch.(1)
1
read-only
ICU_ICSB32
ICU ch.2/3 Control Register B [BHW]
ICU
0x189
8
read-only
n
0x0
0x0
IEI2
indicates the latest valid edge of ICU ch.(2)
0
read-only
IEI3
indicates the latest valid edge of ICU ch.(3)
1
read-only
OCU_OCCP0
OCU ch.0 Compare Value Store Register [HW]
OCU
0x102
16
read-write
n
0x0
0x0
OCU_OCCP1
OCU ch.1 Compare Value Store Register [HW]
OCU
0x106
-1
read-write
n
0x0
0x0
OCU_OCCP2
OCU ch.2 Compare Value Store Register [HW]
OCU
0x10A
-1
read-write
n
0x0
0x0
OCU_OCCP3
OCU ch.3 Compare Value Store Register [HW]
OCU
0x10E
-1
read-write
n
0x0
0x0
OCU_OCCP4
OCU ch.4 Compare Value Store Register [HW]
OCU
0x112
-1
read-write
n
0x0
0x0
OCU_OCCP5
OCU ch.5 Compare Value Store Register [HW]
OCU
0x116
-1
read-write
n
0x0
0x0
OCU_OCFS10
OCU ch.0/1 Connecting FRT Select Register [BHW]
OCU
0x168
8
read-write
n
0x0
0x0
FSO0
Connects FRT ch.x to OCU ch.0
0
3
read-write
FSO1
Connects FRT ch.x to OCU ch.1
4
3
read-write
OCU_OCFS32
OCU ch.2/3 Connecting FRT Select Register [BHW]
OCU
0x169
8
read-write
n
0x0
0x0
FSO2
Connects FRT ch.x to OCU ch.2
0
3
read-write
FSO3
Connects FRT ch.x to OCU ch.3
4
3
read-write
OCU_OCFS54
OCU ch.4/5 Connecting FRT Select Register [BHW]
OCU
0x16A
8
read-write
n
0x0
0x0
FSO4
Connects FRT ch.x to OCU ch.4
0
3
read-write
FSO5
Connects FRT ch.x to OCU ch.5
4
3
read-write
OCU_OCSA10
OCU ch.0/1 Control Register A [BHW]
OCU
0x118
8
read-write
n
0x0
0x0
CST0
Enables the operation of OCU ch.(0)
0
read-write
CST1
Enables the operation of OCU ch.(1)
1
read-write
IOE0
Generates interrupt when OCSA.IOP0 is set to 1
4
read-write
IOE1
Generates interrupt when OCSA.IOP1 is set to 1
5
read-write
IOP0
Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0)
6
read-write
IOP1
Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1)
7
read-write
OCU_OCSA32
OCU ch.2/3 Control Register A [BHW]
OCU
0x11C
8
read-write
n
0x0
0x0
CST2
Enables the operation of OCU ch.(2)
0
read-write
CST3
Enables the operation of OCU ch.(3)
1
read-write
IOE2
Generates interrupt when OCSA.IOP2 is set to 1
4
read-write
IOE3
Generates interrupt when OCSA.IOP3 is set to 1
5
read-write
IOP2
Indicates that a match has already been detected between FRT's count value and OCCP(2) value at OCU ch.(2)
6
read-write
IOP3
Indicates that a match has already been detected between FRT's count value and OCCP(3) value at OCU ch.(3)
7
read-write
OCU_OCSA54
OCU ch.4/5 Control Register A [BHW]
OCU
0x120
8
read-write
n
0x0
0x0
CST4
Enables the operation of OCU ch.(4)
0
read-write
CST5
Enables the operation of OCU ch.(5)
1
read-write
IOE4
Generates interrupt when OCSA.IOP4 is set to 1
4
read-write
IOE5
Generates interrupt when OCSA.IOP5 is set to 1
5
read-write
IOP4
Indicates that a match has already been detected between FRT's count value and OCCP(4) value at OCU ch.(4)
6
read-write
IOP5
Indicates that a match has already been detected between FRT's count value and OCCP(5) value at OCU ch.(5)
7
read-write
OCU_OCSB10
OCU ch.0/1 Control Register B [BHW]
OCU
0x119
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD0
Indicates that the RT(0) output pin is in the High-level output state
0
read-write
OTD1
Indicates that the RT(1) output pin is in the High-level output state
1
read-write
OCU_OCSB32
OCU ch.2/3 Control Register B [BHW]
OCU
0x11D
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD2
Indicates that the RT(2) output pin is in the High-level output state
0
read-write
OTD3
Indicates that the RT(3) output pin is in the High-level output state
1
read-write
OCU_OCSB54
OCU ch.4/5 Control Register B [BHW]
OCU
0x121
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD4
Indicates that the RT(4) output pin is in the High-level output state
0
read-write
OTD5
Indicates that the RT(5) output pin is in the High-level output state
1
read-write
OCU_OCSC
OCU Control Register C [BHW]
OCU
0x125
8
read-write
n
0x0
0x0
MOD0
OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
0
read-write
MOD1
OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
1
read-write
MOD2
OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
2
read-write
MOD3
OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
3
read-write
MOD4
OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
4
read-write
MOD5
OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
5
read-write
OCU_OCSD10
OCU ch.0/1 Control Register D [BHW]
OCU
0x11A
16
read-write
n
0x0
0x0
OCCP0BUFE
Enable buffer register function of OCCP(0)
0
1
read-write
OCCP1BUFE
Enable buffer register function of OCCP(1)
2
1
read-write
OCSE0BUFE
Enable buffer register function of OCSE(0)
4
1
read-write
OCSE1BUFE
Enable buffer register function of OCSE(1)
6
1
read-write
OEBM0
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM1
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX0
extends the matching determination conditions of the connected FRT with the OCCP(0) register value
12
read-write
OFEX1
extends the matching determination conditions of the connected FRT with the OCCP(1) register value
13
read-write
OPBM0
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM1
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSD32
OCU ch.2/3 Control Register D [BHW]
OCU
0x11E
16
read-write
n
0x0
0x0
OCCP2BUFE
Enable buffer register function of OCCP(2)
0
1
read-write
OCCP3BUFE
Enable buffer register function of OCCP(3)
2
1
read-write
OCSE2BUFE
Enable buffer register function of OCSE(2)
4
1
read-write
OCSE3BUFE
Enable buffer register function of OCSE(3)
6
1
read-write
OEBM2
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM3
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX2
extends the matching determination conditions of the connected FRT with the OCCP(2) register value
12
read-write
OFEX3
extends the matching determination conditions of the connected FRT with the OCCP(3) register value
13
read-write
OPBM2
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM3
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSD54
OCU ch.4/5 Control Register D [BHW]
OCU
0x122
16
read-write
n
0x0
0x0
OCCP4BUFE
Enable buffer register function of OCCP(4)
0
1
read-write
OCCP5BUFE
Enable buffer register function of OCCP(5)
2
1
read-write
OCSE4BUFE
Enable buffer register function of OCSE(4)
4
1
read-write
OCSE5BUFE
Enable buffer register function of OCSE(5)
6
1
read-write
OEBM4
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM5
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX4
extends the matching determination conditions of the connected FRT with the OCCP(4) register value
12
read-write
OFEX5
extends the matching determination conditions of the connected FRT with the OCCP(5) register value
13
read-write
OPBM4
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM5
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSE0
OCU ch.0 Control Register E [BHW]
OCU
0x128
16
read-write
n
0x0
0x0
OCSE
specify the setting conditions of the OCU's matching detection register (IOP0)
0
15
read-write
OCU_OCSE1
OCU ch.1 Control Register E [BHW]
OCU
0x12C
32
read-write
n
0x0
0x0
OCSE
specify the setting conditions of the OCU's matching detection register (IOP0/IOP1)
0
31
read-write
OCU_OCSE2
OCU ch.2 Control Register E [BHW]
OCU
0x130
-1
read-write
n
0x0
0x0
OCU_OCSE3
OCU ch.3 Control Register E [BHW]
OCU
0x134
-1
read-write
n
0x0
0x0
OCU_OCSE4
OCU ch.4 Control Register E [BHW]
OCU
0x138
-1
read-write
n
0x0
0x0
OCU_OCSE5
OCU ch.5 Control Register E [BHW]
OCU
0x13C
-1
read-write
n
0x0
0x0
WFG_NZCL
NZCL Control Register [HW]
WFG
0x1B4
16
read-write
n
0x0
0x0
DHOLD
selects whether the RTO output signal of WFG is held when the DTIF interrupt signal is asserted
7
read-write
DIMA
selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set
8
read-write
DIMB
selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set
9
read-write
DTIEA
Enables the path for digital noise filter from DTTIX pin
0
read-write
DTIEB
Enables the path from DTTIX pin to analog noise filter
5
read-write
NWS
set the noise-canceling width for a digital noise-canceller
1
2
read-write
SDTI
sets the WFIR.DTIFA register by writing to the register from the CPU
4
write-only
WIM10
selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set
12
read-write
WIM32
selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set
13
read-write
WIM54
selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set
14
read-write
WFG_WFIR
WFG Interrupt Control Register [HW]
WFG
0x1B0
16
read-write
n
0x0
0x0
DTICA
clears the DTIFA interrupt flag
1
write-only
DTICB
clears DTIFB bit
3
write-only
DTIFA
detects the event of DTTIX signal input via digital noise-canceller
0
read-only
DTIFB
detects DTTIX signal input via analog noise filter
2
read-only
TMIC10
clears TIMF10 bit
5
write-only
TMIC32
clears TIMF32 bit
9
write-only
TMIC54
clears TIMF54 bit
13
write-only
TMIE10
starts WFG10 reload timer and checks the operation state of it
6
read-write
TMIE32
1stops the WFG32 reload timer and clears TMIF32
10
read-write
TMIE54
stops the WFG54 reload timer and clears TMIF54
14
read-write
TMIF10
detects the event of WFG10 reload timer interrupt occurrence
4
read-only
TMIF32
detects the event of WFG32 reload timer interrupt occurrence
8
read-only
TMIF54
detects the event of WFG54 reload timer interrupt occurrence
12
read-only
TMIS10
stops the WFG10 reload timer and clears TMIF10
7
write-only
TMIS32
stops the WFG32 reload timer and clears TMIF32
11
write-only
TMIS54
stops the WFG54 reload timer and clears TMIF54
15
write-only
WFG_WFSA10
WFG Control Register A for WFG ch.0/1 [BHW]
WFG
0x1A4
16
read-write
n
0x0
0x0
DCK
set the count clock cycle for the WFG timer and Pulse counter
0
2
read-write
DMOD
1specifies polarity for RTO(0) and RTO(1) signal outputs
12
1
read-write
GTEN
selects the output conditions for the CH_GATE output signal of the WFG
6
1
read-write
PGEN
specifies how to reflect the CH_PPG signal for each channel of the WFG
10
1
read-write
PSEL
select the PPG timer unit to be used for each channel of the WFG
8
1
read-write
TMD
select the WFG's operation mode
3
2
read-write
WFG_WFSA32
WFG Control Register A for WFG ch.2/3 [BHW]
WFG
0x1A8
-1
read-write
n
0x0
0x0
WFG_WFSA54
WFG Control Register A for WFG ch.4/5 [BHW]
WFG
0x1AC
-1
read-write
n
0x0
0x0
WFG_WFTA10
WFG Timer Value Register for WFG ch.0/1 [HW]
WFG
0x190
16
read-write
n
0x0
0x0
WFG_WFTA32
WFG Timer Value Register for WFG ch.2/3 [HW]
WFG
0x198
16
read-write
n
0x0
0x0
WFG_WFTA54
WFG Timer Value Register for WFG ch.4/5 [HW]
WFG
0x1A0
16
read-write
n
0x0
0x0
WFG_WFTB10
WFG Timer Value Register for WFG ch.0/1 [HW]
WFG
0x192
16
read-write
n
0x0
0x0
WFG_WFTB32
WFG Timer Value Register for WFG ch.2/3 [HW]
WFG
0x19A
16
read-write
n
0x0
0x0
WFG_WFTB54
WFG Timer Value Register for WFG ch.4/5 [HW]
WFG
0x1A2
16
read-write
n
0x0
0x0
WFG_WFTF10
Pulse Counter Value Register for WFG ch.0/1 [HW]
WFG
0x18E
16
read-write
n
0x0
0x0
WFG_WFTF32
Pulse Counter Value Register for WFG ch.2/3 [HW]
WFG
0x196
16
read-write
n
0x0
0x0
WFG_WFTF54
Pulse Counter Value Register for WFG ch.4/5 [HW]
WFG
0x19E
16
read-write
n
0x0
0x0
MFT1
Multifunction Timer 1
MFT
0x0
0x102
0x2
registers
n
0x106
0x2
registers
n
0x10A
0x2
registers
n
0x10E
0x2
registers
n
0x112
0x2
registers
n
0x116
0xE
registers
n
0x125
0x1
registers
n
0x128
0x2
registers
n
0x12C
0x6
registers
n
0x134
0x6
registers
n
0x13C
0x4
registers
n
0x142
0x2
registers
n
0x146
0x6
registers
n
0x14E
0x2
registers
n
0x152
0x6
registers
n
0x15A
0x2
registers
n
0x15E
0xD
registers
n
0x16C
0x2
registers
n
0x170
0x3
registers
n
0x176
0x2
registers
n
0x17A
0x2
registers
n
0x17E
0x2
registers
n
0x182
0x4
registers
n
0x188
0x2
registers
n
0x18E
0x6
registers
n
0x196
0x6
registers
n
0x19E
0x8
registers
n
0x1A8
0x2
registers
n
0x1AC
0x2
registers
n
0x1B0
0x2
registers
n
0x1B4
0x2
registers
n
0x1BA
0x2
registers
n
0x1BE
0x2
registers
n
0x1C2
0x2
registers
n
0x1C6
0x2
registers
n
0x1CA
0x2
registers
n
0x1CE
0x4
registers
n
0x1D4
0x3
registers
n
0x1D8
0x3
registers
n
0x1DC
0x3
registers
n
0x1E0
0x3
registers
n
0x1E4
0x3
registers
n
0x1E8
0x3
registers
n
0x1EC
0x1
registers
n
MFT1_WFG_DTIF
22
MFT1_FRT_PEAK
28
MFT1_FRT_ZERO
29
MFT1_ICU
30
MFT1_OCU
31
ADCMP_ACFS10
ADCMP ch.0/1 Connecting FRT Select Register [BHW]
ADCMP
0x170
8
read-write
n
0x0
0x0
FSA0
specify the FRT to be connected to ADCMP ch.(0)
0
3
read-write
FSA1
specify the FRT to be connected to ADCMP ch.(1)
4
3
read-write
ADCMP_ACFS32
ADCMP ch.2/3 Connecting FRT Select Register [BHW]
ADCMP
0x171
8
read-write
n
0x0
0x0
FSA2
specify the FRT to be connected to ADCMP ch.(2)
0
3
read-write
FSA3
specify the FRT to be connected to ADCMP ch.(3)
4
3
read-write
ADCMP_ACFS54
ADCMP ch.4/5 Connecting FRT Select Register [BHW]
ADCMP
0x172
8
read-write
n
0x0
0x0
FSA4
specify the FRT to be connected to ADCMP ch.(4)
0
3
read-write
FSA5
specify the FRT to be connected to ADCMP ch.(5)
4
3
read-write
ADCMP_ACMC0
ADCMP ch.0 Mask Compare Value Storage Register [BHW]
ADCMP
0x1D6
8
read-write
n
0x0
0x0
AMC
specifies the value to be compared with the FRT interrupt mask counter
0
3
read-write
MPCE
specifies whether a comparison is performed with the FRT peak interrupt mask counter
7
read-write
MZCE
specifies whether a comparison is performed with the FRT zero interrupt mask counter
6
read-write
ADCMP_ACMC1
ADCMP ch.1 Mask Compare Value Storage Register [BHW]
ADCMP
0x1DA
-1
read-write
n
0x0
0x0
ADCMP_ACMC2
ADCMP ch.2 Mask Compare Value Storage Register [BHW]
ADCMP
0x1DE
-1
read-write
n
0x0
0x0
ADCMP_ACMC3
ADCMP ch.3 Mask Compare Value Storage Register [BHW]
ADCMP
0x1E2
-1
read-write
n
0x0
0x0
ADCMP_ACMC4
ADCMP ch.4 Mask Compare Value Storage Register [BHW]
ADCMP
0x1E6
-1
read-write
n
0x0
0x0
ADCMP_ACMC5
ADCMP ch.5 Mask Compare Value Storage Register [BHW]
ADCMP
0x1EA
-1
read-write
n
0x0
0x0
ADCMP_ACMP0
ADCMP ch.0 Compare Value Store Register [HW]
ADCMP
0x1BA
16
read-write
n
0x0
0x0
ACMP
0
0
15
read-write
ADCMP_ACMP1
ADCMP ch.1 Compare Value Store Register [HW]
ADCMP
0x1BE
-1
read-write
n
0x0
0x0
ADCMP_ACMP2
ADCMP ch.2 Compare Value Store Register [HW]
ADCMP
0x1C2
-1
read-write
n
0x0
0x0
ADCMP_ACMP3
ADCMP ch.3 Compare Value Store Register [HW]
ADCMP
0x1C6
-1
read-write
n
0x0
0x0
ADCMP_ACMP4
ADCMP ch.4 Compare Value Store Register [HW]
ADCMP
0x1CA
-1
read-write
n
0x0
0x0
ADCMP_ACMP5
ADCMP ch.5 Compare Value Store Register [HW]
ADCMP
0x1CE
-1
read-write
n
0x0
0x0
ADCMP_ACSA
ADCMP Control Register A [BHW]
ADCMP
0x1D0
16
read-write
n
0x0
0x0
CE10
enables/disables compatibility of ADCMP ch.1 and ch.0 with FM3 Family products
0
1
read-write
CE32
enables/disables compatibility of ADCMP ch.3 and ch.2 with FM3 Family products
2
1
read-write
CE54
enables/disables compatibility of ADCMP ch.5 and ch.4 with FM3 Family products
4
1
read-write
SEL10
selects compatible operation of ADCMP ch.1 and ch.0 with FM3 Family products
8
1
read-write
SEL32
selects compatible operation of ADCMP ch.3 and ch.2 with FM3 Family products
10
1
read-write
SEL54
selects compatible operation of ADCMP ch.5 and ch.4 with FM3 Family products
12
1
read-write
ADCMP_ACSC0
ADCMP ch.0 Control Register C [BHW]
ADCMP
0x1D4
8
read-write
n
0x0
0x0
ADSEL
specify the destinations of ADC start signals that are output by ADCMP
2
2
read-write
APBM
sets the linked transfer with the FRT interrupt mask counter
5
read-write
BUFE
select enable/disable and transfer timing for buffer function of the ACMP register
0
1
read-write
ADCMP_ACSC1
ADCMP ch.1 Control Register C [BHW]
ADCMP
0x1D8
-1
read-write
n
0x0
0x0
ADCMP_ACSC2
ADCMP ch.2 Control Register C [BHW]
ADCMP
0x1DC
-1
read-write
n
0x0
0x0
ADCMP_ACSC3
ADCMP ch.3 Control Register C [BHW]
ADCMP
0x1E0
-1
read-write
n
0x0
0x0
ADCMP_ACSC4
ADCMP ch.4 Control Register C [BHW]
ADCMP
0x1E4
-1
read-write
n
0x0
0x0
ADCMP_ACSC5
ADCMP ch.5 Control Register C [BHW]
ADCMP
0x1E8
-1
read-write
n
0x0
0x0
ADCMP_ACSD0
ADCMP ch.0 Control Register D [BHW]
ADCMP
0x1D5
8
read-write
n
0x0
0x0
AMOD
selects operation mode for ADCMP
0
read-write
DE
enables/disables the operation of the ADCMP that is counting down for the connected FRT
4
read-write
OCUS
selects the OCU OCCP register that will become the start for offset start
1
read-write
PE
enables/disables the operation of the ADCMP that is counting down at the Peak value of the connected FRT
5
read-write
UE
enables/disables the operation of the ADCMP that is counting up for the connected FRT
6
read-write
ZE
enables/disables the operation of the ADCMP when the FRT is 0x0000
7
read-write
ADCMP_ACSD1
ADCMP ch.1 Control Register D [BHW]
ADCMP
0x1D9
-1
read-write
n
0x0
0x0
ADCMP_ACSD2
ADCMP ch.2 Control Register D [BHW]
ADCMP
0x1DD
-1
read-write
n
0x0
0x0
ADCMP_ACSD3
ADCMP ch.3 Control Register D [BHW]
ADCMP
0x1E1
-1
read-write
n
0x0
0x0
ADCMP_ACSD4
ADCMP ch.4 Control Register D [BHW]
ADCMP
0x1E5
-1
read-write
n
0x0
0x0
ADCMP_ACSD5
ADCMP ch.5 Control Register D [BHW]
ADCMP
0x1E9
-1
read-write
n
0x0
0x0
FRT_TCAL
FRT Simultaneous Start Control Register [W]
FRT
0x164
32
read-write
n
0x0
0x0
SCLR00
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit0
16
write-only
SCLR01
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit0
17
write-only
SCLR02
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit0
18
write-only
SCLR10
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit1
19
write-only
SCLR11
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit1
20
write-only
SCLR12
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit1
21
write-only
SCLR20
Mirror register of the SCLR bit located in TCSA0 register of MFT-unit2
22
write-only
SCLR21
Mirror register of the SCLR bit located in TCSA1 register of MFT-unit2
23
write-only
SCLR22
Mirror register of the SCLR bit located in TCSA2 register of MFT-unit2
24
write-only
STOP00
Mirror register of the STOP bit located in TCSA0 register of MFT-unit0
0
read-write
STOP01
Mirror register of the STOP bit located in TCSA1 register of MFT-unit0
1
read-write
STOP02
Mirror register of the STOP bit located in TCSA2 register of MFT-unit0
2
read-write
STOP10
Mirror register of the STOP bit located in TCSA0 register of MFT-unit1
3
read-write
STOP11
Mirror register of the STOP bit located in TCSA1 register of MFT-unit1
4
read-write
STOP12
Mirror register of the STOP bit located in TCSA2 register of MFT-unit1
5
read-write
STOP20
Mirror register of the STOP bit located in TCSA0 register of MFT-unit2
6
read-write
STOP21
Mirror register of the STOP bit located in TCSA1 register of MFT-unit2
7
read-write
STOP22
Mirror register of the STOP bit located in TCSA2 register of MFT-unit2
8
read-write
FRT_TCCP0
FRT-ch.0 Cycle Setting Register [HW]
FRT
0x142
16
read-write
n
0x0
0x0
TCCP
Count Cycle Setting Bits
0
15
read-write
FRT_TCCP1
FRT-ch.1 Cycle Setting Register [HW]
FRT
0x14E
-1
read-write
n
0x0
0x0
FRT_TCCP2
FRT-ch.2 Cycle Setting Register [HW]
FRT
0x15A
-1
read-write
n
0x0
0x0
FRT_TCDT0
FRT-ch.0 Count Value Register [HW]
FRT
0x146
16
read-write
n
0x0
0x0
FRT_TCDT1
FRT-ch.1 Count Value Register [HW]
FRT
0x152
-1
read-write
n
0x0
0x0
FRT_TCDT2
FRT-ch.2 Count Value Register [HW]
FRT
0x15E
-1
read-write
n
0x0
0x0
FRT_TCSA0
FRT-ch.0 Control Register A [BHW]
FRT
0x148
16
read-write
n
0x0
0x0
BFE
Enables TCCP's buffer function
7
read-write
CLK
FRT clock cycle
0
3
read-write
ECKE
Uses an external input clock (FRCK) as FRT's count clock
15
read-write
ICLR
interrupt flag
9
read-write
ICRE
Generates interrupt when TCSA.ICLR is set to 1
8
read-write
IRQZE
Generates interrupt when TCSA.IRQZF is set to 1
13
read-write
IRQZF
zero interrupt flag
14
read-write
MODE
FRT's count mode
5
read-write
SCLR
FRT operation state initialization request
4
write-only
STOP
Puts FRT in stopping state
6
read-write
FRT_TCSA1
FRT-ch.1 Control Register A [BHW]
FRT
0x154
-1
read-write
n
0x0
0x0
FRT_TCSA2
FRT-ch.2 Control Register A [BHW]
FRT
0x160
-1
read-write
n
0x0
0x0
FRT_TCSC0
FRT-ch.0 Control Register C [HW]
FRT
0x14A
16
read-write
n
0x0
0x0
MSPC
Current counter value of a Peak value detection mask counter
12
3
read-only
MSPI
Masked Peak value detection number
4
3
read-write
MSZC
Current counter value of a Zero value detection mask counter
8
3
read-only
MSZI
Masked Zero value detection number
0
3
read-write
FRT_TCSC1
FRT-ch.1 Control Register C [HW]
FRT
0x156
-1
read-write
n
0x0
0x0
FRT_TCSC2
FRT-ch.2 Control Register C [HW]
FRT
0x162
-1
read-write
n
0x0
0x0
FRT_TCSD
FRT Control Register D [BHW]
FRT
0x1EC
8
read-write
n
0x0
0x0
OFMD1
selects the count mode with offset for FRT ch.1
0
read-write
OFMD2
selects the count mode with offset for FRT ch.2
1
read-write
ICU_ICCP0
ICU-ch.0 Capture Value Store Register [HW]
ICU
0x176
16
read-only
n
0x0
0x0
ICU_ICCP1
ICU-ch.1 Capture Value Store Register [HW]
ICU
0x17A
-1
read-write
n
0x0
0x0
ICU_ICCP2
ICU-ch.2 Capture Value Store Register [HW]
ICU
0x17E
-1
read-write
n
0x0
0x0
ICU_ICCP3
ICU-ch.3 Capture Value Store Register [HW]
ICU
0x182
-1
read-write
n
0x0
0x0
ICU_ICFS10
ICU ch.0/1 Connecting FRT Select Register [BHW]
ICU
0x16C
8
read-write
n
0x0
0x0
FSI0
Connects FRT ch.x to ICU ch.(0)
0
3
read-write
FSI1
Connects FRT ch.x to ICU ch.(1)
4
3
read-write
ICU_ICFS32
ICU ch.2/3 Connecting FRT Select Register [BHW]
ICU
0x16D
8
read-write
n
0x0
0x0
FSI2
Connects FRT ch.x to ICU ch.(2)
0
3
read-write
FSI3
Connects FRT ch.x to ICU ch.(3)
4
3
read-write
ICU_ICSA10
ICU ch.0/1 Control Register A [BHW]
ICU
0x184
8
read-write
n
0x0
0x0
EG0
enables/disables the operation of ICU-ch.(0) and selects a valid edge(s)
0
1
read-write
EG1
enables/disables the operation of ICU-ch.(1) and selects a valid edge(s)
2
1
read-write
ICE0
Generates interrupt when ICSA.ICP0 is set to 1
4
read-write
ICE1
Generates interrupt when ICSA.ICP1 is set to 1
5
read-write
ICP0
Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed
6
read-write
ICP1
Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed
7
read-write
ICU_ICSA32
ICU ch.2/3 Control Register A [BHW]
ICU
0x188
8
read-write
n
0x0
0x0
EG2
enables/disables the operation of ICU-ch.(2) and selects a valid edge(s)
0
1
read-write
EG3
enables/disables the operation of ICU-ch.(3) and selects a valid edge(s)
2
1
read-write
ICE2
Generates interrupt when ICSA.ICP2 is set to 1
4
read-write
ICE3
Generates interrupt when ICSA.ICP3 is set to 1
5
read-write
ICP2
Indicates that a valid edge has been detected at ICU ch.(2) and the capture operation has been performed
6
read-write
ICP3
Indicates that a valid edge has been detected at ICU ch.(3) and the capture operation has been performed
7
read-write
ICU_ICSB10
ICU ch.0/1 Control Register B [BHW]
ICU
0x185
8
read-only
n
0x0
0x0
IEI0
indicates the latest valid edge of ICU ch.(0)
0
read-only
IEI1
indicates the latest valid edge of ICU ch.(1)
1
read-only
ICU_ICSB32
ICU ch.2/3 Control Register B [BHW]
ICU
0x189
8
read-only
n
0x0
0x0
IEI2
indicates the latest valid edge of ICU ch.(2)
0
read-only
IEI3
indicates the latest valid edge of ICU ch.(3)
1
read-only
OCU_OCCP0
OCU ch.0 Compare Value Store Register [HW]
OCU
0x102
16
read-write
n
0x0
0x0
OCU_OCCP1
OCU ch.1 Compare Value Store Register [HW]
OCU
0x106
-1
read-write
n
0x0
0x0
OCU_OCCP2
OCU ch.2 Compare Value Store Register [HW]
OCU
0x10A
-1
read-write
n
0x0
0x0
OCU_OCCP3
OCU ch.3 Compare Value Store Register [HW]
OCU
0x10E
-1
read-write
n
0x0
0x0
OCU_OCCP4
OCU ch.4 Compare Value Store Register [HW]
OCU
0x112
-1
read-write
n
0x0
0x0
OCU_OCCP5
OCU ch.5 Compare Value Store Register [HW]
OCU
0x116
-1
read-write
n
0x0
0x0
OCU_OCFS10
OCU ch.0/1 Connecting FRT Select Register [BHW]
OCU
0x168
8
read-write
n
0x0
0x0
FSO0
Connects FRT ch.x to OCU ch.0
0
3
read-write
FSO1
Connects FRT ch.x to OCU ch.1
4
3
read-write
OCU_OCFS32
OCU ch.2/3 Connecting FRT Select Register [BHW]
OCU
0x169
8
read-write
n
0x0
0x0
FSO2
Connects FRT ch.x to OCU ch.2
0
3
read-write
FSO3
Connects FRT ch.x to OCU ch.3
4
3
read-write
OCU_OCFS54
OCU ch.4/5 Connecting FRT Select Register [BHW]
OCU
0x16A
8
read-write
n
0x0
0x0
FSO4
Connects FRT ch.x to OCU ch.4
0
3
read-write
FSO5
Connects FRT ch.x to OCU ch.5
4
3
read-write
OCU_OCSA10
OCU ch.0/1 Control Register A [BHW]
OCU
0x118
8
read-write
n
0x0
0x0
CST0
Enables the operation of OCU ch.(0)
0
read-write
CST1
Enables the operation of OCU ch.(1)
1
read-write
IOE0
Generates interrupt when OCSA.IOP0 is set to 1
4
read-write
IOE1
Generates interrupt when OCSA.IOP1 is set to 1
5
read-write
IOP0
Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0)
6
read-write
IOP1
Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1)
7
read-write
OCU_OCSA32
OCU ch.2/3 Control Register A [BHW]
OCU
0x11C
8
read-write
n
0x0
0x0
CST2
Enables the operation of OCU ch.(2)
0
read-write
CST3
Enables the operation of OCU ch.(3)
1
read-write
IOE2
Generates interrupt when OCSA.IOP2 is set to 1
4
read-write
IOE3
Generates interrupt when OCSA.IOP3 is set to 1
5
read-write
IOP2
Indicates that a match has already been detected between FRT's count value and OCCP(2) value at OCU ch.(2)
6
read-write
IOP3
Indicates that a match has already been detected between FRT's count value and OCCP(3) value at OCU ch.(3)
7
read-write
OCU_OCSA54
OCU ch.4/5 Control Register A [BHW]
OCU
0x120
8
read-write
n
0x0
0x0
CST4
Enables the operation of OCU ch.(4)
0
read-write
CST5
Enables the operation of OCU ch.(5)
1
read-write
IOE4
Generates interrupt when OCSA.IOP4 is set to 1
4
read-write
IOE5
Generates interrupt when OCSA.IOP5 is set to 1
5
read-write
IOP4
Indicates that a match has already been detected between FRT's count value and OCCP(4) value at OCU ch.(4)
6
read-write
IOP5
Indicates that a match has already been detected between FRT's count value and OCCP(5) value at OCU ch.(5)
7
read-write
OCU_OCSB10
OCU ch.0/1 Control Register B [BHW]
OCU
0x119
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD0
Indicates that the RT(0) output pin is in the High-level output state
0
read-write
OTD1
Indicates that the RT(1) output pin is in the High-level output state
1
read-write
OCU_OCSB32
OCU ch.2/3 Control Register B [BHW]
OCU
0x11D
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD2
Indicates that the RT(2) output pin is in the High-level output state
0
read-write
OTD3
Indicates that the RT(3) output pin is in the High-level output state
1
read-write
OCU_OCSB54
OCU ch.4/5 Control Register B [BHW]
OCU
0x121
8
read-write
n
0x0
0x0
CMOD
selects OCU's operation mode in combination with OCSC.MOD0 to MOD5
4
read-write
FM4
selects FM4 mode for operating mode
7
read-write
OTD4
Indicates that the RT(4) output pin is in the High-level output state
0
read-write
OTD5
Indicates that the RT(5) output pin is in the High-level output state
1
read-write
OCU_OCSC
OCU Control Register C [BHW]
OCU
0x125
8
read-write
n
0x0
0x0
MOD0
OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
0
read-write
MOD1
OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0,h.1 in combination with OCSB10.CMOD
1
read-write
MOD2
OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
2
read-write
MOD3
OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2,h.3 in combination with OCSB32.CMOD
3
read-write
MOD4
OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
4
read-write
MOD5
OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4,h.5 in combination with OCSB54.CMOD
5
read-write
OCU_OCSD10
OCU ch.0/1 Control Register D [BHW]
OCU
0x11A
16
read-write
n
0x0
0x0
OCCP0BUFE
Enable buffer register function of OCCP(0)
0
1
read-write
OCCP1BUFE
Enable buffer register function of OCCP(1)
2
1
read-write
OCSE0BUFE
Enable buffer register function of OCSE(0)
4
1
read-write
OCSE1BUFE
Enable buffer register function of OCSE(1)
6
1
read-write
OEBM0
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM1
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX0
extends the matching determination conditions of the connected FRT with the OCCP(0) register value
12
read-write
OFEX1
extends the matching determination conditions of the connected FRT with the OCCP(1) register value
13
read-write
OPBM0
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM1
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSD32
OCU ch.2/3 Control Register D [BHW]
OCU
0x11E
16
read-write
n
0x0
0x0
OCCP2BUFE
Enable buffer register function of OCCP(2)
0
1
read-write
OCCP3BUFE
Enable buffer register function of OCCP(3)
2
1
read-write
OCSE2BUFE
Enable buffer register function of OCSE(2)
4
1
read-write
OCSE3BUFE
Enable buffer register function of OCSE(3)
6
1
read-write
OEBM2
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM3
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX2
extends the matching determination conditions of the connected FRT with the OCCP(2) register value
12
read-write
OFEX3
extends the matching determination conditions of the connected FRT with the OCCP(3) register value
13
read-write
OPBM2
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM3
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSD54
OCU ch.4/5 Control Register D [BHW]
OCU
0x122
16
read-write
n
0x0
0x0
OCCP4BUFE
Enable buffer register function of OCCP(4)
0
1
read-write
OCCP5BUFE
Enable buffer register function of OCCP(5)
2
1
read-write
OCSE4BUFE
Enable buffer register function of OCSE(4)
4
1
read-write
OCSE5BUFE
Enable buffer register function of OCSE(5)
6
1
read-write
OEBM4
sets the linked transfer settings with the FRT interrupt mask counter
10
read-write
OEBM5
sets the linked transfer settings with the FRT interrupt mask counter
11
read-write
OFEX4
extends the matching determination conditions of the connected FRT with the OCCP(4) register value
12
read-write
OFEX5
extends the matching determination conditions of the connected FRT with the OCCP(5) register value
13
read-write
OPBM4
sets the linked transfer settings with the FRT interrupt mask counter
8
read-write
OPBM5
sets the linked transfer settings with the FRT interrupt mask counter
9
read-write
OCU_OCSE0
OCU ch.0 Control Register E [BHW]
OCU
0x128
16
read-write
n
0x0
0x0
OCSE
specify the setting conditions of the OCU's matching detection register (IOP0)
0
15
read-write
OCU_OCSE1
OCU ch.1 Control Register E [BHW]
OCU
0x12C
32
read-write
n
0x0
0x0
OCSE
specify the setting conditions of the OCU's matching detection register (IOP0/IOP1)
0
31
read-write
OCU_OCSE2
OCU ch.2 Control Register E [BHW]
OCU
0x130
-1
read-write
n
0x0
0x0
OCU_OCSE3
OCU ch.3 Control Register E [BHW]
OCU
0x134
-1
read-write
n
0x0
0x0
OCU_OCSE4
OCU ch.4 Control Register E [BHW]
OCU
0x138
-1
read-write
n
0x0
0x0
OCU_OCSE5
OCU ch.5 Control Register E [BHW]
OCU
0x13C
-1
read-write
n
0x0
0x0
WFG_NZCL
NZCL Control Register [HW]
WFG
0x1B4
16
read-write
n
0x0
0x0
DHOLD
selects whether the RTO output signal of WFG is held when the DTIF interrupt signal is asserted
7
read-write
DIMA
selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set
8
read-write
DIMB
selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set
9
read-write
DTIEA
Enables the path for digital noise filter from DTTIX pin
0
read-write
DTIEB
Enables the path from DTTIX pin to analog noise filter
5
read-write
NWS
set the noise-canceling width for a digital noise-canceller
1
2
read-write
SDTI
sets the WFIR.DTIFA register by writing to the register from the CPU
4
write-only
WIM10
selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set
12
read-write
WIM32
selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set
13
read-write
WIM54
selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set
14
read-write
WFG_WFIR
WFG Interrupt Control Register [HW]
WFG
0x1B0
16
read-write
n
0x0
0x0
DTICA
clears the DTIFA interrupt flag
1
write-only
DTICB
clears DTIFB bit
3
write-only
DTIFA
detects the event of DTTIX signal input via digital noise-canceller
0
read-only
DTIFB
detects DTTIX signal input via analog noise filter
2
read-only
TMIC10
clears TIMF10 bit
5
write-only
TMIC32
clears TIMF32 bit
9
write-only
TMIC54
clears TIMF54 bit
13
write-only
TMIE10
starts WFG10 reload timer and checks the operation state of it
6
read-write
TMIE32
1stops the WFG32 reload timer and clears TMIF32
10
read-write
TMIE54
stops the WFG54 reload timer and clears TMIF54
14
read-write
TMIF10
detects the event of WFG10 reload timer interrupt occurrence
4
read-only
TMIF32
detects the event of WFG32 reload timer interrupt occurrence
8
read-only
TMIF54
detects the event of WFG54 reload timer interrupt occurrence
12
read-only
TMIS10
stops the WFG10 reload timer and clears TMIF10
7
write-only
TMIS32
stops the WFG32 reload timer and clears TMIF32
11
write-only
TMIS54
stops the WFG54 reload timer and clears TMIF54
15
write-only
WFG_WFSA10
WFG Control Register A for WFG ch.0/1 [BHW]
WFG
0x1A4
16
read-write
n
0x0
0x0
DCK
set the count clock cycle for the WFG timer and Pulse counter
0
2
read-write
DMOD
1specifies polarity for RTO(0) and RTO(1) signal outputs
12
1
read-write
GTEN
selects the output conditions for the CH_GATE output signal of the WFG
6
1
read-write
PGEN
specifies how to reflect the CH_PPG signal for each channel of the WFG
10
1
read-write
PSEL
select the PPG timer unit to be used for each channel of the WFG
8
1
read-write
TMD
select the WFG's operation mode
3
2
read-write
WFG_WFSA32
WFG Control Register A for WFG ch.2/3 [BHW]
WFG
0x1A8
-1
read-write
n
0x0
0x0
WFG_WFSA54
WFG Control Register A for WFG ch.4/5 [BHW]
WFG
0x1AC
-1
read-write
n
0x0
0x0
WFG_WFTA10
WFG Timer Value Register for WFG ch.0/1 [HW]
WFG
0x190
16
read-write
n
0x0
0x0
WFG_WFTA32
WFG Timer Value Register for WFG ch.2/3 [HW]
WFG
0x198
16
read-write
n
0x0
0x0
WFG_WFTA54
WFG Timer Value Register for WFG ch.4/5 [HW]
WFG
0x1A0
16
read-write
n
0x0
0x0
WFG_WFTB10
WFG Timer Value Register for WFG ch.0/1 [HW]
WFG
0x192
16
read-write
n
0x0
0x0
WFG_WFTB32
WFG Timer Value Register for WFG ch.2/3 [HW]
WFG
0x19A
16
read-write
n
0x0
0x0
WFG_WFTB54
WFG Timer Value Register for WFG ch.4/5 [HW]
WFG
0x1A2
16
read-write
n
0x0
0x0
WFG_WFTF10
Pulse Counter Value Register for WFG ch.0/1 [HW]
WFG
0x18E
16
read-write
n
0x0
0x0
WFG_WFTF32
Pulse Counter Value Register for WFG ch.2/3 [HW]
WFG
0x196
16
read-write
n
0x0
0x0
WFG_WFTF54
Pulse Counter Value Register for WFG ch.4/5 [HW]
WFG
0x19E
16
read-write
n
0x0
0x0
MFT_PPG
PPG Configuration
MFT_PPG
0x0
0x1
0x1
registers
n
0x100
0x2
registers
n
0x104
0x2
registers
n
0x11
0x1
registers
n
0x14
0x1
registers
n
0x140
0x2
registers
n
0x144
0x2
registers
n
0x200
0x2
registers
n
0x204
0x2
registers
n
0x208
0x2
registers
n
0x20C
0x2
registers
n
0x21
0x1
registers
n
0x210
0x2
registers
n
0x214
0x2
registers
n
0x218
0x1
registers
n
0x240
0x2
registers
n
0x244
0x2
registers
n
0x248
0x2
registers
n
0x24C
0x2
registers
n
0x250
0x2
registers
n
0x254
0x2
registers
n
0x258
0x1
registers
n
0x280
0x2
registers
n
0x284
0x2
registers
n
0x288
0x2
registers
n
0x28C
0x2
registers
n
0x29
0x1
registers
n
0x290
0x2
registers
n
0x294
0x2
registers
n
0x298
0x1
registers
n
0x2C
0x1
registers
n
0x2C0
0x2
registers
n
0x2C4
0x2
registers
n
0x2C8
0x2
registers
n
0x2CC
0x2
registers
n
0x2D0
0x2
registers
n
0x2D4
0x2
registers
n
0x2D8
0x1
registers
n
0x300
0x2
registers
n
0x304
0x2
registers
n
0x308
0x2
registers
n
0x30C
0x2
registers
n
0x31
0x1
registers
n
0x310
0x2
registers
n
0x314
0x2
registers
n
0x318
0x1
registers
n
0x34
0x1
registers
n
0x340
0x2
registers
n
0x344
0x2
registers
n
0x348
0x2
registers
n
0x34C
0x2
registers
n
0x350
0x2
registers
n
0x354
0x2
registers
n
0x358
0x1
registers
n
0x41
0x1
registers
n
0x49
0x1
registers
n
0x4C
0x1
registers
n
0x51
0x1
registers
n
0x54
0x1
registers
n
0x9
0x1
registers
n
0xC
0x1
registers
n
PPG00_02_04
36
PPG08_10_12
37
PPG16_18_20
38
COMP0
PPG Compare Register 0 [BHW]
0x9
8
read-write
n
0x0
0x0
COMP1
PPG Compare Register 1 [BHW]
0x29
read-write
n
0x0
0x0
COMP10
PPG Compare Register 10 [BHW]
0x4C
read-write
n
0x0
0x0
COMP12
PPG Compare Register 12 [BHW]
0x51
read-write
n
0x0
0x0
COMP14
PPG Compare Register 14 [BHW]
0x54
read-write
n
0x0
0x0
COMP2
PPG Compare Register 2 [BHW]
0xC
8
read-write
n
0x0
0x0
COMP3
PPG Compare Register 3 [BHW]
0x2C
read-write
n
0x0
0x0
COMP4
PPG Compare Register 4 [BHW]
0x11
read-write
n
0x0
0x0
COMP5
PPG Compare Register 5 [BHW]
0x31
read-write
n
0x0
0x0
COMP6
PPG Compare Register 6 [BHW]
0x14
read-write
n
0x0
0x0
COMP7
PPG Compare Register 7 [BHW]
0x34
read-write
n
0x0
0x0
COMP8
PPG Compare Register 8 [BHW]
0x49
read-write
n
0x0
0x0
GATEC0
PPG Gate Function Control Registers 0 [BHW]
0x218
8
read-write
n
0x0
0x0
EDGE0
Select Start Effective Level for PPG0
0
read-write
EDGE2
Select Start Effective Level for PPG2
4
read-write
STRG0
Select a trigger for PPG0
1
read-write
STRG2
Select a trigger for PPG2
5
read-write
GATEC12
PPG Gate Function Control Registers 12 [BHW]
0x2D8
8
read-write
n
0x0
0x0
EDGE12
Select Start Effective Level for PPG12
0
read-write
EDGE14
Select Start Effective Level for PPG14
4
read-write
STRG12
Select a trigger for PPG12
1
read-write
STRG14
Select a trigger for PPG14
5
read-write
GATEC16
PPG Gate Function Control Registers 16 [BHW]
0x318
8
read-write
n
0x0
0x0
EDGE16
Select Start Effective Level for PPG16
0
read-write
EDGE18
Select Start Effective Level for PPG18
4
read-write
STRG16
Select a trigger for PPG16
1
read-write
STRG18
Select a trigger for PPG18
5
read-write
GATEC20
PPG Gate Function Control Registers 20 [BHW]
0x358
8
read-write
n
0x0
0x0
EDGE20
Select Start Effective Level for PPG20
0
read-write
EDGE22
Select Start Effective Level for PPG22
4
read-write
STRG20
Select a trigger for PPG20
1
read-write
STRG22
Select a trigger for PPG22
5
read-write
GATEC4
PPG Gate Function Control Registers 4 [BHW]
0x258
8
read-write
n
0x0
0x0
EDGE4
Select Start Effective Level for PPG4
0
read-write
EDGE6
Select Start Effective Level for PPG6
4
read-write
STRG4
Select a trigger for PPG4
1
read-write
STRG6
Select a trigger for PPG6
5
read-write
GATEC8
PPG Gate Function Control Registers 8 [BHW]
0x298
8
read-write
n
0x0
0x0
EDGE10
Select Start Effective Level for PPG10
4
read-write
EDGE8
Select Start Effective Level for PPG8
0
read-write
STRG10
Select a trigger for PPG10
5
read-write
STRG8
Select a trigger for PPG8
1
read-write
PPGC0
PPG Operation Mode Control Register 0 [BHW]
0x201
8
read-write
n
0x0
0x0
INTM
Interrupt Mode Select bit
5
read-write
MD
PPG Operation Mode Set bits
1
1
read-write
PCS
PPG DOWN Counter Operation Clock Select bits
3
1
read-write
PIE
PPG Interrupt Enable bit
7
read-write
PUF
PPG Counter Underflow bit
6
read-write
TTRG
PPG start trigger select bit
0
read-write
PPGC1
PPG Operation Mode Control Register 1 [BHW]
0x200
8
read-write
n
0x0
0x0
INTM
Interrupt Mode Select bit
5
read-write
PCS
PPG DOWN Counter Operation Clock Select bits
3
1
read-write
PIE
PPG Interrupt Enable bit
7
read-write
PUF
PPG Counter Underflow bit
6
read-write
PPGC10
PPG Operation Mode Control Register 10 [BHW]
0x285
read-write
n
0x0
0x0
PPGC11
PPG Operation Mode Control Register 11 [BHW]
0x284
read-write
n
0x0
0x0
PPGC12
PPG Operation Mode Control Register 12 [BHW]
0x2C1
read-write
n
0x0
0x0
PPGC13
PPG Operation Mode Control Register 13 [BHW]
0x2C0
read-write
n
0x0
0x0
PPGC14
PPG Operation Mode Control Register 14 [BHW]
0x2C5
read-write
n
0x0
0x0
PPGC15
PPG Operation Mode Control Register 15 [BHW]
0x2C4
read-write
n
0x0
0x0
PPGC16
PPG Operation Mode Control Register 16 [BHW]
0x301
read-write
n
0x0
0x0
PPGC17
PPG Operation Mode Control Register 17 [BHW]
0x300
read-write
n
0x0
0x0
PPGC18
PPG Operation Mode Control Register 18 [BHW]
0x305
read-write
n
0x0
0x0
PPGC19
PPG Operation Mode Control Register 19 [BHW]
0x304
read-write
n
0x0
0x0
PPGC2
PPG Operation Mode Control Register 2 [BHW]
0x205
read-write
n
0x0
0x0
PPGC20
PPG Operation Mode Control Register 20 [BHW]
0x341
read-write
n
0x0
0x0
PPGC21
PPG Operation Mode Control Register 21 [BHW]
0x340
read-write
n
0x0
0x0
PPGC22
PPG Operation Mode Control Register 22 [BHW]
0x345
read-write
n
0x0
0x0
PPGC23
PPG Operation Mode Control Register 23 [BHW]
0x344
read-write
n
0x0
0x0
PPGC3
PPG Operation Mode Control Register 3 [BHW]
0x204
read-write
n
0x0
0x0
PPGC4
PPG Operation Mode Control Register 4 [BHW]
0x241
read-write
n
0x0
0x0
PPGC5
PPG Operation Mode Control Register 5 [BHW]
0x240
read-write
n
0x0
0x0
PPGC6
PPG Operation Mode Control Register 6 [BHW]
0x245
read-write
n
0x0
0x0
PPGC7
PPG Operation Mode Control Register 7 [BHW]
0x244
read-write
n
0x0
0x0
PPGC8
PPG Operation Mode Control Register 8 [BHW]
0x281
read-write
n
0x0
0x0
PPGC9
PPG Operation Mode Control Register 9 [BHW]
0x280
read-write
n
0x0
0x0
PRLH0
PPG0 Reload Registers High [BHW]
0x209
8
read-write
n
0x0
0x0
PRLH
Reload Registers High
0
7
read-write
PRLH1
PPG1 Reload Registers High [BHW]
0x20D
read-write
n
0x0
0x0
PRLH10
PPG10 Reload Registers High [BHW]
0x291
read-write
n
0x0
0x0
PRLH11
PPG11 Reload Registers High [BHW]
0x295
read-write
n
0x0
0x0
PRLH12
PPG12 Reload Registers High [BHW]
0x2C9
read-write
n
0x0
0x0
PRLH13
PPG13 Reload Registers High [BHW]
0x2CD
read-write
n
0x0
0x0
PRLH14
PPG14 Reload Registers High [BHW]
0x2D1
read-write
n
0x0
0x0
PRLH15
PPG15 Reload Registers High [BHW]
0x2D5
read-write
n
0x0
0x0
PRLH16
PPG16 Reload Registers High [BHW]
0x309
read-write
n
0x0
0x0
PRLH17
PPG17 Reload Registers High [BHW]
0x30D
read-write
n
0x0
0x0
PRLH18
PPG18 Reload Registers High [BHW]
0x311
read-write
n
0x0
0x0
PRLH19
PPG19 Reload Registers High [BHW]
0x315
read-write
n
0x0
0x0
PRLH2
PPG2 Reload Registers High [BHW]
0x211
read-write
n
0x0
0x0
PRLH20
PPG20 Reload Registers High [BHW]
0x349
read-write
n
0x0
0x0
PRLH21
PPG21 Reload Registers High [BHW]
0x34D
read-write
n
0x0
0x0
PRLH22
PPG22 Reload Registers High [BHW]
0x351
read-write
n
0x0
0x0
PRLH23
PPG23 Reload Registers High [BHW]
0x355
read-write
n
0x0
0x0
PRLH3
PPG3 Reload Registers High [BHW]
0x215
read-write
n
0x0
0x0
PRLH4
PPG4 Reload Registers High [BHW]
0x249
read-write
n
0x0
0x0
PRLH5
PPG5 Reload Registers High [BHW]
0x24D
read-write
n
0x0
0x0
PRLH6
PPG6 Reload Registers High [BHW]
0x251
read-write
n
0x0
0x0
PRLH7
PPG7 Reload Registers High [BHW]
0x255
read-write
n
0x0
0x0
PRLH8
PPG8 Reload Registers High [BHW]
0x289
read-write
n
0x0
0x0
PRLH9
PPG9 Reload Registers High [BHW]
0x28D
read-write
n
0x0
0x0
PRLL0
PPG0 Reload Registers Low [BHW]
0x208
8
read-write
n
0x0
0x0
PRLL
Reload Registers Low
0
7
read-write
PRLL1
PPG1 Reload Registers Low [BHW]
0x20C
read-write
n
0x0
0x0
PRLL10
PPG10 Reload Registers Low [BHW]
0x290
read-write
n
0x0
0x0
PRLL11
PPG11 Reload Registers Low [BHW]
0x294
read-write
n
0x0
0x0
PRLL12
PPG12 Reload Registers Low [BHW]
0x2C8
read-write
n
0x0
0x0
PRLL13
PPG13 Reload Registers Low [BHW]
0x2CC
read-write
n
0x0
0x0
PRLL14
PPG14 Reload Registers Low [BHW]
0x2D0
read-write
n
0x0
0x0
PRLL15
PPG15 Reload Registers Low [BHW]
0x2D4
read-write
n
0x0
0x0
PRLL16
PPG16 Reload Registers Low [BHW]
0x308
read-write
n
0x0
0x0
PRLL17
PPG17 Reload Registers Low [BHW]
0x30C
read-write
n
0x0
0x0
PRLL18
PPG18 Reload Registers Low [BHW]
0x310
read-write
n
0x0
0x0
PRLL19
PPG19 Reload Registers Low [BHW]
0x314
read-write
n
0x0
0x0
PRLL2
PPG2 Reload Registers Low [BHW]
0x210
read-write
n
0x0
0x0
PRLL20
PPG20 Reload Registers Low [BHW]
0x348
read-write
n
0x0
0x0
PRLL21
PPG21 Reload Registers Low [BHW]
0x34C
read-write
n
0x0
0x0
PRLL22
PPG22 Reload Registers Low [BHW]
0x350
read-write
n
0x0
0x0
PRLL23
PPG23 Reload Registers Low [BHW]
0x354
read-write
n
0x0
0x0
PRLL3
PPG3 Reload Registers Low [BHW]
0x214
read-write
n
0x0
0x0
PRLL4
PPG4 Reload Registers Low [BHW]
0x248
read-write
n
0x0
0x0
PRLL5
PPG5 Reload Registers Low [BHW]
0x24C
read-write
n
0x0
0x0
PRLL6
PPG6 Reload Registers Low [BHW]
0x250
read-write
n
0x0
0x0
PRLL7
PPG7 Reload Registers Low [BHW]
0x254
read-write
n
0x0
0x0
PRLL8
PPG8 Reload Registers Low [BHW]
0x288
read-write
n
0x0
0x0
PRLL9
PPG9 Reload Registers Low [BHW]
0x28C
read-write
n
0x0
0x0
REVC0
Output Reverse Register 0 [BHW]
0x104
16
read-write
n
0x0
0x0
REV00
PPG0 Output Reverse Enable bit
0
read-write
REV01
PPG1 Output Reverse Enable bit
1
read-write
REV02
PPG2 Output Reverse Enable bit
2
read-write
REV03
PPG3 Output Reverse Enable bit
3
read-write
REV04
PPG4 Output Reverse Enable bit
4
read-write
REV05
PPG5 Output Reverse Enable bit
5
read-write
REV06
PPG6 Output Reverse Enable bit
6
read-write
REV07
PPG7 Output Reverse Enable bit
7
read-write
REV08
PPG8 Output Reverse Enable bit
8
read-write
REV09
PPG9 Output Reverse Enable bit
9
read-write
REV10
PPG10 Output Reverse Enable bit
10
read-write
REV11
PPG11 Output Reverse Enable bit
11
read-write
REV12
PPG12 Output Reverse Enable bit
12
read-write
REV13
PPG13 Output Reverse Enable bit
13
read-write
REV14
PPG14 Output Reverse Enable bit
14
read-write
REV15
PPG15 Output Reverse Enable bit
15
read-write
REVC1
Output Reverse Register 1 [BHW]
0x144
16
read-write
n
0x0
0x0
REV16
PPG16 Output Reverse Enable bit
0
read-write
REV17
PPG17 Output Reverse Enable bit
1
read-write
REV18
PPG18 Output Reverse Enable bit
2
read-write
REV19
PPG19 Output Reverse Enable bit
3
read-write
REV20
PPG20 Output Reverse Enable bit
4
read-write
REV21
PPG21 Output Reverse Enable bit
5
read-write
REV22
PPG22 Output Reverse Enable bit
6
read-write
REV23
PPG23 Output Reverse Enable bit
7
read-write
TRG0
PPG Start Register 0 [BHW]
0x100
16
read-write
n
0x0
0x0
PEN00
PPG0 Start Trigger bit
0
read-write
PEN01
PPG1 Start Trigger bit
1
read-write
PEN02
PPG2 Start Trigger bit
2
read-write
PEN03
PPG3 Start Trigger bit
3
read-write
PEN04
PPG4 Start Trigger bit
4
read-write
PEN05
PPG5 Start Trigger bit
5
read-write
PEN06
PPG6 Start Trigger bit
6
read-write
PEN07
PPG7 Start Trigger bit
7
read-write
PEN08
PPG8 Start Trigger bit
8
read-write
PEN09
PPG9 Start Trigger bit
9
read-write
PEN10
PPG10 Start Trigger bit
10
read-write
PEN11
PPG11 Start Trigger bit
11
read-write
PEN12
PPG12 Start Trigger bit
12
read-write
PEN13
PPG13 Start Trigger bit
13
read-write
PEN14
PPG14 Start Trigger bit
14
read-write
PEN15
PPG15 Start Trigger bit
15
read-write
TRG1
PPG Start Register 1 [BHW]
0x140
16
read-write
n
0x0
0x0
PEN16
PPG16 Start Trigger bit
0
read-write
PEN17
PPG17 Start Trigger bit
1
read-write
PEN18
PPG18 Start Trigger bit
2
read-write
PEN19
PPG19 Start Trigger bit
3
read-write
PEN20
PPG20 Start Trigger bit
4
read-write
PEN21
PPG21 Start Trigger bit
5
read-write
PEN22
PPG22 Start Trigger bit
6
read-write
PEN23
PPG23 Start Trigger bit
7
read-write
TTCR0
PPG Start Trigger Control Register 0 [BHW]
0x1
8
read-write
n
0x0
0x0
CS0
8-bit UP counter clock select bits for comparison
2
1
read-write
MONI0
8-bit UP counter operation state monitor bit for comparison
1
read-only
STR0
8-bit UP counter operation enable bit for comparison
0
write-only
TRG0O
PPG0 trigger stop bit
4
write-only
TRG2O
PPG2 trigger stop bit
5
write-only
TRG4O
PPG4 trigger stop bit
6
write-only
TRG6O
PPG6 trigger stop bit
7
write-only
TTCR1
PPG Start Trigger Control Register 1 [BHW]
0x21
8
read-write
n
0x0
0x0
CS1
8-bit UP counter clock select bits for comparison
2
1
read-write
MONI1
8-bit UP counter operation state monitor bit for comparison
1
read-only
STR1
8-bit UP counter operation enable bit for comparison
0
write-only
TRG1O
PPG1 trigger stop bit
4
write-only
TRG3O
PPG3 trigger stop bit
5
write-only
TRG5O
PPG5 trigger stop bit
6
write-only
TRG7O
PPG7 trigger stop bit
7
write-only
TTCR2
PPG Start Trigger Control Register 2 [BHW]
0x41
8
read-write
n
0x0
0x0
CS2
8-bit UP counter clock select bits for comparison
2
1
read-write
MONI2
8-bit UP counter operation state monitor bit for comparison
1
read-only
STR2
8-bit UP counter operation enable bit for comparison
0
write-only
TRG16O
PPG16 trigger stop bit
4
write-only
TRG18O
PPG18 trigger stop bit
5
write-only
TRG20O
PPG20 trigger stop bit
6
write-only
TRG22O
PPG22 trigger stop bit
7
write-only
QPRC0
Quadrature Position/Revolution Counter 0
QPRC
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x3C
0x4
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
QPRC0
19
QCR
QPRC Control Register [BHW]
0x18
16
read-write
n
0x0
0x0
AES
AIN detection edge selection bits
10
1
read-write
BES
BIN detection edge selection bits
12
1
read-write
CGE
Detection edge selection bits
14
1
read-write
CGSC
Count clear or gate selection bit
5
read-write
PCM
Position counter mode bits
0
1
read-write
PCRM
Position counter reset mask bits
8
1
read-write
PSTP
Position counter stop bit
4
read-write
RCM
Revolution counter mode bits
2
1
read-write
RSEL
Register function selection bit
6
read-write
SWAP
Swap bit
7
read-write
QECR
QPRC Extension Control Register [BHW]
0x1C
16
read-write
n
0x0
0x0
ORNGF
Outrange interrupt request flag bit
1
read-write
ORNGIE
Outrange interrupt enable bit
2
read-write
ORNGMD
Outrange mode selection bit
0
read-write
PEC
Phase edge change bit
3
read-write
QICRH
High-Order Bytes of QPRC Interrupt Control Register [BHW]
0x15
8
read-write
n
0x0
0x0
CDCF
Count inversion interrupt request flag bit
1
read-write
CDCIE
Count inversion interrupt enable bit
0
read-write
DIROU
Last position counter flow direction bit
3
read-only
DIRPC
Last position counter direction bit
2
read-only
QPCNRCMF
PC match and RC match interrupt request flag bit
5
read-write
QPCNRCMIE
PC match and RC match interrupt enable bit
4
read-write
QICRL
Low-Order Bytes of QPRC Interrupt Control Register [BHW]
0x14
8
read-write
n
0x0
0x0
OFDF
Overflow interrupt request flag bit
6
read-write
OUZIE
Overflow/underflow or zero index interrupt enable bit
4
read-write
QPCMF
PC match interrupt request flag bit
1
read-write
QPCMIE
PC match interrupt enable bit
0
read-write
QPRCMF
PC and RC match interrupt request flag bit
3
read-write
QPRCMIE
PC and RC match interrupt enable bit
2
read-write
UFDF
Underflow interrupt request flag bit
5
read-write
ZIIF
Zero index interrupt request flag bit
7
read-write
QMPR
QPRC Maximum Position Register [HW]
0x10
16
read-write
n
0x0
0x0
QPCCR
QPRC Position Counter Compare Register [HW]
0x8
16
read-write
n
0x0
0x0
QPCR
QPRC Position Count Register [HW]
0x0
16
read-write
n
0x0
0x0
QPRCR
QPRC Position and Revolution Counter Compare Register [HW]
0xC
16
read-write
n
0x0
0x0
QPRCRR
Quad Counter Position Rotation Count Register [BHW]
0x3C
32
read-only
n
0x0
0x0
QPCRR
Quad counter position count display bit
0
15
read-only
QRCRR
Quad counter rotation count display bit
16
15
read-only
QRCR
QPRC Revolution Count Register [HW]
0x4
16
read-write
n
0x0
0x0
QPRC0_NF
Quadrature Position/Revolution Counter 0 Noise Filter
QPRC_NF
0x0
0x0
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
NFCTLA
AIN Noise Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
AINLV
Input invert bit
4
read-write
AINMD
Mask bit
5
read-write
AINNWS
Noise filter width select bits
0
2
read-write
NFCTLB
BIN Noise Control Register [BHW]
0x4
8
read-write
n
0x0
0x0
BINLV
Input invert bit
4
read-write
BINMD
Mask bit
5
read-write
BINNWS
Noise filter width select bits
0
2
read-write
NFCTLZ
ZIN Noise Control Register [BHW]
0x8
8
read-write
n
0x0
0x0
ZINLV
Input invert bit
4
read-write
ZINMD
Mask bit
5
read-write
ZINNWS
Noise filter width select bits
0
2
read-write
QPRC1
Quadrature Position/Revolution Counter 1
QPRC
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x3C
0x4
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
QPRC1
20
QCR
QPRC Control Register [BHW]
0x18
16
read-write
n
0x0
0x0
AES
AIN detection edge selection bits
10
1
read-write
BES
BIN detection edge selection bits
12
1
read-write
CGE
Detection edge selection bits
14
1
read-write
CGSC
Count clear or gate selection bit
5
read-write
PCM
Position counter mode bits
0
1
read-write
PCRM
Position counter reset mask bits
8
1
read-write
PSTP
Position counter stop bit
4
read-write
RCM
Revolution counter mode bits
2
1
read-write
RSEL
Register function selection bit
6
read-write
SWAP
Swap bit
7
read-write
QECR
QPRC Extension Control Register [BHW]
0x1C
16
read-write
n
0x0
0x0
ORNGF
Outrange interrupt request flag bit
1
read-write
ORNGIE
Outrange interrupt enable bit
2
read-write
ORNGMD
Outrange mode selection bit
0
read-write
PEC
Phase edge change bit
3
read-write
QICRH
High-Order Bytes of QPRC Interrupt Control Register [BHW]
0x15
8
read-write
n
0x0
0x0
CDCF
Count inversion interrupt request flag bit
1
read-write
CDCIE
Count inversion interrupt enable bit
0
read-write
DIROU
Last position counter flow direction bit
3
read-only
DIRPC
Last position counter direction bit
2
read-only
QPCNRCMF
PC match and RC match interrupt request flag bit
5
read-write
QPCNRCMIE
PC match and RC match interrupt enable bit
4
read-write
QICRL
Low-Order Bytes of QPRC Interrupt Control Register [BHW]
0x14
8
read-write
n
0x0
0x0
OFDF
Overflow interrupt request flag bit
6
read-write
OUZIE
Overflow/underflow or zero index interrupt enable bit
4
read-write
QPCMF
PC match interrupt request flag bit
1
read-write
QPCMIE
PC match interrupt enable bit
0
read-write
QPRCMF
PC and RC match interrupt request flag bit
3
read-write
QPRCMIE
PC and RC match interrupt enable bit
2
read-write
UFDF
Underflow interrupt request flag bit
5
read-write
ZIIF
Zero index interrupt request flag bit
7
read-write
QMPR
QPRC Maximum Position Register [HW]
0x10
16
read-write
n
0x0
0x0
QPCCR
QPRC Position Counter Compare Register [HW]
0x8
16
read-write
n
0x0
0x0
QPCR
QPRC Position Count Register [HW]
0x0
16
read-write
n
0x0
0x0
QPRCR
QPRC Position and Revolution Counter Compare Register [HW]
0xC
16
read-write
n
0x0
0x0
QPRCRR
Quad Counter Position Rotation Count Register [BHW]
0x3C
32
read-only
n
0x0
0x0
QPCRR
Quad counter position count display bit
0
15
read-only
QRCRR
Quad counter rotation count display bit
16
15
read-only
QRCR
QPRC Revolution Count Register [HW]
0x4
16
read-write
n
0x0
0x0
QPRC1_NF
Quadrature Position/Revolution Counter 1 Noise Filter
QPRC_NF
0x0
0x0
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
NFCTLA
AIN Noise Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
AINLV
Input invert bit
4
read-write
AINMD
Mask bit
5
read-write
AINNWS
Noise filter width select bits
0
2
read-write
NFCTLB
BIN Noise Control Register [BHW]
0x4
8
read-write
n
0x0
0x0
BINLV
Input invert bit
4
read-write
BINMD
Mask bit
5
read-write
BINNWS
Noise filter width select bits
0
2
read-write
NFCTLZ
ZIN Noise Control Register [BHW]
0x8
8
read-write
n
0x0
0x0
ZINLV
Input invert bit
4
read-write
ZINMD
Mask bit
5
read-write
ZINNWS
Noise filter width select bits
0
2
read-write
QPRC2
Quadrature Position/Revolution Counter 2
QPRC
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x3C
0x4
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
QPRC2
96
QCR
QPRC Control Register [BHW]
0x18
16
read-write
n
0x0
0x0
AES
AIN detection edge selection bits
10
1
read-write
BES
BIN detection edge selection bits
12
1
read-write
CGE
Detection edge selection bits
14
1
read-write
CGSC
Count clear or gate selection bit
5
read-write
PCM
Position counter mode bits
0
1
read-write
PCRM
Position counter reset mask bits
8
1
read-write
PSTP
Position counter stop bit
4
read-write
RCM
Revolution counter mode bits
2
1
read-write
RSEL
Register function selection bit
6
read-write
SWAP
Swap bit
7
read-write
QECR
QPRC Extension Control Register [BHW]
0x1C
16
read-write
n
0x0
0x0
ORNGF
Outrange interrupt request flag bit
1
read-write
ORNGIE
Outrange interrupt enable bit
2
read-write
ORNGMD
Outrange mode selection bit
0
read-write
PEC
Phase edge change bit
3
read-write
QICRH
High-Order Bytes of QPRC Interrupt Control Register [BHW]
0x15
8
read-write
n
0x0
0x0
CDCF
Count inversion interrupt request flag bit
1
read-write
CDCIE
Count inversion interrupt enable bit
0
read-write
DIROU
Last position counter flow direction bit
3
read-only
DIRPC
Last position counter direction bit
2
read-only
QPCNRCMF
PC match and RC match interrupt request flag bit
5
read-write
QPCNRCMIE
PC match and RC match interrupt enable bit
4
read-write
QICRL
Low-Order Bytes of QPRC Interrupt Control Register [BHW]
0x14
8
read-write
n
0x0
0x0
OFDF
Overflow interrupt request flag bit
6
read-write
OUZIE
Overflow/underflow or zero index interrupt enable bit
4
read-write
QPCMF
PC match interrupt request flag bit
1
read-write
QPCMIE
PC match interrupt enable bit
0
read-write
QPRCMF
PC and RC match interrupt request flag bit
3
read-write
QPRCMIE
PC and RC match interrupt enable bit
2
read-write
UFDF
Underflow interrupt request flag bit
5
read-write
ZIIF
Zero index interrupt request flag bit
7
read-write
QMPR
QPRC Maximum Position Register [HW]
0x10
16
read-write
n
0x0
0x0
QPCCR
QPRC Position Counter Compare Register [HW]
0x8
16
read-write
n
0x0
0x0
QPCR
QPRC Position Count Register [HW]
0x0
16
read-write
n
0x0
0x0
QPRCR
QPRC Position and Revolution Counter Compare Register [HW]
0xC
16
read-write
n
0x0
0x0
QPRCRR
Quad Counter Position Rotation Count Register [BHW]
0x3C
32
read-only
n
0x0
0x0
QPCRR
Quad counter position count display bit
0
15
read-only
QRCRR
Quad counter rotation count display bit
16
15
read-only
QRCR
QPRC Revolution Count Register [HW]
0x4
16
read-write
n
0x0
0x0
QPRC2_NF
Quadrature Position/Revolution Counter 2 Noise Filter
QPRC_NF
0x0
0x0
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
NFCTLA
AIN Noise Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
AINLV
Input invert bit
4
read-write
AINMD
Mask bit
5
read-write
AINNWS
Noise filter width select bits
0
2
read-write
NFCTLB
BIN Noise Control Register [BHW]
0x4
8
read-write
n
0x0
0x0
BINLV
Input invert bit
4
read-write
BINMD
Mask bit
5
read-write
BINNWS
Noise filter width select bits
0
2
read-write
NFCTLZ
ZIN Noise Control Register [BHW]
0x8
8
read-write
n
0x0
0x0
ZINLV
Input invert bit
4
read-write
ZINMD
Mask bit
5
read-write
ZINNWS
Noise filter width select bits
0
2
read-write
QPRC3
Quadrature Position/Revolution Counter 3
QPRC
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x3C
0x4
registers
n
0x4
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
QPRC3
97
QCR
QPRC Control Register [BHW]
0x18
16
read-write
n
0x0
0x0
AES
AIN detection edge selection bits
10
1
read-write
BES
BIN detection edge selection bits
12
1
read-write
CGE
Detection edge selection bits
14
1
read-write
CGSC
Count clear or gate selection bit
5
read-write
PCM
Position counter mode bits
0
1
read-write
PCRM
Position counter reset mask bits
8
1
read-write
PSTP
Position counter stop bit
4
read-write
RCM
Revolution counter mode bits
2
1
read-write
RSEL
Register function selection bit
6
read-write
SWAP
Swap bit
7
read-write
QECR
QPRC Extension Control Register [BHW]
0x1C
16
read-write
n
0x0
0x0
ORNGF
Outrange interrupt request flag bit
1
read-write
ORNGIE
Outrange interrupt enable bit
2
read-write
ORNGMD
Outrange mode selection bit
0
read-write
PEC
Phase edge change bit
3
read-write
QICRH
High-Order Bytes of QPRC Interrupt Control Register [BHW]
0x15
8
read-write
n
0x0
0x0
CDCF
Count inversion interrupt request flag bit
1
read-write
CDCIE
Count inversion interrupt enable bit
0
read-write
DIROU
Last position counter flow direction bit
3
read-only
DIRPC
Last position counter direction bit
2
read-only
QPCNRCMF
PC match and RC match interrupt request flag bit
5
read-write
QPCNRCMIE
PC match and RC match interrupt enable bit
4
read-write
QICRL
Low-Order Bytes of QPRC Interrupt Control Register [BHW]
0x14
8
read-write
n
0x0
0x0
OFDF
Overflow interrupt request flag bit
6
read-write
OUZIE
Overflow/underflow or zero index interrupt enable bit
4
read-write
QPCMF
PC match interrupt request flag bit
1
read-write
QPCMIE
PC match interrupt enable bit
0
read-write
QPRCMF
PC and RC match interrupt request flag bit
3
read-write
QPRCMIE
PC and RC match interrupt enable bit
2
read-write
UFDF
Underflow interrupt request flag bit
5
read-write
ZIIF
Zero index interrupt request flag bit
7
read-write
QMPR
QPRC Maximum Position Register [HW]
0x10
16
read-write
n
0x0
0x0
QPCCR
QPRC Position Counter Compare Register [HW]
0x8
16
read-write
n
0x0
0x0
QPCR
QPRC Position Count Register [HW]
0x0
16
read-write
n
0x0
0x0
QPRCR
QPRC Position and Revolution Counter Compare Register [HW]
0xC
16
read-write
n
0x0
0x0
QPRCRR
Quad Counter Position Rotation Count Register [BHW]
0x3C
32
read-only
n
0x0
0x0
QPCRR
Quad counter position count display bit
0
15
read-only
QRCRR
Quad counter rotation count display bit
16
15
read-only
QRCR
QPRC Revolution Count Register [HW]
0x4
16
read-write
n
0x0
0x0
QPRC3_NF
Quadrature Position/Revolution Counter 3 Noise Filter
QPRC_NF
0x0
0x0
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
NFCTLA
AIN Noise Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
AINLV
Input invert bit
4
read-write
AINMD
Mask bit
5
read-write
AINNWS
Noise filter width select bits
0
2
read-write
NFCTLB
BIN Noise Control Register [BHW]
0x4
8
read-write
n
0x0
0x0
BINLV
Input invert bit
4
read-write
BINMD
Mask bit
5
read-write
BINNWS
Noise filter width select bits
0
2
read-write
NFCTLZ
ZIN Noise Control Register [BHW]
0x8
8
read-write
n
0x0
0x0
ZINLV
Input invert bit
4
read-write
ZINMD
Mask bit
5
read-write
ZINNWS
Noise filter width select bits
0
2
read-write
RTC
REAL-TIME CLOCK
RTC
0x0
0x0
0x13
registers
n
0x15
0x3
registers
n
0x19
0x2
registers
n
0x1C
0x4
registers
n
0x20
0x2
registers
n
0x24
0x3
registers
n
0x28
0x2
registers
n
0x2C
0x1
registers
n
0x30
0x1
registers
n
RTC
50
ALDR
Alarm Date Register [BHW]
0x17
8
read-write
n
0x0
0x0
AD
The first digit of the alarm-set date
0
3
read-write
TAD
The second digit of the alarm-set date
4
1
read-write
ALHR
Alarm Hour Register [BHW]
0x16
8
read-write
n
0x0
0x0
AH
The first digit of the alarm-set hour
0
3
read-write
TAH
The second digit of the alarm-set hour
4
1
read-write
ALMIR
Alarm Minute Register [BHW]
0x15
8
read-write
n
0x0
0x0
AMI
The first digit of the alarm-set minute
0
3
read-write
TAMI
The second digit of the alarm-set minute
4
2
read-write
ALMOR
Alarm Month Register [BHW]
0x19
8
read-write
n
0x0
0x0
AMO
The first digit of the alarm-set month
0
3
read-write
TAMO0
The second digit of the alarm-set month
4
read-write
ALYR
Alarm Years Register [BHW]
0x1A
8
read-write
n
0x0
0x0
AY
The first digit of the alarm-set year
0
3
read-write
TAY
The second digit of the alarm-set year
4
3
read-write
WTBR
Counter Cycle Setting Register [BHW]
0x8
32
read-write
n
0x0
0x0
BR
Counter Cycle Setting bits
0
23
read-write
WTCAL
Frequency Correction Value Setting Register [BHW]
0x24
16
read-write
n
0x0
0x0
WTCAL
Frequency correction value setting bits
0
9
read-write
WTCALEN
Frequency Correction Enable Register [BHW]
0x26
8
read-write
n
0x0
0x0
WTCALEN
Frequency correction enable bit
0
read-write
WTCALPRD
Frequency Correction Cycle Setting Register [BHW]
0x2C
8
read-write
n
0x0
0x0
WTCALPRD
frequency correction value
0
5
read-write
WTCLKM
Selection Clock Status Register [BHW]
0x21
8
read-only
n
0x0
0x0
WTCLKM
Clock selection status bits
0
1
read-only
WTCLKS
Clock Selection Register [BHW]
0x20
8
read-write
n
0x0
0x0
WTCLKS
Input clock selection bit
0
read-write
WTCOSEL
RTCCO Output Selection Register [BHW]
0x30
8
read-write
n
0x0
0x0
WTCOSEL
RTCCO output selection bit
0
read-write
WTCR1
Control Register 1 [BHW]
0x0
32
read-write
n
0x0
0x0
BUSY
Busy bit
6
read-only
DEN
Alarm date register enable bit
10
read-write
HEN
Alarm hour register enable bit
9
read-write
INTALI
Alarm interrupt flag bit
21
read-write
INTALIE
Alarm interrupt enable bit
29
read-write
INTCRI
Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit
23
read-write
INTCRIE
Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit
31
read-write
INTERI
Time rewrite error interrupt flag bit
22
read-write
INTERIE
Time rewrite error interrupt enable bit
30
read-write
INTHI
1-hour interrupt flag bit
19
read-write
INTHIE
1-hour interrupt enable bit
27
read-write
INTMI
1-minute interrupt flag bit
18
read-write
INTMIE
1-minute interrupt enable bit
26
read-write
INTSI
1-second interrupt flag bit
17
read-write
INTSIE
1-second interrupt enable bit
25
read-write
INTSSI
0.5-second interrupt flag bit
16
read-write
INTSSIE
0.5-second interrupt enable bit
24
read-write
INTTMI
Timer interrupt flag bit
20
read-write
INTTMIE
Timer interrupt enable bit
28
read-write
MIEN
Alarm minute register enable bit
8
read-write
MOEN
Alarm month register enable bit
11
read-write
RUN
RTC count block operation bit
2
read-only
SCRST
Sub second generation/1-second generation counter reset bit
5
read-write
SCST
1-second clock output stop bit
4
read-write
SRST
RTC reset bit
3
read-write
ST
Start bit
0
read-write
YEN
Alarm year register enable bit
12
read-write
WTCR2
Control Register 2 [BHW]
0x4
32
read-write
n
0x0
0x0
CREAD
Year/month/date/hour/minute/second/day of the week counter value read control bit
0
read-write
TMEN
Timer counter control bit
9
read-write
TMRUN
Timer counter operation bit
10
read-only
TMST
Timer counter start bit
8
read-write
WTDIV
Divider Ratio Setting Register [BHW]
0x28
8
read-write
n
0x0
0x0
WTDIV
Divider ratio setting bits
0
3
read-write
WTDIVEN
Divider Output Enable Register [BHW]
0x29
8
read-write
n
0x0
0x0
WTDIVEN
Divider enable bit
0
read-write
WTDIVRDY
Divider status bit
1
read-only
WTDR
Date Register [BHW]
0xF
8
read-write
n
0x0
0x0
D
The first digit of the date
0
3
read-write
TD
The second digit of the date
4
1
read-write
WTDW
Day of the Week Register [BHW]
0x10
8
read-write
n
0x0
0x0
DW
Day of the week
0
2
read-write
WTHR
Hour register [BHW]
0xE
8
read-write
n
0x0
0x0
H
The first digit of the hour
0
3
read-write
TH
The second digit of the hour
4
1
read-write
WTMIR
Minute Register [BHW]
0xD
8
read-write
n
0x0
0x0
MI
The first digit of the minute
0
3
read-write
TMI
The second digit of the minute
4
2
read-write
WTMOR
Month Register [BHW]
0x11
8
read-write
n
0x0
0x0
MO
The first digit of the month
0
3
read-write
TMO0
The second digit in the month
4
read-write
WTSR
Second Register [BHW]
0xC
8
read-write
n
0x0
0x0
S
The first digit of the second
0
3
read-write
TS
The second digit of the second
4
2
read-write
WTTR
Timer Setting Register [BHW]
0x1C
32
read-write
n
0x0
0x0
TM
Timer setting register
0
17
read-write
WTYR
Year Register [BHW]
0x12
8
read-write
n
0x0
0x0
TY
The second digit of the year
4
3
read-write
Y
The first digit of the year
0
3
read-write
SBSSR
Software-based Simultaneous Startup Register
SBSSR
0x0
0xFC
0x2
registers
n
BTSSSR
Software-based Simultaneous Startup Register [BHW]
0xFC
16
write-only
n
0x0
0x0
SSSR0
Software-based simultaneous startup bit of Ch.0
0
write-only
SSSR1
Software-based simultaneous startup bit of Ch.1
1
write-only
SSSR10
Software-based simultaneous startup bit of Ch.10
10
write-only
SSSR11
Software-based simultaneous startup bit of Ch.11
11
write-only
SSSR12
Software-based simultaneous startup bit of Ch.12
12
write-only
SSSR13
Software-based simultaneous startup bit of Ch.13
13
write-only
SSSR14
Software-based simultaneous startup bit of Ch.14
14
write-only
SSSR15
Software-based simultaneous startup bit of Ch.15
15
write-only
SSSR2
Software-based simultaneous startup bit of Ch.2
2
write-only
SSSR3
Software-based simultaneous startup bit of Ch.3
3
write-only
SSSR4
Software-based simultaneous startup bit of Ch.4
4
write-only
SSSR5
Software-based simultaneous startup bit of Ch.5
5
write-only
SSSR6
Software-based simultaneous startup bit of Ch.6
6
write-only
SSSR7
Software-based simultaneous startup bit of Ch.7
7
write-only
SSSR8
Software-based simultaneous startup bit of Ch.8
8
write-only
SSSR9
Software-based simultaneous startup bit of Ch.9
9
write-only
SMCIF0
Smart Card Interface 0 Registers
SMCIF
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x2
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
ICC0_1
117
BAUDRATE
Baud Rate Register [HW]
0x14
16
read-write
n
0x0
0x0
BRREG
Baud rate register bits
0
14
read-write
LITTLESTEP
Little step bit for baud rate
15
read-write
CARDCLOCK
Card Clock Frequency Register [HW]
0x10
16
read-write
n
0x0
0x0
CLKDIVIDER
Card clock frequency divider
0
15
read-write
DATA
Data Register [HW]
0xC
16
read-write
n
0x0
0x0
DATA
Transmit/Received data
0
8
read-write
DATA_FIFO
FIFO Access Register [HW]
0x24
16
read-write
n
0x0
0x0
DATA
Transmit/Received data
0
8
read-write
FIFO_CLEAR_MSB_READ
Read FIFO Clear Register [HW]
0x38
16
read-write
n
0x0
0x0
CLRRDFIFO
Read FIFO clear bit
0
read-write
FIFO_CLEAR_MSB_WRITE
Write FIFO Clear Register [HW]
0x34
16
read-write
n
0x0
0x0
CLRWRFIFO
Write FIFO clear bit
0
read-write
FIFO_LEVEL_READ
Read FIFO Level Register [HW]
0x28
16
read-only
n
0x0
0x0
FIFORDLEVEL
Read FIFO level
0
15
read-only
FIFO_LEVEL_WRITE
Write FIFO Level Register [HW]
0x2C
16
read-only
n
0x0
0x0
FIFOWRLEVEL
Read FIFO level
0
15
read-only
FIFO_MODE
FIFO Mode Register [HW]
0x30
16
read-write
n
0x0
0x0
FIFOEN
FIFO enable bit
0
read-write
RDFIFOIRQEN
Read FIFO full interrupt enable bit
3
read-write
RDFIFOLEVEL
Read FIFO level
12
3
read-write
RDFIFOOVRIRQEN
Read FIFO overflow interrupt enable bit
1
read-write
WRFIFOIRQEN
Write FIFO empty interrupt enable bit
2
read-write
WRFIFOLEVEL
Write FIFO level
8
3
read-write
GLOBALCONTROL1
Global Control Register 1 [HW]
0x0
16
read-write
n
0x0
0x0
CKMOD
Clock generation mode select bit
10
read-write
FRM0
Clock generation mode select bit
1
read-write
FRM1
Data frame coding style select bit
2
read-write
GUAEN
Guard timer enable bit
12
read-write
IDTSC
Idle timer clock select bit
14
read-write
IOMOD
Data generation mode select bit
9
read-write
MASKCAEVENT
Card event detect interrupt enable bit
7
read-write
MASKITEXP
Idle timer expired interrupt enable bit
8
read-write
MASKRXFUL
Receive data register full interrupt enable bit
4
read-write
MASKSTI
Start bit detect interrupt enable bit
6
read-write
MASKTXEMP
Transmit data register empty interrupt enable bit
5
read-write
MODE8N1
Clock generation mode select bit
3
read-write
PARITY
Odd/Even parity select bit
0
read-write
RESND
Transmiter and receiver resend function enable bit
11
read-write
STIDT
Start idle timer bit
13
read-write
GLOBALCONTROL2
Global Control Register 2 [HW]
0x20
16
write-only
n
0x0
0x0
ICCDISABLE
ICC disable/enable bit
3
read-write
INVDATAOUT
Output inversion enable bit
1
read-write
RX8N1
Serial data output enable bit
0
read-write
GUARDTIMER
Guard Timer Register [HW]
0x18
16
read-write
n
0x0
0x0
GTREG
Guard time in ETUs
0
7
read-write
IDLETIMER
Idle Timer Register [HW]
0x1C
16
read-write
n
0x0
0x0
IDTREG
Reload value for idle timer
0
15
read-write
IRQ_STATUS
Interrupt Status Register [HW]
0x40
16
read-only
n
0x0
0x0
CARDEVENTIRQ
Card event interrupt flag bit
4
read-only
IDTEXPIRQ
Idle timer expired interrupt flag bit
3
read-only
RDFIFOIRQ
Read FIFO full interrupt flag bit
2
read-only
RDFIFOOVRIRQ
Read FIFO overflow interrupt flag bit
0
read-only
RXFULIRQ
Received data register full interrupt flag bit
7
read-only
RXSTBIIRQ
Received start bit interrupt flag bit
5
read-only
TXEMPIRQ
Transmit data register empty interrupt flag bit
6
read-only
WRFIFOIRQ
Write FIFO empty interrupt flag bit
1
read-only
PORTCONTROL
Port Control Register [HW]
0x8
16
read-write
n
0x0
0x0
CLKOUTEN
ICx_CLK output enable bit
12
read-write
CLKPT
ICx_CLK output value
6
read-write
IO1
Level on ICx_DATA pin
2
read-write
IO1EN
ICx_DATA output enable control bit
4
read-write
RST
ICx_RST output value
7
read-write
RSTOUTEN
ICx_RST output enable bit
13
read-write
TRIMOD
ICx_DATA output enable generation mode select bit
0
read-write
VCCEN
ICx_VCC output value
8
read-write
VCCOUTEN
ICx_VCC output enable bit
14
read-write
VPEN
ICx_VPEN output value
9
read-write
VPENOUTEN
ICx_VPEN output enable bit
15
read-write
STATUS
Status Register [HW]
0x4
16
read-only
n
0x0
0x0
CARDDETECT
Level on ICx_CIN input pin
4
read-only
CARDEVENT
Card event flag
5
read-only
IDTRUN
Idle timer running flag
7
read-only
RDFIFOFUL
Read FIFO full flag bit
9
read-only
RDFIFOOVR
Read FIFO overflow flag
8
read-only
RECOFL
Received data register overflow flag
6
read-only
RXACT
Receiver status flag
2
read-only
RXFUL
Received data register status flag
1
read-only
RXRESEND
Receiver resend flag bit
13
read-only
RXSTARTERR
Received start bit error flag bit
11
read-only
TXACT
Transmitter status flag
3
read-only
TXEMP
Transmit data register status flag
0
read-only
TXRESEND
Transmitter resend flag bit
12
read-only
WRFIFOEMP
Write FIFO empty flag bit
10
read-only
SMCIF1
Smart Card Interface 1 Registers
SMCIF
0x0
0x0
0x2
registers
n
0x10
0x2
registers
n
0x14
0x2
registers
n
0x18
0x2
registers
n
0x1C
0x2
registers
n
0x20
0x2
registers
n
0x24
0x2
registers
n
0x28
0x2
registers
n
0x2C
0x2
registers
n
0x30
0x2
registers
n
0x34
0x2
registers
n
0x38
0x2
registers
n
0x3C
0x2
registers
n
0x4
0x2
registers
n
0x40
0x2
registers
n
0x8
0x2
registers
n
0xC
0x2
registers
n
BAUDRATE
Baud Rate Register [HW]
0x14
16
read-write
n
0x0
0x0
BRREG
Baud rate register bits
0
14
read-write
LITTLESTEP
Little step bit for baud rate
15
read-write
CARDCLOCK
Card Clock Frequency Register [HW]
0x10
16
read-write
n
0x0
0x0
CLKDIVIDER
Card clock frequency divider
0
15
read-write
DATA
Data Register [HW]
0xC
16
read-write
n
0x0
0x0
DATA
Transmit/Received data
0
8
read-write
DATA_FIFO
FIFO Access Register [HW]
0x24
16
read-write
n
0x0
0x0
DATA
Transmit/Received data
0
8
read-write
FIFO_CLEAR_MSB_READ
Read FIFO Clear Register [HW]
0x38
16
read-write
n
0x0
0x0
CLRRDFIFO
Read FIFO clear bit
0
read-write
FIFO_CLEAR_MSB_WRITE
Write FIFO Clear Register [HW]
0x34
16
read-write
n
0x0
0x0
CLRWRFIFO
Write FIFO clear bit
0
read-write
FIFO_LEVEL_READ
Read FIFO Level Register [HW]
0x28
16
read-only
n
0x0
0x0
FIFORDLEVEL
Read FIFO level
0
15
read-only
FIFO_LEVEL_WRITE
Write FIFO Level Register [HW]
0x2C
16
read-only
n
0x0
0x0
FIFOWRLEVEL
Read FIFO level
0
15
read-only
FIFO_MODE
FIFO Mode Register [HW]
0x30
16
read-write
n
0x0
0x0
FIFOEN
FIFO enable bit
0
read-write
RDFIFOIRQEN
Read FIFO full interrupt enable bit
3
read-write
RDFIFOLEVEL
Read FIFO level
12
3
read-write
RDFIFOOVRIRQEN
Read FIFO overflow interrupt enable bit
1
read-write
WRFIFOIRQEN
Write FIFO empty interrupt enable bit
2
read-write
WRFIFOLEVEL
Write FIFO level
8
3
read-write
GLOBALCONTROL1
Global Control Register 1 [HW]
0x0
16
read-write
n
0x0
0x0
CKMOD
Clock generation mode select bit
10
read-write
FRM0
Clock generation mode select bit
1
read-write
FRM1
Data frame coding style select bit
2
read-write
GUAEN
Guard timer enable bit
12
read-write
IDTSC
Idle timer clock select bit
14
read-write
IOMOD
Data generation mode select bit
9
read-write
MASKCAEVENT
Card event detect interrupt enable bit
7
read-write
MASKITEXP
Idle timer expired interrupt enable bit
8
read-write
MASKRXFUL
Receive data register full interrupt enable bit
4
read-write
MASKSTI
Start bit detect interrupt enable bit
6
read-write
MASKTXEMP
Transmit data register empty interrupt enable bit
5
read-write
MODE8N1
Clock generation mode select bit
3
read-write
PARITY
Odd/Even parity select bit
0
read-write
RESND
Transmiter and receiver resend function enable bit
11
read-write
STIDT
Start idle timer bit
13
read-write
GLOBALCONTROL2
Global Control Register 2 [HW]
0x20
16
write-only
n
0x0
0x0
ICCDISABLE
ICC disable/enable bit
3
read-write
INVDATAOUT
Output inversion enable bit
1
read-write
RX8N1
Serial data output enable bit
0
read-write
GUARDTIMER
Guard Timer Register [HW]
0x18
16
read-write
n
0x0
0x0
GTREG
Guard time in ETUs
0
7
read-write
IDLETIMER
Idle Timer Register [HW]
0x1C
16
read-write
n
0x0
0x0
IDTREG
Reload value for idle timer
0
15
read-write
IRQ_STATUS
Interrupt Status Register [HW]
0x40
16
read-only
n
0x0
0x0
CARDEVENTIRQ
Card event interrupt flag bit
4
read-only
IDTEXPIRQ
Idle timer expired interrupt flag bit
3
read-only
RDFIFOIRQ
Read FIFO full interrupt flag bit
2
read-only
RDFIFOOVRIRQ
Read FIFO overflow interrupt flag bit
0
read-only
RXFULIRQ
Received data register full interrupt flag bit
7
read-only
RXSTBIIRQ
Received start bit interrupt flag bit
5
read-only
TXEMPIRQ
Transmit data register empty interrupt flag bit
6
read-only
WRFIFOIRQ
Write FIFO empty interrupt flag bit
1
read-only
PORTCONTROL
Port Control Register [HW]
0x8
16
read-write
n
0x0
0x0
CLKOUTEN
ICx_CLK output enable bit
12
read-write
CLKPT
ICx_CLK output value
6
read-write
IO1
Level on ICx_DATA pin
2
read-write
IO1EN
ICx_DATA output enable control bit
4
read-write
RST
ICx_RST output value
7
read-write
RSTOUTEN
ICx_RST output enable bit
13
read-write
TRIMOD
ICx_DATA output enable generation mode select bit
0
read-write
VCCEN
ICx_VCC output value
8
read-write
VCCOUTEN
ICx_VCC output enable bit
14
read-write
VPEN
ICx_VPEN output value
9
read-write
VPENOUTEN
ICx_VPEN output enable bit
15
read-write
STATUS
Status Register [HW]
0x4
16
read-only
n
0x0
0x0
CARDDETECT
Level on ICx_CIN input pin
4
read-only
CARDEVENT
Card event flag
5
read-only
IDTRUN
Idle timer running flag
7
read-only
RDFIFOFUL
Read FIFO full flag bit
9
read-only
RDFIFOOVR
Read FIFO overflow flag
8
read-only
RECOFL
Received data register overflow flag
6
read-only
RXACT
Receiver status flag
2
read-only
RXFUL
Received data register status flag
1
read-only
RXRESEND
Receiver resend flag bit
13
read-only
RXSTARTERR
Received start bit error flag bit
11
read-only
TXACT
Transmitter status flag
3
read-only
TXEMP
Transmit data register status flag
0
read-only
TXRESEND
Transmitter resend flag bit
12
read-only
WRFIFOEMP
Write FIFO empty flag bit
10
read-only
SWWDT
Software Watchdog Timer
SWWDT
0x0
0x0
0x14
registers
n
0x18
0x4
registers
n
0xC00
0x4
registers
n
SWDT
1
WDOGCONTROL
Software Watchdog Timer Control Register [W]
0x8
32
read-write
n
0x0
0x0
INTEN
Interrupt and counter enable bit of the software watchdog
0
read-write
RESEN
Reset enable bit of the software watchdog
1
read-write
SPM
Software Watchdog window watchdog mode enable bit
4
read-write
TWD
Timing window setting bit of the software watchdog
2
1
read-write
WDOGINTCLR
Software Watchdog Timer Clear Register [W]
0xC
32
read-write
n
0x0
0x0
WDOGLOAD
Software Watchdog Timer Load Register [W]
0x0
32
read-write
n
0x0
0x0
WDOGLOCK
Software Watchdog Timer Lock Register [W]
0xC00
32
read-write
n
0x0
0x0
WDOGRIS
Software Watchdog Timer Interrupt Status Register [W]
0x10
32
read-only
n
0x0
0x0
RIS
Software watchdog interrupt status bit
0
read-only
WDOGSPMC
Software Watchdog Timer Window Watchdog Mode Control Register [W]
0x18
32
read-write
n
0x0
0x0
TGR
Software watchdog trigger type bit
0
read-write
WDOGVALUE
Software Watchdog Timer Value Register [W]
0x4
32
read-only
n
0x0
0x0
UNIQUE_ID
Unique ID
UNIQUE_ID
0x0
0x0
0x4
registers
n
0x4
0x4
registers
n
UIDR0
Unique ID Register 0 [W]
0x0
32
read-only
n
0x0
0x0
UID
Unique ID 27 through 0
4
27
read-only
UIDR1
Unique ID Register 1 [W]
0x4
32
read-only
n
0x0
0x0
UID
Unique ID 40 through 28
0
12
read-only
USB0
USB0 Function
USB
0x0
0x2100
0x2
registers
n
0x2104
0x2
registers
n
0x2108
0x2
registers
n
0x210C
0x2
registers
n
0x2110
0x2
registers
n
0x2114
0x2
registers
n
0x2118
0x2
registers
n
0x211C
0x1
registers
n
0x2120
0x2
registers
n
0x2124
0x2
registers
n
0x2128
0x2
registers
n
0x212C
0x2
registers
n
0x2130
0x2
registers
n
0x2134
0x2
registers
n
0x2138
0x2
registers
n
0x213C
0x2
registers
n
0x2140
0x2
registers
n
0x2144
0x2
registers
n
0x2148
0x2
registers
n
0x214C
0x2
registers
n
0x2150
0x2
registers
n
0x2154
0x2
registers
n
0x2158
0x2
registers
n
0x215C
0x2
registers
n
0x2160
0x2
registers
n
0x2164
0x2
registers
n
0x2168
0x2
registers
n
0x216C
0x2
registers
n
0x2170
0x2
registers
n
0x2174
0x2
registers
n
USB0_F
78
USB0_H_F
79
EP0C
EP0 Control Register [HW]
0x2124
16
read-write
n
0x0
0x0
PKS
Packet Size Endpoint 0 Setting bits
0
6
read-write
STAL
Endpoint 0 Stall Setting bit
9
read-write
EP0DT
EP0 Data Register [BHW]
0x2160
16
read-write
n
0x0
0x0
BFDT
Endpoint Send/Receive Buffer Data
0
15
read-write
EP0IS
EP0I Status Register [HW]
0x2144
16
read-write
n
0x0
0x0
BFINI
Send Buffer Initialization bit
15
read-write
DRQI
Send/Receive Data Interrupt Request bit
10
read-write
DRQIIE
Send Data Interrupt Enable bit
14
read-write
EP0OS
EP0O Status Register [HW]
0x2148
16
read-write
n
0x0
0x0
BFINI
Receive Buffer Initialization bit
15
read-write
DRQO
Receive Data Interrupt Request bit
10
read-write
DRQOIE
Receive Data Interrupt Enable bit
14
read-write
SIZE
Packet Size Indication bit
0
6
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP1C
EP1 Control Register [HW]
0x2128
16
read-write
n
0x0
0x0
DIR
Endpoint Transfer Direction Select bit
12
read-write
DMAE
DMA Automatic Transfer Enable bit
11
read-write
EPEN
Endpoint Enable bit
15
read-write
NULE
Null Automatic Transfer Enable bit
10
read-write
PKS
Packet Size Setting bits
0
8
read-write
STAL
Endpoint Stall Setting bit
9
read-write
TYPE
Endpoint Transfer Type Select bits
13
1
read-write
EP1DT
EP1 Data Register [BHW]
0x2164
read-write
n
0x0
0x0
EP1S
EP1 Status Register [HW]
0x214C
16
read-write
n
0x0
0x0
BFINI
Send/Receive Buffer Initialization bit
15
read-write
BUSY
Busy Flag bit
11
read-only
DRQ
Packet Transfer Interrupt Request bit
10
read-write
DRQIE
Packet Transfer Interrupt Enable bit
14
read-write
SIZE
packet SIZE
0
8
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP2C
EP2 Control Register [HW]
0x212C
16
read-write
n
0x0
0x0
DIR
Endpoint Transfer Direction Select bit
12
read-write
DMAE
DMA Automatic Transfer Enable bit
11
read-write
EPEN
Endpoint Enable bit
15
read-write
NULE
Null Automatic Transfer Enable bit
10
read-write
PKS
Packet Size Setting bits
0
6
read-write
STAL
Endpoint Stall Setting bit
9
read-write
TYPE
Endpoint Transfer Type Select bits
13
1
read-write
EP2DT
EP2 Data Register [BHW]
0x2168
read-write
n
0x0
0x0
EP2S
EP2 Status Register [HW]
0x2150
16
read-write
n
0x0
0x0
BFINI
Send/Receive Buffer Initialization bit
15
read-write
BUSY
Busy Flag bit
11
read-only
DRQ
Packet Transfer Interrupt Request bit
10
read-write
DRQIE
Packet Transfer Interrupt Enable bit
14
read-write
SIZE
packet SIZE
0
6
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP3C
EP3 Control Register [HW]
0x2130
read-write
n
0x0
0x0
EP3DT
EP3 Data Register [BHW]
0x216C
read-write
n
0x0
0x0
EP3S
EP3 Status Register [HW]
0x2154
read-write
n
0x0
0x0
EP4C
EP4 Control Register [HW]
0x2134
read-write
n
0x0
0x0
EP4DT
EP4 Data Register [BHW]
0x2170
read-write
n
0x0
0x0
EP4S
EP4 Status Register [HW]
0x2158
read-write
n
0x0
0x0
EP5C
EP5 Control Register [HW]
0x2138
read-write
n
0x0
0x0
EP5DT
EP5 Data Register [BHW]
0x2174
read-write
n
0x0
0x0
EP5S
EP5 Status Register [HW]
0x215C
read-write
n
0x0
0x0
HADR
Host Address Register [BHW]
0x2111
8
read-write
n
0x0
0x0
ADDRESS
Host Address
0
6
read-write
HCNT
Host Control Register [BHW]
0x2100
16
read-write
n
0x0
0x0
CANCEL
token cancellation enable bit
9
read-write
CMPIRE
token completion interrupt enable bit
5
read-write
CNNIRE
device connection detection interrupt enable bit
4
read-write
DIRE
device disconnection detection interrupt enable bit
3
read-write
HOST
host mode bit
0
read-write
RETRY
retry enable bit
8
read-write
RWKIRE
resume interrupt enable bit
7
read-write
SOFIRE
SOF interrupt enable bit
2
read-write
SOFSTEP
SOF interrupt occurrence selection bit
10
read-write
URIRE
bus reset interrupt enable bit
6
read-write
URST
bus reset bit
1
read-write
HEOF
EOF Setup Register [BHW]
0x2114
16
read-write
n
0x0
0x0
HEOF
End Frame
0
13
read-write
HERR
Host Error Status Register [BHW]
0x2105
8
read-write
n
0x0
0x0
CRC
CRC error flag
4
read-write
HS
handshake status flags
0
1
read-write
LSTSOF
lost SOF flag
7
read-write
RERR
receive error flag
6
read-write
STUFF
stuffing error flag
2
read-write
TGERR
toggle error flag
3
read-write
TOUT
timeout flag
5
read-write
HFCOMP
SOF Interrupt Frame Compare Register [BHW]
0x2109
8
read-write
n
0x0
0x0
FRAMECOMP
frame compare data
0
7
read-write
HFRAME
Frame Setup Register [BHW]
0x2118
16
read-write
n
0x0
0x0
FRAME
Frame Setup
0
10
read-write
HIRQ
Host Interrupt Register [BHW]
0x2104
8
read-write
n
0x0
0x0
CMPIRQ
token completion flag
3
read-write
CNNIRQ
device connection detection flag
2
read-write
DIRQ
device disconnection detection flag
1
read-write
RWKIRQ
remote Wake-up end flag
5
read-write
SOFIRQ
SOF starting flag
0
read-write
TCAN
token cancellation flag
7
read-write
URIRQ
bus reset end flag
4
read-write
HRTIMER
Retry Timer Setup Register [BHW]
0x210C
16
read-write
n
0x0
0x0
RTIMER
retry timer setting
0
15
read-write
HRTIMER2
Retry Timer Setup Register 2 [BHW]
0x2110
8
read-write
n
0x0
0x0
RTIMER2
retry timer setting 2
0
1
read-write
HSTATE
Host Status Register [BHW]
0x2108
8
read-write
n
0x0
0x0
ALIVE
specify the keep-alive function in the low-speed mode
5
read-write
CLKSEL
USB operation clock selection bit
4
read-write
CSTAT
connection status flag
0
read-only
SOFBUSY
SOF busy flag
3
read-write
SUSP
suspend setting bit
2
read-write
TMODE
transmission mode flag
1
read-only
HTOKEN
Host Token Endpoint Register [BHW]
0x211C
8
read-write
n
0x0
0x0
ENDPT
endpoint bits
0
3
read-write
TGGL
toggle bit
7
read-write
TKNEN
token enable bits
4
2
read-write
TMSP
Time Stamp Register [HW]
0x213C
16
read-only
n
0x0
0x0
TMSP
Time Stamp bits
0
10
read-only
UDCC
UDC Control Register [BHW]
0x2120
16
read-write
n
0x0
0x0
HCONX
Host Connection bit
5
read-write
PWC
Power Control bit
0
read-write
RESUM
Resume Setting bit
6
read-write
RFBK
Data Toggle Mode Select bit
1
read-write
RST
Function Reset bit
7
read-write
STALCLREN
Endpoint 1 to 5 STAL bit Clear Select bit
3
read-write
USTP
USB Operating Clock Stop bit
4
read-write
UDCIE
UDC Interrupt Enable Register [BHW]
0x2141
8
read-write
n
0x0
0x0
BRSTIE
Bus Reset Enable bit
3
read-write
CONFIE
Configuration Interrupt Enable bit
0
read-write
CONFN
Configuration Number Indication bit
1
read-only
SOFIE
SOF Reception Interrupt Enable bit
4
read-write
SUSPIE
Suspend Interrupt Enable bit
5
read-write
WKUPIE
Wake-up Interrupt Enable bit
2
read-write
UDCS
UDC Status Register [BHW]
0x2140
8
read-write
n
0x0
0x0
BRST
Bus Reset Detection bit
3
read-write
CONF
Configuration Detection bit
0
read-write
SETP
Setup Stage Detection bit
1
read-write
SOF
SOF Detection bit
4
read-write
SUSP
Suspend detection bit
5
read-write
WKUP
Wake-up Detection bit
2
read-write
USB1
USB1 Function
USB
0x0
0x2100
0x2
registers
n
0x2104
0x2
registers
n
0x2108
0x2
registers
n
0x210C
0x2
registers
n
0x2110
0x2
registers
n
0x2114
0x2
registers
n
0x2118
0x2
registers
n
0x211C
0x1
registers
n
0x2120
0x2
registers
n
0x2124
0x2
registers
n
0x2128
0x2
registers
n
0x212C
0x2
registers
n
0x2130
0x2
registers
n
0x2134
0x2
registers
n
0x2138
0x2
registers
n
0x213C
0x2
registers
n
0x2140
0x2
registers
n
0x2144
0x2
registers
n
0x2148
0x2
registers
n
0x214C
0x2
registers
n
0x2150
0x2
registers
n
0x2154
0x2
registers
n
0x2158
0x2
registers
n
0x215C
0x2
registers
n
0x2160
0x2
registers
n
0x2164
0x2
registers
n
0x2168
0x2
registers
n
0x216C
0x2
registers
n
0x2170
0x2
registers
n
0x2174
0x2
registers
n
USB1_F
113
USB1_H_F
114
EP0C
EP0 Control Register [HW]
0x2124
16
read-write
n
0x0
0x0
PKS
Packet Size Endpoint 0 Setting bits
0
6
read-write
STAL
Endpoint 0 Stall Setting bit
9
read-write
EP0DT
EP0 Data Register [BHW]
0x2160
16
read-write
n
0x0
0x0
BFDT
Endpoint Send/Receive Buffer Data
0
15
read-write
EP0IS
EP0I Status Register [HW]
0x2144
16
read-write
n
0x0
0x0
BFINI
Send Buffer Initialization bit
15
read-write
DRQI
Send/Receive Data Interrupt Request bit
10
read-write
DRQIIE
Send Data Interrupt Enable bit
14
read-write
EP0OS
EP0O Status Register [HW]
0x2148
16
read-write
n
0x0
0x0
BFINI
Receive Buffer Initialization bit
15
read-write
DRQO
Receive Data Interrupt Request bit
10
read-write
DRQOIE
Receive Data Interrupt Enable bit
14
read-write
SIZE
Packet Size Indication bit
0
6
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP1C
EP1 Control Register [HW]
0x2128
16
read-write
n
0x0
0x0
DIR
Endpoint Transfer Direction Select bit
12
read-write
DMAE
DMA Automatic Transfer Enable bit
11
read-write
EPEN
Endpoint Enable bit
15
read-write
NULE
Null Automatic Transfer Enable bit
10
read-write
PKS
Packet Size Setting bits
0
8
read-write
STAL
Endpoint Stall Setting bit
9
read-write
TYPE
Endpoint Transfer Type Select bits
13
1
read-write
EP1DT
EP1 Data Register [BHW]
0x2164
read-write
n
0x0
0x0
EP1S
EP1 Status Register [HW]
0x214C
16
read-write
n
0x0
0x0
BFINI
Send/Receive Buffer Initialization bit
15
read-write
BUSY
Busy Flag bit
11
read-only
DRQ
Packet Transfer Interrupt Request bit
10
read-write
DRQIE
Packet Transfer Interrupt Enable bit
14
read-write
SIZE
packet SIZE
0
8
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP2C
EP2 Control Register [HW]
0x212C
16
read-write
n
0x0
0x0
DIR
Endpoint Transfer Direction Select bit
12
read-write
DMAE
DMA Automatic Transfer Enable bit
11
read-write
EPEN
Endpoint Enable bit
15
read-write
NULE
Null Automatic Transfer Enable bit
10
read-write
PKS
Packet Size Setting bits
0
6
read-write
STAL
Endpoint Stall Setting bit
9
read-write
TYPE
Endpoint Transfer Type Select bits
13
1
read-write
EP2DT
EP2 Data Register [BHW]
0x2168
read-write
n
0x0
0x0
EP2S
EP2 Status Register [HW]
0x2150
16
read-write
n
0x0
0x0
BFINI
Send/Receive Buffer Initialization bit
15
read-write
BUSY
Busy Flag bit
11
read-only
DRQ
Packet Transfer Interrupt Request bit
10
read-write
DRQIE
Packet Transfer Interrupt Enable bit
14
read-write
SIZE
packet SIZE
0
6
read-only
SPK
Short Packet Interrupt Request bit
9
read-write
SPKIE
Short Packet Interrupt Enable bit
13
read-write
EP3C
EP3 Control Register [HW]
0x2130
read-write
n
0x0
0x0
EP3DT
EP3 Data Register [BHW]
0x216C
read-write
n
0x0
0x0
EP3S
EP3 Status Register [HW]
0x2154
read-write
n
0x0
0x0
EP4C
EP4 Control Register [HW]
0x2134
read-write
n
0x0
0x0
EP4DT
EP4 Data Register [BHW]
0x2170
read-write
n
0x0
0x0
EP4S
EP4 Status Register [HW]
0x2158
read-write
n
0x0
0x0
EP5C
EP5 Control Register [HW]
0x2138
read-write
n
0x0
0x0
EP5DT
EP5 Data Register [BHW]
0x2174
read-write
n
0x0
0x0
EP5S
EP5 Status Register [HW]
0x215C
read-write
n
0x0
0x0
HADR
Host Address Register [BHW]
0x2111
8
read-write
n
0x0
0x0
ADDRESS
Host Address
0
6
read-write
HCNT
Host Control Register [BHW]
0x2100
16
read-write
n
0x0
0x0
CANCEL
token cancellation enable bit
9
read-write
CMPIRE
token completion interrupt enable bit
5
read-write
CNNIRE
device connection detection interrupt enable bit
4
read-write
DIRE
device disconnection detection interrupt enable bit
3
read-write
HOST
host mode bit
0
read-write
RETRY
retry enable bit
8
read-write
RWKIRE
resume interrupt enable bit
7
read-write
SOFIRE
SOF interrupt enable bit
2
read-write
SOFSTEP
SOF interrupt occurrence selection bit
10
read-write
URIRE
bus reset interrupt enable bit
6
read-write
URST
bus reset bit
1
read-write
HEOF
EOF Setup Register [BHW]
0x2114
16
read-write
n
0x0
0x0
HEOF
End Frame
0
13
read-write
HERR
Host Error Status Register [BHW]
0x2105
8
read-write
n
0x0
0x0
CRC
CRC error flag
4
read-write
HS
handshake status flags
0
1
read-write
LSTSOF
lost SOF flag
7
read-write
RERR
receive error flag
6
read-write
STUFF
stuffing error flag
2
read-write
TGERR
toggle error flag
3
read-write
TOUT
timeout flag
5
read-write
HFCOMP
SOF Interrupt Frame Compare Register [BHW]
0x2109
8
read-write
n
0x0
0x0
FRAMECOMP
frame compare data
0
7
read-write
HFRAME
Frame Setup Register [BHW]
0x2118
16
read-write
n
0x0
0x0
FRAME
Frame Setup
0
10
read-write
HIRQ
Host Interrupt Register [BHW]
0x2104
8
read-write
n
0x0
0x0
CMPIRQ
token completion flag
3
read-write
CNNIRQ
device connection detection flag
2
read-write
DIRQ
device disconnection detection flag
1
read-write
RWKIRQ
remote Wake-up end flag
5
read-write
SOFIRQ
SOF starting flag
0
read-write
TCAN
token cancellation flag
7
read-write
URIRQ
bus reset end flag
4
read-write
HRTIMER
Retry Timer Setup Register [BHW]
0x210C
16
read-write
n
0x0
0x0
RTIMER
retry timer setting
0
15
read-write
HRTIMER2
Retry Timer Setup Register 2 [BHW]
0x2110
8
read-write
n
0x0
0x0
RTIMER2
retry timer setting 2
0
1
read-write
HSTATE
Host Status Register [BHW]
0x2108
8
read-write
n
0x0
0x0
ALIVE
specify the keep-alive function in the low-speed mode
5
read-write
CLKSEL
USB operation clock selection bit
4
read-write
CSTAT
connection status flag
0
read-only
SOFBUSY
SOF busy flag
3
read-write
SUSP
suspend setting bit
2
read-write
TMODE
transmission mode flag
1
read-only
HTOKEN
Host Token Endpoint Register [BHW]
0x211C
8
read-write
n
0x0
0x0
ENDPT
endpoint bits
0
3
read-write
TGGL
toggle bit
7
read-write
TKNEN
token enable bits
4
2
read-write
TMSP
Time Stamp Register [HW]
0x213C
16
read-only
n
0x0
0x0
TMSP
Time Stamp bits
0
10
read-only
UDCC
UDC Control Register [BHW]
0x2120
16
read-write
n
0x0
0x0
HCONX
Host Connection bit
5
read-write
PWC
Power Control bit
0
read-write
RESUM
Resume Setting bit
6
read-write
RFBK
Data Toggle Mode Select bit
1
read-write
RST
Function Reset bit
7
read-write
STALCLREN
Endpoint 1 to 5 STAL bit Clear Select bit
3
read-write
USTP
USB Operating Clock Stop bit
4
read-write
UDCIE
UDC Interrupt Enable Register [BHW]
0x2141
8
read-write
n
0x0
0x0
BRSTIE
Bus Reset Enable bit
3
read-write
CONFIE
Configuration Interrupt Enable bit
0
read-write
CONFN
Configuration Number Indication bit
1
read-only
SOFIE
SOF Reception Interrupt Enable bit
4
read-write
SUSPIE
Suspend Interrupt Enable bit
5
read-write
WKUPIE
Wake-up Interrupt Enable bit
2
read-write
UDCS
UDC Status Register [BHW]
0x2140
8
read-write
n
0x0
0x0
BRST
Bus Reset Detection bit
3
read-write
CONF
Configuration Detection bit
0
read-write
SETP
Setup Stage Detection bit
1
read-write
SOF
SOF Detection bit
4
read-write
SUSP
Suspend detection bit
5
read-write
WKUP
Wake-up Detection bit
2
read-write
USBETHERCLK
USB/Ethernet Clock
USBETHERCLK
0x0
0x0
0x1
registers
n
0x10
0x1
registers
n
0x14
0x1
registers
n
0x18
0x1
registers
n
0x1C
0x1
registers
n
0x20
0x1
registers
n
0x24
0x1
registers
n
0x28
0x1
registers
n
0x2C
0x1
registers
n
0x30
0x1
registers
n
0x34
0x1
registers
n
0x4
0x1
registers
n
0x8
0x1
registers
n
0xC
0x1
registers
n
UCCR
USB/Ethernet-PLL Clock Control Register [BHW]
0x0
8
read-write
n
0x0
0x0
ECEN
Ethernet clock output enable bit
4
read-write
ECSEL
Ethernet clock selection bit
5
1
read-write
UCEN0
USB0 clock output enable bit
0
read-write
UCEN1
USB1 clock output enable bit
3
read-write
UCSEL
USB1/0 clock selection bit
1
1
read-write
UPCR1
USB/Ethernet-PLL Control Register 1 [BHW]
0x4
8
read-write
n
0x0
0x0
UPINC
USB/Ethernet-PLL input clock selection bit
1
read-write
UPLLEN
USB/Ethernet-PLL oscillation enable bit
0
read-write
UPCR2
USB/Ethernet-PLL Control Register 2 [BHW]
0x8
8
read-write
n
0x0
0x0
UPOWT
USB/Ethernet-PLL oscillation stabilization wait time setting bit
0
2
read-write
UPCR3
USB/Ethernet-PLL Control Register 3 [BHW]
0xC
8
read-write
n
0x0
0x0
UPLLK
Frequency division ratio (K) setting bit of the USB/Ethernet-PLL clock
0
4
read-write
UPCR4
USB/Ethernet-PLL Control Register 4 [BHW]
0x10
8
read-write
n
0x0
0x0
UPLLN
Frequency division ratio (N) setting bit of the USB/Ethernet-PLL clock
0
6
read-write
UPCR5
USB/Ethernet-PLL Control Register 5 [BHW]
0x24
8
read-write
n
0x0
0x0
UPLLM
Frequency division ratio (M) setting bit of the USB/Ethernet-PLL clock
0
3
read-write
UPCR6
USB/Ethernet-PLL Setting Register 6 [BHW]
0x28
8
read-write
n
0x0
0x0
UBSR
CLKPLL division ratio setting bit
0
3
read-write
UPCR7
USB/Ethernet-PLL Setting Register 7 [BHW]
0x2C
8
read-write
n
0x0
0x0
EPLLEN
USB/Ethernet-PLL control bit in Timer mode
0
read-write
UPINT_CLR
USB/Ethernet-PLL Interrupt Source Clear Register [BHW]
0x1C
8
write-only
n
0x0
0x0
UPCSC
USB/Ethernet-PLL oscillation stabilization interrupt source clear bit
0
write-only
UPINT_ENR
USB/Ethernet-PLL Interrupt Source Enable Register [BHW]
0x18
8
read-write
n
0x0
0x0
UPCSE
USB/Ethernet-PLL oscillation stabilization wait complete interrupt enable bit
0
read-write
UPINT_STR
USB/Ethernet-PLL Interrupt Source Status Register [BHW]
0x20
8
read-only
n
0x0
0x0
UPCSI
USB/Ethernet-PLL interrupt source status bit
0
read-only
UP_STR
USB/Ethernet-PLL Status Register [BHW]
0x14
8
read-only
n
0x0
0x0
UPRDY
USB/Ethernet-PLL oscillation stabilization bit
0
read-only
USBEN0
USB0 Enable Register [BHW]
0x30
8
read-write
n
0x0
0x0
USBEN0
USB0 enable bit
0
read-write
USBEN1
USB1 Enable Register [BHW]
0x34
8
read-write
n
0x0
0x0
USBEN1
USB1 enable bit
0
read-write
WC
Watch Counter
WC
0x0
0x0
0x3
registers
n
0x10
0x2
registers
n
0x14
0x1
registers
n
WC
48
CLK_EN
Division Clock Enable Register [BHW]
0x14
8
read-write
n
0x0
0x0
CLK_EN
Division clock enable bit
0
read-write
CLK_EN_R
Division clock enable read bit
1
read-write
CLK_SEL
Clock Selection Register [BHW]
0x10
16
read-write
n
0x0
0x0
SEL_IN
Input clock selection bit
0
1
read-write
SEL_OUT
Output clock selection bit
8
2
read-write
WCCR
Watch Counter Control Register [BHW]
0x2
8
read-write
n
0x0
0x0
CS
Count clock select bits
2
1
read-write
WCEN
Watch counter operation enable bit
7
read-write
WCIE
Interrupt request enable bit
1
read-write
WCIF
Interrupt request flag bit
0
read-write
WCOP
Watch counter operating state flag
6
read-only
WCRD
Watch Counter Read Register [BHW]
0x0
8
read-only
n
0x0
0x0
CTR
Counter read bits
0
5
read-only
WCRL
Watch Counter Reload Register [BHW]
0x1
8
read-write
n
0x0
0x0
RLC
Counter reload value setting bits
0
5
read-write