Renesas R7FA4W1A 2024.05.05 ARM 32-bit Cortex-M4F Microcontroller based device, CPU clock up to 48MHz, etc. CM4 r0p1 little true true 4 false 8 32 ACMPLP Low-Power Analog Comparator ACMPLP 0x0 0x0 0x3 registers n 0x4 0x2 registers n COMPFIR ACMPLP Filter Control Register 0x1 8 read-write n 0x0 0x0 C0EDG ACMPLP0 Edge Detection Selection 3 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C0EPO ACMPLP0 Edge Polarity Switching 2 read-write 0 Interrupt and ELC event request at rising edge #0 1 Interrupt and ELC event request at falling edge #1 C0FCK ACMPLP0 Filter Select 0 1 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLK #01 10 Sampling at PCLK/8 #10 11 Sampling at PCLK/32 #11 C1EDG ACMPLP1 Edge Detection Selection 7 read-write 0 Interrupt and ELC event request by one-edge detection #0 1 Interrupt and ELC event request by both-edge detection #1 C1EPO ACMPLP1 Edge Polarity Switching 6 read-write 0 Interrupt and ELC event request at rising edge #0 1 Interrupt and ELC event request at falling edge #1 C1FCK ACMPLP1 Filter Select 4 1 read-write 00 No Sampling (bypass) #00 01 Sampling at PCLK #01 10 Sampling at PCLK/8 #10 11 Sampling at PCLK/32 #11 COMPMDR ACMPLP Mode Setting Register 0x0 8 read-write n 0x0 0x0 C0ENB ACMPLP0 Operation Enable 0 read-write 0 Disabled #0 1 Enabled #1 C0MON ACMPLP0 Monitor Flag 3 read-only 0 CMPIN0 < CMPREF0, CMPIN0 < internal reference voltage, or ACMPLP0 operation disabled.(When the window function is disabled)/CMPIN0 < VRFL, CMPIN0 > VRFH, or ACMPLP0 operation disabled.(When the window function is enabled) #0 1 CMPIN0 > CMPREF0, or CMPIN0 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN0 < VRFH.(When the window function is enabled) #1 C0VRF ACMPLP0 Reference Voltage Selection 2 read-write 0 IVREF0 #0 1 internal reference voltage (Vref) #1 C0WDE ACMPLP0 Window Function Mode Enable 1 read-write 0 Disabled #0 1 Enabled #1 C1ENB ACMPLP1 Operation Enable 4 read-write 0 Disabled #0 1 Enabled #1 C1MON ACMPLP1 Monitor Flag 7 read-only 0 CMPIN1 < CMPREF1, CMPIN1 < internal reference voltage, or ACMPLP1 operation disabled.(When the window function is disabled)/CMPIN1 < VRFL, CMPIN1 > VRFH, or ACMPLP1 operation disabled.(When the window function is enabled) #0 1 CMPIN1 > CMPREF1, or CMPIN1 > internal reference voltage.(When the window function is disabled)/VRFL < CMPIN1 < VRFH.(When the window function is enabled) #1 C1VRF ACMPLP1 Reference Voltage Selection 6 read-write 0 IVREF0 or IVREF1 #0 1 internal reference voltage (Vref) #1 C1WDE ACMPLP1 Window Function Mode Enable 5 read-write 0 Disabled #0 1 Enabled #1 COMPOCR ACMPLP Output Control Register 0x2 8 read-write n 0x0 0x0 C0OE ACMPLP0 VCOUT Pin Output Enable 1 read-write 0 Disabled #0 1 Enabled #1 C0OP ACMPLP0 VCOUT Output Polarity Selection 2 read-write 0 Non inverted #0 1 Inverted #1 C1OE ACMPLP1 VCOUT Pin Output Enable 5 read-write 0 Disabled #0 1 Enabled #1 C1OP ACMPLP1 VCOUT Output Polarity Selection 6 read-write 0 Non inverted #0 1 Inverted #1 Reserved These bits are read as 00. The write value should be 00. 3 1 read-write Reserved These bits are read as 00. The write value should be 00. 3 1 read-write SPDMD ACMPLP0/ACMPLP1 Speed Selection 7 read-write 0 Comparator low-speed mode #0 1 Comparator high-speed mode #1 COMPSEL0 Comparator Input Select Register 0x4 8 read-write n 0x0 0x0 CMPSEL20 ACMPLP0 Input(IVCMP0) Selection 0 2 read-write 000 No input #000 001 CMPIN0 (P100) #001 100 CMPIN0 (P503) #100 CMPSEL64 ACMPLP1 Input (IVCMP1) Selection 4 2 read-write 000 No input #000 001 CMPIN1 (P102) #001 100 CMPIN1 (P501) #100 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write COMPSEL1 Comparator Reference Voltage Select Register 0x5 8 read-write n 0x0 0x0 C1VRF2 ACMPLP1 Reference Voltage Selection 7 read-write 0 IVREF0 selected #0 1 IVREF1 selected. #1 CRVS20 ACMPLP0 Reference Voltage(IVREF0) Selection* 0 2 read-write 000 No input #000 001 CMPREF0 (P101) #001 010 DAC8 (ch0) output #010 100 CMPREF0 (P502) #100 CRVS64 ACMPLP1 Reference Voltage(IVREF1) Selection 4 2 read-write 000 No input #000 001 CMPREF1 (P103) #001 010 DAC8 (ch1) output #010 100 CMPREF1 (P500) #100 Reserved This bit is read as 0. The write value should be 0. 3 read-write ADC140 14bit A/D Converter ADC140 0x0 0x0 0xD registers n 0x1A0 0x4 registers n 0x1B0 0x2 registers n 0x1B4 0x2 registers n 0x1E0 0x1 registers n 0x62 0x16 registers n 0x7A 0x4 registers n 0x80 0x9 registers n 0x8A 0x1 registers n 0x8C 0x1 registers n 0x90 0x15 registers n 0xA6 0x1 registers n 0xA8 0x5 registers n 0xB0 0x21 registers n 0xD2 0x1 registers n 0xDD 0x13 registers n 0xE 0x4A registers n ADADC A/D-Converted Value Addition/Average Count Select Register 0xC 8 read-write n 0x0 0x0 ADC Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1, do not set the addition count to three times (ADADC.ADC[2:0] = 010b) 0 2 read-write 000 1-time conversion (no addition; same as normal conversion) #000 001 2-time conversion (addition once) #001 010 3-time conversion (addition twice) #010 011 4-time conversion (addition three times) #011 101 16-time conversion (addition 15 times), can be set when selecting 12-bit accuracy. #101 AVEE Average mode enable bit.Note: The AVEE bit converts twice, and only when converting it four times, is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode. 7 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write ADADS0 A/D-Converted Value Addition/Average Channel Select Register 0 0x8 16 read-write n 0x0 0x0 ADS00 A/D-Converted Value Addition/Average Channel AN000 Select 0 read-write 0 AN000 is not selected. #0 1 AN000 is selected. #1 ADS01 A/D-Converted Value Addition/Average Channel AN001 Select 1 read-write 0 AN001 is not selected. #0 1 AN001 is selected. #1 ADS02 A/D-Converted Value Addition/Average Channel AN002 Select 2 read-write 0 AN002 is not selected. #0 1 AN002 is selected. #1 ADS03 A/D-Converted Value Addition/Average Channel AN003 Select 3 read-write 0 AN003 is not selected. #0 1 AN003 is selected. #1 ADS04 A/D-Converted Value Addition/Average Channel AN004 Select 4 read-write 0 AN004 is not selected. #0 1 AN004 is selected. #1 ADS05 A/D-Converted Value Addition/Average Channel AN005 Select 5 read-write 0 AN005 is not selected. #0 1 AN005 is selected. #1 ADS06 A/D-Converted Value Addition/Average Channel AN006 Select 6 read-write 0 AN006 is not selected. #0 1 AN006 is selected. #1 ADS07 A/D-Converted Value Addition/Average Channel AN007 Select 7 read-write 0 AN007 is not selected. #0 1 AN007 is selected. #1 ADS08 A/D-Converted Value Addition/Average Channel AN008 Select 8 read-write 0 AN008 is not selected. #0 1 AN008 is selected. #1 ADS09 A/D-Converted Value Addition/Average Channel AN009 Select 9 read-write 0 AN009 is not selected. #0 1 AN009 is selected. #1 ADS10 A/D-Converted Value Addition/Average Channel AN010 Select 10 read-write 0 AN010 is not selected. #0 1 AN010 is selected. #1 ADS11 A/D-Converted Value Addition/Average Channel AN011 Select 11 read-write 0 AN011 is not selected. #0 1 AN011 is selected. #1 ADS12 A/D-Converted Value Addition/Average Channel AN012 Select 12 read-write 0 AN012 is not selected. #0 1 AN012 is selected. #1 ADS13 A/D-Converted Value Addition/Average Channel AN013 Select 13 read-write 0 AN013 is not selected. #0 1 AN013 is selected. #1 ADS14 A/D-Converted Value Addition/Average Channel AN014 Select 14 read-write 0 AN014 is not selected. #0 1 AN014 is selected. #1 ADS15 A/D-Converted Value Addition/Average Channel AN015 Select 15 read-write 0 AN015 is not selected. #0 1 AN015 is selected. #1 ADADS1 A/D-Converted Value Addition/Average Channel Select Register 1 0xA 16 read-write n 0x0 0x0 ADS16 A/D-Converted Value Addition/Average Channel AN016 Select 0 read-write 0 AN016 is not selected. #0 1 AN016 is selected. #1 ADS17 A/D-Converted Value Addition/Average Channel AN017 Select 1 read-write 0 AN017 is not selected. #0 1 AN017 is selected. #1 ADS18 A/D-Converted Value Addition/Average Channel AN018 Select 2 read-write 0 AN018 is not selected. #0 1 AN018 is selected. #1 ADS19 A/D-Converted Value Addition/Average Channel AN019 Select 3 read-write 0 AN019 is not selected. #0 1 AN019 is selected. #1 ADS20 A/D-Converted Value Addition/Average Channel AN020 Select 4 read-write 0 AN020 is not selected. #0 1 AN020 is selected. #1 ADS21 A/D-Converted Value Addition/Average Channel AN021 Select 5 read-write 0 AN021 is not selected. #0 1 AN021 is selected. #1 ADS22 A/D-Converted Value Addition/Average Channel AN022 Select 6 read-write 0 AN022 is not selected. #0 1 AN022 is selected. #1 ADS23 A/D-Converted Value Addition/Average Channel AN023 Select 7 read-write 0 AN023 is not selected. #0 1 AN023 is selected. #1 ADS24 A/D-Converted Value Addition/Average Channel AN024 Select 8 read-write 0 AN024 is not selected. #0 1 AN024 is selected. #1 ADS25 A/D-Converted Value Addition/Average Channel AN025 Select 9 read-write 0 AN025 is not selected. #0 1 AN025 is selected. #1 ADS26 A/D-Converted Value Addition/Average Channel AN026 Select 10 read-write 0 AN026 is not selected. #0 1 AN026 is selected. #1 ADS27 A/D-Converted Value Addition/Average Channel AN027 Select 11 read-write 0 AN027 is not selected. #0 1 AN027 is selected. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADANSA0 A/D Channel Select Register A0 0x4 16 read-write n 0x0 0x0 ANSA00 AN000 Select 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ANSA01 AN001 Select 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSA010 AN010 Select 10 read-write 0 AN010 is not subjected to conversion. #0 1 AN010 is subjected to conversion. #1 ANSA011 AN011 Select 11 read-write 0 AN011 is not subjected to conversion. #0 1 AN011 is subjected to conversion. #1 ANSA012 AN012 Select 12 read-write 0 AN012 is not subjected to conversion. #0 1 AN012 is subjected to conversion. #1 ANSA013 AN013 Select 13 read-write 0 AN013 is not subjected to conversion. #0 1 AN013 is subjected to conversion. #1 ANSA014 AN014 Select 14 read-write 0 AN014 is not subjected to conversion. #0 1 AN014 is subjected to conversion. #1 ANSA015 AN015 Select 15 read-write 0 AN015 is not subjected to conversion. #0 1 AN015 is subjected to conversion. #1 ANSA02 AN002 Select 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSA03 AN003 Select 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSA04 AN004 Select 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSA05 AN005 Select 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSA06 AN006 Select 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSA07 AN007 Select 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSA08 AN008 Select 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSA09 AN009 Select 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ADANSA1 A/D Channel Select Register A1 0x6 16 read-write n 0x0 0x0 ANSA16 AN016 Select 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ANSA17 AN017 Select 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSA18 AN018 Select 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSA19 AN019 Select 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSA20 AN020 Select 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSA21 AN021 Select 5 read-write 0 AN021 is not subjected to conversion. #0 1 AN021 is subjected to conversion. #1 ANSA22 AN022 Select 6 read-write 0 AN022 is not subjected to conversion. #0 1 AN022 is subjected to conversion. #1 ANSA23 AN023 Select 7 read-write 0 AN023 is not subjected to conversion. #0 1 AN023 is subjected to conversion. #1 ANSA24 AN024 Select 8 read-write 0 AN024 is not subjected to conversion. #0 1 AN024 is subjected to conversion. #1 ANSA25 AN025 Select 9 read-write 0 AN025 is not subjected to conversion. #0 1 AN025 is subjected to conversion. #1 ANSA26 AN026 Select 10 read-write 0 AN026 is not subjected to conversion. #0 1 AN026 is subjected to conversion. #1 ANSA27 AN027 Select 11 read-write 0 AN027 is not subjected to conversion. #0 1 AN027 is subjected to conversion. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADANSB0 A/D Channel Select Register B0 0x14 16 read-write n 0x0 0x0 ANSB00 AN000 Select 0 read-write 0 AN000 is not subjected to conversion. #0 1 AN000 is subjected to conversion. #1 ANSB01 AN001 Select 1 read-write 0 AN001 is not subjected to conversion. #0 1 AN001 is subjected to conversion. #1 ANSB02 AN002 Select 2 read-write 0 AN002 is not subjected to conversion. #0 1 AN002 is subjected to conversion. #1 ANSB03 AN003 Select 3 read-write 0 AN003 is not subjected to conversion. #0 1 AN003 is subjected to conversion. #1 ANSB04 AN004 Select 4 read-write 0 AN004 is not subjected to conversion. #0 1 AN004 is subjected to conversion. #1 ANSB05 AN005 Select 5 read-write 0 AN005 is not subjected to conversion. #0 1 AN005 is subjected to conversion. #1 ANSB06 AN006 Select 6 read-write 0 AN006 is not subjected to conversion. #0 1 AN006 is subjected to conversion. #1 ANSB07 AN007 Select 7 read-write 0 AN007 is not subjected to conversion. #0 1 AN007 is subjected to conversion. #1 ANSB08 AN008 Select 8 read-write 0 AN008 is not subjected to conversion. #0 1 AN008 is subjected to conversion. #1 ANSB09 AN009 Select 9 read-write 0 AN009 is not subjected to conversion. #0 1 AN009 is subjected to conversion. #1 ANSB10 AN010 Select 10 read-write 0 AN010 is not subjected to conversion. #0 1 AN010 is subjected to conversion. #1 ANSB11 AN011 Select 11 read-write 0 AN011 is not subjected to conversion. #0 1 AN011 is subjected to conversion. #1 ANSB12 AN012 Select 12 read-write 0 AN012 is not subjected to conversion. #0 1 AN012 is subjected to conversion. #1 ANSB13 AN013 Select 13 read-write 0 AN013 is not subjected to conversion. #0 1 AN013 is subjected to conversion. #1 ANSB14 AN014 Select 14 read-write 0 AN014 is not subjected to conversion. #0 1 AN014 is subjected to conversion. #1 ANSB15 AN015 Select 15 read-write 0 AN015 is not subjected to conversion. #0 1 AN015 is subjected to conversion. #1 ADANSB1 A/D Channel Select Register B1 0x16 16 read-write n 0x0 0x0 ANSB16 AN016 Select 0 read-write 0 AN016 is not subjected to conversion. #0 1 AN016 is subjected to conversion. #1 ANSB17 AN017 Select 1 read-write 0 AN017 is not subjected to conversion. #0 1 AN017 is subjected to conversion. #1 ANSB18 AN018 Select 2 read-write 0 AN018 is not subjected to conversion. #0 1 AN018 is subjected to conversion. #1 ANSB19 AN019 Select 3 read-write 0 AN019 is not subjected to conversion. #0 1 AN019 is subjected to conversion. #1 ANSB20 AN020 Select 4 read-write 0 AN020 is not subjected to conversion. #0 1 AN020 is subjected to conversion. #1 ANSB21 AN021 Select 5 read-write 0 AN021 is not subjected to conversion. #0 1 AN021 is subjected to conversion. #1 ANSB22 AN022 Select 6 read-write 0 AN022 is not subjected to conversion. #0 1 AN022 is subjected to conversion. #1 ANSB23 AN023 Select 7 read-write 0 AN023 is not subjected to conversion. #0 1 AN023 is subjected to conversion. #1 ANSB24 AN024 Select 8 read-write 0 AN024 is not subjected to conversion. #0 1 AN024 is subjected to conversion. #1 ANSB25 AN025 Select 9 read-write 0 AN025 is not subjected to conversion. #0 1 AN025 is subjected to conversion. #1 ANSB26 AN026 Select 10 read-write 0 AN026 is not subjected to conversion. #0 1 AN026 is subjected to conversion. #1 ANSB27 AN027 Select 11 read-write 0 AN027 is not subjected to conversion. #0 1 AN027 is subjected to conversion. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADCER A/D Control Extended Register 0xE 16 read-write n 0x0 0x0 ACE A/D Data Register Automatic Clearing Enable 5 read-write 0 Disables automatic clearing. #0 1 Enables automatic clearing. #1 ADPRC A/D Conversion Accuracy Specify 1 1 read-write 00 A/D conversion is performed with 12-bit accuracy. #00 11 A/D conversion is performed with 14-bit accuracy. #11 ADRFMT A/D Data Register Format Select 15 read-write 0 Flush-right is selected for the A/D data register format. #0 1 Flush-left is selected for the A/D data register format. #1 DIAGLD Self-Diagnosis Mode Select 10 read-write 0 Rotation mode for self-diagnosis voltage #0 1 Fixed mode for self-diagnosis voltage #1 DIAGM Self-Diagnosis Enable 11 read-write 0 Disables self-diagnosis of A/D converter. #0 1 Enables self-diagnosis of A/D converter. #1 DIAGVAL Self-Diagnosis Conversion Voltage Select 8 1 read-write 00 When the self-diagnosis fixation mode is selected, it set prohibits it. #00 01 The self-diagnosis by using the voltage of 0V. #01 10 The self-diagnosis by using the voltage of reference supply x 1/2. #10 11 The self-diagnosis by using the voltage of the reference supply. #11 Reserved These bits are read as 000. The write value should be 000. 12 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write ADCMPANSER A/D Compare Function Window A Extended Input Select Register 0x92 8 read-write n 0x0 0x0 CMPOCA Internal reference voltage Compare selection bit. 1 read-write 0 Excludes the internal reference voltage from the compare window A target range. #0 1 Includes the internal reference voltage in the compare window A target range. #1 CMPTSA Temperature sensor output Compare selection bit. 0 read-write 0 Excludes the temperature sensor output from the compare window A target range. #0 1 Includes the temperature sensor output in the compare window A target range. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPANSR0 A/D Compare Function Window A Channel Select Register 0 0x94 16 read-write n 0x0 0x0 CMPCHA00 AN000 Select 0 read-write 0 Excludes AN000 from the compare window A target range. #0 1 Includes AN000 from the compare window A target range. #1 CMPCHA01 AN001 Select 1 read-write 0 Excludes AN001 from the compare window A target range. #0 1 Includes AN001 from the compare window A target range. #1 CMPCHA02 AN002 Select 2 read-write 0 Excludes AN002 from the compare window A target range. #0 1 Includes AN002 from the compare window A target range. #1 CMPCHA03 AN003 Select 3 read-write 0 Excludes AN003 from the compare window A target range. #0 1 Includes AN003 from the compare window A target range. #1 CMPCHA04 AN004 Select 4 read-write 0 Excludes AN004 from the compare window A target range. #0 1 Includes AN004 from the compare window A target range. #1 CMPCHA05 AN005 Select 5 read-write 0 Excludes AN005 from the compare window A target range. #0 1 Includes AN005 from the compare window A target range. #1 CMPCHA06 AN006 Select 6 read-write 0 Excludes AN006 from the compare window A target range. #0 1 Includes AN006 from the compare window A target range. #1 CMPCHA07 AN007 Select 7 read-write 0 Excludes AN007 from the compare window A target range. #0 1 Includes AN007 from the compare window A target range. #1 CMPCHA08 AN008 Select 8 read-write 0 Excludes AN008 from the compare window A target range. #0 1 Includes AN008 from the compare window A target range. #1 CMPCHA09 AN009 Select 9 read-write 0 Excludes AN009 from the compare window A target range. #0 1 Includes AN009 from the compare window A target range. #1 CMPCHA10 AN010 Select 10 read-write 0 Excludes AN010 from the compare window A target range. #0 1 Includes AN010 from the compare window A target range. #1 CMPCHA11 AN011 Select 11 read-write 0 Excludes AN011 from the compare window A target range. #0 1 Includes AN011 from the compare window A target range. #1 CMPCHA12 AN012 Select 12 read-write 0 Excludes AN012 from the compare window A target range. #0 1 Includes AN012 from the compare window A target range. #1 CMPCHA13 AN013 Select 13 read-write 0 Excludes AN013 from the compare window A target range. #0 1 Includes AN013 from the compare window A target range. #1 CMPCHA14 AN014 Select 14 read-write 0 Excludes AN014 from the compare window A target range. #0 1 Includes AN014 from the compare window A target range. #1 CMPCHA15 AN015 Select 15 read-write 0 Excludes AN015 from the compare window A target range. #0 1 Includes AN015 from the compare window A target range. #1 ADCMPANSR1 A/D Compare Function Window A Channel Select Register 1 0x96 16 read-write n 0x0 0x0 CMPCHA16 AN016 Select 0 read-write 0 Excludes AN016 from the compare window A target range. #0 1 Includes AN016 from the compare window A target range. #1 CMPCHA17 AN017 Select 1 read-write 0 Excludes AN017 from the compare window A target range. #0 1 Includes AN017 from the compare window A target range. #1 CMPCHA18 AN018 Select 2 read-write 0 Excludes AN018 from the compare window A target range. #0 1 Includes AN018 from the compare window A target range. #1 CMPCHA19 AN019 Select 3 read-write 0 Excludes AN019 from the compare window A target range. #0 1 Includes AN019 from the compare window A target range. #1 CMPCHA20 AN020 Select 4 read-write 0 Excludes AN020 from the compare window A target range. #0 1 Includes AN020 from the compare window A target range. #1 CMPCHA21 AN021 Select 5 read-write 0 Excludes AN021 from the compare window A target range. #0 1 Includes AN021 from the compare window A target range. #1 CMPCHA22 AN022 Select 6 read-write 0 Excludes AN022 from the compare window A target range. #0 1 Includes AN022 from the compare window A target range. #1 CMPCHA23 AN023 Select 7 read-write 0 Excludes AN023 from the compare window A target range. #0 1 Includes AN023 from the compare window A target range. #1 CMPCHA24 AN024 Select 8 read-write 0 Excludes AN024 from the compare window A target range. #0 1 Includes AN024 from the compare window A target range. #1 CMPCHA25 AN025 Select 9 read-write 0 Excludes AN025 from the compare window A target range. #0 1 Includes AN025 from the compare window A target range. #1 CMPCHA26 AN026 Select 10 read-write 0 Excludes AN026 from the compare window A target range. #0 1 Includes AN026 from the compare window A target range. #1 CMPCHA27 AN027 Select 11 read-write 0 Excludes AN027 from the compare window A target range. #0 1 Includes AN027 from the compare window A target range. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADCMPBNSR A/D Compare Function Window B Channel Selection Register 0xA6 8 read-write n 0x0 0x0 CMPCHB Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected. 0 5 read-write 0x00 AN000 0x00 0x01 AN001 0x01 0x02 AN002 0x02 0x03 AN003 0x03 0x04 AN004 0x04 0x05 AN005 0x05 0x06 AN006 0x06 0x07 AN007 0x07 0x08 AN008 0x08 0x09 AN009 0x09 0x0A AN010 0x0A 0x0B AN011 0x0B 0x0C AN012 0x0C 0x0D AN013 0x0D 0x0E AN014 0x0E 0x0F AN015 0x0F 0x10 AN016 0x10 0x11 AN017 0x11 0x12 AN018 0x12 0x13 AN019 0x13 0x14 AN020 0x14 0x15 AN021 0x15 0x16 AN022 0x16 0x17 AN023 0x17 0x18 AN024 0x18 0x19 AN025 0x19 0x1A AN026 0x1A 0x1B AN027 0x1B 0x20 Temperature sensor 0x20 0x21 Internal reference voltage 0x21 0x3F No channel is selected 0x3F CMPLB Compare window B Compare condition setting bit. 7 read-write 0 CMPLLB value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < CMPLLB value or CMPULB value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 CMPLLB value < A/D converted value(ADCMPCR.WCMPE=0) / CMPLLB value < A/D converted value < CMPULB value (ADCMPCR.WCMPE=1) #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write ADCMPBSR A/D Compare Function Window B Status Register 0xAC 8 read-write n 0x0 0x0 CMPSTB Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN027, temperature sensor, and internal reference voltage) made the object of window B relation condition. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ADCMPCR A/D Compare Function Control Register 0x90 16 read-write n 0x0 0x0 CMPAB Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1). 0 1 read-write 00 ADC140_WCMPM is output when window A comparison conditions are met OR window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #00 01 S14ADWMELC0 is output when window A comparison conditions are met EXOR window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #01 10 ADC140_WCMPM is output when window A comparison conditions are met and window B comparison conditions are met. ADC140_WCMPUM is output in other cases. #10 11 Setting prohibited. #11 CMPAE Compare Window A Operation Enable 11 read-write 0 Compare window A operation is disabled. ADC140_WCMPM and ADC140_WCMPUM outputs are disabled. #0 1 Compare window A operation is enabled. #1 CMPAIE Compare A Interrupt Enable 15 read-write 0 ADC140_CMPAI interrupt is disabled when comparison conditions (window A) are met. #0 1 ADC140_CMPAI interrupt is enabled when comparison conditions (window A) are met. #1 CMPBE Compare Window B Operation Enable 9 read-write 0 Compare window B operation is disabled. ADC140_WCMPM and ADC140_WCMPUM outputs are disabled. #0 1 Compare window B operation is enabled. #1 CMPBIE Compare B Interrupt Enable 13 read-write 0 ADC140_CMPAI interrupt is disabled when comparison conditions (window B) are met. #0 1 ADC140_CMPAI interrupt is enabled when comparison conditions (window B) are met. #1 Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write WCMPE Window Function Setting 14 read-write 0 Window function is disabled. Window A and window B operate as a comparator to comparator the single value on the lower side with the A/D conversion result. #0 1 Window function is enabled. Window A and window B operate as a comparator to comparator the two values on the upper and lower sides with the A/D conversion result. #1 ADCMPDR0 A/D Compare Function Window A Lower-Side Level Setting Register 0x9C 16 read-write n 0x0 0x0 ADCMPDR0 The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A. 0 15 read-write ADCMPDR1 A/D Compare Function Window A Upper-Side Level Setting Register 0x9E 16 read-write n 0x0 0x0 ADCMPDR1 The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.. 0 15 read-write ADCMPLER A/D Compare Function Window A Extended Input Comparison Condition Setting Register 0x93 8 read-write n 0x0 0x0 CMPLOCA Compare Window A Internal Reference Voltage ComparisonCondition Select 1 read-write 0 ADCMPDR0 value > A/D converted value(ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or A/D converted value > ADCMPDR1 value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 value < A/D converted value < ADCMPDR1 value(ADCMPCR.WCMPE=1) #1 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select 0 read-write 0 ADCMPDR0 register value > A/D-converted value(ADCMPCR.WCMPE=0) / AD-converted value < ADCMPDR0 register value or A/D-converted value > ADCMPDR1 register value(ADCMPCR.WCMPE=1). #0 1 ADCMPDR0 register value < A/D-converted value(ADCMPCR.WCMPE=0) / ADCMPDR0 register value < A/D-converted value < ADCMPDR1 register value(ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPLR0 A/D Compare Function Window A Comparison Condition Setting Register 0 0x98 16 read-write n 0x0 0x0 CMPLCHA00 Comparison condition of AN000 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA01 Comparison condition of AN001 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA02 Comparison condition of AN002 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA03 Comparison condition of AN003 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA04 Comparison condition of AN004 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA05 Comparison condition of AN005 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA06 Comparison condition of AN006 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA07 Comparison condition of AN007 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA08 Comparison condition of AN008 8 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA09 Comparison condition of AN009 9 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA10 Comparison condition of AN010 10 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA11 Comparison condition of AN011 11 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA12 Comparison condition of AN012 12 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA13 Comparison condition of AN013 13 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA14 Comparison condition of AN014 14 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA15 Comparison condition of AN015 15 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 ADCMPLR1 A/D Compare Function Window A Comparison Condition Setting Register 1 0x9A 16 read-write n 0x0 0x0 CMPLCHA16 Comparison condition of AN016 0 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA17 Comparison condition of AN017 1 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA18 Comparison condition of AN018 2 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA19 Comparison condition of AN019 3 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA20 Comparison condition of AN020 4 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA21 Comparison condition of AN021 5 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA22 Comparison condition of AN022 6 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA23 Comparison condition of AN023 7 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA24 Comparison condition of AN024 8 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA25 Comparison condition of AN025 9 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA26 Comparison condition of AN026 10 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 CMPLCHA27 Comparison condition of AN027 11 read-write 0 ADCMPDR0 value > A/D converted value (ADCMPCR.WCMPE=0) / A/D converted value < ADCMPDR0 value or, ADCMPDR1 value < A/D converted value (ADCMPCR.WCMPE=1) #0 1 ADCMPDR0 value < A/D converted value (ADCMPCR.WCMPE=0) / A/DCMPDR0 value < A/D converted value < ADCMPDR1 value (ADCMPCR.WCMPE=1). #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADCMPSER A/D Compare Function Window A Extended Input Channel Status Register 0xA4 8 read-write n 0x0 0x0 CMPSTOCA Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison conditions for CMPSTTSA are not met any time. 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ADCMPSR0 A/D Compare Function Window A Channel Status Register 0 0xA0 16 read-write n 0x0 0x0 CMPSTCHA00 Compare window A flag of AN000 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA01 Compare window A flag of AN001 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA02 Compare window A flag of AN002 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA03 Compare window A flag of AN003 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA04 Compare window A flag of AN004 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA05 Compare window A flag of AN005 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA06 Compare window A flag of AN006 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA07 Compare window A flag of AN007 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA08 Compare window A flag of AN008 8 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA09 Compare window A flag of AN009 9 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA10 Compare window A flag of AN010 10 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA11 Compare window A flag of AN011 11 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA12 Compare window A flag of AN012 12 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA13 Compare window A flag of AN013 13 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA14 Compare window A flag of AN014 14 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA15 Compare window A flag of AN015 15 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 ADCMPSR1 A/D Compare Function Window A Channel Status Register 1 0xA2 16 read-write n 0x0 0x0 CMPSTCHA16 Compare window A flag of AN016 0 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA17 Compare window A flag of AN017 1 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA18 Compare window A flag of AN018 2 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA19 Compare window A flag of AN019 3 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA20 Compare window A flag of AN020 4 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA21 Compare window A flag of AN021 5 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA22 Compare window A flag of AN022 6 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA23 Compare window A flag of AN023 7 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA24 Compare window A flag of AN024 8 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA25 Compare window A flag of AN025 9 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA26 Compare window A flag of AN026 10 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 CMPSTCHA27 Compare window A flag of AN027 11 read-write zeroToClear modify 0 Comparison conditions are not met. #0 1 Comparison conditions are met. #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write ADCSR A/D Control Register 0x0 16 read-write n 0x0 0x0 ADCS Scan Mode Select 13 1 read-write 00 Single scan mode #00 01 Group scan mode #01 10 Continuous scan mode #10 11 Setting prohibited #11 ADHSC A/D Conversion Operation Mode Select 10 read-write 0 High speed A/D conversion mode #0 1 Low current A/D conversion mode #1 ADST A/D Conversion Start 15 read-write modify 0 Stops A/D conversion process. #0 1 Starts A/D conversion process. #1 DBLANS Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected. 0 4 read-write DBLE Double Trigger Mode Select 7 read-write 0 Double trigger mode non-selection #0 1 Double trigger mode selection #1 EXTRG Trigger Select 8 read-write 0 A/D conversion is started by the synchronous trigger (ELC). #0 1 A/D conversion is started by the asynchronous trigger (ADTRG0#). #1 GBADIE Group B Scan End Interrupt Enable 6 read-write 0 Disables S12GBADI0 interrupt generation upon group B scan completion. #0 1 Enables S12GBADI0 interrupt generation upon group B scan completion. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write TRGE Trigger Start Enable 9 read-write 0 Disables A/D conversion to be started by the synchronous or asynchronous trigger. #0 1 Enables A/D conversion to be started by the synchronous or asynchronous trigger. #1 ADDBLDR A/D Data Duplication Register 0x18 16 read-only n 0x0 0x0 ADDBLDR This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode. 0 15 read-only ADDBLDRA A/D Data Duplexing Register A 0x84 16 read-only n 0x0 0x0 ADDBLDRA This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDBLDRB A/D Data Duplexing Register B 0x86 16 read-only n 0x0 0x0 ADDBLDRB This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode. 0 15 read-only ADDISCR A/D Disconnection Detection Control Register 0x7A 8 read-write n 0x0 0x0 ADNDIS The charging time 0 4 read-write 0000 Disconnection detection is disabled #0000 0001 Setting prohibited #0001 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write ADDR0 A/D Data Register %s 0x40 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR1 A/D Data Register %s 0x62 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR10 A/D Data Register %s 0x1EE 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR11 A/D Data Register %s 0x224 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR12 A/D Data Register %s 0x25C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR13 A/D Data Register %s 0x296 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR14 A/D Data Register %s 0x2D2 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR15 A/D Data Register %s 0x310 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR16 A/D Data Register %s 0x350 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR17 A/D Data Register %s 0x392 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR18 A/D Data Register %s 0x3D6 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR19 A/D Data Register %s 0x41C 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR2 A/D Data Register %s 0x86 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR20 A/D Data Register %s 0x464 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR21 A/D Data Register %s 0x4AE 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR22 A/D Data Register %s 0x4FA 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR23 A/D Data Register %s 0x548 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR24 A/D Data Register %s 0x598 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR25 A/D Data Register %s 0x5EA 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR26 A/D Data Register %s 0x63E 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR27 A/D Data Register %s 0x694 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR3 A/D Data Register %s 0xAC 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR4 A/D Data Register %s 0xD4 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR5 A/D Data Register %s 0xFE 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR6 A/D Data Register %s 0x12A 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR7 A/D Data Register %s 0x158 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR8 A/D Data Register %s 0x188 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADDR9 A/D Data Register %s 0x1BA 16 read-only n 0x0 0x0 ADDR The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion. 0 15 read-only ADEXICR A/D Conversion Extended Input Control Register 0x12 16 read-write n 0x0 0x0 OCSA Internal Reference Voltage A/D Conversion Select 9 read-write 0 The internal reference voltage is not selected. #0 1 The internal reference voltage is selected for group A in single scan mode, continuous scan mode, or group scan mode. #1 OCSAD Internal Reference Voltage A/D converted Value Addition/Average Mode Select 1 read-write 0 Internal reference voltage A/D-converted value addition/average mode is not selected. #0 1 Internal reference voltage A/D-converted value addition/average mode is selected. #1 Reserved This bit is read as 0. The write value should be 0. 15 read-write Reserved This bit is read as 0. The write value should be 0. 14 read-write Reserved This bit is read as 0. The write value should be 0. 12 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write Reserved This bit is read as 0. The write value should be 0. 10 read-write TSSA Temperature Sensor Output A/D Conversion Select 8 read-write 0 The temperature sensor output is not selected. #0 1 The temperature sensor output is selected. #1 TSSAD Temperature Sensor Output A/D converted Value Addition/Average Mode Select 0 read-write 0 Temperature sensor output A/D-converted value addition/average mode is not selected. #0 1 Temperature sensor output A/D-converted value addition/average mode is selected. #1 ADGSPCR A/D Group Scan Priority Control Register 0x80 16 read-write n 0x0 0x0 GBRP Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1, single scan is performed continuously for group B regardless of the setting of the GBRSCN bit. 15 read-write 0 Single scan for group B is not continuously activated. #0 1 Single scan for group B is continuously activated. #1 GBRSCN Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.) 1 read-write 0 Scanning for group B is not restarted after having been discontinued due to group A priority control. #0 1 Scanning for group B is restarted after having been discontinued due to group A priority control. #1 PGS Group A priority control setting bit.Note: When the PGS bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values, proper operation is not guaranteed. 0 read-write 0 Operation is without group A priority control #0 1 Operation is with group A priority control #1 Reserved These bits are read as 000000. The write value should be 000000. 9 5 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write ADHVREFCNT A/D High-Potential/Low-Potential Reference Voltage Control Register 0x8A 8 read-write n 0x0 0x0 ADSLP Sleep 7 read-write 0 Normal operation #0 1 Standby state. #1 CMPAB High-Potential Reference Voltage Select 0 1 read-write 00 AVCC0 is selected as the high-potential reference voltage #00 01 VREFH0 is selected as the high-potential reference voltage #01 10 Internal reference voltage is selected as the high-potential reference voltage #10 11 Internal node discharge. No reference voltage pin is selected. #11 LVSEL Low-Potential Reference Voltage Select 2 2 read-write 0 AVSS0 is selected as the low-potential reference voltage #0 1 VREFL0 is selected as the low-potential reference voltage. #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write ADOCDR A/D Internal Reference Voltage Data Register 0x1C 16 read-only n 0x0 0x0 ADOCDR This is a 16-bit read-only register for storing the A/D result of internal reference voltage. 0 15 read-only ADRD A/D Self-Diagnosis Data Register 0x1E 16 read-only n 0x0 0x0 AD A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC. 0 13 read-only DIAGST Self-Diagnosis Status 14 1 read-only 00 Self-diagnosis has never been executed since power-on. #00 01 Self-diagnosis using the voltage of 0 V has been executed. #01 10 Self-diagnosis using the voltage of reference power supply(VREFH) x 1/2 has been executed. #10 11 Self-diagnosis using the voltage of reference power supply(VREFH) has been executed. #11 ADSSTR0 A/D Sampling State Register %s 0x1C0 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR1 A/D Sampling State Register %s 0x2A1 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR10 A/D Sampling State Register %s 0xAB7 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR11 A/D Sampling State Register %s 0xBA2 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR12 A/D Sampling State Register %s 0xC8E 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR13 A/D Sampling State Register %s 0xD7B 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR14 A/D Sampling State Register %s 0xE69 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR15 A/D Sampling State Register %s 0xF58 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR2 A/D Sampling State Register %s 0x383 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR3 A/D Sampling State Register %s 0x466 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR4 A/D Sampling State Register %s 0x54A 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR5 A/D Sampling State Register %s 0x62F 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR6 A/D Sampling State Register %s 0x715 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR7 A/D Sampling State Register %s 0x7FC 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR8 A/D Sampling State Register %s 0x8E4 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTR9 A/D Sampling State Register %s 0x9CD 8 read-write n 0x0 0x0 SST Sampling time setting 0 7 read-write ADSSTRL A/D Sampling State Register L 0xDD 8 read-write n 0x0 0x0 SST Sampling Time Setting (AN016-AN027) 0 7 read-write ADSSTRO A/D Sampling State Register O 0xDF 8 read-write n 0x0 0x0 SST Sampling Time Setting (Internal reference voltage) 0 7 read-write ADSSTRT A/D Sampling State Register T 0xDE 8 read-write n 0x0 0x0 SST Sampling Time Setting (temperature sensor output) 0 7 read-write ADSTRGR A/D Conversion Start Trigger Select Register 0x10 16 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write TRSA A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode, the A/D conversion start trigger for group A is selected. 8 5 read-write TRSB A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode. 0 5 read-write ADTSDR A/D Temperature Sensor Data Register 0x1A 16 read-only n 0x0 0x0 ADTSDR This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output. 0 15 read-only ADWINLLB A/D Compare Function Window B Lower-Side Level Setting Register 0xA8 16 read-write n 0x0 0x0 ADWINLLB This register is used to compare A window function is used to set the lower level of the window B. 0 15 read-write ADWINMON A/D Compare Function Window A/B Status Monitor Register 0x8C 8 read-only n 0x0 0x0 MONCMPA Comparison Result Monitor A 4 read-only 0 Window A comparison conditions are not met. #0 1 Window A comparison conditions are met. #1 MONCMPB Comparison Result Monitor B 5 read-only 0 Window B comparison conditions are not met. #0 1 Window B comparison conditions are met. #1 MONCOMB Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled. 0 read-only 0 Window A / window B composite conditions are not met. #0 1 Window A / window B composite conditions are met. #1 Reserved These bits are read as 00. 6 1 read-only Reserved These bits are read as 00. 6 1 read-only ADWINULB A/D Compare Function Window B Upper-Side Level Setting Register 0xAA 16 read-write n 0x0 0x0 ADWINULB This register is used to compare A window function is used to set the higher level of the window B. 0 15 read-write AGT0 Asynchronous General purpose Timer 0 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF Compare match A flag 6 read-write zeroToClear modify 0 No match #0 1 Match. #1 TCMBF Compare match B flag 7 read-write zeroToClear modify 0 No match #0 1 Match. #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count in progress. #1 TEDGF Active edge judgment flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received. #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts. #1 TSTOP AGT count forced stop 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped. #1 TUNDF Underflow flag 5 read-write zeroToClear modify 0 No match #0 1 Match. #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT Count control 6 1 read-write others settings are prohibited. 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn. #01 TIPF Input filter 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTOn output enable 2 read-write 0 AGTOn output disabled #0 1 AGTOn output enabled. #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 Select the AGTIOn except for below pins #00 01 Setting prohibited #01 10 Select the P402/AGTIOn. P402/AGTIOn is input only. It is not possible to output #10 11 Select the P403/AGTIOn. P403/AGTIOn is input only. It is not possible to output #11 TIES AGTIO input enable 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode. #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK Count source 4 2 read-write others settings are prohibited. 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0*6 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. #110 TEDGPL Edge polarity 3 read-write 0 Single-edge #0 1 Both-edge. #1 TMOD Operating mode 0 2 read-write others settings are prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode. #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS AGTLCLK/AGTSCLK count source clock frequency division ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128. #111 LPM Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write AGT1 Asynchronous General purpose Timer 1 AGT0 0x0 0x0 0x6 registers n 0x8 0x3 registers n 0xC 0x4 registers n AGT AGT Counter Register 0x0 16 read-write n 0x0 0x0 AGT 16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register, the 16-bit counter is forcibly stopped and set to FFFFH. 0 15 read-write AGTCMA AGT Compare Match A Register 0x2 16 read-write n 0x0 0x0 AGTCMA AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register, set to FFFFH 0 15 read-write AGTCMB AGT Compare Match B Register 0x4 16 read-write n 0x0 0x0 AGTCMB AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register, set to FFFFH 0 15 read-write AGTCMSR AGT Compare Match Function Select Register 0xE 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write TCMEA Compare match A register enable 0 read-write 0 Disable compare match A register #0 1 Enable compare match A register #1 TCMEB Compare match B register enable 4 read-write 0 Disable compare match B register #0 1 Enable compare match B register #1 TOEA AGTOA output enable 1 read-write 0 AGTOA output disabled (port) #0 1 AGTOA output enabled #1 TOEB AGTOB output enable 5 read-write 0 AGTOB output disabled (port) #0 1 AGTOB output enabled #1 TOPOLA AGTOA polarity select 2 read-write 0 AGTOA Output is started at low #0 1 AGTOA Output is started at high #1 TOPOLB AGTOB polarity select 6 read-write 0 AGTOB Output is started at low #0 1 AGTOB Output is started at high #1 AGTCR AGT Control Register 0x8 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write TCMAF Compare match A flag 6 read-write zeroToClear modify 0 No match #0 1 Match. #1 TCMBF Compare match B flag 7 read-write zeroToClear modify 0 No match #0 1 Match. #1 TCSTF AGT count status flag 1 read-only 0 Count stops #0 1 Count in progress. #1 TEDGF Active edge judgment flag 4 read-write zeroToClear modify 0 No active edge received #0 1 Active edge received. #1 TSTART AGT count start 0 read-write 0 Count stops #0 1 Count starts. #1 TSTOP AGT count forced stop 2 write-only 0 Writing is invalid #0 1 The count is forcibly stopped. #1 TUNDF Underflow flag 5 read-write zeroToClear modify 0 No match #0 1 Match. #1 AGTIOC AGT I/O Control Register 0xC 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TEDGSEL I/O polarity switchFunction varies depending on the operating mode. 0 read-write TIOGT Count control 6 1 read-write others settings are prohibited. 00 Event is always counted #00 01 Event is counted during polarity period specified for AGTEEn. #01 TIPF Input filter 4 1 read-write 00 No filter #00 01 Filter sampled at PCLKB #01 10 Filter sampled at PCLKB/8 #10 11 Filter sampled at PCLKB/32 #11 TOE AGTOn output enable 2 read-write 0 AGTOn output disabled #0 1 AGTOn output enabled. #1 AGTIOSEL AGT Pin Select Register 0xF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SEL AGTIO pin select 0 1 read-write 00 Select the AGTIOn except for below pins #00 01 Setting prohibited #01 10 Select the P402/AGTIOn. P402/AGTIOn is input only. It is not possible to output #10 11 Select the P403/AGTIOn. P403/AGTIOn is input only. It is not possible to output #11 TIES AGTIO input enable 4 read-write 0 External event input is disabled during Software Standby mode #0 1 External event input is enabled during Software Standby mode. #1 AGTISR AGT Event Pin Select Register 0xD 8 read-write n 0x0 0x0 EEPS AGTEE polarty selection 2 read-write 0 An event is counted during the low-level period #0 1 An event is counted during the high-level period #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write AGTMR1 AGT Mode Register 1 0x9 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write TCK Count source 4 2 read-write others settings are prohibited. 000 PCLKB #000 001 PCLKB/8 #001 011 PCLKB/2 #011 100 Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register #100 101 Underflow event signal from AGT0*6 #101 110 Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register. #110 TEDGPL Edge polarity 3 read-write 0 Single-edge #0 1 Both-edge. #1 TMOD Operating mode 0 2 read-write others settings are prohibited 000 Timer mode #000 001 Pulse output mode #001 010 Event counter mode #010 011 Pulse width measurement mode #011 100 Pulse period measurement mode. #100 AGTMR2 AGT Mode Register 2 0xA 8 read-write n 0x0 0x0 CKS AGTLCLK/AGTSCLK count source clock frequency division ratio 0 2 read-write 000 1/1 #000 001 1/2 #001 010 1/4 #010 011 1/8 #011 100 1/16 #100 101 1/32 #101 110 1/64 #110 111 1/128. #111 LPM Low Power Mode 7 read-write 0 Normal mode #0 1 Low Power mode #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write BUS BUS Control BUS 0x0 0x1000 0x10 registers n 0x1100 0x2 registers n 0x1108 0x8 registers n 0x1114 0x10 registers n 0x1128 0x2 registers n 0x1130 0xC registers n 0x1800 0x40 registers n 0x1804 0x40 registers n 0x2 0x40 registers n 0x4 0x40 registers n 0x8 0x40 registers n 0x802 0x2 registers n 0x80A 0x40 registers n 0x812 0x30 registers n 0x880 0x2 registers n BUS1ERRADD Bus Error Address Register %s 0x1800 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS1ERRSTAT Bus Error Status Register %s 0x1804 8 read-only n 0x0 0x0 ACCSTST Error Access StatusThe status at the time of the error 0 read-only 0 Read access #0 1 Write Access #1 ERRSTAT Bus Error StatusWhen bus error assert, error flag occurs. 7 read-only 0 No bus error occurred #0 1 Bus error occurred. #1 Reserved These bits are read as 000000. 1 5 read-only BUS2ERRADD Bus Error Address Register %s 0x1810 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS2ERRSTAT Bus Error Status Register %s 0x1814 8 read-only n 0x0 0x0 ACCSTST Error Access StatusThe status at the time of the error 0 read-only 0 Read access #0 1 Write Access #1 ERRSTAT Bus Error StatusWhen bus error assert, error flag occurs. 7 read-only 0 No bus error occurred #0 1 Bus error occurred. #1 Reserved These bits are read as 000000. 1 5 read-only BUS3ERRADD Bus Error Address Register %s 0x1820 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS3ERRSTAT Bus Error Status Register %s 0x1824 8 read-only n 0x0 0x0 ACCSTST Error Access StatusThe status at the time of the error 0 read-only 0 Read access #0 1 Write Access #1 ERRSTAT Bus Error StatusWhen bus error assert, error flag occurs. 7 read-only 0 No bus error occurred #0 1 Bus error occurred. #1 Reserved These bits are read as 000000. 1 5 read-only BUS4ERRADD Bus Error Address Register %s 0x1830 32 read-only n 0x0 0x0 BERAD Bus Error AddressWhen a bus error occurs, It stores an error address. 0 31 read-only BUS4ERRSTAT Bus Error Status Register %s 0x1834 8 read-only n 0x0 0x0 ACCSTST Error Access StatusThe status at the time of the error 0 read-only 0 Read access #0 1 Write Access #1 ERRSTAT Bus Error StatusWhen bus error assert, error flag occurs. 7 read-only 0 No bus error occurred #0 1 Bus error occurred. #1 Reserved These bits are read as 000000. 1 5 read-only BUSMCNTDMA Master Bus Control Register %s 0x100C 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported #0 1 A bus error is not reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSMCNTM4D Master Bus Control Register %s 0x1004 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported #0 1 A bus error is not reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSMCNTM4I Master Bus Control Register %s 0x1000 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported #0 1 A bus error is not reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSMCNTSYS Master Bus Control Register %s 0x1008 16 read-write n 0x0 0x0 IERES Ignore Error Responses 15 read-write 0 A bus error is reported #0 1 A bus error is not reported. #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 0 14 read-write BUSSCNTEXT Slave Bus Control Register %s 0x1134 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTEXT2 Slave Bus Control Register %s 0x1138 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTFBU Slave Bus Control Register %s 0x1130 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTFLI Slave Bus Control Register FLI 0x1100 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTMBIU Slave Bus Control Register %s 0x1108 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTP0B Slave Bus Control Register %s 0x1114 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTP2B Slave Bus Control Register %s 0x1118 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTP3B Slave Bus Control Register %s 0x111C 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTP4B Slave Bus Control Register %s 0x1120 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTP6B Slave Bus Control Register P6B 0x1128 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write BUSSCNTRAM0 Slave Bus Control Register %s 0x110C 16 read-write n 0x0 0x0 ARBMET Arbitration MethodSpecify the priority between groups 4 1 read-write others Setting prohibited 00 fixed priority #00 01 round-robin #01 Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 6 9 read-write CS0CR CS0 Control Register 0x802 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 16-bit bus space #00 01 Setting prohibited #01 10 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disabled #0 1 Enabled #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area 0. #0 1 Address/data multiplexed I/O interface is selected for area 0. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CS0MOD CS%s Mode Register 0x2 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disabled #0 1 Enabled #1 PRDMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PRENB Page Read Access Enable 8 read-write 0 Disabled #0 1 Enabled #1 PWENB Page Write Access Enable 9 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS0REC CS%s Recovery Cycle Register 0x80A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS0WCR1 CS%s Wait Control Register 1 0x4 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write CS0WCR2 CS%s Wait Control Register 2 0x8 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS1CR CS%s Control Register 0x812 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 16-bit bus space #00 01 Setting prohibited #01 10 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disabled #0 1 Enabled #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area 0. #0 1 Address/data multiplexed I/O interface is selected for area 0. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CS1MOD CS%s Mode Register 0x12 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disabled #0 1 Enabled #1 PRDMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PRENB Page Read Access Enable 8 read-write 0 Disabled #0 1 Enabled #1 PWENB Page Write Access Enable 9 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS1REC CS%s Recovery Cycle Register 0x81A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS1WCR1 CS%s Wait Control Register 1 0x14 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write CS1WCR2 CS%s Wait Control Register 2 0x18 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS2CR CS%s Control Register 0x822 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 16-bit bus space #00 01 Setting prohibited #01 10 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disabled #0 1 Enabled #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area 0. #0 1 Address/data multiplexed I/O interface is selected for area 0. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CS2MOD CS%s Mode Register 0x22 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disabled #0 1 Enabled #1 PRDMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PRENB Page Read Access Enable 8 read-write 0 Disabled #0 1 Enabled #1 PWENB Page Write Access Enable 9 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS2REC CS%s Recovery Cycle Register 0x82A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS2WCR1 CS%s Wait Control Register 1 0x24 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write CS2WCR2 CS%s Wait Control Register 2 0x28 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CS3CR CS%s Control Register 0x832 16 read-write n 0x0 0x0 BSIZE External Bus Width Select 4 1 read-write 00 16-bit bus space #00 01 Setting prohibited #01 10 8-bit bus space #10 11 Setting prohibited #11 EMODE Endian Mode 8 read-write 0 Little Endian #0 1 Big Endian #1 EXENB Operation Enable 0 read-write 0 Disabled #0 1 Enabled #1 MPXEN Address/Data Multiplexed I/O Interface Select 12 read-write 0 Separate bus interface is selected for area 0. #0 1 Address/data multiplexed I/O interface is selected for area 0. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CS3MOD CS%s Mode Register 0x32 16 read-write n 0x0 0x0 EWENB External Wait Enable 3 read-write 0 Disabled #0 1 Enabled #1 PRDMOD Page Read Access Mode Select 15 read-write 0 Normal access compatible mode #0 1 External data read continuous assertion mode #1 PRENB Page Read Access Enable 8 read-write 0 Disabled #0 1 Enabled #1 PWENB Page Write Access Enable 9 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write WRMOD Write Access Mode Select 0 read-write 0 Byte strobe mode #0 1 Single write strobe mode #1 CS3REC CS%s Recovery Cycle Register 0x83A 16 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RRCV Read Recovery 0 3 read-write others RRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 WRCV Write Recovery 8 3 read-write others WRCV recovery cycle is inserted. 0x0 No recovery cycle is inserted. 0x0 CS3WCR1 CS%s Wait Control Register 1 0x34 32 read-write n 0x0 0x0 CSPRWAIT Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1. 8 2 read-write others Wait with a length of CSPRWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSPWWAIT Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1. 0 2 read-write others Wait with a length of CSPWWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRWAIT Normal Read Cycle Wait Select 24 4 read-write others Wait with a length of CSRWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 CSWWAIT Normal Write Cycle Wait Select 16 4 read-write others Wait with a length of CSWWAIT clock cycle is inserted. 0x00 No wait is inserted. 0x00 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 000. The write value should be 000. 21 2 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write CS3WCR2 CS%s Wait Control Register 2 0x38 32 read-write n 0x0 0x0 AWAIT Address Cycle Wait Select 12 1 read-write others Wait with a length of AWAIT clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSON CS Assert Wait Select 28 2 read-write others Wait with a length of CSON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSROFF Read-Access CS Extension Cycle Select 0 2 read-write others Wait with a length of CSROFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSWOFF Write-Access CS Extension Cycle Select 4 2 read-write others Wait with a length of CSWOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 RDON RD Assert Wait Select 16 2 read-write others Wait with a length of RDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 19 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write WDOFF Write Data Output Extension Cycle Select 8 2 read-write others Wait with a length of WDOFF clock cycle is inserted. 0x0 No wait is inserted. 0x0 WDON Write Data Output Wait Select 24 2 read-write others Wait with a length of WDON clock cycle is inserted. 0x0 No wait is inserted. 0x0 WRON WR Assert Wait Select 20 2 read-write others Wait with a length of WRON clock cycle is inserted. 0x0 No wait is inserted. 0x0 CSRECEN CS Recovery Cycle Insertion Enable Register 0x880 16 read-write n 0x0 0x0 RECVEN0 Separate Bus Recovery Cycle Insertion Enable 0 0 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN1 Separate Bus Recovery Cycle Insertion Enable 1 1 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN2 Separate Bus Recovery Cycle Insertion Enable 2 2 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN3 Separate Bus Recovery Cycle Insertion Enable 3 3 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN4 Separate Bus Recovery Cycle Insertion Enable 4 4 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN5 Separate Bus Recovery Cycle Insertion Enable 5 5 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN6 Separate Bus Recovery Cycle Insertion Enable 6 6 read-write 0 Disabled. #0 1 Enabled. #1 RECVEN7 Separate Bus Recovery Cycle Insertion Enable 7 7 read-write 0 Disabled. #0 1 Enabled. #1 RECVENM0 Multiplexed Bus Recovery Cycle Insertion Enable 0 8 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM1 Multiplexed Bus Recovery Cycle Insertion Enable 1 9 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM2 Multiplexed Bus Recovery Cycle Insertion Enable 2 10 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM3 Multiplexed Bus Recovery Cycle Insertion Enable 3 11 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM4 Multiplexed Bus Recovery Cycle Insertion Enable 4 12 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM5 Multiplexed Bus Recovery Cycle Insertion Enable 5 13 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM6 Multiplexed Bus Recovery Cycle Insertion Enable 6 14 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 RECVENM7 Multiplexed Bus Recovery Cycle Insertion Enable 7 15 read-write 0 Recovery cycle insertion is disabled. #0 1 Recovery cycle insertion is enabled. #1 CAC Clock Frequency Accuracy Measurement Circuit CAC 0x0 0x0 0x5 registers n 0x6 0x6 registers n CACNTBR CAC Counter Buffer Register 0xA 16 read-only n 0x0 0x0 CACNTBR CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input 0 15 read-only CACR0 CAC Control Register 0 0x0 8 read-write n 0x0 0x0 CFME Clock Frequency Measurement Enable. 0 read-write 0 Disable #0 1 Enable #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write CACR1 CAC Control Register 1 0x1 8 read-write n 0x0 0x0 CACREFE CACREF Pin Input Enable 0 read-write 0 Disable #0 1 Enable #1 EDGES Valid Edge Select 6 1 read-write 00 Rising edge #00 01 Falling edge #01 10 Both rising and falling edges #10 11 Setting prohibited #11 FMCS Measurement Target Clock Select 1 2 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 TCSS Measurement Target Clock Frequency Division Ratio Select 4 1 read-write 00 No division #00 01 x 1/4 clock #01 10 x 1/8 clock #10 11 x 1/32 clock #11 CACR2 CAC Control Register 2 0x2 8 read-write n 0x0 0x0 DFS Digital Filter Selection 6 1 read-write 00 Digital filtering is disabled. #00 01 The sampling clock for the digital filter is the frequency measuring clock. #01 10 The sampling clock for the digital filter is the frequency measuring clock divided by 4. #10 11 The sampling clock for the digital filter is the frequency measuring clock divided by 16. #11 RCDS Measurement Reference Clock Frequency Division Ratio Select 4 1 read-write 00 1/32 clock #00 01 1/128 clock #01 10 1/1024 clock #10 11 1/8192 clock #11 RPS Reference Signal Select 0 read-write 0 CACREF pin input #0 1 Internal clock (internally generated signal) #1 RSCS Measurement Reference Clock Select 1 2 read-write 000 Main clock #000 001 Sub-clock #001 010 HOCO clock #010 011 MOCO clock #011 100 LOCO clock #100 101 Peripheral module clock(PCLKB) #101 110 IWDTCLK clock #110 111 Setting prohibited #111 CAICR CAC Interrupt Control Register 0x3 8 read-write n 0x0 0x0 FERRFCL FERRF Clear 4 write-only 0 No effect on operations #0 1 Clears the FERRF flag #1 FERRIE Frequency Error Interrupt Request Enable 0 read-write 0 Disable #0 1 Enable #1 MENDFCL MENDF Clear 5 write-only 0 No effect on operations #0 1 Clears the MENDF flag #1 MENDIE Measurement End Interrupt Request Enable 1 read-write 0 Disable #0 1 Enable #1 OVFFCL OVFF Clear 6 write-only 0 No effect on operations #0 1 Clears the OVFF flag #1 OVFIE Overflow Interrupt Request Enable 2 read-write 0 Disable #0 1 Enable #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write CALLVR CAC Lower-Limit Value Setting Register 0x8 16 read-write n 0x0 0x0 CALLVR CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency. 0 15 read-write CASTR CAC Status Register 0x4 8 read-only n 0x0 0x0 FERRF Frequency Error Flag 0 read-only 0 The clock frequency is within the range corresponding to the settings. #0 1 The clock frequency has deviated beyond the range corresponding to the settings (frequency error). #1 MENDF Measurement End Flag 1 read-only 0 Measurement is in progress. #0 1 Measurement has ended. #1 OVFF Counter Overflow Flag 2 read-only 0 The counter has not overflowed. #0 1 The counter has overflowed. #1 CAULVR CAC Upper-Limit Value Setting Register 0x6 16 read-write n 0x0 0x0 CAULVR CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency. 0 15 read-write CAN0 CAN0 Module CAN0 0x0 0x200 0x200 registers n 0x204 0x200 registers n 0x206 0x200 registers n 0x207 0x200 registers n 0x208 0x200 registers n 0x209 0x200 registers n 0x20A 0x200 registers n 0x20B 0x200 registers n 0x20C 0x200 registers n 0x20D 0x200 registers n 0x20E 0x200 registers n 0x400 0x30 registers n 0x42C 0x4 registers n 0x820 0x20 registers n 0x820 0x39 registers n 0x820 0x20 registers n AFSR Acceptance Filter Support Register 0x856 16 read-write n 0x0 0x0 AFSR After the standard ID of a received message is written, the value converted for data table search can be read. 0 15 read-write BCR Bit Configuration Register 0x844 32 read-write n 0x0 0x0 BRP Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). 16 9 read-write CCLKS CAN Clock Source Selection 0 read-write 0 PCLK (generated by the PLL clock) #0 1 CANMCLK (generated by the main clock) #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 00. The write value should be 00. 14 1 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write SJW Resynchronization Jump Width Control 12 1 read-write 00 1 Tq #00 01 2 Tq #01 10 3 Tq #10 11 4 Tq #11 TSEG1 Time Segment 1 Control 28 3 read-write others Setting prohibited 0011 4 Tq #0011 0100 5 Tq #0100 0101 6 Tq #0101 0110 7 Tq #0110 0111 8 Tq #0111 1000 9 Tq #1000 1001 10 Tq #1001 1010 11 Tq #1010 1011 12 Tq #1011 1100 13 Tq #1100 1101 14 Tq #1101 1110 15 Tq #1110 1111 16 Tq #1111 TSEG2 Time Segment 2 Control 8 2 read-write 000 Setting prohibited #000 001 2 Tq #001 010 3 Tq #010 011 4 Tq #011 100 5 Tq #100 101 6 Tq #101 110 7 Tq #110 111 8 Tq #111 CSSR Channel Search Support Register 0x851 8 read-write n 0x0 0x0 CSSR When the value for the channel search is input, the channel number is output to MSSR. 0 7 read-write CTLR Control Register 0x840 16 read-write n 0x0 0x0 BOM Bus-Off Recovery Mode by a program request 11 1 read-write 00 Normal mode (ISO11898-1 compliant) #00 01 Entry to CAN halt mode automatically at bus-off entry #01 10 Entry to CAN halt mode automatically at bus-off end #10 11 Entry to CAN halt mode (during bus-off recovery period) #11 CANM CAN Operating Mode Select 8 1 read-write 00 CAN operation mode #00 01 CAN reset mode #01 10 CAN halt mode #10 11 CAN reset mode (forcible transition) #11 IDFM ID Format Mode Select 1 1 read-write 00 Standard ID mode.All mailboxes (including FIFO mailboxes) handle only standard Ids. #00 01 Extended ID mode.All mailboxes (including FIFO mailboxes) handle only extended IDs. #01 10 Mixed ID mode.All mailboxes (including FIFO mailboxes) handle both standard IDs and extended IDs. Standard IDs or extended IDs are specified by using the IDE bit in the corresponding mailbox in normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for mailboxes [0] to [23], the IDE bits in FIDCR0 and FIDCR1 are used for the receive FIFO, and the IDE bit in mailbox [24] is used for the transmit FIFO. #10 11 Do not use this combination #11 MBM CAN Mailbox Mode Select 0 read-write 0 Normal mailbox mode #0 1 FIFO mailbox mode #1 MLM Message Lost Mode Select 3 read-write 0 Overwrite mode #0 1 Overrun mode #1 RBOC Forcible Return From Bus-Off 13 read-write 0 Nothing occurred #0 1 Forcible return from bus-off #1 Reserved These bits are read as 00. The write value should be 00. 14 1 read-write SLPM CAN Sleep Mode 10 read-write 0 Other than CAN sleep mode #0 1 CAN sleep mode #1 TPM Transmission Priority Mode Select 4 read-write 0 ID priority transmit mode #0 1 Mailbox number priority transmit mode #1 TSPS Time Stamp Prescaler Select 6 1 read-write 00 Every bit time #00 01 Every 2-bit time #01 10 Every 4-bit time #10 11 Every 8-bit time #11 TSRC Time Stamp Counter Reset Command 5 read-write 0 Nothing occurred #0 1 Reset #1 ECSR Error Code Store Register 0x850 8 read-write n 0x0 0x0 ADEF ACK Delimiter Error Flag 6 read-write 0 No ACK delimiter error detected #0 1 ACK delimiter error detected #1 AEF ACK Error Flag 2 read-write 0 No ACK error detected #0 1 ACK error detected #1 BE0F Bit Error (dominant) Flag 5 read-write 0 No bit error (dominant) detected #0 1 Bit error (dominant) detected #1 BE1F Bit Error (recessive) Flag 4 read-write 0 No bit error (recessive) detected #0 1 Bit error (recessive) detected #1 CEF CRC Error Flag 3 read-write 0 No CRC error detected #0 1 CRC error detected #1 EDPM Error Display Mode Select 7 read-write 0 Output of first detected error code #0 1 Output of accumulated error code #1 FEF Form Error Flag 1 read-write 0 No form error detected #0 1 Form error detected #1 SEF Stuff Error Flag 0 read-write 0 No stuff error detected #0 1 Stuff error detected #1 EIER Error Interrupt Enable Register 0x84C 8 read-write n 0x0 0x0 BEIE Bus Error Interrupt Enable 0 read-write 0 Bus error interrupt disabled #0 1 Bus error interrupt enabled #1 BLIE Bus Lock Interrupt Enable 7 read-write 0 Bus lock interrupt disabled #0 1 Bus lock interrupt enabled #1 BOEIE Bus-Off Entry Interrupt Enable 3 read-write 0 Bus-off entry interrupt disabled #0 1 Bus-off entry interrupt enabled #1 BORIE Bus-Off Recovery Interrupt Enable 4 read-write 0 Bus-off recovery interrupt disabled #0 1 Bus-off recovery interrupt enabled #1 EPIE Error-Passive Interrupt Enable 2 read-write 0 Error-passive interrupt disabled #0 1 Error-passive interrupt enabled #1 EWIE Error-Warning Interrupt Enable 1 read-write 0 Error-warning interrupt disabled #0 1 Error-warning interrupt enabled #1 OLIE Overload Frame Transmit Interrupt Enable 6 read-write 0 Overload frame transmit interrupt disabled #0 1 Overload frame transmit interrupt enabled #1 ORIE Overrun Interrupt Enable 5 read-write 0 Receive overrun interrupt disabled #0 1 Receive overrun interrupt enabled #1 EIFR Error Interrupt Factor Judge Register 0x84D 8 read-write n 0x0 0x0 BEIF Bus Error Detect Flag 0 read-write 0 No bus error detected #0 1 Bus error detected #1 BLIF Bus Lock Detect Flag 7 read-write 0 No bus lock detected #0 1 Bus lock detected #1 BOEIF Bus-Off Entry Detect Flag 3 read-write 0 No bus-off entry detected #0 1 Bus-off entry detected #1 BORIF Bus-Off Recovery Detect Flag 4 read-write 0 No bus-off recovery detected #0 1 Bus-off recovery detected #1 EPIF Error-Passive Detect Flag 2 read-write 0 No error-passive detected #0 1 Error-passive detected #1 EWIF Error-Warning Detect Flag 1 read-write 0 No error-warning detected #0 1 Error-warning detected #1 OLIF Overload Frame Transmission Detect Flag 6 read-write 0 No overload frame transmission detected #0 1 Overload frame transmission detected #1 ORIF Receive Overrun Detect Flag 5 read-write 0 No receive overrun detected #0 1 Receive overrun detected #1 FIDCR0 FIFO Received ID Compare Registers 0x420 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write FIDCR1 FIFO Received ID Compare Registers 0x424 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB0_D0 Mailbox Register 0x206 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D1 Mailbox Register 0x207 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D2 Mailbox Register 0x208 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D3 Mailbox Register 0x209 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D4 Mailbox Register 0x20A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D5 Mailbox Register 0x20B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D6 Mailbox Register 0x20C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_D7 Mailbox Register 0x20D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB0_DL Mailbox Register 0x204 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB0_ID Mailbox Register 0x200 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB0_TS Mailbox Register 0x20E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB10_D0 Mailbox Register 0x2A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D1 Mailbox Register 0x2A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D2 Mailbox Register 0x2A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D3 Mailbox Register 0x2A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D4 Mailbox Register 0x2AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D5 Mailbox Register 0x2AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D6 Mailbox Register 0x2AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_D7 Mailbox Register 0x2AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB10_DL Mailbox Register 0x2A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB10_ID Mailbox Register 0x2A0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB10_TS Mailbox Register 0x2AE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB11_D0 Mailbox Register 0x2B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D1 Mailbox Register 0x2B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D2 Mailbox Register 0x2B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D3 Mailbox Register 0x2B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D4 Mailbox Register 0x2BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D5 Mailbox Register 0x2BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D6 Mailbox Register 0x2BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_D7 Mailbox Register 0x2BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB11_DL Mailbox Register 0x2B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB11_ID Mailbox Register 0x2B0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB11_TS Mailbox Register 0x2BE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB12_D0 Mailbox Register 0x2C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D1 Mailbox Register 0x2C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D2 Mailbox Register 0x2C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D3 Mailbox Register 0x2C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D4 Mailbox Register 0x2CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D5 Mailbox Register 0x2CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D6 Mailbox Register 0x2CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_D7 Mailbox Register 0x2CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB12_DL Mailbox Register 0x2C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB12_ID Mailbox Register 0x2C0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB12_TS Mailbox Register 0x2CE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB13_D0 Mailbox Register 0x2D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D1 Mailbox Register 0x2D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D2 Mailbox Register 0x2D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D3 Mailbox Register 0x2D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D4 Mailbox Register 0x2DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D5 Mailbox Register 0x2DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D6 Mailbox Register 0x2DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_D7 Mailbox Register 0x2DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB13_DL Mailbox Register 0x2D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB13_ID Mailbox Register 0x2D0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB13_TS Mailbox Register 0x2DE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB14_D0 Mailbox Register 0x2E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D1 Mailbox Register 0x2E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D2 Mailbox Register 0x2E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D3 Mailbox Register 0x2E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D4 Mailbox Register 0x2EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D5 Mailbox Register 0x2EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D6 Mailbox Register 0x2EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_D7 Mailbox Register 0x2ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB14_DL Mailbox Register 0x2E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB14_ID Mailbox Register 0x2E0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB14_TS Mailbox Register 0x2EE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB15_D0 Mailbox Register 0x2F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D1 Mailbox Register 0x2F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D2 Mailbox Register 0x2F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D3 Mailbox Register 0x2F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D4 Mailbox Register 0x2FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D5 Mailbox Register 0x2FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D6 Mailbox Register 0x2FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_D7 Mailbox Register 0x2FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB15_DL Mailbox Register 0x2F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB15_ID Mailbox Register 0x2F0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB15_TS Mailbox Register 0x2FE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB16_D0 Mailbox Register 0x306 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D1 Mailbox Register 0x307 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D2 Mailbox Register 0x308 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D3 Mailbox Register 0x309 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D4 Mailbox Register 0x30A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D5 Mailbox Register 0x30B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D6 Mailbox Register 0x30C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_D7 Mailbox Register 0x30D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB16_DL Mailbox Register 0x304 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB16_ID Mailbox Register 0x300 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB16_TS Mailbox Register 0x30E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB17_D0 Mailbox Register 0x316 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D1 Mailbox Register 0x317 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D2 Mailbox Register 0x318 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D3 Mailbox Register 0x319 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D4 Mailbox Register 0x31A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D5 Mailbox Register 0x31B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D6 Mailbox Register 0x31C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_D7 Mailbox Register 0x31D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB17_DL Mailbox Register 0x314 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB17_ID Mailbox Register 0x310 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB17_TS Mailbox Register 0x31E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB18_D0 Mailbox Register 0x326 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D1 Mailbox Register 0x327 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D2 Mailbox Register 0x328 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D3 Mailbox Register 0x329 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D4 Mailbox Register 0x32A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D5 Mailbox Register 0x32B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D6 Mailbox Register 0x32C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_D7 Mailbox Register 0x32D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB18_DL Mailbox Register 0x324 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB18_ID Mailbox Register 0x320 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB18_TS Mailbox Register 0x32E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB19_D0 Mailbox Register 0x336 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D1 Mailbox Register 0x337 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D2 Mailbox Register 0x338 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D3 Mailbox Register 0x339 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D4 Mailbox Register 0x33A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D5 Mailbox Register 0x33B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D6 Mailbox Register 0x33C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_D7 Mailbox Register 0x33D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB19_DL Mailbox Register 0x334 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB19_ID Mailbox Register 0x330 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB19_TS Mailbox Register 0x33E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB1_D0 Mailbox Register 0x216 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D1 Mailbox Register 0x217 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D2 Mailbox Register 0x218 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D3 Mailbox Register 0x219 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D4 Mailbox Register 0x21A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D5 Mailbox Register 0x21B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D6 Mailbox Register 0x21C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_D7 Mailbox Register 0x21D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB1_DL Mailbox Register 0x214 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB1_ID Mailbox Register 0x210 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB1_TS Mailbox Register 0x21E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB20_D0 Mailbox Register 0x346 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D1 Mailbox Register 0x347 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D2 Mailbox Register 0x348 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D3 Mailbox Register 0x349 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D4 Mailbox Register 0x34A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D5 Mailbox Register 0x34B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D6 Mailbox Register 0x34C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_D7 Mailbox Register 0x34D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB20_DL Mailbox Register 0x344 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB20_ID Mailbox Register 0x340 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB20_TS Mailbox Register 0x34E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB21_D0 Mailbox Register 0x356 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D1 Mailbox Register 0x357 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D2 Mailbox Register 0x358 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D3 Mailbox Register 0x359 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D4 Mailbox Register 0x35A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D5 Mailbox Register 0x35B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D6 Mailbox Register 0x35C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_D7 Mailbox Register 0x35D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB21_DL Mailbox Register 0x354 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB21_ID Mailbox Register 0x350 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB21_TS Mailbox Register 0x35E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB22_D0 Mailbox Register 0x366 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D1 Mailbox Register 0x367 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D2 Mailbox Register 0x368 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D3 Mailbox Register 0x369 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D4 Mailbox Register 0x36A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D5 Mailbox Register 0x36B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D6 Mailbox Register 0x36C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_D7 Mailbox Register 0x36D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB22_DL Mailbox Register 0x364 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB22_ID Mailbox Register 0x360 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB22_TS Mailbox Register 0x36E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB23_D0 Mailbox Register 0x376 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D1 Mailbox Register 0x377 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D2 Mailbox Register 0x378 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D3 Mailbox Register 0x379 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D4 Mailbox Register 0x37A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D5 Mailbox Register 0x37B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D6 Mailbox Register 0x37C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_D7 Mailbox Register 0x37D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB23_DL Mailbox Register 0x374 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB23_ID Mailbox Register 0x370 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB23_TS Mailbox Register 0x37E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB24_D0 Mailbox Register 0x386 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D1 Mailbox Register 0x387 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D2 Mailbox Register 0x388 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D3 Mailbox Register 0x389 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D4 Mailbox Register 0x38A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D5 Mailbox Register 0x38B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D6 Mailbox Register 0x38C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_D7 Mailbox Register 0x38D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB24_DL Mailbox Register 0x384 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB24_ID Mailbox Register 0x380 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB24_TS Mailbox Register 0x38E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB25_D0 Mailbox Register 0x396 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D1 Mailbox Register 0x397 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D2 Mailbox Register 0x398 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D3 Mailbox Register 0x399 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D4 Mailbox Register 0x39A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D5 Mailbox Register 0x39B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D6 Mailbox Register 0x39C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_D7 Mailbox Register 0x39D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB25_DL Mailbox Register 0x394 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB25_ID Mailbox Register 0x390 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB25_TS Mailbox Register 0x39E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB26_D0 Mailbox Register 0x3A6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D1 Mailbox Register 0x3A7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D2 Mailbox Register 0x3A8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D3 Mailbox Register 0x3A9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D4 Mailbox Register 0x3AA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D5 Mailbox Register 0x3AB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D6 Mailbox Register 0x3AC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_D7 Mailbox Register 0x3AD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB26_DL Mailbox Register 0x3A4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB26_ID Mailbox Register 0x3A0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB26_TS Mailbox Register 0x3AE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB27_D0 Mailbox Register 0x3B6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D1 Mailbox Register 0x3B7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D2 Mailbox Register 0x3B8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D3 Mailbox Register 0x3B9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D4 Mailbox Register 0x3BA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D5 Mailbox Register 0x3BB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D6 Mailbox Register 0x3BC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_D7 Mailbox Register 0x3BD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB27_DL Mailbox Register 0x3B4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB27_ID Mailbox Register 0x3B0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB27_TS Mailbox Register 0x3BE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB28_D0 Mailbox Register 0x3C6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D1 Mailbox Register 0x3C7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D2 Mailbox Register 0x3C8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D3 Mailbox Register 0x3C9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D4 Mailbox Register 0x3CA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D5 Mailbox Register 0x3CB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D6 Mailbox Register 0x3CC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_D7 Mailbox Register 0x3CD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB28_DL Mailbox Register 0x3C4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB28_ID Mailbox Register 0x3C0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB28_TS Mailbox Register 0x3CE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB29_D0 Mailbox Register 0x3D6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D1 Mailbox Register 0x3D7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D2 Mailbox Register 0x3D8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D3 Mailbox Register 0x3D9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D4 Mailbox Register 0x3DA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D5 Mailbox Register 0x3DB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D6 Mailbox Register 0x3DC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_D7 Mailbox Register 0x3DD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB29_DL Mailbox Register 0x3D4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB29_ID Mailbox Register 0x3D0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB29_TS Mailbox Register 0x3DE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB2_D0 Mailbox Register 0x226 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D1 Mailbox Register 0x227 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D2 Mailbox Register 0x228 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D3 Mailbox Register 0x229 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D4 Mailbox Register 0x22A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D5 Mailbox Register 0x22B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D6 Mailbox Register 0x22C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_D7 Mailbox Register 0x22D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB2_DL Mailbox Register 0x224 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB2_ID Mailbox Register 0x220 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB2_TS Mailbox Register 0x22E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB30_D0 Mailbox Register 0x3E6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D1 Mailbox Register 0x3E7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D2 Mailbox Register 0x3E8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D3 Mailbox Register 0x3E9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D4 Mailbox Register 0x3EA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D5 Mailbox Register 0x3EB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D6 Mailbox Register 0x3EC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_D7 Mailbox Register 0x3ED 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB30_DL Mailbox Register 0x3E4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB30_ID Mailbox Register 0x3E0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB30_TS Mailbox Register 0x3EE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB31_D0 Mailbox Register 0x3F6 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D1 Mailbox Register 0x3F7 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D2 Mailbox Register 0x3F8 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D3 Mailbox Register 0x3F9 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D4 Mailbox Register 0x3FA 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D5 Mailbox Register 0x3FB 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D6 Mailbox Register 0x3FC 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_D7 Mailbox Register 0x3FD 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB31_DL Mailbox Register 0x3F4 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB31_ID Mailbox Register 0x3F0 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB31_TS Mailbox Register 0x3FE 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB3_D0 Mailbox Register 0x236 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D1 Mailbox Register 0x237 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D2 Mailbox Register 0x238 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D3 Mailbox Register 0x239 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D4 Mailbox Register 0x23A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D5 Mailbox Register 0x23B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D6 Mailbox Register 0x23C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_D7 Mailbox Register 0x23D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB3_DL Mailbox Register 0x234 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB3_ID Mailbox Register 0x230 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB3_TS Mailbox Register 0x23E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB4_D0 Mailbox Register 0x246 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D1 Mailbox Register 0x247 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D2 Mailbox Register 0x248 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D3 Mailbox Register 0x249 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D4 Mailbox Register 0x24A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D5 Mailbox Register 0x24B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D6 Mailbox Register 0x24C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_D7 Mailbox Register 0x24D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB4_DL Mailbox Register 0x244 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB4_ID Mailbox Register 0x240 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB4_TS Mailbox Register 0x24E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB5_D0 Mailbox Register 0x256 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D1 Mailbox Register 0x257 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D2 Mailbox Register 0x258 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D3 Mailbox Register 0x259 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D4 Mailbox Register 0x25A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D5 Mailbox Register 0x25B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D6 Mailbox Register 0x25C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_D7 Mailbox Register 0x25D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB5_DL Mailbox Register 0x254 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB5_ID Mailbox Register 0x250 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB5_TS Mailbox Register 0x25E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB6_D0 Mailbox Register 0x266 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D1 Mailbox Register 0x267 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D2 Mailbox Register 0x268 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D3 Mailbox Register 0x269 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D4 Mailbox Register 0x26A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D5 Mailbox Register 0x26B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D6 Mailbox Register 0x26C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_D7 Mailbox Register 0x26D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB6_DL Mailbox Register 0x264 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB6_ID Mailbox Register 0x260 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB6_TS Mailbox Register 0x26E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB7_D0 Mailbox Register 0x276 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D1 Mailbox Register 0x277 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D2 Mailbox Register 0x278 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D3 Mailbox Register 0x279 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D4 Mailbox Register 0x27A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D5 Mailbox Register 0x27B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D6 Mailbox Register 0x27C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_D7 Mailbox Register 0x27D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB7_DL Mailbox Register 0x274 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB7_ID Mailbox Register 0x270 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB7_TS Mailbox Register 0x27E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB8_D0 Mailbox Register 0x286 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D1 Mailbox Register 0x287 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D2 Mailbox Register 0x288 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D3 Mailbox Register 0x289 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D4 Mailbox Register 0x28A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D5 Mailbox Register 0x28B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D6 Mailbox Register 0x28C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_D7 Mailbox Register 0x28D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB8_DL Mailbox Register 0x284 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB8_ID Mailbox Register 0x280 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB8_TS Mailbox Register 0x28E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MB9_D0 Mailbox Register 0x296 8 read-write n 0x0 0x0 DATA0 Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D1 Mailbox Register 0x297 8 read-write n 0x0 0x0 DATA1 Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D2 Mailbox Register 0x298 8 read-write n 0x0 0x0 DATA2 Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D3 Mailbox Register 0x299 8 read-write n 0x0 0x0 DATA3 Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D4 Mailbox Register 0x29A 8 read-write n 0x0 0x0 DATA4 Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D5 Mailbox Register 0x29B 8 read-write n 0x0 0x0 DATA5 Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D6 Mailbox Register 0x29C 8 read-write n 0x0 0x0 DATA6 Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_D7 Mailbox Register 0x29D 8 read-write n 0x0 0x0 DATA7 Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from bit 7. 0 7 read-write MB9_DL Mailbox Register 0x294 16 read-write n 0x0 0x0 DLC Data Length Code 0 3 read-write others Data length = 8 bytes 0000 Data length = 0 byte #0000 0001 Data length = 1 byte #0001 0010 Data length = 2 bytes #0010 0011 Data length = 3 bytes #0011 0100 Data length = 4 bytes #0100 0101 Data length = 5 bytes #0101 0110 Data length = 6 bytes #0110 0111 Data length = 7 bytes #0111 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write MB9_ID Mailbox Register 0x290 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write IDE ID Extension 31 read-write 0 Standard ID #0 1 Extended ID #1 Reserved This bit is read as 0. The write value should be 0. 29 read-write RTR Remote Transmission Request 30 read-write 0 Data frame #0 1 Remote frame #1 SID Standard ID 18 10 read-write MB9_TS Mailbox Register 0x29E 16 read-write n 0x0 0x0 TSH Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 8 7 read-write TSL Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox. 0 7 read-write MCTL_RX0 Message Control Register for Receive MCTL_TX[%s] 0x820 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX1 Message Control Register for Receive MCTL_TX[%s] 0x821 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX10 Message Control Register for Receive MCTL_TX[%s] 0x82A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX11 Message Control Register for Receive MCTL_TX[%s] 0x82B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX12 Message Control Register for Receive MCTL_TX[%s] 0x82C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX13 Message Control Register for Receive MCTL_TX[%s] 0x82D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX14 Message Control Register for Receive MCTL_TX[%s] 0x82E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX15 Message Control Register for Receive MCTL_TX[%s] 0x82F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX16 Message Control Register for Receive MCTL_TX[%s] 0x830 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX17 Message Control Register for Receive MCTL_TX[%s] 0x831 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX18 Message Control Register for Receive MCTL_TX[%s] 0x832 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX19 Message Control Register for Receive MCTL_TX[%s] 0x833 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX2 Message Control Register for Receive MCTL_TX[%s] 0x822 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX20 Message Control Register for Receive MCTL_TX[%s] 0x834 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX21 Message Control Register for Receive MCTL_TX[%s] 0x835 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX22 Message Control Register for Receive MCTL_TX[%s] 0x836 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX23 Message Control Register for Receive MCTL_TX[%s] 0x837 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX24 Message Control Register for Receive MCTL_TX[%s] 0x838 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX25 Message Control Register for Receive MCTL_TX[%s] 0x839 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX26 Message Control Register for Receive MCTL_TX[%s] 0x83A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX27 Message Control Register for Receive MCTL_TX[%s] 0x83B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX28 Message Control Register for Receive MCTL_TX[%s] 0x83C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX29 Message Control Register for Receive MCTL_TX[%s] 0x83D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX3 Message Control Register for Receive MCTL_TX[%s] 0x823 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX30 Message Control Register for Receive MCTL_TX[%s] 0x83E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX31 Message Control Register for Receive MCTL_TX[%s] 0x83F 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX4 Message Control Register for Receive MCTL_TX[%s] 0x824 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX5 Message Control Register for Receive MCTL_TX[%s] 0x825 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX6 Message Control Register for Receive MCTL_TX[%s] 0x826 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX7 Message Control Register for Receive MCTL_TX[%s] 0x827 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX8 Message Control Register for Receive MCTL_TX[%s] 0x828 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX9 Message Control Register for Receive MCTL_TX[%s] 0x829 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[0] Message Control Register for Receive MCTL_TX[%s] 0x1040 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[10] Message Control Register for Receive MCTL_TX[%s] 0x61B7 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[11] Message Control Register for Receive MCTL_TX[%s] 0x69E2 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[12] Message Control Register for Receive MCTL_TX[%s] 0x720E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[13] Message Control Register for Receive MCTL_TX[%s] 0x7A3B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[14] Message Control Register for Receive MCTL_TX[%s] 0x8269 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[15] Message Control Register for Receive MCTL_TX[%s] 0x8A98 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[16] Message Control Register for Receive MCTL_TX[%s] 0x92C8 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[17] Message Control Register for Receive MCTL_TX[%s] 0x9AF9 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[18] Message Control Register for Receive MCTL_TX[%s] 0xA32B 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[19] Message Control Register for Receive MCTL_TX[%s] 0xAB5E 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[1] Message Control Register for Receive MCTL_TX[%s] 0x1861 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[20] Message Control Register for Receive MCTL_TX[%s] 0xB392 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[21] Message Control Register for Receive MCTL_TX[%s] 0xBBC7 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[22] Message Control Register for Receive MCTL_TX[%s] 0xC3FD 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[23] Message Control Register for Receive MCTL_TX[%s] 0xCC34 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[24] Message Control Register for Receive MCTL_TX[%s] 0xD46C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[25] Message Control Register for Receive MCTL_TX[%s] 0xDCA5 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[26] Message Control Register for Receive MCTL_TX[%s] 0xE4DF 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[27] Message Control Register for Receive MCTL_TX[%s] 0xED1A 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[28] Message Control Register for Receive MCTL_TX[%s] 0xF556 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[29] Message Control Register for Receive MCTL_TX[%s] 0xFD93 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[2] Message Control Register for Receive MCTL_TX[%s] 0x2083 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[30] Message Control Register for Receive MCTL_TX[%s] 0x105D1 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[31] Message Control Register for Receive MCTL_TX[%s] 0x10E10 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[3] Message Control Register for Receive MCTL_TX[%s] 0x28A6 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[4] Message Control Register for Receive MCTL_TX[%s] 0x30CA 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[5] Message Control Register for Receive MCTL_TX[%s] 0x38EF 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[6] Message Control Register for Receive MCTL_TX[%s] 0x4115 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[7] Message Control Register for Receive MCTL_TX[%s] 0x493C 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[8] Message Control Register for Receive MCTL_TX[%s] 0x5164 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_RX[9] Message Control Register for Receive MCTL_TX[%s] 0x598D 8 read-write n 0x0 0x0 INVALDATA Reception-in-Progress Status Flag (Receive mailbox setting enabled) 1 read-only 0 Message valid #0 1 Message being updated #1 MSGLOST Message Lost Flag(Receive mailbox setting enabled) 2 read-write 0 Message is not overwritten or overrun #0 1 Message is overwritten or overrun #1 NEWDATA Reception Complete Flag 0 read-write 0 No data has been received or 0 is written to the NEWDATA bit #0 1 A new message is being stored or has been stored to the mailbox #1 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX0 Message Control Register for Transmit 0x820 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX1 Message Control Register for Transmit 0x821 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX10 Message Control Register for Transmit 0x82A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX11 Message Control Register for Transmit 0x82B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX12 Message Control Register for Transmit 0x82C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX13 Message Control Register for Transmit 0x82D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX14 Message Control Register for Transmit 0x82E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX15 Message Control Register for Transmit 0x82F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX16 Message Control Register for Transmit 0x830 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX17 Message Control Register for Transmit 0x831 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX18 Message Control Register for Transmit 0x832 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX19 Message Control Register for Transmit 0x833 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX2 Message Control Register for Transmit 0x822 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX20 Message Control Register for Transmit 0x834 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX21 Message Control Register for Transmit 0x835 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX22 Message Control Register for Transmit 0x836 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX23 Message Control Register for Transmit 0x837 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX24 Message Control Register for Transmit 0x838 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX25 Message Control Register for Transmit 0x839 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX26 Message Control Register for Transmit 0x83A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX27 Message Control Register for Transmit 0x83B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX28 Message Control Register for Transmit 0x83C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX29 Message Control Register for Transmit 0x83D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX3 Message Control Register for Transmit 0x823 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX30 Message Control Register for Transmit 0x83E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX31 Message Control Register for Transmit 0x83F 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX4 Message Control Register for Transmit 0x824 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX5 Message Control Register for Transmit 0x825 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX6 Message Control Register for Transmit 0x826 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX7 Message Control Register for Transmit 0x827 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX8 Message Control Register for Transmit 0x828 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX9 Message Control Register for Transmit 0x829 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write Reserved This bit is read as 0. The write value should be 0. 3 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[0] Message Control Register for Transmit 0x1040 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[10] Message Control Register for Transmit 0x61B7 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[11] Message Control Register for Transmit 0x69E2 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[12] Message Control Register for Transmit 0x720E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[13] Message Control Register for Transmit 0x7A3B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[14] Message Control Register for Transmit 0x8269 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[15] Message Control Register for Transmit 0x8A98 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[16] Message Control Register for Transmit 0x92C8 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[17] Message Control Register for Transmit 0x9AF9 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[18] Message Control Register for Transmit 0xA32B 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[19] Message Control Register for Transmit 0xAB5E 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[1] Message Control Register for Transmit 0x1861 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[20] Message Control Register for Transmit 0xB392 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[21] Message Control Register for Transmit 0xBBC7 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[22] Message Control Register for Transmit 0xC3FD 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[23] Message Control Register for Transmit 0xCC34 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[24] Message Control Register for Transmit 0xD46C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[25] Message Control Register for Transmit 0xDCA5 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[26] Message Control Register for Transmit 0xE4DF 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[27] Message Control Register for Transmit 0xED1A 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[28] Message Control Register for Transmit 0xF556 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[29] Message Control Register for Transmit 0xFD93 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[2] Message Control Register for Transmit 0x2083 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[30] Message Control Register for Transmit 0x105D1 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[31] Message Control Register for Transmit 0x10E10 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[3] Message Control Register for Transmit 0x28A6 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[4] Message Control Register for Transmit 0x30CA 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[5] Message Control Register for Transmit 0x38EF 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[6] Message Control Register for Transmit 0x4115 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[7] Message Control Register for Transmit 0x493C 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[8] Message Control Register for Transmit 0x5164 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MCTL_TX[9] Message Control Register for Transmit 0x598D 8 read-write n 0x0 0x0 ONESHOT One-Shot Enable 4 read-write 0 One-shot reception or one-shot transmission disabled #0 1 One-shot reception or one-shot transmission enabled #1 RECREQ Receive Mailbox Request 6 read-write 0 Not configured for reception #0 1 Configured for reception #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SENTDATA Transmission Complete Flag 0 read-write 0 Transmission is not completed #0 1 Transmission is completed #1 TRMABT Transmission Abort Complete Flag (Transmit mailbox setting enabled) 2 read-write 0 Transmission has started, transmission abort failed because transmission is completed, or transmission abort is not requested #0 1 Transmission abort is completed #1 TRMACTIVE Transmission-in-Progress Status Flag (Transmit mailbox setting enabled) 1 read-only 0 Transmission is pending or transmission is not requested #0 1 From acceptance of transmission request to completion of transmission, or error/arbitration-lost #1 TRMREQ Transmit Mailbox Request 7 read-write 0 Not configured for transmission #0 1 Configured for transmission #1 MIER Mailbox Interrupt Enable Register 0x42C 32 read-write n 0x0 0x0 MB0 mailbox 0 Interrupt Enable 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB24 mailbox 24 Interrupt Enable 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB25 mailbox 25 Interrupt Enable 25 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB26 mailbox 26 Interrupt Enable 26 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB27 mailbox 27 Interrupt Enable 27 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB28 mailbox 28 Interrupt Enable 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB29 mailbox 29 Interrupt Enable 29 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB3 mailbox 3 Interrupt Enable 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB30 mailbox 30 Interrupt Enable 30 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB31 mailbox 31 Interrupt Enable 31 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MIER_FIFO Mailbox Interrupt Enable Register for FIFO Mailbox Mode MIER 0x42C 32 read-write n 0x0 0x0 MB0 mailbox 0 Interrupt Enable 0 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB1 mailbox 1 Interrupt Enable 1 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB10 mailbox 10 Interrupt Enable 10 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB11 mailbox 11 Interrupt Enable 11 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB12 mailbox 12 Interrupt Enable 12 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB13 mailbox 13 Interrupt Enable 13 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB14 mailbox 14 Interrupt Enable 14 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB15 mailbox 15 Interrupt Enable 15 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB16 mailbox 16 Interrupt Enable 16 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB17 mailbox 17 Interrupt Enable 17 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB18 mailbox 18 Interrupt Enable 18 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB19 mailbox 19 Interrupt Enable 19 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB2 mailbox 2 Interrupt Enable 2 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB20 mailbox 20 Interrupt Enable 20 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB21 mailbox 21 Interrupt Enable 21 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB22 mailbox 22 Interrupt Enable 22 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB23 mailbox 23 Interrupt Enable 23 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB24 Transmit FIFO Interrupt Enable 24 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB25 Transmit FIFO Interrupt Generation Timing Control 25 read-write 0 Every time transmission is completed #0 1 When the transmit FIFO becomes empty due to completion of transmission #1 MB28 Receive FIFO Interrupt Enable 28 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB29 Receive FIFO Interrupt Generation Timing Control 29 read-write 0 Every time reception is completed #0 1 When the receive FIFO becomes buffer warning by completion of reception #1 MB3 mailbox 3 Interrupt Enable 3 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB4 mailbox 4 Interrupt Enable 4 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB5 mailbox 5 Interrupt Enable 5 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB6 mailbox 6 Interrupt Enable 6 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB7 mailbox 7 Interrupt Enable 7 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB8 mailbox 8 Interrupt Enable 8 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 MB9 mailbox 9 Interrupt Enable 9 read-write 0 Interrupt disabled #0 1 Interrupt enabled #1 Reserved These bits are read as 00. The write value should be 00. 26 1 read-write MKIVLR Mask Invalid Register 0x428 32 read-write n 0x0 0x0 MB0 mailbox 0 Mask Invalid 0 read-write 0 Mask valid #0 1 Mask invalid #1 MB1 mailbox 1 Mask Invalid 1 read-write 0 Mask valid #0 1 Mask invalid #1 MB10 mailbox 10 Mask Invalid 10 read-write 0 Mask valid #0 1 Mask invalid #1 MB11 mailbox 11 Mask Invalid 11 read-write 0 Mask valid #0 1 Mask invalid #1 MB12 mailbox 12 Mask Invalid 12 read-write 0 Mask valid #0 1 Mask invalid #1 MB13 mailbox 13 Mask Invalid 13 read-write 0 Mask valid #0 1 Mask invalid #1 MB14 mailbox 14 Mask Invalid 14 read-write 0 Mask valid #0 1 Mask invalid #1 MB15 mailbox 15 Mask Invalid 15 read-write 0 Mask valid #0 1 Mask invalid #1 MB16 mailbox 16 Mask Invalid 16 read-write 0 Mask valid #0 1 Mask invalid #1 MB17 mailbox 17 Mask Invalid 17 read-write 0 Mask valid #0 1 Mask invalid #1 MB18 mailbox 18 Mask Invalid 18 read-write 0 Mask valid #0 1 Mask invalid #1 MB19 mailbox 19 Mask Invalid 19 read-write 0 Mask valid #0 1 Mask invalid #1 MB2 mailbox 2 Mask Invalid 2 read-write 0 Mask valid #0 1 Mask invalid #1 MB20 mailbox 20 Mask Invalid 20 read-write 0 Mask valid #0 1 Mask invalid #1 MB21 mailbox 21 Mask Invalid 21 read-write 0 Mask valid #0 1 Mask invalid #1 MB22 mailbox 22 Mask Invalid 22 read-write 0 Mask valid #0 1 Mask invalid #1 MB23 mailbox 23 Mask Invalid 23 read-write 0 Mask valid #0 1 Mask invalid #1 MB24 mailbox 24 Mask Invalid 24 read-write 0 Mask valid #0 1 Mask invalid #1 MB25 mailbox 25 Mask Invalid 25 read-write 0 Mask valid #0 1 Mask invalid #1 MB26 mailbox 26 Mask Invalid 26 read-write 0 Mask valid #0 1 Mask invalid #1 MB27 mailbox 27 Mask Invalid 27 read-write 0 Mask valid #0 1 Mask invalid #1 MB28 mailbox 28 Mask Invalid 28 read-write 0 Mask valid #0 1 Mask invalid #1 MB29 mailbox 29 Mask Invalid 29 read-write 0 Mask valid #0 1 Mask invalid #1 MB3 mailbox 3 Mask Invalid 3 read-write 0 Mask valid #0 1 Mask invalid #1 MB30 mailbox 30 Mask Invalid 30 read-write 0 Mask valid #0 1 Mask invalid #1 MB31 mailbox 31 Mask Invalid 31 read-write 0 Mask valid #0 1 Mask invalid #1 MB4 mailbox 4 Mask Invalid 4 read-write 0 Mask valid #0 1 Mask invalid #1 MB5 mailbox 5 Mask Invalid 5 read-write 0 Mask valid #0 1 Mask invalid #1 MB6 mailbox 6 Mask Invalid 6 read-write 0 Mask valid #0 1 Mask invalid #1 MB7 mailbox 7 Mask Invalid 7 read-write 0 Mask valid #0 1 Mask invalid #1 MB8 mailbox 8 Mask Invalid 8 read-write 0 Mask valid #0 1 Mask invalid #1 MB9 mailbox 9 Mask Invalid 9 read-write 0 Mask valid #0 1 Mask invalid #1 MKR0 Mask Register 0x400 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR1 Mask Register 0x404 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR2 Mask Register 0x408 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR3 Mask Register 0x40C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR4 Mask Register 0x410 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR5 Mask Register 0x414 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR6 Mask Register 0x418 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR7 Mask Register 0x41C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[0] Mask Register 0x800 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[1] Mask Register 0xC04 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[2] Mask Register 0x100C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[3] Mask Register 0x1418 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[4] Mask Register 0x1828 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[5] Mask Register 0x1C3C 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[6] Mask Register 0x2054 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MKR[7] Mask Register 0x2470 32 read-write n 0x0 0x0 EID Extended ID 0 17 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write SID Standard ID 18 10 read-write MSMR Mailbox Search Mode Register 0x853 8 read-write n 0x0 0x0 MBSM Mailbox Search Mode Select 0 1 read-write 00 Receive mailbox search mode #00 01 Transmit mailbox search mode #01 10 Message lost search mode #10 11 Channel search mode #11 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write MSSR Mailbox Search Status Register 0x852 8 read-only n 0x0 0x0 MBNST Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR. 0 4 read-only Reserved These bits are read as 00. 5 1 read-only SEST Search Result Status 7 read-only 0 Search result found #0 1 No search result #1 RECR Receive Error Count Register 0x84E 8 read-only n 0x0 0x0 RECR Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception. 0 7 read-only RFCR Receive FIFO Control Register 0x848 8 read-write n 0x0 0x0 RFE Receive FIFO Enable 0 read-write 0 Receive FIFO disabled #0 1 Receive FIFO enabled #1 RFEST Receive FIFO Empty Status Flag 7 read-only 0 Unread message in receive FIFO #0 1 No unread message in receive FIFO #1 RFFST Receive FIFO Full Status Flag 5 read-only 0 Receive FIFO is not full #0 1 Receive FIFO is full (4 unread messages) #1 RFMLF Receive FIFO Message Lost Flag 4 read-write 0 No receive FIFO message lost has occurred #0 1 Receive FIFO message lost has occurred #1 RFUST Receive FIFO Unread Message Number Status 1 2 read-only others Setting prohibited 000 No unread message #000 001 1 unread message #001 010 2 unread messages #010 011 3 unread messages #011 100 4 unread messages #100 RFWST Receive FIFO Buffer Warning Status Flag 6 read-only 0 Receive FIFO is not buffer warning #0 1 Receive FIFO is buffer warning (3 unread messages) #1 RFPCR Receive FIFO Pointer Control Register 0x849 8 write-only n 0x0 0x0 RFPCR The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR. 0 7 write-only STR Status Register 0x842 16 read-only n 0x0 0x0 BOST Bus-Off Status Flag 12 read-only 0 Not in bus-off state #0 1 In bus-off state #1 EPST Error-Passive Status Flag 11 read-only 0 Not in error-passive state #0 1 In error-passive state #1 EST Error Status Flag 7 read-only 0 No error occurred #0 1 Error occurred #1 FMLST FIFO Mailbox Message Lost Status Flag 5 read-only 0 RFMLF bit = 0 #0 1 RFMLF bit = 1 #1 HLTST CAN Halt Status Flag 9 read-only 0 Not in CAN halt mode #0 1 In CAN halt mode #1 NDST NEWDATA Status Flag 0 read-only 0 No mailbox with NEWDATA bit = 1 #0 1 Mailbox(es) with NEWDATA bit = 1 #1 NMLST Normal Mailbox Message Lost Status Flag 4 read-only 0 No mailbox with MSGLOST bit = 1 #0 1 Mailbox(es) with MSGLOST bit = 1 #1 RECST Receive Status Flag (receiver) 14 read-only 0 Bus idle or transmission in progress #0 1 Reception in progress #1 Reserved This bit is read as 0. 15 read-only RFST Receive FIFO Status Flag 2 read-only 0 No message in receive FIFO (empty) #0 1 Message in receive FIFO #1 RSTST CAN Reset Status Flag 8 read-only 0 Not in CAN reset mode #0 1 In CAN reset mode #1 SDST SENTDATA Status Flag 1 read-only 0 No mailbox with SENTDATA bit = 1 #0 1 Mailbox(es) with SENTDATA bit = 1 #1 SLPST CAN Sleep Status Flag 10 read-only 0 Not in CAN sleep mode #0 1 In CAN sleep mode #1 TABST Transmission Abort Status Flag 6 read-only 0 No mailbox with TRMABT bit = 1 #0 1 Mailbox(es) with TRMABT bit = 1 #1 TFST Transmit FIFO Status Flag 3 read-only 0 Transmit FIFO is full #0 1 Transmit FIFO is not full #1 TRMST Transmit Status Flag (transmitter) 13 read-only 0 Bus idle or reception in progress #0 1 Transmission in progress or in bus-off state #1 TCR Test Control Register 0x858 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write TSTE CAN Test Mode Enable 0 read-write 0 CAN test mode disabled #0 1 CAN test mode enabled #1 TSTM CAN Test Mode Select 1 1 read-write 00 Other than CAN test mode #00 01 Listen-only mode #01 10 Self-test mode 0 (external loopback) #10 11 Self-test mode 1 (internal loopback) #11 TECR Transmit Error Count Register 0x84F 8 read-only n 0x0 0x0 TECR Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission. 0 7 read-only TFCR Transmit FIFO Control Register 0x84A 8 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 4 1 read-write TFE Transmit FIFO Enable 0 read-write 0 Transmit FIFO disabled #0 1 Transmit FIFO enabled #1 TFEST Transmit FIFO Empty Status 7 read-only 0 Unsent message in transmit FIFO #0 1 No unsent message in transmit FIFO #1 TFFST Transmit FIFO Full Status 6 read-only 0 Transmit FIFO is not full #0 1 Transmit FIFO is full (4 unsent messages) #1 TFUST Transmit FIFO Unsent Message Number Status 1 2 read-only others Setting prohibited 000 No unsent message #000 001 1 unsent message #001 010 2 unsent messages #010 011 3 unsent messages #011 100 4 unsent messages #100 TFPCR Transmit FIFO Pointer Control Register 0x84B 8 write-only n 0x0 0x0 TFPCR The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR. 0 7 write-only TSR Time Stamp Register 0x854 16 read-only n 0x0 0x0 TSR Free-running counter value for the time stamp function 0 15 read-only CRC CRC Calculator CRC 0x0 0x0 0x2 registers n 0x4 0x1 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0x8 0x4 registers n 0x8 0x2 registers n 0xC 0x2 registers n CRCCR0 CRC Control Register0 0x0 8 read-write n 0x0 0x0 DORCIR CRCDOR Register Clear 7 write-only 0 No effect. #0 1 Clears the CRCDOR register. #1 GPS CRC Generating Polynomial Switching 0 2 read-write 000 No calculation is executed. #000 001 8-bit CRC-8 (X8 + X2 + X + 1) #001 010 16-bit CRC-16 (X16 + X15 + X2 + 1) #010 011 16-bit CRC-CCITT (X16 + X12 + X5 + 1) #011 100 32-bit CRC-32 (X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1) #100 101 32-bit CRC-32C (X32+X28+X27+X26+ X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1) #101 LMS CRC Calculation Switching 6 read-write 0 Generates CRC for LSB first communication. #0 1 Generates CRC for MSB first communication. #1 Reserved These bits are read as 000. The write value should be 000. 3 2 read-write CRCCR1 CRC Control Register1 0x1 8 read-write n 0x0 0x0 CRCSEN Snoop enable bit 7 read-write 0 Disabled #0 1 Enabled #1 CRCSWR Snoop-on-write/read switch bit 6 read-write 0 Snoop-on-read #0 1 Snoop-on-write #1 Reserved These bits are read as 000000. The write value should be 000000. 0 5 read-write CRCDIR CRC Data Input Register 0x4 32 read-write n 0x0 0x0 CRCDIR Calculation input Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDIR_BY CRC Data Input Register (byte access) CRCDIR 0x4 8 read-write n 0x0 0x0 CRCDIR_BY Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT ) 0 7 read-write CRCDOR CRC Data Output Register 0x8 32 read-write n 0x0 0x0 CRCDOR Calculation output Data (Case of CRC-32, CRC-32C ) 0 31 read-write CRCDOR_BY CRC Data Output Register(byte access) CRCDOR 0x8 8 read-write n 0x0 0x0 CRCDOR_BY Calculation output Data (Case of CRC-8 ) 0 7 read-write CRCDOR_HA CRC Data Output Register (halfword access) CRCDOR 0x8 16 read-write n 0x0 0x0 CRCDOR_HA Calculation output Data (Case of CRC-16 or CRC-CCITT ) 0 15 read-write CRCSAR Snoop Address Register 0xC 16 read-write n 0x0 0x0 CRCSA snoop address bitSet the I/O register address to snoop 0 13 read-write 0x0003 SCI0.TDR 0x0003 0x0005 SCI0.RDR 0x0005 0x0023 SCI1.TDR 0x0023 0x0025 SCI1.RDR 0x0025 0x0043 SCI2.TDR 0x0043 0x0045 SCI2.RDR 0x0045 0x0063 SCI3.TDR 0x0063 0x0065 SCI3.RDR 0x0065 0x0083 SCI4.TDR 0x0083 0x0085 SCI4.RDR 0x0085 0x0123 SCI9.TDR 0x0123 0x0125 SCI9.RDR 0x0125 Reserved These bits are read as 00. The write value should be 00. 14 1 read-write CTSU Capacitive Touch Sensing Unit CTSU 0x0 0x0 0x1E registers n CTSUCHAC0 CTSU Channel Enable Control Register 0 0x6 8 read-write n 0x0 0x0 CTSUCHAC0 CTSU Channel Enable Control 0.0: Not measurement target1: Measurement targetNote: CTSUCHAC0[0] corresponds to TS00 and CTSUCHAC0[7] corresponds to TS07. but the write value of CTSUCHAC0[2] should be 0. 0 7 read-write CTSUCHAC1 CTSU Channel Enable Control Register 1 0x7 8 read-write n 0x0 0x0 CTSUCHAC1 CTSU Channel Enable Control 1.0: Not measurement target1: Measurement targetNote: CTSUCHAC1[0] corresponds to TS08 and CTSUCHAC1[7] corresponds to TS15. 0 7 read-write CTSUCHAC2 CTSU Channel Enable Control Register 2 0x8 8 read-write n 0x0 0x0 CTSUCHAC2 CTSU Channel Enable Control 2.0: Not measurement target1: Measurement targetNote: CTSUCHAC2[0] corresponds to TS16 and CTSUCHAC2[7] corresponds to TS23. 0 7 read-write CTSUCHAC3 CTSU Channel Enable Control Register 3 0x9 8 read-write n 0x0 0x0 CTSUCHAC3 CTSU Channel Enable Control 3.0: Not measurement target1: Measurement targetNote: CTSUCHAC3[0] corresponds to TS24 and CTSUCHAC3[7] corresponds to TS31. 0 7 read-write CTSUCHAC4 CTSU Channel Enable Control Register 4 0xA 8 read-write n 0x0 0x0 CTSUCHAC4 CTSU Channel Enable Control 4.0: Not measurement target1: Measurement targetNote: CTSUCHAC4[0] corresponds to TS32 and CTSUCHAC4[3] corresponds to TS35. but the write value of CTSUCHAC0[4],CTSUCHAC4[5],CTSUCHAC4[6],CTSUCHAC4[7] should be 0. 0 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write CTSUCHTRC0 CTSU Channel Transmit/Receive Control Register 0 0xB 8 read-write n 0x0 0x0 CTSUCHTRC0 CTSU Channel Transmit/Receive Control 0 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC1 CTSU Channel Transmit/Receive Control Register 1 0xC 8 read-write n 0x0 0x0 CTSUCHTRC1 CTSU Channel Transmit/Receive Control 1 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC2 CTSU Channel Transmit/Receive Control Register 3 0xD 8 read-write n 0x0 0x0 CTSUCHTRC2 CTSU Channel Transmit/Receive Control 2 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC3 CTSU Channel Transmit/Receive Control Register 3 0xE 8 read-write n 0x0 0x0 CTSUCHTRC3 CTSU Channel Transmit/Receive Control 3 0 7 read-write 0 Reception #0 1 Transmission #1 CTSUCHTRC4 CTSU Channel Transmit/Receive Control Register 4 0xF 8 read-write n 0x0 0x0 CTSUCHAC4 CTSU Channel Transmit/Receive Control 4 0 3 read-write 0 Reception #0 1 Transmission #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write CTSUCR0 CTSU Control Register 0 0x0 8 read-write n 0x0 0x0 CTSUCAP CTSU Measurement Operation Start Trigger Select 1 read-write 0 Software trigger. #0 1 External trigger. #1 CTSUINIT CTSU Control Block Initialization 4 read-write 0 Writing a 0 has no effect, this bit is read as 0. #0 1 initializes the CTSU control block and registers. #1 CTSUIOC CTSU Transmit Pin Control 3 read-write 0 Low-level output from transmit channel non-measurement pin. #0 1 High-level output from transmit channel non-measurement pin. #1 CTSUSNZ CTSU Wait State Power-Saving Enable 2 read-write 0 Power-saving function during wait state is disabled. #0 1 Power-saving function during wait state is enabled. #1 CTSUSTRT CTSU Measurement Operation Start 0 read-write 0 Measurement operation stops. #0 1 Measurement operation starts. #1 CTSUCR1 CTSU Control Register 1 0x1 8 read-write n 0x0 0x0 CTSUATUNE0 CTSU Power Supply Operating Mode Setting 2 read-write 0 Normal operating mode #0 1 Low-voltage operating mode #1 CTSUATUNE1 CTSU Power Supply Capacity Adjustment 3 read-write 0 Normal output #0 1 High-current output #1 CTSUCLK CTSU Operating Clock Select 4 1 read-write 00 PCLK #00 01 PCLK/2 (PCLK divided by 2) #01 10 PCLK/2 (PCLK divided by 4) #10 11 Setting prohibited #11 CTSUCSW CTSU LPF Capacitance Charging Control 1 read-write 0 Turned off capacitance switch #0 1 Turned on capacitance switch #1 CTSUMD CTSU Measurement Mode Select 6 1 read-write 00 Self-capacitance single scan mode #00 01 Self-capacitance multi-scan mode #01 10 Mutual capacitance simple scan mode #10 11 Mutual capacitance full scan mode #11 CTSUPON CTSU Power Supply Enable 0 read-write 0 Powered off the CTSU #0 1 Powered on the CTSU #1 CTSUDCLKC CTSU High-Pass Noise Reduction Control Register 0x10 8 read-write n 0x0 0x0 CTSUSSCNT CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b. 4 1 read-write CTSUSSMOD CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b. 0 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CTSUERRS CTSU Error Status Register 0x1C 16 read-only n 0x0 0x0 CTSUICOMP TSCAP Voltage Error Monitor 15 read-only 0 Normal TSCAP voltage #0 1 Abnormal TSCAP voltage #1 Reserved These bits are read as 000000000000000. 0 14 read-only CTSUMCH0 CTSU Measurement Channel Register 0 0x4 8 read-write n 0x0 0x0 CTSUMCH0 CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan mode, the measurement is stopped. 0 5 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CTSUMCH1 CTSU Measurement Channel Register 1 0x5 8 read-write n 0x0 0x0 CTSUMCH1 CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111, the measurement is stopped. 0 5 read-only Reserved These bits are read as 00. The write value should be 00. 6 1 read-write CTSURC CTSU Reference Counter 0x1A 16 read-only n 0x0 0x0 CTSURC CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs. 0 15 read-only CTSUSC CTSU Sensor Counter 0x18 16 read-only n 0x0 0x0 CTSUSC CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs. 0 15 read-only CTSUSDPRS CTSU Synchronous Noise Reduction Setting Register 0x2 8 read-write n 0x0 0x0 CTSUPRMODE CTSU Base Period and Pulse Count Setting 4 1 read-write 00 510 pulses #00 01 126 pulses #01 10 62 pulses (recommended setting value) #10 11 Setting prohibited #11 CTSUPRRATIO CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b) 0 3 read-write CTSUSOFF CTSU High-Pass Noise Reduction Function Off Setting 6 read-write 0 High-pass noise reduction function turned on #0 1 High-pass noise reduction function turned off #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write CTSUSO0 CTSU Sensor Offset Register 0 0x14 16 read-write n 0x0 0x0 CTSUSNUM CTSU Measurement Count Setting 10 5 read-write CTSUSO CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 ) 0 9 read-write CTSUSO1 CTSU Sensor Offset Register 1 0x16 16 read-write n 0x0 0x0 CTSUICOG CTSU ICO Gain Adjustment 13 1 read-write 00 100 percent gain #00 01 66 percent gain #01 10 50 percent gain #10 11 40 percent gain #11 CTSURICOA CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 ) 0 7 read-write CTSUSDPA CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2 8 4 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write CTSUSSC CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register 0x12 16 read-write n 0x0 0x0 CTSUSSDIV CTSU Spectrum Diffusion Frequency Division Setting 8 3 read-write 0000 4.00 <= fb #0000 0001 2.00 <= fb < 4.00 #0001 0010 1.33 <= fb < 2.00 #0010 0011 1.00 <= fb < 1.33 #0011 0100 0.80 <= fb < 1.00 #0100 0101 0.67 <= fb < 0.80 #0101 0110 0.57 <= fb < 0.67 #0110 0111 0.50 <= fb < 0.57 #0111 1000 0.44 <= fb < 0.50 #1000 1001 0.40 <= fb < 0.44 #1001 1010 0.36 <= fb < 0.40 #1010 1011 0.33 <= fb < 0.36 #1011 1100 0.31 <= fb < 0.33 #1100 1101 0.29 <= fb < 0.31 #1101 1110 0.27 <= fb < 0.29 #1110 1111 fb < 0.27 #1111 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write CTSUSST CTSU Sensor Stabilization Wait Control Register 0x3 8 read-write n 0x0 0x0 CTSUSST CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b. 0 7 read-write CTSUST CTSU Status Register 0x11 8 read-write n 0x0 0x0 CTSUDTSR CTSU Data Transfer Status Flag 4 read-only 0 Measurement result has been read #0 1 Measurement result has not been read #1 CTSUPS CTSU Mutual Capacitance Status Flag 7 read-only 0 First measurement #0 1 Second measurement #1 CTSUROVF CTSU Reference Counter Overflow Flag 6 read-write 0 No overflow #0 1 An overflow #1 CTSUSOVF CTSU Sensor Counter Overflow Flag 5 read-write 0 No overflow #0 1 An overflow #1 CTSUSTC CTSU Measurement Status Counter 0 2 read-write 000 Status 0 #000 001 Status 1 #001 010 Status 2 #010 011 Status 3 #011 100 Status 4 #100 101 Status 5 #101 Reserved This bit is read as 0. The write value should be 0. 3 read-write DAC12 12-bit D/A converter DAC12 0x0 0x0 0x2 registers n 0x4 0x4 registers n DAADSCR D/A-A/D Synchronous Start Control Register 0x6 8 read-write n 0x0 0x0 DAADST D/A-A/D Synchronous Conversion 7 read-write 0 D/A converter operation does not synchronize with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is disabled). #0 1 D/A converter operation synchronizes with A/D converter operation (unit 1) (countermeasure against interference between D/A and A/D conversions is enabled). #1 DACR D/A Control Register 0x4 8 read-write n 0x0 0x0 DAOE0 D/A Output Enable 0 6 read-write 0 Analog output of channel 0 (DA0) is disabled. #0 1 D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write DADPR DADR0 Format Select Register 0x5 8 read-write n 0x0 0x0 DPSEL DADRm Format Select 7 read-write 0 Right justified format. #0 1 Left justified format. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write DADR0 D/A Data Register 0 0x0 16 read-write n 0x0 0x0 DADR D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1, the low-order 4 bits are fixed to 0: left justified format. 0 15 read-write DAVREFCR D/A VREF Control Register 0x7 8 read-write n 0x0 0x0 REF D/A Reference Voltage Select 0 2 read-write 000 Not selected #000 001 AVCC0/AVSS0 #001 011 Internal reference voltage/AVSS0 #011 110 VREFH/VREFL #110 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write DAC8 8-bit D/A converter DAC8 0x0 0x0 0x2 registers n 0x3 0x1 registers n DACS0 D/A Conversion Value Setting Register %s 0x0 8 read-write n 0x0 0x0 DACS DACS D/A conversion store data note: When 8-bit D/A Converter output is selected as the reference input for the ACMPLP in the COMPSEL1 register, and ACMPLP operation is enabled (COMPMDR.CnENB = 1), changing the DACS[7:0] bits for the channel in use isprohibited. 0 7 read-write DACS1 D/A Conversion Value Setting Register %s 0x1 8 read-write n 0x0 0x0 DACS DACS D/A conversion store data note: When 8-bit D/A Converter output is selected as the reference input for the ACMPLP in the COMPSEL1 register, and ACMPLP operation is enabled (COMPMDR.CnENB = 1), changing the DACS[7:0] bits for the channel in use isprohibited. 0 7 read-write DAM D/A Converter Mode Register 0x3 8 read-write n 0x0 0x0 DACE0 D/A Operation Enable 0 4 read-write 0 D/A conversion disabled for channel 0 #0 1 D/A conversion enabled for channel 0. #1 DACE1 D/A Operation Enable 1 5 read-write 0 D/A conversion disabled for channel 1 #0 1 D/A conversion enabled for channel 1 #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write DBG Debug Function DBG 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x20 0x4 registers n DBGSTOPCR Debug Stop Control Register 0x10 32 read-write n 0x0 0x0 DBGSTOP_IWDT Mask bit for IWDT reset/interrupt 0 read-write 0 Mask IWDT reset/interrupt #0 1 Enable IWDT reset #1 DBGSTOP_LVD b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask) 16 2 read-write DBGSTOP_RECCR Mask bit for RAM ECC error reset/interrupt 25 read-write 0 Enable RAM ECC error reset/interrupt #0 1 Mask RAM ECC error reset/interrupt #1 DBGSTOP_RPER Mask bit for RAM parity error reset/interrupt 24 read-write 0 Enable RAM parity error reset/interrupt #0 1 Mask RAM parity error reset/interrupt #1 DBGSTOP_WDT Mask bit for WDT reset/interrupt 1 read-write 0 Mask WDT reset/interrupt #0 1 Enable WDT reset #1 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write DBGSTR Debug Status Register 0x0 32 read-only n 0x0 0x0 CDBGPWRUPACK Debug power-up acknowledge 29 read-only 0 Debug power-up request is not acknowledged #0 1 Debug power-up request is acknowledged #1 CDBGPWRUPREQ Debug power-up request 28 read-only 0 OCD is not requesting debug power-up #0 1 OCD is requesting debug power-up #1 Reserved These bits are read as 00. 30 1 read-only Reserved These bits are read as 00. 30 1 read-only TRACECTR Trace Control Register 0x20 32 read-write n 0x0 0x0 ENETBFULL Enable bit for halt request by ETB full 31 read-write 0 ETB full does not cause CPU halt #0 1 ETB full cause CPU halt #1 Reserved These bits are read as 0000000000000000000000000000000. The write value should be 0000000000000000000000000000000. 0 30 read-write DMA DMAC Module Activation DMA 0x0 0x0 0x1 registers n DMAST DMAC Module Activation Register 0x0 8 read-write n 0x0 0x0 DMST DMAC Operation Enable 0 read-write 0 Disabled. #0 1 Enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DMAC0 Direct memory access controller 0 DMAC0 0x0 0x0 0xE registers n 0x10 0x2 registers n 0x13 0x3 registers n 0x18 0x7 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved This bit is read as 0. The write value should be 0. 13 read-write SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write modify 0 Disabled #0 1 Enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write Reserved These bits are read as 000000. The write value should be 000000. 26 5 read-write DMCRB DMA Block Transfer Count Register 0xC 16 read-write n 0x0 0x0 DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write others DMCRB blocks 0000 65,536 blocks #0000 DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDAR Specifies the transfer destination start address. 0 31 read-write DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disabled #0 1 Enabled #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SWREQ DMA Software Start 0 read-write modify 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSAR Specifies the transfer source start address. 0 31 read-write DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMA Active Flag 7 read-only 0 DMAC operation suspended #0 1 DMAC operating. #1 DTIF Transfer End Interrupt Flag 4 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 ESIF Transfer Escape End Interrupt Flag 0 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts*1 from peripheral modules or external interrupt input pins #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 DMAC1 Direct memory access controller 1 DMAC0 0x0 0x0 0xE registers n 0x10 0x2 registers n 0x13 0x3 registers n 0x18 0x7 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved This bit is read as 0. The write value should be 0. 13 read-write SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write modify 0 Disabled #0 1 Enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write Reserved These bits are read as 000000. The write value should be 000000. 26 5 read-write DMCRB DMA Block Transfer Count Register 0xC 16 read-write n 0x0 0x0 DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write others DMCRB blocks 0000 65,536 blocks #0000 DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDAR Specifies the transfer destination start address. 0 31 read-write DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disabled #0 1 Enabled #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SWREQ DMA Software Start 0 read-write modify 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSAR Specifies the transfer source start address. 0 31 read-write DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMA Active Flag 7 read-only 0 DMAC operation suspended #0 1 DMAC operating. #1 DTIF Transfer End Interrupt Flag 4 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 ESIF Transfer Escape End Interrupt Flag 0 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts*1 from peripheral modules or external interrupt input pins #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 DMAC2 Direct memory access controller 2 DMAC0 0x0 0x0 0xE registers n 0x10 0x2 registers n 0x13 0x3 registers n 0x18 0x7 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved This bit is read as 0. The write value should be 0. 13 read-write SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write modify 0 Disabled #0 1 Enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write Reserved These bits are read as 000000. The write value should be 000000. 26 5 read-write DMCRB DMA Block Transfer Count Register 0xC 16 read-write n 0x0 0x0 DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write others DMCRB blocks 0000 65,536 blocks #0000 DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDAR Specifies the transfer destination start address. 0 31 read-write DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disabled #0 1 Enabled #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SWREQ DMA Software Start 0 read-write modify 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSAR Specifies the transfer source start address. 0 31 read-write DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMA Active Flag 7 read-only 0 DMAC operation suspended #0 1 DMAC operating. #1 DTIF Transfer End Interrupt Flag 4 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 ESIF Transfer Escape End Interrupt Flag 0 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts*1 from peripheral modules or external interrupt input pins #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 DMAC3 Direct memory access controller 3 DMAC0 0x0 0x0 0xE registers n 0x10 0x2 registers n 0x13 0x3 registers n 0x18 0x7 registers n DMAMD DMA Address Mode Register 0x14 16 read-write n 0x0 0x0 DARA Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings. 0 4 read-write DM Destination Address Update Mode 6 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved This bit is read as 0. The write value should be 0. 13 read-write SARA Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings. 8 4 read-write SM Source Address Update Mode 14 1 read-write 00 Fixed address #00 01 Offset addition #01 10 Incremented address #10 11 Decremented address. #11 DMCNT DMA Transfer Enable Register 0x1C 8 read-write n 0x0 0x0 DTE DMA Transfer Enable 0 read-write modify 0 Disabled #0 1 Enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DMCRA DMA Transfer Count Register 0x8 32 read-write n 0x0 0x0 DMCRAH Upper bits of transfer count 16 9 read-write DMCRAL Lower bits of transfer count 0 15 read-write Reserved These bits are read as 000000. The write value should be 000000. 26 5 read-write DMCRB DMA Block Transfer Count Register 0xC 16 read-write n 0x0 0x0 DMCRB Specifies the number of block transfer operations or repeat transfer operations. 0 15 read-write others DMCRB blocks 0000 65,536 blocks #0000 DMDAR DMA Destination Address Register 0x4 32 read-write n 0x0 0x0 DMDAR Specifies the transfer destination start address. 0 31 read-write DMINT DMA Interrupt Setting Register 0x13 8 read-write n 0x0 0x0 DARIE Destination Address Extended Repeat Area Overflow Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled #1 DTIE Transfer End Interrupt Enable 4 read-write 0 Disabled #0 1 Enabled #1 ESIE Transfer Escape End Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write RPTIE Repeat Size End Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled #1 SARIE Source Address Extended Repeat Area Overflow Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled #1 DMOFR DMA Offset Register 0x18 32 read-write n 0x0 0x0 DMOFR Specifies the offset when offset addition is selected as the address update mode for transfer source or destination. 0 31 read-write DMREQ DMA Software Start Register 0x1D 8 read-write n 0x0 0x0 CLRS DMA Software Start Bit Auto Clear Select 4 read-write 0 SWREQ bit is cleared after DMA transfer is started by software. #0 1 SWREQ bit is not cleared after DMA transfer is started by software. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SWREQ DMA Software Start 0 read-write modify 0 DMA transfer is not requested. #0 1 DMA transfer is requested. #1 DMSAR DMA Source Address Register 0x0 32 read-write n 0x0 0x0 DMSAR Specifies the transfer source start address. 0 31 read-write DMSTS DMA Status Register 0x1E 8 read-write n 0x0 0x0 ACT DMA Active Flag 7 read-only 0 DMAC operation suspended #0 1 DMAC operating. #1 DTIF Transfer End Interrupt Flag 4 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 ESIF Transfer Escape End Interrupt Flag 0 read-write zeroToClear modify 0 No interrupt #0 1 Interrupt occurred. #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write DMTMD DMA Transfer Mode Register 0x10 16 read-write n 0x0 0x0 DCTG Transfer Request Source Select 0 1 read-write 00 Software #00 01 Interrupts*1 from peripheral modules or external interrupt input pins #01 10 Setting prohibited #10 11 Setting prohibited #11 DTS Repeat Area Select 12 1 read-write 00 The destination is specified as the repeat area or block area. #00 01 The source is specified as the repeat area or block area. #01 10 The repeat area or block area is not specified. #10 11 Setting prohibited #11 MD Transfer Mode Select 14 1 read-write 00 Normal transfer #00 01 Repeat transfer #01 10 Block transfer #10 11 Setting prohibited #11 Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write SZ Transfer Data Size Select 8 1 read-write 00 8 bits #00 01 16 bits #01 10 32 bits #10 11 Setting prohibited #11 DOC Data Operation Circuit DOC 0x0 0x0 0x1 registers n 0x2 0x4 registers n DOCR DOC Control Register 0x0 8 read-write n 0x0 0x0 DCSEL Detection Condition Select 2 read-write 0 DOPCF is set when data mismatch is detected. #0 1 DOPCF is set when data match is detected. #1 DOPCF Data Operation Circuit FlagIndicates the result of an operation. 5 read-only DOPCFCL DOPCF Clear 6 read-write 0 Maintains the DOPCF flag state. #0 1 Clears the DOPCF flag. #1 OMS Operating Mode Select 0 1 read-write 00 Data comparison mode #00 01 Data addition mode #01 10 Data subtraction mode #10 11 Setting prohibited #11 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write DODIR DOC Data Input Register 0x2 16 read-write n 0x0 0x0 DODIR 16-bit read-write register in which 16-bit data for use in the operations are stored. 0 15 read-write DODSR DOC Data Setting Register 0x4 16 read-write n 0x0 0x0 DODSR This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes. 0 15 read-write DTC Data Transfer Controller DTC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0xC 0x1 registers n 0xE 0x2 registers n DTCCR DTC Control Register 0x0 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved This bit is read as 1. The write value should be 1. 3 read-write Reserved This bit is read as 1. The write value should be 1. 3 read-write RRS DTC Transfer Information Read Skip Enable. 4 read-write 0 Do not skip transfer information read #0 1 Skip transfer information read when vector numbers match #1 DTCST DTC Module Start Register 0xC 8 read-write n 0x0 0x0 DTCST DTC Module Start 0 read-write 0 DTC module stop #0 1 DTC module start #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write DTCSTS DTC Status Register 0xE 16 read-only n 0x0 0x0 ACT DTC Active Flag 15 read-only 0 DTC transfer operation is not in progress. #0 1 DTC transfer operation is in progress. #1 Reserved These bits are read as 0000000. 8 6 read-only VECN DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1) 0 7 read-only DTCVBR DTC Vector Base Register 0x4 32 read-write n 0x0 0x0 DTCVBR DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0. 0 31 read-write ELC Event Link Controller ELC 0x0 0x0 0x1 registers n 0x10 0x28 registers n 0x2 0x4 registers n 0x40 0x2 registers n 0x48 0x14 registers n ELCR Event Link Controller Register 0x0 8 read-write n 0x0 0x0 ELCON All Event Link Enable 7 read-write 0 ELC function is disabled. #0 1 ELC function is enabled. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write ELSEGR0 Event Link Software Event Generation Register %s 0x4 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 1 4 read-write SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 read-write 0 Write to SEG bit is disabled. #0 1 Write to SEG bit is enabled. #1 WI ELSEGR Register Write Disable 7 write-only 0 Write to ELSEGR register is enabled. #0 1 Write to ELSEGR register is disabled. #1 ELSEGR1 Event Link Software Event Generation Register %s 0x8 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 1 4 read-write SEG Software Event Generation 0 write-only 0 Normal operation #0 1 Software event is generated. #1 WE SEG Bit Write Enable 6 read-write 0 Write to SEG bit is disabled. #0 1 Write to SEG bit is enabled. #1 WI ELSEGR Register Write Disable 7 write-only 0 Write to ELSEGR register is enabled. #0 1 Write to ELSEGR register is disabled. #1 ELSR0 Event Link Setting Register %s 0x20 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR1 Event Link Setting Register %s 0x34 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR12 Event Link Setting Register 12 0x40 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR14 Event Link Setting Register %s 0x90 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR15 Event Link Setting Register %s 0xDC 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR16 Event Link Setting Register %s 0x12C 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR17 Event Link Setting Register %s 0x180 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR18 Event Link Setting Register %s 0x1D8 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR2 Event Link Setting Register %s 0x4C 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR3 Event Link Setting Register %s 0x68 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR4 Event Link Setting Register %s 0x88 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR5 Event Link Setting Register %s 0xAC 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR6 Event Link Setting Register %s 0xD4 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR7 Event Link Setting Register %s 0x100 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR8 Event Link Setting Register %s 0x130 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write ELSR9 Event Link Setting Register %s 0x164 16 read-write n 0x0 0x0 ELS Event Link Select 0 7 read-write 0x00 Event output to the corresponding peripheral module is disabled. 0x00 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write FCACHE Flash Cache FCACHE 0x0 0x100 0x2 registers n 0x104 0x2 registers n 0x11C 0x1 registers n FCACHEE Flash Cache Enable Register 0x100 16 read-write n 0x0 0x0 FCACHEEN FCACHE Enable 0 read-write 0 FCACHE is disabled #0 1 FCACHE is enabled #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write FCACHEIV Flash Cache Invalidate Register 0x104 16 read-write n 0x0 0x0 FCACHEIV FCACHE Invalidation 0 read-write oneToSet modify 0 (Read)not in progress / (Write) no effect. #0 1 (Read)in progress /(Write) Starting Cache Invalidation #1 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write FLWT Flash Wait Cycle Register 0x11C 8 read-write n 0x0 0x0 FLWT These bits represent the ratio of the CPU clock period to the Flash memory access time. 0 2 read-write others Setting prohibited 000 zero wait #000 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write GPT164 General PWM Timer 4 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT165 General PWM Timer 5 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT166 General PWM Timer 6 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT167 General PWM Timer 7 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT168 General PWM Timer 8 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT169 General PWM Timer 9 (16-bit) GPT164 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELC_GPTH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELC_GPTH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELC_GPTH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELC_GPTH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELC_GPTH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELC_GPTH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELC_GPTH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT320 General PWM Timer 0 (32-bit) GPT320 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELCH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELCH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELCH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELCH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELCH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELCH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELCH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT321 General PWM Timer 1 (32-bit) GPT320 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELCH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELCH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELCH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELCH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELCH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELCH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELCH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT322 General PWM Timer 2 (32-bit) GPT320 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELCH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELCH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELCH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELCH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELCH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELCH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELCH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT323 General PWM Timer 3 (32-bit) GPT320 0x0 0x0 0x74 registers n 0x74 0x4 registers n 0x78 0x4 registers n 0x7C 0x4 registers n 0x80 0x4 registers n 0x84 0x20 registers n GTBER General PWM Timer Buffer Enable Register 0x40 32 read-write n 0x0 0x0 BD BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable 0 1 read-write 0 Buffer operation is enabled #0 1 Buffer operation is disabled #1 CCRA GTCCRA Buffer Operation 16 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRA <--> GTCCRC) #01 10 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #10 11 Double buffer operation (GTCCRA <--> GTCCRC <--> GTCCRD) #11 CCRB GTCCRB Buffer Operation 18 1 read-write 00 Buffer operation is not performed #00 01 Single buffer operation (GTCCRB <--> GTCCRE) #01 10 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #10 11 Double buffer operation (GTCCRB <--> GTCCRE <--> GTCCRF) #11 CCRSWT GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0. 22 write-only 0 no effect #0 1 Forcibly performs buffer transfer of GTCCRA and GTCCRB. This bit automatically returns to 0 after the writing of 1. #1 PR GTPR Buffer Operation 20 1 read-write others Setting prohibited 00 Buffer operation is not performed #00 01 Single buffer operation (GTPBR --> GTPR) #01 GTCCRA General PWM Timer Compare Capture Register A 0x4C 32 read-write n 0x0 0x0 GTCCRA Compare Capture Register A 0 31 read-write GTCCRB General PWM Timer Compare Capture Register B 0x50 32 read-write n 0x0 0x0 GTCCRB Compare Capture Register B 0 31 read-write GTCCRC General PWM Timer Compare Capture Register C 0x54 32 read-write n 0x0 0x0 GTCCRC Compare Capture Register C 0 31 read-write GTCCRD General PWM Timer Compare Capture Register D 0x5C 32 read-write n 0x0 0x0 GTCCRD Compare Capture Register D 0 31 read-write GTCCRE General PWM Timer Compare Capture Register E 0x58 32 read-write n 0x0 0x0 GTCCRE Compare Capture Register E 0 31 read-write GTCCRF General PWM Timer Compare Capture Register F 0x60 32 read-write n 0x0 0x0 GTCCRF Compare Capture Register F 0 31 read-write GTCLR General PWM Timer Software Clear Register 0xC 32 write-only n 0x0 0x0 CCLR0 Channel 0 GTCNT Count Clear 0 write-only 0 No effect #0 1 GPT320.GTCNT counter clears #1 CCLR1 Channel 1 GTCNT Count Clear 1 write-only 0 No effect #0 1 GPT321.GTCNT counter clears #1 CCLR2 Channel 2 GTCNT Count Clear 2 write-only 0 No effect #0 1 GPT322.GTCNT counter clears #1 CCLR3 Channel 3 GTCNT Count Clear 3 write-only 0 No effect #0 1 GPT323.GTCNT counter clears #1 CCLR4 Channel 4 GTCNT Count Clear 4 write-only 0 No effect #0 1 GPT164.GTCNT counter clears #1 CCLR5 Channel 5 GTCNT Count Clear 5 write-only 0 No effect #0 1 GPT165.GTCNT counter clears #1 CCLR6 Channel 6 GTCNT Count Clear 6 write-only 0 No effect #0 1 GPT166.GTCNT counter clears #1 CCLR7 Channel 7 GTCNT Count Clear 7 write-only 0 No effect #0 1 GPT167.GTCNT counter clears #1 CCLR8 Channel 8 GTCNT Count Clear 8 write-only 0 No effect #0 1 GPT168.GTCNT counter clears #1 CCLR9 Channel 9 GTCNT Count Clear 9 write-only 0 No effect #0 1 GPT169.GTCNT counter clears #1 Reserved The write value should be 0000000000000000000000. 10 21 write-only GTCNT General PWM Timer Counter 0x48 32 read-write n 0x0 0x0 GTCNT Counter 0 31 read-write GTCR General PWM Timer Control Register 0x2C 32 read-write n 0x0 0x0 CST Count Start 0 read-write 0 Count operation is stopped #0 1 Count operation is performed #1 MD Mode Select 16 2 read-write 000 Saw-wave PWM mode (single buffer or double buffer possible) #000 001 Saw-wave one-shot pulse mode (fixed buffer operation) #001 010 Setting prohibited #010 011 Setting prohibited #011 100 Triangle-wave PWM mode 1 (16-bit transfer at crest) (single buffer or double buffer possible) #100 101 Triangle-wave PWM mode 2 (16-bit transfer at crest and trough) (single buffer or double buffer possible) #101 110 Triangle-wave PWM mode 3 (32-bit transfer at trough) fixed buffer operation) #110 111 Setting prohibited #111 Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write TPCS Timer Prescaler Select 24 2 read-write others Setting prohibied 000 PCLK/1 #000 001 PCLK/4 #001 010 PCLK/16 #010 011 PCLK/64 #011 100 PCLK/256 #100 101 PCLK/1024 #101 GTCSR General PWM Timer Clear Source Select Register 0x18 32 read-write n 0x0 0x0 CCLR Software Source Counter Clear Enable 31 read-write 0 Counter clear is disable by the GTCLR register #0 1 Counter clear is enable by the GTCLR register #1 CSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 11 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 CSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 10 read-write 0 Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 CSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 9 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 CSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 8 read-write 0 Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 CSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 15 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 CSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 14 read-write 0 Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 CSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 13 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 CSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 12 read-write 0 Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 CSELCA ELC_GPTA Event Source Counter Clear Enable 16 read-write 0 Counter clear is disable at the ELC_GPTA input #0 1 Counter clear is enable at the ELC_GPTA input #1 CSELCB ELC_GPTB Event Source Counter Clear Enable 17 read-write 0 Counter clear is disable at the ELC_GPTB input #0 1 Counter clear is enable at the ELC_GPTB input #1 CSELCC ELC_GPTC Event Source Counter Clear Enable 18 read-write 0 Counter clear is disable at the ELC_GPTC input #0 1 Counter clear is enable at the ELC_GPTC input #1 CSELCD ELC_GPTD Event Source Counter Clear Enable 19 read-write 0 Counter clear is disable at the ELC_GPTD input #0 1 Counter clear is enable at the ELC_GPTD input #1 CSELCE ELC_GPTE Event Source Counter Clear Enable 20 read-write 0 Counter clear is disable at the ELC_GPTE input #0 1 Counter clear is enable at the ELC_GPTE input #1 CSELCF ELC_GPTF Event Source Counter Clear Enable 21 read-write 0 Counter clear is disable at the ELC_GPTF input #0 1 Counter clear is enable at the ELC_GPTF input #1 CSELCG ELC_GPTG Event Source Counter Clear Enable 22 read-write 0 Counter clear is disable at the ELC_GPTG input #0 1 Counter clear is enable at the ELC_GPTG input #1 CSELCH ELCH Event Source Counter Clear Enable 23 read-write 0 Counter clear is disable at the ELC_GPTH input #0 1 Counter clear is enable at the ELC_GPTH input #1 CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 1 read-write 0 Counter clear is disable at the falling edge of GTETRGA input #0 1 Counter clear is enable at the falling edge of GTETRGA input #1 CSGTRGAR GTETRGA Pin Rising Input Source Counter Clear Enable 0 read-write 0 Counter clear is disable at the rising edge of GTETRGA input #0 1 Counter clear is enable at the rising edge of GTETRGA input #1 CSGTRGBF GTETRGB Pin Falling Input Source Counter Clear Enable 3 read-write 0 Counter clear is disable at the falling edge of GTETRGB input #0 1 Counter clear is enable at the falling edge of GTETRGB input #1 CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 2 read-write 0 Counter clear is disable at the rising edge of GTETRGB input #0 1 Counter clear is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTDNSR General PWM Timer Down Count Source Select Register 0x20 32 read-write n 0x0 0x0 DSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 11 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 DSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 10 read-write 0 Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 DSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 9 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 DSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 8 read-write 0 Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 DSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 15 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 DSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 14 read-write 0 Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 DSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 13 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 DSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 12 read-write 0 Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 DSELCA ELC_GPTA Event Source Counter Count Down Enable 16 read-write 0 Counter count down is disable at the ELC_GPTA input #0 1 Counter count down is enable at the ELC_GPTA input #1 DSELCB ELC_GPTB Event Source Counter Count Down Enable 17 read-write 0 Counter count down is disable at the ELC_GPTB input #0 1 Counter count down is enable at the ELC_GPTB input #1 DSELCC ELC_GPTC Event Source Counter Count Down Enable 18 read-write 0 Counter count down is disable at the ELC_GPTC input #0 1 Counter count down is enable at the ELC_GPTC input #1 DSELCD ELC_GPTD Event Source Counter Count Down Enable 19 read-write 0 Counter count down is disable at the ELC_GPTD input #0 1 Counter count down is enable at the ELC_GPTD input #1 DSELCE ELC_GPTE Event Source Counter Count Down Enable 20 read-write 0 Counter count down is disable at the ELC_GPTE input #0 1 Counter count down is enable at the ELC_GPTE input #1 DSELCF ELC_GPTF Event Source Counter Count Down Enable 21 read-write 0 Counter count down is disable at the ELC_GPTF input #0 1 Counter count down is enable at the ELC_GPTF input #1 DSELCG ELC_GPTG Event Source Counter Count Down Enable 22 read-write 0 Counter count down is disable at the ELC_GPTG input #0 1 Counter count down is enable at the ELC_GPTG input #1 DSELCH ELCH Event Source Counter Count Down Enable 23 read-write 0 Counter count down is disable at the ELC_GPTH input #0 1 Counter count down is enable at the ELC_GPTH input #1 DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 1 read-write 0 Counter count down is disable at the falling edge of GTETRGA input #0 1 Counter count down is enable at the falling edge of GTETRGA input #1 DSGTRGAR GTETRGA Pin Rising Input Source Counter Count Down Enable 0 read-write 0 Counter count down is disable at the rising edge of GTETRGA input #0 1 Counter count down is enable at the rising edge of GTETRGA input #1 DSGTRGBF GTETRGB Pin Falling Input Source Counter Count Down Enable 3 read-write 0 Counter count down is disable at the falling edge of GTETRGB input #0 1 Counter count down is enable at the falling edge of GTETRGB input #1 DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 2 read-write 0 Counter count down is disable at the rising edge of GTETRGB input #0 1 Counter count down is enable at the rising edge of GTETRGB input #1 GTDTCR General PWM Timer Dead Time Control Register 0x88 32 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write TDE Negative-Phase Waveform Setting 0 read-write 0 GTCCRB is set without using GTDVU and GTDVD. #0 1 GTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB. #1 GTDVU General PWM Timer Dead Time Value Register U 0x8C 32 read-write n 0x0 0x0 GTDVU Dead Time Value Register U 0 31 read-write GTICASR General PWM Timer Input Capture Source Select Register A 0x24 32 read-write n 0x0 0x0 ASCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable 11 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 ASCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 10 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 ASCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable 9 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 ASCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable 8 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 ASCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable 15 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 ASCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 14 read-write 0 GTCCRA input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 ASCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable 13 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 ASCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable 12 read-write 0 GTCCRA input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRA input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 ASELCA ELC_GPTA Event Source GTCCRA Input Capture Enable 16 read-write 0 GTCCRA input capture is disable at the ELC_GPTA input #0 1 GTCCRA input capture is enable at the ELC_GPTA input #1 ASELCB ELC_GPTB Event Source GTCCRA Input Capture Enable 17 read-write 0 GTCCRA input capture is disable at the ELC_GPTB input #0 1 GTCCRA input capture is enable at the ELC_GPTB input #1 ASELCC ELC_GPTC Event Source GTCCRA Input Capture Enable 18 read-write 0 GTCCRA input capture is disable at the ELC_GPTC input #0 1 GTCCRA input capture is enable at the ELC_GPTC input #1 ASELCD ELC_GPTD Event Source GTCCRA Input Capture Enable 19 read-write 0 GTCCRA input capture is disable at the ELC_GPTD input #0 1 GTCCRA input capture is enable at the ELC_GPTD input #1 ASELCE ELC_GPTE Event Source GTCCRA Input Capture Enable 20 read-write 0 GTCCRA input capture is disable at the ELC_GPTE input #0 1 GTCCRA input capture is enable at the ELC_GPTE input #1 ASELCF ELC_GPTF Event Source GTCCRA Input Capture Enable 21 read-write 0 GTCCRA input capture is disable at the ELC_GPTF input #0 1 GTCCRA input capture is enable at the ELC_GPTF input #1 ASELCG ELC_GPTG Event Source GTCCRA Input Capture Enable 22 read-write 0 GTCCRA input capture is disable at the ELC_GPTG input #0 1 GTCCRA input capture is enable at the ELC_GPTG input #1 ASELCH ELCH Event Source GTCCRA Input Capture Enable 23 read-write 0 GTCCRA input capture is disable at the ELC_GPTH input #0 1 GTCCRA input capture is enable at the ELC_GPTH input #1 ASGTRGAF GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable 1 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGA input #1 ASGTRGAR GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable 0 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGA input #1 ASGTRGBF GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable 3 read-write 0 GTCCRA input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRA input capture is enable at the falling edge of GTETRGB input #1 ASGTRGBR GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable 2 read-write 0 GTCCRA input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRA input capture is enable at the rising edge of GTETRGB input #1 GTICBSR General PWM Timer Input Capture Source Select Register B 0x28 32 read-write n 0x0 0x0 BSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable 11 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 BSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 10 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 BSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable 9 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 BSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable 8 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 BSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable 15 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 BSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 14 read-write 0 GTCCRB input capture is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 BSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable 13 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 BSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable 12 read-write 0 GTCCRB input capture is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 GTCCRB input capture is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 BSELCA ELC_GPTA Event Source GTCCRB Input Capture Enable 16 read-write 0 GTCCRB input capture is disable at the ELC_GPTA input #0 1 GTCCRB input capture is enable at the ELC_GPTA input #1 BSELCB ELC_GPTB Event Source GTCCRB Input Capture Enable 17 read-write 0 GTCCRB input capture is disable at the ELC_GPTB input #0 1 GTCCRB input capture is enable at the ELC_GPTB input #1 BSELCC ELC_GPTC Event Source GTCCRB Input Capture Enable 18 read-write 0 GTCCRB input capture is disable at the ELC_GPTC input #0 1 GTCCRB input capture is enable at the ELC_GPTC input #1 BSELCD ELC_GPTD Event Source GTCCRB Input Capture Enable 19 read-write 0 GTCCRB input capture is disable at the ELC_GPTD input #0 1 GTCCRB input capture is enable at the ELC_GPTD input #1 BSELCE ELC_GPTE Event Source GTCCRB Input Capture Enable 20 read-write 0 GTCCRB input capture is disable at the ELC_GPTE input #0 1 GTCCRB input capture is enable at the ELC_GPTE input #1 BSELCF ELC_GPTF Event Source GTCCRB Input Capture Enable 21 read-write 0 GTCCRB input capture is disable at the ELC_GPTF input #0 1 GTCCRB input capture is enable at the ELC_GPTF input #1 BSELCG ELC_GPTG Event Source GTCCRB Input Capture Enable 22 read-write 0 GTCCRB input capture is disable at the ELC_GPTG input #0 1 GTCCRB input capture is enable at the ELC_GPTG input #1 BSELCH ELCH Event Source GTCCRB Input Capture Enable 23 read-write 0 GTCCRB input capture is disable at the ELC_GPTH input #0 1 GTCCRB input capture is enable at the ELC_GPTH input #1 BSGTRGAF GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable 1 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGA input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGA input #1 BSGTRGAR GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable 0 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGA input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGA input #1 BSGTRGBF GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable 3 read-write 0 GTCCRB input capture is disable at the falling edge of GTETRGB input #0 1 GTCCRB input capture is enable at the falling edge of GTETRGB input #1 BSGTRGBR GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable 2 read-write 0 GTCCRB input capture is disable at the rising edge of GTETRGB input #0 1 GTCCRB input capture is enable at the rising edge of GTETRGB input #1 GTINTAD General PWM Timer Interrupt Output Setting Register 0x38 32 read-write n 0x0 0x0 GRP Output Disable Source Select 24 1 read-write others Setting prohibited 00 Group A output disable request #00 01 Group B output disable request #01 GRPABH Same Time Output Level High Disable Request Enable 29 read-write 0 Same time output level high disable request is disabled. #0 1 Same time output level high disable request is enabled. #1 GRPABL Same Time Output Level Low Disable Request Enable 30 read-write 0 Same time output level low disable request is disabled. #0 1 Same time output level low disable request is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 26 2 read-write Reserved These bits are read as 000. The write value should be 000. 26 2 read-write GTIOR General PWM Timer I/O Control Register 0x34 32 read-write n 0x0 0x0 GTIOA GTIOCA Pin Function Select 0 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRA compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRA compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRA compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRA compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRA compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRA compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRA compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRA compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRA compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRA compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRA compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRA compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRA compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRA compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRA compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRA compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRA compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRA compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRA compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRA compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRA compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRA compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRA compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRA compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRA compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRA compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRA compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRA compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRA compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRA compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRA compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRA compare match. #11111 GTIOB GTIOCB Pin Function Select 16 4 read-write 00000 Initial output is Low. Output retained at cycle end. Output retained at GTCCRB compare match. #00000 00001 Initial output is Low. Output retained at cycle end. Low output at GTCCRB compare match. #00001 00010 Initial output is Low. Output retained at cycle end. High output at GTCCRB compare match. #00010 00011 Initial output is Low. Output retained at cycle end. Output toggled at GTCCRB compare match. #00011 00100 Initial output is Low. Low output at cycle end. Output retained at GTCCRB compare match. #00100 00101 Initial output is Low. Low output at cycle end. Low output at GTCCRB compare match. #00101 00110 Initial output is Low. Low output at cycle end. High output at GTCCRB compare match. #00110 00111 Initial output is Low. Low output at cycle end. Output toggled at GTCCRB compare match. #00111 01000 Initial output is Low. High output at cycle end. Output retained at GTCCRB compare match. #01000 01001 Initial output is Low. High output at cycle end. Low output at GTCCRB compare match. #01001 01010 Initial output is Low. High output at cycle end. High output at GTCCRB compare match. #01010 01011 Initial output is Low. High output at cycle end. Output toggled at GTCCRB compare match. #01011 01100 Initial output is Low. Output toggled at cycle end. Output retained at GTCCRB compare match. #01100 01101 Initial output is Low. Output toggled at cycle end. Low output at GTCCRB compare match. #01101 01110 Initial output is Low. Output toggled at cycle end. High output at GTCCRB compare match. #01110 01111 Initial output is Low. Output toggled at cycle end. Output toggled at GTCCRB compare match. #01111 10000 Initial output is High. Output retained at cycle end. Output retained at GTCCRB compare match. #10000 10001 Initial output is High. Output retained at cycle end. Low output at GTCCRB compare match. #10001 10010 Initial output is High. Output retained at cycle end. High output at GTCCRB compare match. #10010 10011 Initial output is High. Output retained at cycle end. Output toggled at GTCCRB compare match. #10011 10100 Initial output is High. Low output at cycle end. Output retained at GTCCRB compare match. #10100 10101 Initial output is High. Low output at cycle end. Low output at GTCCRB compare match. #10101 10110 Initial output is High. Low output at cycle end. High output at GTCCRB compare match. #10110 10111 Initial output is High. Low output at cycle end. Output toggled at GTCCRB compare match. #10111 11000 Initial output is High. High output at cycle end. Output retained at GTCCRB compare match. #11000 11001 Initial output is High. High output at cycle end. Low output at GTCCRB compare match. #11001 11010 Initial output is High. High output at cycle end. High output at GTCCRB compare match. #11010 11011 Initial output is High. High output at cycle end. Output toggled at GTCCRB compare match. #11011 11100 Initial output is High. Output toggled at cycle end. Output retained at GTCCRB compare match. #11100 11101 Initial output is High. Output toggled at cycle end. Low output at GTCCRB compare match. #11101 11110 Initial output is High. Output toggled at cycle end. High output at GTCCRB compare match. #11110 11111 Initial output is High. Output toggled at cycle end. Output toggled at GTCCRB compare match. #11111 NFAEN Noise Filter A Enable 13 read-write 0 The noise filter for the GTIOCA pin is disabled. #0 1 The noise filter for the GTIOCA pin is enabled. #1 NFBEN Noise Filter B Enable 29 read-write 0 The noise filter for the GTIOCB pin is disabled. #0 1 The noise filter for the GTIOCB pin is enabled. #1 NFCSA Noise Filter A Sampling Clock Select 14 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFCSB Noise Filter B Sampling Clock Select 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 OADF GTIOCA Pin Disable Value Setting 9 1 read-write 00 Output disable is prohibited. #00 01 GTIOCA pin is set to Hi-Z when output disable is performed. #01 10 GTIOCA pin is set to 0 when output disable is performed. #10 11 GTIOCA pin is set to 1 when output disable is performed. #11 OADFLT GTIOCA Pin Output Value Setting at the Count Stop 6 read-write 0 The GTIOCA pin outputs low when counting is stopped. #0 1 The GTIOCA pin outputs high when counting is stopped. #1 OAE GTIOCA Pin Output Enable 8 read-write 0 Output is disabled #0 1 Output is enabled #1 OAHLD GTIOCA Pin Output Setting at the Start/Stop Count 7 read-write 0 The GTIOCA pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCA pin output level is retained at start/stop of counting. #1 OBDF GTIOCB Pin Disable Value Setting 25 1 read-write 00 Output disable is prohibited. #00 01 GTIOCB pin is set to Hi-Z when output disable is performed. #01 10 GTIOCB pin is set to 0 when output disable is performed. #10 11 GTIOCB pin is set to 1 when output disable is performed. #11 OBDFLT GTIOCB Pin Output Value Setting at the Count Stop 22 read-write 0 The GTIOCB pin outputs low when counting is stopped. #0 1 The GTIOCB pin outputs high when counting is stopped. #1 OBE GTIOCB Pin Output Enable 24 read-write 0 Output is disabled #0 1 Output is enabled #1 OBHLD GTIOCB Pin Output Setting at the Start/Stop Count 23 read-write 0 The GTIOCB pin output level at start/stop of counting depends on the register setting. #0 1 The GTIOCB pin output level is retained at start/stop of counting. #1 Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved This bit is read as 0. The write value should be 0. 21 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write Reserved These bits are read as 00. The write value should be 00. 11 1 read-write GTPBR General PWM Timer Cycle Setting Buffer Register 0x68 32 read-write n 0x0 0x0 GTPBR Cycle Setting Buffer Register 0 31 read-write GTPR General PWM Timer Cycle Setting Register 0x64 32 read-write n 0x0 0x0 GTPR Cycle Setting Register 0 31 read-write GTPSR General PWM Timer Stop Source Select Register 0x14 32 read-write n 0x0 0x0 CSTOP Software Source Counter Stop Enable 31 read-write 0 Counter stop is disable by the GTSTP register #0 1 Counter stop is enable by the GTSTP register #1 PSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 11 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 PSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 10 read-write 0 Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 PSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 9 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 PSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 8 read-write 0 Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 PSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 15 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 PSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 14 read-write 0 Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 PSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 13 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 PSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 12 read-write 0 Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 PSELCA ELC_GPTA Event Source Counter Stop Enable 16 read-write 0 Counter stop is disable at the ELC_GPTA input #0 1 Counter stop is enable at the ELC_GPTA input #1 PSELCB ELC_GPTB Event Source Counter Stop Enable 17 read-write 0 Counter stop is disable at the ELC_GPTB input #0 1 Counter stop is enable at the ELC_GPTB input #1 PSELCC ELC_GPTC Event Source Counter Stop Enable 18 read-write 0 Counter stop is disable at the ELC_GPTC input #0 1 Counter stop is enable at the ELC_GPTC input #1 PSELCD ELC_GPTD Event Source Counter Stop Enable 19 read-write 0 Counter stop is disable at the ELC_GPTD input #0 1 Counter stop is enable at the ELC_GPTD input #1 PSELCE ELC_GPTE Event Source Counter Stop Enable 20 read-write 0 Counter stop is disable at the ELC_GPTE input #0 1 Counter stop is enable at the ELC_GPTE input #1 PSELCF ELC_GPTF Event Source Counter Stop Enable 21 read-write 0 Counter stop is disable at the ELC_GPTF input #0 1 Counter stop is enable at the ELC_GPTF input #1 PSELCG ELC_GPTG Event Source Counter Stop Enable 22 read-write 0 Counter stop is disable at the ELC_GPTG input #0 1 Counter stop is enable at the ELC_GPTG input #1 PSELCH ELCH Event Source Counter Stop Enable 23 read-write 0 Counter stop is disable at the ELC_GPTH input #0 1 Counter stop is enable at the ELC_GPTH input #1 PSGTRGAF GTETRGA Pin Falling Input Source Counter Stop Enable 1 read-write 0 Counter stop is disable at the falling edge of GTETRGA input #0 1 Counter stop is enable at the falling edge of GTETRGA input #1 PSGTRGAR GTETRGA Pin Rising Input Source Counter Stop Enable 0 read-write 0 Counter stop is disable at the rising edge of GTETRGA input #0 1 Counter stop is enable at the rising edge of GTETRGA input #1 PSGTRGBF GTETRGB Pin Falling Input Source Counter Stop Enable 3 read-write 0 Counter stop is disable at the falling edge of GTETRGB input #0 1 Counter stop is enable at the falling edge of GTETRGB input #1 PSGTRGBR GTETRGB Pin Rising Input Source Counter Stop Enable 2 read-write 0 Counter stop is disable at the rising edge of GTETRGB input #0 1 Counter stop is enable at the rising edge of GTETRGB input #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write GTSSR General PWM Timer Start Source Select Register 0x10 32 read-write n 0x0 0x0 CSTRT Software Source Counter Start Enable 31 read-write 0 Counter start is disable by the GTSTR register #0 1 Counter start is enable by the GTSTR register #1 Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 24 6 read-write SSCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 11 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 SSCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 10 read-write 0 Counter start is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 SSCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 9 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 SSCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 8 read-write 0 Counter start is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter start is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 SSCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 15 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 SSCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 14 read-write 0 Counter start is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 SSCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 13 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 SSCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 12 read-write 0 Counter start is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter start is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 SSELCA ELC_GPTA Event Source Counter Start Enable 16 read-write 0 Counter start is disable at the ELC_GPTA input #0 1 Counter start is enable at the ELC_GPTA input #1 SSELCB ELC_GPTB Event Source Counter Start Enable 17 read-write 0 Counter start is disable at the ELC_GPTB input #0 1 Counter start is enable at the ELC_GPTB input #1 SSELCC ELC_GPTC Event Source Counter Start Enable 18 read-write 0 Counter start is disable at the ELC_GPTC input #0 1 Counter start is enable at the ELC_GPTC input #1 SSELCD ELC_GPTD Event Source Counter Start Enable 19 read-write 0 Counter start is disable at the ELC_GPTD input #0 1 Counter start is enable at the ELC_GPTD input #1 SSELCE ELC_GPTE Event Source Counter Start Enable 20 read-write 0 Counter start is disable at the ELC_GPTE input #0 1 Counter start is enable at the ELC_GPTE input #1 SSELCF ELC_GPTF Event Source Counter Start Enable 21 read-write 0 Counter start is disable at the ELC_GPTF input #0 1 Counter start is enable at the ELC_GPTF input #1 SSELCG ELC_GPTG Event Source Counter Start Enable 22 read-write 0 Counter start is disable at the ELC_GPTG input #0 1 Counter start is enable at the ELC_GPTG input #1 SSELCH ELCH Event Source Counter Start Enable 23 read-write 0 Counter start is disable at the ELC_GPTH input #0 1 Counter start is enable at the ELC_GPTH input #1 SSGTRGAF GTETRGA Pin Falling Input Source Counter Start Enable 1 read-write 0 Counter start is disable at the falling edge of GTETRGA input #0 1 Counter start is enable at the falling edge of GTETRGA input #1 SSGTRGAR GTETRGA Pin Rising Input Source Counter Start Enable 0 read-write 0 Counter start is disable at the rising edge of GTETRGA input #0 1 Counter start is enable at the rising edge of GTETRGA input #1 SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 3 read-write 0 Counter start is disable at the falling edge of GTETRGB input #0 1 Counter start is enable at the falling edge of GTETRGB input #1 SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 2 read-write 0 Counter start is disable at the rising edge of GTETRGB input #0 1 Counter start is enable at the rising edge of GTETRGB input #1 GTST General PWM Timer Status Register 0x3C 32 read-write n 0x0 0x0 OABHF Same Time Output Level High Disable Request Enable 29 read-only 0 GTIOCA pin and GTIOCB pin don't output 1 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 1 at the same time. #1 OABLF Same Time Output Level Low Disable Request Enable 30 read-only 0 GTIOCA pin and GTIOCB pin don't output 0 at the same time. #0 1 GTIOCA pin and GTIOCB pin output 0 at the same time. #1 ODF Output Disable Flag 24 read-only 0 No output disable request is generated. #0 1 An output disable request is generated. #1 Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 16 7 read-write TCFA Input Capture/Compare Match Flag A 0 read-write 0 No input capture/compare match of GTCCRA is generated. #0 1 An input capture/compare match of GTCCRA is generated. #1 TCFB Input Capture/Compare Match Flag B 1 read-write 0 No input capture/compare match of GTCCRB is generated. #0 1 An input capture/compare match of GTCCRB is generated. #1 TCFC Input Compare Match Flag C 2 read-write 0 No compare match of GTCCRC is generated. #0 1 A compare match of GTCCRC is generated. #1 TCFD Input Compare Match Flag D 3 read-write 0 No compare match of GTCCRD is generated. #0 1 A compare match of GTCCRD is generated. #1 TCFE Input Compare Match Flag E 4 read-write 0 No compare match of GTCCRE is generated. #0 1 A compare match of GTCCRE is generated. #1 TCFF Input Compare Match Flag F 5 read-write 0 No compare match of GTCCRF is generated. #0 1 A compare match of GTCCRF is generated. #1 TCFPU Underflow Flag 7 read-write 0 No underflow (trough) has occurred. #0 1 An underflow (trough) has occurred. #1 TCPFO Overflow Flag 6 read-write 0 No overflow (crest) has occurred. #0 1 An overflow (crest) has occurred. #1 TUCF Count Direction Flag 15 read-only 0 The GTCNT counter counts downward. #0 1 The GTCNT counter counts upward. #1 GTSTP General PWM Timer Software Stop Register 0x8 32 read-write n 0x0 0x0 CSTOP0 Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 0 read-write 0 No effect (write) / counter running (read) #0 1 GPT320.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP1 Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 1 read-write 0 No effect (write) / counter running (read) #0 1 GPT321.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP2 Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 2 read-write 0 No effect (write) / counter running (read) #0 1 GPT322.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP3 Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 3 read-write 0 No effect (write) / counter running (read) #0 1 GPT323.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP4 Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 4 read-write 0 No effect (write) / counter running (read) #0 1 GPT164.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP5 Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 5 read-write 0 No effect (write) / counter running (read) #0 1 GPT165.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP6 Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 6 read-write 0 No effect (write) / counter running (read) #0 1 GPT166.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP7 Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 7 read-write 0 No effect (write) / counter running (read) #0 1 GPT167.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP8 Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 8 read-write 0 No effect (write) / counter running (read) #0 1 GPT168.GTCNT counter stops (write) / Counter stop (read) #1 CSTOP9 Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop. 9 read-write 0 No effect (write) / counter running (read) #0 1 GPT169.GTCNT counter stops (write) / Counter stop (read) #1 Reserved These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111. 10 21 read-write GTSTR General PWM Timer Software Start Register 0x4 32 read-write n 0x0 0x0 CSTRT0 Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 0 read-write 0 No effect (write) / counter stop (read) #0 1 GPT320.GTCNT counter starts (write) / Counter running (read) #1 CSTRT1 Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 1 read-write 0 No effect (write) / counter stop (read) #0 1 GPT321.GTCNT counter starts (write) / Counter running (read) #1 CSTRT2 Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 2 read-write 0 No effect (write) / counter stop (read) #0 1 GPT322.GTCNT counter starts (write) / Counter running (read) #1 CSTRT3 Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 3 read-write 0 No effect (write) / counter stop (read) #0 1 GPT323.GTCNT counter starts (write) / Counter running (read) #1 CSTRT4 Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 4 read-write 0 No effect (write) / counter stop (read) #0 1 GPT164.GTCNT counter starts (write) / Counter running (read) #1 CSTRT5 Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 5 read-write 0 No effect (write) / counter stop (read) #0 1 GPT165.GTCNT counter starts (write) / Counter running (read) #1 CSTRT6 Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 6 read-write 0 No effect (write) / counter stop (read) #0 1 GPT166.GTCNT counter starts (write) / Counter running (read) #1 CSTRT7 Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 7 read-write 0 No effect (write) / counter stop (read) #0 1 GPT167.GTCNT counter starts (write) / Counter running (read) #1 CSTRT8 Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 8 read-write 0 No effect (write) / counter stop (read) #0 1 GPT168.GTCNT counter starts (write) / Counter running (read) #1 CSTRT9 Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running. 9 read-write 0 No effect (write) / counter stop (read) #0 1 GPT169.GTCNT counter starts (write) / Counter running (read) #1 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write GTUDDTYC General PWM Timer Count Direction and Duty Setting Register 0x30 32 read-write n 0x0 0x0 OADTY GTIOCA Output Duty Setting 16 1 read-write 00 GTIOCA pin duty is depend on compare match #00 01 GTIOCA pin duty is depend on compare match #01 10 GTIOCA pin duty 0 percent #10 11 GTIOCA pin duty 100 percent #11 OADTYF Forcible GTIOCA Output Duty Setting 18 read-write 0 Not forcibly set #0 1 Forcibly set #1 OADTYR GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 19 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOA[3:2] function after releasing 0 percent/100 percent duty setting. #1 OBDTY GTIOCB Output Duty Setting 24 1 read-write 00 GTIOCB pin duty is depend on compare match #00 01 GTIOCB pin duty is depend on compare match #01 10 GTIOCB pin duty 0 percent #10 11 GTIOCB pin duty 100 percent #11 OBDTYF Forcible GTIOCB Output Duty Setting 26 read-write 0 Not forcibly set #0 1 Forcibly set #1 OBDTYR GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting 27 read-write 0 Apply output value set in 0 percent/100 percent duty to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #0 1 Apply masked compare match output value to GTIOB[3:2] function after releasing 0 percent/100 percent duty setting. #1 Reserved These bits are read as 0000. The write value should be 0000. 20 3 read-write UD Count Direction Setting 0 read-write 0 GTCNT counts down. #0 1 GTCNT counts up. #1 UDF Forcible Count Direction Setting 1 read-write 0 Not forcibly set #0 1 Forcibly set #1 GTUPSR General PWM Timer Up Count Source Select Register 0x1C 32 read-write n 0x0 0x0 USCAFBH GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable 11 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 1 #1 USCAFBL GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable 10 read-write 0 Counter count up is disable at the falling edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCA input when GTIOCB input is 0 #1 USCARBH GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable 9 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 1 #1 USCARBL GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable 8 read-write 0 Counter count up is disable at the rising edge of GTIOCA input when GTIOCB input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCA input when GTIOCB input is 0 #1 USCBFAH GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable 15 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 1 #1 USCBFAL GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable 14 read-write 0 Counter count up is disable at the falling edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the falling edge of GTIOCB input when GTIOCA input is 0 #1 USCBRAH GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable 13 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 1 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 1 #1 USCBRAL GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable 12 read-write 0 Counter count up is disable at the rising edge of GTIOCB input when GTIOCA input is 0 #0 1 Counter count up is enable at the rising edge of GTIOCB input when GTIOCA input is 0 #1 USELCA ELC_GPTA Event Source Counter Count Up Enable 16 read-write 0 Counter count up is disable at the ELC_GPTA input #0 1 Counter count up is enable at the ELC_GPTA input #1 USELCB ELC_GPTB Event Source Counter Count Up Enable 17 read-write 0 Counter count up is disable at the ELC_GPTB input #0 1 Counter count up is enable at the ELC_GPTB input #1 USELCC ELC_GPTC Event Source Counter Count Up Enable 18 read-write 0 Counter count up is disable at the ELC_GPTC input #0 1 Counter count up is enable at the ELC_GPTC input #1 USELCD ELC_GPTD Event Source Counter Count Up Enable 19 read-write 0 Counter count up is disable at the ELC_GPTD input #0 1 Counter count up is enable at the ELC_GPTD input #1 USELCE ELC_GPTE Event Source Counter Count Up Enable 20 read-write 0 Counter count up is disable at the ELC_GPTE input #0 1 Counter count up is enable at the ELC_GPTE input #1 USELCF ELC_GPTF Event Source Counter Count Up Enable 21 read-write 0 Counter count up is disable at the ELC_GPTF input #0 1 Counter count up is enable at the ELC_GPTF input #1 USELCG ELC_GPTG Event Source Counter Count Up Enable 22 read-write 0 Counter count up is disable at the ELC_GPTG input #0 1 Counter count up is enable at the ELC_GPTG input #1 USELCH ELCH Event Source Counter Count Up Enable 23 read-write 0 Counter count up is disable at the ELC_GPTH input #0 1 Counter count up is enable at the ELC_GPTH input #1 USGTRGAF GTETRGA Pin Falling Input Source Counter Count Up Enable 1 read-write 0 Counter count up is disable at the falling edge of GTETRGA input #0 1 Counter count up is enable at the falling edge of GTETRGA input #1 USGTRGAR GTETRGA Pin Rising Input Source Counter Count Up Enable 0 read-write 0 Counter count up is disable at the rising edge of GTETRGA input #0 1 Counter count up is enable at the rising edge of GTETRGA input #1 USGTRGBF GTETRGB Pin Falling Input Source Counter Count Up Enable 3 read-write 0 Counter count up is disable at the falling edge of GTETRGB input #0 1 Counter count up is enable at the falling edge of GTETRGB input #1 USGTRGBR GTETRGB Pin Rising Input Source Counter Count Up Enable 2 read-write 0 Counter count up is disable at the rising edge of GTETRGB input #0 1 Counter count up is enable at the rising edge of GTETRGB input #1 GTWP General PWM Timer Write-Protection Register 0x0 32 read-write n 0x0 0x0 PRKEY GTWP Key Code 8 7 write-only others The WP bits write is not permitted. 0xA5 Written to these bits, the WP bits write is permitted. 0xA5 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write WP Register Write Disable 0 read-write 0 Write to the register is enabled #0 1 Write to the register is disabled #1 GPT_OPS Output Phase Switching Controller GPT_OPS 0x0 0x0 0x4 registers n OPSCR Output Phase Switching Control Register 0x0 32 read-write n 0x0 0x0 ALIGN Input phase alignment 21 read-write 0 Input phase is aligned to PCLK. #0 1 Input phase is aligned PWM. #1 EN Enable-Phase Output Control 8 read-write 0 Not Output(Hi-Z external terminals). #0 1 Output #1 FB External Feedback Signal EnableThis bit selects the input phase from the software settings and external input. 16 read-write 0 Select the external input. #0 1 Select the soft setting(OPSCR.UF, VF, WF). #1 GODF Group output disable function 26 read-write 0 This bit function is ignored. #0 1 Group disable will clear OPSCR.EN Bit. #1 GRP Output disabled source selection 24 1 read-write others Setting prohibited 00 Select Group A output disable source #00 01 Select Group B output disable source #01 INV Invert-Phase Output Control 19 read-write 0 Positive Logic (Active High)output #0 1 Negative Logic (Active Low)output #1 N Negative-Phase Output (N) Control 18 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 NFCS External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input. 30 1 read-write 00 PCLK/1 #00 01 PCLK/4 #01 10 PCLK/16 #10 11 PCLK/64 #11 NFEN External Input Noise Filter Enable 29 read-write 0 Do not use a noise filter to the external input. #0 1 Use a noise filter to the external input. #1 P Positive-Phase Output (P) Control 17 read-write 0 Level signal output #0 1 PWM signal output (PWM of GPT0) #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved These bits are read as 00. The write value should be 00. 22 1 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write RV Output phase rotation direction reversal 20 read-write 0 U/V/W-Phase output #0 1 Output to reverse the V / W-phase #1 U Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 4 read-only UF Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 0 read-write V Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 5 read-only VF Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 1 read-write W Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF) 6 read-only WF Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1. 2 read-write ICU Interrupt Controller ICU 0x0 0x0 0x10 registers n 0x0 0x10 registers n 0x100 0x1 registers n 0x120 0x2 registers n 0x130 0x2 registers n 0x140 0x2 registers n 0x1A0 0x4 registers n 0x200 0x2 registers n 0x280 0x10 registers n 0x300 0x80 registers n IEL0 ICU Interrupt 0 0 IEL1 ICU Interrupt 1 1 IEL2 ICU Interrupt 2 2 IEL3 ICU Interrupt 3 3 IEL4 ICU Interrupt 4 4 IEL5 ICU Interrupt 5 5 IEL6 ICU Interrupt 6 6 IEL7 ICU Interrupt 7 7 IEL8 ICU Interrupt 8 8 IEL9 ICU Interrupt 9 9 IEL10 ICU Interrupt 10 10 IEL11 ICU Interrupt 11 11 IEL12 ICU Interrupt 12 12 IEL13 ICU Interrupt 13 13 IEL14 ICU Interrupt 14 14 IEL15 ICU Interrupt 15 15 IEL16 ICU Interrupt 16 16 IEL17 ICU Interrupt 17 17 IEL18 ICU Interrupt 18 18 IEL19 ICU Interrupt 19 19 IEL20 ICU Interrupt 20 20 IEL21 ICU Interrupt 21 21 IEL22 ICU Interrupt 22 22 IEL23 ICU Interrupt 23 23 IEL24 ICU Interrupt 24 24 IEL25 ICU Interrupt 25 25 IEL26 ICU Interrupt 26 26 IEL27 ICU Interrupt 27 27 IEL28 ICU Interrupt 28 28 IEL29 ICU Interrupt 29 29 IEL30 ICU Interrupt 30 30 IEL31 ICU Interrupt 31 31 DELSR0 DMAC Event Link Setting Register %s 0x280 16 read-write n 0x0 0x0 DELS Event selection to DMAC Start request 0 7 read-write others See Event Table 0x000 Nothing is selected. 0x000 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write DELSR1 DMAC Event Link Setting Register %s 0x284 16 read-write n 0x0 0x0 DELS Event selection to DMAC Start request 0 7 read-write others See Event Table 0x000 Nothing is selected. 0x000 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write DELSR2 DMAC Event Link Setting Register %s 0x288 16 read-write n 0x0 0x0 DELS Event selection to DMAC Start request 0 7 read-write others See Event Table 0x000 Nothing is selected. 0x000 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write DELSR3 DMAC Event Link Setting Register %s 0x28C 16 read-write n 0x0 0x0 DELS Event selection to DMAC Start request 0 7 read-write others See Event Table 0x000 Nothing is selected. 0x000 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write IELSR0 ICU Event Link Setting Register %s 0x300 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR1 ICU Event Link Setting Register %s 0x304 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR10 ICU Event Link Setting Register %s 0x328 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR11 ICU Event Link Setting Register %s 0x32C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR12 ICU Event Link Setting Register %s 0x330 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR13 ICU Event Link Setting Register %s 0x334 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR14 ICU Event Link Setting Register %s 0x338 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR15 ICU Event Link Setting Register %s 0x33C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR16 ICU Event Link Setting Register %s 0x340 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR17 ICU Event Link Setting Register %s 0x344 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR18 ICU Event Link Setting Register %s 0x348 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR19 ICU Event Link Setting Register %s 0x34C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR2 ICU Event Link Setting Register %s 0x308 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR20 ICU Event Link Setting Register %s 0x350 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR21 ICU Event Link Setting Register %s 0x354 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR22 ICU Event Link Setting Register %s 0x358 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR23 ICU Event Link Setting Register %s 0x35C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR24 ICU Event Link Setting Register %s 0x360 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR25 ICU Event Link Setting Register %s 0x364 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR26 ICU Event Link Setting Register %s 0x368 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR27 ICU Event Link Setting Register %s 0x36C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR28 ICU Event Link Setting Register %s 0x370 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR29 ICU Event Link Setting Register %s 0x374 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR3 ICU Event Link Setting Register %s 0x30C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR30 ICU Event Link Setting Register %s 0x378 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR31 ICU Event Link Setting Register %s 0x37C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR4 ICU Event Link Setting Register %s 0x310 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR5 ICU Event Link Setting Register %s 0x314 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR6 ICU Event Link Setting Register %s 0x318 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR7 ICU Event Link Setting Register %s 0x31C 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR8 ICU Event Link Setting Register %s 0x320 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IELSR9 ICU Event Link Setting Register %s 0x324 32 read-write n 0x0 0x0 DTCE DTC Activation Enable 24 read-write 0 DTC activation is disabled #0 1 DTC activation is enabled #1 IELS ICU Event selection to NVICSet the number for the event signal to be linked . 0 7 read-write others See Event Table 0x000 Nothing is selected 0x000 IR Interrupt Status Flag 16 read-write 0 No interrupt request is generated #0 1 An interrupt request is generated ( 1 write to the IR bit is prohibited. ) #1 Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write IRQCR0 IRQ Control Register %s 0x0 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR1 IRQ Control Register %s 0x1 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR10 IRQ Control Register %s 0xA 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR11 IRQ Control Register %s 0xB 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR12 IRQ Control Register %s 0xC 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR13 IRQ Control Register %s 0xD 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR14 IRQ Control Register %s 0xE 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR15 IRQ Control Register %s 0xF 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR2 IRQ Control Register %s 0x2 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR3 IRQ Control Register %s 0x3 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR4 IRQ Control Register %s 0x4 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR5 IRQ Control Register %s 0x5 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR6 IRQ Control Register %s 0x6 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR7 IRQ Control Register %s 0x7 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR8 IRQ Control Register %s 0x8 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write IRQCR9 IRQ Control Register %s 0x9 8 read-write n 0x0 0x0 FCLKSEL IRQ Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 FLTEN IRQ Digital Filter Enable 7 read-write 0 Digital filter disabled. #0 1 Digital filter enabled. #1 IRQMD IRQ Detection Sense Select 0 1 read-write 00 Falling edge #00 01 Rising edge #01 10 Rising and falling edges #10 11 Low level #11 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write NMICLR Non-Maskable Interrupt Status Clear Register 0x130 16 read-write n 0x0 0x0 BUSMCLR Bus Master Error Clear 11 write-only 0 No effect. #0 1 Clear the NMISR.BUSMST flag. #1 BUSSCLR Bus Slave Error Clear 10 write-only 0 No effect. #0 1 Clear the NMISR.BUSSST flag. #1 IWDTCLR IWDT Clear 0 write-only 0 No effect. #0 1 Clear the NMISR.IWDTST flag. #1 LVD1CLR LVD1 Clear 2 write-only 0 No effect. #0 1 Clear the NMISR.LVD1ST flag. #1 LVD2CLR LVD2 Clear 3 write-only 0 No effect. #0 1 Clear the NMISR.LVD2ST flag. #1 NMICLR NMI Clear 7 write-only 0 No effect. #0 1 Clear the NMISR.NMIST flag. #1 OSTCLR OST Clear 6 write-only 0 No effect. #0 1 Clear the NMISR.OSTST flag. #1 RECCCLR SRAM ECC Error Clear 9 write-only 0 No effect. #0 1 Clear the NMISR.RECCST flag. #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write RPECLR SRAM Parity Error Clear 8 write-only 0 No effect. #0 1 Clear the NMISR.RPEST flag. #1 SPECLR CPU Stack Pointer Monitor Interrupt Clear 12 write-only 0 No effect. #0 1 Clear the NMISR.SPEST flag. #1 VBATTCLR VBATT Clear 4 write-only 0 No effect. #0 1 Clear the NMISR.VBATTST flag. #1 WDTCLR WDT Clear 1 write-only 0 No effect. #0 1 Clear the NMISR.WDTST flag. #1 NMICR NMI Pin Interrupt Control Register 0x100 8 read-write n 0x0 0x0 NFCLKSEL NMI Digital Filter Sampling Clock Select 4 1 read-write 00 PCLKB #00 01 PCLKB/8 #01 10 PCLKB/32 #10 11 PCLKB/64 #11 NFLTEN NMI Digital Filter Enable 7 read-write 0 Digital filter is disabled. #0 1 Digital filter is enabled. #1 NMIMD NMI Detection Set 0 read-write 0 Falling edge #0 1 Rising edge #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write NMIER Non-Maskable Interrupt Enable Register 0x120 16 read-write n 0x0 0x0 BUSMEN MPU Bus Master Error Interrupt Enable 11 read-write 0 Disabled #0 1 Enabled. #1 BUSSEN MPU Bus Slave Error Interrupt Enable 10 read-write 0 Disabled #0 1 Enabled. #1 IWDTEN IWDT Underflow/Refresh Error Interrupt Enable 0 read-write 0 Disabled #0 1 Enabled. #1 LVD1EN Voltage-Monitoring 1 Interrupt Enable 2 read-write 0 Disabled #0 1 Enabled. #1 LVD2EN Voltage-Monitoring 2 Interrupt Enable 3 read-write 0 Disabled #0 1 Enabled. #1 NMIEN NMI Pin Interrupt Enable 7 read-write 0 Disabled #0 1 Enabled. #1 OSTEN Oscillation Stop Detection Interrupt Enable 6 read-write 0 Disabled #0 1 Enabled. #1 RECCEN RAM ECC Error Interrupt Enable 9 read-write 0 Disabled #0 1 Enabled. #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write RPEEN RAM Parity Error Interrupt Enable 8 read-write 0 Disabled #0 1 Enabled. #1 SPEEN CPU Stack pointer monitor Interrupt Enable 12 read-write 0 Disabled #0 1 Enabled. #1 VBATTEN VBATT monitor Interrupt Enable 4 read-write 0 Disabled #0 1 Enabled. #1 WDTEN WDT Underflow/Refresh Error Interrupt Enable 1 read-write 0 Disabled #0 1 Enabled. #1 NMISR Non-Maskable Interrupt Status Register 0x140 16 read-only n 0x0 0x0 BUSMST MPU Bus Master Error Interrupt Status Flag 11 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 BUSSST MPU Bus Slave Error Interrupt Status Flag 10 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 IWDTST IWDT Underflow/Refresh Error Status Flag 0 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 LVD1ST Voltage-Monitoring 1 Interrupt Status Flag 2 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 LVD2ST Voltage-Monitoring 2 Interrupt Status Flag 3 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 NMIST NMI Status Flag 7 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 OSTST Oscillation Stop Detection Interrupt Status Flag 6 read-only 0 Interrupt not requested for main oscillation stop #0 1 Interrupt requested for main oscillation stop. #1 RECCST RAM ECC Error Interrupt Status Flag 9 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 Reserved These bits are read as 000. 13 2 read-only Reserved These bits are read as 000. 13 2 read-only RPEST RAM Parity Error Interrupt Status Flag 8 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 SPEST CPU Stack pointer monitor Interrupt Status Flag 12 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 VBATTST VBATT monitor Interrupt Status Flag 4 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 WDTST WDT Underflow/Refresh Error Status Flag 1 read-only 0 Interrupt not requested #0 1 Interrupt requested. #1 SELSR0 Snooze Event Link Setting Register 0x200 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write SELS SYS Event Link Select 0 7 read-write others Settings prohibited. 0x000 Nothing is selected 0x000 0x015 DTC_COMPLETE 0x015 0x02D ADC140_WCMPM 0x02D 0x02E ADC140_WCMPUM 0x02E 0x048 CTSU_CTSUFN 0x048 0x04A DOC_DOPCI 0x04A 0x0B0 SCI0_AM 0x0B0 0x0B1 SCI0_RXI_OR_ERI 0x0B1 WUPEN Wake Up Interrupt Enable Register 0x1A0 32 read-write n 0x0 0x0 ACMPLP0WUPEN ACMPLP0 interrupt S/W standby returns enable 23 read-write 0 S/W standby returns by ACMPLP0 interrupt is disabled #0 1 S/W standby returns by ACMPLP0 interrupt is enabled #1 AGT1CAWUPEN AGT1 compare match A interrupt S/W standby returns enable 29 read-write 0 S/W standby returns by AGT1 compare match A interrupt is disabled #0 1 S/W standby returns by AGT1 compare match A interrupt is enabled #1 AGT1CBWUPEN AGT1 compare match B interrupt S/W standby returns enable 30 read-write 0 S/W standby returns by AGT1 compare match B interrupt is disabled #0 1 S/W standby returns by AGT1 compare match B interrupt is enabled #1 AGT1UDWUPEN AGT1 underflow interrupt S/W standby returns enable 28 read-write 0 S/W standby returns by AGT1 underflow interrupt is disabled #0 1 S/W standby returns by AGT1 underflow interrupt is enabled #1 IIC0WUPEN IIC0 address match interrupt S/W standby returns enable 31 read-write 0 S/W standby returns by IIC0 address match interrupt is disabled #0 1 S/W standby returns by IIC0 address match interrupt is enabled #1 IRQWUPEN0 IRQ0 interrupt S/W standby returns enable 0 read-write 0 S/W standby returns by IRQ0 interrupt is disabled #0 1 S/W standby returns by IRQ0 interrupt is enabled #1 IRQWUPEN1 IRQ1 interrupt S/W standby returns enable 1 read-write 0 S/W standby returns by IRQ1 interrupt is disabled #0 1 S/W standby returns by IRQ1 interrupt is enabled #1 IRQWUPEN10 IRQ10 interrupt S/W standby returns enable 10 read-write 0 S/W standby returns by IRQ10 interrupt is disabled #0 1 S/W standby returns by IRQ10 interrupt is enabled #1 IRQWUPEN11 IRQ11 interrupt S/W standby returns enable 11 read-write 0 S/W standby returns by IRQ11 interrupt is disabled #0 1 S/W standby returns by IRQ11 interrupt is enabled #1 IRQWUPEN12 IRQ12 interrupt S/W standby returns enable 12 read-write 0 S/W standby returns by IRQ12 interrupt is disabled #0 1 S/W standby returns by IRQ12 interrupt is enabled #1 IRQWUPEN13 IRQ13 interrupt S/W standby returns enable 13 read-write 0 S/W standby returns by IRQ13 interrupt is disabled #0 1 S/W standby returns by IRQ13 interrupt is enabled #1 IRQWUPEN14 IRQ14 interrupt S/W standby returns enable 14 read-write 0 S/W standby returns by IRQ14 interrupt is disabled #0 1 S/W standby returns by IRQ14 interrupt is enabled #1 IRQWUPEN15 IRQ15 interrupt S/W standby returns enable 15 read-write 0 S/W standby returns by IRQ15 interrupt is disabled #0 1 S/W standby returns by IRQ15 interrupt is enabled #1 IRQWUPEN2 IRQ2 interrupt S/W standby returns enable 2 read-write 0 S/W standby returns by IRQ2 interrupt is disabled #0 1 S/W standby returns by IRQ2 interrupt is enabled #1 IRQWUPEN3 IRQ3 interrupt S/W standby returns enable 3 read-write 0 S/W standby returns by IRQ3 interrupt is disabled #0 1 S/W standby returns by IRQ3 interrupt is enabled #1 IRQWUPEN4 IRQ4 interrupt S/W standby returns enable 4 read-write 0 S/W standby returns by IRQ4 interrupt is disabled #0 1 S/W standby returns by IRQ4 interrupt is enabled #1 IRQWUPEN5 IRQ5 interrupt S/W standby returns enable 5 read-write 0 S/W standby returns by IRQ5 interrupt is disabled #0 1 S/W standby returns by IRQ5 interrupt is enabled #1 IRQWUPEN6 IRQ6 interrupt S/W standby returns enable 6 read-write 0 S/W standby returns by IRQ6 interrupt is disabled #0 1 S/W standby returns by IRQ6 interrupt is enabled #1 IRQWUPEN7 IRQ7 interrupt S/W standby returns enable 7 read-write 0 S/W standby returns by IRQ7 interrupt is disabled #0 1 S/W standby returns by IRQ7 interrupt is enabled #1 IRQWUPEN8 IRQ8 interrupt S/W standby returns enable 8 read-write 0 S/W standby returns by IRQ8 interrupt is disabled #0 1 S/W standby returns by IRQ8 interrupt is enabled #1 IRQWUPEN9 IRQ9 interrupt S/W standby returns enable 9 read-write 0 S/W standby returns by IRQ9 interrupt is disabled #0 1 S/W standby returns by IRQ9 interrupt is enabled #1 IWDTWUPEN IWDT interrupt S/W standby returns enable 16 read-write 0 S/W standby returns by IWDT interrupt is disabled #0 1 S/W standby returns by IWDT interrupt is enabled #1 KEYWUPEN Key interrupt S/W standby returns enable 17 read-write 0 S/W standby returns by KEY interrupt is disabled #0 1 S/W standby returns by KEY interrupt is enabled #1 LVD1WUPEN LVD1 interrupt S/W standby returns enable 18 read-write 0 S/W standby returns by LVD1 interrupt is disabled #0 1 S/W standby returns by LVD1 interrupt is enabled #1 LVD2WUPEN LVD2 interrupt S/W standby returns enable 19 read-write 0 S/W standby returns by LVD2 interrupt is disabled #0 1 S/W standby returns by LVD2 interrupt is enabled #1 Reserved This bit is read as 0. The write value should be 0. 26 read-write Reserved This bit is read as 0. The write value should be 0. 26 read-write RTCALMWUPEN RTC alarm interrupt S/W standby returns enable 24 read-write 0 S/W standby returns by RTC alarm interrupt is disabled #0 1 S/W standby returns by RTC alarm interrupt is enabled #1 RTCPRDWUPEN RCT period interrupt S/W standby returns enable 25 read-write 0 S/W standby returns by RTC period interrupt is disabled #0 1 S/W standby returns by RTC period interrupt is enabled #1 USBFSWUPEN USBFS interrupt S/W standby returns enable 27 read-write 0 S/W standby returns by USBFS interrupt is disabled #0 1 S/W standby returns by USBFS interrupt is enabled #1 VBATTWUPEN VBATT monitor interrupt S/W standby returns enable 20 read-write 0 S/W standby returns by VBATT monitor interrupt is disabled #0 1 S/W standby returns by VBATT monitor interrupt is enabled #1 IIC0 Inter-Integrated Circuit 0 IIC0 0x0 0x0 0x10 registers n 0x10 0x4 registers n 0x16 0x2 registers n 0xB 0x6 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period(Low-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 SCLI SCL Line Monitor 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SCLO SCL Output Control/Monitor 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAI SDA Line Monitor 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 SDAO SDA Output Control/Monitor 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SOWP SCLO/SDAO Write Protect 4 read-write 0 Bits SCLO and SDAO can be written #0 1 Bits SCLO and SDAO are protected. #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write RS Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 SP Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 ST Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRR 8-bit register that stores the received data 0 7 read-only ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 TMOE Timeout Function Enable 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Receive data full interrupt request (IIC_RXI) is disabled. #0 1 Receive data full interrupt request (IIC_RXI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Transmit end interrupt request (IIC_TEI) is disabled. #0 1 Transmit end interrupt request (IIC_TEI) is enabled. #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 Transmit data empty interrupt request (IIC_TXI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect(This bit is read as 1.) 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 2 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 MTWP MST/TRS Write Protect 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 TMOH Timeout H Count Control 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Select 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKBT Transmit Acknowledge 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKWP ACKBT Write Protect 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 RDRFS RDRF Flag Set Timing Selection 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 SMBS SMBus/I2C Bus Selection 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 GCAE General Call Address Enable 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 HOAE Host Address Enable 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write SAR0E Slave Address Register 0 Enable 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 AAS1 Slave Address 1 Detection Flag 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS2 Slave Address 2 Detection Flag 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 GCA General Call Address Detection Flag 3 read-write 0 General call address is not detected. #0 1 General call address is detected. #1 HOA Host Address Detection Flag 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 NACKF NACK Detection Flag 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 RDRF Receive Data Full Flag 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 START Start Condition Detection Flag 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 STOP Stop Condition Detection Flag 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 TMOF Timeout Detection Flag 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 ICWUR I2C Bus Wake Up Unit Register 0x16 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 1 2 read-write WUACK ACK bit for Wakeup Mode 4 read-write 0 State of synchronous operation #0 1 State of asynchronous operation #1 WUAFA Wakeup Analog Filter Additional Selection 0 read-write 0 Do not add the wakeup analog filter #0 1 Add the wakeup analog filter. #1 WUE Wakeup Function Enable 7 read-write 0 Wakeup function disabled #0 1 Wakeup function enabled. #1 WUF Wakeup Event Occurrence Flag 5 read-write 0 Slave address does not match during wakeup function #0 1 Slave address matches during wakeup function. #1 WUIE Wakeup Interrupt Request Enable 6 read-write 0 Wakeup Interrupt Request (IIC0_WUI) disabled #0 1 Wakeup Interrupt Request (IIC0_WUI) enabled. #1 ICWUR2 I2C Bus Wake up Unit Register 2 0x17 8 read-write n 0x0 0x0 Reserved These bits are read as 11111. The write value should be 11111. 3 4 read-write WUASYF Wake-up Function Asynchronous Operation Status Flag 1 read-only 0 IIC synchronous circuit enable condition #0 1 IIC asynchronous circuit enable condition. #1 WUSEN Wake-up Function Synchronous Enable 0 read-only 0 IIC asynchronous circuit enable #0 1 IIC synchronous circuit enable #1 WUSYF Wake-up Function Synchronous Operation Status Flag 2 read-only 0 IIC asynchronous circuit enable condition #0 1 IIC synchronous circuit enable condition. #1 SARL0 Slave Address Register L%s 0xA 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL1 Slave Address Register L%s 0xC 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL2 Slave Address Register L%s 0xE 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARU0 Slave Address Register U%s 0xB 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU1 Slave Address Register U%s 0xD 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU2 Slave Address Register U%s 0xF 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write IIC1 Inter-Integrated Circuit 1 IIC1 0x0 0x0 0x10 registers n 0x10 0x4 registers n 0xB 0x6 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period(Low-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 SCLI SCL Line Monitor 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SCLO SCL Output Control/Monitor 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAI SDA Line Monitor 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 SDAO SDA Output Control/Monitor 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SOWP SCLO/SDAO Write Protect 4 read-write 0 Bits SCLO and SDAO can be written #0 1 Bits SCLO and SDAO are protected. #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write RS Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 SP Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 ST Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRR 8-bit register that stores the received data 0 7 read-only ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 TMOE Timeout Function Enable 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Receive data full interrupt request (IIC_RXI) is disabled. #0 1 Receive data full interrupt request (IIC_RXI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Transmit end interrupt request (IIC_TEI) is disabled. #0 1 Transmit end interrupt request (IIC_TEI) is enabled. #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 Transmit data empty interrupt request (IIC_TXI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect(This bit is read as 1.) 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 2 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 MTWP MST/TRS Write Protect 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 TMOH Timeout H Count Control 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Select 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKBT Transmit Acknowledge 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKWP ACKBT Write Protect 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 RDRFS RDRF Flag Set Timing Selection 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 SMBS SMBus/I2C Bus Selection 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 GCAE General Call Address Enable 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 HOAE Host Address Enable 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write SAR0E Slave Address Register 0 Enable 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 AAS1 Slave Address 1 Detection Flag 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS2 Slave Address 2 Detection Flag 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 GCA General Call Address Detection Flag 3 read-write 0 General call address is not detected. #0 1 General call address is detected. #1 HOA Host Address Detection Flag 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 NACKF NACK Detection Flag 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 RDRF Receive Data Full Flag 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 START Start Condition Detection Flag 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 STOP Stop Condition Detection Flag 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 TMOF Timeout Detection Flag 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 SARL0 Slave Address Register L%s 0xA 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL1 Slave Address Register L%s 0xC 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL2 Slave Address Register L%s 0xE 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARU0 Slave Address Register U%s 0xB 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU1 Slave Address Register U%s 0xD 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU2 Slave Address Register U%s 0xF 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write IIC2 Inter-Integrated Circuit 2 IIC1 0x0 0x0 0x10 registers n 0x10 0x4 registers n 0xB 0x6 registers n ICBRH I2C Bus Bit Rate High-Level Register 0x11 8 read-write n 0x0 0x0 BRH Bit Rate High-Level Period(High-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICBRL I2C Bus Bit Rate Low-Level Register 0x10 8 read-write n 0x0 0x0 BRL Bit Rate Low-Level Period(Low-level period of SCL clock) 0 4 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write ICCR1 I2C Bus Control Register 1 0x0 8 read-write n 0x0 0x0 CLO Extra SCL Clock Cycle Output 5 read-write 0 Does not output an extra SCL clock cycle. #0 1 Outputs an extra SCL clock cycle. #1 ICE I2C Bus Interface Enable 7 read-write 0 Disable (SCLn and SDAn pins in inactive state) #0 1 Enable (SCLn and SDAn pins in active state) #1 IICRST I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 6 read-write 0 Releases the RIIC reset or internal reset. #0 1 Initiates the RIIC reset or internal reset. #1 SCLI SCL Line Monitor 1 read-only 0 SCLn line is low. #0 1 SCLn line is high. #1 SCLO SCL Output Control/Monitor 3 read-write 0 (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. #0 1 (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. #1 SDAI SDA Line Monitor 0 read-only 0 SDAn line is low. #0 1 SDAn line is high. #1 SDAO SDA Output Control/Monitor 2 read-write 0 (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. #0 1 (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. #1 SOWP SCLO/SDAO Write Protect 4 read-write 0 Bits SCLO and SDAO can be written #0 1 Bits SCLO and SDAO are protected. #1 ICCR2 I2C Bus Control Register 2 0x1 8 read-write n 0x0 0x0 BBSY Bus Busy Detection Flag 7 read-only 0 The I2C bus is released (bus free state). #0 1 The I2C bus is occupied (bus busy state). #1 MST Master/Slave Mode 6 read-write 0 Slave mode #0 1 Master mode #1 Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write RS Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition. 2 read-write 0 Does not request to issue a restart condition. #0 1 Requests to issue a restart condition. #1 SP Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued. 3 read-write 0 Does not request to issue a stop condition. #0 1 Requests to issue a stop condition. #1 ST Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state). 1 read-write 0 Does not request to issue a start condition. #0 1 Requests to issue a start condition. #1 TRS Transmit/Receive Mode 5 read-write 0 Receive mode #0 1 Transmit mode #1 ICDRR I2C Bus Receive Data Register 0x13 8 read-only n 0x0 0x0 ICDRR 8-bit register that stores the received data 0 7 read-only ICDRT I2C Bus Transmit Data Register 0x12 8 read-write n 0x0 0x0 ICDRT 8-bit read-write register that stores transmit data. 0 7 read-write ICFER I2C Bus Function Enable Register 0x5 8 read-write n 0x0 0x0 MALE Master Arbitration-Lost Detection Enable 1 read-write 0 Master arbitration-lost detection is disabled. #0 1 Master arbitration-lost detection is enabled. #1 NACKE NACK Reception Transfer Suspension Enable 4 read-write 0 Transfer operation is not suspended during NACK reception (transfer suspension disabled). #0 1 Transfer operation is suspended during NACK reception (transfer suspension enabled). #1 NALE NACK Transmission Arbitration-Lost Detection Enable 2 read-write 0 NACK transmission arbitration-lost detection is disabled. #0 1 NACK transmission arbitration-lost detection is enabled. #1 NFE Digital Noise Filter Circuit Enable 5 read-write 0 No digital noise filter circuit is used. #0 1 A digital noise filter circuit is used. #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write SALE Slave Arbitration-Lost Detection Enable 3 read-write 0 Slave arbitration-lost detection is disabled. #0 1 Slave arbitration-lost detection is enabled. #1 SCLE SCL Synchronous Circuit Enable 6 read-write 0 No SCL synchronous circuit is used. #0 1 An SCL synchronous circuit is used. #1 TMOE Timeout Function Enable 0 read-write 0 The timeout function is disabled. #0 1 The timeout function is enabled. #1 ICIER I2C Bus Interrupt Enable Register 0x7 8 read-write n 0x0 0x0 ALIE Arbitration-Lost Interrupt Request Enable 1 read-write 0 Arbitration-lost interrupt request (ALI) is disabled. #0 1 Arbitration-lost interrupt request (ALI) is enabled. #1 NAKIE NACK Reception Interrupt Request Enable 4 read-write 0 NACK reception interrupt request (NAKI) is disabled. #0 1 NACK reception interrupt request (NAKI) is enabled. #1 RIE Receive Data Full Interrupt Request Enable 5 read-write 0 Receive data full interrupt request (IIC_RXI) is disabled. #0 1 Receive data full interrupt request (IIC_RXI) is enabled. #1 SPIE Stop Condition Detection Interrupt Request Enable 3 read-write 0 Stop condition detection interrupt request (SPI) is disabled. #0 1 Stop condition detection interrupt request (SPI) is enabled. #1 STIE Start Condition Detection Interrupt Request Enable 2 read-write 0 Start condition detection interrupt request (STI) is disabled. #0 1 Start condition detection interrupt request (STI) is enabled. #1 TEIE Transmit End Interrupt Request Enable 6 read-write 0 Transmit end interrupt request (IIC_TEI) is disabled. #0 1 Transmit end interrupt request (IIC_TEI) is enabled. #1 TIE Transmit Data Empty Interrupt Request Enable 7 read-write 0 Transmit data empty interrupt request (IIC_TXI) is disabled. #0 1 Transmit data empty interrupt request (IIC_TXI) is enabled. #1 TMOIE Timeout Interrupt Request Enable 0 read-write 0 Timeout interrupt request (TMOI) is disabled. #0 1 Timeout interrupt request (TMOI) is enabled. #1 ICMR1 I2C Bus Mode Register 1 0x2 8 read-write n 0x0 0x0 BC Bit Counter 0 2 read-write 000 9 bits #000 001 2 bits #001 010 3 bits #010 011 4 bits #011 100 5 bits #100 101 6 bits #101 110 7 bits #110 111 8 bits #111 BCWP BC Write Protect(This bit is read as 1.) 3 write-only 0 Enables a value to be written in the BC[2:0] bits. #0 1 Disables a value to be written in the BC[2:0] bits. #1 CKS Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS ) 4 2 read-write 000 PCLKB/1 clock #000 001 PCLKB/2 clock #001 010 PCLKB/4 clock #010 011 PCLKB/8 clock #011 100 PCLKB/16 clock #100 101 PCLKB/32 clock #101 110 PCLKB/64 clock #110 111 PCLKB/128 clock #111 MTWP MST/TRS Write Protect 7 read-write 0 Disables writing to the MST and TRS bits in ICCR2. #0 1 Enables writing to the MST and TRS bits in ICCR2. #1 ICMR2 I2C Bus Mode Register 2 0x3 8 read-write n 0x0 0x0 DLCS SDA Output Delay Clock Source Select 7 read-write 0 The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter. #0 1 The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter. #1 Reserved This bit is read as 0. The write value should be 0. 3 read-write SDDL SDA Output Delay Counter 4 2 read-write 000 No output delay #000 001 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles (ICMR2.DLCS=1) #001 010 2 fIIC cycles (ICMR2.DLCS=0) / 3 or 4 fIIC cycles (ICMR2.DLCS=1) #010 011 3 fIIC cycles (ICMR2.DLCS=0) / 5 or 6 fIIC cycles (ICMR2.DLCS=1) #011 100 4 fIIC cycles (ICMR2.DLCS=0) / 7 or 8 fIIC cycles (ICMR2.DLCS=1) #100 101 5 fIIC cycles (ICMR2.DLCS=0) / 9 or 10 fIIC cycles (ICMR2.DLCS=1) #101 110 6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1) #110 111 7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1) #111 TMOH Timeout H Count Control 2 read-write 0 Count is disabled while the SCLn line is at a high level. #0 1 Count is enabled while the SCLn line is at a high level. #1 TMOL Timeout L Count Control 1 read-write 0 Count is disabled while the SCLn line is at a low level. #0 1 Count is enabled while the SCLn line is at a low level. #1 TMOS Timeout Detection Time Select 0 read-write 0 Long mode is selected. #0 1 Short mode is selected. #1 ICMR3 I2C Bus Mode Register 3 0x4 8 read-write n 0x0 0x0 ACKBR Receive Acknowledge 2 read-only 0 A 0 is received as the acknowledge bit (ACK reception). #0 1 A 1 is received as the acknowledge bit (NACK reception). #1 ACKBT Transmit Acknowledge 3 read-write 0 A 0 is sent as the acknowledge bit (ACK transmission). #0 1 A 1 is sent as the acknowledge bit (NACK transmission). #1 ACKWP ACKBT Write Protect 4 read-write 0 Modification of the ACKBT bit is disabled. #0 1 Modification of the ACKBT bit is enabled. #1 NF Noise Filter Stage Selection 0 1 read-write 00 Noise of up to one fIIC cycle is filtered out (single-stage filter). #00 01 Noise of up to two fIIC cycles is filtered out (2-stage filter). #01 10 Noise of up to three fIIC cycles is filtered out (3-stage filter). #10 11 Noise of up to four fIIC cycles is filtered out (4-stage filter) #11 RDRFS RDRF Flag Set Timing Selection 5 read-write 0 The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.) #0 1 The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.) #1 SMBS SMBus/I2C Bus Selection 7 read-write 0 The I2C bus is selected. #0 1 The SMBus is selected. #1 WAIT WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand. 6 read-write 0 No WAIT (The period between ninth clock cycle and first clock cycle is not held low.) #0 1 WAIT (The period between ninth clock cycle and first clock cycle is held low.) #1 ICSER I2C Bus Status Enable Register 0x6 8 read-write n 0x0 0x0 DIDE Device-ID Address Detection Enable 5 read-write 0 Device-ID address detection is disabled. #0 1 Device-ID address detection is enabled. #1 GCAE General Call Address Enable 3 read-write 0 General call address detection is disabled. #0 1 General call address detection is enabled. #1 HOAE Host Address Enable 7 read-write 0 Host address detection is disabled. #0 1 Host address detection is enabled. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write SAR0E Slave Address Register 0 Enable 0 read-write 0 Slave address in SARL0 and SARU0 is disabled. #0 1 Slave address in SARL0 and SARU0 is enabled. #1 SAR1E Slave Address Register 1 Enable 1 read-write 0 Slave address in SARL1 and SARU1 is disabled. #0 1 Slave address in SARL1 and SARU1 is enabled. #1 SAR2E Slave Address Register 2 Enable 2 read-write 0 Slave address in SARL2 and SARU2 is disabled. #0 1 Slave address in SARL2 and SARU2 is enabled #1 ICSR1 I2C Bus Status Register 1 0x8 8 read-write n 0x0 0x0 AAS0 Slave Address 0 Detection Flag 0 read-write zeroToClear modify 0 Slave address 0 is not detected. #0 1 Slave address 0 is detected. #1 AAS1 Slave Address 1 Detection Flag 1 read-write zeroToClear modify 0 Slave address 1 is not detected. #0 1 Slave address 1 is detected. #1 AAS2 Slave Address 2 Detection Flag 2 read-write zeroToClear modify 0 Slave address 2 is not detected. #0 1 Slave address 2 is detected #1 DID Device-ID Address Detection Flag 5 read-write 0 Device-ID command is not detected. #0 1 Device-ID command is detected. #1 GCA General Call Address Detection Flag 3 read-write 0 General call address is not detected. #0 1 General call address is detected. #1 HOA Host Address Detection Flag 7 read-write zeroToClear modify 0 Host address is not detected. #0 1 Host address is detected. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write ICSR2 I2C Bus Status Register 2 0x9 8 read-write n 0x0 0x0 AL Arbitration-Lost Flag 1 read-write zeroToClear modify 0 Arbitration is not lost. #0 1 Arbitration is lost. #1 NACKF NACK Detection Flag 4 read-write zeroToClear modify 0 NACK is not detected. #0 1 NACK is detected. #1 RDRF Receive Data Full Flag 5 read-write zeroToClear modify 0 ICDRR contains no receive data. #0 1 ICDRR contains receive data. #1 START Start Condition Detection Flag 2 read-write zeroToClear modify 0 Start condition is not detected. #0 1 Start condition is detected. #1 STOP Stop Condition Detection Flag 3 read-write zeroToClear modify 0 Stop condition is not detected. #0 1 Stop condition is detected. #1 TDRE Transmit Data Empty Flag 7 read-only 0 ICDRT contains transmit data. #0 1 ICDRT contains no transmit data. #1 TEND Transmit End Flag 6 read-write zeroToClear modify 0 Data is being transmitted. #0 1 Data has been transmitted. #1 TMOF Timeout Detection Flag 0 read-write zeroToClear modify 0 Timeout is not detected. #0 1 Timeout is detected. #1 SARL0 Slave Address Register L%s 0xA 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL1 Slave Address Register L%s 0xC 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARL2 Slave Address Register L%s 0xE 8 read-write n 0x0 0x0 SVA A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9,SVA8,SVA[7:0] } 0 7 read-write SARU0 Slave Address Register U%s 0xB 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU1 Slave Address Register U%s 0xD 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write SARU2 Slave Address Register U%s 0xF 8 read-write n 0x0 0x0 FS 7-Bit/10-Bit Address Format Selection 0 read-write 0 The 7-bit address format is selected. #0 1 The 10-bit address format is selected. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SVA8 10-Bit Address(bit8) 1 read-write SVA9 10-Bit Address(bit9) 2 read-write IWDT Independent Watchdog Timer IWDT 0x0 0x0 0x1 registers n 0x4 0x2 registers n IWDTRR IWDT Refresh Register 0x0 8 read-write n 0x0 0x0 IWDTRR The counter is refreshed by writing 0x00 and then writing 0xFF to this register. 0 7 read-write IWDTSR IWDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Counter ValueValue counted by the counter 0 13 read-only REFEF Refresh Error Flag 15 read-write zeroToClear modify 0 Refresh error not occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write zeroToClear modify 0 Underflow not occurred #0 1 Underflow occurred #1 KINT Key Interrupt Function KINT 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n KRCTL KEY Return Control Register 0x0 8 read-write n 0x0 0x0 KREG Detection Edge Selection (KRF0 to KRF7) 0 read-write 0 Falling edge #0 1 Rising edge #1 KRMD Usage of Key Interrupt Flags(KR0 to KR7) 7 read-write 0 Do not use key interrupt flags #0 1 Use key interrupt flags. #1 Reserved These bits are read as 000000. The write value should be 000000. 1 5 read-write KRF KEY Return Flag Register 0x4 8 read-write n 0x0 0x0 zeroToClear modify KRF0 Key interrupt flag 0 0 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF1 Key interrupt flag 1 1 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF2 Key interrupt flag 2 2 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF3 Key interrupt flag 3 3 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF4 Key interrupt flag 4 4 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF5 Key interrupt flag 5 5 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF6 Key interrupt flag 6 6 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRF7 Key interrupt flag 7 7 read-write zeroToClear modify 0 No interrupt detected #0 1 Interrupt detected. #1 KRM KEY Return Mode Register 0x8 8 read-write n 0x0 0x0 KRM0 Key interrupt mode control 0 0 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM1 Key interrupt mode control 1 1 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM2 Key interrupt mode control 2 2 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM3 Key interrupt mode control 3 3 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM4 Key interrupt mode control 4 4 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM5 Key interrupt mode control 5 5 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM6 Key interrupt mode control 6 6 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 KRM7 Key interrupt mode control 7 7 read-write 0 Does not detect key interrupt signal #0 1 Detect key interrupt signal. #1 MMF Memory Mirror Function MMF 0x0 0x0 0x8 registers n MMEN MemMirror Enable Register 0x4 32 read-write n 0x0 0x0 EN Memory Mirror Function Enable 0 read-write 0 Memory Mirror Function is disabled. #0 1 Memory Mirror Function is enabled. #1 KEY MMEN Key Code 24 7 write-only others Writing to the EN bit is invalid. 0xDB Writing to the EN bit is valid, when the KEY bits are written 0xDB. 0xDB Reserved These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000. 1 22 read-write MMSFR MemMirror Special Function Register 0x0 32 read-write n 0x0 0x0 KEY MMSFR Key Code 24 7 write-only others Writing to the MEMMIRADDR bits are invalid. 0xDB Writing to the MEMMIRADDR bits are valid, when the KEY bits are written 0xDB. 0xDB MEMMIRADDR Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0. 7 15 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write Reserved This bit is read as 0. The write value should be 0. 23 read-write MMPU Bus Master MPU MMPU 0x0 0x0 0x2 registers n 0x102 0x2 registers n 0x200 0x100 registers n 0x204 0x100 registers n 0x208 0x100 registers n MMPUACA0 Group A Region %s Access Control Register 0x200 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA1 Group A Region %s Access Control Register 0x210 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA10 Group A Region %s Access Control Register 0x2A0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA11 Group A Region %s Access Control Register 0x2B0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA12 Group A Region %s Access Control Register 0x2C0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA13 Group A Region %s Access Control Register 0x2D0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA14 Group A Region %s Access Control Register 0x2E0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA15 Group A Region %s Access Control Register 0x2F0 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA2 Group A Region %s Access Control Register 0x220 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA3 Group A Region %s Access Control Register 0x230 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA4 Group A Region %s Access Control Register 0x240 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA5 Group A Region %s Access Control Register 0x250 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA6 Group A Region %s Access Control Register 0x260 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA7 Group A Region %s Access Control Register 0x270 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA8 Group A Region %s Access Control Register 0x280 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUACA9 Group A Region %s Access Control Register 0x290 16 read-write n 0x0 0x0 ENABLE Region enable 0 read-write 0 Group m Region n unit is disabled #0 1 Group m Region n unit is enabled #1 Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write RP Read protection 1 read-write 0 Read permission #0 1 Read protection #1 WP Write protection 2 read-write 0 Write permission #0 1 Write protection #1 MMPUCTLA Bus Master MPU Control Register A 0x0 16 read-write n 0x0 0x0 ENABLE Master Group enable 0 read-write 0 Master Group A disabled #0 1 Master Group A enabled. #1 KEY Key CodeThese bits are used to enable or disable writing of the OAD and ENABLE bit. 8 7 write-only OAD Operation after detection 1 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write MMPUEA0 Group A Region %s End Address Register 0x208 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA1 Group A Region %s End Address Register 0x218 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA10 Group A Region %s End Address Register 0x2A8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA11 Group A Region %s End Address Register 0x2B8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA12 Group A Region %s End Address Register 0x2C8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA13 Group A Region %s End Address Register 0x2D8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA14 Group A Region %s End Address Register 0x2E8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA15 Group A Region %s End Address Register 0x2F8 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA2 Group A Region %s End Address Register 0x228 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA3 Group A Region %s End Address Register 0x238 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA4 Group A Region %s End Address Register 0x248 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA5 Group A Region %s End Address Register 0x258 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA6 Group A Region %s End Address Register 0x268 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA7 Group A Region %s End Address Register 0x278 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA8 Group A Region %s End Address Register 0x288 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUEA9 Group A Region %s End Address Register 0x298 32 read-write n 0x0 0x0 MMPUEA Region end address registerAddress where the region end, for use in region determination.NOTE: The low-order 2 bits are fixed to 1. 0 31 read-write MMPUPTA Group A Protection of Register 0x102 16 read-write n 0x0 0x0 KEY Write Keyword The data written to these bits are not stored. 8 7 write-only others Writing to the PROTECT bit is invalid. 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 PROTECT Protection of register(MMPUSAn, MMPUEAn and MMPUACAn) 0 read-write 0 All Bus Master MPU Group A register writing is possible. #0 1 All Bus Master MPU Group A register writing is protected. Read is possible. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MMPUSA0 Group A Region %s Start Address Register 0x204 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA1 Group A Region %s Start Address Register 0x214 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA10 Group A Region %s Start Address Register 0x2A4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA11 Group A Region %s Start Address Register 0x2B4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA12 Group A Region %s Start Address Register 0x2C4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA13 Group A Region %s Start Address Register 0x2D4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA14 Group A Region %s Start Address Register 0x2E4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA15 Group A Region %s Start Address Register 0x2F4 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA2 Group A Region %s Start Address Register 0x224 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA3 Group A Region %s Start Address Register 0x234 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA4 Group A Region %s Start Address Register 0x244 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA5 Group A Region %s Start Address Register 0x254 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA6 Group A Region %s Start Address Register 0x264 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA7 Group A Region %s Start Address Register 0x274 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA8 Group A Region %s Start Address Register 0x284 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MMPUSA9 Group A Region %s Start Address Register 0x294 32 read-write n 0x0 0x0 MMPUSA Address where the region starts, for use in region determination.NOTE: The low-order 2 bits are fixed to 0. 0 31 read-write MSTP Module Stop Control B,C,D MSTP 0x0 0x0 0xC registers n MSTPCRB Module Stop Control Register B 0x0 32 read-write n 0x0 0x0 MSTPB11 Universal Serial Bus 2.0 FS Interface Module Stop 11 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB18 Serial Peripheral Interface 1 Module Stop 18 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB19 Serial Peripheral Interface 0 Module Stop 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB2 Controller Area Network Module Stop 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB22 Serial Communication Interface 9 Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB27 Serial Communication Interface 4 Module Stop 27 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB28 Serial Communication Interface 3 Module Stop 28 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB29 Serial Communication Interface 2 Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB30 Serial Communication Interface 1 Module Stop 30 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB31 Serial Communication Interface 0 Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB6 Queued Serial Peripheral Interface Module Stop 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB7 I2C Bus Interface 2 Module Stop 7 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB8 I2C Bus Interface 1 Module Stop 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPB9 I2C Bus Interface 0 Module Stop 9 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111. The write value should be 111. 3 2 read-write Reserved These bits are read as 11. The write value should be 11. 20 1 read-write Reserved These bits are read as 111111. The write value should be 111111. 12 5 read-write Reserved This bit is read as 1. The write value should be 1. 10 read-write Reserved These bits are read as 111. The write value should be 111. 3 2 read-write Reserved These bits are read as 111. The write value should be 111. 3 2 read-write MSTPCRC Module Stop Control Register C 0x4 32 read-write n 0x0 0x0 MSTPC0 Clock Frequency Accuracy Measurement Circuit Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC1 Cyclic Redundancy Check Calculator Module Stop 1 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC12 Secure Digital Host Interface/Multi Media Card Interface ModuleStop 12 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC13 Data Operation Circuit Module Stop 13 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC14 Event Link Controller Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC3 Capacitive Touch Sensing Unit Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC31 TSIP Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC4 Segment LCD Controller Module Stop 4 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPC8 Synchronous Serial Interface 0 Module Stop 8 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111. The write value should be 111. 5 2 read-write Reserved These bits are read as 111. The write value should be 111. 9 2 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write Reserved These bits are read as 111. The write value should be 111. 5 2 read-write MSTPCRD Module Stop Control Register D 0x8 32 read-write n 0x0 0x0 MSTPD14 Port Output Enable for GPT Module Stop 14 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD16 14-Bit A/D Converter Module Stop 16 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD19 8-bit D/A Converter Module Stop 19 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD2 Asynchronous General Purpose Timer 1 Module Stop 2 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD20 12-Bit D/A Converter Module Stop 20 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD29 Low-Power Analog Comparator Module Stop 29 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD3 Asynchronous General Purpose Timer 0 Module Stop 3 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD31 Operational Amplifier Module Stop 31 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD5 General PWM Timer 323 to 320 Module Stop 5 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPD6 General PWM Timer 169 to 164 Module Stop 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved This bit is read as 1. The write value should be 1. 4 read-write Reserved These bits are read as 11111111. The write value should be 11111111. 21 7 read-write Reserved These bits are read as 11. The write value should be 11. 17 1 read-write Reserved This bit is read as 1. The write value should be 1. 15 read-write Reserved These bits are read as 1111111. The write value should be 1111111. 7 6 read-write Reserved This bit is read as 1. The write value should be 1. 4 read-write Reserved This bit is read as 1. The write value should be 1. 4 read-write OPAMP OperationalAmplifier OPAMP 0x0 0x8 0x5 registers n AMPC Operational amplifier control register 0xB 8 read-write n 0x0 0x0 AMPE0 Operation control of operational amplifier(UNIT0) 0 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for AGT is enabled. #1 AMPE1 Operation control of operational amplifier(UNIT1) 1 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 AMPE2 Operation control of operational amplifier(UNIT2) 2 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 AMPE3 Operation control of operational amplifier(UNIT3) 3 read-write 0 Operation amplifier is stopped. #0 1 Software trigger mode: Operation of operational amplifier is enabled Operation of the operational amplifier reference current circuit is also enabled regardless of the IREFE bit se An activation trigger mode or An activation and A/D trigger mode: Wait for An activation is enabled. #1 IREFE Operation control of operational amplifier reference current circuit 7 read-write 0 Operational amplifier reference current circuit is stopped. #0 1 Operation of operational amplifier reference current circuit is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 4 2 read-write AMPMC Operational amplifier mode control register 0x8 8 read-write n 0x0 0x0 AMPPC0 Operational amplifier precharge control status 0 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC1 Operational amplifier precharge control status 1 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC2 Operational amplifier precharge control status 2 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPPC3 Operational amplifier precharge control status 3 read-write 0 Precharging is stopped. #0 1 Precharging is enabled. #1 AMPSP Operation mode selection 7 read-write 0 Low-power mode (low-speed). #0 1 High-speed mode. #1 Reserved These bits are read as 000. The write value should be 000. 4 2 read-write AMPMON Operational amplifier monitor register 0xC 8 read-only n 0x0 0x0 AMPMON0 Operational amplifier status(UNIT0) 0 read-only 0 Operational amplifier 0 is stopped. #0 1 Operational amplifier 0 is operating. #1 AMPMON1 Operational amplifier status(UNIT1) 1 read-only 0 Operational amplifier 1 is stopped. #0 1 Operational amplifier 1 is operating. #1 AMPMON2 Operational amplifier status(UNIT2) 2 read-only 0 Operational amplifier 2 is stopped. #0 1 Operational amplifier 2 is operating. #1 AMPMON3 Operational amplifier status(UNIT3) 3 read-only 0 Operational amplifier 3 is stopped. #0 1 Operational amplifier 3 is operating. #1 Reserved These bits are read as 0000. 4 3 read-only AMPTRM Operational amplifier trigger mode control register 0x9 8 read-write n 0x0 0x0 AMPTRM00 Operational amplifier function activation/stop trigger control 0 read-write 0 Software trigger mode(AMPTRM01=0)/Setting prohibited(AMPTRM01=1). #0 1 An activation trigger mode(AMPTRM01=0)/An activation and A/D trigger mode(AMPTRM01=1). #1 AMPTRM01 Operational amplifier function activation/stop trigger control 1 read-write 0 Software trigger mode(AMPTRM00=0)/An activation trigger mode(AMPTRM00=1). #0 1 Setting prohibited(AMPTRM00=0)/An activation and A/D trigger mode(AMPTRM00=1). #1 AMPTRM10 Operational amplifier function activation/stop trigger control 2 read-write 0 Software trigger mode(AMPTRM11=0)/Setting prohibited(AMPTRM11=1). #0 1 An activation trigger mode(AMPTRM11=0)/An activation and A/D trigger mode(AMPTRM11=1). #1 AMPTRM11 Operational amplifier function activation/stop trigger control 3 read-write 0 Software trigger mode(AMPTRM10=0)/An activation trigger mode(AMPTRM10=1). #0 1 Setting prohibited(AMPTRM10=0)/An activation and A/D trigger mode(AMPTRM10=1). #1 AMPTRM20 Operational amplifier function activation/stop trigger control 4 read-write 0 Software trigger mode(AMPTRM21=0)/Setting prohibited(AMPTRM21=1). #0 1 An activation trigger mode(AMPTRM21=0)/An activation and A/D trigger mode(AMPTRM21=1). #1 AMPTRM21 Operational amplifier function activation/stop trigger control 5 read-write 0 Software trigger mode(AMPTRM20=0)/An activation trigger mode(AMPTRM20=1). #0 1 Setting prohibited(AMPTRM20=0)/An activation and A/D trigger mode(AMPTRM20=1). #1 AMPTRM30 Operational amplifier function activation/stop trigger control 6 read-write 0 Software trigger mode(AMPTRM31=0)/Setting prohibited(AMPTRM31=1). #0 1 An activation trigger mode(AMPTRM31=0)/An activation and A/D trigger mode(AMPTRM31=1). #1 AMPTRM31 Operational amplifier function activation/stop trigger control 7 read-write 0 Software trigger mode(AMPTRM30=0)/An activation trigger mode(AMPTRM30=1). #0 1 Setting prohibited(AMPTRM30=0)/An activation and A/D trigger mode(AMPTRM30=1). #1 AMPTRS Operational Amplifier Activation Trigger Select Register 0xA 8 read-write n 0x0 0x0 AMPTRS ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register. 0 1 read-write 00 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 1.Operational amplifier 2: Operational amplifier An activation trigger 2.Operational amplifier 3: Operational amplifier An activation trigger 3 #00 01 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 1.Operational amplifier 3: Operational amplifier An activation trigger 1 #01 10 Setting prohibited #10 11 Operational amplifier 0: Operational amplifier An activation trigger 0.Operational amplifier 1: Operational amplifier An activation trigger 0.Operational amplifier 2: Operational amplifier An activation trigger 0.Operational amplifier 3: Operational amplifier An activation trigger 0 #11 PFS Pmn Pin Function Control Register PFS 0x0 0x0 0x4 registers n 0x100 0x20 registers n 0x102 0x20 registers n 0x103 0x20 registers n 0x120 0x4 registers n 0x122 0x2 registers n 0x123 0x5 registers n 0x126 0x2 registers n 0x127 0x19 registers n 0x12A 0x18 registers n 0x12B 0x18 registers n 0x140 0x20 registers n 0x142 0x20 registers n 0x143 0x20 registers n 0x16C 0x8 registers n 0x16E 0x8 registers n 0x16F 0x8 registers n 0x180 0x1C registers n 0x182 0x1C registers n 0x183 0x1C registers n 0x1A0 0x8 registers n 0x1A2 0x8 registers n 0x1A3 0x8 registers n 0x1A8 0x14 registers n 0x1AA 0x14 registers n 0x1AB 0x14 registers n 0x1C0 0x18 registers n 0x1C2 0x18 registers n 0x1C3 0x18 registers n 0x1E0 0x8 registers n 0x1E2 0x8 registers n 0x1E3 0x8 registers n 0x1E8 0x10 registers n 0x1EA 0x10 registers n 0x1EB 0x10 registers n 0x2 0x2 registers n 0x200 0x28 registers n 0x202 0x28 registers n 0x203 0x28 registers n 0x240 0xC registers n 0x242 0xC registers n 0x243 0xC registers n 0x278 0x8 registers n 0x27A 0x8 registers n 0x27B 0x8 registers n 0x28 0x18 registers n 0x2A 0x18 registers n 0x2B 0x18 registers n 0x3 0x25 registers n 0x40 0x20 registers n 0x42 0x20 registers n 0x43 0x20 registers n 0x6 0x24 registers n 0x60 0x4 registers n 0x62 0x2 registers n 0x63 0x5 registers n 0x66 0x2 registers n 0x67 0x5 registers n 0x6A 0x2 registers n 0x6B 0x15 registers n 0x6E 0x14 registers n 0x6F 0x14 registers n 0x7 0x24 registers n 0x80 0x4 registers n 0x82 0x2 registers n 0x83 0x5 registers n 0x86 0x2 registers n 0x87 0x15 registers n 0x8A 0x14 registers n 0x8B 0x14 registers n 0xB0 0x10 registers n 0xB2 0x10 registers n 0xB3 0x10 registers n 0xC0 0x4 registers n 0xC2 0x2 registers n 0xC3 0x25 registers n 0xC6 0x24 registers n 0xC7 0x24 registers n 0xE8 0x18 registers n 0xEA 0x18 registers n 0xEB 0x18 registers n P000PFS P000 Pin Function Control Register 0x0 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function SelectThese bits select the peripheral function. For individual pin functions, see the MPC table 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P000PFS_BY P000 Pin Function Control Register P000PFS 0x3 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P000PFS_HA P000 Pin Function Control Register P000PFS 0x2 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P001PFS P00%s Pin Function Control Register 0x8 32 read-write n 0x0 0x0 P001PFS_BY P00%s Pin Function Control Register P00%sPFS 0xE 8 read-write n 0x0 0x0 P001PFS_HA P00%s Pin Function Control Register P00%sPFS 0xC 16 read-write n 0x0 0x0 P002PFS P00%s Pin Function Control Register 0x10 32 read-write n 0x0 0x0 P002PFS_BY P00%s Pin Function Control Register P00%sPFS 0x19 8 read-write n 0x0 0x0 P002PFS_HA P00%s Pin Function Control Register P00%sPFS 0x16 16 read-write n 0x0 0x0 P003PFS P00%s Pin Function Control Register 0x1C 32 read-write n 0x0 0x0 P003PFS_BY P00%s Pin Function Control Register P00%sPFS 0x28 8 read-write n 0x0 0x0 P003PFS_HA P00%s Pin Function Control Register P00%sPFS 0x24 16 read-write n 0x0 0x0 P004PFS P00%s Pin Function Control Register 0x2C 32 read-write n 0x0 0x0 P004PFS_BY P00%s Pin Function Control Register P00%sPFS 0x3B 8 read-write n 0x0 0x0 P004PFS_HA P00%s Pin Function Control Register P00%sPFS 0x36 16 read-write n 0x0 0x0 P005PFS P00%s Pin Function Control Register 0x40 32 read-write n 0x0 0x0 P005PFS_BY P00%s Pin Function Control Register P00%sPFS 0x52 8 read-write n 0x0 0x0 P005PFS_HA P00%s Pin Function Control Register P00%sPFS 0x4C 16 read-write n 0x0 0x0 P006PFS P00%s Pin Function Control Register 0x58 32 read-write n 0x0 0x0 P006PFS_BY P00%s Pin Function Control Register P00%sPFS 0x6D 8 read-write n 0x0 0x0 P006PFS_HA P00%s Pin Function Control Register P00%sPFS 0x66 16 read-write n 0x0 0x0 P007PFS P00%s Pin Function Control Register 0x74 32 read-write n 0x0 0x0 P007PFS_BY P00%s Pin Function Control Register P00%sPFS 0x8C 8 read-write n 0x0 0x0 P007PFS_HA P00%s Pin Function Control Register P00%sPFS 0x84 16 read-write n 0x0 0x0 P008PFS P00%s Pin Function Control Register 0x94 32 read-write n 0x0 0x0 P008PFS_BY P00%s Pin Function Control Register P00%sPFS 0xAF 8 read-write n 0x0 0x0 P008PFS_HA P00%s Pin Function Control Register P00%sPFS 0xA6 16 read-write n 0x0 0x0 P009PFS P00%s Pin Function Control Register 0xB8 32 read-write n 0x0 0x0 P009PFS_BY P00%s Pin Function Control Register P00%sPFS 0xD6 8 read-write n 0x0 0x0 P009PFS_HA P00%s Pin Function Control Register P00%sPFS 0xCC 16 read-write n 0x0 0x0 P010PFS P0%s Pin Function Control Register 0x50 32 read-write n 0x0 0x0 P010PFS_BY P0%s Pin Function Control Register P0%sPFS 0x56 8 read-write n 0x0 0x0 P010PFS_HA P0%s Pin Function Control Register P0%sPFS 0x54 16 read-write n 0x0 0x0 P011PFS P0%s Pin Function Control Register 0x7C 32 read-write n 0x0 0x0 P011PFS_BY P0%s Pin Function Control Register P0%sPFS 0x85 8 read-write n 0x0 0x0 P011PFS_HA P0%s Pin Function Control Register P0%sPFS 0x82 16 read-write n 0x0 0x0 P012PFS P0%s Pin Function Control Register 0xAC 32 read-write n 0x0 0x0 P012PFS_BY P0%s Pin Function Control Register P0%sPFS 0xB8 8 read-write n 0x0 0x0 P012PFS_HA P0%s Pin Function Control Register P0%sPFS 0xB4 16 read-write n 0x0 0x0 P013PFS P0%s Pin Function Control Register 0xE0 32 read-write n 0x0 0x0 P013PFS_BY P0%s Pin Function Control Register P0%sPFS 0xEF 8 read-write n 0x0 0x0 P013PFS_HA P0%s Pin Function Control Register P0%sPFS 0xEA 16 read-write n 0x0 0x0 P014PFS P0%s Pin Function Control Register 0x118 32 read-write n 0x0 0x0 P014PFS_BY P0%s Pin Function Control Register P0%sPFS 0x12A 8 read-write n 0x0 0x0 P014PFS_HA P0%s Pin Function Control Register P0%sPFS 0x124 16 read-write n 0x0 0x0 P015PFS P0%s Pin Function Control Register 0x154 32 read-write n 0x0 0x0 P015PFS_BY P0%s Pin Function Control Register P0%sPFS 0x169 8 read-write n 0x0 0x0 P015PFS_HA P0%s Pin Function Control Register P0%sPFS 0x162 16 read-write n 0x0 0x0 P100PFS P10%s Pin Function Control Register 0x80 32 read-write n 0x0 0x0 P100PFS_BY P10%s Pin Function Control Register P10%sPFS 0x86 8 read-write n 0x0 0x0 P100PFS_HA P10%s Pin Function Control Register P10%sPFS 0x84 16 read-write n 0x0 0x0 P101PFS P10%s Pin Function Control Register 0xC4 32 read-write n 0x0 0x0 P101PFS_BY P10%s Pin Function Control Register P10%sPFS 0xCD 8 read-write n 0x0 0x0 P101PFS_HA P10%s Pin Function Control Register P10%sPFS 0xCA 16 read-write n 0x0 0x0 P102PFS P10%s Pin Function Control Register 0x10C 32 read-write n 0x0 0x0 P102PFS_BY P10%s Pin Function Control Register P10%sPFS 0x118 8 read-write n 0x0 0x0 P102PFS_HA P10%s Pin Function Control Register P10%sPFS 0x114 16 read-write n 0x0 0x0 P103PFS P10%s Pin Function Control Register 0x158 32 read-write n 0x0 0x0 P103PFS_BY P10%s Pin Function Control Register P10%sPFS 0x167 8 read-write n 0x0 0x0 P103PFS_HA P10%s Pin Function Control Register P10%sPFS 0x162 16 read-write n 0x0 0x0 P104PFS P10%s Pin Function Control Register 0x1A8 32 read-write n 0x0 0x0 P104PFS_BY P10%s Pin Function Control Register P10%sPFS 0x1BA 8 read-write n 0x0 0x0 P104PFS_HA P10%s Pin Function Control Register P10%sPFS 0x1B4 16 read-write n 0x0 0x0 P105PFS P10%s Pin Function Control Register 0x1FC 32 read-write n 0x0 0x0 P105PFS_BY P10%s Pin Function Control Register P10%sPFS 0x211 8 read-write n 0x0 0x0 P105PFS_HA P10%s Pin Function Control Register P10%sPFS 0x20A 16 read-write n 0x0 0x0 P106PFS P10%s Pin Function Control Register 0x254 32 read-write n 0x0 0x0 P106PFS_BY P10%s Pin Function Control Register P10%sPFS 0x26C 8 read-write n 0x0 0x0 P106PFS_HA P10%s Pin Function Control Register P10%sPFS 0x264 16 read-write n 0x0 0x0 P107PFS P10%s Pin Function Control Register 0x2B0 32 read-write n 0x0 0x0 P107PFS_BY P10%s Pin Function Control Register P10%sPFS 0x2CB 8 read-write n 0x0 0x0 P107PFS_HA P10%s Pin Function Control Register P10%sPFS 0x2C2 16 read-write n 0x0 0x0 P108PFS P108 Pin Function Control Register 0x60 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P108PFS_BY P108 Pin Function Control Register P108PFS 0x63 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P108PFS_HA P108 Pin Function Control Register P108PFS 0x62 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P109PFS P109 Pin Function Control Register 0x64 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P109PFS_BY P109 Pin Function Control Register P109PFS 0x67 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P109PFS_HA P109 Pin Function Control Register P109PFS 0x66 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Port Drive Capability 10 read-write 0 Low drive #0 1 Middle drive. #1 EOF Event on Failing 13 read-write 0 No effected #0 1 Detect failing edge #1 EOR Event on Rising 12 read-write 0 No effected #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P110PFS P110 Pin Function Control Register 0x68 32 read-write n 0x0 0x0 P110PFS_BY P110 Pin Function Control Register P110PFS 0x6B 8 read-write n 0x0 0x0 P110PFS_HA P110 Pin Function Control Register P110PFS 0x6A 16 read-write n 0x0 0x0 P111PFS P1%s Pin Function Control Register 0xD8 32 read-write n 0x0 0x0 P111PFS_BY P1%s Pin Function Control Register P1%sPFS 0xDE 8 read-write n 0x0 0x0 P111PFS_HA P1%s Pin Function Control Register P1%sPFS 0xDC 16 read-write n 0x0 0x0 P112PFS P1%s Pin Function Control Register 0x148 32 read-write n 0x0 0x0 P112PFS_BY P1%s Pin Function Control Register P1%sPFS 0x151 8 read-write n 0x0 0x0 P112PFS_HA P1%s Pin Function Control Register P1%sPFS 0x14E 16 read-write n 0x0 0x0 P113PFS P1%s Pin Function Control Register 0x1BC 32 read-write n 0x0 0x0 P113PFS_BY P1%s Pin Function Control Register P1%sPFS 0x1C8 8 read-write n 0x0 0x0 P113PFS_HA P1%s Pin Function Control Register P1%sPFS 0x1C4 16 read-write n 0x0 0x0 P114PFS P1%s Pin Function Control Register 0x234 32 read-write n 0x0 0x0 P114PFS_BY P1%s Pin Function Control Register P1%sPFS 0x243 8 read-write n 0x0 0x0 P114PFS_HA P1%s Pin Function Control Register P1%sPFS 0x23E 16 read-write n 0x0 0x0 P115PFS P1%s Pin Function Control Register 0x2B0 32 read-write n 0x0 0x0 P115PFS_BY P1%s Pin Function Control Register P1%sPFS 0x2C2 8 read-write n 0x0 0x0 P115PFS_HA P1%s Pin Function Control Register P1%sPFS 0x2BC 16 read-write n 0x0 0x0 P200PFS P200 Pin Function Control Register 0x80 32 read-write n 0x0 0x0 P200PFS_BY P200 Pin Function Control Register P200PFS 0x83 8 read-write n 0x0 0x0 P200PFS_HA P200 Pin Function Control Register P200PFS 0x82 16 read-write n 0x0 0x0 P201PFS P201 Pin Function Control Register 0x84 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 read-write 0 Low drive #0 1 High drive #1 EOF Event on Falling 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 read-write 0 Do not care #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P201PFS_BY P201 Pin Function Control Register P201PFS 0x87 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P201PFS_HA P201 Pin Function Control Register P201PFS 0x86 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 read-write 0 Low drive #0 1 High drive #1 EOF Event on Falling 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 read-write 0 Do not care #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P202PFS P20%s Pin Function Control Register 0x110 32 read-write n 0x0 0x0 P202PFS_BY P20%s Pin Function Control Register P20%sPFS 0x116 8 read-write n 0x0 0x0 P202PFS_HA P20%s Pin Function Control Register P20%sPFS 0x114 16 read-write n 0x0 0x0 P203PFS P20%s Pin Function Control Register 0x19C 32 read-write n 0x0 0x0 P203PFS_BY P20%s Pin Function Control Register P20%sPFS 0x1A5 8 read-write n 0x0 0x0 P203PFS_HA P20%s Pin Function Control Register P20%sPFS 0x1A2 16 read-write n 0x0 0x0 P204PFS P20%s Pin Function Control Register 0x22C 32 read-write n 0x0 0x0 P204PFS_BY P20%s Pin Function Control Register P20%sPFS 0x238 8 read-write n 0x0 0x0 P204PFS_HA P20%s Pin Function Control Register P20%sPFS 0x234 16 read-write n 0x0 0x0 P205PFS P20%s Pin Function Control Register 0x2C0 32 read-write n 0x0 0x0 P205PFS_BY P20%s Pin Function Control Register P20%sPFS 0x2CF 8 read-write n 0x0 0x0 P205PFS_HA P20%s Pin Function Control Register P20%sPFS 0x2CA 16 read-write n 0x0 0x0 P206PFS P20%s Pin Function Control Register 0x358 32 read-write n 0x0 0x0 P206PFS_BY P20%s Pin Function Control Register P20%sPFS 0x36A 8 read-write n 0x0 0x0 P206PFS_HA P20%s Pin Function Control Register P20%sPFS 0x364 16 read-write n 0x0 0x0 P212PFS P2%s Pin Function Control Register 0x160 32 read-write n 0x0 0x0 P212PFS_BY P2%s Pin Function Control Register P2%sPFS 0x166 8 read-write n 0x0 0x0 P212PFS_HA P2%s Pin Function Control Register P2%sPFS 0x164 16 read-write n 0x0 0x0 P213PFS P2%s Pin Function Control Register 0x214 32 read-write n 0x0 0x0 P213PFS_BY P2%s Pin Function Control Register P2%sPFS 0x21D 8 read-write n 0x0 0x0 P213PFS_HA P2%s Pin Function Control Register P2%sPFS 0x21A 16 read-write n 0x0 0x0 P214PFS P2%s Pin Function Control Register 0x2CC 32 read-write n 0x0 0x0 P214PFS_BY P2%s Pin Function Control Register P2%sPFS 0x2D8 8 read-write n 0x0 0x0 P214PFS_HA P2%s Pin Function Control Register P2%sPFS 0x2D4 16 read-write n 0x0 0x0 P215PFS P2%s Pin Function Control Register 0x388 32 read-write n 0x0 0x0 P215PFS_BY P2%s Pin Function Control Register P2%sPFS 0x397 8 read-write n 0x0 0x0 P215PFS_HA P2%s Pin Function Control Register P2%sPFS 0x392 16 read-write n 0x0 0x0 P300PFS P300 Pin Function Control Register 0xC0 32 read-write n 0x0 0x0 P300PFS_BY P300 Pin Function Control Register P300PFS 0xC3 8 read-write n 0x0 0x0 P300PFS_HA P300 Pin Function Control Register P300PFS 0xC2 16 read-write n 0x0 0x0 P301PFS P30%s Pin Function Control Register 0x188 32 read-write n 0x0 0x0 P301PFS_BY P30%s Pin Function Control Register P30%sPFS 0x18E 8 read-write n 0x0 0x0 P301PFS_HA P30%s Pin Function Control Register P30%sPFS 0x18C 16 read-write n 0x0 0x0 P302PFS P30%s Pin Function Control Register 0x250 32 read-write n 0x0 0x0 P302PFS_BY P30%s Pin Function Control Register P30%sPFS 0x259 8 read-write n 0x0 0x0 P302PFS_HA P30%s Pin Function Control Register P30%sPFS 0x256 16 read-write n 0x0 0x0 P303PFS P30%s Pin Function Control Register 0x31C 32 read-write n 0x0 0x0 P303PFS_BY P30%s Pin Function Control Register P30%sPFS 0x328 8 read-write n 0x0 0x0 P303PFS_HA P30%s Pin Function Control Register P30%sPFS 0x324 16 read-write n 0x0 0x0 P304PFS P30%s Pin Function Control Register 0x3EC 32 read-write n 0x0 0x0 P304PFS_BY P30%s Pin Function Control Register P30%sPFS 0x3FB 8 read-write n 0x0 0x0 P304PFS_HA P30%s Pin Function Control Register P30%sPFS 0x3F6 16 read-write n 0x0 0x0 P305PFS P30%s Pin Function Control Register 0x4C0 32 read-write n 0x0 0x0 P305PFS_BY P30%s Pin Function Control Register P30%sPFS 0x4D2 8 read-write n 0x0 0x0 P305PFS_HA P30%s Pin Function Control Register P30%sPFS 0x4CC 16 read-write n 0x0 0x0 P306PFS P30%s Pin Function Control Register 0x598 32 read-write n 0x0 0x0 P306PFS_BY P30%s Pin Function Control Register P30%sPFS 0x5AD 8 read-write n 0x0 0x0 P306PFS_HA P30%s Pin Function Control Register P30%sPFS 0x5A6 16 read-write n 0x0 0x0 P307PFS P30%s Pin Function Control Register 0x674 32 read-write n 0x0 0x0 P307PFS_BY P30%s Pin Function Control Register P30%sPFS 0x68C 8 read-write n 0x0 0x0 P307PFS_HA P30%s Pin Function Control Register P30%sPFS 0x684 16 read-write n 0x0 0x0 P308PFS P30%s Pin Function Control Register 0x754 32 read-write n 0x0 0x0 P308PFS_BY P30%s Pin Function Control Register P30%sPFS 0x76F 8 read-write n 0x0 0x0 P308PFS_HA P30%s Pin Function Control Register P30%sPFS 0x766 16 read-write n 0x0 0x0 P309PFS P30%s Pin Function Control Register 0x838 32 read-write n 0x0 0x0 P309PFS_BY P30%s Pin Function Control Register P30%sPFS 0x856 8 read-write n 0x0 0x0 P309PFS_HA P30%s Pin Function Control Register P30%sPFS 0x84C 16 read-write n 0x0 0x0 P310PFS P3%s Pin Function Control Register 0x1D0 32 read-write n 0x0 0x0 P310PFS_BY P3%s Pin Function Control Register P3%sPFS 0x1D6 8 read-write n 0x0 0x0 P310PFS_HA P3%s Pin Function Control Register P3%sPFS 0x1D4 16 read-write n 0x0 0x0 P311PFS P3%s Pin Function Control Register 0x2BC 32 read-write n 0x0 0x0 P311PFS_BY P3%s Pin Function Control Register P3%sPFS 0x2C5 8 read-write n 0x0 0x0 P311PFS_HA P3%s Pin Function Control Register P3%sPFS 0x2C2 16 read-write n 0x0 0x0 P312PFS P3%s Pin Function Control Register 0x3AC 32 read-write n 0x0 0x0 P312PFS_BY P3%s Pin Function Control Register P3%sPFS 0x3B8 8 read-write n 0x0 0x0 P312PFS_HA P3%s Pin Function Control Register P3%sPFS 0x3B4 16 read-write n 0x0 0x0 P313PFS P3%s Pin Function Control Register 0x4A0 32 read-write n 0x0 0x0 P313PFS_BY P3%s Pin Function Control Register P3%sPFS 0x4AF 8 read-write n 0x0 0x0 P313PFS_HA P3%s Pin Function Control Register P3%sPFS 0x4AA 16 read-write n 0x0 0x0 P314PFS P3%s Pin Function Control Register 0x598 32 read-write n 0x0 0x0 P314PFS_BY P3%s Pin Function Control Register P3%sPFS 0x5AA 8 read-write n 0x0 0x0 P314PFS_HA P3%s Pin Function Control Register P3%sPFS 0x5A4 16 read-write n 0x0 0x0 P315PFS P3%s Pin Function Control Register 0x694 32 read-write n 0x0 0x0 P315PFS_BY P3%s Pin Function Control Register P3%sPFS 0x6A9 8 read-write n 0x0 0x0 P315PFS_HA P3%s Pin Function Control Register P3%sPFS 0x6A2 16 read-write n 0x0 0x0 P400PFS P40%s Pin Function Control Register 0x200 32 read-write n 0x0 0x0 P400PFS_BY P40%s Pin Function Control Register P40%sPFS 0x206 8 read-write n 0x0 0x0 P400PFS_HA P40%s Pin Function Control Register P40%sPFS 0x204 16 read-write n 0x0 0x0 P401PFS P40%s Pin Function Control Register 0x304 32 read-write n 0x0 0x0 P401PFS_BY P40%s Pin Function Control Register P40%sPFS 0x30D 8 read-write n 0x0 0x0 P401PFS_HA P40%s Pin Function Control Register P40%sPFS 0x30A 16 read-write n 0x0 0x0 P402PFS P40%s Pin Function Control Register 0x40C 32 read-write n 0x0 0x0 P402PFS_BY P40%s Pin Function Control Register P40%sPFS 0x418 8 read-write n 0x0 0x0 P402PFS_HA P40%s Pin Function Control Register P40%sPFS 0x414 16 read-write n 0x0 0x0 P403PFS P40%s Pin Function Control Register 0x518 32 read-write n 0x0 0x0 P403PFS_BY P40%s Pin Function Control Register P40%sPFS 0x527 8 read-write n 0x0 0x0 P403PFS_HA P40%s Pin Function Control Register P40%sPFS 0x522 16 read-write n 0x0 0x0 P404PFS P40%s Pin Function Control Register 0x628 32 read-write n 0x0 0x0 P404PFS_BY P40%s Pin Function Control Register P40%sPFS 0x63A 8 read-write n 0x0 0x0 P404PFS_HA P40%s Pin Function Control Register P40%sPFS 0x634 16 read-write n 0x0 0x0 P405PFS P40%s Pin Function Control Register 0x73C 32 read-write n 0x0 0x0 P405PFS_BY P40%s Pin Function Control Register P40%sPFS 0x751 8 read-write n 0x0 0x0 P405PFS_HA P40%s Pin Function Control Register P40%sPFS 0x74A 16 read-write n 0x0 0x0 P406PFS P40%s Pin Function Control Register 0x854 32 read-write n 0x0 0x0 P406PFS_BY P40%s Pin Function Control Register P40%sPFS 0x86C 8 read-write n 0x0 0x0 P406PFS_HA P40%s Pin Function Control Register P40%sPFS 0x864 16 read-write n 0x0 0x0 P407PFS P40%s Pin Function Control Register 0x970 32 read-write n 0x0 0x0 P407PFS_BY P40%s Pin Function Control Register P40%sPFS 0x98B 8 read-write n 0x0 0x0 P407PFS_HA P40%s Pin Function Control Register P40%sPFS 0x982 16 read-write n 0x0 0x0 P408PFS P408 Pin Function Control Register 0x120 32 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 read-write 0 Low drive(DSCR1 = 0)/Middle drive for llC Fast-mode(DSCR1 = 1) #0 1 Middle drive(DSCR1 = 0)/Setting prohibited(DSCR1 = 1) #1 DSCR1 Drive Strength Control Register 11 read-write 0 Low drive(DSCR = 0)/Middle drive(DSCR = 1) #0 1 Middle drive for IIC Fast-mode(DSCR = 0)/Setting prohibited(DSCR = 1) #1 EOF Event on Falling 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 read-write 0 Do not care #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PMR Port Mode Control 16 read-write 0 Uses the pin as a general I/O pin. #0 1 Uses the pin as an I/O port for peripheral functions. #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 PSEL Port Function Select These bits select the peripheral function. For individual pin functions, see the setting table. 24 4 read-write Reserved These bits are read as 000. The write value should be 000. 29 2 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P408PFS_BY P408 Pin Function Control Register P408PFS 0x123 8 read-write n 0x0 0x0 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P408PFS_HA P408 Pin Function Control Register P408PFS 0x122 16 read-write n 0x0 0x0 ASEL Analog Input enable 15 read-write 0 Used other than as analog pin #0 1 Used as analog pin #1 DSCR Drive Strength Control Register 10 read-write 0 Low drive(DSCR1 = 0)/Middle drive for llC Fast-mode(DSCR1 = 1) #0 1 Middle drive(DSCR1 = 0)/Setting prohibited(DSCR1 = 1) #1 DSCR1 Drive Strength Control Register 11 read-write 0 Low drive(DSCR = 0)/Middle drive(DSCR = 1) #0 1 Middle drive for IIC Fast-mode(DSCR = 0)/Setting prohibited(DSCR = 1) #1 EOF Event on Falling 13 read-write 0 Do not care #0 1 Detect falling edge #1 EOR Event on Rising 12 read-write 0 Do not care #0 1 Detect rising edge #1 ISEL IRQ input enable 14 read-write 0 Not used as IRQn input pin #0 1 Used as IRQn input pin #1 NCODR N-Channel Open Drain Control 6 read-write 0 CMOS output #0 1 NMOS open-drain output #1 PCR Pull-up Control 4 read-write 0 Disables an input pull-up. #0 1 Enables an input pull-up. #1 PDR Port Direction 2 read-write 0 Input (Functions as an input pin.) #0 1 Output (Functions as an output pin.) #1 PIDR Port Input Data 1 read-only 0 Low input #0 1 High input #1 PODR Port Output Data 0 read-write 0 Low output #0 1 High output #1 Reserved These bits are read as 000. The write value should be 000. 7 2 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write P409PFS P409 Pin Function Control Register 0x124 32 read-write n 0x0 0x0 P409PFS_BY P409 Pin Function Control Register P409PFS 0x127 8 read-write n 0x0 0x0 P409PFS_HA P409 Pin Function Control Register P409PFS 0x126 16 read-write n 0x0 0x0 P410PFS P4%s Pin Function Control Register 0x250 32 read-write n 0x0 0x0 P410PFS_BY P4%s Pin Function Control Register P409PFS 0x256 8 read-write n 0x0 0x0 P410PFS_HA P4%s Pin Function Control Register P409PFS 0x254 16 read-write n 0x0 0x0 P411PFS P4%s Pin Function Control Register 0x37C 32 read-write n 0x0 0x0 P411PFS_BY P4%s Pin Function Control Register P409PFS 0x385 8 read-write n 0x0 0x0 P411PFS_HA P4%s Pin Function Control Register P409PFS 0x382 16 read-write n 0x0 0x0 P412PFS P4%s Pin Function Control Register 0x4AC 32 read-write n 0x0 0x0 P412PFS_BY P4%s Pin Function Control Register P409PFS 0x4B8 8 read-write n 0x0 0x0 P412PFS_HA P4%s Pin Function Control Register P409PFS 0x4B4 16 read-write n 0x0 0x0 P413PFS P4%s Pin Function Control Register 0x5E0 32 read-write n 0x0 0x0 P413PFS_BY P4%s Pin Function Control Register P409PFS 0x5EF 8 read-write n 0x0 0x0 P413PFS_HA P4%s Pin Function Control Register P409PFS 0x5EA 16 read-write n 0x0 0x0 P414PFS P4%s Pin Function Control Register 0x718 32 read-write n 0x0 0x0 P414PFS_BY P4%s Pin Function Control Register P409PFS 0x72A 8 read-write n 0x0 0x0 P414PFS_HA P4%s Pin Function Control Register P409PFS 0x724 16 read-write n 0x0 0x0 P415PFS P4%s Pin Function Control Register 0x854 32 read-write n 0x0 0x0 P415PFS_BY P4%s Pin Function Control Register P409PFS 0x869 8 read-write n 0x0 0x0 P415PFS_HA P4%s Pin Function Control Register P409PFS 0x862 16 read-write n 0x0 0x0 P500PFS P50%s Pin Function Control Register 0x280 32 read-write n 0x0 0x0 P500PFS_BY P50%s Pin Function Control Register P50%sPFS 0x286 8 read-write n 0x0 0x0 P500PFS_HA P50%s Pin Function Control Register P50%sPFS 0x284 16 read-write n 0x0 0x0 P501PFS P50%s Pin Function Control Register 0x3C4 32 read-write n 0x0 0x0 P501PFS_BY P50%s Pin Function Control Register P50%sPFS 0x3CD 8 read-write n 0x0 0x0 P501PFS_HA P50%s Pin Function Control Register P50%sPFS 0x3CA 16 read-write n 0x0 0x0 P502PFS P50%s Pin Function Control Register 0x50C 32 read-write n 0x0 0x0 P502PFS_BY P50%s Pin Function Control Register P50%sPFS 0x518 8 read-write n 0x0 0x0 P502PFS_HA P50%s Pin Function Control Register P50%sPFS 0x514 16 read-write n 0x0 0x0 P503PFS P50%s Pin Function Control Register 0x658 32 read-write n 0x0 0x0 P503PFS_BY P50%s Pin Function Control Register P50%sPFS 0x667 8 read-write n 0x0 0x0 P503PFS_HA P50%s Pin Function Control Register P50%sPFS 0x662 16 read-write n 0x0 0x0 P504PFS P50%s Pin Function Control Register 0x7A8 32 read-write n 0x0 0x0 P504PFS_BY P50%s Pin Function Control Register P50%sPFS 0x7BA 8 read-write n 0x0 0x0 P504PFS_HA P50%s Pin Function Control Register P50%sPFS 0x7B4 16 read-write n 0x0 0x0 P505PFS P50%s Pin Function Control Register 0x8FC 32 read-write n 0x0 0x0 P505PFS_BY P50%s Pin Function Control Register P50%sPFS 0x911 8 read-write n 0x0 0x0 P505PFS_HA P50%s Pin Function Control Register P50%sPFS 0x90A 16 read-write n 0x0 0x0 P506PFS P50%s Pin Function Control Register 0xA54 32 read-write n 0x0 0x0 P506PFS_BY P50%s Pin Function Control Register P50%sPFS 0xA6C 8 read-write n 0x0 0x0 P506PFS_HA P50%s Pin Function Control Register P50%sPFS 0xA64 16 read-write n 0x0 0x0 P507PFS P50%s Pin Function Control Register 0xBB0 32 read-write n 0x0 0x0 P507PFS_BY P50%s Pin Function Control Register P50%sPFS 0xBCB 8 read-write n 0x0 0x0 P507PFS_HA P50%s Pin Function Control Register P50%sPFS 0xBC2 16 read-write n 0x0 0x0 P511PFS P5%s Pin Function Control Register 0x2D8 32 read-write n 0x0 0x0 P511PFS_BY P5%s Pin Function Control Register P5%sPFS 0x2DE 8 read-write n 0x0 0x0 P511PFS_HA P5%s Pin Function Control Register P5%sPFS 0x2DC 16 read-write n 0x0 0x0 P512PFS P5%s Pin Function Control Register 0x448 32 read-write n 0x0 0x0 P512PFS_BY P5%s Pin Function Control Register P5%sPFS 0x451 8 read-write n 0x0 0x0 P512PFS_HA P5%s Pin Function Control Register P5%sPFS 0x44E 16 read-write n 0x0 0x0 P600PFS P60%s Pin Function Control Register 0x300 32 read-write n 0x0 0x0 P600PFS_BY P60%s Pin Function Control Register P60%sPFS 0x306 8 read-write n 0x0 0x0 P600PFS_HA P60%s Pin Function Control Register P60%sPFS 0x304 16 read-write n 0x0 0x0 P601PFS P60%s Pin Function Control Register 0x484 32 read-write n 0x0 0x0 P601PFS_BY P60%s Pin Function Control Register P60%sPFS 0x48D 8 read-write n 0x0 0x0 P601PFS_HA P60%s Pin Function Control Register P60%sPFS 0x48A 16 read-write n 0x0 0x0 P602PFS P60%s Pin Function Control Register 0x60C 32 read-write n 0x0 0x0 P602PFS_BY P60%s Pin Function Control Register P60%sPFS 0x618 8 read-write n 0x0 0x0 P602PFS_HA P60%s Pin Function Control Register P60%sPFS 0x614 16 read-write n 0x0 0x0 P603PFS P60%s Pin Function Control Register 0x798 32 read-write n 0x0 0x0 P603PFS_BY P60%s Pin Function Control Register P60%sPFS 0x7A7 8 read-write n 0x0 0x0 P603PFS_HA P60%s Pin Function Control Register P60%sPFS 0x7A2 16 read-write n 0x0 0x0 P604PFS P60%s Pin Function Control Register 0x928 32 read-write n 0x0 0x0 P604PFS_BY P60%s Pin Function Control Register P60%sPFS 0x93A 8 read-write n 0x0 0x0 P604PFS_HA P60%s Pin Function Control Register P60%sPFS 0x934 16 read-write n 0x0 0x0 P605PFS P60%s Pin Function Control Register 0xABC 32 read-write n 0x0 0x0 P605PFS_BY P60%s Pin Function Control Register P60%sPFS 0xAD1 8 read-write n 0x0 0x0 P605PFS_HA P60%s Pin Function Control Register P60%sPFS 0xACA 16 read-write n 0x0 0x0 P606PFS P60%s Pin Function Control Register 0xC54 32 read-write n 0x0 0x0 P606PFS_BY P60%s Pin Function Control Register P60%sPFS 0xC6C 8 read-write n 0x0 0x0 P606PFS_HA P60%s Pin Function Control Register P60%sPFS 0xC64 16 read-write n 0x0 0x0 P608PFS P60%s Pin Function Control Register 0x340 32 read-write n 0x0 0x0 P608PFS_BY P60%s Pin Function Control Register P60%sPFS 0x346 8 read-write n 0x0 0x0 P608PFS_HA P60%s Pin Function Control Register P60%sPFS 0x344 16 read-write n 0x0 0x0 P609PFS P60%s Pin Function Control Register 0x4E4 32 read-write n 0x0 0x0 P609PFS_BY P60%s Pin Function Control Register P60%sPFS 0x4ED 8 read-write n 0x0 0x0 P609PFS_HA P60%s Pin Function Control Register P60%sPFS 0x4EA 16 read-write n 0x0 0x0 P610PFS P6%s Pin Function Control Register 0x350 32 read-write n 0x0 0x0 P610PFS_BY P6%s Pin Function Control Register P6%sPFS 0x356 8 read-write n 0x0 0x0 P610PFS_HA P6%s Pin Function Control Register P6%sPFS 0x354 16 read-write n 0x0 0x0 P611PFS P6%s Pin Function Control Register 0x4FC 32 read-write n 0x0 0x0 P611PFS_BY P6%s Pin Function Control Register P6%sPFS 0x505 8 read-write n 0x0 0x0 P611PFS_HA P6%s Pin Function Control Register P6%sPFS 0x502 16 read-write n 0x0 0x0 P612PFS P6%s Pin Function Control Register 0x6AC 32 read-write n 0x0 0x0 P612PFS_BY P6%s Pin Function Control Register P6%sPFS 0x6B8 8 read-write n 0x0 0x0 P612PFS_HA P6%s Pin Function Control Register P6%sPFS 0x6B4 16 read-write n 0x0 0x0 P613PFS P6%s Pin Function Control Register 0x860 32 read-write n 0x0 0x0 P613PFS_BY P6%s Pin Function Control Register P6%sPFS 0x86F 8 read-write n 0x0 0x0 P613PFS_HA P6%s Pin Function Control Register P6%sPFS 0x86A 16 read-write n 0x0 0x0 P614PFS P6%s Pin Function Control Register 0xA18 32 read-write n 0x0 0x0 P614PFS_BY P6%s Pin Function Control Register P6%sPFS 0xA2A 8 read-write n 0x0 0x0 P614PFS_HA P6%s Pin Function Control Register P6%sPFS 0xA24 16 read-write n 0x0 0x0 P700PFS P70%s Pin Function Control Register 0x380 32 read-write n 0x0 0x0 P700PFS_BY P70%s Pin Function Control Register P70%sPFS 0x386 8 read-write n 0x0 0x0 P700PFS_HA P70%s Pin Function Control Register P70%sPFS 0x384 16 read-write n 0x0 0x0 P701PFS P70%s Pin Function Control Register 0x544 32 read-write n 0x0 0x0 P701PFS_BY P70%s Pin Function Control Register P70%sPFS 0x54D 8 read-write n 0x0 0x0 P701PFS_HA P70%s Pin Function Control Register P70%sPFS 0x54A 16 read-write n 0x0 0x0 P702PFS P70%s Pin Function Control Register 0x70C 32 read-write n 0x0 0x0 P702PFS_BY P70%s Pin Function Control Register P70%sPFS 0x718 8 read-write n 0x0 0x0 P702PFS_HA P70%s Pin Function Control Register P70%sPFS 0x714 16 read-write n 0x0 0x0 P703PFS P70%s Pin Function Control Register 0x8D8 32 read-write n 0x0 0x0 P703PFS_BY P70%s Pin Function Control Register P70%sPFS 0x8E7 8 read-write n 0x0 0x0 P703PFS_HA P70%s Pin Function Control Register P70%sPFS 0x8E2 16 read-write n 0x0 0x0 P704PFS P70%s Pin Function Control Register 0xAA8 32 read-write n 0x0 0x0 P704PFS_BY P70%s Pin Function Control Register P70%sPFS 0xABA 8 read-write n 0x0 0x0 P704PFS_HA P70%s Pin Function Control Register P70%sPFS 0xAB4 16 read-write n 0x0 0x0 P705PFS P70%s Pin Function Control Register 0xC7C 32 read-write n 0x0 0x0 P705PFS_BY P70%s Pin Function Control Register P70%sPFS 0xC91 8 read-write n 0x0 0x0 P705PFS_HA P70%s Pin Function Control Register P70%sPFS 0xC8A 16 read-write n 0x0 0x0 P708PFS P70%s Pin Function Control Register 0x3C0 32 read-write n 0x0 0x0 P708PFS_BY P70%s Pin Function Control Register P70%sPFS 0x3C6 8 read-write n 0x0 0x0 P708PFS_HA P70%s Pin Function Control Register P70%sPFS 0x3C4 16 read-write n 0x0 0x0 P709PFS P70%s Pin Function Control Register 0x5A4 32 read-write n 0x0 0x0 P709PFS_BY P70%s Pin Function Control Register P70%sPFS 0x5AD 8 read-write n 0x0 0x0 P709PFS_HA P70%s Pin Function Control Register P70%sPFS 0x5AA 16 read-write n 0x0 0x0 P710PFS P7%s Pin Function Control Register 0x3D0 32 read-write n 0x0 0x0 P710PFS_BY P7%s Pin Function Control Register P7%sPFS 0x3D6 8 read-write n 0x0 0x0 P710PFS_HA P7%s Pin Function Control Register P7%sPFS 0x3D4 16 read-write n 0x0 0x0 P711PFS P7%s Pin Function Control Register 0x5BC 32 read-write n 0x0 0x0 P711PFS_BY P7%s Pin Function Control Register P7%sPFS 0x5C5 8 read-write n 0x0 0x0 P711PFS_HA P7%s Pin Function Control Register P7%sPFS 0x5C2 16 read-write n 0x0 0x0 P712PFS P7%s Pin Function Control Register 0x7AC 32 read-write n 0x0 0x0 P712PFS_BY P7%s Pin Function Control Register P7%sPFS 0x7B8 8 read-write n 0x0 0x0 P712PFS_HA P7%s Pin Function Control Register P7%sPFS 0x7B4 16 read-write n 0x0 0x0 P713PFS P7%s Pin Function Control Register 0x9A0 32 read-write n 0x0 0x0 P713PFS_BY P7%s Pin Function Control Register P7%sPFS 0x9AF 8 read-write n 0x0 0x0 P713PFS_HA P7%s Pin Function Control Register P7%sPFS 0x9AA 16 read-write n 0x0 0x0 P800PFS P80%s Pin Function Control Register 0x400 32 read-write n 0x0 0x0 P800PFS_BY P80%s Pin Function Control Register P80%sPFS 0x406 8 read-write n 0x0 0x0 P800PFS_HA P80%s Pin Function Control Register P80%sPFS 0x404 16 read-write n 0x0 0x0 P801PFS P80%s Pin Function Control Register 0x604 32 read-write n 0x0 0x0 P801PFS_BY P80%s Pin Function Control Register P80%sPFS 0x60D 8 read-write n 0x0 0x0 P801PFS_HA P80%s Pin Function Control Register P80%sPFS 0x60A 16 read-write n 0x0 0x0 P802PFS P80%s Pin Function Control Register 0x80C 32 read-write n 0x0 0x0 P802PFS_BY P80%s Pin Function Control Register P80%sPFS 0x818 8 read-write n 0x0 0x0 P802PFS_HA P80%s Pin Function Control Register P80%sPFS 0x814 16 read-write n 0x0 0x0 P803PFS P80%s Pin Function Control Register 0xA18 32 read-write n 0x0 0x0 P803PFS_BY P80%s Pin Function Control Register P80%sPFS 0xA27 8 read-write n 0x0 0x0 P803PFS_HA P80%s Pin Function Control Register P80%sPFS 0xA22 16 read-write n 0x0 0x0 P804PFS P80%s Pin Function Control Register 0xC28 32 read-write n 0x0 0x0 P804PFS_BY P80%s Pin Function Control Register P80%sPFS 0xC3A 8 read-write n 0x0 0x0 P804PFS_HA P80%s Pin Function Control Register P80%sPFS 0xC34 16 read-write n 0x0 0x0 P805PFS P80%s Pin Function Control Register 0xE3C 32 read-write n 0x0 0x0 P805PFS_BY P80%s Pin Function Control Register P80%sPFS 0xE51 8 read-write n 0x0 0x0 P805PFS_HA P80%s Pin Function Control Register P80%sPFS 0xE4A 16 read-write n 0x0 0x0 P806PFS P80%s Pin Function Control Register 0x1054 32 read-write n 0x0 0x0 P806PFS_BY P80%s Pin Function Control Register P80%sPFS 0x106C 8 read-write n 0x0 0x0 P806PFS_HA P80%s Pin Function Control Register P80%sPFS 0x1064 16 read-write n 0x0 0x0 P807PFS P80%s Pin Function Control Register 0x1270 32 read-write n 0x0 0x0 P807PFS_BY P80%s Pin Function Control Register P80%sPFS 0x128B 8 read-write n 0x0 0x0 P807PFS_HA P80%s Pin Function Control Register P80%sPFS 0x1282 16 read-write n 0x0 0x0 P808PFS P80%s Pin Function Control Register 0x1490 32 read-write n 0x0 0x0 P808PFS_BY P80%s Pin Function Control Register P80%sPFS 0x14AE 8 read-write n 0x0 0x0 P808PFS_HA P80%s Pin Function Control Register P80%sPFS 0x14A4 16 read-write n 0x0 0x0 P809PFS P80%s Pin Function Control Register 0x16B4 32 read-write n 0x0 0x0 P809PFS_BY P80%s Pin Function Control Register P80%sPFS 0x16D5 8 read-write n 0x0 0x0 P809PFS_HA P80%s Pin Function Control Register P80%sPFS 0x16CA 16 read-write n 0x0 0x0 P900PFS P90%s Pin Function Control Register 0x480 32 read-write n 0x0 0x0 P900PFS_BY P90%s Pin Function Control Register P90%sPFS 0x486 8 read-write n 0x0 0x0 P900PFS_HA P90%s Pin Function Control Register P90%sPFS 0x484 16 read-write n 0x0 0x0 P901PFS P90%s Pin Function Control Register 0x6C4 32 read-write n 0x0 0x0 P901PFS_BY P90%s Pin Function Control Register P90%sPFS 0x6CD 8 read-write n 0x0 0x0 P901PFS_HA P90%s Pin Function Control Register P90%sPFS 0x6CA 16 read-write n 0x0 0x0 P902PFS P90%s Pin Function Control Register 0x90C 32 read-write n 0x0 0x0 P902PFS_BY P90%s Pin Function Control Register P90%sPFS 0x918 8 read-write n 0x0 0x0 P902PFS_HA P90%s Pin Function Control Register P90%sPFS 0x914 16 read-write n 0x0 0x0 P914PFS P9%s Pin Function Control Register 0x4F0 32 read-write n 0x0 0x0 P914PFS_BY P9%s Pin Function Control Register P9%sPFS 0x4F6 8 read-write n 0x0 0x0 P914PFS_HA P9%s Pin Function Control Register P9%sPFS 0x4F4 16 read-write n 0x0 0x0 P915PFS P9%s Pin Function Control Register 0x76C 32 read-write n 0x0 0x0 P915PFS_BY P9%s Pin Function Control Register P9%sPFS 0x775 8 read-write n 0x0 0x0 P915PFS_HA P9%s Pin Function Control Register P9%sPFS 0x772 16 read-write n 0x0 0x0 PMISC Miscellaneous Port Control Register PMISC 0x0 0x0 0x4 registers n PWPR Write-Protect Register 0x3 8 read-write n 0x0 0x0 B0WI PFSWE Bit Write Disable 7 read-write 0 Writing to the PFSWE bit is enabled #0 1 Writing to the PFSWE bit is disabled #1 PFSWE PFS Register Write Enable 6 read-write 0 Writing to the PFS register is disabled #0 1 Writing to the PFS register is enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 0 5 read-write POEG Port Output Enable Module for GPT POEG 0x0 0x0 0x200 registers n 0x0 0x200 registers n POEGGA POEG Group %s Setting Register 0x0 32 read-write n 0x0 0x0 INV GTETRG Input Reverse 28 read-write 0 GTETRG Input #0 1 GTETRG Input Reversed. #1 IOCE Output-disable Request Enable from GPTNote: Can be modified only once after a reset. 5 read-write 0 Output-disable request from the GPT disable request disabled #0 1 Output-disable request from the GPT disable request enabled. #1 IOCF Output-disable Request Detection Flag from GPT 1 read-write zeroToClear modify 0 No output-disable request from the GPT disable request has occurred #0 1 Output-disable request from the GPT disable request occurred. #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sampling GTETRG pin input level for three times in every PCLKB. #00 01 Sampling GTETRG pin input level for three times in every PCLKB /8. #01 10 Sampling GTETRG pin input level for three times in every PCLKB /32. #10 11 Sampling GTETRG pin input level for three times in every PCLKB /128. #11 NFEN Noise Filter Enable 29 read-write 0 Filtering noise disabled #0 1 Filtering noise enabled #1 OSTPE Oscillation Stop Detection EnableNote: Can be modified only once after a reset. 6 read-write 0 A output-disable request from the oscillation stop detection disabled. #0 1 A output-disable request from the oscillation stop detection enabled. #1 OSTPF Oscillation Stop Detection Flag 2 read-write zeroToClear modify 0 No output-disable request from oscillation stop detection has occurred #0 1 Output-disable request from oscillation stop detection occurred. #1 PIDE Port Input Detection EnableNote: Can be modified only once after a reset. 4 read-write 0 Output-disable request from the GTETRG pins disabled #0 1 Output-disable request from the GTETRG pins enabled. #1 PIDF Port Input Detection Flag 0 read-write zeroToClear modify 0 No output-disable request from the GTETRGn pin has occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 17 10 read-write SSF Software Stop Flag 3 read-write 0 No output-disable request from software has occurred #0 1 Output-disable request from software occurred. #1 ST GTETRG Input Status Flag 16 read-only 0 GTETRG input after filtering is 0. #0 1 GTETRG input after filtering is 1. #1 POEGGB POEG Group %s Setting Register 0x100 32 read-write n 0x0 0x0 INV GTETRG Input Reverse 28 read-write 0 GTETRG Input #0 1 GTETRG Input Reversed. #1 IOCE Output-disable Request Enable from GPTNote: Can be modified only once after a reset. 5 read-write 0 Output-disable request from the GPT disable request disabled #0 1 Output-disable request from the GPT disable request enabled. #1 IOCF Output-disable Request Detection Flag from GPT 1 read-write zeroToClear modify 0 No output-disable request from the GPT disable request has occurred #0 1 Output-disable request from the GPT disable request occurred. #1 NFCS Noise Filter Clock Select 30 1 read-write 00 Sampling GTETRG pin input level for three times in every PCLKB. #00 01 Sampling GTETRG pin input level for three times in every PCLKB /8. #01 10 Sampling GTETRG pin input level for three times in every PCLKB /32. #10 11 Sampling GTETRG pin input level for three times in every PCLKB /128. #11 NFEN Noise Filter Enable 29 read-write 0 Filtering noise disabled #0 1 Filtering noise enabled #1 OSTPE Oscillation Stop Detection EnableNote: Can be modified only once after a reset. 6 read-write 0 A output-disable request from the oscillation stop detection disabled. #0 1 A output-disable request from the oscillation stop detection enabled. #1 OSTPF Oscillation Stop Detection Flag 2 read-write zeroToClear modify 0 No output-disable request from oscillation stop detection has occurred #0 1 Output-disable request from oscillation stop detection occurred. #1 PIDE Port Input Detection EnableNote: Can be modified only once after a reset. 4 read-write 0 Output-disable request from the GTETRG pins disabled #0 1 Output-disable request from the GTETRG pins enabled. #1 PIDF Port Input Detection Flag 0 read-write zeroToClear modify 0 No output-disable request from the GTETRGn pin has occurred #0 1 Output-disable request from the GTETRGn pin occurred. #1 Reserved These bits are read as 00000000000. The write value should be 00000000000. 17 10 read-write SSF Software Stop Flag 3 read-write 0 No output-disable request from software has occurred #0 1 Output-disable request from software occurred. #1 ST GTETRG Input Status Flag 16 read-only 0 GTETRG input after filtering is 0. #0 1 GTETRG input after filtering is 1. #1 PORT0 Port 0 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT1 Port 1 Control Registers PORT1 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x4 0x8 registers n 0x8 0x8 registers n 0xC 0x4 registers n EIDR Event input data register PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EORR Event output set register PCNTR4 0xC 16 read-write n 0x0 0x0 EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR Pmn Event Output Reset 16 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output set register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT2 Port 2 Control Registers PORT1 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x4 0x8 registers n 0x8 0x8 registers n 0xC 0x4 registers n EIDR Event input data register PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EORR Event output set register PCNTR4 0xC 16 read-write n 0x0 0x0 EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR Pmn Event Output Reset 16 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output set register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT3 Port 3 Control Registers PORT1 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x4 0x8 registers n 0x8 0x8 registers n 0xC 0x4 registers n EIDR Event input data register PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EORR Event output set register PCNTR4 0xC 16 read-write n 0x0 0x0 EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR Pmn Event Output Reset 16 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output set register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT4 Port 4 Control Registers PORT1 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x4 0x8 registers n 0x8 0x8 registers n 0xC 0x4 registers n EIDR Event input data register PCNTR2 0x4 16 read-only n 0x0 0x0 EIDR Pmn Event Input Data 0 15 read-only 0 Low input #0 1 High input. #1 EORR Event output set register PCNTR4 0xC 16 read-write n 0x0 0x0 EORR Pmn Event Output Reset 0 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Event output reset register PCNTR4 0xE 16 read-write n 0x0 0x0 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PCNTR4 Port Control Register 4 0xC 32 read-write n 0x0 0x0 EORR Pmn Event Output Reset 16 15 read-write 0 No affect to output #0 1 Low output #1 EOSR Pmn Event Output Set 0 15 read-write 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output set register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output reset register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT5 Port 5 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT6 Port 6 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT7 Port 7 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT8 Port 8 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PORT9 Port 9 Control Registers PORT0 0x0 0x0 0x4 registers n 0x0 0x8 registers n 0x6 0x6 registers n 0x8 0x4 registers n PCNTR1 Port Control Register 1 0x0 32 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PODR Pmn Output Data 16 15 read-write 0 Low output #0 1 High output. #1 PCNTR2 Port Control Register 2 0x4 32 read-only n 0x0 0x0 EIDR Pmn Event Input Data 16 15 read-only 0 Low input #0 1 High input. #1 PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PCNTR3 Port Control Register 3 0x8 32 write-only n 0x0 0x0 PORR Pmn Output Reset 16 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 PDR Data direction register PCNTR1 0x2 16 read-write n 0x0 0x0 PDR Pmn Direction 0 15 read-write 0 Input (functions as an input pin) #0 1 Output (functions as an output pin). #1 PIDR Input data register PCNTR2 0x6 16 read-only n 0x0 0x0 uint32_t PIDR Pmn Input Data 0 15 read-only 0 Low input #0 1 High input. #1 PODR Output data register PCNTR1 0x0 16 read-write n 0x0 0x0 PODR Pmn Output Data 0 15 read-write 0 Low output #0 1 High output. #1 PORR Output reset register PCNTR3 0x8 16 write-only n 0x0 0x0 PORR Pmn Output Reset 0 15 write-only 0 No affect to output #0 1 Low output. #1 POSR Output set register PCNTR3 0xA 16 write-only n 0x0 0x0 POSR Pmn Output Set 0 15 write-only 0 No affect to output #0 1 High output. #1 QSPI Quad-SPI QSPI 0x0 0x0 0x1C registers n 0x20 0xC registers n 0x30 0x8 registers n 0x4C 0x4 registers n 0x800 0xC registers n SFMCMD Communication Mode Control Register 0x14 32 read-write n 0x0 0x0 DCOM Selection of a mode of communication with the SPI bus 0 read-write 0 ROM access mode #0 1 Direct communication mode #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMCNT1 External QSPI Address Register 1 0x804 32 read-write n 0x0 0x0 QSPI_EXT BANK Switching AddressWhen accessing from 0x6000_0000 to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. 26 5 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 16 9 read-write Reserved These bits are read as 0000000000. The write value should be 0000000000. 16 9 read-write SFMCOM Communication Port Register 0x10 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMD Port for direct communication with the SPI bus.Input/output to and from this port is converted to an SPI bus cycle. This port is accessible in the direct communication mode (DCOM=1) only.Access to this port is ignored in the ROM access mode. 0 7 read-write SFMCST Communication Status Register 0x18 32 read-write n 0x0 0x0 COMBSY SPI bus cycle completion state in direct communication 0 read-only 0 There is no serial transfer being processed. #0 1 There is a serial transfer being processed. #1 EROMR Status of ROM access detection in the direct communication modeNOTE: Writing of 0 only is possible. Writing of 1 is ignored. 7 read-only 0 ROM access is not detected in direct communication mode #0 1 ROM access is detected in direct communication mode #1 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write SFMPMD Port Control Register 0x34 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write Reserved These bits are read as 0000000000000. The write value should be 0000000000000. 3 12 read-write SFMWPL Specify level of WP pin 2 read-write 0 Low level #0 1 High level #1 SFMSAC Address Mode Control Register 0x24 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write SFM4BC Selection of a default instruction code, when Serial Interface address width is selected 4 bytes. 4 read-write 0 Does not use 4 Byte address read Instruction code #0 1 Use 4 Byte address read Instruction code #1 SFMAS Selection the number of address bits of the serial interface 0 1 read-write 00 1byte #00 01 2bytes #01 10 3bytes #10 11 4 bytes #11 SFMSDC Dummy Cycle Control Register 0x28 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMDN Selection of the number of dummy cycles of Fast Read instructions 0 3 read-write 0000 Default dummy cycles of each instruction. #0000 SFMXD Mode data for serial ROM. (Control XIP mode) 8 7 read-write 0 XIP mode is prohibited #0 1 XIP mode is permitted #1 SFMXEN XIP mode permission 7 read-write 0 XIP mode is prohibited #0 1 XIP mode is permitted #1 SFMXST XIP mode status 6 read-only 0 Normal (non-XIP) mode is operating #0 1 XIP mode is operating #1 SFMSIC Instruction Code Register 0x20 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMCIC Serial ROM instruction code to substitute 0 7 read-write SFMSKC Clock Control Register 0x8 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMDTY Selection of a duty ratio correction function for the SCK signal 5 read-write 0 Serial interface reference cycle selection (* Pay attention to the irregularity.) #0 1 Delays the rising of the SCK signal by 0.5*PCLKA.(* Valid with PCLKA multiplied by an odd number) #1 SFMDV Serial interface reference cycle selection (* Pay attention to the irregularity.)NOTE: When PCLKA multiplied by an odd number is selected, the high-level width of the SCK signal is longer than the low-level width by 1 x PCLKA before duty ratio correction. 0 4 read-write 10000 18 x PCLKA #10000 10001 20 x PCLKA #10001 10010 22 x PCLKA #10010 10011 24 x PCLKA #10011 10100 26 x PCLKA #10100 10101 28 x PCLKA #10101 10110 30 x PCLKA #10110 10111 32 x PCLKA #10111 11000 34 x PCLKA #11000 11001 36 x PCLKA #11001 11010 38 x PCLKA #11010 11011 40 x PCLKA #11011 11100 42 x PCLKA #11100 11101 44 x PCLKA #11101 11110 46 x PCLKA #11110 11111 48 x PCLKA #11111 SFMSMD Transfer Mode Control Register 0x0 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 000. The write value should be 000. 12 2 read-write Reserved These bits are read as 000. The write value should be 000. 12 2 read-write SFMCCE Read instruction code selection. 15 read-write 0 Default instruction code set for each instruction #0 1 Instruction code written in the SFMSIC register #1 SFMMD3 SPI mode selection. An initial value is determined by input to CFGMD3. 8 read-write 0 SPI mode 0 #0 1 SPI mode 3 #1 SFMOEX Extension of the I/O buffer output enable signal for the serial interface 9 read-write 0 Does not extend the output enable signal #0 1 Extends the output enable signal by 1*QSPCLK #1 SFMOHW Hold time adjustment for serial transmission 10 read-write 0 Does not extend the high-level width of SCK at transmission time #0 1 Extends the high-level width of SCK by 1*PCLKA at transmission time #1 SFMOSW Setup time adjustment for serial transmission 11 read-write 0 Does not extend the low-level width of SCK at transmission time #0 1 Extends the low-level width of SCK by 1*PCLKA at transmission time #1 SFMPAE Selection of the function for stopping prefetch at locations other than on byte boundaries 7 read-write 0 Disables prefetch stopping at locations other than on byte boundaries #0 1 Enables prefetch stopping at locations other than on byte boundaries #1 SFMPFE Selection of the prefetch function 6 read-write 0 Disables prefetch #0 1 Enables prefetch #1 SFMRM Serial interface read mode selection 0 2 read-write 000 Standard Read #000 001 Fast Read #001 010 Fast Read Dual Output #010 011 Fast Read Dual I/O #011 100 Fast Read Quad Output #100 101 Fast Read Quad I/O #101 110 Setting prohibited #110 111 Setting prohibited #111 SFMSE Selection of the prefetch function 4 1 read-write 00 Does not extend QSSL #00 01 Extends QSSL by 33*QSPCLK #01 10 Extends QSSL by 129*QSPCLK #10 11 Extends QSSL infinitely #11 SFMSPC SPI Protocol Control Register 0x30 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write Reserved These bits are read as 00000000000. The write value should be 00000000000. 5 10 read-write SFMSDE Selection of the minimum time of input output switch, when Dual SPI protocol or Quad SPI protocol is selected. 4 read-write 0 Does not allocate minimum switch time #0 1 Allocate the minimum switch time equivalent to 1*QSPXLK #1 SFMSPI Selection of SPI protocolNOTE: Serial ROM's SPI protocol is required to be set by software separately. 0 1 read-write 00 Extended SPI protocol #00 01 Dual SPI protocol #01 10 Quad SPI protocol #10 11 Setting prohibited. #11 SFMSSC Chip Selection Control Register 0x4 32 read-write n 0x0 0x0 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write SFMSHD QSSL signal release timing selection 4 read-write 0 Releases QSSL 0.5*SCK after the last rising edge of QSPCLK #0 1 Releases QSSL 1.5*SCK after the last rising edge of QSPCLK #1 SFMSLD QSSL signal output timing selection 5 read-write 0 Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK #0 1 Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK #1 SFMSW Selection of a minimum high-level width of the QSSL signal 0 3 read-write 0000 1 x QSPCLK #0000 0001 2 x QSPCLK #0001 0010 3 x QSPCLK #0010 0011 4 x QSPCLK #0011 0100 5 x QSPCLK #0100 0101 6 x QSPCLK #0101 0110 7 x QSPCLK #0110 0111 8 x QSPCLK #0111 1000 9 x QSPCLK #1000 1001 10 x QSPCLK #1001 1010 11 x QSPCLK #1010 1011 12 x QSPCLK #1011 1100 13 x QSPCLK #1100 1101 14 x QSPCLK #1101 1110 15 x QSPCLK #1110 1111 16 x QSPCLK #1111 SFMSST Status Register 0xC 32 read-only n 0x0 0x0 PFCNT Number of bytes of prefetched dataRange: 00000 - 10010 (No combination other than the above is available.) 0 4 read-only 00000 Nodata has been prefetched. #00000 PFFUL Prefetch buffer state 6 read-only 0 The prefetch buffer has a free space. #0 1 The prefetch buffer is full. #1 PFOFF Prefetch function operation state 7 read-only 0 The prefetch function is operating. #0 1 The prefetch function is not enabled or is not operating. #1 Reserved These bits are read as 0000000000000000. 16 15 read-only Reserved These bits are read as 00000000. 8 7 read-only Reserved These bits are read as 00000000. 8 7 read-only RTC Realtime Clock RTC 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x12 0x1 registers n 0x14 0x1 registers n 0x16 0x1 registers n 0x18 0x1 registers n 0x1A 0x1 registers n 0x1C 0x2 registers n 0x1C 0x3 registers n 0x1E 0x1 registers n 0x2 0x1 registers n 0x22 0x1 registers n 0x24 0x1 registers n 0x28 0x1 registers n 0x2A 0x5 registers n 0x4 0x1 registers n 0x40 0x6 registers n 0x52 0x30 registers n 0x54 0x30 registers n 0x56 0x30 registers n 0x5A 0x30 registers n 0x5C 0x30 registers n 0x6 0x1 registers n 0x8 0x1 registers n 0xA 0x1 registers n 0xC 0x1 registers n 0xE 0x3 registers n BCNT0 Binary Counter 0 RSECCNT 0x2 8 read-write n 0x0 0x0 BCNT0 The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0. 0 7 read-write BCNT0AER Binary Counter 0 Alarm Enable Register RDAYAR 0x18 8 read-write n 0x0 0x0 ENB The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0. 0 7 read-write BCNT0AR Binary Counter 0 Alarm Register RSECAR 0x10 8 read-write n 0x0 0x0 BCNT0AR he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0. 0 7 read-write BCNT0CP0 BCNT0 Capture Register %s RSECCP%s 0x52 8 read-only n 0x0 0x0 BCNT0CP BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. 0 7 read-only BCNT0CP1 BCNT0 Capture Register %s RSECCP%s 0x62 8 read-only n 0x0 0x0 BCNT0CP BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. 0 7 read-only BCNT0CP2 BCNT0 Capture Register %s RSECCP%s 0x72 8 read-only n 0x0 0x0 BCNT0CP BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected. 0 7 read-only BCNT1 Binary Counter 1 RMINCNT 0x4 8 read-write n 0x0 0x0 BCNT1 The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8. 0 7 read-write BCNT1AER Binary Counter 1 Alarm Enable Register RMONAR 0x1A 8 read-write n 0x0 0x0 ENB The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8. 0 7 read-write BCNT1AR Binary Counter 1 Alarm Register RMINAR 0x12 8 read-write n 0x0 0x0 BCNT1AR he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8. 0 7 read-write BCNT1CP0 BCNT1 Capture Register %s RMINCP%s 0x54 8 read-only n 0x0 0x0 BCNT1CP BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. 0 7 read-only BCNT1CP1 BCNT1 Capture Register %s RMINCP%s 0x64 8 read-only n 0x0 0x0 BCNT1CP BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. 0 7 read-only BCNT1CP2 BCNT1 Capture Register %s RMINCP%s 0x74 8 read-only n 0x0 0x0 BCNT1CP BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected. 0 7 read-only BCNT2 Binary Counter 2 RHRCNT 0x6 8 read-write n 0x0 0x0 BCNT2 The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write BCNT2AER Binary Counter 2 Alarm Enable Register RYRAR 0x1C 16 read-write n 0x0 0x0 ENB The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16. 0 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write BCNT2AR Binary Counter 2 Alarm Register RHRAR 0x14 8 read-write n 0x0 0x0 BCNT2AR The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16. 0 7 read-write BCNT2CP0 BCNT2 Capture Register %s RHRCP%s 0x56 8 read-only n 0x0 0x0 BCNT2CP BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. 0 7 read-only BCNT2CP1 BCNT2 Capture Register %s RHRCP%s 0x66 8 read-only n 0x0 0x0 BCNT2CP BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. 0 7 read-only BCNT2CP2 BCNT2 Capture Register %s RHRCP%s 0x76 8 read-only n 0x0 0x0 BCNT2CP BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected. 0 7 read-only BCNT3 Binary Counter 3 RWKCNT 0x8 8 read-write n 0x0 0x0 BCNT3 The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write BCNT3AER Binary Counter 3 Alarm Enable Register RYRAREN 0x1E 8 read-write n 0x0 0x0 ENB The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24. 0 7 read-write BCNT3AR Binary Counter 3 Alarm Register RWKAR 0x16 8 read-write n 0x0 0x0 BCNT3AR The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24. 0 7 read-write BCNT3CP0 BCNT3 Capture Register %s RDAYCP%s 0x5A 8 read-only n 0x0 0x0 BCNT3CP BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. 0 7 read-only BCNT3CP1 BCNT3 Capture Register %s RDAYCP%s 0x6A 8 read-only n 0x0 0x0 BCNT3CP BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. 0 7 read-only BCNT3CP2 BCNT3 Capture Register %s RDAYCP%s 0x7A 8 read-only n 0x0 0x0 BCNT3CP BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected. 0 7 read-only R64CNT 64-Hz Counter 0x0 8 read-only n 0x0 0x0 F16HZ 16Hz 2 read-only F1HZ 1Hz 6 read-only F2HZ 2Hz 5 read-only F32HZ 32Hz 1 read-only F4HZ 4Hz 4 read-only F64HZ 64Hz 0 read-only F8HZ 8Hz 3 read-only RADJ Time Error Adjustment Register 0x2E 8 read-write n 0x0 0x0 ADJ Adjustment Value These bits specify the adjustment value from the prescaler. 0 5 read-write PMADJ Plus-Minus 6 1 read-write 00 Adjustment is not performed. #00 01 Adjustment is performed by the addition to the prescaler. #01 10 Adjustment is performed by the subtraction from the prescaler. #10 11 Setting prohibited #11 RCR1 RTC Control Register 1 0x22 8 read-write n 0x0 0x0 AIE Alarm Interrupt Enable 0 read-write 0 An alarm interrupt request is disabled. #0 1 An alarm interrupt request is enabled. #1 CIE Carry Interrupt Enable 1 read-write 0 A carry interrupt request is disabled. #0 1 A carry interrupt request is enabled. #1 PES Periodic Interrupt Select 4 3 read-write others No periodic interrupts are generated. 0110 A periodic interrupt is generated every 1/256 second((RCR4.RCKSEL = 0)./A periodic interrupt is generated every 1/128 second((RCR4.RCKSEL = 1). #0110 0111 A periodic interrupt is generated every 1/128 second. #0111 1000 A periodic interrupt is generated every 1/64 second. #1000 1001 A periodic interrupt is generated every 1/32 second. #1001 1010 A periodic interrupt is generated every 1/16 second. #1010 1011 A periodic interrupt is generated every 1/8 second. #1011 1100 A periodic interrupt is generated every 1/4 second. #1100 1101 A periodic interrupt is generated every 1/2 second. #1101 1110 A periodic interrupt is generated every 1 second. #1110 1111 A periodic interrupt is generated every 2 seconds. #1111 PIE Periodic Interrupt Enable 2 read-write 0 A periodic interrupt request is disabled. #0 1 A periodic interrupt request is enabled. #1 RTCOS RTCOUT Output Select 3 read-write 0 RTCOUT outputs 1 Hz. #0 1 RTCOUT outputs 64 Hz. #1 RCR2 RTC Control Register 2 0x24 8 read-write n 0x0 0x0 AADJE Automatic Adjustment Enable (When the LOCO clock is selected, the setting of this bit is disabled.) 4 read-write 0 Automatic adjustment is disabled. #0 1 Automatic adjustment is enabled. #1 AADJP Automatic Adjustment Period Select (When the LOCO clock is selected, the setting of this bit is disabled.) 5 read-write 0 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every minute. #0 1 The RADJ.ADJ[5:0] setting value is adjusted from the count value of the prescaler every 10 seconds. #1 ADJ30 30-Second Adjustment 2 read-write 0 Writing is invalid.(write) / In normal time operation, or 30-second adjustment has completed.(read) #0 1 30-second adjustment is executed.(write) / During 30-second adjustment.(read) #1 CNTMD Count Mode Select 7 read-write 0 The calendar count mode. #0 1 The binary count mode. #1 HR24 Hours Mode 6 read-write 0 The RTC operates in 12-hour mode. #0 1 The RTC operates in 24-hour mode. #1 RESET RTC Software Reset 1 read-write 0 Writing is invalid.(write) / In normal time operation, or an RTC software reset has completed.(read) #0 1 The prescaler and the target registers for RTC software reset *1 are initialized.(write) / During an RTC software reset.(read) #1 RTCOE RTCOUT Output Enable 3 read-write 0 RTCOUT output disabled. #0 1 RTCOUT output enabled. #1 START Start 0 read-write 0 Prescaler and time counter are stopped. #0 1 Prescaler and time counter operate normally. #1 RCR4 RTC Control Register 4 0x28 8 read-write n 0x0 0x0 RCKSEL Count Source Select 0 read-write 0 Sub-clock oscillator is selected. #0 1 LOCO clock oscillator is selected. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write RDAYAR Date Alarm Register 0x18 8 read-write n 0x0 0x0 DATE1 1 Day Value for the ones place of days 0 3 read-write DATE10 10 Days Value for the tens place of days 4 1 read-write ENB Compare enable 7 read-write 0 The register value is not compared with the RDAYCNT counter value. #0 1 The register value is compared with the RDAYCNT counter value. #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write RDAYCNT Day Counter 0xA 8 read-write n 0x0 0x0 DATE1 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. 0 3 read-write DATE10 10-Day Count Counts from 0 to 3 once per carry from the ones place. 4 1 read-write RDAYCP0 Date Capture Register %s 0x5A 8 read-only n 0x0 0x0 DATE1 1-Day Capture Capture value for the ones place of minutes 0 3 read-only DATE10 10-Day Capture Capture value for the tens place of minutes 4 1 read-only Reserved These bits are read as 00. 6 1 read-only RDAYCP1 Date Capture Register %s 0x6A 8 read-only n 0x0 0x0 DATE1 1-Day Capture Capture value for the ones place of minutes 0 3 read-only DATE10 10-Day Capture Capture value for the tens place of minutes 4 1 read-only Reserved These bits are read as 00. 6 1 read-only RDAYCP2 Date Capture Register %s 0x7A 8 read-only n 0x0 0x0 DATE1 1-Day Capture Capture value for the ones place of minutes 0 3 read-only DATE10 10-Day Capture Capture value for the tens place of minutes 4 1 read-only Reserved These bits are read as 00. 6 1 read-only RFRH Frequency Register H 0x2A 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000000. The write value should be 000000000000000. 1 14 read-write RFC16 Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock, this bit sets the comparison value of the 128-Hz clock cycle. 0 read-write RFRL Frequency Register L 0x2C 16 read-write n 0x0 0x0 RFC Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock, this bit sets the comparison value of the 128-Hz clock cycle. 0 15 read-write RHRAR Hour Alarm Register 0x14 8 read-write n 0x0 0x0 ENB Compare enable 7 read-write 0 The register value is not compared with the RHRCNT counter value. #0 1 The register value is compared with the RHRCNT counter value. #1 HR1 1-Hour Count Value for the ones place of hours 0 3 read-write HR10 10-Hour Count Value for the tens place of hours 4 1 read-write PM Time Counter Setting for a.m./p.m. 6 read-write 0 a.m. #0 1 p.m. #1 RHRCNT Hour Counter 0x6 8 read-write n 0x0 0x0 HR1 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place. 0 3 read-write HR10 10-Hour Count Counts from 0 to 2 once per carry from the ones place. 4 1 read-write PM Time Counter Setting for a.m./p.m. 6 read-write 0 a.m. #0 1 p.m. #1 RHRCP0 Hour Capture Register %s 0x56 8 read-only n 0x0 0x0 HR1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only HR10 10-Minute Capture Capture value for the tens place of minutes 4 1 read-only PM A.m./p.m. select for time counter setting. 6 read-only 0 a.m. #0 1 p.m. #1 Reserved This bit is read as 0. 7 read-only RHRCP1 Hour Capture Register %s 0x66 8 read-only n 0x0 0x0 HR1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only HR10 10-Minute Capture Capture value for the tens place of minutes 4 1 read-only PM A.m./p.m. select for time counter setting. 6 read-only 0 a.m. #0 1 p.m. #1 Reserved This bit is read as 0. 7 read-only RHRCP2 Hour Capture Register %s 0x76 8 read-only n 0x0 0x0 HR1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only HR10 10-Minute Capture Capture value for the tens place of minutes 4 1 read-only PM A.m./p.m. select for time counter setting. 6 read-only 0 a.m. #0 1 p.m. #1 Reserved This bit is read as 0. 7 read-only RMINAR Minute Alarm Register 0x12 8 read-write n 0x0 0x0 ENB Compare enable 7 read-write 0 The register value is not compared with the RMINCNT counter value. #0 1 The register value is compared with the RMINCNT counter value. #1 MIN1 1-Minute Count Value for the ones place of minutes 0 3 read-write MIN10 10-Minute Count Value for the tens place of minutes 4 2 read-write RMINCNT Minute Counter 0x4 8 read-write n 0x0 0x0 MIN1 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. 0 3 read-write MIN10 10-Minute Count Counts from 0 to 5 for 60-minute counting. 4 2 read-write RMINCP0 Minute Capture Register %s 0x54 8 read-only n 0x0 0x0 MIN1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only MIN10 10-Minute Capture Capture value for the tens place of minutes 4 2 read-only Reserved This bit is read as 0. 7 read-only RMINCP1 Minute Capture Register %s 0x64 8 read-only n 0x0 0x0 MIN1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only MIN10 10-Minute Capture Capture value for the tens place of minutes 4 2 read-only Reserved This bit is read as 0. 7 read-only RMINCP2 Minute Capture Register %s 0x74 8 read-only n 0x0 0x0 MIN1 1-Minute Capture Capture value for the ones place of minutes 0 3 read-only MIN10 10-Minute Capture Capture value for the tens place of minutes 4 2 read-only Reserved This bit is read as 0. 7 read-only RMONAR Month Alarm Register 0x1A 8 read-write n 0x0 0x0 ENB Compare enable 7 read-write 0 The register value is not compared with the RMONCNT counter value. #0 1 The register value is compared with the RMONCNT counter value. #1 MON1 1 Month Value for the ones place of months 0 3 read-write MON10 10 Months Value for the tens place of months 4 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write RMONCNT Month Counter 0xC 8 read-write n 0x0 0x0 MON1 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. 0 3 read-write MON10 10-Month Count Counts from 0 to 1 once per carry from the ones place. 4 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write RMONCP0 Month Capture Register %s 0x5C 8 read-only n 0x0 0x0 MON1 1-Month Capture Capture value for the ones place of months 0 3 read-only MON10 10-Month Capture Capture value for the tens place of months 4 read-only RMONCP1 Month Capture Register %s 0x6C 8 read-only n 0x0 0x0 MON1 1-Month Capture Capture value for the ones place of months 0 3 read-only MON10 10-Month Capture Capture value for the tens place of months 4 read-only RMONCP2 Month Capture Register %s 0x7C 8 read-only n 0x0 0x0 MON1 1-Month Capture Capture value for the ones place of months 0 3 read-only MON10 10-Month Capture Capture value for the tens place of months 4 read-only RSECAR Second Alarm Register 0x10 8 read-write n 0x0 0x0 ENB Compare enable 7 read-write 0 The register value is not compared with the RSECCNT counter value. #0 1 The register value is compared with the RSECCNT counter value. #1 SEC1 1-Second Value for the ones place of seconds 0 3 write-only SEC10 10-Seconds Value for the tens place of seconds 4 2 read-write RSECCNT Second Counter 0x2 8 read-write n 0x0 0x0 SEC1 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place. 0 3 read-write SEC10 10-Second Count Counts from 0 to 5 for 60-second counting. 4 2 read-write RSECCP0 Second Capture Register %s 0x52 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only SEC1 1-Second Capture Capture value for the ones place of seconds 0 3 read-only SEC10 10-Second Capture Capture value for the tens place of seconds 4 2 read-only RSECCP1 Second Capture Register %s 0x62 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only SEC1 1-Second Capture Capture value for the ones place of seconds 0 3 read-only SEC10 10-Second Capture Capture value for the tens place of seconds 4 2 read-only RSECCP2 Second Capture Register %s 0x72 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only SEC1 1-Second Capture Capture value for the ones place of seconds 0 3 read-only SEC10 10-Second Capture Capture value for the tens place of seconds 4 2 read-only RTCCR0 Time Capture Control Register %s 0x40 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write TCCT Time Capture Control 0 1 read-write 00 No event is detected. #00 01 Rising edge is detected. #01 10 Falling edge is detected. #10 11 Both edges are detected. #11 TCNF Time Capture Noise Filter Control 4 1 read-write 00 The noise filter is off. #00 01 Setting prohibited #01 10 The noise filter is on (count source). #10 11 The noise filter is on (count source by divided by 32). #11 TCST Time Capture Status 2 read-only 0 No event is detected. #0 1 An event is detected. #1 RTCCR1 Time Capture Control Register %s 0x42 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write TCCT Time Capture Control 0 1 read-write 00 No event is detected. #00 01 Rising edge is detected. #01 10 Falling edge is detected. #10 11 Both edges are detected. #11 TCNF Time Capture Noise Filter Control 4 1 read-write 00 The noise filter is off. #00 01 Setting prohibited #01 10 The noise filter is on (count source). #10 11 The noise filter is on (count source by divided by 32). #11 TCST Time Capture Status 2 read-only 0 No event is detected. #0 1 An event is detected. #1 RTCCR2 Time Capture Control Register %s 0x44 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write TCCT Time Capture Control 0 1 read-write 00 No event is detected. #00 01 Rising edge is detected. #01 10 Falling edge is detected. #10 11 Both edges are detected. #11 TCNF Time Capture Noise Filter Control 4 1 read-write 00 The noise filter is off. #00 01 Setting prohibited #01 10 The noise filter is on (count source). #10 11 The noise filter is on (count source by divided by 32). #11 TCST Time Capture Status 2 read-only 0 No event is detected. #0 1 An event is detected. #1 RWKAR Day-of-Week Alarm Register 0x16 8 read-write n 0x0 0x0 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 ENB Compare enable 7 read-write 0 The register value is not compared with the RWKCNT counter value. #0 1 The register value is compared with the RWKCNT counter value. #1 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write RWKCNT Day-of-Week Counter 0x8 8 read-write n 0x0 0x0 DAYW Day-of-Week Counting 0 2 read-write 000 Sunday #000 001 Monday #001 010 Tuesday #010 011 Wednesday #011 100 Thursday #100 101 Friday #101 110 Saturday #110 111 Setting Prohibited #111 RYRAR Year Alarm Register 0x1C 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write YR1 1 Year Value for the ones place of years 0 3 read-write YR10 10 Years Value for the tens place of years 4 3 read-write RYRAREN Year Alarm Enable Register 0x1E 8 read-write n 0x0 0x0 ENB Compare enable 7 read-write 0 The register value is not compared with the RYRCNT counter value. #0 1 The register value is compared with the RYRCNT counter value. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write RYRCNT Year Counter 0xE 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write YR1 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place. 0 3 read-write YR10 10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place, 1 is added to the hundreds place. 4 3 read-write SCI0 Serial Communication Interface 0 SCI0 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0xD registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0xC registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x2 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) 3 read-write 0 reception data full interrupt (RXI) #0 1 receive error interrupt (ERI) #1 FM FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 read-write 0 Non-FIFO mode(Selects o TDR/RDR for communication) #0 1 FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) #1 RFRST Receive FIFO Data Register Reset(Valid only in FCR.FM=1) 1 read-write 0 The number of data stored in FRDRH and FRDRL register are NOT made 0 #0 1 The number of data stored in FRDRH and FRDRL register are made 0 #1 RSTRG RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 12 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 RTRG Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 8 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 TFRST Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) 2 read-write 0 The number of data stored in FTDRH and FTDRL register are NOT made 0 #0 1 The number of data stored in FTDRH and FTDRL register are made 0 #1 TTRG Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 4 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 0 4 read-only Reserved These bits are read as 000. 13 2 read-only Reserved These bits are read as 000. 13 2 read-only T Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 8 4 read-only FRDRH Receive FIFO Data Register H RDRHL 0x10 8 read-only n 0x0 0x0 DR Receive data ready flag(It is same as SSR.DR) 2 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 FER Framing error flag 4 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL #0 1 A framing error has occurred at the first data of FRDRH and FRDRL #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun error flag(It is same as SSR.ORER) 5 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity error flag 3 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL #0 1 A parity error has occurred at the first data of FRDRH and FRDRL #1 RDATH Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 read-only RDF Receive FIFO data full flag(It is same as SSR.RDF) 6 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. 7 read-only FRDRHL Receive FIFO Data Register HL RDRHL 0x10 16 read-only n 0x0 0x0 DR Receive data ready flag(It is same as SSR.DR) 10 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 FER Framing error flag 12 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL. #0 1 A framing error has occurred at the first data of FRDRH and FRDRL. #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun error flag(It is same as SSR.ORER) 13 read-only 0 No overrun error occurred. #0 1 An overrun error has occurred. #1 PER Parity error flag 11 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL. #0 1 A parity error has occurred at the first data of FRDRH and FRDRL. #1 RDAT Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 read-only RDF Receive FIFO data full flag(It is same as SSR.RDF) 14 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. 15 read-only FRDRL Receive FIFO Data Register L RDRHL 0x11 8 read-only n 0x0 0x0 RDATL Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. 0 7 read-only FTDRH Transmit FIFO Data Register H TDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 1 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 Reserved The write value should be 111111. 2 5 write-only TDATH Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 write-only FTDRHL Transmit FIFO Data Register HL TDRHL 0xE 16 write-only n 0x0 0x0 MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 9 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 Reserved The write value should be 111111. 10 5 write-only TDAT Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 write-only FTDRL Transmit FIFO Data Register L TDRHL 0xF 8 write-only n 0x0 0x0 TDATL Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 2 4 read-only ORER Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 PNUM Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 8 4 read-only Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_FIFO Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) 0 read-write zeroToClear modify 0 Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) #0 1 Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. #1 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred. #0 1 A framing error has occurred. #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred. #0 1 A parity error has occurred. #1 RDF Receive FIFO data full flag 6 read-write zeroToClear modify 0 The quantity of receive data written in FRDR falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. The write value should be 0. 1 read-write TDFE Transmit FIFO data empty flag 7 read-write zeroToClear modify 0 The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. #0 1 The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write zeroToClear modify 0 A character is being transmitted or standing by for transmission. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SCI1 Serial Communication Interface 1 SCI0 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0xD registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0xC registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x2 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write FCR FIFO Control Register 0x14 16 read-write n 0x0 0x0 DRES Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) 3 read-write 0 reception data full interrupt (RXI) #0 1 receive error interrupt (ERI) #1 FM FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 read-write 0 Non-FIFO mode(Selects o TDR/RDR for communication) #0 1 FIFO mode (Selects to FTDRH and FTDRL/FRDRH and FRDRL for communication) #1 RFRST Receive FIFO Data Register Reset(Valid only in FCR.FM=1) 1 read-write 0 The number of data stored in FRDRH and FRDRL register are NOT made 0 #0 1 The number of data stored in FRDRH and FRDRL register are made 0 #1 RSTRG RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 12 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 RTRG Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 8 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 TFRST Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) 2 read-write 0 The number of data stored in FTDRH and FTDRL register are NOT made 0 #0 1 The number of data stored in FTDRH and FTDRL register are made 0 #1 TTRG Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 4 3 read-write others Triger number n (n= 0-15) 0000 Trigger number 0 #0000 FDR FIFO Data Count Register 0x16 16 read-only n 0x0 0x0 R Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 0 4 read-only Reserved These bits are read as 000. 13 2 read-only Reserved These bits are read as 000. 13 2 read-only T Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, while FCR.FM=1) 8 4 read-only FRDRH Receive FIFO Data Register H RDRHL 0x10 8 read-only n 0x0 0x0 DR Receive data ready flag(It is same as SSR.DR) 2 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 FER Framing error flag 4 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL #0 1 A framing error has occurred at the first data of FRDRH and FRDRL #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun error flag(It is same as SSR.ORER) 5 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity error flag 3 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL #0 1 A parity error has occurred at the first data of FRDRH and FRDRL #1 RDATH Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 read-only RDF Receive FIFO data full flag(It is same as SSR.RDF) 6 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. 7 read-only FRDRHL Receive FIFO Data Register HL RDRHL 0x10 16 read-only n 0x0 0x0 DR Receive data ready flag(It is same as SSR.DR) 10 read-only 0 Receiving is in progress, or no received data has remained in FRDRH and FRDRL after normally completed receiving. #0 1 Next receive data has not been received for a period after normal completed receiving. #1 FER Framing error flag 12 read-only 0 No framing error occurred at the first data of FRDRH and FRDRL. #0 1 A framing error has occurred at the first data of FRDRH and FRDRL. #1 MPB Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0]) 9 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun error flag(It is same as SSR.ORER) 13 read-only 0 No overrun error occurred. #0 1 An overrun error has occurred. #1 PER Parity error flag 11 read-only 0 No parity error occurred at the first data of FRDRH and FRDRL. #0 1 A parity error has occurred at the first data of FRDRH and FRDRL. #1 RDAT Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 read-only RDF Receive FIFO data full flag(It is same as SSR.RDF) 14 read-only 0 The quantity of receive data written in FRDRH and FRDRL falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. 15 read-only FRDRL Receive FIFO Data Register L RDRHL 0x11 8 read-only n 0x0 0x0 RDATL Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register, please read by an order of the FRDRH register and the FRDRL register. 0 7 read-only FTDRH Transmit FIFO Data Register H TDRHL 0xE 8 write-only n 0x0 0x0 MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 1 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 Reserved The write value should be 111111. 2 5 write-only TDATH Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 write-only FTDRHL Transmit FIFO Data Register HL TDRHL 0xE 16 write-only n 0x0 0x0 MPBT Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected) 9 write-only 0 Data transmission cycles #0 1 ID transmission cycles #1 Reserved The write value should be 111111. 10 5 write-only TDAT Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 8 write-only FTDRL Transmit FIFO Data Register L TDRHL 0xF 8 write-only n 0x0 0x0 TDATL Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 7 write-only LSR Line Status Register 0x18 16 read-only n 0x0 0x0 FNUM Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 2 4 read-only ORER Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected) 0 read-only 0 No overrun error occurred #0 1 An overrun error has occurred #1 PNUM Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL). 8 4 read-only Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_FIFO Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) SSR 0x4 8 read-write n 0x0 0x0 DR Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected) 0 read-write zeroToClear modify 0 Receiving is in progress, or no received data has remained in FRDR after normally completed receiving.(receive FIFO is empty) #0 1 Next receive data has not been received for a period after normal completed receiving, , when data is stored in FIFO to equal or less than receive triggering number. #1 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred. #0 1 A framing error has occurred. #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred. #0 1 A parity error has occurred. #1 RDF Receive FIFO data full flag 6 read-write zeroToClear modify 0 The quantity of receive data written in FRDR falls below the specified receive triggering number. #0 1 The quantity of receive data written in FRDR is equal to or greater than the specified receive triggering number. #1 Reserved This bit is read as 0. The write value should be 0. 1 read-write TDFE Transmit FIFO data empty flag 7 read-write zeroToClear modify 0 The quantity of transmit data written in FTDR exceeds the specified transmit triggering number. #0 1 The quantity of transmit data written in FTDR is equal to or less than the specified transmit triggering number #1 TEND Transmit End Flag 2 read-write zeroToClear modify 0 A character is being transmitted or standing by for transmission. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SCI2 Serial Communication Interface 2 SCI2 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x0 0x1 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x4 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SCI3 Serial Communication Interface 3 SCI2 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x0 0x1 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x4 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SCI4 Serial Communication Interface 4 SCI2 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x0 0x1 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x4 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SCI9 Serial Communication Interface 9 SCI2 0x0 0x0 0x1 registers n 0x0 0x3 registers n 0x0 0x1 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x10 0x2 registers n 0x2 0x3 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0x4 0x1 registers n 0xE 0x4 registers n 0xE 0x2 registers n 0xE 0x4 registers n BRR Bit Rate Register 0x1 8 read-write n 0x0 0x0 BRR BRR is an 8-bit register that adjusts the bit rate. 0 7 read-write CDR Compare Match Data Register 0x1A 16 read-write n 0x0 0x0 CMPD Compare Match DataCompare data pattern for address match wake-up function 0 8 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write DCCR Data Compare Match Control Register 0x13 8 read-write n 0x0 0x0 DCME Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor) 7 read-write 0 Address match function is disabled. #0 1 Address match function is enabled #1 DCMF Data Compare Match Flag 0 read-write zeroToClear modify 0 No matched #0 1 Matched #1 DFER Data Compare Match Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 DPER Data Compare Match Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 IDSEL ID frame select(Valid only in asynchronous mode(including multi-processor) 6 read-write 0 Always compare data regardless of the value of the MPB bit. #0 1 Compare data when the MPB bit is 1 (ID frame) only. #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write MDDR Modulation Duty Register 0x12 8 read-write n 0x0 0x0 MDDR MDDR corrects the bit rate adjusted by the BRR register. 0 7 read-write RDR Receive Data Register 0x5 8 read-only n 0x0 0x0 RDR RDR is an 8-bit register that stores receive data. 0 7 read-only RDRHL Receive 9-bit Data Register 0x10 16 read-only n 0x0 0x0 RDRHL RDRHL is an 16-bit register that stores receive data. 0 15 read-only SCMR Smart Card Mode Register 0x6 8 read-write n 0x0 0x0 BCP2 Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits 7 read-write 0 S=93(SMR.BCP[1:0]=00), 128(SMR.BCP[1:0]=01), 186(SMR.BCP[1:0]=10), 512(SMR.BCP[1:0]=11) #0 1 S=32(SMR.BCP[1:0]=00), 64(SMR.BCP[1:0]=01), 372(SMR.BCP[1:0]=10), 256(SMR.BCP[1:0]=11) #1 CHR1 Character Length 1(Only valid in asynchronous mode) 4 read-write 0 Transmit/receive in 9-bit data length #0 1 Transmit/receive in 8-bit data length(SMR.CHR=0) / in 7bit data length(SMR.CHR=1) #1 Reserved These bits are read as 11. The write value should be 11. 5 1 read-write Reserved These bits are read as 11. The write value should be 11. 5 1 read-write SDIR Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode. 3 read-write 0 Transfer with LSB first #0 1 Transfer with MSB first #1 SINV Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode. 2 read-write 0 TDR contents are transmitted as they are. Receive data is stored as it is in RDR. #0 1 TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. #1 SMIF Smart Card Interface Mode Select 0 read-write 0 Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode) #0 1 Smart card interface mode #1 SCR Serial Control Register (SCMR.SMIF = 0) 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write others The clock with a frequency 16 times the bit rate should be input from the SCKn pin. (when SEMR.ABCS bit is 0) Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1.(Asynchronous mode) / The SCKn pin functions as the clock input pin(Clock synchronous mode) 00 The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #00 01 The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode) #01 MPIE Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1) 3 read-write 0 Normal reception #0 1 When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed. #1 RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write 0 SCI_TEI interrupt request is disabled #0 1 SCI_TEI interrupt request is enabled #1 TIE Transmit Interrupt Enable 7 read-write 0 SCI_TXI interrupt request is disabled #0 1 SCI_TXI interrupt request is enabled #1 SCR_SMCI Serial Control Register (SCMR.SMIF =1) SCR 0x2 8 read-write n 0x0 0x0 CKE Clock Enable 0 1 read-write 00 Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1) #00 01 Clock Output #01 10 Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1) #10 11 Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1) #11 MPIE Multi-Processor Interrupt Enable 3 read-write RE Receive Enable 4 read-write 0 Serial reception is disabled #0 1 Serial reception is enabled #1 RIE Receive Interrupt Enable 6 read-write 0 SCI_RXI and SCI_ERI interrupt requests are disabled #0 1 SCI_RXI and SCI_ERI interrupt requests are enabled #1 TE Transmit Enable 5 read-write 0 Serial transmission is disabled #0 1 Serial transmission is enabled #1 TEIE Transmit End Interrupt Enable 2 read-write TIE Transmit Interrupt Enable 7 read-write 0 A SCI_TXI interrupt request is disabled #0 1 A SCI_TXI interrupt request is enabled #1 SEMR Serial Extended Mode Register 0x7 8 read-write n 0x0 0x0 ABCS Asynchronous Mode Base Clock Select(Valid only in asynchronous mode) 4 read-write 0 Selects 16 base clock cycles for 1-bit period. #0 1 Selects 8 base clock cycles for 1-bit period. #1 ABCSE Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0) 3 read-write 0 Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR. #0 1 Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator. #1 BGDM Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode). 6 read-write 0 Baud rate generator outputs the clock with normal frequency. #0 1 Baud rate generator outputs the clock with doubled frequency. #1 BRME Bit Rate Modulation Enable 2 read-write 0 Bit rate modulation function is disabled. #0 1 Bit rate modulation function is enabled. #1 NFEN Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input. 5 read-write 0 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is disabled. #0 1 Noise cancellation function for the RXDn/SSCLn and SSDAn input signal is enabled. #1 Reserved These bits are read as 00. The write value should be 00. 0 1 read-write RXDESEL Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode) 7 read-write 0 The low level on the RXDn pin is detected as the start bit. #0 1 A falling edge on the RXDn pin is detected as the start bit. #1 SIMR1 I2C Mode Register 1 0x9 8 read-write n 0x0 0x0 IICDL SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator. 3 4 read-write others (IICDL - 1 ) to IIDCDL cycles. The delay is in the clock cycles from the on-chip baud rate generator. 00000 No output delay #00000 IICM Simple I2C Mode Select 0 read-write 0 Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1) #0 1 Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1) #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SIMR2 I2C Mode Register 2 0xA 8 read-write n 0x0 0x0 IICACKT ACK Transmission Data 5 read-write 0 ACK transmission #0 1 NACK transmission and reception of ACK/NACK #1 IICCSC Clock Synchronization 1 read-write 0 No synchronization with the clock signal #0 1 Synchronization with the clock signal #1 IICINTM I2C Interrupt Mode Select 0 read-write 0 Use ACK/NACK interrupts. #0 1 Use reception and transmission interrupts #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SIMR3 I2C Mode Register 3 0xB 8 read-write n 0x0 0x0 IICRSTAREQ Restart Condition Generation 1 read-write 0 A restart condition is not generated. #0 1 A restart condition is generated. #1 IICSCLS SCL Output Select 6 1 read-write 00 Serial clock output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSCLn pin. #10 11 Place the SSCLn pin in the high-impedance state. #11 IICSDAS SDA Output Select 4 1 read-write 00 Serial data output #00 01 Generate a start, restart, or stop condition. #01 10 Output the low level on the SSDAn pin. #10 11 Place the SSDAn pin in the high-impedance state. #11 IICSTAREQ Start Condition Generation 0 read-write 0 A start condition is not generated. #0 1 A start condition is generated. #1 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.) 3 read-write zeroToClear modify 0 There are no requests for generating conditions or a condition is being generated. #0 1 A start, restart, or stop condition is completely generated. #1 IICSTPREQ Stop Condition Generation 2 read-write 0 A stop condition is not generated. #0 1 A stop condition is generated. #1 SISR I2C Status Register 0xC 8 read-only n 0x0 0x0 IICACKR ACK Reception Data Flag 0 read-only 0 ACK received #0 1 NACK received #1 Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 5 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 3 read-only Reserved This bit is read as 0. 2 read-only Reserved This bit is read as 0. 2 read-only SMR Serial Mode Register (SCMR.SMIF = 0) 0x0 8 read-write n 0x0 0x0 CHR Character Length(Valid only in asynchronous mode) 6 read-write 0 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 8bit data length(SCMR.CHR1=1) #0 1 Transmit/receive in 9-bit data length(SCMR.CHR1=0) / in 7bit data length(SCMR.CHR1=1) #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 CM Communication Mode 7 read-write 0 Asynchronous mode or simple I2C mode #0 1 Clock synchronous mode #1 MP Multi-Processor Mode(Valid only in asynchronous mode) 2 read-write 0 Multi-processor communications function is disabled #0 1 Multi-processor communications function is enabled #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving ) #0 1 The parity bit is added (transmitting) / The parity bit is checked (receiving) #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 STOP Stop Bit Length(Valid only in asynchronous mode) 3 read-write 0 1 stop bit #0 1 2 stop bits #1 SMR_SMCI Serial mode register (SCMR.SMIF = 1) SMR 0x0 8 read-write n 0x0 0x0 BCP Base Clock Pulse(Valid only in asynchronous mode) 2 1 read-write 00 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32) (SCMR.BCP2=1) #00 01 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1) #01 10 186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1) #10 11 512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1) #11 BLK Block Transfer Mode 6 read-write 0 Normal mode operation #0 1 Block transfer mode operation #1 CKS Clock Select 0 1 read-write 00 PCLK clock #00 01 PCLK/4 clock #01 10 PCLK/16 clock #10 11 PCLK/64 clock #11 GM GSM Mode 7 read-write 0 Normal mode operation #0 1 GSM mode operation #1 PE Parity Enable(Valid only in asynchronous mode) 5 read-write 0 Setting Prohibited #0 1 Set this bit to 1 in smart card interface mode. #1 PM Parity Mode (Valid only when the PE bit is 1) 4 read-write 0 Selects even parity #0 1 Selects odd parity #1 SNFR Noise Filter Setting Register 0x8 8 read-write n 0x0 0x0 NFCS Noise Filter Clock Select 0 2 read-write others Settings prohibited. 000 The clock signal divided by 1 is used with the noise filter.(In asynchronous mode) #000 001 The clock signal divided by 1 is used with the noise filter.(In simple I2C mode) #001 010 The clock signal divided by 2 is used with the noise filter.(In simple I2C mode) #010 011 The clock signal divided by 4 is used with the noise filter.(In simple I2C mode) #011 100 The clock signal divided by 8 is used with the noise filter.(In simple I2C mode) #100 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPMR SPI Mode Register 0xD 8 read-write n 0x0 0x0 CKPH Clock Phase Select 7 read-write 0 Clock is not delayed. #0 1 Clock is delayed. #1 CKPOL Clock Polarity Select 6 read-write 0 Clock polarity is not inverted. #0 1 Clock polarity is inverted #1 CTSE CTS Enable 1 read-write 0 CTS function is disabled (RTS output function is enabled). #0 1 CTS function is enabled. #1 MFF Mode Fault Flag 4 read-write zeroToClear modify 0 No mode fault error #0 1 Mode fault error #1 MSS Master Slave Select 2 read-write 0 Transmission is through the TXDn pin and reception is through the RXDn pin (master mode). #0 1 Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode). #1 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write SSE SSn Pin Function Enable 0 read-write 0 SSn pin function is disabled. #0 1 SSn pin function is enabled. #1 SPTR Serial Port Register 0x1C 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write RXDMON Serial input data monitor bit(The state of the RXD terminal is shown.) 0 read-only 0 RXD pin is low. #0 1 RXD pin is high. #1 SPB2DT Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.) 1 read-write 0 Low level is output on TXD pin #0 1 High level is output on TXD pin #1 SPB2IO Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.) 2 read-write 0 The value of SPB2DT bit is not output in TXD pin. #0 1 The value of SPB2DT bit is output in TXD pin. #1 SSR Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) 0x4 8 read-write n 0x0 0x0 FER Framing Error Flag 4 read-write zeroToClear modify 0 No framing error occurred #0 1 A framing error has occurred #1 MPB Multi-Processor 1 read-only 0 Data transmission cycles #0 1 ID transmission cycles #1 MPBT Multi-Processor Bit Transfer 0 read-write 0 Data transmission cycles #0 1 ID transmission cycles #1 ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 SSR_SMCI Serial Status Register(SCMR.SMIF = 1) SSR 0x4 8 read-write n 0x0 0x0 ERS Error Signal Status Flag 4 read-write zeroToClear modify 0 Low error signal not responded #0 1 Low error signal responded #1 MPB Multi-ProcessorThis bit should be 0 in smart card interface mode. 1 read-only MPBT Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode. 0 read-write ORER Overrun Error Flag 5 read-write zeroToClear modify 0 No overrun error occurred #0 1 An overrun error has occurred #1 PER Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurred #0 1 A parity error has occurred #1 RDRF Receive Data Full Flag 6 read-write zeroToClear modify 0 No received data is in RDR register #0 1 Received data is in RDR register #1 TDRE Transmit Data Empty Flag 7 read-write zeroToClear modify 0 Transmit data is in TDR register #0 1 No transmit data is in TDR register #1 TEND Transmit End Flag 2 read-only 0 A character is being transmitted. #0 1 Character transfer has been completed. #1 TDR Transmit Data Register 0x3 8 read-write n 0x0 0x0 TDR TDR is an 8-bit register that stores transmit data. 0 7 read-write TDRHL Transmit 9-bit Data Register 0xE 16 read-write n 0x0 0x0 TDRHL TDRHL is a 16-bit register that stores transmit data. 0 15 write-only SLCDC Segment LCD Controller/Driver SLCDC 0x0 0x0 0x4 registers n 0x100 0x36 registers n LCDC0 LCD Clock Control Register 0 0x2 8 read-write n 0x0 0x0 LCDC LCD clock (LCDCL) 0 5 read-write 000001 (Sub clock)/22 or (LOCO clock)/22 #000001 000010 (Sub clock)/23 or (LOCO clock)/23 #000010 000011 (Sub clock)/24 or (LOCO clock)/24 #000011 000100 (Sub clock)/25 or (LOCO clock)/25 #000100 000101 (Sub clock)/26 or (LOCO clock)/26 #000101 000110 (Sub clock)/27 or (LOCO clock)/27 #000110 000111 (Sub clock)/28 or (LOCO clock)/28 #000111 001000 (Sub clock)/29 or (LOCO clock)/29 #001000 001001 (Sub clock)/210 or (LOCO clock)/210 #001001 010001 (Main clock)/28 or (HOCO clock)/28 #010001 010010 (Main clock)/29 or (HOCO clock)/29 #010010 010011 (Main clock)/210 or (HOCO clock)/210 #010011 010100 (Main clock)/211 or (HOCO clock)/211 #010100 010101 (Main clock)/212 or (HOCO clock)/212 #010101 010110 (Main clock)/213 or (HOCO clock)/213 #010110 010111 (Main clock)/214 or (HOCO clock)/214 #010111 011000 (Main clock)/215 or (HOCO clock)/215 #011000 011001 (Main clock)/216 or (HOCO clock)/216 #011001 011010 (Main clock)/217 or (HOCO clock)/217 #011010 011011 (Main clock)/218 or (HOCO clock)/218 #011011 101011 (Main clock)/219 or (HOCO clock)/219 #101011 LCDM0 LCD Mode Register 0 0x0 8 read-write n 0x0 0x0 LBAS LCD Display Bias Method Select 0 1 read-write 00 1/2 bias method #00 01 1/3 bias method #01 10 1/4 bias method #10 11 Setting prohibited #11 LDTY Time Slice of LCD Display Select 2 2 read-write 000 Static #000 001 2-time slice #001 010 3-time slice #010 011 4-time slice #011 101 8-time slice #101 LWAVE LCD display waveform selection 5 read-write 0 Waveform A #0 1 Waveform B #1 MDSET LCD drive voltage generator selection 6 1 read-write 00 External resistance division method #00 01 Internal voltage boosting method #01 10 Capacitor split method #10 11 Setting prohibited #11 LCDM1 LCD Mode Register 1 0x1 8 read-write n 0x0 0x0 BLON Display data area control 4 read-write 0 Displaying an A-pattern area data (lower four bits of LCD display data register)(LCDSEL=0)/Displaying a B-pattern area data (higher four bits of LCD display data register)(LCDSEL=1) #0 1 Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC)) #1 LCDON LCD Display Enable/Disable 7 read-write 0 Output ground level to segment/common pin(SCOC=0)/Display off (all segment outputs are deselected)(SCOC=1) #0 1 Output ground level to segment/common pin(SCOC=0)/Display on(SCOC=1) #1 LCDSEL Display data area control 3 read-write 0 Displaying an A-pattern area data (lower four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) #0 1 Displaying a B-pattern area data (higher four bits of LCD display data register)(BLON=0)/Alternately displaying A-pattern and B-pattern area data (blinking display corresponding to the constant-period interrupt (INTRTC) timing of the real-time clock (RTC))(BLON=1) #1 LCDVLM Voltage Boosting Pin Initial Value Switching Control 0 read-write 0 Set when VDD >= 2.7 V #0 1 Set when VDD <= 4.2 V #1 Reserved These bits are read as 00. The write value should be 00. 1 1 read-write SCOC LCD Display Enable/Disable 6 read-write 0 Output ground level to segment/common pin(LCDON=0)/Output ground level to segment/common pin(LCDON=1) #0 1 Display off (all segment outputs are deselected)(LCDON=0)/Display on(LCDON=1) #1 VLCON Voltage boost circuit or capacitor split circuit operation enable/disable 5 read-write 0 Stops voltage boost circuit or capacitor split circuit operation #0 1 Enables voltage boost circuit or capacitor split circuit operation #1 SEG0 LCD Display Data Register %s 0x200 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG1 LCD Display Data Register %s 0x301 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG10 LCD Display Data Register %s 0xC37 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG11 LCD Display Data Register %s 0xD42 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG12 LCD Display Data Register %s 0xE4E 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG13 LCD Display Data Register %s 0xF5B 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG14 LCD Display Data Register %s 0x1069 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG15 LCD Display Data Register %s 0x1178 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG16 LCD Display Data Register %s 0x1288 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG17 LCD Display Data Register %s 0x1399 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG18 LCD Display Data Register %s 0x14AB 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG19 LCD Display Data Register %s 0x15BE 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG2 LCD Display Data Register %s 0x403 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG20 LCD Display Data Register %s 0x16D2 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG21 LCD Display Data Register %s 0x17E7 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG22 LCD Display Data Register %s 0x18FD 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG23 LCD Display Data Register %s 0x1A14 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG24 LCD Display Data Register %s 0x1B2C 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG25 LCD Display Data Register %s 0x1C45 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG26 LCD Display Data Register %s 0x1D5F 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG27 LCD Display Data Register %s 0x1E7A 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG28 LCD Display Data Register %s 0x1F96 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG29 LCD Display Data Register %s 0x20B3 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG3 LCD Display Data Register %s 0x506 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG30 LCD Display Data Register %s 0x21D1 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG31 LCD Display Data Register %s 0x22F0 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG32 LCD Display Data Register %s 0x2410 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG33 LCD Display Data Register %s 0x2531 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG34 LCD Display Data Register %s 0x2653 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG35 LCD Display Data Register %s 0x2776 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG36 LCD Display Data Register %s 0x289A 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG37 LCD Display Data Register %s 0x29BF 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG38 LCD Display Data Register %s 0x2AE5 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG39 LCD Display Data Register %s 0x2C0C 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG4 LCD Display Data Register %s 0x60A 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG40 LCD Display Data Register %s 0x2D34 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG41 LCD Display Data Register %s 0x2E5D 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG42 LCD Display Data Register %s 0x2F87 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG43 LCD Display Data Register %s 0x30B2 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG44 LCD Display Data Register %s 0x31DE 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG45 LCD Display Data Register %s 0x330B 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG46 LCD Display Data Register %s 0x3439 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG47 LCD Display Data Register %s 0x3568 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG48 LCD Display Data Register %s 0x3698 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG49 LCD Display Data Register %s 0x37C9 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG5 LCD Display Data Register %s 0x70F 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG50 LCD Display Data Register %s 0x38FB 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG51 LCD Display Data Register %s 0x3A2E 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG52 LCD Display Data Register %s 0x3B62 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG53 LCD Display Data Register %s 0x3C97 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG6 LCD Display Data Register %s 0x815 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG7 LCD Display Data Register %s 0x91C 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG8 LCD Display Data Register %s 0xA24 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write SEG9 LCD Display Data Register %s 0xB2D 8 read-write n 0x0 0x0 SEG LCD Display Data 0 7 read-write VLCD LCD Boost Level Control Register 0x3 8 read-write n 0x0 0x0 VLCD Reference Voltage(Contrast Adjustment) Select 0 4 read-write 00100 Reference voltageselection(contrast adjustment): 1.00 V (default) VL4 voltage: 3.00 V(1/3 bias method)/4.00 V(1/4 bias method) #00100 00101 Reference voltageselection(contrast adjustment): 1.05 V VL4 voltage: 3.15 V(1/3 bias method)/4.20 V(1/4 bias method) #00101 00110 Reference voltageselection(contrast adjustment): 1.10 V VL4 voltage: 3.30 V(1/3 bias method)/4.40 V(1/4 bias method) #00110 00111 Reference voltageselection(contrast adjustment): 1.15 V VL4 voltage: 3.45 V(1/3 bias method)/4.60 V(1/4 bias method) #00111 01000 Reference voltageselection(contrast adjustment): 1.20 V VL4 voltage: 3.60 V(1/3 bias method)/4.80 V(1/4 bias method) #01000 01001 Reference voltageselection(contrast adjustment): 1.25 V VL4 voltage: 3.75 V(1/3 bias method)/5.00 V(1/4 bias method) #01001 01010 Reference voltageselection(contrast adjustment): 1.30 V VL4 voltage: 3.90 V(1/3 bias method)/5.20 V(1/4 bias method) #01010 01011 Reference voltageselection(contrast adjustment): 1.35 V VL4 voltage: 4.05 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01011 01100 Reference voltageselection(contrast adjustment): 1.40 V VL4 voltage: 4.20 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01100 01101 Reference voltageselection(contrast adjustment): 1.45 V VL4 voltage: 4.35 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01101 01110 Reference voltageselection(contrast adjustment): 1.50 V VL4 voltage: 4.50 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01110 01111 Reference voltageselection(contrast adjustment): 1.55 V VL4 voltage: 4.65 V(1/3 bias method)/Setting prohibited(1/4 bias method) #01111 10000 Reference voltageselection(contrast adjustment): 1.60 V VL4 voltage: 4.80 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10000 10001 Reference voltageselection(contrast adjustment): 1.65 V VL4 voltage: 4.95 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10001 10010 Reference voltageselection(contrast adjustment): 1.70 V VL4 voltage: 5.10 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10010 10011 Reference voltageselection(contrast adjustment): 1.75 V VL4 voltage: 5.25 V(1/3 bias method)/Setting prohibited(1/4 bias method) #10011 SMPU Bus Slave MPU SMPU 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x20 0xC registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n SMPUCTL Slave MPU Control Register 0x0 16 read-write n 0x0 0x0 KEY Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit. 8 7 read-write others Writing to the PROTECT and OAD bit is invalid. 0xA5 Writing to the PROTECT and OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 OAD Master Group enable 0 read-write 0 Non-maskable interrupt. #0 1 Internal reset. #1 PROTECT Protection of register Protected register SMPUMBIU, SMPUFBIU, SMPUSRAM0, SMPUP0BIU, SMPUP2BIU, SMPUP6BIU,SMPUEXBIU, SMPUEXBIU2 1 1 read-write 0 All Bus Slave register writing is possible. #0 1 All Bus Slave register writing is protected. Read is possible. #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SMPUEXBIU Access Control Register for EXBIU 0x30 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUEXBIU2 Access Control Register for EXBIU2 0x34 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUFBIU Access Control Register for FBIU 0x14 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUMBIU Access Control Register for MBIU 0x10 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUP0BIU Access Control Register for P%sBIU 0x20 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUP2BIU Access Control Register for P%sBIU 0x24 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUP6BIU Access Control Register for P%sBIU 0x28 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SMPUSRAM0 Access Control Register for SRAM0 0x18 16 read-write n 0x0 0x0 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write RPCPU CPU Read protection 0 read-write 0 CPU read of memory protection disabled. #0 1 CPU read of memory protection enabled. #1 RPGRPA Master Group A Read protection 2 read-write 0 Master group A read of memory protection disabled. #0 1 Master group A read of memory protection enabled. #1 WPCPU CPU Write protection 1 read-write 0 CPU write of memory protection disabled. #0 1 CPU write of memory protection enabled. #1 WPGRPA Master Group A Write protection 3 read-write 0 Master group A write of memory protection disabled. #0 1 Master group A write of memory protection enabled. #1 SPI0 Serial Peripheral Interface 0 SPI0 0x0 0x0 0x8 registers n 0x4 0x2 registers n 0x8 0x18 registers n SPBR SPI Bit Rate Register 0xA 8 read-write n 0x0 0x0 SPR SPBR sets the bit rate in master mode. 0 7 read-write SPCKD SPI Clock Delay Register 0xC 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPCMD0 SPI Command Register %s 0x10 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD1 SPI Command Register %s 0x12 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD2 SPI Command Register %s 0x14 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD3 SPI Command Register %s 0x16 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD4 SPI Command Register %s 0x18 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD5 SPI Command Register %s 0x1A 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD6 SPI Command Register %s 0x1C 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCMD7 SPI Command Register %s 0x1E 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCR SPI Control Register 0x0 8 read-write n 0x0 0x0 MODFEN Mode Fault Error Detection Enable 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 MSTR SPI Master/Slave Mode Select 3 read-write 0 Slave mode #0 1 Master mode #1 SPE SPI Function Enable 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPEIE SPI Error Interrupt Enable 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 SPMS SPI Mode Select 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 TXMD Communications Operating Mode Select 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPCR2 SPI Control Register 2 0xF 8 read-write n 0x0 0x0 PTE Parity Self-Testing 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SCKASE RSPCK Auto-Stop Function Enable 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 SPIIE SPI Idle Interrupt Enable 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPDCR SPI Data Control Register 0xB 8 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPFC Number of Frames Specification 0 1 read-write 00 1 frame #00 01 2 frames #01 10 3 frames #10 11 4 frames. #11 SPLW SPI Word Access/Halfword Access Specification 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 SPDR SPI Data Register 0x4 32 read-write n 0x0 0x0 SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x4 16 read-write n 0x0 0x0 SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPND SPI Next-Access Delay Register 0xE 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPPCR SPI Pin Control Register 0x2 8 read-write n 0x0 0x0 MOIFE MOSI Idle Value Fixing Enable 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPLP RSPI Loopback 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPLP2 RSPI Loopback 2 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPSCR SPI Sequence Control Register 0x8 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPSLN RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0. 0 2 read-write 000 Length 1 SPDMDx x = 0->0->... #000 001 Length 2 SPDMDx x = 0->1->0->... #001 010 Length 3 SPDMDx x = 0->1->2->0->... #010 011 Length 4 SPDMDx x = 0->1->2->3->0->... #011 100 Length 5 SPDMDx x = 0->1->2->3->4->0->... #100 101 Length 6 SPDMDx x = 0->1->2->3->4->5->0->... #101 110 Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->... #110 111 Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->... #111 SPSR SPI Status Register 0x3 8 read-write n 0x0 0x0 IDLNF SPI Idle Flag 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 read-write zeroToClear modify 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 OVRF Overrun Error Flag 0 read-write zeroToClear modify 0 No overrun error occurs #0 1 An overrun error occurs #1 PERF Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurs #0 1 A parity error occurs #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write SPRF SPI Receive Buffer Full Flag 7 read-write zeroToClear modify 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 SPTEF SPI Transmit Buffer Empty Flag 5 read-write zeroToClear modify 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag(When MODF is 0, This bit is invalid.) 4 read-write zeroToClear modify 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 SPSSR SPI Sequence Status Register 0x9 8 read-only n 0x0 0x0 Reserved This bit is read as 0. 7 read-only Reserved This bit is read as 0. 7 read-only SPCP SPI Command Pointer 0 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SPECM SPI Error Command 4 2 read-only 000 SPCMD0 #000 001 SPCMD1 #001 010 SPCMD2 #010 011 SPCMD3 #011 100 SPCMD4 #100 101 SPCMD5 #101 110 SPCMD6 #110 111 SPCMD7 #111 SSLND SPI Slave Select Negation Delay Register 0xD 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLP SPI Slave Select Polarity Register 0x1 8 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write SSL0P SSL0 Signal Polarity Setting 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL3P SSL3 Signal Polarity Setting 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SPI1 Serial Peripheral Interface 1 SPI1 0x0 0x0 0x8 registers n 0x4 0x2 registers n 0x8 0xA registers n SPBR SPI Bit Rate Register 0xA 8 read-write n 0x0 0x0 SPR SPBR sets the bit rate in master mode. 0 7 read-write SPCKD SPI Clock Delay Register 0xC 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SCKDL RSPCK Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SPCMD0 SPI Command Register 0 0x10 16 read-write n 0x0 0x0 BRDV Bit Rate Division Setting 2 1 read-write 00 These bits select the base bit rate #00 01 These bits select the base bit rate divided by 2 #01 10 These bits select the base bit rate divided by 4 #10 11 These bits select the base bit rate divided by 8 #11 CPHA RSPCK Phase Setting 0 read-write 0 Data sampling on odd edge, data variation on even edge #0 1 Data variation on odd edge, data sampling on even edge #1 CPOL RSPCK Polarity Setting 1 read-write 0 RSPCK is low when idle #0 1 RSPCK is high when idle #1 LSBF RSPI LSB First 12 read-write 0 MSB first #0 1 LSB first #1 SCKDEN RSPCK Delay Setting Enable 15 read-write 0 An RSPCK delay of 1 RSPCK #0 1 An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD) #1 SLNDEN SSL Negation Delay Setting Enable 14 read-write 0 An SSL negation delay of 1 RSPCK #0 1 An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND) #1 SPB RSPI Data Length Setting 8 3 read-write others 8bits 0000 20 bits #0000 0001 24 bits #0001 0010 32 bits #0010 0011 32 bits #0011 1000 9 bits #1000 1001 10 bits #1001 1010 11 bits #1010 1011 12 bits #1011 1100 13 bits #1100 1101 14 bits #1101 1110 15 bits #1110 1111 16 bits #1111 SPNDEN RSPI Next-Access Delay Enable 13 read-write 0 A next-access delay of 1 RSPCK + 2 PCLK #0 1 A next-access delay is equal to the setting of the RSPI next-access delay register (SPND) #1 SSLA SSL Signal Assertion Setting 4 2 read-write others Setting prohibited 000 SSL0 #000 001 SSL1 #001 010 SSL2 #010 011 SSL3 #011 SSLKP SSL Signal Level Keeping 7 read-write 0 Negates all SSL signals upon completion of transfer #0 1 Keeps the SSL signal level from the end of transfer until the beginning of the next access #1 SPCR SPI Control Register 0x0 8 read-write n 0x0 0x0 MODFEN Mode Fault Error Detection Enable 2 read-write 0 Disables the detection of mode fault error #0 1 Enables the detection of mode fault error #1 MSTR SPI Master/Slave Mode Select 3 read-write 0 Slave mode #0 1 Master mode #1 SPE SPI Function Enable 6 read-write 0 Disables the SPI function #0 1 Enables the SPI function #1 SPEIE SPI Error Interrupt Enable 4 read-write 0 Disables the generation of SPI error interrupt requests #0 1 Enables the generation of SPI error interrupt requests #1 SPMS SPI Mode Select 0 read-write 0 SPI operation (4-wire method) #0 1 Clock synchronous operation (3-wire method) #1 SPRIE SPI Receive Buffer Full Interrupt Enable 7 read-write 0 Disables the generation of SPI receive buffer full interrupt requests #0 1 Enables the generation of SPI receive buffer full interrupt requests #1 SPTIE Transmit Buffer Empty Interrupt Enable 5 read-write 0 Disables the generation of transmit buffer empty interrupt requests #0 1 Enables the generation of transmit buffer empty interrupt requests #1 TXMD Communications Operating Mode Select 1 read-write 0 Full-duplex synchronous serial communications #0 1 Serial communications consisting of only transmit operations #1 SPCR2 SPI Control Register 2 0xF 8 read-write n 0x0 0x0 PTE Parity Self-Testing 3 read-write 0 Disables the self-diagnosis function of the parity circuit #0 1 Enables the self-diagnosis function of the parity circuit #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SCKASE RSPCK Auto-Stop Function Enable 4 read-write 0 Disables the RSPCK auto-stop function #0 1 Enables the RSPCK auto-stop function #1 SPIIE SPI Idle Interrupt Enable 2 read-write 0 Disables the generation of idle interrupt requests #0 1 Enables the generation of idle interrupt requests #1 SPOE Parity Mode 1 read-write 0 Selects even parity for use in transmission and reception #0 1 Selects odd parity for use in transmission and reception #1 SPPE Parity Enable 0 read-write 0 Does not add the parity bit to transmit data and does not check the parity bit of receive data #0 1 Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1) #1 SPDCR SPI Data Control Register 0xB 8 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPLW SPI Word Access/Halfword Access Specification 5 read-write 0 SPDR_HA is valid to access in halfwords #0 1 SPDR is valid (to access in words). #1 SPRDTD RSPI Receive/Transmit Data Selection 4 read-write 0 SPDR values are read from the receive buffer #0 1 SPDR values are read from the transmit buffer (but only if the transmit buffer is empty) #1 SPDR SPI Data Register 0x4 32 read-write n 0x0 0x0 SPDR SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR. 0 31 read-write SPDR_HA SPI Data Register ( halfword access ) SPDR 0x4 16 read-write n 0x0 0x0 SPDR_HA SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA. 0 15 read-write SPND SPI Next-Access Delay Register 0xE 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SPNDL SPI Next-Access Delay Setting 0 2 read-write 000 1 RSPCK + 2 PCLK #000 001 2 RSPCK + 2 PCLK #001 010 3 RSPCK + 2 PCLK #010 011 4 RSPCK + 2 PCLK #011 100 5 RSPCK + 2 PCLK #100 101 6 RSPCK + 2 PCLK #101 110 7 RSPCK + 2 PCLK #110 111 8 RSPCK + 2 PCLK #111 SPPCR SPI Pin Control Register 0x2 8 read-write n 0x0 0x0 MOIFE MOSI Idle Value Fixing Enable 5 read-write 0 MOSI output value equals final data from previous transfer #0 1 MOSI output value equals the value set in the MOIFV bit #1 MOIFV MOSI Idle Fixed Value 4 read-write 0 The level output on the MOSIn pin during MOSI idling corresponds to low. #0 1 The level output on the MOSIn pin during MOSI idling corresponds to high. #1 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write SPLP RSPI Loopback 0 read-write 0 Normal mode #0 1 Loopback mode (data is inverted for transmission) #1 SPLP2 RSPI Loopback 2 1 read-write 0 Normal mode #0 1 Loopback mode (data is not inverted for transmission) #1 SPSR SPI Status Register 0x3 8 read-write n 0x0 0x0 IDLNF SPI Idle Flag 1 read-only 0 SPI is in the idle state #0 1 SPI is in the transfer state #1 MODF Mode Fault Error Flag 2 read-write zeroToClear modify 0 Neither mode fault error nor underrun error occurs #0 1 A mode fault error or an underrun error occurs. #1 OVRF Overrun Error Flag 0 read-write zeroToClear modify 0 No overrun error occurs #0 1 An overrun error occurs #1 PERF Parity Error Flag 3 read-write zeroToClear modify 0 No parity error occurs #0 1 A parity error occurs #1 Reserved This bit is read as 0. The write value should be 0. 6 read-write SPRF SPI Receive Buffer Full Flag 7 read-write zeroToClear modify 0 No valid data in SPDR #0 1 Valid data found in SPDR #1 SPTEF SPI Transmit Buffer Empty Flag 5 read-write zeroToClear modify 0 Data found in the transmit buffer #0 1 No data in the transmit buffer #1 UDRF Underrun Error Flag(When MODF is 0, This bit is invalid.) 4 read-write zeroToClear modify 0 A mode fault error occurs (MODF=1) #0 1 An underrun error occurs (MODF=1) #1 SSLND SPI Slave Select Negation Delay Register 0xD 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SLNDL SSL Negation Delay Setting 0 2 read-write 000 1 RSPCK #000 001 2 RSPCK #001 010 3 RSPCK #010 011 4 RSPCK #011 100 5 RSPCK #100 101 6 RSPCK #101 110 7 RSPCK #110 111 8 RSPCK #111 SSLP SPI Slave Select Polarity Register 0x1 8 read-write n 0x0 0x0 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write SSL0P SSL0 Signal Polarity Setting 0 read-write 0 SSL0 signal is active low #0 1 SSL0 signal is active high #1 SSL1P SSL1 Signal Polarity Setting 1 read-write 0 SSL1 signal is active low #0 1 SSL1 signal is active high #1 SSL2P SSL2 Signal Polarity Setting 2 read-write 0 SSL2 signal is active low #0 1 SSL2 signal is active high #1 SSL3P SSL3 Signal Polarity Setting 3 read-write 0 SSL3 signal is active low #0 1 SSL3 signal is active high #1 SPMON CPU Stack Pointer Monitor SPMON 0x0 0x0 0x2 registers n 0x14 0xC registers n 0x4 0xE registers n MSPMPUCTL Stack Pointer Monitor Access Control Register 0x4 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled. #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write MSPMPUEA Main Stack Pointer (MSP) Monitor End Address Register 0xC 32 read-write n 0x0 0x0 MSPMPUEA Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 0 31 read-write MSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x0 16 read-write n 0x0 0x0 KEY Write Keyword The data written to these bits are not stored. 8 7 write-only others Writing to the OAD bit is invalid. 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 OAD Operation after detection 0 read-write 0 Non-maskable interrupt #0 1 Reset. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MSPMPUPT Stack Pointer Monitor Protection Register 0x6 16 read-write n 0x0 0x0 KEY Write Keyword The data written to these bits are not stored. 8 7 write-only others Writing to the PROTECT bit is invalid. 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 PROTECT Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MSPMPUSA Main Stack Pointer (MSP) Monitor Start Address Register 0x8 32 read-write n 0x0 0x0 MSPMPUSA Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 0 31 read-write PSPMPUCTL Stack Pointer Monitor Access Control Register 0x14 16 read-write n 0x0 0x0 ENABLE Stack Pointer Monitor Enable 0 read-write 0 Stack pointer monitor is disabled #0 1 Stack pointer monitor is enabled #1 ERROR Stack Pointer Monitor Error Flag 8 read-write 0 Stack pointer has not overflowed or underflowed #0 1 Stack pointer has overflowed or underflowed #1 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write PSPMPUEA Process Stack Pointer (PSP) Monitor End Address Register 0x1C 32 read-write n 0x0 0x0 PSPMPUEA Region end address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. 0 31 read-write PSPMPUOAD Stack Pointer Monitor Operation After Detection Register 0x10 16 read-write n 0x0 0x0 KEY Key CodeThe data written to these bits are not stored. 8 7 write-only others Writing to the OAD bit is invalid. 0xA5 Writing to the OAD bit is valid, when the KEY bits are written 0xA5. 0xA5 OAD Operation after detection 0 read-write 0 Non-maskable interrupt #0 1 Reset. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write PSPMPUPT Stack Pointer Monitor Protection Register 0x16 16 read-write n 0x0 0x0 KEY Key CodeThe data written to these bits are not stored. 8 7 write-only others Writing to the PROTECT bit is invalid. 0xA5 Writing to the PROTECT bit is valid, when the KEY bits are written 0xA5. 0xA5 PROTECT Protection register (PSPMPUAC, PSPMPUSA and PSPMPUSE) 0 read-write 0 Stack Pointer Monitor register writing is possible. #0 1 Stack Pointer Monitor register writing is protected. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write PSPMPUSA Process Stack Pointer (PSP) Monitor Start Address Register 0x18 32 read-write n 0x0 0x0 PSPMPUSA Region start address register Address where the region starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0. 0 31 read-write SRAM SRAM Control SRAM 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC0 0x5 registers n 0xD0 0x1 registers n 0xD4 0x1 registers n 0xD8 0x1 registers n ECC1STS ECC 1-Bit Error Status Register 0xC3 8 read-write n 0x0 0x0 ECC1ERR ECC 1-Bit Error Status 0 read-write zeroToClear modify 0 No 1-bit ECC error occurred #0 1 1-bit ECC error occurred #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ECC1STSEN ECC 1-Bit Error Information Update Enable Register 0xC2 8 read-write n 0x0 0x0 E1STSEN ECC 1-Bit Error Information Update Enable 0 read-write 0 Disables updating of the 1-bit ECC error information. #0 1 Enables updating of the 1-bit ECC error information. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ECC2STS ECC 2-Bit Error Status Register 0xC1 8 read-write n 0x0 0x0 ECC2ERR ECC 2-Bit Error Status 0 read-write zeroToClear modify 0 No 2-bit ECC error occurred #0 1 2-bit ECC error occurred. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ECCETST ECC Test Control Register 0xD4 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write TSTBYP ECC Bypass Select 0 read-write 0 ECC bypass disabled. #0 1 ECC bypass enabled. #1 ECCMODE ECC Operating Mode Control Register 0xC0 8 read-write n 0x0 0x0 ECCMOD ECC Operating Mode Select 0 1 read-write 00 Disable ECC function #00 01 Setting prohibited #01 10 Enable ECC function without error checking #10 11 Enable ECC function with error checking #11 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write ECCOAD SRAM ECC Error Operation After Detection Register 0xD8 8 read-write n 0x0 0x0 OAD Operation after Detection 0 read-write 0 Non-maskable interrupt #0 1 Reset #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write ECCPRCR ECC Protection Register 0xC4 8 read-write n 0x0 0x0 ECCPRCR Register Write Control 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers #1 KW Write Key Code 1 6 write-only others Writing to the ECCRAMPRCR bit is invalid. 1111000 Writing to the ECCRAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 ECCPRCR2 ECC Protection Register 2 0xD0 8 read-write n 0x0 0x0 ECCPRCR2 Register Write Control 0 read-write 0 Disable writes to the protected registers #0 1 Enable writes to the protected registers. #1 KW2 Write Key Code 1 6 write-only others Writing to the ECCRAMPRCR2 bit is invalid. 1111000 These bits enable or disable writes to the ECCPRCR2 bit.. #1111000 PARIOAD SRAM Parity Error Operation After Detection Register 0x0 8 read-write n 0x0 0x0 OAD Operation after Detection 0 read-write 0 Non maskable interrupt. #0 1 Reset #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write SRAMPRCR SRAM Protection Register 0x4 8 read-write n 0x0 0x0 KW Write Key Code 1 6 write-only others Writing to the RAMPRCR bit is invalid. 1111000 Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b. #1111000 SRAMPRCR Register Write Control 0 read-write 0 Disable writes to protected registers #0 1 Enable writes to protected registers. #1 SSIE0 Serial Sound Interface Ver.2.0 SSIE0 0x0 0x0 0x8 registers n 0x10 0x18 registers n SSICR Control Register 0x0 32 read-write n 0x0 0x0 BCKP Selects Bit Clock Polarity 13 read-write 0 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a rising edge of SSIBCK) #0 1 SSILRCK/SSIFS and SSITXD0/SSIRXD0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0 are sampled at a falling edge of SSIBCK). #1 CKDV Selects Bit Clock Division Ratio 4 3 read-write 0000 AUDIO_MCK #0000 0001 AUDIO_MCK/2 #0001 0010 AUDIO_MCK/4 #0010 0011 AUDIO_MCK/8 #0011 0100 AUDIO_MCK/16 #0100 0101 AUDIO_MCK/32 #0101 0110 AUDIO_MCK/64 #0110 0111 AUDIO_MCK/128 #0111 1000 AUDIO_MCK/6 #1000 1001 AUDIO_MCK/12 #1001 1010 AUDIO_MCK/24 #1010 1011 AUDIO_MCK/48 #1011 1100 AUDIO_MCK/96 #1100 CKS Selects an Audio Clock for Master-mode Communication 30 read-write 0 Selects the AUDIO_CLK input #0 1 Selects the GTIOC1A (GPT output). #1 DEL Selects Serial Data Delay 8 read-write 0 Delay of one cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0 #0 1 No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0 In the monaural format, this bit controls the waveform of SSILRCK/SSIFS. #1 DWL Selects Data Word Length 19 2 read-write 000 8 bits #000 001 16 bits #001 010 18 bits #010 011 20 bits #011 100 22 bits #100 101 24 bits #101 110 32 bits #110 IIEN Idle Mode Interrupt Output Enable 25 read-write 0 Disables idle mode interrupt output #0 1 Enables idle mode interrupt output. #1 LRCKP Selects the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 12 read-write 0 The initial value is at a high level The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS #0 1 The initial value is at a low level The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS. #1 MST Master Enable 14 read-write 0 Slave-mode communication #0 1 Master-mode communication. #1 MUEN Mute Enable 3 read-write 0 Disables muting on the next frame boundary #0 1 Enables muting on the next frame boundary. #1 PDTA Selects Placement Data Alignment 9 read-write 0 Left-justifies placement data (SSIFTDR, SSIFRDR) #0 1 Right-justifies placement data (SSIFTDR, SSIFRDR). #1 REN Receive Enable 0 read-write 0 Disables the receive operation. #0 1 Enables the receive operation. #1 Reserved This bit is read as 0. The write value should be 0. 31 read-write Reserved These bits are read as 000. The write value should be 000. 22 2 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write ROIEN Receive Overflow Interrupt Output Enable 26 read-write 0 Disables receive overflow interrupt output #0 1 Enables receive overflow interrupt output. #1 RUIEN Receive Underflow Interrupt Output Enable 27 read-write 0 Disables receive underflow interrupt output #0 1 Enables receive underflow interrupt output. #1 SDTA Selects Serial Data Alignment 10 read-write 0 Transmits and receives serial data first and then padding bits #0 1 Transmit and receives padding bits first and then serial data. #1 SPDP Selects Serial Padding Polarity 11 read-write 0 Padding data is at a low level #0 1 Padding data is at a high level. #1 SWL Selects System Word Length 16 2 read-write 000 8 bits #000 001 16 bits #001 010 24 bits #010 011 32 bits #011 100 48 bits #100 101 64 bits #101 110 128 bits #110 111 256 bits. #111 TEN Transmit Enable 1 read-write 0 Disables the transmit operation. #0 1 Enables the transmit operation. #1 TOIEN Transmit Overflow Interrupt Output Enable 28 read-write 0 Disables transmit overflow interrupt output #0 1 Enables transmit overflow interrupt output. #1 TUIEN Transmit Underflow Interrupt Output Enable 29 read-write 0 Disables transmit underflow interrupt output #0 1 Enables transmit underflow interrupt output. #1 SSIFCR FIFO Control Register 0x10 32 read-write n 0x0 0x0 AUCKE AUDIO_MCK Enable in Mastermode Communication 31 read-write 0 Disables supply of AUDIO_MCK #0 1 Enables supply of AUDIO_MCK. #1 BSW Byte Swap Enable 11 read-write 0 Disables byte swap #0 1 Enables byte swap #1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 17 13 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RFRST Receive FIFO Data Register Reset 0 read-write 0 Clears a receive data FIFO reset condition #0 1 Sets a receive data FIFO reset condition. #1 RIE Receive Data Full Interrupt Output Enable 2 read-write 0 Disables receive data full interrupts #0 1 Enables receive data full interrupts. #1 SSIRST Software Reset 16 read-write 0 Clears a software reset condition #0 1 Sets a software reset condition. #1 TFRST Transmit FIFO Data Register Reset 1 read-write 0 Clears a transmit data FIFO reset condition #0 1 Sets a transmit data FIFO reset condition. #1 TIE Transmit Data Empty Interrupt Output Enable 3 read-write 0 Disables transmit data empty interrupts #0 1 Enables transmit data empty interrupts. #1 SSIFRDR Receive FIFO Data Register 0x1C 32 read-only n 0x0 0x0 SSIFRDR Receive FIFO data. 0 31 read-only SSIFSR FIFO Status Register 0x14 32 read-write n 0x0 0x0 RDC Number of Receive FIFO Data Indication FlagNumber of receive FIFO data indication flag. 8 3 read-only RDF Receive Data Full Flag 0 read-write zeroToClear modify 0 The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS #0 1 The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one. #1 Reserved These bits are read as 0000. The write value should be 0000. 28 3 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write Reserved These bits are read as 0000000. The write value should be 0000000. 17 6 read-write TDC Number of Transmit FIFO Data Indication FlagNumber of transmit FIFO data indication flag. 24 3 read-only TDE Transmit Data Empty Flag 16 read-write zeroToClear modify 0 The free space of SSIFTDR is not more than the value of SSISCR.TDES #0 1 The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one. #1 SSIFTDR Transmit FIFO Data Register 0x18 32 write-only n 0x0 0x0 SSIFTDR Transmit FIFO Data 0 31 write-only SSISCR Status Control Register 0x24 32 read-write n 0x0 0x0 RDFS RDF Setting Condition Select 0 2 read-write 000 SSIFRDR has one stage or more data size #000 001 SSIFRDR has two stages or more data size (snip) #001 110 SSIFRDR has seven stages or more data size #110 111 SSIFRDR has eight stages or more data size. #111 Reserved These bits are read as 0000000000000000. The write value should be 0000000000000000. 16 15 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write TDES TDE Setting Condition Select 8 2 read-write 000 SSIFTDR has one stage or more free space #000 001 SSIFTDR has two stages or more free space (snip) #001 110 SSIFTDR has seven stages or more free space #110 111 SSIFTDR has eight stages or more free space. #111 SSISR Status Register 0x4 32 read-write n 0x0 0x0 IIRQ Idle Mode Status Flag 25 read-only 0 In the communication state #0 1 In the idle state #1 Reserved These bits are read as 00. The write value should be 00. 30 1 read-write Reserved These bits are read as 00. The write value should be 00. 30 1 read-write ROIRQ Receive Overflow Error Status Flag 26 read-write 0 No receive overflow error is generated #0 1 A receive overflow error is generated. #1 RUIRQ Receive Underflow Error Status Flag 27 read-write 0 No receive underflow error is generated #0 1 A receive underflow error is generated. #1 TOIRQ Transmit Overflow Error Status Flag 28 read-write 0 No transmit overflow error is generated #0 1 A transmit overflow error is generated. #1 TUIRQ Transmit Underflow Error Status flag 29 read-write 0 No transmit underflow error is generated #0 1 A transmit underflow error is generated. #1 SSITDMR TDM Mode Register 0x20 32 read-write n 0x0 0x0 BCKASTP Whether to Enable Stopping BCK Output When SSIE is in Idle Status 9 read-write 0 Always outputs BCK to the SSIBCK pin #0 1 Automatically controls output of BCK to the SSIBCK pin. #1 LRCONT Whether to Enable LRCK/FS Continuation 8 read-write 0 Disables LRCK/FS continuation #0 1 Enables LRCK/FS continuation. #1 OMOD Audio Format Select 0 1 read-write 00 I2S format #00 01 Setting prohibited #01 10 Monaural format #10 11 Setting prohibited. #11 Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write Reserved These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000. 10 21 read-write SYSTEM System Control SYSTEM 0x0 0x1C 0x4 registers n 0x20 0x5 registers n 0x26 0x1 registers n 0x2A 0x2 registers n 0x30 0x3 registers n 0x36 0x3 registers n 0x3C 0x1 registers n 0x3E 0x4 registers n 0x3FE 0x2 registers n 0x40E 0x1 registers n 0x410 0x2 registers n 0x413 0x1 registers n 0x417 0x5 registers n 0x41D 0x3 registers n 0x480 0x2 registers n 0x490 0x1 registers n 0x492 0x1 registers n 0x4B0 0x3 registers n 0x4B4 0x1 registers n 0x4B6 0x1 registers n 0x4B8 0x8 registers n 0x50 0x1 registers n 0x500 0x200 registers n 0x52 0x1 registers n 0x61 0x2 registers n 0x92 0x1 registers n 0x94 0x1 registers n 0x98 0x5 registers n 0x9E 0x1 registers n 0x9F 0x1 registers n 0xA0 0x1 registers n 0xA2 0x1 registers n 0xA5 0x1 registers n 0xAA 0x1 registers n 0xC 0x2 registers n 0xC0 0x2 registers n 0xC6 0x1 registers n 0xD0 0x1 registers n 0xE0 0x4 registers n 0xE1 0x4 registers n BCKCR External Bus Clock Control Register 0x30 8 read-write n 0x0 0x0 BCLKDIV EBCLK Pin Output Select 0 read-write 0 BCLK #0 1 BCLK/2 #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write BKRACR Backup Register Access Control Register 0xC6 8 read-write n 0x0 0x0 BKRACS Backup Register Access Control Register 0 2 read-write others Setting prohibited 000 Access control disable. When System clock source is SOSC or LOCO. #000 110 Access control enable. System clock source is other than SOSC or LOCO. #110 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write CKOCR Clock Out Control Register 0x3E 8 read-write n 0x0 0x0 CKODIV Clock out input frequency Division Select 4 2 read-write 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 111 /128 #111 CKOEN Clock out enable 7 read-write 0 Clock Out disable #0 1 Clock Out enable #1 CKOSEL Clock out source select 0 2 read-write others Setting prohibited 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 MOSC #011 100 SOSC #100 Reserved This bit is read as 0. The write value should be 0. 3 read-write EBCKOCR External Bus Clock Output Control Register 0x52 8 read-write n 0x0 0x0 EBCKOEN EBCLK Pin Output Control 0 read-write 0 BCLK pin output is disabled. (Fixed high) #0 1 BCLK pin output is enabled #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write FLSTOP Flash Operation Control Register 0x9E 8 read-write n 0x0 0x0 FLSTOP Selecting ON/OFF of the Flash Memory Operation 0 read-write 0 Code flash and data flash memory operates #0 1 Code flash and data flash memory stops. #1 FLSTPF Flash Memory Operation Status Flag 4 read-write 0 Transition completed #0 1 During transition (from the flash-stop-status to flash-operating-status or vice versa) #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write HOCOCR High-Speed On-Chip Oscillator Control Register 0x36 8 read-write n 0x0 0x0 HCSTP HOCO Stop 0 read-write 0 HOCO is operating. #0 1 HOCO is stopped. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write HOCOUTCR HOCO User Trimming Control Register 0x62 8 read-write n 0x0 0x0 HOCOUTRM HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO trimming bits 0 7 read-write HOCOWTCR High-Speed On-Chip Oscillator Wait Control Register 0xA5 8 read-write n 0x0 0x0 HSTS HOCO wait time setting 0 2 read-write others Setting prohibited 101 If HOCO frequency is other than 64MHz, should set the value to 101b. #101 110 If HOCO frequency = 64MHz, should set the value to 110b. #110 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write LOCOCR Low-Speed On-Chip Oscillator Control Register 0x490 8 read-write n 0x0 0x0 LCSTP LOCO Stop 0 read-write 0 LOCO is operating. #0 1 LOCO is stopped. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write LOCOUTCR LOCO User Trimming Control Register 0x492 8 read-write n 0x0 0x0 LOCOUTRM LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO trimming bits 0 7 read-write LVCMPCR Voltage Monitor Circuit Control Register 0x417 8 read-write n 0x0 0x0 LVD1E Voltage Detection 1 Enable 5 read-write 0 Voltage detection 1 circuit disabled #0 1 Voltage detection 1 circuit enabled #1 LVD2E Voltage Detection 2 Enable 6 read-write 0 Voltage detection 2 circuit disabled #0 1 Voltage detection 2 circuit enabled #1 Reserved These bits are read as 00. The write value should be 00. 2 1 read-write Reserved This bit is read as 0. The write value should be 0. 4 read-write Reserved These bits are read as 00. The write value should be 00. 2 1 read-write Reserved These bits are read as 00. The write value should be 00. 2 1 read-write LVD1CR0 Voltage Monitor %s Circuit Control Register 0 0x41A 8 read-write n 0x0 0x0 CMPE Voltage Monitor Circuit Comparison Result Output Enable 2 read-write 0 Voltage Monitor circuit comparison result output disabled. #0 1 Voltage Monitor circuit comparison result output enabled. #1 Reserved These bits are read as 000. The write value should be 000. 3 2 read-write Reserved These bits are read as 000. The write value should be 000. 3 2 read-write RI Voltage Monitor Circuit Mode Select 6 read-write 0 Voltage Monitor interrupt during Vdet1 passage #0 1 Voltage Monitor reset enabled when the voltage falls to and below Vdet1 #1 RIE Voltage Monitor Interrupt/Reset Enable 0 read-write 0 Disabled #0 1 Enabled #1 RN Voltage Monitor Reset Negate Select 7 read-write 0 Negation follows a stabilization time (tLVD) after VCC > Vdet1 is detected. #0 1 Negation follows a stabilization time (tLVD) after assertion of the LVD reset. #1 LVD1CR1 Voltage Monitor %s Circuit Control Register 1 0xE0 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor Interrupt Generation Condition Select 0 1 read-write 00 When VCC>=Vdet (rise) is detected #00 01 When VCC #01 10 When drop and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write LVD1SR Voltage Monitor %s Circuit Status Register 0xE1 8 read-write n 0x0 0x0 DET Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. 0 read-write zeroToClear modify 0 Not detected #0 1 Vdet1 passage detection #1 MON Voltage Monitor 1 Signal Monitor Flag 1 read-only 0 VCC < Vdet #0 1 VCC >= Vdet or MON bit is disabled #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write LVD2CR0 Voltage Monitor %s Circuit Control Register 0 0x41B 8 read-write n 0x0 0x0 CMPE Voltage Monitor Circuit Comparison Result Output Enable 2 read-write 0 Voltage Monitor circuit comparison result output disabled. #0 1 Voltage Monitor circuit comparison result output enabled. #1 Reserved These bits are read as 000. The write value should be 000. 3 2 read-write Reserved These bits are read as 000. The write value should be 000. 3 2 read-write RI Voltage Monitor Circuit Mode Select 6 read-write 0 Voltage Monitor interrupt during Vdet1 passage #0 1 Voltage Monitor reset enabled when the voltage falls to and below Vdet1 #1 RIE Voltage Monitor Interrupt/Reset Enable 0 read-write 0 Disabled #0 1 Enabled #1 RN Voltage Monitor Reset Negate Select 7 read-write 0 Negation follows a stabilization time (tLVD) after VCC > Vdet1 is detected. #0 1 Negation follows a stabilization time (tLVD) after assertion of the LVD reset. #1 LVD2CR1 Voltage Monitor %s Circuit Control Register 1 0xE2 8 read-write n 0x0 0x0 IDTSEL Voltage Monitor Interrupt Generation Condition Select 0 1 read-write 00 When VCC>=Vdet (rise) is detected #00 01 When VCC #01 10 When drop and rise are detected #10 11 Settings prohibited #11 IRQSEL Voltage Monitor Interrupt Type Select 2 read-write 0 Non-maskable interrupt #0 1 Maskable interrupt #1 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write LVD2SR Voltage Monitor %s Circuit Status Register 0xE3 8 read-write n 0x0 0x0 DET Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0. 0 read-write zeroToClear modify 0 Not detected #0 1 Vdet1 passage detection #1 MON Voltage Monitor 1 Signal Monitor Flag 1 read-only 0 VCC < Vdet #0 1 VCC >= Vdet or MON bit is disabled #1 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write LVDLVLR Voltage Detection Level Select Register 0x418 8 read-write n 0x0 0x0 LVD1LVL Voltage Detection 1 Level Select (Standard voltage during drop in voltage) 0 4 read-write others Setting prohibited 00000 4.29V (Vdet1_0) #00000 00001 4.14V (Vdet1_1) #00001 00010 4.02V (Vdet1_2) #00010 00011 3.84V (Vdet1_3) #00011 00100 3.10V (Vdet1_4) #00100 00101 3.00V (Vdet1_5) #00101 00110 2.90V (Vdet1_6) #00110 00111 2.79V (Vdet1_7) #00111 01000 2.68V (Vdet1_8) #01000 01001 2.58V (Vdet1_9) #01001 01010 2.48V (Vdet1_A) #01010 01011 2.20V (Vdet1_B) #01011 01100 1.96V (Vdet1_C) #01100 01101 1.86V (Vdet1_D) #01101 01110 1.75V (Vdet1_E) #01110 01111 1.65V (Vdet1_F) #01111 LVD2LVL Voltage Detection 2 Level Select (Standard voltage during drop in voltage) 5 2 read-write others Setting prohibited. 000 4.29V (Vdet2_0) #000 001 4.14V (Vdet2_1) #001 010 4.02V (Vdet2_2) #010 011 3.84V (Vdet2_3) #011 MEMWAIT Memory Wait Cycle Control Register 0x31 8 read-write n 0x0 0x0 MEMWAIT Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz). 0 read-write 0 no wait #0 1 wait #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MOCOCR Middle-Speed On-Chip Oscillator Control Register 0x38 8 read-write n 0x0 0x0 MCSTP MOCO Stop 0 read-write 0 MOCO is operating. #0 1 MOCO is stopped. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MOCOUTCR MOCO User Trimming Control Register 0x61 8 read-write n 0x0 0x0 MOCOUTRM MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO trimming bits 0 7 read-write MOMCR Main Clock Oscillator Mode Oscillation Control Register 0x413 8 read-write n 0x0 0x0 MODRV1 Main Clock Oscillator Drive Capability 1 Switching 3 read-write 0 10 MHz to 20 MHz #0 1 1 MHz to 10 MHz. #1 MOSEL Main Clock Oscillator Switching 6 read-write 0 Resonator #0 1 External clock input #1 Reserved These bits are read as 00. The write value should be 00. 4 1 read-write Reserved These bits are read as 00. The write value should be 00. 4 1 read-write Reserved These bits are read as 00. The write value should be 00. 4 1 read-write MOSCCR Main Clock Oscillator Control Register 0x32 8 read-write n 0x0 0x0 MOSTP Main Clock Oscillator StopNote: MOMCR register must be set before setting MOSTP to 0. 0 read-write 0 Main clock oscillator is operating. #0 1 Main clock oscillator is stopped. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write MOSCWTCR Main Clock Oscillator Wait Control Register 0xA2 8 read-write n 0x0 0x0 MSTS Main clock oscillator wait time setting 0 3 read-write others Setting prohibited 0000 Wait time = 2 cycles (0.25 us) #0000 0001 Wait time = 1024 cycles (128 us) #0001 0010 Wait time = 2048 cycles (256 us) #0010 0011 Wait time = 4096 cycles (512 us) #0011 0100 Wait time = 8192 cycles (1024 us) #0100 0101 Wait time = 16384 cycles (2048 us) (value after reset) #0101 0110 Wait time = 32768 cycles (4096 us) #0110 0111 Wait time = 65536 cycles (8192 us) #0111 1000 Wait time = 131072 cycles (16384 us) #1000 1001 Wait time = 262144 cycles (32768 us). #1001 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write MSTPCRA Module Stop Control Register A 0x1C 32 read-write n 0x0 0x0 MSTPA0 RAM0 Module Stop 0 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA22 DMA Controller/Data Transfer Controller Module Stop 22 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 MSTPA6 ECCRAM Module Stop 6 read-write 0 Cancel the module-stop state #0 1 Enter the module-stop state #1 Reserved These bits are read as 111111111111111. The write value should be 111111111111111. 7 14 read-write Reserved These bits are read as 111111111111111. The write value should be 111111111111111. 7 14 read-write Reserved These bits are read as 111111111111111. The write value should be 111111111111111. 7 14 read-write OPCCR Operating Power Control Register 0xA0 8 read-write n 0x0 0x0 OPCM Operating Power Control Mode Select 0 1 read-write 00 High-speed mode #00 01 Middle-speed mode #01 10 Low-voltage mode #10 11 Low-speed mode #11 OPCMTSF Operating Power Control Mode Transition Status Flag 4 read-write 0 Transition completed #0 1 During transition #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write OSCSF Oscillation Stabilization Flag Register 0x3C 8 read-only n 0x0 0x0 HOCOSF HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1. 0 read-only 0 The HOCO clock is stopped or oscillation of the HOCO clock has not yet become stable. #0 1 Oscillation of the HOCO clock is stable so the clock is available for use as the system clock. #1 MOSCSF Main Clock Oscillation Stabilization Flag 3 read-only 0 MOSTP = 1 (stopping the main clock oscillator) or oscillation of the main clock has not yet become stable. #0 1 Oscillation of the main clock is stable so the clock is available for use as the system clock. #1 PLLSF PLL Clock Oscillation Stabilization Flag 5 read-only 0 The PLL clock is stopped or oscillation of the PLL clock has not yet become stable. #0 1 Oscillation of the PLL clock is stable so the clock is available for use as the system clock. #1 Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 4 read-only Reserved This bit is read as 0. 4 read-only OSTDCR Oscillation Stop Detection Control Register 0x40 8 read-write n 0x0 0x0 OSTDE Oscillation Stop Detection Function Enable 7 read-write 0 Oscillation stop detection function is disabled. #0 1 Oscillation stop detection function is enabled. #1 OSTDIE Oscillation Stop Detection Interrupt Enable 0 read-write 0 The oscillation stop detection interrupt is disabled. Oscillation stop detection is not notified to the POEG. #0 1 The oscillation stop detection interrupt is enabled. Oscillation stop detection is notified to the POEG. #1 Reserved These bits are read as 000000. The write value should be 000000. 1 5 read-write OSTDSR Oscillation Stop Detection Status Register 0x41 8 read-write n 0x0 0x0 OSTDF Oscillation Stop Detection Flag 0 read-write zeroToClear modify 0 The main clock oscillation stop has not been detected. #0 1 The main clock oscillation stop has been detected. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write PLLCCR2 PLL Clock Control Register2 0x2B 8 read-write n 0x0 0x0 PLLMUL PLL Frequency Multiplication Factor Select 0 4 read-write others x PLLMUL[4:0] +1 1111 Settings prohibited. #1111 PLODIV PLL Output Frequency Division Ratio Select 6 1 read-write 00 /1. #00 01 /2. #01 10 /4. #10 11 Setting prohibited. #11 Reserved This bit is read as 0. The write value should be 0. 5 read-write PLLCR PLL Control Register 0x2A 8 read-write n 0x0 0x0 PLLSTP PLL Stop Control 0 read-write 0 PLL is operating. #0 1 PLL is stopped. #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write PRCR Protect Register 0x3FE 16 read-write n 0x0 0x0 PRC0 Protect Bit 0 0 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRC1 Protect Bit 1 1 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRC3 Protect Bit 3 3 read-write 0 Writes protected. #0 1 Writes not protected. #1 PRKEY PRC Key Code 8 7 write-only others Disables writing to the PRCR register. 0x5A Enables writing to the PRCR register. 0x5A Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write PSMCR Power Save Memory Control Register 0x9F 8 read-write n 0x0 0x0 PSMC Power save memory control. 0 1 read-write others Setting prohibited. 00 All RAM is on Software Standby mode. #00 01 48KB RAM is on in Software Standby mode. #01 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write RSTSR0 Reset Status Register 0 0x410 8 read-write n 0x0 0x0 LVD0RF Voltage Monitor 0 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 1 read-write zeroToClear modify 0 Voltage Monitor 0 reset not detected. #0 1 Voltage Monitor 0 reset detected. #1 LVD1RF Voltage Monitor 1 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 2 read-write zeroToClear modify 0 Voltage Monitor 1 reset not detected. #0 1 Voltage Monitor 1 reset detected. #1 LVD2RF Voltage Monitor 2 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 3 read-write zeroToClear modify 0 Voltage Monitor 2 reset not detected. #0 1 Voltage Monitor 2 reset detected. #1 PORF Power-On Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1. 0 read-write zeroToClear modify 0 Power-on reset not detected. #0 1 Power-on reset detected. #1 Reserved These bits are read as 0000. The write value should be 0000. 4 3 read-write RSTSR1 Reset Status Register 1 0xC0 16 read-write n 0x0 0x0 BUSMRF Bus Master MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 11 read-write zeroToClear modify 0 Bus Master MPU reset not detected. #0 1 Bus Master MPU reset detected. #1 BUSSRF Bus Slave MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 10 read-write zeroToClear modify 0 Bus Slave MPU reset not detected. #0 1 Bus Slave MPU reset detected. #1 IWDTRF Independent Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 0 read-write zeroToClear modify 0 Independent watchdog timer reset not detected. #0 1 Independent watchdog timer reset detected. #1 REERF RAM ECC Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 9 read-write zeroToClear modify 0 RAM ECC error reset not detected. #0 1 RAM ECC error reset detected. #1 Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write RPERF RAM Parity Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 8 read-write zeroToClear modify 0 RAM parity error reset not detected. #0 1 RAM parity error reset detected. #1 SPERF SP Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 12 read-write zeroToClear modify 0 SP error reset not detected. #0 1 SP error reset detected. #1 SWRF Software Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 2 read-write zeroToClear modify 0 Software reset not detected. #0 1 Software reset detected. #1 WDTRF Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1. 1 read-write zeroToClear modify 0 Watchdog timer reset not detected. #0 1 Watchdog timer reset detected. #1 RSTSR2 Reset Status Register 2 0x411 8 read-write n 0x0 0x0 CWSF Cold/Warm Start Determination FlagNote: Only 1 can be written to set the flag. 0 read-write oneToSet modify 0 Cold start #0 1 Warm start #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write SBYCR Standby Control Register 0xC 16 read-write n 0x0 0x0 OPE Output Port Enable 14 read-write 0 In software standby mode Address output pins, Data output pins, and other bus control signal output pins are set to the high-impedance state. In snooze mode, the status of the address bus and bus control signals are same as before entering software standby mode. #0 1 In software standby mode Address output pins, Data output pins, and other bus control signal output pins retain the output state. #1 Reserved These bits are read as 00000000000000. The write value should be 00000000000000. 0 13 read-write SSBY Software Standby 15 read-write 0 Sleep mode #0 1 Software Standby mode #1 SCKDIVCR System Clock Division Control Register 0x20 32 read-write n 0x0 0x0 BCK External Bus Clock (BCLK) Select 16 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 FCK Flash IF Clock (FCLK) Select 28 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 ICK System Clock (ICLK) Select 24 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 PCKA Peripheral Module Clock A (PCLKA) Select 12 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 PCKB Peripheral Module Clock B (PCLKB) Select 8 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 PCKC Peripheral Module Clock C (PCLKC) Select 4 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 PCKD Peripheral Module Clock D (PCLKD) Select 0 2 read-write others Setting prohibited 000 /1 #000 001 /2 #001 010 /4 #010 011 /8 #011 100 /16 #100 101 /32 #101 110 /64 #110 Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 27 read-write Reserved These bits are read as 00000. The write value should be 00000. 19 4 read-write Reserved This bit is read as 0. The write value should be 0. 15 read-write Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write SCKSCR System Clock Source Control Register 0x26 8 read-write n 0x0 0x0 CKSEL Clock Source SelectSelecting the system clock source faster than 32MHz(system clock source > 32MHz ) is prohibit when SCKDIVCR.ICK[2:0] bits select the division-by-1 and MEMWAIT.MEMWAIT =0. 0 2 read-write others Setting prohibited 000 HOCO #000 001 MOCO #001 010 LOCO #010 011 Main clock oscillator #011 100 Sub-clock oscillator #100 101 PLL #101 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write SLCDSCKCR Segment LCD Source Clock Control Register 0x50 8 read-write n 0x0 0x0 LCDSCKEN LCD Source Clock Out Enable 7 read-write 0 LCD source clock out disabled #0 1 LCD source clock out enabled. #1 LCDSCKSEL LCD Source Clock (LCDSRCCLK) Select 0 2 read-write others Settings other than above are prohibited. 000 LOCO #000 001 SOSC #001 010 MOSC #010 100 HOCO #100 Reserved These bits are read as 0000. The write value should be 0000. 3 3 read-write SNZCR Snooze Control Register 0x92 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 2 4 read-write RXDREQEN RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode. 0 read-write 0 Ignore RXD0 falling edge in Software Standby mode. #0 1 Accept RXD0 falling edge in Standby mode as a request to transit to Snooze mode. #1 SNZDTCEN DTC Enable in Snooze Mode 1 read-write 0 Disable DTC operation #0 1 Enable DTC operation #1 SNZE Snooze Mode Enable 7 read-write 0 Disable Snooze Mode #0 1 Enable Snooze Mode #1 SNZEDCR Snooze End Control Register 0x94 8 read-write n 0x0 0x0 AD0MATED ADC140 Compare Match Snooze End Enable 3 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AD0UMTED ADC140 Compare Mismatch Snooze End Enable 4 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 AGT1UNFED AGT1 Underflow Snooze End Enable 0 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCNZRED Not Last DTC Transmission Completion Snooze End Enable 2 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 DTCZRED Last DTC Transmission Completion Snooze End Enable 1 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 Reserved These bits are read as 00. The write value should be 00. 5 1 read-write SCI0UMTED SCI0 Address Mismatch Snooze End Enable 7 read-write 0 Disable the Snooze End request #0 1 Enable the Snooze End request #1 SNZREQCR Snooze Request Control Register 0x98 32 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 18 4 read-write Reserved These bits are read as 00. The write value should be 00. 26 1 read-write Reserved These bits are read as 00000. The write value should be 00000. 18 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 18 4 read-write SNZREQEN0 Snooze Request Enable 0Enable IRQ0 pin snooze request 0 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN1 Snooze Request Enable 1Enable IRQ1 pin snooze request 1 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN10 Snooze Request Enable 10Enable IRQ10 pin snooze request 10 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN11 Snooze Request Enable 11Enable IRQ11 pin snooze request 11 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN12 Snooze Request Enable 12Enable IRQ12 pin snooze request 12 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN13 Snooze Request Enable 13Enable IRQ13 pin snooze request 13 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN14 Snooze Request Enable 14Enable IRQ14 pin snooze request 14 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN15 Snooze Request Enable 15Enable IRQ15 pin snooze request 15 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN17 Snooze Request Enable 17Enable KR snooze request 17 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN2 Snooze Request Enable 2Enable IRQ2 pin snooze request 2 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN23 Snooze Request Enable 23Enable RTC alarm snooze request 23 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN24 Snooze Request Enable 24Enable RTC alarm snooze request 24 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN25 Snooze Request Enable 25Enable RTC period snooze request 25 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN28 Snooze Request Enable 28Enable AGT1 underflow snooze request 28 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN29 Snooze Request Enable 29Enable AGT1 compare match A snooze request 29 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN3 Snooze Request Enable 3Enable IRQ3 pin snooze request 3 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN30 Snooze Request Enable 30Enable AGT1 compare match B snooze request 30 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN4 Snooze Request Enable 4Enable IRQ4 pin snooze request 4 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN5 Snooze Request Enable 5Enable IRQ5 pin snooze request 5 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN6 Snooze Request Enable 6Enable IRQ6 pin snooze request 6 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN7 Snooze Request Enable 7Enable IRQ7 pin snooze request 7 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN8 Snooze Request Enable 8Enable IRQ8 pin snooze request 8 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SNZREQEN9 Snooze Request Enable 9Enable IRQ9 pin snooze request 9 read-write 0 Disable snooze request #0 1 Enable snooze request #1 SOMCR Sub Clock Oscillator Mode Control Register 0x481 8 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write SODRV Sub-Clock Oscillator Drive Capability Switching 0 1 read-write 00 Normal mode #00 01 Low power mode 1 #01 10 Low power mode 2 #10 11 Low power mode 3. #11 SOPCCR Sub Operating Power Control Register 0xAA 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write SOPCM Sub Operating Power Control Mode Select 0 read-write 0 Other than Subosc-speed mode #0 1 Subosc-speed mode #1 SOPCMTSF Sub Operating Power Control Mode Transition Status Flag 4 read-only 0 Transition completed #0 1 During transition #1 SOSCCR Sub-Clock Oscillator Control Register 0x480 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write SOSTP Sub-Clock Oscillator Stop 0 read-write 0 Sub-clock oscillator is operating. #0 1 Sub-clock oscillator is stopped. #1 SYOCDCR System Control OCD Control Register 0x40E 8 read-write n 0x0 0x0 DBGEN Debugger Enable bit 7 read-write 0 On-chip debugger is disabled #0 1 On-chip debugger is enabled #1 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write TRCKCR Trace Clock Control Register 0x3F 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 4 2 read-write TRCK Trace Clock operating frequency select 0 3 read-write others Setting prohibited 0000 /1 #0000 0001 /2(value after reset) #0001 0010 /4 #0010 TRCKEN Trace Clock operating enable 7 read-write 0 Operation disabled #0 1 Operation enabled. #1 USBCKCR USB Clock Control register 0xD0 8 read-write n 0x0 0x0 HSTS USB Clock Source Select 0 read-write 0 PLL(Value after reset) #0 1 HOCO #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write VBTBKR0 VBATT Backup Register [%s] 0x500 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR1 VBATT Backup Register [%s] 0x501 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR10 VBATT Backup Register [%s] 0x50A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR100 VBATT Backup Register [%s] 0x564 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR101 VBATT Backup Register [%s] 0x565 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR102 VBATT Backup Register [%s] 0x566 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR103 VBATT Backup Register [%s] 0x567 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR104 VBATT Backup Register [%s] 0x568 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR105 VBATT Backup Register [%s] 0x569 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR106 VBATT Backup Register [%s] 0x56A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR107 VBATT Backup Register [%s] 0x56B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR108 VBATT Backup Register [%s] 0x56C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR109 VBATT Backup Register [%s] 0x56D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR11 VBATT Backup Register [%s] 0x50B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR110 VBATT Backup Register [%s] 0x56E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR111 VBATT Backup Register [%s] 0x56F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR112 VBATT Backup Register [%s] 0x570 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR113 VBATT Backup Register [%s] 0x571 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR114 VBATT Backup Register [%s] 0x572 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR115 VBATT Backup Register [%s] 0x573 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR116 VBATT Backup Register [%s] 0x574 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR117 VBATT Backup Register [%s] 0x575 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR118 VBATT Backup Register [%s] 0x576 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR119 VBATT Backup Register [%s] 0x577 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR12 VBATT Backup Register [%s] 0x50C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR120 VBATT Backup Register [%s] 0x578 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR121 VBATT Backup Register [%s] 0x579 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR122 VBATT Backup Register [%s] 0x57A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR123 VBATT Backup Register [%s] 0x57B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR124 VBATT Backup Register [%s] 0x57C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR125 VBATT Backup Register [%s] 0x57D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR126 VBATT Backup Register [%s] 0x57E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR127 VBATT Backup Register [%s] 0x57F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR128 VBATT Backup Register [%s] 0x580 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR129 VBATT Backup Register [%s] 0x581 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR13 VBATT Backup Register [%s] 0x50D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR130 VBATT Backup Register [%s] 0x582 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR131 VBATT Backup Register [%s] 0x583 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR132 VBATT Backup Register [%s] 0x584 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR133 VBATT Backup Register [%s] 0x585 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR134 VBATT Backup Register [%s] 0x586 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR135 VBATT Backup Register [%s] 0x587 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR136 VBATT Backup Register [%s] 0x588 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR137 VBATT Backup Register [%s] 0x589 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR138 VBATT Backup Register [%s] 0x58A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR139 VBATT Backup Register [%s] 0x58B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR14 VBATT Backup Register [%s] 0x50E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR140 VBATT Backup Register [%s] 0x58C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR141 VBATT Backup Register [%s] 0x58D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR142 VBATT Backup Register [%s] 0x58E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR143 VBATT Backup Register [%s] 0x58F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR144 VBATT Backup Register [%s] 0x590 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR145 VBATT Backup Register [%s] 0x591 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR146 VBATT Backup Register [%s] 0x592 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR147 VBATT Backup Register [%s] 0x593 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR148 VBATT Backup Register [%s] 0x594 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR149 VBATT Backup Register [%s] 0x595 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR15 VBATT Backup Register [%s] 0x50F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR150 VBATT Backup Register [%s] 0x596 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR151 VBATT Backup Register [%s] 0x597 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR152 VBATT Backup Register [%s] 0x598 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR153 VBATT Backup Register [%s] 0x599 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR154 VBATT Backup Register [%s] 0x59A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR155 VBATT Backup Register [%s] 0x59B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR156 VBATT Backup Register [%s] 0x59C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR157 VBATT Backup Register [%s] 0x59D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR158 VBATT Backup Register [%s] 0x59E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR159 VBATT Backup Register [%s] 0x59F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR16 VBATT Backup Register [%s] 0x510 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR160 VBATT Backup Register [%s] 0x5A0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR161 VBATT Backup Register [%s] 0x5A1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR162 VBATT Backup Register [%s] 0x5A2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR163 VBATT Backup Register [%s] 0x5A3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR164 VBATT Backup Register [%s] 0x5A4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR165 VBATT Backup Register [%s] 0x5A5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR166 VBATT Backup Register [%s] 0x5A6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR167 VBATT Backup Register [%s] 0x5A7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR168 VBATT Backup Register [%s] 0x5A8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR169 VBATT Backup Register [%s] 0x5A9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR17 VBATT Backup Register [%s] 0x511 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR170 VBATT Backup Register [%s] 0x5AA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR171 VBATT Backup Register [%s] 0x5AB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR172 VBATT Backup Register [%s] 0x5AC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR173 VBATT Backup Register [%s] 0x5AD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR174 VBATT Backup Register [%s] 0x5AE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR175 VBATT Backup Register [%s] 0x5AF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR176 VBATT Backup Register [%s] 0x5B0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR177 VBATT Backup Register [%s] 0x5B1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR178 VBATT Backup Register [%s] 0x5B2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR179 VBATT Backup Register [%s] 0x5B3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR18 VBATT Backup Register [%s] 0x512 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR180 VBATT Backup Register [%s] 0x5B4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR181 VBATT Backup Register [%s] 0x5B5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR182 VBATT Backup Register [%s] 0x5B6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR183 VBATT Backup Register [%s] 0x5B7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR184 VBATT Backup Register [%s] 0x5B8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR185 VBATT Backup Register [%s] 0x5B9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR186 VBATT Backup Register [%s] 0x5BA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR187 VBATT Backup Register [%s] 0x5BB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR188 VBATT Backup Register [%s] 0x5BC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR189 VBATT Backup Register [%s] 0x5BD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR19 VBATT Backup Register [%s] 0x513 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR190 VBATT Backup Register [%s] 0x5BE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR191 VBATT Backup Register [%s] 0x5BF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR192 VBATT Backup Register [%s] 0x5C0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR193 VBATT Backup Register [%s] 0x5C1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR194 VBATT Backup Register [%s] 0x5C2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR195 VBATT Backup Register [%s] 0x5C3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR196 VBATT Backup Register [%s] 0x5C4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR197 VBATT Backup Register [%s] 0x5C5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR198 VBATT Backup Register [%s] 0x5C6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR199 VBATT Backup Register [%s] 0x5C7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR2 VBATT Backup Register [%s] 0x502 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR20 VBATT Backup Register [%s] 0x514 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR200 VBATT Backup Register [%s] 0x5C8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR201 VBATT Backup Register [%s] 0x5C9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR202 VBATT Backup Register [%s] 0x5CA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR203 VBATT Backup Register [%s] 0x5CB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR204 VBATT Backup Register [%s] 0x5CC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR205 VBATT Backup Register [%s] 0x5CD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR206 VBATT Backup Register [%s] 0x5CE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR207 VBATT Backup Register [%s] 0x5CF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR208 VBATT Backup Register [%s] 0x5D0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR209 VBATT Backup Register [%s] 0x5D1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR21 VBATT Backup Register [%s] 0x515 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR210 VBATT Backup Register [%s] 0x5D2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR211 VBATT Backup Register [%s] 0x5D3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR212 VBATT Backup Register [%s] 0x5D4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR213 VBATT Backup Register [%s] 0x5D5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR214 VBATT Backup Register [%s] 0x5D6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR215 VBATT Backup Register [%s] 0x5D7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR216 VBATT Backup Register [%s] 0x5D8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR217 VBATT Backup Register [%s] 0x5D9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR218 VBATT Backup Register [%s] 0x5DA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR219 VBATT Backup Register [%s] 0x5DB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR22 VBATT Backup Register [%s] 0x516 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR220 VBATT Backup Register [%s] 0x5DC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR221 VBATT Backup Register [%s] 0x5DD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR222 VBATT Backup Register [%s] 0x5DE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR223 VBATT Backup Register [%s] 0x5DF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR224 VBATT Backup Register [%s] 0x5E0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR225 VBATT Backup Register [%s] 0x5E1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR226 VBATT Backup Register [%s] 0x5E2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR227 VBATT Backup Register [%s] 0x5E3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR228 VBATT Backup Register [%s] 0x5E4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR229 VBATT Backup Register [%s] 0x5E5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR23 VBATT Backup Register [%s] 0x517 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR230 VBATT Backup Register [%s] 0x5E6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR231 VBATT Backup Register [%s] 0x5E7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR232 VBATT Backup Register [%s] 0x5E8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR233 VBATT Backup Register [%s] 0x5E9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR234 VBATT Backup Register [%s] 0x5EA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR235 VBATT Backup Register [%s] 0x5EB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR236 VBATT Backup Register [%s] 0x5EC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR237 VBATT Backup Register [%s] 0x5ED 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR238 VBATT Backup Register [%s] 0x5EE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR239 VBATT Backup Register [%s] 0x5EF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR24 VBATT Backup Register [%s] 0x518 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR240 VBATT Backup Register [%s] 0x5F0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR241 VBATT Backup Register [%s] 0x5F1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR242 VBATT Backup Register [%s] 0x5F2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR243 VBATT Backup Register [%s] 0x5F3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR244 VBATT Backup Register [%s] 0x5F4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR245 VBATT Backup Register [%s] 0x5F5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR246 VBATT Backup Register [%s] 0x5F6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR247 VBATT Backup Register [%s] 0x5F7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR248 VBATT Backup Register [%s] 0x5F8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR249 VBATT Backup Register [%s] 0x5F9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR25 VBATT Backup Register [%s] 0x519 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR250 VBATT Backup Register [%s] 0x5FA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR251 VBATT Backup Register [%s] 0x5FB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR252 VBATT Backup Register [%s] 0x5FC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR253 VBATT Backup Register [%s] 0x5FD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR254 VBATT Backup Register [%s] 0x5FE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR255 VBATT Backup Register [%s] 0x5FF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR256 VBATT Backup Register [%s] 0x600 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR257 VBATT Backup Register [%s] 0x601 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR258 VBATT Backup Register [%s] 0x602 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR259 VBATT Backup Register [%s] 0x603 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR26 VBATT Backup Register [%s] 0x51A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR260 VBATT Backup Register [%s] 0x604 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR261 VBATT Backup Register [%s] 0x605 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR262 VBATT Backup Register [%s] 0x606 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR263 VBATT Backup Register [%s] 0x607 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR264 VBATT Backup Register [%s] 0x608 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR265 VBATT Backup Register [%s] 0x609 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR266 VBATT Backup Register [%s] 0x60A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR267 VBATT Backup Register [%s] 0x60B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR268 VBATT Backup Register [%s] 0x60C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR269 VBATT Backup Register [%s] 0x60D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR27 VBATT Backup Register [%s] 0x51B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR270 VBATT Backup Register [%s] 0x60E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR271 VBATT Backup Register [%s] 0x60F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR272 VBATT Backup Register [%s] 0x610 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR273 VBATT Backup Register [%s] 0x611 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR274 VBATT Backup Register [%s] 0x612 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR275 VBATT Backup Register [%s] 0x613 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR276 VBATT Backup Register [%s] 0x614 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR277 VBATT Backup Register [%s] 0x615 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR278 VBATT Backup Register [%s] 0x616 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR279 VBATT Backup Register [%s] 0x617 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR28 VBATT Backup Register [%s] 0x51C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR280 VBATT Backup Register [%s] 0x618 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR281 VBATT Backup Register [%s] 0x619 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR282 VBATT Backup Register [%s] 0x61A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR283 VBATT Backup Register [%s] 0x61B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR284 VBATT Backup Register [%s] 0x61C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR285 VBATT Backup Register [%s] 0x61D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR286 VBATT Backup Register [%s] 0x61E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR287 VBATT Backup Register [%s] 0x61F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR288 VBATT Backup Register [%s] 0x620 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR289 VBATT Backup Register [%s] 0x621 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR29 VBATT Backup Register [%s] 0x51D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR290 VBATT Backup Register [%s] 0x622 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR291 VBATT Backup Register [%s] 0x623 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR292 VBATT Backup Register [%s] 0x624 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR293 VBATT Backup Register [%s] 0x625 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR294 VBATT Backup Register [%s] 0x626 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR295 VBATT Backup Register [%s] 0x627 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR296 VBATT Backup Register [%s] 0x628 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR297 VBATT Backup Register [%s] 0x629 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR298 VBATT Backup Register [%s] 0x62A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR299 VBATT Backup Register [%s] 0x62B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR3 VBATT Backup Register [%s] 0x503 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR30 VBATT Backup Register [%s] 0x51E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR300 VBATT Backup Register [%s] 0x62C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR301 VBATT Backup Register [%s] 0x62D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR302 VBATT Backup Register [%s] 0x62E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR303 VBATT Backup Register [%s] 0x62F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR304 VBATT Backup Register [%s] 0x630 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR305 VBATT Backup Register [%s] 0x631 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR306 VBATT Backup Register [%s] 0x632 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR307 VBATT Backup Register [%s] 0x633 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR308 VBATT Backup Register [%s] 0x634 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR309 VBATT Backup Register [%s] 0x635 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR31 VBATT Backup Register [%s] 0x51F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR310 VBATT Backup Register [%s] 0x636 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR311 VBATT Backup Register [%s] 0x637 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR312 VBATT Backup Register [%s] 0x638 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR313 VBATT Backup Register [%s] 0x639 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR314 VBATT Backup Register [%s] 0x63A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR315 VBATT Backup Register [%s] 0x63B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR316 VBATT Backup Register [%s] 0x63C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR317 VBATT Backup Register [%s] 0x63D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR318 VBATT Backup Register [%s] 0x63E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR319 VBATT Backup Register [%s] 0x63F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR32 VBATT Backup Register [%s] 0x520 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR320 VBATT Backup Register [%s] 0x640 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR321 VBATT Backup Register [%s] 0x641 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR322 VBATT Backup Register [%s] 0x642 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR323 VBATT Backup Register [%s] 0x643 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR324 VBATT Backup Register [%s] 0x644 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR325 VBATT Backup Register [%s] 0x645 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR326 VBATT Backup Register [%s] 0x646 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR327 VBATT Backup Register [%s] 0x647 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR328 VBATT Backup Register [%s] 0x648 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR329 VBATT Backup Register [%s] 0x649 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR33 VBATT Backup Register [%s] 0x521 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR330 VBATT Backup Register [%s] 0x64A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR331 VBATT Backup Register [%s] 0x64B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR332 VBATT Backup Register [%s] 0x64C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR333 VBATT Backup Register [%s] 0x64D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR334 VBATT Backup Register [%s] 0x64E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR335 VBATT Backup Register [%s] 0x64F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR336 VBATT Backup Register [%s] 0x650 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR337 VBATT Backup Register [%s] 0x651 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR338 VBATT Backup Register [%s] 0x652 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR339 VBATT Backup Register [%s] 0x653 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR34 VBATT Backup Register [%s] 0x522 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR340 VBATT Backup Register [%s] 0x654 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR341 VBATT Backup Register [%s] 0x655 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR342 VBATT Backup Register [%s] 0x656 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR343 VBATT Backup Register [%s] 0x657 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR344 VBATT Backup Register [%s] 0x658 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR345 VBATT Backup Register [%s] 0x659 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR346 VBATT Backup Register [%s] 0x65A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR347 VBATT Backup Register [%s] 0x65B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR348 VBATT Backup Register [%s] 0x65C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR349 VBATT Backup Register [%s] 0x65D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR35 VBATT Backup Register [%s] 0x523 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR350 VBATT Backup Register [%s] 0x65E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR351 VBATT Backup Register [%s] 0x65F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR352 VBATT Backup Register [%s] 0x660 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR353 VBATT Backup Register [%s] 0x661 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR354 VBATT Backup Register [%s] 0x662 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR355 VBATT Backup Register [%s] 0x663 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR356 VBATT Backup Register [%s] 0x664 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR357 VBATT Backup Register [%s] 0x665 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR358 VBATT Backup Register [%s] 0x666 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR359 VBATT Backup Register [%s] 0x667 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR36 VBATT Backup Register [%s] 0x524 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR360 VBATT Backup Register [%s] 0x668 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR361 VBATT Backup Register [%s] 0x669 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR362 VBATT Backup Register [%s] 0x66A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR363 VBATT Backup Register [%s] 0x66B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR364 VBATT Backup Register [%s] 0x66C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR365 VBATT Backup Register [%s] 0x66D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR366 VBATT Backup Register [%s] 0x66E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR367 VBATT Backup Register [%s] 0x66F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR368 VBATT Backup Register [%s] 0x670 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR369 VBATT Backup Register [%s] 0x671 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR37 VBATT Backup Register [%s] 0x525 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR370 VBATT Backup Register [%s] 0x672 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR371 VBATT Backup Register [%s] 0x673 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR372 VBATT Backup Register [%s] 0x674 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR373 VBATT Backup Register [%s] 0x675 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR374 VBATT Backup Register [%s] 0x676 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR375 VBATT Backup Register [%s] 0x677 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR376 VBATT Backup Register [%s] 0x678 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR377 VBATT Backup Register [%s] 0x679 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR378 VBATT Backup Register [%s] 0x67A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR379 VBATT Backup Register [%s] 0x67B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR38 VBATT Backup Register [%s] 0x526 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR380 VBATT Backup Register [%s] 0x67C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR381 VBATT Backup Register [%s] 0x67D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR382 VBATT Backup Register [%s] 0x67E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR383 VBATT Backup Register [%s] 0x67F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR384 VBATT Backup Register [%s] 0x680 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR385 VBATT Backup Register [%s] 0x681 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR386 VBATT Backup Register [%s] 0x682 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR387 VBATT Backup Register [%s] 0x683 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR388 VBATT Backup Register [%s] 0x684 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR389 VBATT Backup Register [%s] 0x685 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR39 VBATT Backup Register [%s] 0x527 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR390 VBATT Backup Register [%s] 0x686 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR391 VBATT Backup Register [%s] 0x687 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR392 VBATT Backup Register [%s] 0x688 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR393 VBATT Backup Register [%s] 0x689 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR394 VBATT Backup Register [%s] 0x68A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR395 VBATT Backup Register [%s] 0x68B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR396 VBATT Backup Register [%s] 0x68C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR397 VBATT Backup Register [%s] 0x68D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR398 VBATT Backup Register [%s] 0x68E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR399 VBATT Backup Register [%s] 0x68F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR4 VBATT Backup Register [%s] 0x504 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR40 VBATT Backup Register [%s] 0x528 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR400 VBATT Backup Register [%s] 0x690 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR401 VBATT Backup Register [%s] 0x691 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR402 VBATT Backup Register [%s] 0x692 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR403 VBATT Backup Register [%s] 0x693 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR404 VBATT Backup Register [%s] 0x694 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR405 VBATT Backup Register [%s] 0x695 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR406 VBATT Backup Register [%s] 0x696 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR407 VBATT Backup Register [%s] 0x697 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR408 VBATT Backup Register [%s] 0x698 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR409 VBATT Backup Register [%s] 0x699 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR41 VBATT Backup Register [%s] 0x529 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR410 VBATT Backup Register [%s] 0x69A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR411 VBATT Backup Register [%s] 0x69B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR412 VBATT Backup Register [%s] 0x69C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR413 VBATT Backup Register [%s] 0x69D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR414 VBATT Backup Register [%s] 0x69E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR415 VBATT Backup Register [%s] 0x69F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR416 VBATT Backup Register [%s] 0x6A0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR417 VBATT Backup Register [%s] 0x6A1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR418 VBATT Backup Register [%s] 0x6A2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR419 VBATT Backup Register [%s] 0x6A3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR42 VBATT Backup Register [%s] 0x52A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR420 VBATT Backup Register [%s] 0x6A4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR421 VBATT Backup Register [%s] 0x6A5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR422 VBATT Backup Register [%s] 0x6A6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR423 VBATT Backup Register [%s] 0x6A7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR424 VBATT Backup Register [%s] 0x6A8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR425 VBATT Backup Register [%s] 0x6A9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR426 VBATT Backup Register [%s] 0x6AA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR427 VBATT Backup Register [%s] 0x6AB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR428 VBATT Backup Register [%s] 0x6AC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR429 VBATT Backup Register [%s] 0x6AD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR43 VBATT Backup Register [%s] 0x52B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR430 VBATT Backup Register [%s] 0x6AE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR431 VBATT Backup Register [%s] 0x6AF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR432 VBATT Backup Register [%s] 0x6B0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR433 VBATT Backup Register [%s] 0x6B1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR434 VBATT Backup Register [%s] 0x6B2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR435 VBATT Backup Register [%s] 0x6B3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR436 VBATT Backup Register [%s] 0x6B4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR437 VBATT Backup Register [%s] 0x6B5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR438 VBATT Backup Register [%s] 0x6B6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR439 VBATT Backup Register [%s] 0x6B7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR44 VBATT Backup Register [%s] 0x52C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR440 VBATT Backup Register [%s] 0x6B8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR441 VBATT Backup Register [%s] 0x6B9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR442 VBATT Backup Register [%s] 0x6BA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR443 VBATT Backup Register [%s] 0x6BB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR444 VBATT Backup Register [%s] 0x6BC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR445 VBATT Backup Register [%s] 0x6BD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR446 VBATT Backup Register [%s] 0x6BE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR447 VBATT Backup Register [%s] 0x6BF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR448 VBATT Backup Register [%s] 0x6C0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR449 VBATT Backup Register [%s] 0x6C1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR45 VBATT Backup Register [%s] 0x52D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR450 VBATT Backup Register [%s] 0x6C2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR451 VBATT Backup Register [%s] 0x6C3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR452 VBATT Backup Register [%s] 0x6C4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR453 VBATT Backup Register [%s] 0x6C5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR454 VBATT Backup Register [%s] 0x6C6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR455 VBATT Backup Register [%s] 0x6C7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR456 VBATT Backup Register [%s] 0x6C8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR457 VBATT Backup Register [%s] 0x6C9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR458 VBATT Backup Register [%s] 0x6CA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR459 VBATT Backup Register [%s] 0x6CB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR46 VBATT Backup Register [%s] 0x52E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR460 VBATT Backup Register [%s] 0x6CC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR461 VBATT Backup Register [%s] 0x6CD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR462 VBATT Backup Register [%s] 0x6CE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR463 VBATT Backup Register [%s] 0x6CF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR464 VBATT Backup Register [%s] 0x6D0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR465 VBATT Backup Register [%s] 0x6D1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR466 VBATT Backup Register [%s] 0x6D2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR467 VBATT Backup Register [%s] 0x6D3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR468 VBATT Backup Register [%s] 0x6D4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR469 VBATT Backup Register [%s] 0x6D5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR47 VBATT Backup Register [%s] 0x52F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR470 VBATT Backup Register [%s] 0x6D6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR471 VBATT Backup Register [%s] 0x6D7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR472 VBATT Backup Register [%s] 0x6D8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR473 VBATT Backup Register [%s] 0x6D9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR474 VBATT Backup Register [%s] 0x6DA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR475 VBATT Backup Register [%s] 0x6DB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR476 VBATT Backup Register [%s] 0x6DC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR477 VBATT Backup Register [%s] 0x6DD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR478 VBATT Backup Register [%s] 0x6DE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR479 VBATT Backup Register [%s] 0x6DF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR48 VBATT Backup Register [%s] 0x530 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR480 VBATT Backup Register [%s] 0x6E0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR481 VBATT Backup Register [%s] 0x6E1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR482 VBATT Backup Register [%s] 0x6E2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR483 VBATT Backup Register [%s] 0x6E3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR484 VBATT Backup Register [%s] 0x6E4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR485 VBATT Backup Register [%s] 0x6E5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR486 VBATT Backup Register [%s] 0x6E6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR487 VBATT Backup Register [%s] 0x6E7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR488 VBATT Backup Register [%s] 0x6E8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR489 VBATT Backup Register [%s] 0x6E9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR49 VBATT Backup Register [%s] 0x531 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR490 VBATT Backup Register [%s] 0x6EA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR491 VBATT Backup Register [%s] 0x6EB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR492 VBATT Backup Register [%s] 0x6EC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR493 VBATT Backup Register [%s] 0x6ED 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR494 VBATT Backup Register [%s] 0x6EE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR495 VBATT Backup Register [%s] 0x6EF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR496 VBATT Backup Register [%s] 0x6F0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR497 VBATT Backup Register [%s] 0x6F1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR498 VBATT Backup Register [%s] 0x6F2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR499 VBATT Backup Register [%s] 0x6F3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR5 VBATT Backup Register [%s] 0x505 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR50 VBATT Backup Register [%s] 0x532 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR500 VBATT Backup Register [%s] 0x6F4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR501 VBATT Backup Register [%s] 0x6F5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR502 VBATT Backup Register [%s] 0x6F6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR503 VBATT Backup Register [%s] 0x6F7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR504 VBATT Backup Register [%s] 0x6F8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR505 VBATT Backup Register [%s] 0x6F9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR506 VBATT Backup Register [%s] 0x6FA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR507 VBATT Backup Register [%s] 0x6FB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR508 VBATT Backup Register [%s] 0x6FC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR509 VBATT Backup Register [%s] 0x6FD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR51 VBATT Backup Register [%s] 0x533 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR510 VBATT Backup Register [%s] 0x6FE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR511 VBATT Backup Register [%s] 0x6FF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR52 VBATT Backup Register [%s] 0x534 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR53 VBATT Backup Register [%s] 0x535 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR54 VBATT Backup Register [%s] 0x536 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR55 VBATT Backup Register [%s] 0x537 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR56 VBATT Backup Register [%s] 0x538 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR57 VBATT Backup Register [%s] 0x539 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR58 VBATT Backup Register [%s] 0x53A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR59 VBATT Backup Register [%s] 0x53B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR6 VBATT Backup Register [%s] 0x506 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR60 VBATT Backup Register [%s] 0x53C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR61 VBATT Backup Register [%s] 0x53D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR62 VBATT Backup Register [%s] 0x53E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR63 VBATT Backup Register [%s] 0x53F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR64 VBATT Backup Register [%s] 0x540 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR65 VBATT Backup Register [%s] 0x541 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR66 VBATT Backup Register [%s] 0x542 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR67 VBATT Backup Register [%s] 0x543 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR68 VBATT Backup Register [%s] 0x544 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR69 VBATT Backup Register [%s] 0x545 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR7 VBATT Backup Register [%s] 0x507 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR70 VBATT Backup Register [%s] 0x546 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR71 VBATT Backup Register [%s] 0x547 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR72 VBATT Backup Register [%s] 0x548 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR73 VBATT Backup Register [%s] 0x549 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR74 VBATT Backup Register [%s] 0x54A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR75 VBATT Backup Register [%s] 0x54B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR76 VBATT Backup Register [%s] 0x54C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR77 VBATT Backup Register [%s] 0x54D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR78 VBATT Backup Register [%s] 0x54E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR79 VBATT Backup Register [%s] 0x54F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR8 VBATT Backup Register [%s] 0x508 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR80 VBATT Backup Register [%s] 0x550 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR81 VBATT Backup Register [%s] 0x551 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR82 VBATT Backup Register [%s] 0x552 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR83 VBATT Backup Register [%s] 0x553 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR84 VBATT Backup Register [%s] 0x554 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR85 VBATT Backup Register [%s] 0x555 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR86 VBATT Backup Register [%s] 0x556 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR87 VBATT Backup Register [%s] 0x557 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR88 VBATT Backup Register [%s] 0x558 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR89 VBATT Backup Register [%s] 0x559 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR9 VBATT Backup Register [%s] 0x509 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR90 VBATT Backup Register [%s] 0x55A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR91 VBATT Backup Register [%s] 0x55B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR92 VBATT Backup Register [%s] 0x55C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR93 VBATT Backup Register [%s] 0x55D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR94 VBATT Backup Register [%s] 0x55E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR95 VBATT Backup Register [%s] 0x55F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR96 VBATT Backup Register [%s] 0x560 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR97 VBATT Backup Register [%s] 0x561 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR98 VBATT Backup Register [%s] 0x562 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR99 VBATT Backup Register [%s] 0x563 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[0] VBATT Backup Register [%s] 0xA00 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[100] VBATT Backup Register [%s] 0x211BA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[101] VBATT Backup Register [%s] 0x2171F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[102] VBATT Backup Register [%s] 0x21C85 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[103] VBATT Backup Register [%s] 0x221EC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[104] VBATT Backup Register [%s] 0x22754 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[105] VBATT Backup Register [%s] 0x22CBD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[106] VBATT Backup Register [%s] 0x23227 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[107] VBATT Backup Register [%s] 0x23792 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[108] VBATT Backup Register [%s] 0x23CFE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[109] VBATT Backup Register [%s] 0x2426B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[10] VBATT Backup Register [%s] 0x3C37 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[110] VBATT Backup Register [%s] 0x247D9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[111] VBATT Backup Register [%s] 0x24D48 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[112] VBATT Backup Register [%s] 0x252B8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[113] VBATT Backup Register [%s] 0x25829 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[114] VBATT Backup Register [%s] 0x25D9B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[115] VBATT Backup Register [%s] 0x2630E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[116] VBATT Backup Register [%s] 0x26882 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[117] VBATT Backup Register [%s] 0x26DF7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[118] VBATT Backup Register [%s] 0x2736D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[119] VBATT Backup Register [%s] 0x278E4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[11] VBATT Backup Register [%s] 0x4142 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[120] VBATT Backup Register [%s] 0x27E5C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[121] VBATT Backup Register [%s] 0x283D5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[122] VBATT Backup Register [%s] 0x2894F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[123] VBATT Backup Register [%s] 0x28ECA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[124] VBATT Backup Register [%s] 0x29446 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[125] VBATT Backup Register [%s] 0x299C3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[126] VBATT Backup Register [%s] 0x29F41 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[127] VBATT Backup Register [%s] 0x2A4C0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[128] VBATT Backup Register [%s] 0x2AA40 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[129] VBATT Backup Register [%s] 0x2AFC1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[12] VBATT Backup Register [%s] 0x464E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[130] VBATT Backup Register [%s] 0x2B543 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[131] VBATT Backup Register [%s] 0x2BAC6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[132] VBATT Backup Register [%s] 0x2C04A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[133] VBATT Backup Register [%s] 0x2C5CF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[134] VBATT Backup Register [%s] 0x2CB55 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[135] VBATT Backup Register [%s] 0x2D0DC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[136] VBATT Backup Register [%s] 0x2D664 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[137] VBATT Backup Register [%s] 0x2DBED 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[138] VBATT Backup Register [%s] 0x2E177 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[139] VBATT Backup Register [%s] 0x2E702 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[13] VBATT Backup Register [%s] 0x4B5B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[140] VBATT Backup Register [%s] 0x2EC8E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[141] VBATT Backup Register [%s] 0x2F21B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[142] VBATT Backup Register [%s] 0x2F7A9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[143] VBATT Backup Register [%s] 0x2FD38 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[144] VBATT Backup Register [%s] 0x302C8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[145] VBATT Backup Register [%s] 0x30859 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[146] VBATT Backup Register [%s] 0x30DEB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[147] VBATT Backup Register [%s] 0x3137E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[148] VBATT Backup Register [%s] 0x31912 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[149] VBATT Backup Register [%s] 0x31EA7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[14] VBATT Backup Register [%s] 0x5069 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[150] VBATT Backup Register [%s] 0x3243D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[151] VBATT Backup Register [%s] 0x329D4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[152] VBATT Backup Register [%s] 0x32F6C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[153] VBATT Backup Register [%s] 0x33505 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[154] VBATT Backup Register [%s] 0x33A9F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[155] VBATT Backup Register [%s] 0x3403A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[156] VBATT Backup Register [%s] 0x345D6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[157] VBATT Backup Register [%s] 0x34B73 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[158] VBATT Backup Register [%s] 0x35111 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[159] VBATT Backup Register [%s] 0x356B0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[15] VBATT Backup Register [%s] 0x5578 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[160] VBATT Backup Register [%s] 0x35C50 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[161] VBATT Backup Register [%s] 0x361F1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[162] VBATT Backup Register [%s] 0x36793 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[163] VBATT Backup Register [%s] 0x36D36 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[164] VBATT Backup Register [%s] 0x372DA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[165] VBATT Backup Register [%s] 0x3787F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[166] VBATT Backup Register [%s] 0x37E25 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[167] VBATT Backup Register [%s] 0x383CC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[168] VBATT Backup Register [%s] 0x38974 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[169] VBATT Backup Register [%s] 0x38F1D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[16] VBATT Backup Register [%s] 0x5A88 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[170] VBATT Backup Register [%s] 0x394C7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[171] VBATT Backup Register [%s] 0x39A72 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[172] VBATT Backup Register [%s] 0x3A01E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[173] VBATT Backup Register [%s] 0x3A5CB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[174] VBATT Backup Register [%s] 0x3AB79 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[175] VBATT Backup Register [%s] 0x3B128 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[176] VBATT Backup Register [%s] 0x3B6D8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[177] VBATT Backup Register [%s] 0x3BC89 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[178] VBATT Backup Register [%s] 0x3C23B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[179] VBATT Backup Register [%s] 0x3C7EE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[17] VBATT Backup Register [%s] 0x5F99 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[180] VBATT Backup Register [%s] 0x3CDA2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[181] VBATT Backup Register [%s] 0x3D357 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[182] VBATT Backup Register [%s] 0x3D90D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[183] VBATT Backup Register [%s] 0x3DEC4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[184] VBATT Backup Register [%s] 0x3E47C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[185] VBATT Backup Register [%s] 0x3EA35 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[186] VBATT Backup Register [%s] 0x3EFEF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[187] VBATT Backup Register [%s] 0x3F5AA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[188] VBATT Backup Register [%s] 0x3FB66 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[189] VBATT Backup Register [%s] 0x40123 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[18] VBATT Backup Register [%s] 0x64AB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[190] VBATT Backup Register [%s] 0x406E1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[191] VBATT Backup Register [%s] 0x40CA0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[192] VBATT Backup Register [%s] 0x41260 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[193] VBATT Backup Register [%s] 0x41821 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[194] VBATT Backup Register [%s] 0x41DE3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[195] VBATT Backup Register [%s] 0x423A6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[196] VBATT Backup Register [%s] 0x4296A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[197] VBATT Backup Register [%s] 0x42F2F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[198] VBATT Backup Register [%s] 0x434F5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[199] VBATT Backup Register [%s] 0x43ABC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[19] VBATT Backup Register [%s] 0x69BE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[1] VBATT Backup Register [%s] 0xF01 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[200] VBATT Backup Register [%s] 0x44084 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[201] VBATT Backup Register [%s] 0x4464D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[202] VBATT Backup Register [%s] 0x44C17 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[203] VBATT Backup Register [%s] 0x451E2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[204] VBATT Backup Register [%s] 0x457AE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[205] VBATT Backup Register [%s] 0x45D7B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[206] VBATT Backup Register [%s] 0x46349 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[207] VBATT Backup Register [%s] 0x46918 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[208] VBATT Backup Register [%s] 0x46EE8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[209] VBATT Backup Register [%s] 0x474B9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[20] VBATT Backup Register [%s] 0x6ED2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[210] VBATT Backup Register [%s] 0x47A8B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[211] VBATT Backup Register [%s] 0x4805E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[212] VBATT Backup Register [%s] 0x48632 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[213] VBATT Backup Register [%s] 0x48C07 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[214] VBATT Backup Register [%s] 0x491DD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[215] VBATT Backup Register [%s] 0x497B4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[216] VBATT Backup Register [%s] 0x49D8C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[217] VBATT Backup Register [%s] 0x4A365 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[218] VBATT Backup Register [%s] 0x4A93F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[219] VBATT Backup Register [%s] 0x4AF1A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[21] VBATT Backup Register [%s] 0x73E7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[220] VBATT Backup Register [%s] 0x4B4F6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[221] VBATT Backup Register [%s] 0x4BAD3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[222] VBATT Backup Register [%s] 0x4C0B1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[223] VBATT Backup Register [%s] 0x4C690 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[224] VBATT Backup Register [%s] 0x4CC70 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[225] VBATT Backup Register [%s] 0x4D251 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[226] VBATT Backup Register [%s] 0x4D833 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[227] VBATT Backup Register [%s] 0x4DE16 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[228] VBATT Backup Register [%s] 0x4E3FA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[229] VBATT Backup Register [%s] 0x4E9DF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[22] VBATT Backup Register [%s] 0x78FD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[230] VBATT Backup Register [%s] 0x4EFC5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[231] VBATT Backup Register [%s] 0x4F5AC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[232] VBATT Backup Register [%s] 0x4FB94 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[233] VBATT Backup Register [%s] 0x5017D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[234] VBATT Backup Register [%s] 0x50767 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[235] VBATT Backup Register [%s] 0x50D52 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[236] VBATT Backup Register [%s] 0x5133E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[237] VBATT Backup Register [%s] 0x5192B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[238] VBATT Backup Register [%s] 0x51F19 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[239] VBATT Backup Register [%s] 0x52508 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[23] VBATT Backup Register [%s] 0x7E14 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[240] VBATT Backup Register [%s] 0x52AF8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[241] VBATT Backup Register [%s] 0x530E9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[242] VBATT Backup Register [%s] 0x536DB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[243] VBATT Backup Register [%s] 0x53CCE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[244] VBATT Backup Register [%s] 0x542C2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[245] VBATT Backup Register [%s] 0x548B7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[246] VBATT Backup Register [%s] 0x54EAD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[247] VBATT Backup Register [%s] 0x554A4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[248] VBATT Backup Register [%s] 0x55A9C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[249] VBATT Backup Register [%s] 0x56095 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[24] VBATT Backup Register [%s] 0x832C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[250] VBATT Backup Register [%s] 0x5668F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[251] VBATT Backup Register [%s] 0x56C8A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[252] VBATT Backup Register [%s] 0x57286 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[253] VBATT Backup Register [%s] 0x57883 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[254] VBATT Backup Register [%s] 0x57E81 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[255] VBATT Backup Register [%s] 0x58480 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[256] VBATT Backup Register [%s] 0x58A80 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[257] VBATT Backup Register [%s] 0x59081 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[258] VBATT Backup Register [%s] 0x59683 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[259] VBATT Backup Register [%s] 0x59C86 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[25] VBATT Backup Register [%s] 0x8845 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[260] VBATT Backup Register [%s] 0x5A28A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[261] VBATT Backup Register [%s] 0x5A88F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[262] VBATT Backup Register [%s] 0x5AE95 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[263] VBATT Backup Register [%s] 0x5B49C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[264] VBATT Backup Register [%s] 0x5BAA4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[265] VBATT Backup Register [%s] 0x5C0AD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[266] VBATT Backup Register [%s] 0x5C6B7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[267] VBATT Backup Register [%s] 0x5CCC2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[268] VBATT Backup Register [%s] 0x5D2CE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[269] VBATT Backup Register [%s] 0x5D8DB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[26] VBATT Backup Register [%s] 0x8D5F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[270] VBATT Backup Register [%s] 0x5DEE9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[271] VBATT Backup Register [%s] 0x5E4F8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[272] VBATT Backup Register [%s] 0x5EB08 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[273] VBATT Backup Register [%s] 0x5F119 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[274] VBATT Backup Register [%s] 0x5F72B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[275] VBATT Backup Register [%s] 0x5FD3E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[276] VBATT Backup Register [%s] 0x60352 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[277] VBATT Backup Register [%s] 0x60967 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[278] VBATT Backup Register [%s] 0x60F7D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[279] VBATT Backup Register [%s] 0x61594 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[27] VBATT Backup Register [%s] 0x927A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[280] VBATT Backup Register [%s] 0x61BAC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[281] VBATT Backup Register [%s] 0x621C5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[282] VBATT Backup Register [%s] 0x627DF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[283] VBATT Backup Register [%s] 0x62DFA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[284] VBATT Backup Register [%s] 0x63416 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[285] VBATT Backup Register [%s] 0x63A33 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[286] VBATT Backup Register [%s] 0x64051 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[287] VBATT Backup Register [%s] 0x64670 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[288] VBATT Backup Register [%s] 0x64C90 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[289] VBATT Backup Register [%s] 0x652B1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[28] VBATT Backup Register [%s] 0x9796 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[290] VBATT Backup Register [%s] 0x658D3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[291] VBATT Backup Register [%s] 0x65EF6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[292] VBATT Backup Register [%s] 0x6651A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[293] VBATT Backup Register [%s] 0x66B3F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[294] VBATT Backup Register [%s] 0x67165 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[295] VBATT Backup Register [%s] 0x6778C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[296] VBATT Backup Register [%s] 0x67DB4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[297] VBATT Backup Register [%s] 0x683DD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[298] VBATT Backup Register [%s] 0x68A07 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[299] VBATT Backup Register [%s] 0x69032 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[29] VBATT Backup Register [%s] 0x9CB3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[2] VBATT Backup Register [%s] 0x1403 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[300] VBATT Backup Register [%s] 0x6965E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[301] VBATT Backup Register [%s] 0x69C8B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[302] VBATT Backup Register [%s] 0x6A2B9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[303] VBATT Backup Register [%s] 0x6A8E8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[304] VBATT Backup Register [%s] 0x6AF18 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[305] VBATT Backup Register [%s] 0x6B549 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[306] VBATT Backup Register [%s] 0x6BB7B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[307] VBATT Backup Register [%s] 0x6C1AE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[308] VBATT Backup Register [%s] 0x6C7E2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[309] VBATT Backup Register [%s] 0x6CE17 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[30] VBATT Backup Register [%s] 0xA1D1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[310] VBATT Backup Register [%s] 0x6D44D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[311] VBATT Backup Register [%s] 0x6DA84 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[312] VBATT Backup Register [%s] 0x6E0BC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[313] VBATT Backup Register [%s] 0x6E6F5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[314] VBATT Backup Register [%s] 0x6ED2F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[315] VBATT Backup Register [%s] 0x6F36A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[316] VBATT Backup Register [%s] 0x6F9A6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[317] VBATT Backup Register [%s] 0x6FFE3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[318] VBATT Backup Register [%s] 0x70621 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[319] VBATT Backup Register [%s] 0x70C60 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[31] VBATT Backup Register [%s] 0xA6F0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[320] VBATT Backup Register [%s] 0x712A0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[321] VBATT Backup Register [%s] 0x718E1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[322] VBATT Backup Register [%s] 0x71F23 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[323] VBATT Backup Register [%s] 0x72566 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[324] VBATT Backup Register [%s] 0x72BAA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[325] VBATT Backup Register [%s] 0x731EF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[326] VBATT Backup Register [%s] 0x73835 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[327] VBATT Backup Register [%s] 0x73E7C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[328] VBATT Backup Register [%s] 0x744C4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[329] VBATT Backup Register [%s] 0x74B0D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[32] VBATT Backup Register [%s] 0xAC10 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[330] VBATT Backup Register [%s] 0x75157 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[331] VBATT Backup Register [%s] 0x757A2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[332] VBATT Backup Register [%s] 0x75DEE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[333] VBATT Backup Register [%s] 0x7643B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[334] VBATT Backup Register [%s] 0x76A89 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[335] VBATT Backup Register [%s] 0x770D8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[336] VBATT Backup Register [%s] 0x77728 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[337] VBATT Backup Register [%s] 0x77D79 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[338] VBATT Backup Register [%s] 0x783CB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[339] VBATT Backup Register [%s] 0x78A1E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[33] VBATT Backup Register [%s] 0xB131 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[340] VBATT Backup Register [%s] 0x79072 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[341] VBATT Backup Register [%s] 0x796C7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[342] VBATT Backup Register [%s] 0x79D1D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[343] VBATT Backup Register [%s] 0x7A374 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[344] VBATT Backup Register [%s] 0x7A9CC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[345] VBATT Backup Register [%s] 0x7B025 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[346] VBATT Backup Register [%s] 0x7B67F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[347] VBATT Backup Register [%s] 0x7BCDA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[348] VBATT Backup Register [%s] 0x7C336 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[349] VBATT Backup Register [%s] 0x7C993 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[34] VBATT Backup Register [%s] 0xB653 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[350] VBATT Backup Register [%s] 0x7CFF1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[351] VBATT Backup Register [%s] 0x7D650 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[352] VBATT Backup Register [%s] 0x7DCB0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[353] VBATT Backup Register [%s] 0x7E311 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[354] VBATT Backup Register [%s] 0x7E973 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[355] VBATT Backup Register [%s] 0x7EFD6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[356] VBATT Backup Register [%s] 0x7F63A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[357] VBATT Backup Register [%s] 0x7FC9F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[358] VBATT Backup Register [%s] 0x80305 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[359] VBATT Backup Register [%s] 0x8096C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[35] VBATT Backup Register [%s] 0xBB76 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[360] VBATT Backup Register [%s] 0x80FD4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[361] VBATT Backup Register [%s] 0x8163D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[362] VBATT Backup Register [%s] 0x81CA7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[363] VBATT Backup Register [%s] 0x82312 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[364] VBATT Backup Register [%s] 0x8297E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[365] VBATT Backup Register [%s] 0x82FEB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[366] VBATT Backup Register [%s] 0x83659 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[367] VBATT Backup Register [%s] 0x83CC8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[368] VBATT Backup Register [%s] 0x84338 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[369] VBATT Backup Register [%s] 0x849A9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[36] VBATT Backup Register [%s] 0xC09A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[370] VBATT Backup Register [%s] 0x8501B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[371] VBATT Backup Register [%s] 0x8568E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[372] VBATT Backup Register [%s] 0x85D02 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[373] VBATT Backup Register [%s] 0x86377 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[374] VBATT Backup Register [%s] 0x869ED 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[375] VBATT Backup Register [%s] 0x87064 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[376] VBATT Backup Register [%s] 0x876DC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[377] VBATT Backup Register [%s] 0x87D55 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[378] VBATT Backup Register [%s] 0x883CF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[379] VBATT Backup Register [%s] 0x88A4A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[37] VBATT Backup Register [%s] 0xC5BF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[380] VBATT Backup Register [%s] 0x890C6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[381] VBATT Backup Register [%s] 0x89743 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[382] VBATT Backup Register [%s] 0x89DC1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[383] VBATT Backup Register [%s] 0x8A440 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[384] VBATT Backup Register [%s] 0x8AAC0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[385] VBATT Backup Register [%s] 0x8B141 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[386] VBATT Backup Register [%s] 0x8B7C3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[387] VBATT Backup Register [%s] 0x8BE46 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[388] VBATT Backup Register [%s] 0x8C4CA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[389] VBATT Backup Register [%s] 0x8CB4F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[38] VBATT Backup Register [%s] 0xCAE5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[390] VBATT Backup Register [%s] 0x8D1D5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[391] VBATT Backup Register [%s] 0x8D85C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[392] VBATT Backup Register [%s] 0x8DEE4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[393] VBATT Backup Register [%s] 0x8E56D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[394] VBATT Backup Register [%s] 0x8EBF7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[395] VBATT Backup Register [%s] 0x8F282 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[396] VBATT Backup Register [%s] 0x8F90E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[397] VBATT Backup Register [%s] 0x8FF9B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[398] VBATT Backup Register [%s] 0x90629 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[399] VBATT Backup Register [%s] 0x90CB8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[39] VBATT Backup Register [%s] 0xD00C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[3] VBATT Backup Register [%s] 0x1906 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[400] VBATT Backup Register [%s] 0x91348 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[401] VBATT Backup Register [%s] 0x919D9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[402] VBATT Backup Register [%s] 0x9206B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[403] VBATT Backup Register [%s] 0x926FE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[404] VBATT Backup Register [%s] 0x92D92 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[405] VBATT Backup Register [%s] 0x93427 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[406] VBATT Backup Register [%s] 0x93ABD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[407] VBATT Backup Register [%s] 0x94154 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[408] VBATT Backup Register [%s] 0x947EC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[409] VBATT Backup Register [%s] 0x94E85 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[40] VBATT Backup Register [%s] 0xD534 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[410] VBATT Backup Register [%s] 0x9551F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[411] VBATT Backup Register [%s] 0x95BBA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[412] VBATT Backup Register [%s] 0x96256 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[413] VBATT Backup Register [%s] 0x968F3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[414] VBATT Backup Register [%s] 0x96F91 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[415] VBATT Backup Register [%s] 0x97630 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[416] VBATT Backup Register [%s] 0x97CD0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[417] VBATT Backup Register [%s] 0x98371 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[418] VBATT Backup Register [%s] 0x98A13 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[419] VBATT Backup Register [%s] 0x990B6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[41] VBATT Backup Register [%s] 0xDA5D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[420] VBATT Backup Register [%s] 0x9975A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[421] VBATT Backup Register [%s] 0x99DFF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[422] VBATT Backup Register [%s] 0x9A4A5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[423] VBATT Backup Register [%s] 0x9AB4C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[424] VBATT Backup Register [%s] 0x9B1F4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[425] VBATT Backup Register [%s] 0x9B89D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[426] VBATT Backup Register [%s] 0x9BF47 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[427] VBATT Backup Register [%s] 0x9C5F2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[428] VBATT Backup Register [%s] 0x9CC9E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[429] VBATT Backup Register [%s] 0x9D34B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[42] VBATT Backup Register [%s] 0xDF87 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[430] VBATT Backup Register [%s] 0x9D9F9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[431] VBATT Backup Register [%s] 0x9E0A8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[432] VBATT Backup Register [%s] 0x9E758 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[433] VBATT Backup Register [%s] 0x9EE09 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[434] VBATT Backup Register [%s] 0x9F4BB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[435] VBATT Backup Register [%s] 0x9FB6E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[436] VBATT Backup Register [%s] 0xA0222 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[437] VBATT Backup Register [%s] 0xA08D7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[438] VBATT Backup Register [%s] 0xA0F8D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[439] VBATT Backup Register [%s] 0xA1644 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[43] VBATT Backup Register [%s] 0xE4B2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[440] VBATT Backup Register [%s] 0xA1CFC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[441] VBATT Backup Register [%s] 0xA23B5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[442] VBATT Backup Register [%s] 0xA2A6F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[443] VBATT Backup Register [%s] 0xA312A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[444] VBATT Backup Register [%s] 0xA37E6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[445] VBATT Backup Register [%s] 0xA3EA3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[446] VBATT Backup Register [%s] 0xA4561 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[447] VBATT Backup Register [%s] 0xA4C20 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[448] VBATT Backup Register [%s] 0xA52E0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[449] VBATT Backup Register [%s] 0xA59A1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[44] VBATT Backup Register [%s] 0xE9DE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[450] VBATT Backup Register [%s] 0xA6063 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[451] VBATT Backup Register [%s] 0xA6726 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[452] VBATT Backup Register [%s] 0xA6DEA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[453] VBATT Backup Register [%s] 0xA74AF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[454] VBATT Backup Register [%s] 0xA7B75 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[455] VBATT Backup Register [%s] 0xA823C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[456] VBATT Backup Register [%s] 0xA8904 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[457] VBATT Backup Register [%s] 0xA8FCD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[458] VBATT Backup Register [%s] 0xA9697 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[459] VBATT Backup Register [%s] 0xA9D62 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[45] VBATT Backup Register [%s] 0xEF0B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[460] VBATT Backup Register [%s] 0xAA42E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[461] VBATT Backup Register [%s] 0xAAAFB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[462] VBATT Backup Register [%s] 0xAB1C9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[463] VBATT Backup Register [%s] 0xAB898 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[464] VBATT Backup Register [%s] 0xABF68 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[465] VBATT Backup Register [%s] 0xAC639 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[466] VBATT Backup Register [%s] 0xACD0B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[467] VBATT Backup Register [%s] 0xAD3DE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[468] VBATT Backup Register [%s] 0xADAB2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[469] VBATT Backup Register [%s] 0xAE187 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[46] VBATT Backup Register [%s] 0xF439 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[470] VBATT Backup Register [%s] 0xAE85D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[471] VBATT Backup Register [%s] 0xAEF34 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[472] VBATT Backup Register [%s] 0xAF60C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[473] VBATT Backup Register [%s] 0xAFCE5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[474] VBATT Backup Register [%s] 0xB03BF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[475] VBATT Backup Register [%s] 0xB0A9A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[476] VBATT Backup Register [%s] 0xB1176 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[477] VBATT Backup Register [%s] 0xB1853 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[478] VBATT Backup Register [%s] 0xB1F31 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[479] VBATT Backup Register [%s] 0xB2610 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[47] VBATT Backup Register [%s] 0xF968 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[480] VBATT Backup Register [%s] 0xB2CF0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[481] VBATT Backup Register [%s] 0xB33D1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[482] VBATT Backup Register [%s] 0xB3AB3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[483] VBATT Backup Register [%s] 0xB4196 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[484] VBATT Backup Register [%s] 0xB487A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[485] VBATT Backup Register [%s] 0xB4F5F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[486] VBATT Backup Register [%s] 0xB5645 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[487] VBATT Backup Register [%s] 0xB5D2C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[488] VBATT Backup Register [%s] 0xB6414 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[489] VBATT Backup Register [%s] 0xB6AFD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[48] VBATT Backup Register [%s] 0xFE98 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[490] VBATT Backup Register [%s] 0xB71E7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[491] VBATT Backup Register [%s] 0xB78D2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[492] VBATT Backup Register [%s] 0xB7FBE 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[493] VBATT Backup Register [%s] 0xB86AB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[494] VBATT Backup Register [%s] 0xB8D99 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[495] VBATT Backup Register [%s] 0xB9488 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[496] VBATT Backup Register [%s] 0xB9B78 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[497] VBATT Backup Register [%s] 0xBA269 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[498] VBATT Backup Register [%s] 0xBA95B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[499] VBATT Backup Register [%s] 0xBB04E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[49] VBATT Backup Register [%s] 0x103C9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[4] VBATT Backup Register [%s] 0x1E0A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[500] VBATT Backup Register [%s] 0xBB742 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[501] VBATT Backup Register [%s] 0xBBE37 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[502] VBATT Backup Register [%s] 0xBC52D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[503] VBATT Backup Register [%s] 0xBCC24 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[504] VBATT Backup Register [%s] 0xBD31C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[505] VBATT Backup Register [%s] 0xBDA15 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[506] VBATT Backup Register [%s] 0xBE10F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[507] VBATT Backup Register [%s] 0xBE80A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[508] VBATT Backup Register [%s] 0xBEF06 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[509] VBATT Backup Register [%s] 0xBF603 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[50] VBATT Backup Register [%s] 0x108FB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[510] VBATT Backup Register [%s] 0xBFD01 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[511] VBATT Backup Register [%s] 0xC0400 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[51] VBATT Backup Register [%s] 0x10E2E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[52] VBATT Backup Register [%s] 0x11362 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[53] VBATT Backup Register [%s] 0x11897 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[54] VBATT Backup Register [%s] 0x11DCD 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[55] VBATT Backup Register [%s] 0x12304 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[56] VBATT Backup Register [%s] 0x1283C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[57] VBATT Backup Register [%s] 0x12D75 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[58] VBATT Backup Register [%s] 0x132AF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[59] VBATT Backup Register [%s] 0x137EA 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[5] VBATT Backup Register [%s] 0x230F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[60] VBATT Backup Register [%s] 0x13D26 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[61] VBATT Backup Register [%s] 0x14263 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[62] VBATT Backup Register [%s] 0x147A1 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[63] VBATT Backup Register [%s] 0x14CE0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[64] VBATT Backup Register [%s] 0x15220 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[65] VBATT Backup Register [%s] 0x15761 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[66] VBATT Backup Register [%s] 0x15CA3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[67] VBATT Backup Register [%s] 0x161E6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[68] VBATT Backup Register [%s] 0x1672A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[69] VBATT Backup Register [%s] 0x16C6F 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[6] VBATT Backup Register [%s] 0x2815 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[70] VBATT Backup Register [%s] 0x171B5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[71] VBATT Backup Register [%s] 0x176FC 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[72] VBATT Backup Register [%s] 0x17C44 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[73] VBATT Backup Register [%s] 0x1818D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[74] VBATT Backup Register [%s] 0x186D7 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[75] VBATT Backup Register [%s] 0x18C22 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[76] VBATT Backup Register [%s] 0x1916E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[77] VBATT Backup Register [%s] 0x196BB 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[78] VBATT Backup Register [%s] 0x19C09 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[79] VBATT Backup Register [%s] 0x1A158 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[7] VBATT Backup Register [%s] 0x2D1C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[80] VBATT Backup Register [%s] 0x1A6A8 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[81] VBATT Backup Register [%s] 0x1ABF9 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[82] VBATT Backup Register [%s] 0x1B14B 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[83] VBATT Backup Register [%s] 0x1B69E 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[84] VBATT Backup Register [%s] 0x1BBF2 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[85] VBATT Backup Register [%s] 0x1C147 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[86] VBATT Backup Register [%s] 0x1C69D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[87] VBATT Backup Register [%s] 0x1CBF4 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[88] VBATT Backup Register [%s] 0x1D14C 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[89] VBATT Backup Register [%s] 0x1D6A5 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[8] VBATT Backup Register [%s] 0x3224 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[90] VBATT Backup Register [%s] 0x1DBFF 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[91] VBATT Backup Register [%s] 0x1E15A 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[92] VBATT Backup Register [%s] 0x1E6B6 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[93] VBATT Backup Register [%s] 0x1EC13 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[94] VBATT Backup Register [%s] 0x1F171 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[95] VBATT Backup Register [%s] 0x1F6D0 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[96] VBATT Backup Register [%s] 0x1FC30 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[97] VBATT Backup Register [%s] 0x20191 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[98] VBATT Backup Register [%s] 0x206F3 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[99] VBATT Backup Register [%s] 0x20C56 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTBKR[9] VBATT Backup Register [%s] 0x372D 8 read-write n 0x0 0x0 VBTBKR VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset. 0 7 read-write VBTCMPCR VBATT Comparator Control Register 0x4B2 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write VBTCMPE VBATT pin low voltage detect circuit output enable 0 read-write 0 VBATT pin low voltage detect circuit output disabled #0 1 VBATT pin low voltage detect circuit output enabled #1 VBTCR1 VBATT Control Register1 0x41F 8 read-write n 0x0 0x0 BPWSWSTP Battery Power supply Switch Stop 0 read-write 0 Battery Power supply Switch Enable #0 1 Battery Power supply Switch stop #1 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write VBTCR2 VBATT Control Register2 0x4B0 8 read-write n 0x0 0x0 Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write VBTLVDEN VBATT Pin Low Voltage Detect Enable Bit 4 read-write 0 VBATT pin low voltage detect disable #0 1 VBATT pin low voltage detect enable #1 VBTLVDLVL VBATT Pin Voltage Low Voltage Detect Level Select Bit 6 1 read-write 00 2.7V #00 01 Setting prohibited #01 10 2.3V #10 11 2.1V #11 VBTICTLR VBATT Input Control Register 0x4BB 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write VCH0INEN VBATT Wakeup I/O 0 Input Enable 0 read-write 0 VBATWIO0, RTCIC0 inputs disabled #0 1 VBATWIO0, RTCIC0 inputs enabled. #1 VCH1INEN VBATT Wakeup I/O 1 Input Enable 1 read-write 0 VBATWIO1, RTCIC1 inputs disabled #0 1 VBATWIO1, RTCIC1 inputs enabled. #1 VCH2INEN VBATT Wakeup I/O 2 Input Enable 2 read-write 0 VBATWIO2 and RTCIC2 inputs disabled #0 1 VBATWIO2 and RTCIC2 inputs enabled. #1 VBTLVDICR VBATT Pin Low Voltage Detect Interrupt Control Register 0x4B4 8 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 2 5 read-write VBTLVDIE VBATT Pin Low Voltage Detect Interrupt Enable bit 0 read-write 0 VBATT Pin Low Voltage Detect Interrupt Disable #0 1 VBATT Pin Low Voltage Detect Interrupt Enable #1 VBTLVDISEL Pin Low Voltage Detect Interrupt Select bit 1 read-write 0 Non Maskable Interrupt #0 1 Maskable Interrupt #1 VBTOCTLR VBATT Output Control Register 0x4BC 8 read-write n 0x0 0x0 Reserved These bits are read as 00. The write value should be 00. 6 1 read-write VCH0OEN VBATT Wakeup I/O 0 Output Enable 0 read-write 0 VBATWIO0 output disabled #0 1 VBATWIO0 output enabled #1 VCH1OEN VBATT Wakeup I/O 1 Output Enable 1 read-write 0 VBATWIO1 output disabled #0 1 VBATWIO1 output enabled #1 VCH2OEN VBATT Wakeup I/O 2 Output Enable 2 read-write 0 VBATWIO2 output disabled #0 1 VBATWIO2 output enabled #1 VCOU1LSEL VBATT Wakeup I/O 1 Output Level Selection 4 read-write 0 Output L before VBATT wake up trigger #0 1 Output H before VBATT wake up trigger #1 VOUT0LSEL VBATT Wakeup I/O 0 Output Level Selection 3 read-write 0 Output L before VBATT wakeup trigger #0 1 Output H before VBATT wakeup trigger #1 VOUT2LSEL VBATT Wakeup I/O 2 Output Level Selection 5 read-write 0 Output L before VBATT wake up trigger #0 1 Output H before VBATT wake up trigger #1 VBTSR VBATT Status Register 0x4B1 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VBTBLDF VBATT Battery Low voltage Detect Flag 1 read-write zeroToClear modify 0 VBATT pin low voltage not detected #0 1 VBATT pin low voltage detected. #1 VBTRDF VBAT_R Reset Detect Flag 0 read-write zeroToClear modify 0 VBATT_R voltage power-on reset not detected #0 1 VBATT_R selected voltage power-on reset detected. #1 VBTRVLD VBATT_R Valid 4 read-only 0 VBATT_R area not valid #0 1 VBATT_R area valid #1 VBTWCH0OTSR VBATT Wakeup I/O 0 Output Trigger Select Register 0x4B8 8 read-write n 0x0 0x0 CH0VCH1TE VBATWIO0 Output VBATWIO1 Trigger Enable 1 read-write 0 VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is disabled #0 1 VBATT wakeup I/O 0 output trigger by the VBATWIO1 pin is enabled. #1 CH0VCH2TE VBATWIO0 Output VBATWIO2 Trigger Enable 2 read-write 0 VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is disabled #0 1 VBATT wakeup I/O 0 output trigger by the VBATWIO2 pin is enabled. #1 CH0VRTCATE VBATWIO0 Output RTC Alarm Signal Enable 4 read-write 0 VBATT wakeup I/O 0 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 0 output trigger by the RTC alarm signal is enabled. #1 CH0VRTCTE VBATWIO0 Output RTC Periodic Signal Enable 3 read-write 0 VBATT wakeup I/O 0 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 0 output trigger by the RTC periodic signal is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VBTWCH1OTSR VBATT Wakeup I/O 1 Output Trigger Select Register 0x4B9 8 read-write n 0x0 0x0 CH1VCH0TE VBATWIO1 Output VBATWIO0 Trigger Enable 0 read-write 0 VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is disabled #0 1 VBATT wakeup I/O 1 output trigger by the VBATWIO0 pin is enabled. #1 CH1VCH2TE VBATWIO1 Output VBATWIO2 Trigger Enable 2 read-write 0 VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is disabled #0 1 VBATT wakeup I/O 1 output trigger by the VBATWIO2 pin is enabled. #1 CH1VRTCATE VBATWIO1 Output RTC Alarm Signal Enable 4 read-write 0 VBATT wakeup I/O 1 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 1 output trigger by the RTC alarm signal is enabled. #1 CH1VRTCTE VBATWIO1 Output RTC Periodic Signal Enable 3 read-write 0 VBATT wakeup I/O 1 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 1 output trigger by the RTC periodic signal is enabled #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VBTWCH2OTSR VBATT Wakeup I/O 2 Output Trigger Select Register 0x4BA 8 read-write n 0x0 0x0 CH2VCH0TE VBATWIO2 Output VBATWIO0 Trigger Enable 0 read-write 0 VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is disabled #0 1 VBATT wakeup I/O 2 output trigger by the VBATWIO0 pin is enabled. #1 CH2VCH1TE VBATWIO2 Output VBATWIO1 Trigger Enable 1 read-write 0 VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is disabled #0 1 VBATT wakeup I/O 2 output trigger by the VBATWIO1 pin is enabled. #1 CH2VRTCATE VBATWIO2 Output RTC Alarm Signal Enable 4 read-write 0 VBATT wakeup I/O 2 output trigger by the RTC alarm signal is disabled #0 1 VBATT wakeup I/O 2 output trigger by the RTC alarm signal is enabled. #1 CH2VRTCTE VBATWIO2 Output RTC Periodic Signal Enable 3 read-write 0 VBATT wakeup I/O 2 output trigger by the RTC periodic signal is disabled #0 1 VBATT wakeup I/O 2 output trigger by the RTC periodic signal is enabled. #1 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VBTWCTLR VBATT Wakeup function Control Register 0x4B6 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 1 6 read-write VWEN VBATT wakeup enable 0 read-write 0 Disable Wakeup function #0 1 Enable Wakeup function #1 VBTWEGR VBATT Wakeup Trigger source Edge Register 0x4BE 8 read-write n 0x0 0x0 Reserved These bits are read as 00000. The write value should be 00000. 3 4 read-write VCH0EG VBATWIO0 Wakeup Trigger Source Edge Select 0 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VCH1EG VBATWIO1 Wakeup Trigger Source Edge Select 1 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VCH2EG VBATWIO2 Wakeup Trigger Source Edge Select 2 read-write 0 Wakeup trigger is generated at a falling edge #0 1 Wakeup trigger is generated at a rising edge. #1 VBTWFR VBATT Wakeup trigger source Flag Register 0x4BF 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VCH0F VBATWIO0 Wakeup Trigger Flag 0 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO0 pin is generated #0 1 A wakeup trigger by the VBATWIO0 pin is generated #1 VCH1F VBATWIO1 Wakeup Trigger Flag 1 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO1 pin is generated #0 1 A wakeup trigger by the VBATWIO1 pin is generated #1 VCH2F VBATWIO2 Wakeup Trigger Flag 2 read-write zeroToClear modify 0 No wakeup trigger by the VBATWIO2 pin is generated #0 1 A wakeup trigger by the VBATWIO2 pin is generated #1 VRTCAF VBATT RTC-Alarm Wakeup Trigger Flag 4 read-write zeroToClear modify 0 No wakeup trigger by the RTC alarm is generated #0 1 A wakeup trigger by the RTC alarm is generated #1 VRTCIF VBATT RTC-Interval Wakeup Trigger Flag 3 read-write zeroToClear modify 0 No wakeup trigger by the RTC interval is generated #0 1 A wakeup trigger by the RTC interval is generated #1 VBTWTER VBATT Wakeup Trigger source Enable Register 0x4BD 8 read-write n 0x0 0x0 Reserved These bits are read as 000. The write value should be 000. 5 2 read-write VCH0E VBATWIO0 Pin Enable 0 read-write 0 VBATT wakeup triggered by the VBATWIO0 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO0 pin is enabled. #1 VCH1E VBATWIO1 Pin Enable 1 read-write 0 VBATT wakeup triggered by the VBATWIO1 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO1 pin is enabled. #1 VCH2E VBATWIO2 Pin Enable 2 read-write 0 VBATT wakeup triggered by the VBATWIO2 pin is disabled #0 1 VBATT wakeup triggered by the VBATWIO2 pin is enabled. #1 VRTCAE RTC Alarm Signal Enable 4 read-write 0 VBATT wakeup triggered by RTC alarm signal is disabled #0 1 VBATT wakeup triggered by RTC alarm signal is enabled. #1 VRTCIE RTC Periodic Signal Enable 3 read-write 0 VBATT wakeup triggered by RTC periodic signal is disabled #0 1 VBATT wakeup triggered by RTC periodic signal is enabled. #1 TSN Temperature Sensor TSN 0x0 0x228 0x2 registers n TSCDRH Temperature Sensor Calibration Data Register H 0x228 8 read-only n 0x0 0x0 TSCDRH The calibration data stores the higher 8 bits of the convertedvalue. 0 7 read-only TSCDRL Temperature Sensor Calibration Data Register L 0x229 8 read-only n 0x0 0x0 TSCDRL The calibration data stores the lower 8 bits of the convertedvalue. 0 7 read-only USBFS USB 2.0 FS Module USBFS 0x0 0x0 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x1C 0x2 registers n 0x20 0x4 registers n 0x28 0xC registers n 0x36 0x8 registers n 0x4 0x2 registers n 0x40 0x4 registers n 0x46 0xC registers n 0x54 0xE registers n 0x64 0x2 registers n 0x68 0x2 registers n 0x6C 0x16 registers n 0x8 0x2 registers n 0x90 0x14 registers n 0x92 0x14 registers n 0xB0 0x2 registers n 0xCC 0x2 registers n 0xD0 0xC registers n BEMPENB BEMP Interrupt Enable Register 0x3A 16 read-write n 0x0 0x0 PIPE0BEMPE BEMP Interrupt Enable for PIPE0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BEMPE BEMP Interrupt Enable for PIPE1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BEMPE BEMP Interrupt Enable for PIPE2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BEMPE BEMP Interrupt Enable for PIPE3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BEMPE BEMP Interrupt Enable for PIPE4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BEMPE BEMP Interrupt Enable for PIPE5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BEMPE BEMP Interrupt Enable for PIPE6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BEMPE BEMP Interrupt Enable for PIPE7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BEMPE BEMP Interrupt Enable for PIPE8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE9BEMPE BEMP Interrupt Enable for PIPE9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write BEMPSTS BEMP Interrupt Status Register 0x4A 16 read-write n 0x0 0x0 PIPE0BEMP BEMP Interrupt Status for PIPE0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BEMP BEMP Interrupt Status for PIPE1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BEMP BEMP Interrupt Status for PIPE2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BEMP BEMP Interrupt Status for PIPE3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BEMP BEMP Interrupt Status for PIPE4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BEMP BEMP Interrupt Status for PIPE5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BEMP BEMP Interrupt Status for PIPE6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BEMP BEMP Interrupt Status for PIPE7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BEMP BEMP Interrupt Status for PIPE8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE9BEMP BEMP Interrupt Status for PIPE9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write BRDYENB BRDY Interrupt Enable Register 0x36 16 read-write n 0x0 0x0 PIPE0BRDYE BRDY Interrupt Enable for PIPE0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1BRDYE BRDY Interrupt Enable for PIPE1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2BRDYE BRDY Interrupt Enable for PIPE2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3BRDYE BRDY Interrupt Enable for PIPE3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4BRDYE BRDY Interrupt Enable for PIPE4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5BRDYE BRDY Interrupt Enable for PIPE5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6BRDYE BRDY Interrupt Enable for PIPE6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7BRDYE BRDY Interrupt Enable for PIPE7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8BRDYE BRDY Interrupt Enable for PIPE8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE9BRDYE BRDY Interrupt Enable for PIPE9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write BRDYSTS BRDY Interrupt Status Register 0x46 16 read-write n 0x0 0x0 PIPE0BRDY BRDY Interrupt Status for PIPE0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1BRDY BRDY Interrupt Status for PIPE1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2BRDY BRDY Interrupt Status for PIPE2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3BRDY BRDY Interrupt Status for PIPE3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4BRDY BRDY Interrupt Status for PIPE4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5BRDY BRDY Interrupt Status for PIPE5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6BRDY BRDY Interrupt Status for PIPE6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7BRDY BRDY Interrupt Status for PIPE7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8BRDY BRDY Interrupt Status for PIPE8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE9BRDY BRDY Interrupt Status for PIPE9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write CFIFO CFIFO Port Register 0x14 16 read-write n 0x0 0x0 FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write CFIFOCTR CFIFO Port Control Register 0x22 16 read-write n 0x0 0x0 BCLR CPU Buffer ClearNote: Only 0 can be read. 14 read-write 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid #0 1 Writing ended #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 3 read-write CFIFOL CFIFO Port Register L CFIFO 0x14 8 read-write n 0x0 0x0 CFIFOSEL CFIFO Port Select Register 0x20 16 read-write n 0x0 0x0 BIGEND CFIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE CFIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 ISEL CFIFO Port Access Direction When DCP is Selected 5 read-write 0 Reading from the buffer memory is selected #0 1 Writing to the buffer memory is selected #1 MBW CFIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the CFIFO.(In double buffer mode, the DTLN[8:0] bit value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO. #1 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write Reserved These bits are read as 00. The write value should be 00. 6 1 read-write REW Buffer Pointer Rewind 14 read-write 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 D0FIFO D0FIFO Port Register 0x18 16 read-write n 0x0 0x0 FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D0FIFOCTR D0FIFO Port Control Register 0x2A 16 read-write n 0x0 0x0 BCLR CPU Buffer ClearNote: Only 0 can be read. 14 read-write 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid #0 1 Writing ended #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 3 read-write D0FIFOL D0FIFO Port Register L D0FIFO 0x18 8 read-write n 0x0 0x0 D0FIFOSEL D0FIFO Port Select Register 0x28 16 read-write n 0x0 0x0 BIGEND FIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 MBW FIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write REW Buffer Pointer RewindNote: Only 0 can be read. 14 read-write 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 D1FIFO D1FIFO Port Register 0x1C 16 read-write n 0x0 0x0 FIFOPORT FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits. 0 15 read-write D1FIFOCTR D1FIFO Port Control Register 0x2E 16 read-write n 0x0 0x0 BCLR CPU Buffer ClearNote: Only 0 can be read. 14 read-write 0 Does not operate #0 1 FIFO buffer cleared on the CPU side. #1 BVAL Buffer Memory Valid Flag 15 read-write 0 Invalid #0 1 Writing ended #1 DTLN Receive Data LengthIndicates the length of the receive data. 0 8 read-only FRDY FIFO Port Ready 13 read-only 0 FIFO port access is disabled. #0 1 FIFO port access is enabled. #1 Reserved These bits are read as 0000. The write value should be 0000. 9 3 read-write D1FIFOL D1FIFO Port Register L D1FIFO 0x1C 8 read-write n 0x0 0x0 D1FIFOSEL D1FIFO Port Select Register 0x2C 16 read-write n 0x0 0x0 BIGEND FIFO Port Endian Control 8 read-write 0 Little endian #0 1 Big endian #1 CURPIPE FIFO Port Access Pipe Specification 0 3 read-write 0000 DCP (Default control pipe) #0000 0001 Pipe 1 #0001 0010 Pipe 2 #0010 0011 Pipe 3 #0011 0100 Pipe 4 #0100 0101 Pipe 5 #0101 0110 Pipe 6 #0110 0111 Pipe 7 #0111 1000 Pipe 8 #1000 1001 Pipe 9 #1001 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled. #1 DREQE DMA/DTC Transfer Request Enable 12 read-write 0 DMA/DTC transfer request is disabled. #0 1 DMA/DTC transfer request is enabled. #1 MBW FIFO Port Access Bit Width 10 read-write 0 8-bit width #0 1 16-bit width #1 RCNT Read Count Mode 15 read-write 0 The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) #0 1 The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) #1 Reserved This bit is read as 0. The write value should be 0. 11 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write REW Buffer Pointer Rewind 14 read-write 0 The buffer pointer is not rewound. #0 1 The buffer pointer is rewound. #1 DCPCFG DCP Configuration Register 0x5C 16 read-write n 0x0 0x0 DIR Transfer Direction 4 read-write 0 Data receiving direction #0 1 Data transmitting direction #1 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write Reserved These bits are read as 00. The write value should be 00. 5 1 read-write SHTNAK Pipe Disabled at End of Transfer 7 read-write 0 Pipe continued at the end of transfer #0 1 Pipe disabled at the end of transfer #1 DCPCTR DCP Control Register 0x60 16 read-write n 0x0 0x0 BSTS Buffer Status 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 CCPL Control Transfer End Enable 2 read-write 0 Invalid #0 1 Completion of control transfer is enabled. #1 PBUSY Pipe Busy 5 read-only 0 DCP is not used for the transaction. #0 1 DCP is used for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 00. The write value should be 00. 12 1 read-write Reserved These bits are read as 00. The write value should be 00. 9 1 read-write Reserved These bits are read as 00. The write value should be 00. 9 1 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Invalid #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Monitor 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Invalid #0 1 Specifies DATA1. #1 SUREQ Setup Token Transmission 14 read-write 0 Invalid #0 1 Transmits the setup packet. #1 SUREQCLR SUREQ Bit Clear 11 read-write 0 Invalid #0 1 Clears the SUREQ bit to 0. #1 DCPMAXP DCP Maximum Packet Size Register 0x5E 16 read-write n 0x0 0x0 DEVSEL Device Select 12 3 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 MXPS Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP. 0 6 read-write 0x08 8 bytes 0x08 0x10 16 bytes 0x10 0x18 24 bytes 0x18 0x20 32 bytes 0x20 0x28 40 bytes 0x28 0x30 48 bytes 0x30 0x38 56 bytes 0x38 0x40 64 bytes 0x40 0x48 72 bytes 0x48 0x50 80 bytes 0x50 0x58 88 bytes 0x58 0x60 96 bytes 0x60 0x68 104 bytes 0x68 0x70 112 bytes 0x70 0x78 120 bytes 0x78 Reserved These bits are read as 00000. The write value should be 00000. 7 4 read-write DEVADD0 Device Address %s Configuration Register 0x1A0 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DEVADD1 Device Address %s Configuration Register 0x272 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DEVADD2 Device Address %s Configuration Register 0x346 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DEVADD3 Device Address %s Configuration Register 0x41C 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DEVADD4 Device Address %s Configuration Register 0x4F4 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DEVADD5 Device Address %s Configuration Register 0x5CE 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write USBSPD Transfer Speed of Communication Target Device 6 1 read-write 00 DEVADDn is not used #00 01 Low speed #01 10 Full speed #10 11 Setting prohibited #11 DVSTCTR0 Device State Control Register 0 0x8 16 read-write n 0x0 0x0 EXICEN USB_EXICEN Output Pin Control 10 read-write 0 External USB_EXICEN pin outputs low #0 1 External USB_EXICEN pin outputs high #1 HNPBTOA Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1, the internal function control keeps the suspended state until the HNP processing ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. 11 read-write 0 Normal Operation #0 1 Switching from device B to device A is enabled #1 Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 12 3 read-write RESUME Resume Output 5 read-write 0 Resume signal is not output. #0 1 Resume signal is output. #1 RHST USB Bus Reset Status 0 2 read-only 000 Communication speed not determined #000 001 Low-speed connection(When the host controller is selected) /USB bus reset in progress( When the function controller is selected) #001 010 Full-speed connection(When the host controller is selected) /USB bus reset in progress or full-speed connection(When the function controller is selected) #010 011 Setting prohibited #011 RWUPE Wakeup Detection Enable 7 read-write 0 Downstream port wakeup is disabled. #0 1 Downstream port wakeup is enabled. #1 UACT USB Bus Enable 4 read-write 0 Downstream port is disabled (SOF transmission is disabled). #0 1 Downstream port is enabled (SOF transmission is enabled). #1 USBRST USB Bus Reset Output 6 read-write 0 USB bus reset signal is not output. #0 1 USB bus reset signal is output. #1 VBUSEN USB_VBUSEN Output Pin Control 9 read-write 0 External USB_VBUSEN pin outputs low #0 1 External USB_VBUSEN pin outputs high #1 WKUP Wakeup Output 8 read-write 0 Remote wakeup signal is not output. #0 1 Remote wakeup signal is output. #1 FRMNUM Frame Number Register 0x4C 16 read-write n 0x0 0x0 CRCE Receive Data Error 14 read-write 0 No error #0 1 An error occurred #1 FRNM Frame NumberLatest frame number 0 10 read-only OVRN Overrun/Underrun Detection Status 15 read-write 0 No error #0 1 An error occurred #1 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write INTENB0 Interrupt Enable Register 0 0x30 16 read-write n 0x0 0x0 BEMPE Buffer Empty Interrupt Enable 10 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BRDYE Buffer Ready Interrupt Enable 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 CTRE Control Transfer Stage Transition Interrupt Enable 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DVSE Device State Transition Interrupt Enable 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 NRDYE Buffer Not Ready Response Interrupt Enable 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 00000000. The write value should be 00000000. 0 7 read-write RSME Resume Interrupt Enable 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SOFE Frame Number Update Interrupt Enable 13 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 VBSE VBUS Interrupt Enable 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 INTENB1 Interrupt Enable Register 1 0x32 16 read-write n 0x0 0x0 ATTCHE Connection Detection Interrupt Enable 11 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 BCHGE USB Bus Change Interrupt Enable 14 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 DTCHE Disconnection Detection Interrupt Enable 12 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 EOFERRE EOF Error Detection Interrupt Enable 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 OVRCRE Overcurrent Input Change Interrupt Enable 15 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PDDETINTE0 PDDETINT0 Detection Interrupt Enable 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved These bits are read as 0000. The write value should be 0000. 7 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 7 3 read-write SACKE Setup Transaction Normal Response Interrupt Enable 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 SIGNE Setup Transaction Error Interrupt Enable 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 INTSTS0 Interrupt Status Register 0 0x40 16 read-write n 0x0 0x0 BEMP Buffer Empty Interrupt Status 10 read-only 0 BEMP interrupts are not generated. #0 1 BEMP interrupts are generated. #1 BRDY Buffer Ready Interrupt Status 8 read-only 0 BRDY interrupts are not generated. #0 1 BRDY interrupts are generated. #1 CTRT Control Transfer Stage Transition Interrupt Status 11 read-write zeroToClear modify 0 Control transfer stage transition interrupts are not generated. #0 1 Control transfer stage transition interrupts are generated. #1 CTSQ Control Transfer Stage 0 2 read-only 000 Idle or setup stage #000 001 Control read data stage #001 010 Control read status stage #010 011 Control write data stage #011 100 Control write status stage #100 101 Control write (no data) status stage #101 110 Control transfer sequence error #110 DVSQ Device State 4 2 read-only 000 Powered state #000 001 Default state #001 010 Address state #010 011 Configured state #011 DVST Device State Transition Interrupt Status 12 read-write zeroToClear modify 0 Device state transition interrupts are not generated. #0 1 Device state transition interrupts are generated. #1 NRDY Buffer Not Ready Interrupt Status 9 read-only 0 NRDY interrupts are not generated. #0 1 NRDY interrupts are generated. #1 RESM Resume Interrupt Status 14 read-write zeroToClear modify 0 Resume interrupts are not generated. #0 1 Resume interrupts are generated. #1 SOFR Frame Number Refresh Interrupt Status 13 read-write zeroToClear modify 0 SOF interrupts are not generated. #0 1 SOF interrupts are generated. #1 VALID USB Request Reception 3 read-write 0 Setup packet is not received #0 1 Setup packet is received #1 VBINT VBUS Interrupt Status 15 read-write zeroToClear modify 0 VBUS interrupts are not generated. #0 1 VBUS interrupts are generated. #1 VBSTS VBUS Input Status 7 read-only 0 USB_VBUS pin is low. #0 1 USB_VBUS pin is high. #1 INTSTS1 Interrupt Status Register 1 0x42 16 read-write n 0x0 0x0 ATTCH ATTCH Interrupt Status 11 read-write zeroToClear modify 0 ATTCH interrupts are not generated. #0 1 ATTCH interrupts are generated. #1 BCHG USB Bus Change Interrupt Status 14 read-write zeroToClear modify 0 BCHG interrupts are not generated. #0 1 BCHG interrupts are generated. #1 DTCH USB Disconnection Detection Interrupt Status 12 read-write zeroToClear modify 0 DTCH interrupts are not generated. #0 1 DTCH interrupts are generated. #1 EOFERR EOF Error Detection Interrupt Status 6 read-write zeroToClear modify 0 EOFERR interrupts are not generated. #0 1 EOFERR interrupts are generated. #1 OVRCR Overcurrent Input Change Interrupt Status 15 read-write zeroToClear modify 0 OVRCR interrupts are not generated. #0 1 OVRCR interrupts are generated. #1 PDDETINT0 PDDET0 Detection Interrupt Status 0 read-write zeroToClear modify 0 PDDET0 detection interrupts are not generated. #0 1 PDDET0 detection interrupts are generated. #1 Reserved This bit is read as 0. The write value should be 0. 13 read-write Reserved These bits are read as 0000. The write value should be 0000. 7 3 read-write Reserved These bits are read as 0000. The write value should be 0000. 7 3 read-write SACK Setup Transaction Normal Response Interrupt Status 4 read-write zeroToClear modify 0 SACK interrupts are not generated. #0 1 SACK interrupts are generated. #1 SIGN Setup Transaction Error Interrupt Status 5 read-write zeroToClear modify 0 SIGN interrupts are not generated. #0 1 SIGN interrupts are generated. #1 NRDYENB NRDY Interrupt Enable Register 0x38 16 read-write n 0x0 0x0 PIPE0NRDYE NRDY Interrupt Enable for PIPE0 0 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE1NRDYE NRDY Interrupt Enable for PIPE1 1 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE2NRDYE NRDY Interrupt Enable for PIPE2 2 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE3NRDYE NRDY Interrupt Enable for PIPE3 3 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE4NRDYE NRDY Interrupt Enable for PIPE4 4 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE5NRDYE NRDY Interrupt Enable for PIPE5 5 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE6NRDYE NRDY Interrupt Enable for PIPE6 6 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE7NRDYE NRDY Interrupt Enable for PIPE7 7 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE8NRDYE NRDY Interrupt Enable for PIPE8 8 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 PIPE9NRDYE NRDY Interrupt Enable for PIPE9 9 read-write 0 Interrupt output disabled #0 1 Interrupt output enabled #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write NRDYSTS NRDY Interrupt Status Register 0x48 16 read-write n 0x0 0x0 PIPE0NRDY NRDY Interrupt Status for PIPE0 0 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE1NRDY NRDY Interrupt Status for PIPE1 1 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE2NRDY NRDY Interrupt Status for PIPE2 2 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE3NRDY NRDY Interrupt Status for PIPE3 3 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE4NRDY NRDY Interrupt Status for PIPE4 4 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE5NRDY NRDY Interrupt Status for PIPE5 5 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE6NRDY NRDY Interrupt Status for PIPE6 6 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE7NRDY NRDY Interrupt Status for PIPE7 7 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE8NRDY NRDY Interrupt Status for PIPE8 8 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 PIPE9NRDY NRDY Interrupt Status for PIPE9 9 read-write zeroToClear modify 0 Interrupts are not generated. #0 1 Interrupts are generated. #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write PIPE1CTR Pipe %s Control Register 0xE0 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 ATREPM Auto Response Mode 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 PIPE1TRE Pipe %s Transaction Counter Enable Register 0x120 16 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write TRCLR Transaction Counter Clear 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 TRENB Transaction Counter Enable 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 PIPE1TRN Pipe %s Transaction Counter Register 0x124 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE2CTR Pipe %s Control Register 0x152 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 ATREPM Auto Response Mode 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 PIPE2TRE Pipe %s Transaction Counter Enable Register 0x1B4 16 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write TRCLR Transaction Counter Clear 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 TRENB Transaction Counter Enable 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 PIPE2TRN Pipe %s Transaction Counter Register 0x1BA 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE3CTR Pipe %s Control Register 0x1C6 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 ATREPM Auto Response Mode 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 PIPE3TRE Pipe %s Transaction Counter Enable Register 0x24C 16 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write TRCLR Transaction Counter Clear 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 TRENB Transaction Counter Enable 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 PIPE3TRN Pipe %s Transaction Counter Register 0x254 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE4CTR Pipe %s Control Register 0x23C 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 ATREPM Auto Response Mode 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 PIPE4TRE Pipe %s Transaction Counter Enable Register 0x2E8 16 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write TRCLR Transaction Counter Clear 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 TRENB Transaction Counter Enable 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 PIPE4TRN Pipe %s Transaction Counter Register 0x2F2 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE5CTR Pipe %s Control Register 0x2B4 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Disabled #0 1 Enabled (all buffers are initialized) #1 ATREPM Auto Response Mode 10 read-write 0 Auto response disabled. #0 1 Auto response enabled. #1 BSTS Buffer Status 15 read-only 0 Buffer access by the CPU is disabled. #0 1 Buffer access by the CPU is enabled. #1 INBUFM Transmit Buffer Monitor 14 read-only 0 No data to be transmitted is in the FIFO buffer #0 1 Data to be transmitted is in the FIFO buffer #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write SQCLR Sequence Toggle Bit Clear 8 read-write 0 Write disabled #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 read-write 0 Write disabled #0 1 Specifies DATA1. #1 PIPE5TRE Pipe %s Transaction Counter Enable Register 0x388 16 read-write n 0x0 0x0 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write TRCLR Transaction Counter Clear 8 read-write 0 Invalid #0 1 The current counter value is cleared. #1 TRENB Transaction Counter Enable 9 read-write 0 Transaction counter is disabled. #0 1 Transaction counter is enabled. #1 PIPE5TRN Pipe %s Transaction Counter Register 0x394 16 read-write n 0x0 0x0 TRNCNT Transaction Counter 0 15 read-write PIPE6CTR Pipe %s Control Register 0xF4 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 PIPE7CTR Pipe %s Control Register 0x170 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 PIPE8CTR Pipe %s Control Register 0x1EE 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 PIPE9CTR Pipe %s Control Register 0x26E 16 read-write n 0x0 0x0 ACLRM Auto Buffer Clear Mode 9 read-write 0 Auto buffer clear mode is disabled. #0 1 Auto buffer clear mode is enabled (all buffers are initialized) #1 BSTS Buffer Status 15 read-only 0 Buffer access is disabled. #0 1 Buffer access is enabled. #1 PBUSY Pipe Busy 5 read-only 0 Pipe n not in use for the transaction #0 1 Pipe n in use for the transaction. #1 PID Response PID 0 1 read-write 00 NAK response #00 01 BUF response (depending on the buffer state) #01 10 STALL response #10 11 STALL response #11 Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 10 4 read-write SQCLR Sequence Toggle Bit Clear 8 write-only 0 Invalid #0 1 Specifies DATA0. #1 SQMON Sequence Toggle Bit Confirmation 6 read-only 0 DATA0 #0 1 DATA1 #1 SQSET Sequence Toggle Bit Set 7 write-only 0 Invalid #0 1 Specifies DATA1. #1 PIPECFG Pipe Configuration Register 0x68 16 read-write n 0x0 0x0 BFRE BRDY Interrupt Operation Specification 10 read-write 0 BRDY interrupt upon transmitting or receiving data #0 1 BRDY interrupt upon completion of reading data #1 DBLB Double Buffer Mode 9 read-write 0 Single buffer #0 1 Double buffer #1 DIR Transfer Direction 4 read-write 0 Receiving direction #0 1 Transmitting direction #1 EPNUM Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe. 0 3 read-write Reserved These bits are read as 000. The write value should be 000. 11 2 read-write Reserved This bit is read as 0. The write value should be 0. 8 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write Reserved This bit is read as 0. The write value should be 0. 6 read-write SHTNAK Pipe Disabled at End of Transfer 7 read-write 0 Continue pipe operation after transfer ends #0 1 Disable pipe operation after transfer ends. #1 TYPE Transfer Type 14 1 read-write 00 Pipe not used #00 01 Bulk transfer(PIPE1 and PIPE5) /Setting prohibited(PIPE6 to PIPE9) #01 10 Setting prohibited(PIPE1 and PIPE5) /Interrupt transfer(PIPE6 to PIPE9) #10 11 Isochronous transfer(PIPE1 and PIPE2) /Setting prohibited(PIPE3 to PIPE9) #11 PIPEMAXP Pipe Maximum Packet Size Register 0x6C 16 read-write n 0x0 0x0 DEVSEL Device Select 12 3 read-write 0000 Address 0000 #0000 0001 Address 0001 #0001 0010 Address 0010 #0010 0011 Address 0011 #0011 0100 Address 0100 #0100 0101 Address 0101 #0101 MXPS Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not provided.) 0 8 read-write Reserved These bits are read as 000. The write value should be 000. 9 2 read-write PIPEPERI Pipe Cycle Control Register 0x6E 16 read-write n 0x0 0x0 IFIS Isochronous IN Buffer Flush 12 read-write 0 The buffer is not flushed. #0 1 The buffer is flushed. #1 IITV Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as nth power of 2. 0 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write Reserved These bits are read as 000. The write value should be 000. 13 2 read-write PIPESEL Pipe Window Select Register 0x64 16 read-write n 0x0 0x0 PIPESEL Pipe Window Select 0 3 read-write 0000 No pipe selected #0000 0001 PIPE1 #0001 0010 PIPE2 #0010 0011 PIPE3 #0011 0100 PIPE4 #0100 0101 PIPE5 #0101 0110 PIPE6 #0110 0111 PIPE7 #0111 1000 PIPE8 #1000 1001 PIPE9 #1001 Reserved These bits are read as 000000000000. The write value should be 000000000000. 4 11 read-write SOFCFG SOF Output Configuration Register 0x3C 16 read-write n 0x0 0x0 BRDYM BRDY Interrupt Status Clear Timing 6 read-write 0 BRDY flag cleared by software #0 1 BRDY flag cleared by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer. #1 EDGESTS Edge Interrupt Output Status Monitor 4 read-only 0 before stopping the clock supply to the USB module #0 1 the edge interrupt output signal is in the middle of the edge processing #1 Reserved These bits are read as 0000000. The write value should be 0000000. 9 6 read-write Reserved This bit is read as 0. The write value should be 0. 7 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write Reserved This bit is read as 0. The write value should be 0. 5 read-write TRNENSEL Transaction-Enabled Time Select 8 read-write 0 Not low-speed communication #0 1 Low-speed communication. #1 SYSCFG System Configuration Control Register 0x0 16 read-write n 0x0 0x0 CNEN CNEN Single End Receiver Enable 8 read-write 0 Single end receiver disabled #0 1 Single end receiver enabled #1 DCFM Controller Function Select 6 read-write 0 Device controller selected #0 1 Host controller selected. #1 DMRPU D- Line Resistor Control 3 read-write 0 Line pull-up disabled #0 1 Line pull-up enabled. #1 DPRPU D+ Line Resistor Control 4 read-write 0 Line pull-down disabled #0 1 Line pull-down enabled. #1 DRPD D+/D- Line Resistor Control 5 read-write 0 Line pull-down disabled #0 1 Line pull-down enabled. #1 Reserved These bits are read as 00000. The write value should be 00000. 11 4 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write Reserved This bit is read as 0. The write value should be 0. 9 read-write SCKE USB Clock Enable 10 read-write 0 Clock supply to the USBFS stopped #0 1 Clock supply to the USBFS enabled. #1 USBE USB Operation Enable 0 read-write 0 Disabled #0 1 Enabled. #1 SYSSTS0 System Configuration Status Register 0 0x4 16 read-only n 0x0 0x0 HTACT USB Host Sequencer Status Monitor 6 read-only 0 Host sequencer completely stopped #0 1 Host sequencer not completely stopped. #1 IDMON External ID0 Input Pin Monitor 2 read-only 0 USB0_ID pin is low #0 1 USB0_ID pin is high #1 LNST USB Data Line Status Monitor 0 1 read-only 00 SE0 #00 01 K-State (FS) / J-State(LS) #01 10 J-State(FS) / K-State(LS) #10 11 SE1 #11 OVCMON External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin. 14 1 read-only Reserved These bits are read as 0000000. 7 6 read-only Reserved These bits are read as 0000000. 7 6 read-only USBBCCTRL0 BC Control Register 0 0xB0 16 read-write n 0x0 0x0 BATCHGE0 BC (Battery Charger) Function Ch0 General Enable Control 7 read-write 0 Disabled #0 1 Enabled #1 CHGDETSTS0 D- Pin 0.6 V Input Detection Status 8 read-only 0 Not detected #0 1 Detected #1 IDMSINKE0 D- Pin 0.6 V Input Detection (Comparator and Sink) Control 2 read-write 0 Detection off #0 1 Detection on ( Comparator and sink current on ) #1 IDPSINKE0 D+ Pin 0.6 V Input Detection (Comparator and Sink) Control 4 read-write 0 Detection off #0 1 Detection on ( Comparator and sink current on ) #1 IDPSRCE0 D+ Pin IDPSRC Output Control 1 read-write 0 Stop #0 1 10uA output #1 PDDETSTS0 D+ Pin 0.6 V Input Detection Status 9 read-only 0 Not detected #0 1 Detected #1 Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write Reserved These bits are read as 000000. The write value should be 000000. 10 5 read-write RPDME0 D- Pin Pull-Down Control 0 read-write 0 Pull-down off #0 1 Pull-down on #1 VDMSRCE0 D- Pin VDMSRC (0.6 V) Output Control 5 read-write 0 Stop #0 1 0.6V output #1 VDPSRCE0 D+ Pin VDPSRC (0.6 V) Output Control 3 read-write 0 Stop #0 1 0.6V output #1 USBINDX USB Request Index Register 0x58 16 read-write n 0x0 0x0 WINDEX IndexThese bits store the USB request wIndex value. 0 15 read-write USBLENG USB Request Length Register 0x5A 16 read-write n 0x0 0x0 WLENGTH LengthThese bits store the USB request wLength value. 0 15 read-write USBMC USB Module Control Register 0xCC 16 read-write n 0x0 0x0 Reserved These bits are read as 00000000. The write value should be 00000000. 8 7 read-write Reserved These bits are read as 00000. The write value should be 00000. 2 4 read-write Reserved These bits are read as 00000. The write value should be 00000. 2 4 read-write VDCEN USB Regulator On/Off Control 7 read-write 0 USB regulator off #0 1 USB regulator on #1 VDDUSBE USB Reference Power Supply Circuit On/Off Control 0 read-write 0 USB reference power supply circuit off #0 1 USB reference power supply circuit on #1 USBREQ USB Request Type Register 0x54 16 read-write n 0x0 0x0 BMREQUESTTYPE Request TypeThese bits store the USB request bmRequestType value. 0 7 read-write BREQUEST RequestThese bits store the USB request bRequest value. 8 7 read-write USBVAL USB Request Value Register 0x56 16 read-write n 0x0 0x0 WVALUE ValueThese bits store the USB request Value value. 0 15 read-write WDT Watchdog Timer WDT 0x0 0x0 0x1 registers n 0x2 0x5 registers n 0x8 0x1 registers n WDTCR WDT Control Register 0x2 16 read-write n 0x0 0x0 CKS Clock Division Ratio Selection 4 3 read-write others setting prohibited 0001 PCLK/4 #0001 0100 PCLK/64 #0100 0110 PCLK/512 #0110 0111 PCLK/2048 #0111 1000 PCLK/8192 #1000 1111 PCLK/128 #1111 Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write Reserved These bits are read as 00. The write value should be 00. 10 1 read-write RPES Window End Position Selection 8 1 read-write 00 75 percent #00 01 50 percent #01 10 25 percent #10 11 0 percent (window end position is not specified) #11 RPSS Window Start Position Selection 12 1 read-write 00 25 percent #00 01 50 percent #01 10 75 percent #10 11 100 percent (window start position is not specified) #11 TOPS Timeout Period Selection 0 1 read-write 00 1,024 cycles (03FFh) #00 01 4,096 cycles (0FFFh) #01 10 8,192 cycles (1FFFh) #10 11 16,384 cycles (3FFFh) #11 WDTCSTPR WDT Count Stop Control Register 0x8 8 read-write n 0x0 0x0 Reserved These bits are read as 0000000. The write value should be 0000000. 0 6 read-write SLCSTP Sleep-Mode Count Stop Control 7 read-write 0 Count stop is disabled. #0 1 Count is stopped at a transition to sleep mode. #1 WDTRCR WDT Reset Control Register 0x6 8 read-write n 0x0 0x0 RSTIRQS Reset Interrupt Request Selection 7 read-write 0 Non-maskable interrupt request or interrupt request output is enabled #0 1 Reset output is enabled. #1 WDTRR WDT Refresh Register 0x0 8 read-write n 0x0 0x0 WDTRR WDTRR is an 8-bit register that refreshes the down-counter of the WDT. 0 7 read-write WDTSR WDT Status Register 0x4 16 read-write n 0x0 0x0 CNTVAL Down-Counter ValueValue counted by the down-counter 0 13 read-only REFEF Refresh Error Flag 15 read-write zeroToClear modify 0 No refresh error occurred #0 1 Refresh error occurred #1 UNDFF Underflow Flag 14 read-write zeroToClear modify 0 No underflow occurred #0 1 Underflow occurred #1