STMicroelectronics STM32G471xx 2024.04.27 STM32G471xx CM4 r0p1 little true true 4 false 8 32 ADC1 Analog-to-Digital Converter ADC 0x0 0x0 0xD0 registers n ADC1_2 ADC1 and ADC2 global interrupt 18 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 19 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 19 CALFACT CALFACT Calibration Factors 0xB4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 CFGR CFGR configuration register 0xC 32 read-write n 0x0 0x0 ALIGN ALIGN 15 1 ALIGN_5 ALIGN_5 5 1 AUTDLY AUTDLY 14 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 AWDCH1CH AWDCH1CH 26 5 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS Injected Queue disable 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 3 2 CFGR2 CFGR2 configuration register 0x10 32 read-write n 0x0 0x0 BULB BULB 26 1 GCOMP GCOMP 16 1 JOVSE DMACFG 1 1 OVSR RES 2 3 OVSS ALIGN 5 4 ROVSE DMAEN 0 1 ROVSM EXTEN 10 1 SMPTRIG SMPTRIG 27 1 SWTRIG SWTRIG 25 1 TROVS Triggered Regular Oversampling 9 1 CR CR control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 32 read-write n 0x0 0x0 DIFSEL_0 Differential mode for channels 0 0 1 read-only DIFSEL_1_18 Differential mode for channels 15 to 1 1 18 read-write DR DR regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA Regular Data converted 0 16 GCOMP GCOMP Gain compensation Register 0xC0 32 read-write n 0x0 0x0 GCOMPCOEFF GCOMPCOEFF 0 14 IER IER interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ISR ISR interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 JDR1 JDR1 injected data register 1 0x80 32 read-only n 0x0 0x0 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 32 read-only n 0x0 0x0 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 32 read-only n 0x0 0x0 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 32 read-only n 0x0 0x0 JDATA4 JDATA4 0 16 JSQR JSQR injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 OFR1 OFR1 offset register 1 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR2 OFR2 offset register 2 0x64 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR3 OFR3 offset register 3 0x68 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR4 OFR4 offset register 4 0x6C 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 SMPR1 SMPR1 sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPR2 SMPR2 sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SQR1 SQR1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 L Regular channel sequence length 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 TR1 TR1 watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 AWDFILT AWDFILT 12 3 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 32 read-write n 0x0 0x0 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 32 read-write n 0x0 0x0 HT3 HT3 16 8 LT3 LT3 0 8 ADC12_Common Analog-to-Digital Converter ADC 0x0 0x0 0x11 registers n CCR CCR ADC common control register 0x8 32 read-write n 0x0 0x0 CH17SEL CH17 selection 23 1 CH18SEL CH18 selection 24 1 CKMODE ADC clock mode 16 2 DELAY Delay between 2 sampling phases 8 4 DMACFG DMA configuration (for multi-ADC mode) 13 1 DUAL Dual ADC mode selection 0 5 MDMA Direct memory access mode for multi ADC mode 14 2 PRESC ADC prescaler 18 4 VBATSEL VBAT selection 24 1 VREFEN VREFINT enable 22 1 VSENSESEL VTS selection 23 1 CDR CDR ADC common regular data register for dual and triple modes 0xC 32 read-only n 0x0 0x0 RDATA_MST Regular data of the master ADC 0 16 RDATA_SLV Regular data of the slave ADC 16 16 CSR CSR ADC Common status register 0x0 32 read-only n 0x0 0x0 ADDRDY_MST ADDRDY_MST 0 1 ADRDY_SLV ADRDY_SLV 16 1 AWD1_MST AWD1_MST 7 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_MST AWD2_MST 8 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_MST AWD3_MST 9 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 EOC_MST EOC_MST 2 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_SLV EOSMP_SLV 17 1 EOS_MST EOS_MST 3 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 JEOC_MST JEOC_MST 5 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_MST JEOS_MST 6 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 OVR_MST OVR_MST 4 1 OVR_SLV Overrun flag of the slave ADC 20 1 ADC2 Analog-to-Digital Converter ADC 0x0 0x0 0xD0 registers n AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 19 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 19 CALFACT CALFACT Calibration Factors 0xB4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 CFGR CFGR configuration register 0xC 32 read-write n 0x0 0x0 ALIGN ALIGN 15 1 ALIGN_5 ALIGN_5 5 1 AUTDLY AUTDLY 14 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 AWDCH1CH AWDCH1CH 26 5 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS Injected Queue disable 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 3 2 CFGR2 CFGR2 configuration register 0x10 32 read-write n 0x0 0x0 BULB BULB 26 1 GCOMP GCOMP 16 1 JOVSE DMACFG 1 1 OVSR RES 2 3 OVSS ALIGN 5 4 ROVSE DMAEN 0 1 ROVSM EXTEN 10 1 SMPTRIG SMPTRIG 27 1 SWTRIG SWTRIG 25 1 TROVS Triggered Regular Oversampling 9 1 CR CR control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 32 read-write n 0x0 0x0 DIFSEL_0 Differential mode for channels 0 0 1 read-only DIFSEL_1_18 Differential mode for channels 15 to 1 1 18 read-write DR DR regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA Regular Data converted 0 16 GCOMP GCOMP Gain compensation Register 0xC0 32 read-write n 0x0 0x0 GCOMPCOEFF GCOMPCOEFF 0 14 IER IER interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ISR ISR interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 JDR1 JDR1 injected data register 1 0x80 32 read-only n 0x0 0x0 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 32 read-only n 0x0 0x0 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 32 read-only n 0x0 0x0 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 32 read-only n 0x0 0x0 JDATA4 JDATA4 0 16 JSQR JSQR injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 OFR1 OFR1 offset register 1 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR2 OFR2 offset register 2 0x64 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR3 OFR3 offset register 3 0x68 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR4 OFR4 offset register 4 0x6C 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 SMPR1 SMPR1 sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPR2 SMPR2 sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SQR1 SQR1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 L Regular channel sequence length 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 TR1 TR1 watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 AWDFILT AWDFILT 12 3 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 32 read-write n 0x0 0x0 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 32 read-write n 0x0 0x0 HT3 HT3 16 8 LT3 LT3 0 8 ADC3 Analog-to-Digital Converter ADC 0x0 0x0 0xD0 registers n ADC3 ADC3 47 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 32 read-write n 0x0 0x0 AWD2CH AWD2CH 0 19 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 32 read-write n 0x0 0x0 AWD3CH AWD3CH 0 19 CALFACT CALFACT Calibration Factors 0xB4 32 read-write n 0x0 0x0 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 CFGR CFGR configuration register 0xC 32 read-write n 0x0 0x0 ALIGN ALIGN 15 1 ALIGN_5 ALIGN_5 5 1 AUTDLY AUTDLY 14 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 AWDCH1CH AWDCH1CH 26 5 CONT CONT 13 1 DISCEN DISCEN 16 1 DISCNUM DISCNUM 17 3 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 JDISCEN JDISCEN 20 1 JQDIS Injected Queue disable 31 1 JQM JQM 21 1 OVRMOD OVRMOD 12 1 RES RES 3 2 CFGR2 CFGR2 configuration register 0x10 32 read-write n 0x0 0x0 BULB BULB 26 1 GCOMP GCOMP 16 1 JOVSE DMACFG 1 1 OVSR RES 2 3 OVSS ALIGN 5 4 ROVSE DMAEN 0 1 ROVSM EXTEN 10 1 SMPTRIG SMPTRIG 27 1 SWTRIG SWTRIG 25 1 TROVS Triggered Regular Oversampling 9 1 CR CR control register 0x8 32 read-write n 0x0 0x0 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 ADSTART ADSTART 2 1 ADSTP ADSTP 4 1 ADVREGEN ADVREGEN 28 1 DEEPPWD DEEPPWD 29 1 JADSTART JADSTART 3 1 JADSTP JADSTP 5 1 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 32 read-write n 0x0 0x0 DIFSEL_0 Differential mode for channels 0 0 1 read-only DIFSEL_1_18 Differential mode for channels 15 to 1 1 18 read-write DR DR regular Data Register 0x40 32 read-only n 0x0 0x0 RDATA Regular Data converted 0 16 GCOMP GCOMP Gain compensation Register 0xC0 32 read-write n 0x0 0x0 GCOMPCOEFF GCOMPCOEFF 0 14 IER IER interrupt enable register 0x4 32 read-write n 0x0 0x0 ADRDYIE ADRDYIE 0 1 AWD1IE AWD1IE 7 1 AWD2IE AWD2IE 8 1 AWD3IE AWD3IE 9 1 EOCIE EOCIE 2 1 EOSIE EOSIE 3 1 EOSMPIE EOSMPIE 1 1 JEOCIE JEOCIE 5 1 JEOSIE JEOSIE 6 1 JQOVFIE JQOVFIE 10 1 OVRIE OVRIE 4 1 ISR ISR interrupt and status register 0x0 32 read-write n 0x0 0x0 ADRDY ADRDY 0 1 AWD1 AWD1 7 1 AWD2 AWD2 8 1 AWD3 AWD3 9 1 EOC EOC 2 1 EOS EOS 3 1 EOSMP EOSMP 1 1 JEOC JEOC 5 1 JEOS JEOS 6 1 JQOVF JQOVF 10 1 OVR OVR 4 1 JDR1 JDR1 injected data register 1 0x80 32 read-only n 0x0 0x0 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 32 read-only n 0x0 0x0 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 32 read-only n 0x0 0x0 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 32 read-only n 0x0 0x0 JDATA4 JDATA4 0 16 JSQR JSQR injected sequence register 0x4C 32 read-write n 0x0 0x0 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 JSQ1 JSQ1 9 5 JSQ2 JSQ2 15 5 JSQ3 JSQ3 21 5 JSQ4 JSQ4 27 5 OFR1 OFR1 offset register 1 0x60 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR2 OFR2 offset register 2 0x64 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR3 OFR3 offset register 3 0x68 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 OFR4 OFR4 offset register 4 0x6C 32 read-write n 0x0 0x0 OFFSET1 OFFSET1 0 12 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1_EN OFFSET1_EN 31 1 OFFSETPOS OFFSETPOS 24 1 SATEN SATEN 25 1 SMPR1 SMPR1 sample time register 1 0x14 32 read-write n 0x0 0x0 SMP0 SMP0 0 3 SMP1 SMP1 3 3 SMP2 SMP2 6 3 SMP3 SMP3 9 3 SMP4 SMP4 12 3 SMP5 SMP5 15 3 SMP6 SMP6 18 3 SMP7 SMP7 21 3 SMP8 SMP8 24 3 SMP9 SMP9 27 3 SMPPLUS Addition of one clock cycle to the sampling time 31 1 SMPR2 SMPR2 sample time register 2 0x18 32 read-write n 0x0 0x0 SMP10 SMP10 0 3 SMP11 SMP11 3 3 SMP12 SMP12 6 3 SMP13 SMP13 9 3 SMP14 SMP14 12 3 SMP15 SMP15 15 3 SMP16 SMP16 18 3 SMP17 SMP17 21 3 SMP18 SMP18 24 3 SQR1 SQR1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 L Regular channel sequence length 0 4 SQ1 SQ1 6 5 SQ2 SQ2 12 5 SQ3 SQ3 18 5 SQ4 SQ4 24 5 SQR2 SQR2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 SQ5 SQ5 0 5 SQ6 SQ6 6 5 SQ7 SQ7 12 5 SQ8 SQ8 18 5 SQ9 SQ9 24 5 SQR3 SQR3 regular sequence register 3 0x38 32 read-write n 0x0 0x0 SQ10 SQ10 0 5 SQ11 SQ11 6 5 SQ12 SQ12 12 5 SQ13 SQ13 18 5 SQ14 SQ14 24 5 SQR4 SQR4 regular sequence register 4 0x3C 32 read-write n 0x0 0x0 SQ15 SQ15 0 5 SQ16 SQ16 6 5 TR1 TR1 watchdog threshold register 1 0x20 32 read-write n 0x0 0x0 AWDFILT AWDFILT 12 3 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 32 read-write n 0x0 0x0 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 32 read-write n 0x0 0x0 HT3 HT3 16 8 LT3 LT3 0 8 ADC345_Common Analog-to-Digital Converter ADC 0x0 0x0 0x11 registers n CCR CCR ADC common control register 0x8 32 read-write n 0x0 0x0 CH17SEL CH17 selection 23 1 CH18SEL CH18 selection 24 1 CKMODE ADC clock mode 16 2 DELAY Delay between 2 sampling phases 8 4 DMACFG DMA configuration (for multi-ADC mode) 13 1 DUAL Dual ADC mode selection 0 5 MDMA Direct memory access mode for multi ADC mode 14 2 PRESC ADC prescaler 18 4 VBATSEL VBAT selection 24 1 VREFEN VREFINT enable 22 1 VSENSESEL VTS selection 23 1 CDR CDR ADC common regular data register for dual and triple modes 0xC 32 read-only n 0x0 0x0 RDATA_MST Regular data of the master ADC 0 16 RDATA_SLV Regular data of the slave ADC 16 16 CSR CSR ADC Common status register 0x0 32 read-only n 0x0 0x0 ADDRDY_MST ADDRDY_MST 0 1 ADRDY_SLV ADRDY_SLV 16 1 AWD1_MST AWD1_MST 7 1 AWD1_SLV Analog watchdog 1 flag of the slave ADC 23 1 AWD2_MST AWD2_MST 8 1 AWD2_SLV Analog watchdog 2 flag of the slave ADC 24 1 AWD3_MST AWD3_MST 9 1 AWD3_SLV Analog watchdog 3 flag of the slave ADC 25 1 EOC_MST EOC_MST 2 1 EOC_SLV End of regular conversion of the slave ADC 18 1 EOSMP_MST EOSMP_MST 1 1 EOSMP_SLV EOSMP_SLV 17 1 EOS_MST EOS_MST 3 1 EOS_SLV End of regular sequence flag of the slave ADC 19 1 JEOC_MST JEOC_MST 5 1 JEOC_SLV End of injected conversion flag of the slave ADC 21 1 JEOS_MST JEOS_MST 6 1 JEOS_SLV End of injected sequence flag of the slave ADC 22 1 JQOVF_MST JQOVF_MST 10 1 JQOVF_SLV Injected Context Queue Overflow flag of the slave ADC 26 1 OVR_MST OVR_MST 4 1 OVR_SLV Overrun flag of the slave ADC 20 1 AES Advanced encryption standard hardware accelerator AES 0x0 0x0 0x400 registers n AES AES 85 CR CR control register 0x0 32 read-write n 0x0 0x0 CCFC Computation Complete Flag Clear 7 1 CCFIE CCF flag interrupt enable 9 1 CHMOD AES chaining mode 5 2 CHMOD_2 CHMOD_2 16 1 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 DMAINEN Enable DMA management of data input phase 11 1 DMAOUTEN Enable DMA management of data output phase 12 1 EN AES enable 0 1 ERRC Error clear 8 1 ERRIE Error interrupt enable 10 1 GCMPH GCMPH 13 2 KEYSIZE KEYSIZE 18 1 MODE AES operating mode 3 2 NPBLB NPBLB 20 4 DINR DINR data input register 0x8 32 read-write n 0x0 0x0 AES_DINR Data Input Register 0 32 DOUTR DOUTR data output register 0xC 32 read-only n 0x0 0x0 AES_DOUTR Data output register 0 32 IVR0 IVR0 initialization vector register 0 0x20 32 read-write n 0x0 0x0 AES_IVR0 initialization vector register (LSB IVR [31:0]) 0 32 IVR1 IVR1 initialization vector register 1 0x24 32 read-write n 0x0 0x0 AES_IVR1 Initialization Vector Register (IVR [63:32]) 0 32 IVR2 IVR2 initialization vector register 2 0x28 32 read-write n 0x0 0x0 AES_IVR2 Initialization Vector Register (IVR [95:64]) 0 32 IVR3 IVR3 initialization vector register 3 0x2C 32 read-write n 0x0 0x0 AES_IVR3 Initialization Vector Register (MSB IVR [127:96]) 0 32 KEYR0 KEYR0 key register 0 0x10 32 read-write n 0x0 0x0 AES_KEYR0 Data Output Register (LSB key [31:0]) 0 32 KEYR1 KEYR1 key register 1 0x14 32 read-write n 0x0 0x0 AES_KEYR1 AES key register (key [63:32]) 0 32 KEYR2 KEYR2 key register 2 0x18 32 read-write n 0x0 0x0 AES_KEYR2 AES key register (key [95:64]) 0 32 KEYR3 KEYR3 key register 3 0x1C 32 read-write n 0x0 0x0 AES_KEYR3 AES key register (MSB key [127:96]) 0 32 KEYR4 KEYR4 key register 4 0x30 32 read-write n 0x0 0x0 KEY AES key 0 32 KEYR5 KEYR5 key register 5 0x34 32 read-write n 0x0 0x0 KEY AES key 0 32 KEYR6 KEYR6 key register 6 0x38 32 read-write n 0x0 0x0 KEY AES key 0 32 KEYR7 KEYR7 key register 7 0x3C 32 read-write n 0x0 0x0 KEY AES key 0 32 SR SR status register 0x4 32 read-only n 0x0 0x0 BUSY BUSY 3 1 CCF Computation complete flag 0 1 RDERR Read error flag 1 1 WRERR Write error flag 2 1 SUSP0R SUSP0R suspend registers 0x40 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP1R SUSP1R suspend registers 0x44 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP2R SUSP2R suspend registers 0x48 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP3R SUSP3R suspend registers 0x4C 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP4R SUSP4R suspend registers 0x50 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP5R SUSP5R suspend registers 0x54 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP6R SUSP6R suspend registers 0x58 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 SUSP7R SUSP7R suspend registers 0x5C 32 read-write n 0x0 0x0 SUSP AES suspend 0 32 COMP Comparator control and status register COMP 0x0 0x0 0x100 registers n COMP1_2_3 COMP1_2_3 64 COMP4 COMP4_5_6 65 C1CSR COMP_C1CSR Comparator control/status register 0x0 32 read-write n 0x0 0x0 BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write COMP_DEGLITCH_EN COMP_DEGLITCH_EN 1 1 read-write EN EN 0 1 read-write HYST HYST 16 3 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write LOCK LOCK 31 1 read-write POL POL 15 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only C2CSR COMP_C2CSR Comparator control/status register 0x4 32 read-write n 0x0 0x0 BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write COMP_DEGLITCH_EN COMP_DEGLITCH_EN 1 1 read-write EN EN 0 1 read-write HYST HYST 16 3 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write LOCK LOCK 31 1 read-write POL POL 15 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only C3CSR COMP_C3CSR Comparator control/status register 0x8 32 read-write n 0x0 0x0 BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write COMP_DEGLITCH_EN COMP_DEGLITCH_EN 1 1 read-write EN EN 0 1 read-write HYST HYST 16 3 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write LOCK LOCK 31 1 read-write POL POL 15 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only C4CSR COMP_C4CSR Comparator control/status register 0x12 32 read-write n 0x0 0x0 BLANKSEL BLANKSEL 19 3 read-write BRGEN BRGEN 22 1 read-write COMP_DEGLITCH_EN COMP_DEGLITCH_EN 1 1 read-write EN EN 0 1 read-write HYST HYST 16 3 read-write INMSEL INMSEL 4 3 read-write INPSEL INPSEL 8 1 read-write LOCK LOCK 31 1 read-write POL POL 15 1 read-write SCALEN SCALEN 23 1 read-write VALUE VALUE 30 1 read-only CORDIC CORDIC Co-processor CORDIC 0x0 0x0 0x400 registers n Cordic Cordic 100 CSR CSR CORDIC Control Status register 0x0 32 read-write n 0x0 0x0 ARGSIZE ARGSIZE 22 1 DMAREN DMAREN 17 1 DMAWEN DMAWEN 18 1 FUNC FUNC 0 4 IEN IEN 16 1 NARGS NARGS 20 1 NRES NRES 19 1 PRECISION PRECISION 4 4 RESSIZE RESSIZE 21 1 RRDY RRDY 31 1 SCALE SCALE 8 3 RDATA RDATA FMAC Read Data register 0x8 32 read-only n 0x0 0x0 RES RES 0 32 WDATA WDATA FMAC Write Data register 0x4 32 read-write n 0x0 0x0 ARG ARG 0 32 CRC Cyclic redundancy check calculation unit CRC 0x0 0x0 0x400 registers n CR CR Control register 0x8 32 read-write n 0x0 0x0 POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only REV_IN Reverse input data 5 2 read-write REV_OUT Reverse output data 7 1 read-write DR DR Data register 0x0 32 read-write n 0x0 0x0 DR Data register bits 0 32 IDR IDR Independent data register 0x4 32 read-write n 0x0 0x0 IDR General-purpose 8-bit data register bits 0 32 INIT INIT Initial CRC value 0x10 32 read-write n 0x0 0x0 CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 32 read-write n 0x0 0x0 POL Programmable polynomial 0 32 CRS CRS CRS 0x0 0x0 0x400 registers n CFGR CFGR This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. 0x4 32 read-write n 0x0 0x0 FELIM Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. 16 8 RELOAD Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. 0 16 SYNCDIV SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 24 3 SYNCPOL SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. 31 1 SYNCSRC SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. 28 2 CR CR CRS control register 0x0 32 read-write n 0x0 0x0 AUTOTRIMEN Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. 6 1 read-write CEN Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 5 1 read-write ERRIE Synchronization or trimming error interrupt enable 2 1 read-write ESYNCIE Expected SYNC interrupt enable 3 1 read-write SWSYNC Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 7 1 read-write SYNCOKIE SYNC event OK interrupt enable 0 1 read-write SYNCWARNIE SYNC warning interrupt enable 1 1 read-write TRIM HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. 8 7 read-write ICR ICR CRS interrupt flag clear register 0xC 32 read-write n 0x0 0x0 ERRC Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. 2 1 ESYNCC Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. 3 1 SYNCOKC SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. 0 1 SYNCWARNC SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. 1 1 ISR ISR CRS interrupt and status register 0x8 32 read-only n 0x0 0x0 ERRF Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. 2 1 ESYNCF Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. 3 1 FECAP Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. 16 16 FEDIR Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. 15 1 SYNCERR SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 8 1 SYNCMISS SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 9 1 SYNCOKF SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. 0 1 SYNCWARNF SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. 1 1 TRIMOVF Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. 10 1 DAC1 Digital-to-analog converter DAC 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 TEN1 DAC channel1 trigger enable 1 1 TEN2 DAC channel2 trigger enable 17 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 HFSEL High frequency interface mode selection 14 2 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode 16 3 SINFORMAT1 Enable signed format for DAC channel1 9 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only DAC1RDY DAC channel1 ready status bit 11 1 read-write DAC2RDY DAC channel 2 ready status bit 27 1 read-write DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write DORSTAT1 DAC channel1 output register status bit 12 1 read-write DORSTAT2 DAC channel 2 output register status bit 28 1 read-write DAC_STMODR DAC_STMODR Sawtooth Mode register 0x60 32 read-write n 0x0 0x0 STINCTRIGSEL1 DAC Channel 1 Sawtooth Increment trigger selection 8 4 STINCTRIGSEL2 DAC Channel 2 Sawtooth Increment trigger selection 24 4 STRSTTRIGSEL1 DAC Channel 1 Sawtooth Reset trigger selection 0 4 STRSTTRIGSEL2 DAC Channel 1 Sawtooth Reset trigger selection 16 4 DAC_STR1 DAC_STR1 Sawtooth register 0x58 32 read-write n 0x0 0x0 STDIR1 DAC Channel1 Sawtooth direction setting 12 1 STINCDATA1 DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA1 DAC Channel 1 Sawtooth reset value 0 12 DAC_STR2 DAC_STR2 Sawtooth register 0x5C 32 read-write n 0x0 0x0 STDIR2 DAC Channel2 Sawtooth direction setting 12 1 STINCDATA2 DAC CH2 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA2 DAC Channel 2 Sawtooth reset value 0 12 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 SWTRIGB1 DAC channel1 software trigger B 16 1 SWTRIGB2 DAC channel2 software trigger B 17 1 DAC2 Digital-to-analog converter DAC 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 TEN1 DAC channel1 trigger enable 1 1 TEN2 DAC channel2 trigger enable 17 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 HFSEL High frequency interface mode selection 14 2 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode 16 3 SINFORMAT1 Enable signed format for DAC channel1 9 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only DAC1RDY DAC channel1 ready status bit 11 1 read-write DAC2RDY DAC channel 2 ready status bit 27 1 read-write DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write DORSTAT1 DAC channel1 output register status bit 12 1 read-write DORSTAT2 DAC channel 2 output register status bit 28 1 read-write DAC_STMODR DAC_STMODR Sawtooth Mode register 0x60 32 read-write n 0x0 0x0 STINCTRIGSEL1 DAC Channel 1 Sawtooth Increment trigger selection 8 4 STINCTRIGSEL2 DAC Channel 2 Sawtooth Increment trigger selection 24 4 STRSTTRIGSEL1 DAC Channel 1 Sawtooth Reset trigger selection 0 4 STRSTTRIGSEL2 DAC Channel 1 Sawtooth Reset trigger selection 16 4 DAC_STR1 DAC_STR1 Sawtooth register 0x58 32 read-write n 0x0 0x0 STDIR1 DAC Channel1 Sawtooth direction setting 12 1 STINCDATA1 DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA1 DAC Channel 1 Sawtooth reset value 0 12 DAC_STR2 DAC_STR2 Sawtooth register 0x5C 32 read-write n 0x0 0x0 STDIR2 DAC Channel2 Sawtooth direction setting 12 1 STINCDATA2 DAC CH2 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA2 DAC Channel 2 Sawtooth reset value 0 12 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 SWTRIGB1 DAC channel1 software trigger B 16 1 SWTRIGB2 DAC channel2 software trigger B 17 1 DAC3 Digital-to-analog converter DAC 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 TEN1 DAC channel1 trigger enable 1 1 TEN2 DAC channel2 trigger enable 17 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 HFSEL High frequency interface mode selection 14 2 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode 16 3 SINFORMAT1 Enable signed format for DAC channel1 9 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only DAC1RDY DAC channel1 ready status bit 11 1 read-write DAC2RDY DAC channel 2 ready status bit 27 1 read-write DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write DORSTAT1 DAC channel1 output register status bit 12 1 read-write DORSTAT2 DAC channel 2 output register status bit 28 1 read-write DAC_STMODR DAC_STMODR Sawtooth Mode register 0x60 32 read-write n 0x0 0x0 STINCTRIGSEL1 DAC Channel 1 Sawtooth Increment trigger selection 8 4 STINCTRIGSEL2 DAC Channel 2 Sawtooth Increment trigger selection 24 4 STRSTTRIGSEL1 DAC Channel 1 Sawtooth Reset trigger selection 0 4 STRSTTRIGSEL2 DAC Channel 1 Sawtooth Reset trigger selection 16 4 DAC_STR1 DAC_STR1 Sawtooth register 0x58 32 read-write n 0x0 0x0 STDIR1 DAC Channel1 Sawtooth direction setting 12 1 STINCDATA1 DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA1 DAC Channel 1 Sawtooth reset value 0 12 DAC_STR2 DAC_STR2 Sawtooth register 0x5C 32 read-write n 0x0 0x0 STDIR2 DAC Channel2 Sawtooth direction setting 12 1 STINCDATA2 DAC CH2 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA2 DAC Channel 2 Sawtooth reset value 0 12 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 SWTRIGB1 DAC channel1 software trigger B 16 1 SWTRIGB2 DAC channel2 software trigger B 17 1 DAC4 Digital-to-analog converter DAC 0x0 0x0 0x400 registers n DAC_CCR DAC_CCR DAC calibration control register 0x38 32 read-write n 0x0 0x0 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_CR DAC_CR DAC control register 0x0 32 read-write n 0x0 0x0 CEN1 DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 14 1 CEN2 DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 30 1 DMAEN1 DAC channel1 DMA enable This bit is set and cleared by software. 12 1 DMAEN2 DAC channel2 DMA enable This bit is set and cleared by software. 28 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 13 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 29 1 EN1 DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 1 EN2 DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 16 1 MAMP1 DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 8 4 MAMP2 DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 24 4 TEN1 DAC channel1 trigger enable 1 1 TEN2 DAC channel2 trigger enable 17 1 TSEL1 DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 2 4 TSEL2 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). 18 4 WAVE1 DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). 6 2 WAVE2 DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) 22 2 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 4 12 DACC2DHR DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 20 12 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 0 12 DACC2DHR DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 16 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC1DHRB DAC channel1 8-bit right-aligned data 8 8 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 32 read-write n 0x0 0x0 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DACC1DHR DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 0 8 DACC2DHR DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 32 read-only n 0x0 0x0 DACC1DOR DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 32 read-only n 0x0 0x0 DACC2DOR DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_MCR DAC_MCR DAC mode control register 0x3C 32 read-write n 0x0 0x0 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 HFSEL High frequency interface mode selection 14 2 MODE1 DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode 0 3 MODE2 DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode 16 3 SINFORMAT1 Enable signed format for DAC channel1 9 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 32 read-write n 0x0 0x0 THOLD1 DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 32 read-write n 0x0 0x0 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI 16 8 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 32 read-write n 0x0 0x0 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. 0 10 DAC_SHSR2 DAC_SHSR2 DAC Sample and Hold sample time register 2 0x44 32 read-write n 0x0 0x0 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. 0 10 DAC_SR DAC_SR DAC status register 0x34 32 read-write n 0x0 0x0 BWST1 DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). 15 1 read-only BWST2 DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). 31 1 read-only CAL_FLAG1 DAC Channel 1 calibration offset status This bit is set and cleared by hardware 14 1 read-only CAL_FLAG2 DAC Channel 2 calibration offset status This bit is set and cleared by hardware 30 1 read-only DAC1RDY DAC channel1 ready status bit 11 1 read-write DAC2RDY DAC channel 2 ready status bit 27 1 read-write DMAUDR1 DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 13 1 read-write DMAUDR2 DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 29 1 read-write DORSTAT1 DAC channel1 output register status bit 12 1 read-write DORSTAT2 DAC channel 2 output register status bit 28 1 read-write DAC_STMODR DAC_STMODR Sawtooth Mode register 0x60 32 read-write n 0x0 0x0 STINCTRIGSEL1 DAC Channel 1 Sawtooth Increment trigger selection 8 4 STINCTRIGSEL2 DAC Channel 2 Sawtooth Increment trigger selection 24 4 STRSTTRIGSEL1 DAC Channel 1 Sawtooth Reset trigger selection 0 4 STRSTTRIGSEL2 DAC Channel 1 Sawtooth Reset trigger selection 16 4 DAC_STR1 DAC_STR1 Sawtooth register 0x58 32 read-write n 0x0 0x0 STDIR1 DAC Channel1 Sawtooth direction setting 12 1 STINCDATA1 DAC CH1 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA1 DAC Channel 1 Sawtooth reset value 0 12 DAC_STR2 DAC_STR2 Sawtooth register 0x5C 32 read-write n 0x0 0x0 STDIR2 DAC Channel2 Sawtooth direction setting 12 1 STINCDATA2 DAC CH2 Sawtooth increment value (12.4 bit format) 16 16 STRSTDATA2 DAC Channel 2 Sawtooth reset value 0 12 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 32 write-only n 0x0 0x0 SWTRIG1 DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 0 1 SWTRIG2 DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. 1 1 SWTRIGB1 DAC channel1 software trigger B 16 1 SWTRIGB2 DAC channel2 software trigger B 17 1 DBGMCU Debug support DBGMCU 0x0 0x0 0x400 registers n APB1H_FZ APB1H_FZ APB Low Freeze Register 2 0xC 32 read-write n 0x0 0x0 DBG_I2C4_STOP DBG_I2C4_STOP 1 1 APB1L_FZ APB1L_FZ APB Low Freeze Register 1 0x8 32 read-write n 0x0 0x0 DBG_I2C1_STOP I2C1 SMBUS timeout mode stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout mode stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout mode stopped when core is halted 30 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_LPTIMER_STOP LPTIM1 counter stopped when core is halted 31 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_TIM3_STOP TIM3 counter stopped when core is halted 1 1 DBG_TIM4_STOP TIM4 counter stopped when core is halted 2 1 DBG_TIM5_STOP TIM5 counter stopped when core is halted 3 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 APB2_FZ APB2_FZ APB High Freeze Register 0x10 32 read-write n 0x0 0x0 DBG_HRTIM0_STOP DBG_HRTIM0_STOP 26 1 DBG_HRTIM1_STOP DBG_HRTIM0_STOP 27 1 DBG_HRTIM2_STOP DBG_HRTIM0_STOP 28 1 DBG_HRTIM3_STOP DBG_HRTIM0_STOP 29 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP TIM17 counter stopped when core is halted 18 1 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM20_STOP TIM20counter stopped when core is halted 20 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 13 1 CR CR Debug MCU Configuration Register 0x4 32 read-write n 0x0 0x0 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STANDBY Debug Standby Mode 2 1 DBG_STOP Debug Stop Mode 1 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 IDCODE IDCODE MCU Device ID Code Register 0x0 32 read-only n 0x0 0x0 DEV_ID Device Identifier 0 16 REV_ID Revision Identifier 16 16 DMA1 DMA controller DMA 0x0 0x0 0x400 registers n DMA1_CH1 DMA1 channel 1 interrupt 11 DMA1_CH2 DMA1 channel 2 interrupt 12 DMA1_CH3 DMA1 channel 3 interrupt 13 DMA1_CH4 DMA1 channel 4 interrupt 14 DMA1_CH5 DMA1 channel 5 interrupt 15 DMA1_CH6 DMA1 channel 6 interrupt 16 DMA1_CH8 DMA1_CH8 96 CCR1 CCR1 DMA channel 1 configuration register 0x8 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR2 CCR2 DMA channel 2 configuration register 0x1C 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR3 CCR3 DMA channel 3 configuration register 0x30 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR4 CCR4 DMA channel 3 configuration register 0x44 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR5 CCR5 DMA channel 4 configuration register 0x58 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR6 CCR6 DMA channel 5 configuration register 0x6C 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR7 CCR7 DMA channel 6 configuration register 0x80 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR8 CCR8 DMA channel 7 configuration register 0x94 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CMAR1 CMAR1 DMA channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR2 CMAR2 DMA channel x memory address register 0x28 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR3 CMAR3 DMA channel x memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR4 CMAR4 DMA channel x memory address register 0x50 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR5 CMAR5 DMA channel x memory address register 0x64 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR6 CMAR6 DMA channel x memory address register 0x78 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR7 CMAR7 DMA channel x memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR8 CMAR8 DMA channel x memory address register 0xA0 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CNDTR1 CNDTR1 channel x number of data to transfer register 0xC 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR2 CNDTR2 channel x number of data to transfer register 0x20 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR3 CNDTR3 channel x number of data to transfer register 0x34 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR4 CNDTR4 channel x number of data to transfer register 0x48 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR5 CNDTR5 channel x number of data to transfer register 0x5C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR6 CNDTR6 channel x number of data to transfer register 0x70 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR7 CNDTR7 channel x number of data to transfer register 0x84 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR8 CNDTR8 channel x number of data to transfer register 0x98 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CPAR1 CPAR1 DMA channel x peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 DMA channel x peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR3 DMA channel x peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 DMA channel x peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 DMA channel x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 DMA channel x peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 DMA channel x peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR8 CPAR8 DMA channel x peripheral address register 0x9C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 IFCR IFCR DMA interrupt flag clear register 0x4 32 write-only n 0x0 0x0 GIF1 GIF1 0 1 GIF2 GIF2 4 1 GIF3 GIF3 8 1 GIF4 GIF4 12 1 GIF5 GIF5 16 1 GIF6 GIF6 20 1 GIF7 GIF7 24 1 GIF8 GIF8 28 1 HTIF1 HTIF1 2 1 HTIF2 HTIF2 6 1 HTIF3 HTIF3 10 1 HTIF4 HTIF4 14 1 HTIF5 HTIF5 18 1 HTIF6 HTIF6 22 1 HTIF7 HTIF7 26 1 HTIF8 HTIF8 30 1 TCIF1 TCIF1 1 1 TCIF2 TCIF2 5 1 TCIF3 TCIF3 9 1 TCIF4 TCIF4 13 1 TCIF5 TCIF5 17 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 25 1 TCIF8 TCIF8 29 1 TEIF1 TEIF1 3 1 TEIF2 TEIF2 7 1 TEIF3 TEIF3 11 1 TEIF4 TEIF4 15 1 TEIF5 TEIF5 19 1 TEIF6 TEIF6 23 1 TEIF7 TEIF7 27 1 TEIF8 TEIF8 31 1 ISR ISR interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 GIF1 0 1 GIF2 GIF2 4 1 GIF3 GIF3 8 1 GIF4 GIF4 12 1 GIF5 GIF5 16 1 GIF6 GIF6 20 1 GIF7 GIF7 24 1 GIF8 GIF8 28 1 HTIF1 HTIF1 2 1 HTIF2 HTIF2 6 1 HTIF3 HTIF3 10 1 HTIF4 HTIF4 14 1 HTIF5 HTIF5 18 1 HTIF6 HTIF6 22 1 HTIF7 HTIF7 26 1 HTIF8 HTIF8 30 1 TCIF1 TCIF1 1 1 TCIF2 TCIF2 5 1 TCIF3 TCIF3 9 1 TCIF4 TCIF4 13 1 TCIF5 TCIF5 17 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 25 1 TCIF8 TCIF8 29 1 TEIF1 TEIF1 3 1 TEIF2 TEIF2 7 1 TEIF3 TEIF3 11 1 TEIF4 TEIF4 15 1 TEIF5 TEIF5 19 1 TEIF6 TEIF6 23 1 TEIF7 TEIF7 27 1 TEIF8 TEIF8 31 1 DMA2 DMA controller DMA 0x0 0x0 0x400 registers n DMA1_CH7 DMA1 Channel 7 interrupt 17 DMA2_CH1 DMA2_CH1 56 DMA2_CH2 DMA2_CH2 57 DMA2_CH3 DMA2_CH3 58 DMA2_CH4 DMA2_CH4 59 DMA2_CH5 DMA2_CH5 60 DMA2_CH6 DMA2_CH6 97 DMA2_CH7 DMA2_CH7 98 DMA2_CH8 DMA2_CH8 99 CCR1 CCR1 DMA channel 1 configuration register 0x8 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR2 CCR2 DMA channel 2 configuration register 0x1C 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR3 CCR3 DMA channel 3 configuration register 0x30 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR4 CCR4 DMA channel 3 configuration register 0x44 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR5 CCR5 DMA channel 4 configuration register 0x58 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR6 CCR6 DMA channel 5 configuration register 0x6C 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR7 CCR7 DMA channel 6 configuration register 0x80 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CCR8 CCR8 DMA channel 7 configuration register 0x94 32 read-write n 0x0 0x0 CIRC CIRC 5 1 DIR DIR 4 1 EN channel enable 0 1 HTIE HTIE 2 1 MEM2MEM MEM2MEM 14 1 MINC MINC 7 1 MSIZE MSIZE 10 2 PINC PINC 6 1 PL PL 12 2 PSIZE PSIZE 8 2 TCIE TCIE 1 1 TEIE TEIE 3 1 CMAR1 CMAR1 DMA channel x memory address register 0x14 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR2 CMAR2 DMA channel x memory address register 0x28 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR3 CMAR3 DMA channel x memory address register 0x3C 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR4 CMAR4 DMA channel x memory address register 0x50 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR5 CMAR5 DMA channel x memory address register 0x64 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR6 CMAR6 DMA channel x memory address register 0x78 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR7 CMAR7 DMA channel x memory address register 0x8C 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CMAR8 CMAR8 DMA channel x memory address register 0xA0 32 read-write n 0x0 0x0 MA Memory 1 address (used in case of Double buffer mode) 0 32 CNDTR1 CNDTR1 channel x number of data to transfer register 0xC 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR2 CNDTR2 channel x number of data to transfer register 0x20 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR3 CNDTR3 channel x number of data to transfer register 0x34 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR4 CNDTR4 channel x number of data to transfer register 0x48 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR5 CNDTR5 channel x number of data to transfer register 0x5C 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR6 CNDTR6 channel x number of data to transfer register 0x70 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR7 CNDTR7 channel x number of data to transfer register 0x84 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CNDTR8 CNDTR8 channel x number of data to transfer register 0x98 32 read-write n 0x0 0x0 NDT Number of data items to transfer 0 16 CPAR1 CPAR1 DMA channel x peripheral address register 0x10 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR2 CPAR2 DMA channel x peripheral address register 0x24 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR3 CPAR3 DMA channel x peripheral address register 0x38 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR4 CPAR4 DMA channel x peripheral address register 0x4C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR5 CPAR5 DMA channel x peripheral address register 0x60 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR6 CPAR6 DMA channel x peripheral address register 0x74 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR7 CPAR7 DMA channel x peripheral address register 0x88 32 read-write n 0x0 0x0 PA Peripheral address 0 32 CPAR8 CPAR8 DMA channel x peripheral address register 0x9C 32 read-write n 0x0 0x0 PA Peripheral address 0 32 IFCR IFCR DMA interrupt flag clear register 0x4 32 write-only n 0x0 0x0 GIF1 GIF1 0 1 GIF2 GIF2 4 1 GIF3 GIF3 8 1 GIF4 GIF4 12 1 GIF5 GIF5 16 1 GIF6 GIF6 20 1 GIF7 GIF7 24 1 GIF8 GIF8 28 1 HTIF1 HTIF1 2 1 HTIF2 HTIF2 6 1 HTIF3 HTIF3 10 1 HTIF4 HTIF4 14 1 HTIF5 HTIF5 18 1 HTIF6 HTIF6 22 1 HTIF7 HTIF7 26 1 HTIF8 HTIF8 30 1 TCIF1 TCIF1 1 1 TCIF2 TCIF2 5 1 TCIF3 TCIF3 9 1 TCIF4 TCIF4 13 1 TCIF5 TCIF5 17 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 25 1 TCIF8 TCIF8 29 1 TEIF1 TEIF1 3 1 TEIF2 TEIF2 7 1 TEIF3 TEIF3 11 1 TEIF4 TEIF4 15 1 TEIF5 TEIF5 19 1 TEIF6 TEIF6 23 1 TEIF7 TEIF7 27 1 TEIF8 TEIF8 31 1 ISR ISR interrupt status register 0x0 32 read-only n 0x0 0x0 GIF1 GIF1 0 1 GIF2 GIF2 4 1 GIF3 GIF3 8 1 GIF4 GIF4 12 1 GIF5 GIF5 16 1 GIF6 GIF6 20 1 GIF7 GIF7 24 1 GIF8 GIF8 28 1 HTIF1 HTIF1 2 1 HTIF2 HTIF2 6 1 HTIF3 HTIF3 10 1 HTIF4 HTIF4 14 1 HTIF5 HTIF5 18 1 HTIF6 HTIF6 22 1 HTIF7 HTIF7 26 1 HTIF8 HTIF8 30 1 TCIF1 TCIF1 1 1 TCIF2 TCIF2 5 1 TCIF3 TCIF3 9 1 TCIF4 TCIF4 13 1 TCIF5 TCIF5 17 1 TCIF6 TCIF6 21 1 TCIF7 TCIF7 25 1 TCIF8 TCIF8 29 1 TEIF1 TEIF1 3 1 TEIF2 TEIF2 7 1 TEIF3 TEIF3 11 1 TEIF4 TEIF4 15 1 TEIF5 TEIF5 19 1 TEIF6 TEIF6 23 1 TEIF7 TEIF7 27 1 TEIF8 TEIF8 31 1 DMAMUX DMAMUX DMAMUX 0x0 0x0 0x400 registers n DMAMUX_OVR DMAMUX_OVR 94 C0CR C0CR DMAMux - DMA request line multiplexer channel x control register 0x0 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C10CR C10CR DMAMux - DMA request line multiplexer channel x control register 0x28 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C11CR C11CR DMAMux - DMA request line multiplexer channel x control register 0x2C 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C12CR C12CR DMAMux - DMA request line multiplexer channel x control register 0x30 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C13CR C13CR DMAMux - DMA request line multiplexer channel x control register 0x34 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C14CR C14CR DMAMux - DMA request line multiplexer channel x control register 0x38 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C15CR C15CR DMAMux - DMA request line multiplexer channel x control register 0x3C 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C1CR C1CR DMAMux - DMA request line multiplexer channel x control register 0x4 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C2CR C2CR DMAMux - DMA request line multiplexer channel x control register 0x8 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C3CR C3CR DMAMux - DMA request line multiplexer channel x control register 0xC 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C4CR C4CR DMAMux - DMA request line multiplexer channel x control register 0x10 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C5CR C5CR DMAMux - DMA request line multiplexer channel x control register 0x14 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C6CR C6CR DMAMux - DMA request line multiplexer channel x control register 0x18 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C7CR C7CR DMAMux - DMA request line multiplexer channel x control register 0x1C 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C8CR C8CR DMAMux - DMA request line multiplexer channel x control register 0x20 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 C9CR C9CR DMAMux - DMA request line multiplexer channel x control register 0x24 32 read-write n 0x0 0x0 DMAREQ_ID Input DMA request line selected 0 7 EGE Event generation enable/disable 9 1 NBREQ Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. 19 5 SE Synchronous operating mode enable/disable 16 1 SOIE Interrupt enable at synchronization event overrun 8 1 SPOL Synchronization event type selector Defines the synchronization event on the selected synchronization input: 17 2 SYNC_ID Synchronization input selected 24 5 CFR CFR DMAMUX request line multiplexer interrupt clear flag register 0x84 32 write-only n 0x0 0x0 CSOF Clear synchronization overrun event flag 0 16 CSR CSR DMAMUX request line multiplexer interrupt channel status register 0x80 32 read-only n 0x0 0x0 SOF Synchronization overrun event flag 0 16 RG0CR RG0CR DMAMux - DMA request generator channel x control register 0x100 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG1CR RG1CR DMAMux - DMA request generator channel x control register 0x104 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG2CR RG2CR DMAMux - DMA request generator channel x control register 0x108 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RG3CR RG3CR DMAMux - DMA request generator channel x control register 0x10C 32 read-write n 0x0 0x0 GE DMA request generator channel enable/disable 16 1 GNBREQ Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. 19 5 GPOL DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input 17 2 OIE Interrupt enable at trigger event overrun 8 1 SIG_ID DMA request trigger input selected 0 5 RGCFR RGCFR DMAMux - DMA request generator clear flag register 0x144 32 write-only n 0x0 0x0 COF Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. 0 4 RGSR RGSR DMAMux - DMA request generator status register 0x140 32 read-only n 0x0 0x0 OF Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. 0 4 EXTI External interrupt/event controller EXTI 0x0 0x0 0x400 registers n PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 USB_HP USB_HP 19 USB_LP USB_LP 20 fdcan1_intr1_it fdcan1_intr1_it 21 fdcan1_intr0_it fdcan1_intr0_it 22 EXTI9_5 EXTI9_5 23 EXTI15_10 EXTI15_10 40 USBWakeUP USBWakeUP 42 CRS CRS 75 EMR1 EMR1 Event mask register 0x4 32 read-write n 0x0 0x0 EM0 Event Mask on line 0 0 1 EM1 Event Mask on line 1 1 1 EM10 Event Mask on line 10 10 1 EM11 Event Mask on line 11 11 1 EM12 Event Mask on line 12 12 1 EM13 Event Mask on line 13 13 1 EM14 Event Mask on line 14 14 1 EM15 Event Mask on line 15 15 1 EM16 Event Mask on line 16 16 1 EM17 Event Mask on line 17 17 1 EM18 Event Mask on line 18 18 1 EM19 Event Mask on line 19 19 1 EM2 Event Mask on line 2 2 1 EM20 Event Mask on line 20 20 1 EM21 Event Mask on line 21 21 1 EM22 Event Mask on line 22 22 1 EM23 Event Mask on line 23 23 1 EM24 Event Mask on line 24 24 1 EM25 Event Mask on line 25 25 1 EM26 Event Mask on line 26 26 1 EM27 Event Mask on line 27 27 1 EM28 Event Mask on line 28 28 1 EM29 Event Mask on line 29 29 1 EM3 Event Mask on line 3 3 1 EM30 Event Mask on line 30 30 1 EM31 Event Mask on line 31 31 1 EM4 Event Mask on line 4 4 1 EM5 Event Mask on line 5 5 1 EM6 Event Mask on line 6 6 1 EM7 Event Mask on line 7 7 1 EM8 Event Mask on line 8 8 1 EM9 Event Mask on line 9 9 1 EMR2 EMR2 Event mask register 0x24 32 read-write n 0x0 0x0 EM32 Event mask on external/internal line 32 0 1 EM33 Event mask on external/internal line 33 1 1 EM34 Event mask on external/internal line 34 2 1 EM35 Event mask on external/internal line 35 3 1 EM36 Event mask on external/internal line 36 4 1 EM37 Event mask on external/internal line 37 5 1 EM38 Event mask on external/internal line 38 6 1 EM39 Event mask on external/internal line 39 7 1 EM40 Event mask on external/internal line 40 8 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 32 read-write n 0x0 0x0 FT0 Falling trigger event configuration of line 0 0 1 FT1 Falling trigger event configuration of line 1 1 1 FT10 Falling trigger event configuration of line 10 10 1 FT11 Falling trigger event configuration of line 11 11 1 FT12 Falling trigger event configuration of line 12 12 1 FT13 Falling trigger event configuration of line 13 13 1 FT14 Falling trigger event configuration of line 14 14 1 FT15 Falling trigger event configuration of line 15 15 1 FT16 Falling trigger event configuration of line 16 16 1 FT18 Falling trigger event configuration of line 18 18 1 FT19 Falling trigger event configuration of line 19 19 1 FT2 Falling trigger event configuration of line 2 2 1 FT20 Falling trigger event configuration of line 20 20 1 FT21 Falling trigger event configuration of line 21 21 1 FT22 Falling trigger event configuration of line 22 22 1 FT3 Falling trigger event configuration of line 3 3 1 FT4 Falling trigger event configuration of line 4 4 1 FT5 Falling trigger event configuration of line 5 5 1 FT6 Falling trigger event configuration of line 6 6 1 FT7 Falling trigger event configuration of line 7 7 1 FT8 Falling trigger event configuration of line 8 8 1 FT9 Falling trigger event configuration of line 9 9 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 32 read-write n 0x0 0x0 FT35 Falling trigger event configuration bit of line 35 3 1 FT36 Falling trigger event configuration bit of line 36 4 1 FT37 Falling trigger event configuration bit of line 37 5 1 FT38 Falling trigger event configuration bit of line 38 6 1 IMR1 IMR1 Interrupt mask register 0x0 32 read-write n 0x0 0x0 IM0 Interrupt Mask on line 0 0 1 IM1 Interrupt Mask on line 1 1 1 IM10 Interrupt Mask on line 10 10 1 IM11 Interrupt Mask on line 11 11 1 IM12 Interrupt Mask on line 12 12 1 IM13 Interrupt Mask on line 13 13 1 IM14 Interrupt Mask on line 14 14 1 IM15 Interrupt Mask on line 15 15 1 IM16 Interrupt Mask on line 16 16 1 IM17 Interrupt Mask on line 17 17 1 IM18 Interrupt Mask on line 18 18 1 IM19 Interrupt Mask on line 19 19 1 IM2 Interrupt Mask on line 2 2 1 IM20 Interrupt Mask on line 20 20 1 IM21 Interrupt Mask on line 21 21 1 IM22 Interrupt Mask on line 22 22 1 IM23 Interrupt Mask on line 23 23 1 IM24 Interrupt Mask on line 24 24 1 IM25 Interrupt Mask on line 25 25 1 IM26 Interrupt Mask on line 26 26 1 IM27 Interrupt Mask on line 27 27 1 IM28 Interrupt Mask on line 28 28 1 IM29 Interrupt Mask on line 29 29 1 IM3 Interrupt Mask on line 3 3 1 IM30 Interrupt Mask on line 30 30 1 IM31 Interrupt Mask on line 31 31 1 IM4 Interrupt Mask on line 4 4 1 IM5 Interrupt Mask on line 5 5 1 IM6 Interrupt Mask on line 6 6 1 IM7 Interrupt Mask on line 7 7 1 IM8 Interrupt Mask on line 8 8 1 IM9 Interrupt Mask on line 9 9 1 IMR2 IMR2 Interrupt mask register 0x20 32 read-write n 0x0 0x0 IM32 Interrupt Mask on external/internal line 32 0 1 IM33 Interrupt Mask on external/internal line 33 1 1 IM34 Interrupt Mask on external/internal line 34 2 1 IM35 Interrupt Mask on external/internal line 35 3 1 IM36 Interrupt Mask on external/internal line 36 4 1 IM37 Interrupt Mask on external/internal line 37 5 1 IM38 Interrupt Mask on external/internal line 38 6 1 IM39 Interrupt Mask on external/internal line 39 7 1 IM40 Interrupt Mask on external/internal line 40 8 1 IM41 Interrupt Mask on external/internal line 41 9 1 IM42 Interrupt Mask on external/internal line 42 10 1 IM43 Interrupt Mask on external/internal line 43 11 1 PR1 PR1 Pending register 0x14 32 read-write n 0x0 0x0 PIF0 Pending bit 0 0 1 PIF1 Pending bit 1 1 1 PIF10 Pending bit 10 10 1 PIF11 Pending bit 11 11 1 PIF12 Pending bit 12 12 1 PIF13 Pending bit 13 13 1 PIF14 Pending bit 14 14 1 PIF15 Pending bit 15 15 1 PIF16 Pending bit 16 16 1 PIF18 Pending bit 18 18 1 PIF19 Pending bit 19 19 1 PIF2 Pending bit 2 2 1 PIF20 Pending bit 20 20 1 PIF21 Pending bit 21 21 1 PIF22 Pending bit 22 22 1 PIF3 Pending bit 3 3 1 PIF4 Pending bit 4 4 1 PIF5 Pending bit 5 5 1 PIF6 Pending bit 6 6 1 PIF7 Pending bit 7 7 1 PIF8 Pending bit 8 8 1 PIF9 Pending bit 9 9 1 PR2 PR2 Pending register 0x34 32 read-write n 0x0 0x0 PIF35 Pending interrupt flag on line 35 3 1 PIF36 Pending interrupt flag on line 36 4 1 PIF37 Pending interrupt flag on line 37 5 1 PIF38 Pending interrupt flag on line 38 6 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 32 read-write n 0x0 0x0 RT RT 29 3 RT0 Rising trigger event configuration of line 0 0 1 RT1 Rising trigger event configuration of line 1 1 1 RT10 Rising trigger event configuration of line 10 10 1 RT11 Rising trigger event configuration of line 11 11 1 RT12 Rising trigger event configuration of line 12 12 1 RT13 Rising trigger event configuration of line 13 13 1 RT14 Rising trigger event configuration of line 14 14 1 RT15 Rising trigger event configuration of line 15 15 1 RT16 Rising trigger event configuration of line 16 16 1 RT18 Rising trigger event configuration of line 18 18 1 RT19 Rising trigger event configuration of line 19 19 1 RT2 Rising trigger event configuration of line 2 2 1 RT20 Rising trigger event configuration of line 20 20 1 RT21 Rising trigger event configuration of line 21 21 1 RT22 Rising trigger event configuration of line 22 22 1 RT3 Rising trigger event configuration of line 3 3 1 RT4 Rising trigger event configuration of line 4 4 1 RT5 Rising trigger event configuration of line 5 5 1 RT6 Rising trigger event configuration of line 6 6 1 RT7 Rising trigger event configuration of line 7 7 1 RT8 Rising trigger event configuration of line 8 8 1 RT9 Rising trigger event configuration of line 9 9 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 32 read-write n 0x0 0x0 RT32 Rising trigger event configuration bit of line 32 0 1 RT33 Rising trigger event configuration bit of line 32 1 1 RT38 Rising trigger event configuration bit of line 38 6 1 RT39 Rising trigger event configuration bit of line 39 7 1 RT40 Rising trigger event configuration bit of line 40 8 1 RT41 Rising trigger event configuration bit of line 41 9 1 SWIER1 SWIER1 Software interrupt event register 0x10 32 read-write n 0x0 0x0 SWI0 Software Interrupt on line 0 0 1 SWI1 Software Interrupt on line 1 1 1 SWI10 Software Interrupt on line 10 10 1 SWI11 Software Interrupt on line 11 11 1 SWI12 Software Interrupt on line 12 12 1 SWI13 Software Interrupt on line 13 13 1 SWI14 Software Interrupt on line 14 14 1 SWI15 Software Interrupt on line 15 15 1 SWI16 Software Interrupt on line 16 16 1 SWI18 Software Interrupt on line 18 18 1 SWI19 Software Interrupt on line 19 19 1 SWI2 Software Interrupt on line 2 2 1 SWI20 Software Interrupt on line 20 20 1 SWI21 Software Interrupt on line 21 21 1 SWI22 Software Interrupt on line 22 22 1 SWI3 Software Interrupt on line 3 3 1 SWI4 Software Interrupt on line 4 4 1 SWI5 Software Interrupt on line 5 5 1 SWI6 Software Interrupt on line 6 6 1 SWI7 Software Interrupt on line 7 7 1 SWI8 Software Interrupt on line 8 8 1 SWI9 Software Interrupt on line 9 9 1 SWIER2 SWIER2 Software interrupt event register 0x30 32 read-write n 0x0 0x0 SWI35 Software interrupt on line 35 3 1 SWI36 Software interrupt on line 36 4 1 SWI37 Software interrupt on line 37 5 1 SWI38 Software interrupt on line 38 6 1 FDCAN FDCAN FDCAN 0x0 0x0 0x400 registers n FDCAN2_intr0 FDCAN2_intr0 86 FDCAN2_intr1 FDCAN2_intr1 87 CCCR CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 BRSE BRSE 9 1 CCE CCE 1 1 CSA CSA 3 1 CSR CSR 4 1 DAR DAR 6 1 EFBI EFBI 13 1 FDOE FDOE 8 1 INIT INIT 0 1 MON MON 5 1 NISO NISO 15 1 PXHD PXHD 12 1 TEST TEST 7 1 TXP TXP 14 1 CKDIV CKDIV FDCAN CFG clock divider register 0x100 32 read-write n 0x0 0x0 PDIV input clock divider. the APB clock could be divided prior to be used by the CAN sub 0 4 CREL CREL FDCAN Core Release Register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 DBTP DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 read-write DSJW DSJW 0 4 read-write DTSEG1 DTSEG1 8 5 write-only DTSEG2 DTSEG2 4 4 read-write TDC TDC 23 1 read-only ECR ECR FDCAN Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CEL 16 8 RP RP 15 1 TEC TEC 0 8 TREC TREC 8 7 ENDN ENDN FDCAN Core Release Register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 HPMS HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x88 32 read-only n 0x0 0x0 BIDX BIDX 0 6 FIDX FIDX 8 7 FLST FLST 15 1 MSI MSI 6 2 IE IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 BECE BECE 20 1 BEUE BEUE 21 1 BOE BOE 25 1 DRX DRX 19 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 HPME HPME 8 1 MRAFE MRAFE 17 1 PEAE PEAE 27 1 PEDE PEDE 28 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 TCE TCE 9 1 TCFE TCFE 10 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TFEE TFEE 11 1 TOOE TOOE 18 1 TSWE TSWE 16 1 WDIE WDIE 26 1 ILE ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 EINT1 EINT1 1 1 ILS ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 BECL BECL 20 1 BEUL BEUL 21 1 BOL BOL 25 1 DRXL DRXL 19 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 HPML HPML 8 1 MRAFL MRAFL 17 1 PEAL PEAL 27 1 PEDL PEDL 28 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 TCFL TCFL 10 1 TCL TCL 9 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TFEL TFEL 11 1 TOOL TOOL 18 1 TSWL TSWL 16 1 WDIL WDIL 26 1 IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 BO BO 25 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 HPM HPM 8 1 MRAF MRAF 17 1 PEA PEA 27 1 PED PED 28 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF0N RF0N 0 1 RF0W RF0W 1 1 RF1F RF1F 6 1 RF1L RF1L 7 1 RF1N RF1N 4 1 RF1W RF1W 5 1 TC TC 9 1 TCF TCF 10 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TFE TFE 11 1 TOO TOO 18 1 TSW TSW 16 1 WDI WDI 26 1 NBTP NBTP FDCAN_NBTP 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 NSJW NSJW 25 7 NTSEG1 NTSEG1 8 8 TSEG2 TSEG2 0 7 PSR PSR FDCAN Protocol Status Register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 write-only BO BO 7 1 read-write DLEC DLEC 8 3 write-only EP EP 5 1 read-write EW EW 6 1 read-write LEC LEC 0 3 read-write PXE PXE 14 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write RESI RESI 11 1 read-write TDCV TDCV 16 7 read-write RWD RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 32 read-write n 0x0 0x0 F0AI F0AI 0 6 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 32 read-write n 0x0 0x0 F0F F0F 24 1 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 RF0L RF0L 25 1 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 32 read-write n 0x0 0x0 F1AI F1AI 0 6 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 32 read-only n 0x0 0x0 DMS DMS 30 2 F1F F1F 24 1 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 RF1L RF1L 25 1 RXGFC RXGFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 write-only ANFS ANFS 4 2 write-only RRFE RRFE 0 1 read-write RRFS RRFS 1 1 read-write TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 32 read-write n 0x0 0x0 TDCF TDCF 0 7 TDCO TDCO 8 7 TEST TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 RX RX 7 1 TX TX 5 2 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 read-write TOP TOP 16 16 read-write TOS TOS 1 2 write-only TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 32 read-only n 0x0 0x0 TOC TOC 0 16 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 TSS TSS 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 32 read-only n 0x0 0x0 TSC TSC 0 16 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 32 read-write n 0x0 0x0 AR AR 0 32 TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 32 read-only n 0x0 0x0 CF CF 0 32 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 CFIE CFIE 0 32 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 32 read-write n 0x0 0x0 CR CR 0 32 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 32 read-only n 0x0 0x0 TRP TRP 0 32 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 32 read-write n 0x0 0x0 TIE TIE 0 32 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 32 read-only n 0x0 0x0 TO TO 0 32 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 32 read-only n 0x0 0x0 EFF EFF 24 1 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 TEFL TEFL 25 1 TXFQS TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQF TFQF 21 1 TFQPI TFQPI 16 5 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 32 read-write n 0x0 0x0 EIDM EIDM 0 29 FDCAN1 FDCAN FDCAN 0x0 0x0 0x400 registers n FDCAN2_intr0 FDCAN2_intr0 86 FDCAN2_intr1 FDCAN2_intr1 87 CCCR CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 BRSE BRSE 9 1 CCE CCE 1 1 CSA CSA 3 1 CSR CSR 4 1 DAR DAR 6 1 EFBI EFBI 13 1 FDOE FDOE 8 1 INIT INIT 0 1 MON MON 5 1 NISO NISO 15 1 PXHD PXHD 12 1 TEST TEST 7 1 TXP TXP 14 1 CKDIV CKDIV FDCAN CFG clock divider register 0x100 32 read-write n 0x0 0x0 PDIV input clock divider. the APB clock could be divided prior to be used by the CAN sub 0 4 CREL CREL FDCAN Core Release Register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 DBTP DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 read-write DSJW DSJW 0 4 read-write DTSEG1 DTSEG1 8 5 write-only DTSEG2 DTSEG2 4 4 read-write TDC TDC 23 1 read-only ECR ECR FDCAN Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CEL 16 8 RP RP 15 1 TEC TEC 0 8 TREC TREC 8 7 ENDN ENDN FDCAN Core Release Register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 HPMS HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x88 32 read-only n 0x0 0x0 BIDX BIDX 0 6 FIDX FIDX 8 7 FLST FLST 15 1 MSI MSI 6 2 IE IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 BECE BECE 20 1 BEUE BEUE 21 1 BOE BOE 25 1 DRX DRX 19 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 HPME HPME 8 1 MRAFE MRAFE 17 1 PEAE PEAE 27 1 PEDE PEDE 28 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 TCE TCE 9 1 TCFE TCFE 10 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TFEE TFEE 11 1 TOOE TOOE 18 1 TSWE TSWE 16 1 WDIE WDIE 26 1 ILE ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 EINT1 EINT1 1 1 ILS ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 BECL BECL 20 1 BEUL BEUL 21 1 BOL BOL 25 1 DRXL DRXL 19 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 HPML HPML 8 1 MRAFL MRAFL 17 1 PEAL PEAL 27 1 PEDL PEDL 28 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 TCFL TCFL 10 1 TCL TCL 9 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TFEL TFEL 11 1 TOOL TOOL 18 1 TSWL TSWL 16 1 WDIL WDIL 26 1 IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 BO BO 25 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 HPM HPM 8 1 MRAF MRAF 17 1 PEA PEA 27 1 PED PED 28 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF0N RF0N 0 1 RF0W RF0W 1 1 RF1F RF1F 6 1 RF1L RF1L 7 1 RF1N RF1N 4 1 RF1W RF1W 5 1 TC TC 9 1 TCF TCF 10 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TFE TFE 11 1 TOO TOO 18 1 TSW TSW 16 1 WDI WDI 26 1 NBTP NBTP FDCAN_NBTP 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 NSJW NSJW 25 7 NTSEG1 NTSEG1 8 8 TSEG2 TSEG2 0 7 PSR PSR FDCAN Protocol Status Register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 write-only BO BO 7 1 read-write DLEC DLEC 8 3 write-only EP EP 5 1 read-write EW EW 6 1 read-write LEC LEC 0 3 read-write PXE PXE 14 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write RESI RESI 11 1 read-write TDCV TDCV 16 7 read-write RWD RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 32 read-write n 0x0 0x0 F0AI F0AI 0 6 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 32 read-write n 0x0 0x0 F0F F0F 24 1 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 RF0L RF0L 25 1 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 32 read-write n 0x0 0x0 F1AI F1AI 0 6 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 32 read-only n 0x0 0x0 DMS DMS 30 2 F1F F1F 24 1 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 RF1L RF1L 25 1 RXGFC RXGFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 write-only ANFS ANFS 4 2 write-only RRFE RRFE 0 1 read-write RRFS RRFS 1 1 read-write TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 32 read-write n 0x0 0x0 TDCF TDCF 0 7 TDCO TDCO 8 7 TEST TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 RX RX 7 1 TX TX 5 2 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 read-write TOP TOP 16 16 read-write TOS TOS 1 2 write-only TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 32 read-only n 0x0 0x0 TOC TOC 0 16 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 TSS TSS 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 32 read-only n 0x0 0x0 TSC TSC 0 16 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 32 read-write n 0x0 0x0 AR AR 0 32 TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 32 read-only n 0x0 0x0 CF CF 0 32 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 CFIE CFIE 0 32 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 32 read-write n 0x0 0x0 CR CR 0 32 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 32 read-only n 0x0 0x0 TRP TRP 0 32 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 32 read-write n 0x0 0x0 TIE TIE 0 32 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 32 read-only n 0x0 0x0 TO TO 0 32 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 32 read-only n 0x0 0x0 EFF EFF 24 1 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 TEFL TEFL 25 1 TXFQS TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQF TFQF 21 1 TFQPI TFQPI 16 5 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 32 read-write n 0x0 0x0 EIDM EIDM 0 29 FDCAN2 FDCAN FDCAN 0x0 0x0 0x400 registers n FDCAN2_intr0 FDCAN2_intr0 86 FDCAN2_intr1 FDCAN2_intr1 87 CCCR CCCR For details about setting and resetting of single bits see Software initialization. 0x18 32 read-write n 0x0 0x0 ASM ASM 2 1 BRSE BRSE 9 1 CCE CCE 1 1 CSA CSA 3 1 CSR CSR 4 1 DAR DAR 6 1 EFBI EFBI 13 1 FDOE FDOE 8 1 INIT INIT 0 1 MON MON 5 1 NISO NISO 15 1 PXHD PXHD 12 1 TEST TEST 7 1 TXP TXP 14 1 CKDIV CKDIV FDCAN CFG clock divider register 0x100 32 read-write n 0x0 0x0 PDIV input clock divider. the APB clock could be divided prior to be used by the CAN sub 0 4 CREL CREL FDCAN Core Release Register 0x0 32 read-only n 0x0 0x0 DAY DAY 0 8 MON MON 8 8 REL REL 28 4 STEP STEP 24 4 SUBSTEP SUBSTEP 20 4 YEAR YEAR 16 4 DBTP DBTP This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. 0xC 32 read-write n 0x0 0x0 DBRP DBRP 16 5 read-write DSJW DSJW 0 4 read-write DTSEG1 DTSEG1 8 5 write-only DTSEG2 DTSEG2 4 4 read-write TDC TDC 23 1 read-only ECR ECR FDCAN Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CEL 16 8 RP RP 15 1 TEC TEC 0 8 TREC TREC 8 7 ENDN ENDN FDCAN Core Release Register 0x4 32 read-only n 0x0 0x0 ETV ETV 0 32 HPMS HPMS This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. 0x88 32 read-only n 0x0 0x0 BIDX BIDX 0 6 FIDX FIDX 8 7 FLST FLST 15 1 MSI MSI 6 2 IE IE The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. 0x54 32 read-write n 0x0 0x0 ARAE ARAE 29 1 BECE BECE 20 1 BEUE BEUE 21 1 BOE BOE 25 1 DRX DRX 19 1 ELOE ELOE 22 1 EPE EPE 23 1 EWE EWE 24 1 HPME HPME 8 1 MRAFE MRAFE 17 1 PEAE PEAE 27 1 PEDE PEDE 28 1 RF0FE RF0FE 2 1 RF0LE RF0LE 3 1 RF0NE RF0NE 0 1 RF0WE RF0WE 1 1 RF1FE RF1FE 6 1 RF1LE RF1LE 7 1 RF1NE RF1NE 4 1 RF1WE RF1WE 5 1 TCE TCE 9 1 TCFE TCFE 10 1 TEFFE TEFFE 14 1 TEFLE TEFLE 15 1 TEFNE TEFNE 12 1 TEFWE TEFWE 13 1 TFEE TFEE 11 1 TOOE TOOE 18 1 TSWE TSWE 16 1 WDIE WDIE 26 1 ILE ILE Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. 0x5C 32 read-write n 0x0 0x0 EINT0 EINT0 0 1 EINT1 EINT1 1 1 ILS ILS The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. 0x58 32 read-write n 0x0 0x0 ARAL ARAL 29 1 BECL BECL 20 1 BEUL BEUL 21 1 BOL BOL 25 1 DRXL DRXL 19 1 ELOL ELOL 22 1 EPL EPL 23 1 EWL EWL 24 1 HPML HPML 8 1 MRAFL MRAFL 17 1 PEAL PEAL 27 1 PEDL PEDL 28 1 RF0FL RF0FL 2 1 RF0LL RF0LL 3 1 RF0NL RF0NL 0 1 RF0WL RF0WL 1 1 RF1FL RF1FL 6 1 RF1LL RF1LL 7 1 RF1NL RF1NL 4 1 RF1WL RF1WL 5 1 TCFL TCFL 10 1 TCL TCL 9 1 TEFFL TEFFL 14 1 TEFLL TEFLL 15 1 TEFNL TEFNL 12 1 TEFWL TEFWL 13 1 TFEL TFEL 11 1 TOOL TOOL 18 1 TSWL TSWL 16 1 WDIL WDIL 26 1 IR IR The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. 0x50 32 read-write n 0x0 0x0 ARA ARA 29 1 BO BO 25 1 DRX DRX 19 1 ELO ELO 22 1 EP EP 23 1 EW EW 24 1 HPM HPM 8 1 MRAF MRAF 17 1 PEA PEA 27 1 PED PED 28 1 RF0F RF0F 2 1 RF0L RF0L 3 1 RF0N RF0N 0 1 RF0W RF0W 1 1 RF1F RF1F 6 1 RF1L RF1L 7 1 RF1N RF1N 4 1 RF1W RF1W 5 1 TC TC 9 1 TCF TCF 10 1 TEFF TEFF 14 1 TEFL TEFL 15 1 TEFN TEFN 12 1 TEFW TEFW 13 1 TFE TFE 11 1 TOO TOO 18 1 TSW TSW 16 1 WDI WDI 26 1 NBTP NBTP FDCAN_NBTP 0x1C 32 read-write n 0x0 0x0 NBRP NBRP 16 9 NSJW NSJW 25 7 NTSEG1 NTSEG1 8 8 TSEG2 TSEG2 0 7 PSR PSR FDCAN Protocol Status Register 0x44 32 read-write n 0x0 0x0 ACT ACT 3 2 write-only BO BO 7 1 read-write DLEC DLEC 8 3 write-only EP EP 5 1 read-write EW EW 6 1 read-write LEC LEC 0 3 read-write PXE PXE 14 1 read-write RBRS RBRS 12 1 read-write REDL REDL 13 1 read-write RESI RESI 11 1 read-write TDCV TDCV 16 7 read-write RWD RWD The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. 0x14 32 read-write n 0x0 0x0 WDC WDC 0 8 read-write WDV WDV 8 8 read-only RXF0A RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 32 read-write n 0x0 0x0 F0AI F0AI 0 6 RXF0S RXF0S FDCAN Rx FIFO 0 Status Register 0x90 32 read-write n 0x0 0x0 F0F F0F 24 1 F0FL F0FL 0 7 F0GI F0GI 8 6 F0PI F0PI 16 6 RF0L RF0L 25 1 RXF1A RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 32 read-write n 0x0 0x0 F1AI F1AI 0 6 RXF1S RXF1S FDCAN Rx FIFO 1 Status Register 0x98 32 read-only n 0x0 0x0 DMS DMS 30 2 F1F F1F 24 1 F1FL F1FL 0 7 F1GI F1GI 8 6 F1PI F1PI 16 6 RF1L RF1L 25 1 RXGFC RXGFC Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. 0x80 32 read-write n 0x0 0x0 ANFE ANFE 2 2 write-only ANFS ANFS 4 2 write-only RRFE RRFE 0 1 read-write RRFS RRFS 1 1 read-write TDCR TDCR FDCAN Transmitter Delay Compensation Register 0x48 32 read-write n 0x0 0x0 TDCF TDCF 0 7 TDCO TDCO 8 7 TEST TEST Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. 0x10 32 read-write n 0x0 0x0 LBCK LBCK 4 1 RX RX 7 1 TX TX 5 2 TOCC TOCC FDCAN Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC ETOC 0 1 read-write TOP TOP 16 16 read-write TOS TOS 1 2 write-only TOCV TOCV FDCAN Timeout Counter Value Register 0x2C 32 read-only n 0x0 0x0 TOC TOC 0 16 TSCC TSCC FDCAN Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP TCP 16 4 TSS TSS 0 2 TSCV TSCV FDCAN Timestamp Counter Value Register 0x24 32 read-only n 0x0 0x0 TSC TSC 0 16 TXBAR TXBAR FDCAN Tx Buffer Add Request Register 0xCC 32 read-write n 0x0 0x0 AR AR 0 32 TXBC TXBC FDCAN Tx Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB NDTB 16 6 TBSA TBSA 2 14 TFQM TFQM 30 1 TFQS TFQS 24 6 TXBCF TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 32 read-only n 0x0 0x0 CF CF 0 32 TXBCIE TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 CFIE CFIE 0 32 TXBCR TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 32 read-write n 0x0 0x0 CR CR 0 32 TXBRP TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 32 read-only n 0x0 0x0 TRP TRP 0 32 TXBTIE TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 32 read-write n 0x0 0x0 TIE TIE 0 32 TXBTO TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 32 read-only n 0x0 0x0 TO TO 0 32 TXEFA TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 32 read-write n 0x0 0x0 EFAI EFAI 0 5 TXEFS TXEFS FDCAN Tx Event FIFO Status Register 0xE4 32 read-only n 0x0 0x0 EFF EFF 24 1 EFFL EFFL 0 6 EFGI EFGI 8 5 EFPI EFPI 16 5 TEFL TEFL 25 1 TXFQS TXFQS The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). 0xC4 32 read-only n 0x0 0x0 TFFL TFFL 0 6 TFGI TFGI 8 5 TFQF TFQF 21 1 TFQPI TFQPI 16 5 XIDAM XIDAM FDCAN Extended ID and Mask Register 0x84 32 read-write n 0x0 0x0 EIDM EIDM 0 29 FLASH Flash Flash 0x0 0x0 0x400 registers n FLASH FLASH 4 ACR ACR Access control register 0x0 32 read-write n 0x0 0x0 DBG_SWEN Debug software enable 18 1 DCEN Data cache enable 10 1 DCRST Data cache reset 12 1 ICEN Instruction cache enable 9 1 ICRST Instruction cache reset 11 1 LATENCY Latency 0 4 PRFTEN Prefetch enable 8 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 CR CR Flash control register 0x14 32 read-write n 0x0 0x0 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 FSTPG Fast programming 18 1 LOCK FLASH_CR Lock 31 1 MER1 Bank 1 Mass erase 2 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 OPTSTRT Options modification start 17 1 PER Page erase 1 1 PG Programming 0 1 PNB Page number 3 7 RDERRIE PCROP read error interrupt enable 26 1 SEC_PROT1 SEC_PROT1 28 1 STRT Start 16 1 ECCR ECCR Flash ECC register 0x18 32 read-write n 0x0 0x0 ADDR_ECC ECC fail address 0 19 read-only BK_ECC BK_ECC 21 1 read-only ECCC ECC correction 30 1 read-write ECCC2 ECC correction 28 1 read-write ECCD ECC detection 31 1 read-write ECCD2 ECC2 detection 29 1 read-write ECCIE ECCIE 24 1 read-write SYSF_ECC SYSF_ECC 22 1 read-only KEYR KEYR Flash key register 0x8 32 write-only n 0x0 0x0 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 32 write-only n 0x0 0x0 OPTKEYR Option byte key 0 32 OPTR OPTR Flash option register 0x20 32 read-write n 0x0 0x0 BOR_LEV BOR reset Level 8 3 IDWG_SW Independent watchdog selection 16 1 IRHEN IRHEN 30 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 nBOOT0 nBOOT0 27 1 nBOOT1 Boot configuration 23 1 NRST_MODE NRST_MODE 28 2 nRST_SHDW nRST_SHDW 14 1 nRST_STDBY nRST_STDBY 13 1 nRST_STOP nRST_STOP 12 1 nSWBOOT0 nSWBOOT0 26 1 RDP Read protection level 0 8 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 WWDG_SW Window watchdog selection 19 1 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 32 read-write n 0x0 0x0 PCROP1_END Bank 1 PCROP area end offset 0 15 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 32 read-write n 0x0 0x0 PCROP1_STRT Bank 1 PCROP area start offset 0 15 PDKEYR PDKEYR Power down key register 0x4 32 write-only n 0x0 0x0 PDKEYR RUN_PD in FLASH_ACR key 0 32 SEC1R SEC1R securable area bank1 register 0x70 32 read-write n 0x0 0x0 BOOT_LOCK BOOT_LOCK 16 1 SEC_SIZE1 SEC_SIZE1 0 8 SR SR Status register 0x10 32 read-write n 0x0 0x0 BSY Busy 16 1 read-only EOP End of operation 0 1 read-write FASTERR Fast programming error 9 1 read-write MISERR Fast programming data miss error 8 1 read-write OPERR Operation error 1 1 read-write OPTVERR Option validity error 15 1 read-write PGAERR Programming alignment error 5 1 read-write PGSERR Programming sequence error 7 1 read-write PROGERR Programming error 3 1 read-write RDERR PCROP read error 14 1 read-write SIZERR Size error 6 1 read-write WRPERR Write protected error 4 1 read-write WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 32 read-write n 0x0 0x0 WRP1A_END Bank 1 WRP first area A end offset 16 7 WRP1A_STRT Bank 1 WRP first area start offset 0 7 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 32 read-write n 0x0 0x0 WRP1B_END Bank 1 WRP second area B start offset 16 7 WRP1B_STRT Bank 1 WRP second area B end offset 0 7 FMAC Filter Math Accelerator FMAC 0x0 0x0 0xC00 registers n FMAC FMAC 101 CR CR FMAC Control register 0x10 32 read-write n 0x0 0x0 CLIPEN CLIPEN 15 1 DMAREN DMAREN 8 1 DMAWEN DMAWEN 9 1 OVFLIEN OVFLIEN 2 1 RESET RESET 16 1 RIEN RIEN 0 1 SATIEN SATIEN 4 1 UNFLIEN UNFLIEN 3 1 WIEN WIEN 1 1 PARAM PARAM FMAC Parameter register 0xC 32 read-write n 0x0 0x0 FUNC FUNC 24 7 P P 0 8 Q Q 8 8 R R 16 8 START START 31 1 RDATA RDATA FMAC Read Data register 0x1C 32 read-only n 0x0 0x0 RDATA RDATA 0 16 SR SR FMAC Status register 0x14 32 read-only n 0x0 0x0 OVFL OVFL 8 1 SAT SAT 10 1 UNFL UNFL 9 1 X1FULL X1FULL 1 1 YEMPTY YEMPTY 0 1 WDATA WDATA FMAC Write Data register 0x18 32 write-only n 0x0 0x0 WDATA WDATA 0 16 X1BUFCFG X1BUFCFG FMAC X1 Buffer Configuration register 0x0 32 read-write n 0x0 0x0 FULL_WM FULL_WM 24 2 X1_BASE X1_BASE 0 8 X1_BUF_SIZE X1_BUF_SIZE 8 8 X2BUFCFG X2BUFCFG FMAC X2 Buffer Configuration register 0x4 32 read-write n 0x0 0x0 X2_BASE X1_BASE 0 8 X2_BUF_SIZE X1_BUF_SIZE 8 8 YBUFCFG YBUFCFG FMAC Y Buffer Configuration register 0x8 32 read-write n 0x0 0x0 EMPTY_WM EMPTY_WM 24 2 Y_BASE X1_BASE 0 8 Y_BUF_SIZE X1_BUF_SIZE 8 8 FPU Floting point unit FPU 0x0 0x0 0xD registers n FPU Floating point interrupt 81 FPCAR FPCAR Floating-point context address register 0x4 32 read-write n 0x0 0x0 ADDRESS Location of unpopulated floating-point 3 29 FPCCR FPCCR Floating-point context control register 0x0 32 read-write n 0x0 0x0 ASPEN ASPEN 31 1 BFRDY BFRDY 6 1 HFRDY HFRDY 4 1 LSPACT LSPACT 0 1 LSPEN LSPEN 30 1 MMRDY MMRDY 5 1 MONRDY MONRDY 8 1 THREAD THREAD 3 1 USER USER 1 1 FPSCR FPSCR Floating-point status control register 0x8 32 read-write n 0x0 0x0 AHP Alternative half-precision control bit 26 1 C Carry condition code flag 29 1 DN Default NaN mode control bit 25 1 DZC Division by zero cumulative exception bit. 1 1 FZ Flush-to-zero mode control bit: 24 1 IDC Input denormal cumulative exception bit. 7 1 IOC Invalid operation cumulative exception bit 0 1 IXC Inexact cumulative exception bit 4 1 N Negative condition code flag 31 1 OFC Overflow cumulative exception bit 2 1 RMode Rounding Mode control field 22 2 UFC Underflow cumulative exception bit 3 1 V Overflow condition code flag 28 1 Z Zero condition code flag 30 1 FPU_CPACR Floating point unit CPACR FPU 0x0 0x0 0x5 registers n CPACR CPACR Coprocessor access control register 0x0 32 read-write n 0x0 0x0 CP CP 20 4 GPIOA General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOB General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOC General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOD General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOE General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOF General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 GPIOG General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFRH AFRH GPIO alternate function high register 0x24 32 read-write n 0x0 0x0 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRL AFRL GPIO alternate function low register 0x20 32 read-write n 0x0 0x0 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 BRR BRR GPIO port bit reset register 0x28 32 write-only n 0x0 0x0 BR0 Port Reset bit 0 1 BR1 Port Reset bit 1 1 BR10 Port Reset bit 10 1 BR11 Port Reset bit 11 1 BR12 Port Reset bit 12 1 BR13 Port Reset bit 13 1 BR14 Port Reset bit 14 1 BR15 Port Reset bit 15 1 BR2 Port Reset bit 2 1 BR3 Port Reset bit 3 1 BR4 Port Reset bit 4 1 BR5 Port Reset bit 5 1 BR6 Port Reset bit 6 1 BR7 Port Reset bit 7 1 BR8 Port Reset bit 8 1 BR9 Port Reset bit 9 1 BSRR BSRR GPIO port bit set/reset register 0x18 32 write-only n 0x0 0x0 BR0 Port x set bit y (y= 0..15) 16 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR15 Port x reset bit y (y = 0..15) 31 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR9 Port x reset bit y (y = 0..15) 25 1 BS0 Port x set bit y (y= 0..15) 0 1 BS1 Port x set bit y (y= 0..15) 1 1 BS10 Port x set bit y (y= 0..15) 10 1 BS11 Port x set bit y (y= 0..15) 11 1 BS12 Port x set bit y (y= 0..15) 12 1 BS13 Port x set bit y (y= 0..15) 13 1 BS14 Port x set bit y (y= 0..15) 14 1 BS15 Port x set bit y (y= 0..15) 15 1 BS2 Port x set bit y (y= 0..15) 2 1 BS3 Port x set bit y (y= 0..15) 3 1 BS4 Port x set bit y (y= 0..15) 4 1 BS5 Port x set bit y (y= 0..15) 5 1 BS6 Port x set bit y (y= 0..15) 6 1 BS7 Port x set bit y (y= 0..15) 7 1 BS8 Port x set bit y (y= 0..15) 8 1 BS9 Port x set bit y (y= 0..15) 9 1 IDR IDR GPIO port input data register 0x10 32 read-only n 0x0 0x0 IDR0 Port input data (y = 0..15) 0 1 IDR1 Port input data (y = 0..15) 1 1 IDR10 Port input data (y = 0..15) 10 1 IDR11 Port input data (y = 0..15) 11 1 IDR12 Port input data (y = 0..15) 12 1 IDR13 Port input data (y = 0..15) 13 1 IDR14 Port input data (y = 0..15) 14 1 IDR15 Port input data (y = 0..15) 15 1 IDR2 Port input data (y = 0..15) 2 1 IDR3 Port input data (y = 0..15) 3 1 IDR4 Port input data (y = 0..15) 4 1 IDR5 Port input data (y = 0..15) 5 1 IDR6 Port input data (y = 0..15) 6 1 IDR7 Port input data (y = 0..15) 7 1 IDR8 Port input data (y = 0..15) 8 1 IDR9 Port input data (y = 0..15) 9 1 LCKR LCKR GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCKK Port x lock bit y (y= 0..15) 16 1 MODER MODER GPIO port mode register 0x0 32 read-write n 0x0 0x0 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER9 Port x configuration bits (y = 0..15) 18 2 ODR ODR GPIO port output data register 0x14 32 read-write n 0x0 0x0 ODR0 Port output data (y = 0..15) 0 1 ODR1 Port output data (y = 0..15) 1 1 ODR10 Port output data (y = 0..15) 10 1 ODR11 Port output data (y = 0..15) 11 1 ODR12 Port output data (y = 0..15) 12 1 ODR13 Port output data (y = 0..15) 13 1 ODR14 Port output data (y = 0..15) 14 1 ODR15 Port output data (y = 0..15) 15 1 ODR2 Port output data (y = 0..15) 2 1 ODR3 Port output data (y = 0..15) 3 1 ODR4 Port output data (y = 0..15) 4 1 ODR5 Port output data (y = 0..15) 5 1 ODR6 Port output data (y = 0..15) 6 1 ODR7 Port output data (y = 0..15) 7 1 ODR8 Port output data (y = 0..15) 8 1 ODR9 Port output data (y = 0..15) 9 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OTYPER OTYPER GPIO port output type register 0x4 32 read-write n 0x0 0x0 OT0 Port x configuration bits (y = 0..15) 0 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT15 Port x configuration bits (y = 0..15) 15 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT9 Port x configuration bits (y = 0..15) 9 1 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 I2C1 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C1_EV I2C1_EV 31 I2C1_ER I2C1_ER 32 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C2 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n WWDG Window Watchdog interrupt 0 I2C2_EV I2C2_EV 33 I2C2_ER I2C2_ER 34 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C3 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C3_EV I2C3_EV 92 I2C3_ER I2C3_ER 93 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 I2C4 Inter-integrated circuit I2C 0x0 0x0 0x400 registers n I2C4_EV I2C4_EV 82 I2C4_ER I2C4_ER 83 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 ADDRIE Address match interrupt enable (slave only) 3 1 ALERTEN SMBUS alert enable 22 1 ANFOFF Analog noise filter OFF 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupts enable 7 1 GCEN General call enable 19 1 NACKIE Not acknowledge received interrupt enable 4 1 NOSTRETCH Clock stretching disable 17 1 PE Peripheral enable 0 1 PECEN PEC enable 23 1 RXDMAEN DMA reception requests enable 15 1 RXIE RX Interrupt enable 2 1 SBC Slave byte control 16 1 SMBDEN SMBus Device Default address enable 21 1 SMBHEN SMBus Host address enable 20 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 TXDMAEN DMA transmission requests enable 14 1 TXIE TX Interrupt enable 1 1 WUPEN Wakeup from STOP enable 18 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD10 10-bit addressing mode (master mode) 11 1 AUTOEND Automatic end mode (master mode) 25 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 NACK NACK generation (slave mode) 15 1 NBYTES Number of bytes 16 8 PECBYTE Packet error checking byte 26 1 RD_WRN Transfer direction (master mode) 10 1 RELOAD NBYTES reload mode 24 1 SADD Slave address bit (master mode) 0 10 START Start generation 13 1 STOP Stop generation (master mode) 14 1 ICR ICR Interrupt clear register 0x1C 32 write-only n 0x0 0x0 ADDRCF Address Matched flag clear 3 1 ALERTCF Alert flag clear 13 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 NACKCF Not Acknowledge flag clear 4 1 OVRCF Overrun/Underrun flag clear 10 1 PECCF PEC Error flag clear 11 1 STOPCF Stop detection flag clear 5 1 TIMOUTCF Timeout detection flag clear 12 1 ISR ISR Interrupt and Status register 0x18 32 read-write n 0x0 0x0 ADDCODE Address match code (Slave mode) 17 7 read-only ADDR Address matched (slave mode) 3 1 read-only ALERT SMBus alert 13 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only BUSY Bus busy 15 1 read-only DIR Transfer direction (Slave mode) 16 1 read-only NACKF Not acknowledge received flag 4 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only PECERR PEC Error in reception 11 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only STOPF Stop detection flag 5 1 read-only TC Transfer Complete (master mode) 6 1 read-only TCR Transfer Complete Reload 7 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only TXE Transmit data register empty (transmitters) 0 1 read-write TXIS Transmit interrupt status (transmitters) 1 1 read-write OAR1 OAR1 Own address register 1 0x8 32 read-write n 0x0 0x0 OA1 Interface address 0 10 OA1EN Own Address 1 enable 15 1 OA1MODE Own Address 1 10-bit mode 10 1 OAR2 OAR2 Own address register 2 0xC 32 read-write n 0x0 0x0 OA2 Interface address 1 7 OA2EN Own Address 2 enable 15 1 OA2MSK Own Address 2 masks 8 3 PECR PECR PEC register 0x20 32 read-only n 0x0 0x0 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 32 read-only n 0x0 0x0 RXDATA 8-bit receive data 0 8 TIMEOUTR TIMEOUTR Status register 1 0x14 32 read-write n 0x0 0x0 TEXTEN Extended clock timeout enable 31 1 TIDLE Idle clock timeout detection 12 1 TIMEOUTA Bus timeout A 0 12 TIMEOUTB Bus timeout B 16 12 TIMOUTEN Clock timeout enable 15 1 TIMINGR TIMINGR Timing register 0x10 32 read-write n 0x0 0x0 PRESC Timing prescaler 28 4 SCLDEL Data setup time 20 4 SCLH SCL high period (master mode) 8 8 SCLL SCL low period (master mode) 0 8 SDADEL Data hold time 16 4 TXDR TXDR Transmit data register 0x28 32 read-write n 0x0 0x0 TXDATA 8-bit transmit data 0 8 IWDG WinWATCHDOG WWDG 0x0 0x0 0x400 registers n CFR CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 WDGTB Timer base 11 3 CR CR Control register 0x0 32 read-write n 0x0 0x0 T 7-bit counter (MSB to LSB) 0 7 WDGA Activation bit 7 1 KR KR Key register 0x0 32 write-only n 0x0 0x0 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 32 read-write n 0x0 0x0 RL Watchdog counter reload value 0 12 SR SR Status register 0x8 32 read-write n 0x0 0x0 EWIF Early wakeup interrupt flag 0 1 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 WINR WINR Window register 0x10 32 read-write n 0x0 0x0 WIN Watchdog counter window value 0 12 LPTIMER1 Low power timer LPTIM 0x0 0x0 0x400 registers n ARR ARR Autoreload Register 0x18 32 read-write n 0x0 0x0 ARR Auto reload value 0 16 CFGR CFGR Configuration Register 0xC 32 read-write n 0x0 0x0 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 COUNTMODE counter mode enabled 23 1 ENC Encoder mode enable 24 1 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 TIMOUT Timeout enable 19 1 TRGFLT Configurable digital filter for trigger 6 2 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 4 WAVE Waveform shape 20 1 WAVPOL Waveform shape polarity 21 1 CMP CMP Compare Register 0x14 32 read-write n 0x0 0x0 CMP Compare value 0 16 CNT CNT Counter Register 0x1C 32 read-only n 0x0 0x0 CNT Counter value 0 16 CR CR Control Register 0x10 32 read-write n 0x0 0x0 CNTSTRT Timer start in continuous mode 2 1 COUNTRST COUNTRST 3 1 ENABLE LPTIM Enable 0 1 RSTARE RSTARE 4 1 SNGSTRT LPTIM start in single mode 1 1 ICR ICR Interrupt Clear Register 0x4 32 write-only n 0x0 0x0 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPMCF compare match Clear Flag 0 1 CMPOKCF Compare register update OK Clear Flag 3 1 DOWNCF Direction change to down Clear Flag 6 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 UPCF Direction change to UP Clear Flag 5 1 IER IER Interrupt Enable Register 0x8 32 read-write n 0x0 0x0 ARRMIE Autoreload match Interrupt Enable 1 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPMIE Compare match Interrupt Enable 0 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 DOWNIE Direction change to down Interrupt Enable 6 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 UPIE Direction change to UP Interrupt Enable 5 1 ISR ISR Interrupt and Status Register 0x0 32 read-only n 0x0 0x0 ARRM Autoreload match 1 1 ARROK Autoreload register update OK 4 1 CMPM Compare match 0 1 CMPOK Compare register update OK 3 1 DOWN Counter direction change up to down 6 1 EXTTRIG External trigger edge event 2 1 UP Counter direction change down to up 5 1 OR OR option register 0x20 32 read-write n 0x0 0x0 IN1 IN1 0 1 IN1_2_1 IN1_2_1 2 2 IN2 IN2 1 1 IN2_2_1 IN2_2_1 4 2 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n LPTIM1 LPTIM1 49 LPUART LPUART 91 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 BRR BRR 0 20 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 Word length 28 1 MME Mute mode enable 13 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 MSBFIRST Most significant bit first 19 1 RXINV RX pin active level inversion 16 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 TCCF Transmission complete clear flag 6 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 FE FE 1 1 IDLE IDLE 4 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 WUF WUF 20 1 PRESC PRESC Prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ TXFRQ 4 1 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 MPU Memory protection unit MPU 0x0 0x0 0x15 registers n CTRL CTRL MPU control register 0x4 32 read-only n 0x0 0x0 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RASR RASR MPU region attribute and size register 0x10 32 read-write n 0x0 0x0 AP Access permission 24 3 B memory attribute 16 1 C memory attribute 17 1 ENABLE Region enable bit. 0 1 S Shareable memory attribute 18 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 TEX memory attribute 19 3 XN Instruction access disable bit 28 1 RBAR RBAR MPU region base address register 0xC 32 read-write n 0x0 0x0 ADDR Region base address field 5 27 REGION MPU region field 0 4 VALID MPU region number valid 4 1 RNR RNR MPU region number register 0x8 32 read-write n 0x0 0x0 REGION MPU region 0 8 TYPER TYPER MPU type register 0x0 32 read-only n 0x0 0x0 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 SEPARATE Separate flag 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0x400 registers n 0x0 0xE04 registers n IABR0 IABR0 Interrupt Active Bit Register 0x200 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 IABR3 IABR3 Interrupt Active Bit Register 0x20C 32 read-only n 0x0 0x0 ACTIVE ACTIVE 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICER3 ICER3 Interrupt Clear-Enable Register 0x8C 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 ICPR3 ICPR3 Interrupt Clear-Pending Register 0x18C 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR21 IPR21 Interrupt Priority Register 0x354 32 read-write n 0x0 0x0 IPR22 IPR22 Interrupt Priority Register 0x358 32 read-write n 0x0 0x0 IPR23 IPR23 Interrupt Priority Register 0x35C 32 read-write n 0x0 0x0 IPR24 IPR24 Interrupt Priority Register 0x360 32 read-write n 0x0 0x0 IPR25 IPR25 Interrupt Priority Register 0x364 32 read-write n 0x0 0x0 IPR3 IPR3 Interrupt Priority Register 0x30C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 32 read-write n 0x0 0x0 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 ISER0 ISER0 Interrupt Set-Enable Register 0x0 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISER3 ISER3 Interrupt Set-Enable Register 0xC 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 ISPR3 ISPR3 Interrupt Set-Pending Register 0x10C 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 STIR STIR Software trigger interrupt register 0xE00 32 read-write n 0x0 0x0 INTID Software generated interrupt ID 0 9 NVIC_STIR Nested vectored interrupt controller NVIC 0x0 0x0 0x5 registers n STIR STIR Software trigger interrupt register 0x0 32 read-write n 0x0 0x0 INTID Software generated interrupt ID 0 9 OPAMP Operational amplifiers OPAMP 0x0 0x0 0x100 registers n OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 32 read-write n 0x0 0x0 CALON CALON 11 1 CALOUT CALOUT 30 1 CALSEL CALSEL 12 2 FORCE_VP FORCE_VP 1 1 LOCK LOCK 31 1 OPAEN Operational amplifier Enable 0 1 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETN TRIMOFFSETN 24 5 TRIMOFFSETP TRIMOFFSETP 19 5 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 VP_SEL VP_SEL 2 2 OPAMP1_TCMR OPAMP1_TCMR OPAMP1 control/status register 0x18 32 read-write n 0x0 0x0 LOCK LOCK 31 1 T1CM_EN T1CM_EN 3 1 T20CM_EN T20CM_EN 5 1 T8CM_EN T8CM_EN 4 1 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x4 32 read-write n 0x0 0x0 CALON CALON 11 1 CALOUT CALOUT 30 1 CALSEL CALSEL 12 2 FORCE_VP FORCE_VP 1 1 LOCK LOCK 31 1 OPAEN Operational amplifier Enable 0 1 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETN TRIMOFFSETN 24 5 TRIMOFFSETP TRIMOFFSETP 19 5 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 VP_SEL VP_SEL 2 2 OPAMP2_TCMR OPAMP2_TCMR OPAMP2 control/status register 0x1C 32 read-write n 0x0 0x0 LOCK LOCK 31 1 T1CM_EN T1CM_EN 3 1 T20CM_EN T20CM_EN 5 1 T8CM_EN T8CM_EN 4 1 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 OPAMP3_CSR OPAMP3_CSR OPAMP3 control/status register 0x8 32 read-write n 0x0 0x0 CALON CALON 11 1 CALOUT CALOUT 30 1 CALSEL CALSEL 12 2 FORCE_VP FORCE_VP 1 1 LOCK LOCK 31 1 OPAEN Operational amplifier Enable 0 1 OPAHSM OPAHSM 7 1 OPAINTOEN OPAINTOEN 8 1 PGA_GAIN PGA_GAIN 14 5 TRIMOFFSETN TRIMOFFSETN 24 5 TRIMOFFSETP TRIMOFFSETP 19 5 USERTRIM USERTRIM 4 1 VM_SEL VM_SEL 5 2 VP_SEL VP_SEL 2 2 OPAMP3_TCMR OPAMP3_TCMR OPAMP3 control/status register 0x20 32 read-write n 0x0 0x0 LOCK LOCK 31 1 T1CM_EN T1CM_EN 3 1 T20CM_EN T20CM_EN 5 1 T8CM_EN T8CM_EN 4 1 VMS_SEL VMS_SEL 0 1 VPS_SEL VPS_SEL 1 2 PWR Power control PWR 0x0 0x0 0x400 registers n CR1 CR1 Power control register 1 0x0 32 read-write n 0x0 0x0 DBP Disable backup domain write protection 8 1 LPMS Low-power mode selection 0 3 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 CR2 CR2 Power control register 2 0x4 32 read-write n 0x0 0x0 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 PVMEN1 Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage 4 1 PVMEN2 Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage 5 1 PVMEN3 Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V 6 1 PVMEN4 Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage 7 1 CR3 CR3 Power control register 3 0x8 32 read-write n 0x0 0x0 APC Apply pull-up and pull-down configuration 10 1 EIWUL Enable external WakeUp line 15 1 EWUP1 Enable Wakeup pin WKUP1 0 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP5 Enable Wakeup pin WKUP5 4 1 RRS SRAM2 retention in Standby mode 8 1 UCPD1_DBDIS DBDIS 14 1 UCPD1_STDBY STDBY 13 1 CR4 CR4 Power control register 4 0xC 32 read-write n 0x0 0x0 VBE VBAT battery charging enable 8 1 VBRS VBAT battery charging resistor selection 9 1 WP1 Wakeup pin WKUP1 polarity 0 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP5 Wakeup pin WKUP5 polarity 4 1 CR5 CR5 Power control register 5 0x80 32 read-write n 0x0 0x0 R1MODE Main regular range 1 mode 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 32 read-write n 0x0 0x0 PD0 Port A pull-down bit y (y=0..15) 0 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 32 read-write n 0x0 0x0 PD0 Port B pull-down bit y (y=0..15) 0 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD15 Port B pull-down bit y (y=0..15) 15 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PDCRC PDCRC Power Port C pull-down control register 0x34 32 read-write n 0x0 0x0 PD0 Port C pull-down bit y (y=0..15) 0 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD15 Port C pull-down bit y (y=0..15) 15 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 32 read-write n 0x0 0x0 PD0 Port D pull-down bit y (y=0..15) 0 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD15 Port D pull-down bit y (y=0..15) 15 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PDCRE PDCRE Power Port E pull-down control register 0x44 32 read-write n 0x0 0x0 PD0 Port E pull-down bit y (y=0..15) 0 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD15 Port E pull-down bit y (y=0..15) 15 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 32 read-write n 0x0 0x0 PD0 Port F pull-down bit y (y=0..15) 0 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD13 Port F pull-down bit y (y=0..15) 13 1 PD14 Port F pull-down bit y (y=0..15) 14 1 PD15 Port F pull-down bit y (y=0..15) 15 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PDCRG PDCRG Power Port G pull-down control register 0x54 32 read-write n 0x0 0x0 PD0 Port G pull-down bit y (y=0..15) 0 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PUCRA PUCRA Power Port A pull-up control register 0x20 32 read-write n 0x0 0x0 PU0 Port A pull-up bit y (y=0..15) 0 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU15 Port A pull-up bit y (y=0..15) 15 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PUCRB PUCRB Power Port B pull-up control register 0x28 32 read-write n 0x0 0x0 PU0 Port B pull-up bit y (y=0..15) 0 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU15 Port B pull-up bit y (y=0..15) 15 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PUCRC PUCRC Power Port C pull-up control register 0x30 32 read-write n 0x0 0x0 PU0 Port C pull-up bit y (y=0..15) 0 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU15 Port C pull-up bit y (y=0..15) 15 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PUCRD PUCRD Power Port D pull-up control register 0x38 32 read-write n 0x0 0x0 PU0 Port D pull-up bit y (y=0..15) 0 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU15 Port D pull-up bit y (y=0..15) 15 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PUCRE PUCRE Power Port E pull-up control register 0x40 32 read-write n 0x0 0x0 PU0 Port E pull-up bit y (y=0..15) 0 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU15 Port E pull-up bit y (y=0..15) 15 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PUCRF PUCRF Power Port F pull-up control register 0x48 32 read-write n 0x0 0x0 PU0 Port F pull-up bit y (y=0..15) 0 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU13 Port F pull-up bit y (y=0..15) 13 1 PU14 Port F pull-up bit y (y=0..15) 14 1 PU15 Port F pull-up bit y (y=0..15) 15 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PUCRG PUCRG Power Port G pull-up control register 0x50 32 read-write n 0x0 0x0 PU0 Port G pull-up bit y (y=0..15) 0 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU9 Port G pull-up bit y (y=0..15) 9 1 SCR SCR Power status clear register 0x18 32 write-only n 0x0 0x0 CSBF Clear standby flag 8 1 CWUF1 Clear wakeup flag 1 0 1 CWUF2 Clear wakeup flag 2 1 1 CWUF3 Clear wakeup flag 3 2 1 CWUF4 Clear wakeup flag 4 3 1 CWUF5 Clear wakeup flag 5 4 1 SR1 SR1 Power status register 1 0x10 32 read-only n 0x0 0x0 SBF Standby flag 8 1 WUF1 Wakeup flag 1 0 1 WUF2 Wakeup flag 2 1 1 WUF3 Wakeup flag 3 2 1 WUF4 Wakeup flag 4 3 1 WUF5 Wakeup flag 5 4 1 WUFI Wakeup flag internal 15 1 SR2 SR2 Power status register 2 0x14 32 read-only n 0x0 0x0 PVDO Power voltage detector output 11 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 13 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V 15 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 VOSF Voltage scaling flag 10 1 RCC Reset and clock control RCC 0x0 0x0 0x400 registers n RCC RCC 5 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 32 read-write n 0x0 0x0 CORDICEN CORDIC clock enable 3 1 CRCEN CRC clock enable 12 1 DMA1EN DMA1 clock enable 0 1 DMA2EN DMA2 clock enable 1 1 DMAMUXEN DMAMUX clock enable 2 1 FLITFEN FLITF clock enable 8 1 FMACEN FMAC clock enable 4 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 32 read-write n 0x0 0x0 CORDICRST CORDIC reset 3 1 CRCRST CRC reset 12 1 DMA1RST DMA1 reset 0 1 DMA2RST DMA2 reset 1 1 DMAMUX1RST DMAMUXRST 2 1 FLITFRST_ FLITF reset 8 1 MATRIXRST MATRIX reset 4 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 32 read-write n 0x0 0x0 CORDICSMEN CORDIC clock enable during sleep mode 3 1 CRCSMEN CRCSMEN 12 1 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMAMUX1SMEN DMAMUX clock enable during Sleep and Stop modes 2 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 FMACSMEN FMACSM clock enable 4 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 32 read-write n 0x0 0x0 ADC12EN ADC clock enable 13 1 ADC345EN DCMI clock enable 14 1 CRYPTEN Cryptography clock enable 24 1 DAC1 AES accelerator clock enable 16 1 DAC2 HASH clock enable 17 1 DAC3 Random Number Generator clock enable 18 1 DAC4 DAC4 clock enable 19 1 GPIOAEN IO port A clock enable 0 1 GPIOBEN IO port B clock enable 1 1 GPIOCEN IO port C clock enable 2 1 GPIODEN IO port D clock enable 3 1 GPIOEEN IO port E clock enable 4 1 GPIOFEN IO port F clock enable 5 1 GPIOGEN IO port G clock enable 6 1 RNGEN Random Number Generator clock enable 26 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 32 read-write n 0x0 0x0 ADC12RST ADC reset 13 1 ADC345RST_ SAR ADC345 interface reset 14 1 CRYPTRST Cryptography module reset 24 1 DAC1RST_ DAC1 interface reset 16 1 DAC2RST DAC2 interface reset 17 1 DAC3RST DAC3 interface reset 18 1 DAC4RST DAC4 interface reset 19 1 GPIOARST IO port A reset 0 1 GPIOBRST IO port B reset 1 1 GPIOCRST IO port C reset 2 1 GPIODRST IO port D reset 3 1 GPIOERST IO port E reset 4 1 GPIOFRST IO port F reset 5 1 GPIOGRST IO port G reset 6 1 RNGRST Random Number Generator module reset 26 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 32 read-write n 0x0 0x0 AD12CSMEN ADC clocks enable during Sleep and Stop modes 13 1 ADC345SMEN DCMI clock enable during Sleep and Stop modes 14 1 CRYPTSMEN Cryptography clock enable during sleep mode 24 1 DAC1SMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 DAC2SMEN HASH clock enable during Sleep and Stop modes 17 1 DAC3SMEN DAC3 clock enable during sleep mode 18 1 DAC4SMEN DAC4 clock enable during sleep mode 19 1 GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIOFSMEN IO port F clocks enable during Sleep and Stop modes 5 1 GPIOGSMEN IO port G clocks enable during Sleep and Stop modes 6 1 RNGSMEN Random Number Generator clock enable during sleep mode 26 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 SRAM3SMEN SRAM2 interface clocks enable during Sleep and Stop modes 10 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 32 read-write n 0x0 0x0 FMCEN Flexible memory controller clock enable 0 1 QUADSPI1EN Quad SPI 1 module clock enable 8 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 32 read-write n 0x0 0x0 FMCRST Flexible memory controller reset 0 1 QUADSPI1RST Quad SPI 1 module reset 8 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 32 read-write n 0x0 0x0 FMCSMEN Flexible memory controller clocks enable during Sleep and Stop modes 0 1 QUADSPI1SMEN QUAD SPI 1 module clock enable during sleep mode 8 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 32 read-write n 0x0 0x0 CRSEN CRSclock enable 8 1 FDCANEN FDCAN clock enable 25 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3 OPAMP interface clock enable 30 1 LPTIM1EN Low power timer 1 clock enable 31 1 PWREN Power interface clock enable 28 1 RTCAPBEN RTC APB clock enable 10 1 SP3EN SPI3 clock enable 15 1 SPI2EN SPI2 clock enable 14 1 TIM2EN TIM2 timer clock enable 0 1 TIM3EN TIM3 timer clock enable 1 1 TIM4EN TIM4 timer clock enable 2 1 TIM5EN TIM5 timer clock enable 3 1 TIM6EN TIM6 timer clock enable 4 1 TIM7EN TIM7 timer clock enable 5 1 UART4EN UART4 clock enable 19 1 UART5EN UART5 clock enable 20 1 USART2EN USART2 clock enable 17 1 USART3EN USART3 clock enable 18 1 USBDEN USBDclock enable 23 1 WWDGEN Window watchdog clock enable 11 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 32 read-write n 0x0 0x0 I2C4EN I2C4 clock enable 1 1 LPUART1EN Low power UART 1 clock enable 0 1 USBPDEN USBPD clock enable 8 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 32 read-write n 0x0 0x0 CRSRST Clock recovery system reset 8 1 FDCANRST FDCAN reset 25 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 I2C3 I2C3 interface reset 30 1 LPTIM1RST Low Power Timer 1 reset 31 1 PWRRST Power interface reset 28 1 SPI2RST SPI2 reset 14 1 SPI3RST SPI3 reset 15 1 TIM2RST TIM2 timer reset 0 1 TIM3RST TIM3 timer reset 1 1 TIM4RST TIM3 timer reset 2 1 TIM5RST TIM5 timer reset 3 1 TIM6RST TIM6 timer reset 4 1 TIM7RST TIM7 timer reset 5 1 UART4RST UART4 reset 19 1 UART5RST UART5 reset 20 1 USART2RST USART2 reset 17 1 USART3RST USART3 reset 18 1 USBDRST USBD reset 23 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 32 read-write n 0x0 0x0 I2C4RST I2C4 reset 1 1 LPUART1RST Low-power UART 1 reset 0 1 USBPDRST USBPD reset 8 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 32 read-write n 0x0 0x0 CRSSMEN CRS clock enable during sleep mode 8 1 FDCANSMEN FDCAN clock enable during sleep mode 25 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 I2C3SMEN_3 I2C 3 interface clock enable during sleep mode 30 1 LPTIM1SMEN Low Power Timer1 clock enable during sleep mode 31 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 TIM3SMEN TIM3 timer clocks enable during Sleep and Stop modes 1 1 TIM4SMEN TIM4 timer clocks enable during Sleep and Stop modes 2 1 TIM5SMEN TIM5 timer clocks enable during Sleep and Stop modes 3 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 UART4SMEN UART4 clocks enable during Sleep and Stop modes 19 1 UART5SMEN UART5 clocks enable during Sleep and Stop modes 20 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 17 1 USART3SMEN USART3 clocks enable during Sleep and Stop modes 18 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 32 read-write n 0x0 0x0 I2C4SMEN I2C4 clocks enable during Sleep and Stop modes 1 1 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 USBPDSMEN USB PD clock enable during sleep mode 8 1 APB2ENR APB2ENR APB2ENR 0x60 32 read-write n 0x0 0x0 HRTIMEREN HRTIMER clock enable 26 1 SAI1EN SAI1 clock enable 21 1 SPI1EN SPI1 clock enable 12 1 SPI4EN SPI 4 clock enable 15 1 SYSCFGEN SYSCFG clock enable 0 1 TIM15EN TIM15 timer clock enable 16 1 TIM16EN TIM16 timer clock enable 17 1 TIM17EN TIM17 timer clock enable 18 1 TIM1EN TIM1 timer clock enable 11 1 TIM20EN Timer 20 clock enable 20 1 TIM8EN TIM8 timer clock enable 13 1 USART1EN USART1clock enable 14 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 32 read-write n 0x0 0x0 HRTIM1RST HRTIMER reset 26 1 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 SPI1RST SPI1 reset 12 1 SPI4RST SPI 4 reset 15 1 SYSCFGRST System configuration (SYSCFG) reset 0 1 TIM15RST TIM15 timer reset 16 1 TIM16RST TIM16 timer reset 17 1 TIM17RST TIM17 timer reset 18 1 TIM1RST TIM1 timer reset 11 1 TIM20RST Timer 20 reset 20 1 TIM8RST TIM8 timer reset 13 1 USART1RST USART1 reset 14 1 APB2SMENR APB2SMENR APB2SMENR 0x80 32 read-write n 0x0 0x0 HRTIMERSMEN HRTIMER clock enable during sleep mode 26 1 SAI1SMEN SAI1 clock enable during sleep mode 21 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 SPI4SMEN SPI4 timer clocks enable during Sleep and Stop modes 15 1 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM17SMEN TIM17 timer clocks enable during Sleep and Stop modes 18 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 TIM20SMEN Timer 20clock enable during sleep mode 20 1 TIM8SMEN TIM8 timer clocks enable during Sleep and Stop modes 13 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 BDCR BDCR BDCR 0x90 32 read-write n 0x0 0x0 LSCCOEN Low speed clock output enable 24 1 read-write LSCOSEL Low speed clock output selection 25 1 read-write LSEBYP LSE oscillator bypass 2 1 read-write LSECSSD LSECSSD 6 1 read-only LSECSSON LSECSSON 5 1 read-write LSEDRV SE oscillator drive capability 3 2 read-write LSEON LSE oscillator enable 0 1 read-write LSERDY LSE oscillator ready 1 1 read-only RTCEN RTC clock enable 15 1 read-write RTCSEL RTC clock source selection 8 2 read-write VSWRST Vswitch domain software reset 16 1 read-write CCIPR1 CCIPR1 CCIPR 0x88 32 read-write n 0x0 0x0 ADC345SEL ADC3/4/5 clock source selection 30 2 ADCSEL ADCs clock source selection 28 2 CLK48SEL 48 MHz clock source selection 26 2 FDCANSEL SAI2 clock source selection 24 2 I2C1SEL I2C1 clock source selection 12 2 I2C2SEL I2C2 clock source selection 14 2 I2C3SEL I2C3 clock source selection 16 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 LPUART1SEL LPUART1 clock source selection 10 2 SAISEL Low power timer 2 clock source selection 20 2 SPISEL_ SAI1 clock source selection 22 2 UART4SEL UART4 clock source selection 6 2 UART5SEL UART5 clock source selection 8 2 USART1SEL USART1 clock source selection 0 2 USART2SEL USART2 clock source selection 2 2 USART3SEL USART3 clock source selection 4 2 CCIPR2 CCIPR2 Peripherals independent clock configuration register 0x9C 32 read-write n 0x0 0x0 I2C4SEL I2C4 clock source selection 0 2 QUADSPISEL Octospi clock source selection 20 2 CFGR CFGR Clock configuration register 0x8 32 read-write n 0x0 0x0 HPRE AHB prescaler 4 4 read-write MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOSEL Microcontroller clock output 24 4 read-write PPRE1 PB low-speed prescaler (APB1) 8 3 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write SW System clock switch 0 2 read-write SWS System clock switch status 2 2 read-only CICR CICR Clock interrupt clear register 0x20 32 write-only n 0x0 0x0 HSECSSC Clock security system interrupt clear 8 1 HSERDYC HSE ready interrupt clear 4 1 HSIRDYC HSI ready interrupt clear 3 1 LSECSSC LSE Clock security system interrupt clear 9 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 PLLSYSRDYC PLL ready interrupt clear 5 1 RC48RDYC HSI48 oscillator ready interrupt clear 10 1 CIER CIER Clock interrupt enable register 0x18 32 read-write n 0x0 0x0 HSERDYIE HSE ready interrupt enable 4 1 HSIRDYIE HSI ready interrupt enable 3 1 LSECSSIE LSE clock security system interrupt enable 9 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 PLLSYSRDYIE PLL ready interrupt enable 5 1 RC48RDYIE HSI48 ready interrupt enable 10 1 CIFR CIFR Clock interrupt flag register 0x1C 32 read-only n 0x0 0x0 HSECSSF Clock security system interrupt flag 8 1 HSERDYF HSE ready interrupt flag 4 1 HSIRDYF HSI ready interrupt flag 3 1 LSECSSF LSE Clock security system interrupt flag 9 1 LSERDYF LSE ready interrupt flag 1 1 LSIRDYF LSI ready interrupt flag 0 1 PLLSYSRDYF PLL ready interrupt flag 5 1 RC48RDYF HSI48 ready interrupt flag 10 1 CR CR Clock control register 0x0 32 read-write n 0x0 0x0 HSEBYP HSE crystal oscillator bypass 18 1 read-write HSECSSON Clock security system enable 19 1 write-only HSEON HSE clock enable 16 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSION HSI clock enable 8 1 read-write HSIRDY HSI clock ready flag 10 1 read-only PLLSYSON Main PLL enable 24 1 read-write PLLSYSRDY Main PLL clock ready flag 25 1 read-only CRRCR CRRCR Clock recovery RC register 0x98 32 read-write n 0x0 0x0 RC48CAL HSI48 clock calibration 7 9 read-only RC48ON HSI48 clock enable 0 1 read-write RC48RDY HSI48 clock ready flag 1 1 read-only CSR CSR CSR 0x94 32 read-write n 0x0 0x0 BORRSTF BOR flag 27 1 read-only LPWRSTF Low-power reset flag 31 1 read-only LSION LSI oscillator enable 0 1 read-write LSIRDY LSI oscillator ready 1 1 read-only OBLRSTF Option byte loader reset flag 25 1 read-only PADRSTF Pad reset flag 26 1 read-only RMVF Remove reset flag 23 1 read-write SFTRSTF Software reset flag 28 1 read-only WDGRSTF Independent window watchdog reset flag 29 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only ICSCR ICSCR Internal clock sources calibration register 0x4 32 read-write n 0x0 0x0 HSICAL0 Internal High Speed clock Calibration 16 8 read-only HSITRIM Internal High Speed clock trimming 24 7 read-write PLLSYSCFGR PLLSYSCFGR PLL configuration register 0xC 32 read-write n 0x0 0x0 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLSYSM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 4 PLLSYSN Main PLL multiplication factor for VCO 8 7 PLLSYSP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLSYSPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLSYSQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLSYSQEN Main PLL PLLUSB1CLK output enable 20 1 PLLSYSR Main PLL division factor for PLLCLK (system clock) 25 2 PLLSYSREN Main PLL PLLCLK output enable 24 1 RNG Random number generator RNG 0x0 0x0 0x400 registers n RNG RNG 90 CR CR control register 0x0 32 read-write n 0x0 0x0 CED Clock error detection 5 1 IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 DR DR data register 0x8 32 read-only n 0x0 0x0 RNDATA Random data 0 32 SR SR status register 0x4 32 read-write n 0x0 0x0 CECS Clock error current status 1 1 read-only CEIS Clock error interrupt status 5 1 read-write DRDY Data ready 0 1 read-only SECS Seed error current status 2 1 read-only SEIS Seed error interrupt status 6 1 read-write RTC Real-time clock RTC 0x0 0x0 0x400 registers n RTC_TAMP_CSS_LSE RTC_TAMP_CSS_LSE 2 RTC_WKUP RTC Wakeup timer 3 RTC_ALARM RTC_ALARM 41 ALRMAR ALRMAR alarm A register 0x40 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 MSK2 Alarm A minutes mask 15 1 MSK3 Alarm A hours mask 23 1 MSK4 Alarm A date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x48 32 read-write n 0x0 0x0 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 MSK2 Alarm B minutes mask 15 1 MSK3 Alarm B hours mask 23 1 MSK4 Alarm B date mask 31 1 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WDSEL Week day selection 30 1 ALRMBSSR ALRMBSSR alarm B sub second register 0x4C 32 read-write n 0x0 0x0 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 CALR CALR calibration register 0x28 32 read-write n 0x0 0x0 CALM Calibration minus 0 9 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW16 Use a 16-second calibration cycle period 13 1 CALW8 Use an 8-second calibration cycle period 14 1 CR CR control register 0x18 32 read-write n 0x0 0x0 ADD1H Add 1 hour (summer time change) 16 1 ALRAE Alarm A enable 8 1 ALRAIE Alarm A interrupt enable 12 1 ALRBE Alarm B enable 9 1 ALRBIE Alarm B interrupt enable 13 1 BKP Backup 18 1 BYPSHAD Bypass the shadow registers 5 1 COE Calibration output enable 23 1 COSEL Calibration output selection 19 1 FMT Hour format 6 1 ITSE timestamp on internal event enable 24 1 OSEL Output selection 21 2 OUT2EN OUT2EN 31 1 POL Output polarity 20 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 SUB1H Subtract 1 hour (winter time change) 17 1 TAMPALRM_PU TAMPALRM_PU 29 1 TAMPALRM_TYPE TAMPALRM_TYPE 30 1 TAMPOE TAMPOE 26 1 TAMPTS TAMPTS 25 1 TSE Time stamp enable 11 1 TSEDGE Time-stamp event active edge 3 1 TSIE Time-stamp interrupt enable 15 1 WCKSEL Wakeup clock selection 0 3 WUTE Wakeup timer enable 10 1 WUTIE Wakeup timer interrupt enable 14 1 DR DR date register 0x4 32 read-write n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 ICSR ICSR initialization and status register 0xC 32 read-write n 0x0 0x0 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only INIT Initialization mode 7 1 read-write INITF Initialization flag 6 1 read-only INITS Initialization status flag 4 1 read-only RECALPF Recalibration pending Flag 16 1 read-only RSF Registers synchronization flag 5 1 read-write SHPF Shift operation pending 3 1 read-write WUTWF Wakeup timer write flag 2 1 read-only MISR MISR status register 0x54 32 read-only n 0x0 0x0 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 ITSMF ITSMF 5 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 WUTMF WUTMF 2 1 PRER PRER prescaler register 0x10 32 read-write n 0x0 0x0 PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 SCR SCR status register 0x5C 32 write-only n 0x0 0x0 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CITSF CITSF 5 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CWUTF CWUTF 2 1 SHIFTR SHIFTR shift control register 0x2C 32 write-only n 0x0 0x0 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 SR SR status register 0x50 32 read-only n 0x0 0x0 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 ITSF ITSF 5 1 TSF TSF 3 1 TSOVF TSOVF 4 1 WUTF WUTF 2 1 SSR SSR sub second register 0x8 32 read-only n 0x0 0x0 SS Sub second value 0 16 TR TR time register 0x0 32 read-write n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 TSDR TSDR time stamp date register 0x34 32 read-only n 0x0 0x0 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 WDU Week day units 13 3 TSSSR TSSSR timestamp sub second register 0x38 32 read-only n 0x0 0x0 SS Sub second value 0 16 TSTR TSTR time stamp time register 0x30 32 read-only n 0x0 0x0 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WPR WPR write protection register 0x24 32 write-only n 0x0 0x0 KEY Write protection key 0 8 WUTR WUTR wakeup timer register 0x14 32 read-write n 0x0 0x0 WUT Wakeup auto-reload value bits 0 16 SAI Serial audio interface SAI 0x0 0x0 0x400 registers n SAI SAI 76 ACLRFR ACLRFR AClear flag register 0x1C 32 read-write n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 ACR1 ACR1 AConfiguration register 1 0x4 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 6 MCKEN MCKEN 27 1 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OSR OSR 26 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIAEN Audio block A enable 16 1 SYNCEN Synchronization enable 10 2 ACR2 ACR2 AConfiguration register 2 0x8 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 ADR ADR AData register 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 AFRCR AFRCR AFRCR 0xC 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 AIM AIM AInterrupt mask register2 0x14 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDET Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 ASLOTR ASLOTR ASlot register 0x10 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 ASR ASR AStatus register 0x18 32 read-write n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 BCLRFR BCLRFR BClear flag register 0x3C 32 write-only n 0x0 0x0 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 LFSDET Clear late frame synchronization detection flag 6 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 WCKCFG Clear wrong clock configuration flag 2 1 BCR1 BCR1 BConfiguration register 1 0x24 32 read-write n 0x0 0x0 CKSTR Clock strobing edge 9 1 DMAEN DMA enable 17 1 DS Data size 5 3 LSBFIRST Least significant bit first 8 1 MCJDIV Master clock divider 20 6 MCKEN MCKEN 27 1 MODE Audio block mode 0 2 MONO Mono mode 12 1 NODIV No divider 19 1 OSR OSR 26 1 OutDri Output drive 13 1 PRTCFG Protocol configuration 2 2 SAIBEN Audio block B enable 16 1 SYNCEN Synchronization enable 10 2 BCR2 BCR2 BConfiguration register 2 0x28 32 read-write n 0x0 0x0 COMP Companding mode 14 2 CPL Complement bit 13 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 MUTE Mute 5 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 TRIS Tristate management on data line 4 1 BDR BDR BData register 0x40 32 read-write n 0x0 0x0 DATA Data 0 32 BFRCR BFRCR BFRCR 0x2C 32 read-write n 0x0 0x0 FRL Frame length 0 8 FSALL Frame synchronization active level length 8 7 FSDEF Frame synchronization definition 16 1 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 BIM BIM BInterrupt mask register2 0x34 32 read-write n 0x0 0x0 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 LFSDETIE Late frame synchronization detection interrupt enable 6 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 WCKCFG Wrong clock configuration interrupt enable 2 1 BSLOTR BSLOTR BSlot register 0x30 32 read-write n 0x0 0x0 FBOFF First bit offset 0 5 NBSLOT Number of slots in an audio frame 8 4 SLOTEN Slot enable 16 16 SLOTSZ Slot size 6 2 BSR BSR BStatus register 0x38 32 read-only n 0x0 0x0 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FLVL FIFO level threshold 16 3 FREQ FIFO request 3 1 LFSDET Late frame synchronization detection 6 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 WCKCFG Wrong clock configuration flag 2 1 PDMCR PDMCR PDM control register 0x44 32 read-write n 0x0 0x0 CKEN1 CKEN1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 MICNBR MICNBR 4 2 PDMEN PDMEN 0 1 PDMDLY PDMDLY PDM delay register 0x48 32 read-write n 0x0 0x0 DLYM1L DLYM1L 0 3 DLYM1R DLYM1R 4 3 DLYM2L DLYM2L 8 3 DLYM2R DLYM2R 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SCB System control block SCB 0x0 0x0 0x41 registers n AFSR AFSR Auxiliary fault status register 0x3C 32 read-write n 0x0 0x0 IMPDEF Implementation defined 0 32 AIRCR AIRCR Application interrupt and reset control register 0xC 32 read-write n 0x0 0x0 ENDIANESS ENDIANESS 15 1 PRIGROUP PRIGROUP 8 3 SYSRESETREQ SYSRESETREQ 2 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 VECTKEYSTAT Register key 16 16 VECTRESET VECTRESET 0 1 BFAR BFAR Bus fault address register 0x38 32 read-write n 0x0 0x0 BFAR Bus fault address 0 32 CCR CCR Configuration and control register 0x14 32 read-write n 0x0 0x0 BFHFNMIGN BFHFNMIGN 8 1 DIV_0_TRP DIV_0_TRP 4 1 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 STKALIGN STKALIGN 9 1 UNALIGN__TRP UNALIGN_ TRP 3 1 USERSETMPEND USERSETMPEND 1 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 32 read-write n 0x0 0x0 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 DIVBYZERO Divide by zero usage fault 25 1 IACCVIOL Instruction access violation flag 1 1 IBUSERR Instruction bus error 8 1 IMPRECISERR Imprecise data bus error 10 1 INVPC Invalid PC load usage fault 18 1 INVSTATE Invalid state usage fault 17 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 NOCP No coprocessor usage fault. 19 1 PRECISERR Precise data bus error 9 1 STKERR Bus fault on stacking for exception entry 12 1 UNALIGNED Unaligned access usage fault 24 1 UNDEFINSTR Undefined instruction usage fault 16 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 CPUID CPUID CPUID base register 0x0 32 read-only n 0x0 0x0 Constant Reads as 0xF 16 4 Implementer Implementer code 24 8 PartNo Part number of the processor 4 12 Revision Revision number 0 4 Variant Variant number 20 4 HFSR HFSR Hard fault status register 0x2C 32 read-write n 0x0 0x0 DEBUG_VT Reserved for Debug use 31 1 FORCED Forced hard fault 30 1 VECTTBL Vector table hard fault 1 1 ICSR ICSR Interrupt control and state register 0x4 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag 22 1 NMIPENDSET NMI set-pending bit. 31 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 RETTOBASE Return to base level 11 1 VECTACTIVE Active vector 0 9 VECTPENDING Pending vector 12 7 MMFAR MMFAR Memory management fault address register 0x34 32 read-write n 0x0 0x0 MMFAR Memory management fault address 0 32 SCR SCR System control register 0x10 32 read-write n 0x0 0x0 SEVEONPEND Send Event on Pending bit 4 1 SLEEPDEEP SLEEPDEEP 2 1 SLEEPONEXIT SLEEPONEXIT 1 1 SHCRS SHCRS System handler control and state register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT Bus fault exception active bit 1 1 BUSFAULTENA Bus fault enable bit 17 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 MEMFAULTACT Memory management fault exception active bit 0 1 MEMFAULTENA Memory management fault enable bit 16 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SVCALLACT SVC call active bit 7 1 SVCALLPENDED SVC call pending bit 15 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTACT Usage fault exception active bit 3 1 USGFAULTENA Usage fault enable bit 18 1 USGFAULTPENDED Usage fault exception pending bit 12 1 SHCSR SHCSR System handler control and state register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT Bus fault exception active bit 1 1 BUSFAULTENA Bus fault enable bit 17 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 MEMFAULTACT Memory management fault exception active bit 0 1 MEMFAULTENA Memory management fault enable bit 16 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SVCALLACT SVC call active bit 7 1 SVCALLPENDED SVC call pending bit 15 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTACT Usage fault exception active bit 3 1 USGFAULTENA Usage fault enable bit 18 1 USGFAULTPENDED Usage fault exception pending bit 12 1 SHPR1 SHPR1 System handler priority registers 0x18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 VTOR VTOR Vector table offset register 0x8 32 read-write n 0x0 0x0 TBLOFF Vector table base offset field 9 21 SCB_ACTLR System control block ACTLR SCB 0x0 0x0 0x5 registers n ACTRL ACTRL Auxiliary control register 0x0 32 read-write n 0x0 0x0 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISMCYCINT DISMCYCINT 0 1 DISOOFP DISOOFP 9 1 SCB_ACTRL System control block ACTLR SCB 0x0 0x0 0x5 registers n ACTRL ACTRL Auxiliary control register 0x0 32 read-write n 0x0 0x0 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISMCYCINT DISMCYCINT 0 1 DISOOFP DISOOFP 9 1 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI1 SPI1 35 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN CHLEN 0 1 CKPOL CKPOL 3 1 DATLEN DATLEN 1 2 I2SCFG I2SCFG 8 2 I2SE I2SE 10 1 I2SMOD I2SMOD 11 1 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV I2SDIV 0 8 MCKOE MCKOE 9 1 ODD ODD 8 1 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 SPI2 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI2 SPI2 36 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN CHLEN 0 1 CKPOL CKPOL 3 1 DATLEN DATLEN 1 2 I2SCFG I2SCFG 8 2 I2SE I2SE 10 1 I2SMOD I2SMOD 11 1 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV I2SDIV 0 8 MCKOE MCKOE 9 1 ODD ODD 8 1 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 SPI3 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI3 SPI3 51 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN CHLEN 0 1 CKPOL CKPOL 3 1 DATLEN DATLEN 1 2 I2SCFG I2SCFG 8 2 I2SE I2SE 10 1 I2SMOD I2SMOD 11 1 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV I2SDIV 0 8 MCKOE MCKOE 9 1 ODD ODD 8 1 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 SPI4 Serial peripheral interface/Inter-IC sound SPI 0x0 0x0 0x400 registers n SPI4 SPI4 84 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 BR Baud rate control 3 3 CPHA Clock phase 0 1 CPOL Clock polarity 1 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 LSBFIRST Frame format 7 1 MSTR Master selection 2 1 RXONLY Receive only 10 1 SPE SPI enable 6 1 SSI Internal slave select 8 1 SSM Software slave management 9 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 DS Data size 8 4 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 NSSP NSS pulse management 3 1 RXDMAEN Rx buffer DMA enable 0 1 RXNEIE RX buffer not empty interrupt enable 6 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 TXEIE Tx buffer empty interrupt enable 7 1 CRCPR CRCPR CRC polynomial register 0x10 32 read-write n 0x0 0x0 CRCPOLY CRC polynomial register 0 16 DR DR data register 0xC 32 read-write n 0x0 0x0 DR Data register 0 16 I2SCFGR I2SCFGR configuration register 0x1C 32 read-write n 0x0 0x0 CHLEN CHLEN 0 1 CKPOL CKPOL 3 1 DATLEN DATLEN 1 2 I2SCFG I2SCFG 8 2 I2SE I2SE 10 1 I2SMOD I2SMOD 11 1 I2SSTD I2SSTD 4 2 PCMSYNC PCMSYNC 7 1 I2SPR I2SPR prescaler register 0x20 32 read-write n 0x0 0x0 I2SDIV I2SDIV 0 8 MCKOE MCKOE 9 1 ODD ODD 8 1 RXCRCR RXCRCR RX CRC register 0x14 32 read-only n 0x0 0x0 RxCRC Rx CRC register 0 16 SR SR status register 0x8 32 read-write n 0x0 0x0 BSY Busy flag 7 1 read-only CRCERR CRC error flag 4 1 read-write FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only RXNE Receive buffer not empty 0 1 read-only TIFRFE TI frame format error 8 1 read-only TXE Transmit buffer empty 1 1 read-only TXCRCR TXCRCR TX CRC register 0x18 32 read-only n 0x0 0x0 TxCRC Tx CRC register 0 16 STK SysTick timer STK 0x0 0x0 0x11 registers n CALIB CALIB SysTick calibration value register 0xC 32 read-write n 0x0 0x0 NOREF NOREF flag. Reads as zero 31 1 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 TENMS Calibration value 0 24 CTRL CTRL SysTick control and status register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 LOAD LOAD SysTick reload value register 0x4 32 read-write n 0x0 0x0 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 32 read-write n 0x0 0x0 CURRENT Current counter value 0 24 SYSCFG System configuration controller SYSCFG 0x0 0x0 0x2A registers n CFGR1 CFGR1 peripheral mode configuration register 0x4 32 read-write n 0x0 0x0 ANASWVDD GPIO analog switch control voltage selection 9 1 BOOSTEN BOOSTEN 8 1 FPU_IE FPU Interrupts Enable 26 6 I2C1_FMP I2C1 FM+ drive capability enable 20 1 I2C2_FMP I2C1 FM+ drive capability enable 21 1 I2C3_FMP I2C1 FM+ drive capability enable 22 1 I2C4_FMP I2C1 FM+ drive capability enable 23 1 I2C_PB6_FMP FM+ drive capability on PB6 16 1 I2C_PB7_FMP FM+ drive capability on PB6 17 1 I2C_PB8_FMP FM+ drive capability on PB6 18 1 I2C_PB9_FMP FM+ drive capability on PB6 19 1 CFGR2 CFGR2 configuration register 2 0x1C 32 read-write n 0x0 0x0 CLL Core Lockup Lock 0 1 ECCL ECC Lock 3 1 PVDL PVD Lock 2 1 SPF SRAM Parity Flag 8 1 SPL SRAM Parity Lock 1 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 32 read-write n 0x0 0x0 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 32 read-write n 0x0 0x0 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 32 read-write n 0x0 0x0 EXTI10 EXTI10 8 4 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 32 read-write n 0x0 0x0 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 MEMRMP MEMRMP Remap Memory register 0x0 32 read-write n 0x0 0x0 FB_mode User Flash Bank mode 8 1 MEM_MODE Memory mapping selection 0 3 SCSR SCSR CCM SRAM control and status register 0x18 32 read-write n 0x0 0x0 CCMBSY CCM SRAM busy by erase operation 1 1 read-only CCMER CCM SRAM Erase 0 1 read-write SKR SKR SRAM2 Key Register 0x24 32 write-only n 0x0 0x0 KEY SRAM2 Key for software erase 0 8 SWPR SWPR SRAM Write protection register 1 0x20 32 read-write n 0x0 0x0 Page0_WP Write protection 0 1 Page10_WP Write protection 10 1 Page11_WP Write protection 11 1 Page12_WP Write protection 12 1 Page13_WP Write protection 13 1 Page14_WP Write protection 14 1 Page15_WP Write protection 15 1 Page16_WP Write protection 16 1 Page17_WP Write protection 17 1 Page18_WP Write protection 18 1 Page19_WP Write protection 19 1 Page1_WP Write protection 1 1 Page20_WP Write protection 20 1 Page21_WP Write protection 21 1 Page22_WP Write protection 22 1 Page23_WP Write protection 23 1 Page24_WP Write protection 24 1 Page25_WP Write protection 25 1 Page26_WP Write protection 26 1 Page27_WP Write protection 27 1 Page28_WP Write protection 28 1 Page29_WP Write protection 29 1 Page2_WP Write protection 2 1 Page30_WP Write protection 30 1 Page31_WP Write protection 31 1 Page3_WP Write protection 3 1 Page4_WP Write protection 4 1 Page5_WP Write protection 5 1 Page6_WP Write protection 6 1 Page7_WP Write protection 7 1 Page8_WP Write protection 8 1 Page9_WP Write protection 9 1 TAMP Tamper and backup registers TAMP 0x0 0x0 0x400 registers n BKP0R BKP0R TAMP backup register 0x100 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP10R BKP10R TAMP backup register 0x128 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP11R BKP11R TAMP backup register 0x12C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP12R BKP12R TAMP backup register 0x130 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP13R BKP13R TAMP backup register 0x134 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP14R BKP14R TAMP backup register 0x138 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP15R BKP15R TAMP backup register 0x13C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP16R BKP16R TAMP backup register 0x140 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP17R BKP17R TAMP backup register 0x144 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP18R BKP18R TAMP backup register 0x148 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP19R BKP19R TAMP backup register 0x14C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP1R BKP1R TAMP backup register 0x104 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP20R BKP20R TAMP backup register 0x150 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP21R BKP21R TAMP backup register 0x154 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP22R BKP22R TAMP backup register 0x158 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP23R BKP23R TAMP backup register 0x15C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP24R BKP24R TAMP backup register 0x160 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP25R BKP25R TAMP backup register 0x164 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP26R BKP26R TAMP backup register 0x168 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP27R BKP27R TAMP backup register 0x16C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP28R BKP28R TAMP backup register 0x170 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP29R BKP29R TAMP backup register 0x174 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP2R BKP2R TAMP backup register 0x108 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP30R BKP30R TAMP backup register 0x178 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP31R BKP31R TAMP backup register 0x17C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP3R BKP3R TAMP backup register 0x10C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP4R BKP4R TAMP backup register 0x110 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP5R BKP5R TAMP backup register 0x114 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP6R BKP6R TAMP backup register 0x118 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP7R BKP7R TAMP backup register 0x11C 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP8R BKP8R TAMP backup register 0x120 32 read-write n 0x0 0x0 BKP BKP 0 32 BKP9R BKP9R TAMP backup register 0x124 32 read-write n 0x0 0x0 BKP BKP 0 32 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ITAMP3E ITAMP3E 18 1 ITAMP4E ITAMP4E 19 1 ITAMP5E ITAMP5E 20 1 ITAMP6E ITAMP6E 21 1 TAMP1E TAMP1E 0 1 TAMP2E TAMP2E 1 1 TAMP3E TAMP2E 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 TAMP1MSK TAMP1MSK 16 1 TAMP1NOER TAMP1NOER 0 1 TAMP1TRG TAMP1TRG 24 1 TAMP2MSK TAMP2MSK 17 1 TAMP2NOER TAMP2NOER 1 1 TAMP2TRG TAMP2TRG 25 1 TAMP3MSK TAMP3MSK 18 1 TAMP3NOER TAMP3NOER 2 1 TAMP3TRG TAMP3TRG 26 1 FLTCR FLTCR TAMP filter control register 0xC 32 read-write n 0x0 0x0 TAMPFLT TAMPFLT 3 2 TAMPFREQ TAMPFREQ 0 3 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 IER IER TAMP interrupt enable register 0x2C 32 read-write n 0x0 0x0 ITAMP3IE ITAMP3IE 18 1 ITAMP4IE ITAMP4IE 19 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 MISR MISR TAMP masked interrupt status register 0x34 32 read-only n 0x0 0x0 ITAMP3MF ITAMP3MF 18 1 ITAMP4MF ITAMP4MF 19 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 TAMP1MF TAMP1MF: 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 SCR SCR TAMP status clear register 0x3C 32 read-write n 0x0 0x0 CITAMP3F CITAMP3F 18 1 CITAMP4F CITAMP4F 19 1 CITAMP5F CITAMP5F 20 1 CITAMP6F CITAMP6F 21 1 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 SR SR TAMP status register 0x30 32 read-only n 0x0 0x0 ITAMP3F ITAMP3F 18 1 ITAMP4F ITAMP4F 19 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 TIM1 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM1_BRK_TIM15 TIM1_BRK_TIM15 24 TIM1_UP_TIM16 TIM1_UP_TIM16 25 TIM1_TRG_COM TIM1_TRG_COM/ 26 TIM1_CC TIM1 Capture Compare interrupt 27 TIM8_CC TIM8_CC 46 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM15 General purpose timers TIM 0x0 0x0 0x400 registers n AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NP Capture/Compare 2 complementary output polarity 7 1 CC2P Capture/Compare 2 output polarity 5 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S CC2S 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 IC2F IC2F 12 4 IC2PSC IC2PSC 10 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S CC2S 8 2 OC1CE OC1CE 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2FE OC2FE 10 1 OC2M OC2M 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE OC2PE 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output idle state 2 (OC2 output) 10 1 TI1S TI1 selection 7 1 DCR DCR DMA control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 TDE Trigger DMA request enable 14 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time generator setup 0 8 DTPE Deadtime Preload Enable 17 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 MSM Master/Slave mode 7 1 SMS Slave mode selection 0 3 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/compare 2 interrupt flag 2 1 CC2OF Capture/Compare 2 overcapture flag 10 1 COMIF COM interrupt flag 5 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TIM16 General purpose timers TIM 0x0 0x0 0x400 registers n AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time generator setup 0 8 DTPE Deadtime Preload Enable 17 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TIM17 General purpose timers TIM 0x0 0x0 0x400 registers n AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode 16 1 OC1PE Output Compare 1 preload enable 3 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 DCR DCR DMA control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time generator setup 0 8 DTPE Deadtime Preload Enable 17 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 COMG Capture/Compare control update generation 5 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 8 SR SR status register 0x10 32 read-write n 0x0 0x0 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 COMIF COM interrupt flag 5 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TIM2 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM2 TIM2 28 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 UIFCPY UIFCPY 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM3 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM3 TIM3 29 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 UIFCPY UIFCPY 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM4 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM4 TIM4 30 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 UIFCPY UIFCPY 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM5 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM5 TIM5 50 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 UIFCPY UIFCPY 31 1 CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 TIM6 Basic-timers TIM 0x0 0x0 0x400 registers n TIM6_DACUNDER TIM6_DACUNDER 54 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 TIM7 Basic-timers TIM 0x0 0x0 0x400 registers n TIM7 TIM7 55 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Low Auto-reload value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 SR SR status register 0x10 32 read-write n 0x0 0x0 UIF Update interrupt flag 0 1 TIM8 Advanced-timers TIM 0x0 0x0 0x400 registers n TIM8_BRK TIM8_BRK 43 TIM8_UP TIM8_UP 44 TIM8_TRG_COM TIM8_TRG_COM 45 AF1 AF1 TIM alternate function option register 1 0x60 32 read-write n 0x0 0x0 BKCMP1E BRK COMP1 enable 1 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP3E BRK COMP3 enable 3 1 BKCMP3P BRK COMP3 input polarity 12 1 BKCMP4E BRK COMP4 enable 4 1 BKCMP4P BRK COMP4 input polarity 13 1 BKCMP5E BRK COMP5 enable 5 1 BKCMP6E BRK COMP6 enable 6 1 BKCMP7E BRK COMP7 enable 7 1 BKINE BRK BKIN input enable 0 1 BKINP BRK BKIN input polarity 9 1 ETRSEL ETR source selection 14 4 AF2 AF2 TIM alternate function option register 2 0x64 32 read-write n 0x0 0x0 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 BK2CMP3E BRK2 COMP3 enable 3 1 BK2CMP3P BRK2 COMP3 input polarity 12 1 BK2CMP4E BRK2 COMP4 enable 4 1 BK2CMP4P BRK2 COMP4 input polarity 13 1 BK2CMP5E BRK2 COMP5 enable 5 1 BK2CMP6E BRK2 COMP6 enable 6 1 BK2CMP7E BRK2 COMP7 enable 7 1 BK2INP BRK2 BKIN input polarity 9 1 BKINE BRK BKIN input enable 0 1 OCRSEL OCREF_CLR source selection 16 3 ARR ARR auto-reload register 0x2C 32 read-write n 0x0 0x0 ARR Auto-reload value 0 16 BDTR BDTR break and dead-time register 0x44 32 read-write n 0x0 0x0 AOE Automatic output enable 14 1 BK2DSRM BK2DSRM 27 1 BK2E Break 2 Enable 24 1 BK2F Break 2 filter 20 4 BK2ID BK2ID 29 1 BK2P Break 2 polarity 25 1 BKBID BKBID 28 1 BKDSRM BKDSRM 26 1 BKE Break enable 12 1 BKF Break filter 16 4 BKP Break polarity 13 1 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 MOE Main output enable 15 1 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 CCER CCER capture/compare enable register 0x20 32 read-write n 0x0 0x0 CC1E Capture/Compare 1 output enable 0 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC2E Capture/Compare 2 output enable 4 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC3E Capture/Compare 3 output enable 8 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC4E Capture/Compare 4 output enable 12 1 CC4NE Capture/Compare 4 complementary output enable 14 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC5E Capture/Compare 5 output enable 16 1 CC5P Capture/Compare 5 output polarity 17 1 CC6E Capture/Compare 6 output enable 20 1 CC6P Capture/Compare 6 output polarity 21 1 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 ICPCS Input capture 1 prescaler 2 2 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 32 read-write n 0x0 0x0 CC1S Capture/Compare 1 selection 0 2 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1FE Output Compare 1 fast enable 2 1 OC1M Output Compare 1 mode 4 3 OC1M_3 Output Compare 1 mode - bit 3 16 1 OC1PE Output Compare 1 preload enable 3 1 OC2CE Output Compare 2 clear enable 15 1 OC2FE Output Compare 2 fast enable 10 1 OC2M Output Compare 2 mode 12 3 OC2M_3 Output Compare 2 mode - bit 3 24 1 OC2PE Output Compare 2 preload enable 11 1 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 32 read-write n 0x0 0x0 CC3S Capture/compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 32 read-write n 0x0 0x0 CC3S Capture/Compare 3 selection 0 2 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3FE Output compare 3 fast enable 2 1 OC3M Output compare 3 mode 4 3 OC3M_3 Output Compare 3 mode - bit 3 16 1 OC3PE Output compare 3 preload enable 3 1 OC4CE Output compare 4 clear enable 15 1 OC4FE Output compare 4 fast enable 10 1 OC4M Output compare 4 mode 12 3 OC4M_3 Output Compare 4 mode - bit 3 24 1 OC4PE Output compare 4 preload enable 11 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x50 32 read-write n 0x0 0x0 OC5CE Output compare 5 clear enable 7 1 OC5FE Output compare 5 fast enable 2 1 OC5M Output compare 5 mode 4 3 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC5PE Output compare 5 preload enable 3 1 OC6CE Output compare 6 clear enable 15 1 OC6FE Output compare 6 fast enable 10 1 OC6M Output compare 6 mode 12 3 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC6PE Output compare 6 preload enable 11 1 CCR1 CCR1 capture/compare register 1 0x34 32 read-write n 0x0 0x0 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 32 read-write n 0x0 0x0 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 32 read-write n 0x0 0x0 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 32 read-write n 0x0 0x0 CCR4 Capture/Compare value 0 16 CCR5 CCR5 capture/compare register 4 0x48 32 read-write n 0x0 0x0 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x4C 32 read-write n 0x0 0x0 CCR6 Capture/Compare value 0 16 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT counter value 0 16 read-write UIFCPY UIFCPY 31 1 read-only CR1 CR1 control register 1 0x0 32 read-write n 0x0 0x0 ARPE Auto-reload preload enable 7 1 CEN Counter enable 0 1 CKD Clock division 8 2 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 DITHEN Dithering Enable 12 1 OPM One-pulse mode 3 1 UDIS Update disable 1 1 UIFREMAP UIF status bit remapping 11 1 URS Update request source 2 1 CR2 CR2 control register 2 0x4 32 read-write n 0x0 0x0 CCDS Capture/compare DMA selection 3 1 CCPC Capture/compare preloaded control 0 1 CCUS Capture/compare control update selection 2 1 MMS Master mode selection 4 3 MMS2 Master mode selection 2 20 4 MMS_3 Master mode selection - bit 3 25 1 OIS1 Output Idle state 1 8 1 OIS1N Output Idle state 1 9 1 OIS2 Output Idle state 2 10 1 OIS2N Output Idle state 2 11 1 OIS3 Output Idle state 3 12 1 OIS3N Output Idle state 3 13 1 OIS4 Output Idle state 4 14 1 OIS4N Output Idle state 4 (OC4N output) 15 1 OIS5 Output Idle state 5 (OC5 output) 16 1 OIS6 Output Idle state 6 (OC6 output) 18 1 TI1S TI1 selection 7 1 DCR DCR control register 0x3DC 32 read-write n 0x0 0x0 DBA DMA base address 0 5 DBL DMA burst length 8 5 DIER DIER DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BIE Break interrupt enable 7 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC4IE Capture/Compare 4 interrupt enable 4 1 COMDE COM DMA request enable 13 1 COMIE COM interrupt enable 5 1 DIRIE Direction Change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 IERRIE Index Error interrupt enable 22 1 TDE Trigger DMA request enable 14 1 TERRIE Transition Error interrupt enable 23 1 TIE Trigger interrupt enable 6 1 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 DMAR DMAR DMA address for full transfer 0x3E0 32 read-write n 0x0 0x0 DMAB DMA register for burst accesses 0 32 DTR2 DTR2 timer Deadtime Register 2 0x54 32 read-write n 0x0 0x0 DTAE Deadtime Asymmetric Enable 16 1 DTGF Dead-time falling edge generator setup 0 8 DTPE Deadtime Preload Enable 17 1 ECR ECR DMA control register 0x58 32 read-write n 0x0 0x0 FIDX First Index 5 1 IBLK Index Blanking 3 2 IDIR Index Direction 1 2 IE Index Enable 0 1 IPOS Index Positioning 6 2 PW Pulse width 16 8 PWPRSC Pulse Width prescaler 24 3 EGR EGR event generation register 0x14 32 write-only n 0x0 0x0 B2G Break 2 generation 8 1 BG Break generation 7 1 CC1G Capture/compare 1 generation 1 1 CC2G Capture/compare 2 generation 2 1 CC3G Capture/compare 3 generation 3 1 CC4G Capture/compare 4 generation 4 1 COMG Capture/Compare control update generation 5 1 TG Trigger generation 6 1 UG Update generation 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value 0 16 RCR RCR repetition counter register 0x30 32 read-write n 0x0 0x0 REP Repetition counter value 0 16 SMCR SMCR slave mode control register 0x8 32 read-write n 0x0 0x0 ECE External clock enable 14 1 ETF External trigger filter 8 4 ETP External trigger polarity 15 1 ETPS External trigger prescaler 12 2 MSM Master/Slave mode 7 1 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 SMSPE SMS Preload Enable 24 1 SMSPS SMS Preload Source 25 1 SMS_3 Slave mode selection - bit 3 16 1 TS Trigger selection 4 3 TS_4_3 Trigger selection - bit 4:3 20 2 SR SR status register 0x10 32 read-write n 0x0 0x0 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC5IF Compare 5 interrupt flag 16 1 CC6IF Compare 6 interrupt flag 17 1 COMIF COM interrupt flag 5 1 DIRF Direction Change interrupt flag 21 1 IDXF Index interrupt flag 20 1 IERRF Index Error interrupt flag 22 1 SBIF System Break interrupt flag 13 1 TERRF Transition Error interrupt flag 23 1 TIF Trigger interrupt flag 6 1 UIF Update interrupt flag 0 1 TISEL TISEL TIM timer input selection register 0x5C 32 read-write n 0x0 0x0 TI1SEL TI1[0] to TI1[15] input selection 0 4 TI2SEL TI2[0] to TI2[15] input selection 8 4 TI3SEL TI3[0] to TI3[15] input selection 16 4 TI4SEL TI4[0] to TI4[15] input selection 24 4 UART4 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n UART4 UART4 52 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 M1 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS DIS_NSS 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN SLVEN 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE TCBGTIE 24 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 UDRCF UDRCF 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT TCBGT 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 UDR UDR 13 1 WUF WUF 20 1 PRESC PRESC USART prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 UART5 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n UART5 UART5 53 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 M1 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS DIS_NSS 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN SLVEN 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE TCBGTIE 24 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 UDRCF UDRCF 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT TCBGT 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 UDR UDR 13 1 WUF WUF 20 1 PRESC PRESC USART prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 UCPD1 UCPD1 UCPD 0x0 0x0 0x400 registers n UCPD1 UCPD1 63 CFG1 CFG1 UCPD configuration register 1 0x0 32 read-write n 0x0 0x0 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXDMAEN RXDMAEN 30 1 RXORDSETEN RXORDSETEN 20 9 TRANSWIN TRANSWIN 11 5 TXDMAEN TXDMAEN 29 1 UCPDEN UCPDEN 31 1 CFG2 CFG2 UCPD configuration register 2 0x4 32 read-write n 0x0 0x0 FORCECLK FORCECLK 2 1 RXFILT2N3 RXFILT2N3 1 1 RXFILTDIS RXFILTDIS 0 1 WUPEN WUPEN 3 1 CR CR UCPD configuration register 2 0xC 32 read-write n 0x0 0x0 ANAMODE ANAMODE 9 1 ANASUBMODE ANASUBMODE 7 2 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 CCENABLE CCENABLE 10 2 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 PHYCCSEL PHYCCSEL 6 1 PHYRXEN PHYRXEN 5 1 RDCH RDCH 18 1 RXMODE RXMODE 4 1 TXHRST TXHRST 3 1 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 ICR ICR UCPD Interrupt Clear Register 0x18 32 read-write n 0x0 0x0 FRSEVTCF FRSEVTCF 20 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXMSGENDCF RXMSGENDCF 12 1 RXORDDETCF RXORDDETCF 9 1 RXOVRCF RXOVRCF 11 1 TXMSGABTCF TXMSGABTCF 3 1 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXUNDCF TXUNDCF 6 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 IMR IMR UCPD Interrupt Mask Register 0x10 32 read-write n 0x0 0x0 FRSEVTIE FRSEVTIE 20 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXMSGENDIE RXMSGENDIE 12 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXOVRIE RXOVRIE 11 1 TXISIE TXISIE 0 1 TXMSGABTIE TXMSGABTIE 3 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXUNDIE TXUNDIE 6 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 RXDR RXDR UCPD Rx Data Register 0x30 32 read-only n 0x0 0x0 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 1 0x34 32 read-write n 0x0 0x0 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 2 0x38 32 read-write n 0x0 0x0 RXSOPX2 RXSOPX2 0 20 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 32 read-only n 0x0 0x0 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx Paysize Register 0x2C 32 read-only n 0x0 0x0 RXPAYSZ RXPAYSZ 0 10 SR SR UCPD Status Register 0x14 32 read-write n 0x0 0x0 FRSEVT FRSEVT 20 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 RXERR RXERR 13 1 RXHRSTDET RXHRSTDET 10 1 RXMSGEND RXMSGEND 12 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXOVR RXOVR 11 1 TXIS TXIS 0 1 TXMSGABT TXMSGABT 3 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXUND TXUND 6 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 TXDR TXDR UCPD Tx Data Register 0x24 32 read-write n 0x0 0x0 TXDATA TXDATA 0 8 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 32 read-write n 0x0 0x0 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx Paysize Register 0x20 32 read-write n 0x0 0x0 TXPAYSZ TXPAYSZ 0 10 USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART1 USART1 37 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 M1 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS DIS_NSS 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN SLVEN 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE TCBGTIE 24 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 UDRCF UDRCF 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT TCBGT 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 UDR UDR 13 1 WUF WUF 20 1 PRESC PRESC USART prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART2 USART2 38 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 M1 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS DIS_NSS 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN SLVEN 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE TCBGTIE 24 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 UDRCF UDRCF 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT TCBGT 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 UDR UDR 13 1 WUF WUF 20 1 PRESC PRESC USART prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USART3 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART3 USART3 39 BRR BRR Baud rate register 0xC 32 read-write n 0x0 0x0 DIV_Fraction DIV_Fraction 0 4 DIV_Mantissa DIV_Mantissa 4 12 CR1 CR1 Control register 1 0x0 32 read-write n 0x0 0x0 CMIE Character match interrupt enable 14 1 DEAT0 DEAT0 21 1 DEAT1 DEAT1 22 1 DEAT2 DEAT2 23 1 DEAT3 DEAT3 24 1 DEAT4 Driver Enable assertion time 25 1 DEDT0 DEDT0 16 1 DEDT1 DEDT1 17 1 DEDT2 DEDT2 18 1 DEDT3 DEDT3 19 1 DEDT4 Driver Enable de-assertion time 20 1 EOBIE End of Block interrupt enable 27 1 FIFOEN FIFOEN 29 1 IDLEIE IDLE interrupt enable 4 1 M0 Word length 12 1 M1 M1 28 1 MME Mute mode enable 13 1 OVER8 Oversampling mode 15 1 PCE Parity control enable 10 1 PEIE PE interrupt enable 8 1 PS Parity selection 9 1 RE Receiver enable 2 1 RTOIE Receiver timeout interrupt enable 26 1 RXFFIE RXFFIE 31 1 RXNEIE RXNE interrupt enable 5 1 TCIE Transmission complete interrupt enable 6 1 TE Transmitter enable 3 1 TXEIE interrupt enable 7 1 TXFEIE TXFEIE 30 1 UE USART enable 0 1 UESM USART enable in Stop mode 1 1 WAKE Receiver wakeup method 11 1 CR2 CR2 Control register 2 0x4 32 read-write n 0x0 0x0 ABREN Auto baud rate enable 20 1 ABRMOD0 ABRMOD0 21 1 ABRMOD1 Auto baud rate mode 22 1 ADD0_3 Address of the USART node 24 4 ADD4_7 Address of the USART node 28 4 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CLKEN Clock enable 11 1 CPHA Clock phase 9 1 CPOL Clock polarity 10 1 DIS_NSS DIS_NSS 3 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 LINEN LIN mode enable 14 1 MSBFIRST Most significant bit first 19 1 RTOEN Receiver timeout enable 23 1 RXINV RX pin active level inversion 16 1 SLVEN SLVEN 0 1 STOP STOP bits 12 2 SWAP Swap TX/RX pins 15 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 CR3 CR3 Control register 3 0x8 32 read-write n 0x0 0x0 CTSE CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DDRE DMA Disable on Reception Error 13 1 DEM Driver enable mode 14 1 DEP Driver enable polarity selection 15 1 DMAR DMA enable receiver 6 1 DMAT DMA enable transmitter 7 1 EIE Error interrupt enable 0 1 HDSEL Half-duplex selection 3 1 IREN Ir mode enable 1 1 IRLP Ir low-power 2 1 NACK Smartcard NACK enable 4 1 ONEBIT One sample bit method enable 11 1 OVRDIS Overrun Disable 12 1 RTSE RTS enable 8 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 SCARCNT Smartcard auto-retry count 17 3 SCEN Smartcard mode enable 5 1 TCBGTIE TCBGTIE 24 1 TXFTCFG TXFTCFG 29 3 TXFTIE TXFTIE 23 1 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 GTPR GTPR Guard time and prescaler register 0x10 32 read-write n 0x0 0x0 GT Guard time value 8 8 PSC Prescaler value 0 8 ICR ICR Interrupt flag clear register 0x20 32 write-only n 0x0 0x0 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 EOBCF End of block clear flag 12 1 FECF Framing error clear flag 1 1 IDLECF Idle line detected clear flag 4 1 LBDCF LIN break detection clear flag 8 1 NCF Noise detected clear flag 2 1 ORECF Overrun error clear flag 3 1 PECF Parity error clear flag 0 1 RTOCF Receiver timeout clear flag 11 1 TCBGTCF TCBGTCF 7 1 TCCF Transmission complete clear flag 6 1 TXFECF TXFECF 5 1 UDRCF UDRCF 13 1 WUCF Wakeup from Stop mode clear flag 20 1 ISR ISR Interrupt and status register 0x1C 32 read-only n 0x0 0x0 ABRE ABRE 14 1 ABRF ABRF 15 1 BUSY BUSY 16 1 CMF CMF 17 1 CTS CTS 10 1 CTSIF CTSIF 9 1 EOBF EOBF 12 1 FE FE 1 1 IDLE IDLE 4 1 LBDF LBDF 8 1 NF NF 2 1 ORE ORE 3 1 PE PE 0 1 REACK REACK 22 1 RTOF RTOF 11 1 RWU RWU 19 1 RXFF RXFF 24 1 RXFT RXFT 26 1 RXNE RXNE 5 1 SBKF SBKF 18 1 TC TC 6 1 TCBGT TCBGT 25 1 TEACK TEACK 21 1 TXE TXE 7 1 TXFE TXFE 23 1 TXFT TXFT 27 1 UDR UDR 13 1 WUF WUF 20 1 PRESC PRESC USART prescaler register 0x2C 32 read-write n 0x0 0x0 PRESCALER PRESCALER 0 4 RDR RDR Receive data register 0x24 32 read-only n 0x0 0x0 RDR Receive data value 0 9 RQR RQR Request register 0x18 32 write-only n 0x0 0x0 ABRRQ Auto baud rate request 0 1 MMRQ Mute mode request 2 1 RXFRQ Receive data flush request 3 1 SBKRQ Send break request 1 1 TXFRQ Transmit data flush request 4 1 RTOR RTOR Receiver timeout register 0x14 32 read-write n 0x0 0x0 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 TDR TDR Transmit data register 0x28 32 read-write n 0x0 0x0 TDR Transmit data value 0 9 USB_FS_device USB_FS_device USB 0x0 0x0 0x400 registers n BTABLE BTABLE Buffer table address 0x50 32 read-write n 0x0 0x0 BTABLE BTABLE 3 13 CNTR CNTR USB control register 0x40 32 read-write n 0x0 0x0 CTRM CTRM 15 1 ERRM ERRM 13 1 ESOFM ESOFM 8 1 FRES FRES 0 1 FSUSP FSUSP 3 1 L1REQM L1REQM 7 1 L1RESUME L1RESUME 5 1 LP_MODE LP_MODE 2 1 PDWN PDWN 1 1 PMAOVRM PMAOVRM 14 1 RESETM RESETM 10 1 RESUME RESUME 4 1 SOFM SOFM 9 1 SUSPM SUSPM 11 1 WKUPM WKUPM 12 1 DADDR DADDR USB device address 0x4C 32 read-write n 0x0 0x0 ADD ADD 0 7 EF EF 7 1 EP0R EP0R USB endpoint n register 0x0 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP1R EP1R USB endpoint n register 0x4 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP2R EP2R USB endpoint n register 0x8 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP3R EP3R USB endpoint n register 0xC 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP4R EP4R USB endpoint n register 0x10 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP5R EP5R USB endpoint n register 0x14 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP6R EP6R USB endpoint n register 0x18 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 EP7R EP7R USB endpoint n register 0x1C 32 read-write n 0x0 0x0 CTR_RX CTR_RX 15 1 CTR_TX CTR_TX 7 1 DTOG_RX DTOG_RX 14 1 DTOG_TX DTOG_TX 6 1 EA EA 0 4 EP_KIND EP_KIND 8 1 EP_TYPE EP_TYPE 9 2 SETUP SETUP 11 1 STAT_RX STAT_RX 12 2 STAT_TX STAT_TX 4 2 FNR FNR USB frame number register 0x48 32 read-only n 0x0 0x0 FN FN 0 11 LCK LCK 13 1 LSOF LSOF 11 2 RXDM RXDM 14 1 RXDP RXDP 15 1 ISTR ISTR USB interrupt status register 0x44 32 read-write n 0x0 0x0 CTR CTR 15 1 DIR DIR 4 1 EP_ID EP_ID 0 4 ERR ERR 13 1 ESOF ESOF 8 1 L1REQ L1REQ 7 1 PMAOVR PMAOVR 14 1 RESET RESET 10 1 SOF SOF 9 1 SUSP SUSP 11 1 WKUP WKUP 12 1 VREFBUF Voltage reference buffer VREFBUF 0x0 0x0 0x1D0 registers n CCR VREFBUF_CCR VREF_BUF Calibration Control Register 0x4 32 read-write n 0x0 0x0 TRIM Trimming code 0 6 CSR VREFBUF_CSR VREF_BUF Control and Status Register 0x0 32 read-write n 0x0 0x0 ENVR Enable Voltage Reference 0 1 read-write HIZ High impedence mode for the VREF_BUF 1 1 read-write VRR Voltage reference buffer ready 3 1 read-only VRS Voltage reference scale 4 2 read-write WWDG WinWATCHDOG IWDG 0x0 0x0 0x400 registers n CFR CFR Configuration register 0x4 32 read-write n 0x0 0x0 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 WDGTB Timer base 11 3 CR CR Control register 0x0 32 read-write n 0x0 0x0 T 7-bit counter (MSB to LSB) 0 7 WDGA Activation bit 7 1 KR KR Key register 0x0 32 write-only n 0x0 0x0 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 32 read-write n 0x0 0x0 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 32 read-write n 0x0 0x0 RL Watchdog counter reload value 0 12 SR SR Status register 0xC 32 read-only n 0x0 0x0 EWIF Early wakeup interrupt flag 0 1 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WVU Watchdog counter window value update 2 1 WINR WINR Window register 0x10 32 read-write n 0x0 0x0 WIN Watchdog counter window value 0 12