SiliconLabs EFR32MG21B010F768IM32 2024.04.27 Mighty Gecko, QFN32, 2.4G, 10dB, Mesh Multi-Protocol, 768kB, 64kB(RAM), 20 GPIO false 8 32 ACMP0_NS ACMP0_NS Registers ACMP0_NS 0x0 0x0 0x1000 registers n ACMP0 41 CFG No Description 0x8 -1 read-write n 0x0 0x0 ACCURACY ACMP accuracy mode 17 1 read-write LOW ACMP operates in low-accuracy mode but consumes less current. 0 HIGH ACMP operates in high-accuracy mode but consumes more current. 1 BIAS Bias Configuration 0 3 read-write HYST Hysteresis mode 8 4 read-write DISABLED Hysteresis disabled 0 SYM10MV 10mV symmetrical hysteresis 1 NEG30MV 30mV hysteresis on negative edge transitions 10 SYM20MV 20mV symmetrical hysteresis 2 SYM30MV 30mV symmetrical hysteresis 3 POS10MV 10mV hysteresis on positive edge transitions 4 POS20MV 20mV hysteresis on positive edge transitions 5 POS30MV 30mV hysteresis on positive edge transitions 6 NEG10MV 10mV hysteresis on negative edge transitions 8 NEG20MV 20mV hysteresis on negative edge transitions 9 INPUTRANGE Input Range 16 1 read-write FULL Use this setting when the input to the comparator core can be from 0 to AVDD. 0 REDUCED It is recommended to use this setting when the input to the comparator core will always be less than AVDD-0.7V. 1 CTRL No Description 0xC read-write n 0x0 0x0 GPIOINV Comparator GPIO Output Invert 1 1 read-write NOTINV The comparator output to GPIO is not inverted 0 INV The comparator output to GPIO is inverted 1 NOTRDYVAL Not Ready Value 0 1 read-write LOW ACMP output is 0 when the ACMP is not ready. 0 HIGH ACMP output is 1 when the ACMP is not ready. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 ACMPRDY ACMP ready interrupt enable 2 1 read-write FALL Falling edge interrupt enable 1 1 read-write INPUTCONFLICT Input conflict interrupt enable 3 1 read-write PORTALLOCERR Port allocation error interrupt enable 4 1 read-write RISE Rising edge interrupt enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 ACMPRDY ACMP ready Interrupt flag 2 1 read-write FALL Falling Edge Triggered Interrupt Flag 1 1 read-write INPUTCONFLICT Input conflict 3 1 read-write PORTALLOCERR Port allocation error 4 1 read-write RISE Rising Edge Triggered Interrupt Flag 0 1 read-write INPUTCTRL No Description 0x10 read-write n 0x0 0x0 CSRESSEL Capacitive Sense Mode Internal Resistor 28 3 read-write RES0 Internal capacitive sense resistor value 0 0 RES1 Internal capacitive sense resistor value 1 1 RES2 Internal capacitive sense resistor value 2 2 RES3 Internal capacitive sense resistor value 3 3 RES4 Internal capacitive sense resistor value 4 4 RES5 Internal capacitive sense resistor value 5 5 RES6 Internal capacitive sense resistor value 6 6 NEGSEL Negative Input Select 8 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 CAPSENSE Capsense mode 48 POSSEL Positive Input Select 0 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 VREFDIV VREF division 16 6 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 ACMPOUT Analog Comparator Output 0 1 read-only ACMPRDY Analog Comparator Ready 2 1 read-only INPUTCONFLICT INPUT conflict 3 1 read-only PORTALLOCERR Port allocation error 4 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 INPUTCTRL Syncbusy for INPUTCTRL 0 1 read-only ACMP0_S ACMP0_S Registers ACMP0_S 0x0 0x0 0x1000 registers n ACMP0 41 CFG No Description 0x8 -1 read-write n 0x0 0x0 ACCURACY ACMP accuracy mode 17 1 read-write LOW ACMP operates in low-accuracy mode but consumes less current. 0 HIGH ACMP operates in high-accuracy mode but consumes more current. 1 BIAS Bias Configuration 0 3 read-write HYST Hysteresis mode 8 4 read-write DISABLED Hysteresis disabled 0 SYM10MV 10mV symmetrical hysteresis 1 NEG30MV 30mV hysteresis on negative edge transitions 10 SYM20MV 20mV symmetrical hysteresis 2 SYM30MV 30mV symmetrical hysteresis 3 POS10MV 10mV hysteresis on positive edge transitions 4 POS20MV 20mV hysteresis on positive edge transitions 5 POS30MV 30mV hysteresis on positive edge transitions 6 NEG10MV 10mV hysteresis on negative edge transitions 8 NEG20MV 20mV hysteresis on negative edge transitions 9 INPUTRANGE Input Range 16 1 read-write FULL Use this setting when the input to the comparator core can be from 0 to AVDD. 0 REDUCED It is recommended to use this setting when the input to the comparator core will always be less than AVDD-0.7V. 1 CTRL No Description 0xC read-write n 0x0 0x0 GPIOINV Comparator GPIO Output Invert 1 1 read-write NOTINV The comparator output to GPIO is not inverted 0 INV The comparator output to GPIO is inverted 1 NOTRDYVAL Not Ready Value 0 1 read-write LOW ACMP output is 0 when the ACMP is not ready. 0 HIGH ACMP output is 1 when the ACMP is not ready. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 ACMPRDY ACMP ready interrupt enable 2 1 read-write FALL Falling edge interrupt enable 1 1 read-write INPUTCONFLICT Input conflict interrupt enable 3 1 read-write PORTALLOCERR Port allocation error interrupt enable 4 1 read-write RISE Rising edge interrupt enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 ACMPRDY ACMP ready Interrupt flag 2 1 read-write FALL Falling Edge Triggered Interrupt Flag 1 1 read-write INPUTCONFLICT Input conflict 3 1 read-write PORTALLOCERR Port allocation error 4 1 read-write RISE Rising Edge Triggered Interrupt Flag 0 1 read-write INPUTCTRL No Description 0x10 read-write n 0x0 0x0 CSRESSEL Capacitive Sense Mode Internal Resistor 28 3 read-write RES0 Internal capacitive sense resistor value 0 0 RES1 Internal capacitive sense resistor value 1 1 RES2 Internal capacitive sense resistor value 2 2 RES3 Internal capacitive sense resistor value 3 3 RES4 Internal capacitive sense resistor value 4 4 RES5 Internal capacitive sense resistor value 5 5 RES6 Internal capacitive sense resistor value 6 6 NEGSEL Negative Input Select 8 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 CAPSENSE Capsense mode 48 POSSEL Positive Input Select 0 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 VREFDIV VREF division 16 6 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 ACMPOUT Analog Comparator Output 0 1 read-only ACMPRDY Analog Comparator Ready 2 1 read-only INPUTCONFLICT INPUT conflict 3 1 read-only PORTALLOCERR Port allocation error 4 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 INPUTCTRL Syncbusy for INPUTCTRL 0 1 read-only ACMP1_NS ACMP1_NS Registers ACMP1_NS 0x0 0x0 0x1000 registers n ACMP1 42 CFG No Description 0x8 -1 read-write n 0x0 0x0 ACCURACY ACMP accuracy mode 17 1 read-write LOW ACMP operates in low-accuracy mode but consumes less current. 0 HIGH ACMP operates in high-accuracy mode but consumes more current. 1 BIAS Bias Configuration 0 3 read-write HYST Hysteresis mode 8 4 read-write DISABLED Hysteresis disabled 0 SYM10MV 10mV symmetrical hysteresis 1 NEG30MV 30mV hysteresis on negative edge transitions 10 SYM20MV 20mV symmetrical hysteresis 2 SYM30MV 30mV symmetrical hysteresis 3 POS10MV 10mV hysteresis on positive edge transitions 4 POS20MV 20mV hysteresis on positive edge transitions 5 POS30MV 30mV hysteresis on positive edge transitions 6 NEG10MV 10mV hysteresis on negative edge transitions 8 NEG20MV 20mV hysteresis on negative edge transitions 9 INPUTRANGE Input Range 16 1 read-write FULL Use this setting when the input to the comparator core can be from 0 to AVDD. 0 REDUCED It is recommended to use this setting when the input to the comparator core will always be less than AVDD-0.7V. 1 CTRL No Description 0xC read-write n 0x0 0x0 GPIOINV Comparator GPIO Output Invert 1 1 read-write NOTINV The comparator output to GPIO is not inverted 0 INV The comparator output to GPIO is inverted 1 NOTRDYVAL Not Ready Value 0 1 read-write LOW ACMP output is 0 when the ACMP is not ready. 0 HIGH ACMP output is 1 when the ACMP is not ready. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 ACMPRDY ACMP ready interrupt enable 2 1 read-write FALL Falling edge interrupt enable 1 1 read-write INPUTCONFLICT Input conflict interrupt enable 3 1 read-write PORTALLOCERR Port allocation error interrupt enable 4 1 read-write RISE Rising edge interrupt enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 ACMPRDY ACMP ready Interrupt flag 2 1 read-write FALL Falling Edge Triggered Interrupt Flag 1 1 read-write INPUTCONFLICT Input conflict 3 1 read-write PORTALLOCERR Port allocation error 4 1 read-write RISE Rising Edge Triggered Interrupt Flag 0 1 read-write INPUTCTRL No Description 0x10 read-write n 0x0 0x0 CSRESSEL Capacitive Sense Mode Internal Resistor 28 3 read-write RES0 Internal capacitive sense resistor value 0 0 RES1 Internal capacitive sense resistor value 1 1 RES2 Internal capacitive sense resistor value 2 2 RES3 Internal capacitive sense resistor value 3 3 RES4 Internal capacitive sense resistor value 4 4 RES5 Internal capacitive sense resistor value 5 5 RES6 Internal capacitive sense resistor value 6 6 NEGSEL Negative Input Select 8 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 CAPSENSE Capsense mode 48 POSSEL Positive Input Select 0 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 VREFDIV VREF division 16 6 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 ACMPOUT Analog Comparator Output 0 1 read-only ACMPRDY Analog Comparator Ready 2 1 read-only INPUTCONFLICT INPUT conflict 3 1 read-only PORTALLOCERR Port allocation error 4 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 INPUTCTRL Syncbusy for INPUTCTRL 0 1 read-only ACMP1_S ACMP1_S Registers ACMP1_S 0x0 0x0 0x1000 registers n ACMP1 42 CFG No Description 0x8 -1 read-write n 0x0 0x0 ACCURACY ACMP accuracy mode 17 1 read-write LOW ACMP operates in low-accuracy mode but consumes less current. 0 HIGH ACMP operates in high-accuracy mode but consumes more current. 1 BIAS Bias Configuration 0 3 read-write HYST Hysteresis mode 8 4 read-write DISABLED Hysteresis disabled 0 SYM10MV 10mV symmetrical hysteresis 1 NEG30MV 30mV hysteresis on negative edge transitions 10 SYM20MV 20mV symmetrical hysteresis 2 SYM30MV 30mV symmetrical hysteresis 3 POS10MV 10mV hysteresis on positive edge transitions 4 POS20MV 20mV hysteresis on positive edge transitions 5 POS30MV 30mV hysteresis on positive edge transitions 6 NEG10MV 10mV hysteresis on negative edge transitions 8 NEG20MV 20mV hysteresis on negative edge transitions 9 INPUTRANGE Input Range 16 1 read-write FULL Use this setting when the input to the comparator core can be from 0 to AVDD. 0 REDUCED It is recommended to use this setting when the input to the comparator core will always be less than AVDD-0.7V. 1 CTRL No Description 0xC read-write n 0x0 0x0 GPIOINV Comparator GPIO Output Invert 1 1 read-write NOTINV The comparator output to GPIO is not inverted 0 INV The comparator output to GPIO is inverted 1 NOTRDYVAL Not Ready Value 0 1 read-write LOW ACMP output is 0 when the ACMP is not ready. 0 HIGH ACMP output is 1 when the ACMP is not ready. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 ACMPRDY ACMP ready interrupt enable 2 1 read-write FALL Falling edge interrupt enable 1 1 read-write INPUTCONFLICT Input conflict interrupt enable 3 1 read-write PORTALLOCERR Port allocation error interrupt enable 4 1 read-write RISE Rising edge interrupt enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 ACMPRDY ACMP ready Interrupt flag 2 1 read-write FALL Falling Edge Triggered Interrupt Flag 1 1 read-write INPUTCONFLICT Input conflict 3 1 read-write PORTALLOCERR Port allocation error 4 1 read-write RISE Rising Edge Triggered Interrupt Flag 0 1 read-write INPUTCTRL No Description 0x10 read-write n 0x0 0x0 CSRESSEL Capacitive Sense Mode Internal Resistor 28 3 read-write RES0 Internal capacitive sense resistor value 0 0 RES1 Internal capacitive sense resistor value 1 1 RES2 Internal capacitive sense resistor value 2 2 RES3 Internal capacitive sense resistor value 3 3 RES4 Internal capacitive sense resistor value 4 4 RES5 Internal capacitive sense resistor value 5 5 RES6 Internal capacitive sense resistor value 6 6 NEGSEL Negative Input Select 8 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 CAPSENSE Capsense mode 48 POSSEL Positive Input Select 0 8 read-write VSS VSS 0 PA0 Port A, Pin0 128 PA1 Port A, Pin1 129 PA2 Port A, Pin2 130 PA3 Port A, Pin3 131 PA4 Port A, Pin4 132 PA5 Port A, Pin5 133 PA6 Port A, Pin6 134 PA7 Port A, Pin7 135 PA8 Port A, Pin8 136 PA9 Port A, Pin9 137 PA10 Port A, Pin10 138 PA11 Port A, Pin11 139 PA12 Port A, Pin12 140 PA13 Port A, Pin13 141 PA14 Port A, Pin14 142 PA15 Port A, Pin15 143 PB0 Port B, Pin0 144 PB1 Port B, Pin1 145 PB2 Port B, Pin2 146 PB3 Port B, Pin3 147 PB4 Port B, Pin4 148 PB5 Port B, Pin5 149 PB6 Port B, Pin6 150 PB7 Port B, Pin7 151 PB8 Port B, Pin8 152 PB9 Port B, Pin9 153 PB10 Port B, Pin10 154 PB11 Port B, Pin11 155 PB12 Port B, Pin12 156 PB13 Port B, Pin13 157 PB14 Port B, Pin14 158 PB15 Port B, Pin15 159 VREFDIVAVDD Divided AVDD 16 PC0 Port C, Pin0 160 PC1 Port C, Pin1 161 PC2 Port C, Pin2 162 PC3 Port C, Pin3 163 PC4 Port C, Pin4 164 PC5 Port C, Pin5 165 PC6 Port C, Pin6 166 PC7 Port C, Pin7 167 PC8 Port C, Pin8 168 PC9 Port C, Pin9 169 VREFDIVAVDDLP Low-Power Divided AVDD 17 PC10 Port C, Pin10 170 PC11 Port C, Pin11 171 PC12 Port C, Pin12 172 PC13 Port C, Pin13 173 PC14 Port C, Pin14 174 PC15 Port C, Pin15 175 PD0 Port D, Pin0 176 PD1 Port D, Pin1 177 PD2 Port D, Pin2 178 PD3 Port D, Pin3 179 VREFDIV1V25 Divided 1V25 reference 18 PD4 Port D, Pin4 180 PD5 Port D, Pin5 181 PD6 Port D, Pin6 182 PD7 Port D, Pin7 183 PD8 Port D, Pin8 184 PD9 Port D, Pin9 185 PD10 Port D, Pin10 186 PD11 Port D, Pin11 187 PD12 Port D, Pin12 188 PD13 Port D, Pin13 189 VREFDIV1V25LP Low-power Divided 1V25 reference 19 PD14 Port D, Pin14 190 PD15 Port D, Pin15 191 VREFDIV2V5 Divided 2V5 reference 20 VREFDIV2V5LP Low-power Divided 2V5 reference 21 VSENSE01DIV4 VSENSE0 divided by 4 32 VSENSE01DIV4LP Low-power VSENSE0 divided by 4 33 VSENSE11DIV4 VSENSE1 divided by 4 34 VSENSE11DIV4LP Low-power VSENSE1 divided by 4 35 VREFDIV VREF division 16 6 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 ACMPOUT Analog Comparator Output 0 1 read-only ACMPRDY Analog Comparator Ready 2 1 read-only INPUTCONFLICT INPUT conflict 3 1 read-only PORTALLOCERR Port allocation error 4 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 INPUTCTRL Syncbusy for INPUTCTRL 0 1 read-only AGC_NS AGC_NS Registers AGC_NS 0x0 0x0 0x1000 registers n AGC 31 AGCPERIOD No Description 0x54 -1 read-write n 0x0 0x0 MAXHICNTTHD max hi-countrer threshold 16 8 read-write PERIODHI AGC measure period hi 0 8 read-write PERIODLO AGC measure period low 8 8 read-write SETTLETIMEIF IF peak Detector settling time 24 4 read-write SETTLETIMERF RF peak Detector settling time 28 4 read-write CTRL0 No Description 0x1C -1 read-write n 0x0 0x0 ADCATTENCODE ADC Attenuator code 25 2 read-write ADCATTENMODE ADC Attenuator mode 23 1 read-write DISABLE ADC attenuator back-off will not be done by AGC 0 NOTMAXGAIN ADC attenuator is backed-off if rxgain is NOT MAXGAIN 1 AGCCLKUNDIVREQ Enable CLKUNDIV to AGC 21 1 read-write AGCRST AGC reset 31 1 read-write DISCFLOOPADJ Disable gain adjustment by CFLOOP 19 1 read-write DISPNDWNCOMP Disable PN gain decrease compensation 30 1 read-write DISPNGAINUP Disable PN gain increase 29 1 read-write DISRESETCHPWR Disable Reset of CHPWR 22 1 read-write DSADISCFLOOP Disable channel filter loop 28 1 read-write ENRSSIRESET Enables reset of RSSI and CCA 27 1 read-write MODE Mode 8 3 read-write CONT AGC loop is adjusting gain continuously. 0 LOCKPREDET Gain is locked once a preamble is detected. 1 LOCKFRAMEDET Gain is locked once a sync word is detected. 2 LOCKDSA Gain is locked once DSA is detected. 3 PWRTARGET Power Target 0 8 read-write RSSISHIFT RSSI Shift 11 8 read-write CTRL1 No Description 0x20 -1 read-write n 0x0 0x0 CCATHRSH Clear Channel Assessment (CCA) Threshold 0 8 read-write PWRPERIOD AGC measure period 12 3 read-write RSSIPERIOD RSSI measure period 8 4 read-write SUBDEN Subperiod denominator 21 5 read-write SUBINT Subperiod integer 26 6 read-write SUBNUM Subperiod numerator 16 5 read-write SUBPERIOD Subperiod 15 1 read-write CTRL2 No Description 0x24 -1 read-write n 0x0 0x0 DISRFPKD Disable RF PEAKDET 31 1 read-write DMASEL DMA select 0 1 read-write RSSI RSSI 0 GAIN Gain 1 PRSDEBUGEN PRS Debug Enable 30 1 read-write REHICNTTHD Exit threshold based on HICNT 5 8 read-write RELBYCHPWR Safe mode release mode 16 2 read-write LO_CNT Increment counter if IFPKD_LO_LAT signal is not set. 0 PWR Increment counter if channel power is below RELTARGETPWR. 1 LO_CNT_PWR Increment if either LO_CNT or PWR. 2 LO_CNT_AND_PWR Increment if both LO_CNT and PWR. 3 RELOTHD Exit threshold based on Release Counter 13 3 read-write RELTARGETPWR Safe Mode Release Power Target 18 8 read-write SAFEMODE AGC safe mode 1 1 read-write SAFEMODETHD Enter threshold 2 3 read-write CTRL3 No Description 0x28 -1 read-write n 0x0 0x0 IFPKDDEB IF PEAKDET debounce mode enable 0 1 read-write IFPKDDEBPRD IF PEAKDET debance period 3 6 read-write IFPKDDEBRST IF PEAKDET debounce period 9 4 read-write IFPKDDEBTHD IF PEAKDET debance thrshold 1 2 read-write RFPKDDEB RF PEAKDET debounce mode enable 13 1 read-write RFPKDDEBPRD RF PEAKDET debance period 16 6 read-write RFPKDDEBRST RFPKD_LAT debounce reset delay 22 4 read-write RFPKDDEBTHD RF PEAKDET debance thrshold 14 2 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FRAMERSSI No Description 0x14 -1 read-only n 0x0 0x0 FRAMERSSIFRAC FRAMERSSI fractional part 6 2 read-only FRAMERSSIINT FRAMERSSI integer part 8 8 read-only GAINRANGE No Description 0x50 -1 read-write n 0x0 0x0 BOOSTLNA LNA GAIN BOOST mode 26 1 read-write GAININCSTEP AGC gain increase step size 8 4 read-write HIPWRTHD High power detect thrshold 20 6 read-write LATCHEDHISTEP Ltached Hi step size 16 4 read-write LNABWADJ LNA BW ADJUST 27 1 read-write LNAINDEXBORDER LNA gain border 0 4 read-write PGAINDEXBORDER PGA gain border 4 4 read-write PNGAINSTEP PN Gain Step size 12 4 read-write GAINSTEPLIM No Description 0x64 -1 read-write n 0x0 0x0 CFLOOPDEL Channel Filter Loop Delay 5 7 read-write CFLOOPSTEPMAX Maximum step in slow loop 0 5 read-write HYST Hysteresis 12 4 read-write MAXPWRVAR Maximum Power Variation 16 8 read-write TRANRSTAGC power transient detector Reset AGC 24 1 read-write HICNTREGION No Description 0x58 -1 read-write n 0x0 0x0 HICNTREGION0 AGC HICNT to step size map region 0 0 4 read-write HICNTREGION1 AGC HICNT to step size map region 1 4 4 read-write HICNTREGION2 AGC HICNT to step size map region 2 8 8 read-write HICNTREGION3 AGC HICNT to step size map region 3 16 8 read-write HICNTREGION4 AGC HICNT to step size map region 4 24 8 read-write IEN No Description 0x44 read-write n 0x0 0x0 CCA CCA Interrupt Enable 2 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write IF No Description 0x38 read-write n 0x0 0x0 CCA Clear Channel Assessment 2 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSIVALID RSSI Value is Valid 0 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LBT No Description 0x88 read-write n 0x0 0x0 CCARSSIPERIOD RSSI Period during CCA measurements 0 4 read-write ENCCAGAINREDUCED CCA gain reduced 5 1 read-write ENCCARSSIMAX Use RSSIMAX to indicate CCA 6 1 read-write ENCCARSSIPERIOD RSSI PERIOD during CCA measurements 4 1 read-write LNAMIXCODE0 No Description 0x74 -1 read-write n 0x0 0x0 LNAMIXSLICE1 LNA/MIX slice code for index 1 0 6 read-write LNAMIXSLICE2 LNA/MIX slice code for index 2 6 6 read-write LNAMIXSLICE3 LNA/MIX slice code for index 3 12 6 read-write LNAMIXSLICE4 LNA/MIX slice code for index 4 18 6 read-write LNAMIXSLICE5 LNA/MIX slice code for index 5 24 6 read-write LNAMIXCODE1 No Description 0x78 -1 read-write n 0x0 0x0 LNAMIXSLICE10 LNA/MIX slice code for index 10 24 6 read-write LNAMIXSLICE6 LNA/MIX slice code for index 6 0 6 read-write LNAMIXSLICE7 LNA/MIX slice code for index 7 6 6 read-write LNAMIXSLICE8 LNA/MIX slice code for index 8 12 6 read-write LNAMIXSLICE9 LNA/MIX slice code for index 9 18 6 read-write MIRRORIF No Description 0x8C read-write n 0x0 0x0 IFMIRRORCLEAR Clear bit for the AGC IF MIRROR Register 3 1 read-write RSSINEGSTEPM Negative RSSI Step Detected 1 1 read-only RSSIPOSSTEPM Positive RSSI Step Detected 0 1 read-only SHORTRSSIPOSSTEPM Short-term Positive RSSI Step Detected 2 1 read-only PGACODE0 No Description 0x7C -1 read-write n 0x0 0x0 PGAGAIN1 PGA GAIN code for index 1 0 4 read-write PGAGAIN2 PGA GAIN code for index 2 4 4 read-write PGAGAIN3 PGA GAIN code for index 3 8 4 read-write PGAGAIN4 PGA GAIN code for index 4 12 4 read-write PGAGAIN5 PGA GAIN code for index 5 16 4 read-write PGAGAIN6 PGA GAIN code for index 6 20 4 read-write PGAGAIN7 PGA GAIN code for index 7 24 4 read-write PGAGAIN8 PGA GAIN code for index 8 28 4 read-write PGACODE1 No Description 0x80 -1 read-write n 0x0 0x0 PGAGAIN10 PGA GAIN code for index 10 4 4 read-write PGAGAIN11 PGA GAIN code for index 11 8 4 read-write PGAGAIN9 PGA GAIN code for index 9 0 4 read-write PNRFATT0 No Description 0x68 -1 read-write n 0x0 0x0 LNAMIXRFATT1 PN RF attenuation code for index 1 0 6 read-write LNAMIXRFATT2 PN RF attenuation code for index 2 6 6 read-write LNAMIXRFATT3 PN RF attenuation code for index 3 12 6 read-write LNAMIXRFATT4 PN RF attenuation code for index 4 18 6 read-write LNAMIXRFATT5 PN RF attenuation code for index 5 24 6 read-write PNRFATT1 No Description 0x6C -1 read-write n 0x0 0x0 LNAMIXRFATT10 PN RF attenuation code for index 10 24 6 read-write LNAMIXRFATT6 PN RF attenuation code for index 6 0 6 read-write LNAMIXRFATT7 PN RF attenuation code for index 7 6 6 read-write LNAMIXRFATT8 PN RF attenuation code for index 8 12 6 read-write LNAMIXRFATT9 PN RF attenuation code for index 9 18 6 read-write PNRFATT2 No Description 0x70 -1 read-write n 0x0 0x0 LNAMIXRFATT11 PN RF attenuation code for index 11 0 6 read-write LNAMIXRFATT12 PN RF attenuation code for index 12 6 6 read-write LNAMIXRFATT13 PN RF attenuation code for index 13 12 6 read-write LNAMIXRFATT14 PN RF attenuation code for index 14 18 6 read-write RSSI No Description 0x10 -1 read-only n 0x0 0x0 RSSIFRAC RSSI fractional part 6 2 read-only RSSIINT RSSI integer part 8 8 read-only RSSISTEPTHR No Description 0x2C read-write n 0x0 0x0 DEMODRESTARTPER Demodulator Restart Period 17 4 read-write DEMODRESTARTTHR Demodulator Restart Threshold 21 8 read-write NEGSTEPTHR Negative Step Threshold 8 8 read-write POSSTEPTHR Positive Step Threshold 0 8 read-write RSSIFAST RSSI fast startup 29 1 read-write STEPPER Step Period 16 1 read-write STATUS0 No Description 0x8 read-write n 0x0 0x0 ADCINDEX ADC Attenuator INDEX 23 2 read-write CCA Clear Channel Assessment 9 1 read-only GAININDEX Gain Table Index 0 6 read-only GAINOK Gain OK 10 1 read-only IFPKDHILAT IFPKD Hi threshold pass Latch 8 1 read-only IFPKDLOLAT IFPKD Lo threshold pass Latch 7 1 read-only LNAINDEX LNA GAIN INDEX 15 4 read-only PGAINDEX PGA GAIN INDEX 11 4 read-only PNINDEX PN GAIN INDEX 19 4 read-only RFPKDLAT RFPKD Latch 6 1 read-only STEPDWN No Description 0x5C -1 read-write n 0x0 0x0 STEPDWN0 AGC gain step size 0 0 3 read-write STEPDWN1 AGC gain step size 1 3 3 read-write STEPDWN2 AGC gain step size 2 6 3 read-write STEPDWN3 AGC gain step size 3 9 3 read-write STEPDWN4 AGC gain step size 4 12 3 read-write STEPDWN5 AGC gain step size 5 15 3 read-write AGC_S AGC_S Registers AGC_S 0x0 0x0 0x1000 registers n AGC 31 AGCPERIOD No Description 0x54 -1 read-write n 0x0 0x0 MAXHICNTTHD max hi-countrer threshold 16 8 read-write PERIODHI AGC measure period hi 0 8 read-write PERIODLO AGC measure period low 8 8 read-write SETTLETIMEIF IF peak Detector settling time 24 4 read-write SETTLETIMERF RF peak Detector settling time 28 4 read-write CTRL0 No Description 0x1C -1 read-write n 0x0 0x0 ADCATTENCODE ADC Attenuator code 25 2 read-write ADCATTENMODE ADC Attenuator mode 23 1 read-write DISABLE ADC attenuator back-off will not be done by AGC 0 NOTMAXGAIN ADC attenuator is backed-off if rxgain is NOT MAXGAIN 1 AGCCLKUNDIVREQ Enable CLKUNDIV to AGC 21 1 read-write AGCRST AGC reset 31 1 read-write DISCFLOOPADJ Disable gain adjustment by CFLOOP 19 1 read-write DISPNDWNCOMP Disable PN gain decrease compensation 30 1 read-write DISPNGAINUP Disable PN gain increase 29 1 read-write DISRESETCHPWR Disable Reset of CHPWR 22 1 read-write DSADISCFLOOP Disable channel filter loop 28 1 read-write ENRSSIRESET Enables reset of RSSI and CCA 27 1 read-write MODE Mode 8 3 read-write CONT AGC loop is adjusting gain continuously. 0 LOCKPREDET Gain is locked once a preamble is detected. 1 LOCKFRAMEDET Gain is locked once a sync word is detected. 2 LOCKDSA Gain is locked once DSA is detected. 3 PWRTARGET Power Target 0 8 read-write RSSISHIFT RSSI Shift 11 8 read-write CTRL1 No Description 0x20 -1 read-write n 0x0 0x0 CCATHRSH Clear Channel Assessment (CCA) Threshold 0 8 read-write PWRPERIOD AGC measure period 12 3 read-write RSSIPERIOD RSSI measure period 8 4 read-write SUBDEN Subperiod denominator 21 5 read-write SUBINT Subperiod integer 26 6 read-write SUBNUM Subperiod numerator 16 5 read-write SUBPERIOD Subperiod 15 1 read-write CTRL2 No Description 0x24 -1 read-write n 0x0 0x0 DISRFPKD Disable RF PEAKDET 31 1 read-write DMASEL DMA select 0 1 read-write RSSI RSSI 0 GAIN Gain 1 PRSDEBUGEN PRS Debug Enable 30 1 read-write REHICNTTHD Exit threshold based on HICNT 5 8 read-write RELBYCHPWR Safe mode release mode 16 2 read-write LO_CNT Increment counter if IFPKD_LO_LAT signal is not set. 0 PWR Increment counter if channel power is below RELTARGETPWR. 1 LO_CNT_PWR Increment if either LO_CNT or PWR. 2 LO_CNT_AND_PWR Increment if both LO_CNT and PWR. 3 RELOTHD Exit threshold based on Release Counter 13 3 read-write RELTARGETPWR Safe Mode Release Power Target 18 8 read-write SAFEMODE AGC safe mode 1 1 read-write SAFEMODETHD Enter threshold 2 3 read-write CTRL3 No Description 0x28 -1 read-write n 0x0 0x0 IFPKDDEB IF PEAKDET debounce mode enable 0 1 read-write IFPKDDEBPRD IF PEAKDET debance period 3 6 read-write IFPKDDEBRST IF PEAKDET debounce period 9 4 read-write IFPKDDEBTHD IF PEAKDET debance thrshold 1 2 read-write RFPKDDEB RF PEAKDET debounce mode enable 13 1 read-write RFPKDDEBPRD RF PEAKDET debance period 16 6 read-write RFPKDDEBRST RFPKD_LAT debounce reset delay 22 4 read-write RFPKDDEBTHD RF PEAKDET debance thrshold 14 2 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FRAMERSSI No Description 0x14 -1 read-only n 0x0 0x0 FRAMERSSIFRAC FRAMERSSI fractional part 6 2 read-only FRAMERSSIINT FRAMERSSI integer part 8 8 read-only GAINRANGE No Description 0x50 -1 read-write n 0x0 0x0 BOOSTLNA LNA GAIN BOOST mode 26 1 read-write GAININCSTEP AGC gain increase step size 8 4 read-write HIPWRTHD High power detect thrshold 20 6 read-write LATCHEDHISTEP Ltached Hi step size 16 4 read-write LNABWADJ LNA BW ADJUST 27 1 read-write LNAINDEXBORDER LNA gain border 0 4 read-write PGAINDEXBORDER PGA gain border 4 4 read-write PNGAINSTEP PN Gain Step size 12 4 read-write GAINSTEPLIM No Description 0x64 -1 read-write n 0x0 0x0 CFLOOPDEL Channel Filter Loop Delay 5 7 read-write CFLOOPSTEPMAX Maximum step in slow loop 0 5 read-write HYST Hysteresis 12 4 read-write MAXPWRVAR Maximum Power Variation 16 8 read-write TRANRSTAGC power transient detector Reset AGC 24 1 read-write HICNTREGION No Description 0x58 -1 read-write n 0x0 0x0 HICNTREGION0 AGC HICNT to step size map region 0 0 4 read-write HICNTREGION1 AGC HICNT to step size map region 1 4 4 read-write HICNTREGION2 AGC HICNT to step size map region 2 8 8 read-write HICNTREGION3 AGC HICNT to step size map region 3 16 8 read-write HICNTREGION4 AGC HICNT to step size map region 4 24 8 read-write IEN No Description 0x44 read-write n 0x0 0x0 CCA CCA Interrupt Enable 2 1 read-write RSSINEGSTEP RSSINEGSTEP Interrupt Enable 4 1 read-write RSSIPOSSTEP RSSIPOSSTEP Interrupt Enable 3 1 read-write RSSIVALID RSSIVALID Interrupt Enable 0 1 read-write SHORTRSSIPOSSTEP SHORTRSSIPOSSTEP Interrupt Enable 6 1 read-write IF No Description 0x38 read-write n 0x0 0x0 CCA Clear Channel Assessment 2 1 read-write RSSINEGSTEP Negative RSSI Step Detected 4 1 read-write RSSIPOSSTEP Positive RSSI Step Detected 3 1 read-write RSSIVALID RSSI Value is Valid 0 1 read-write SHORTRSSIPOSSTEP Short-term Positive RSSI Step Detected 6 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LBT No Description 0x88 read-write n 0x0 0x0 CCARSSIPERIOD RSSI Period during CCA measurements 0 4 read-write ENCCAGAINREDUCED CCA gain reduced 5 1 read-write ENCCARSSIMAX Use RSSIMAX to indicate CCA 6 1 read-write ENCCARSSIPERIOD RSSI PERIOD during CCA measurements 4 1 read-write LNAMIXCODE0 No Description 0x74 -1 read-write n 0x0 0x0 LNAMIXSLICE1 LNA/MIX slice code for index 1 0 6 read-write LNAMIXSLICE2 LNA/MIX slice code for index 2 6 6 read-write LNAMIXSLICE3 LNA/MIX slice code for index 3 12 6 read-write LNAMIXSLICE4 LNA/MIX slice code for index 4 18 6 read-write LNAMIXSLICE5 LNA/MIX slice code for index 5 24 6 read-write LNAMIXCODE1 No Description 0x78 -1 read-write n 0x0 0x0 LNAMIXSLICE10 LNA/MIX slice code for index 10 24 6 read-write LNAMIXSLICE6 LNA/MIX slice code for index 6 0 6 read-write LNAMIXSLICE7 LNA/MIX slice code for index 7 6 6 read-write LNAMIXSLICE8 LNA/MIX slice code for index 8 12 6 read-write LNAMIXSLICE9 LNA/MIX slice code for index 9 18 6 read-write MIRRORIF No Description 0x8C read-write n 0x0 0x0 IFMIRRORCLEAR Clear bit for the AGC IF MIRROR Register 3 1 read-write RSSINEGSTEPM Negative RSSI Step Detected 1 1 read-only RSSIPOSSTEPM Positive RSSI Step Detected 0 1 read-only SHORTRSSIPOSSTEPM Short-term Positive RSSI Step Detected 2 1 read-only PGACODE0 No Description 0x7C -1 read-write n 0x0 0x0 PGAGAIN1 PGA GAIN code for index 1 0 4 read-write PGAGAIN2 PGA GAIN code for index 2 4 4 read-write PGAGAIN3 PGA GAIN code for index 3 8 4 read-write PGAGAIN4 PGA GAIN code for index 4 12 4 read-write PGAGAIN5 PGA GAIN code for index 5 16 4 read-write PGAGAIN6 PGA GAIN code for index 6 20 4 read-write PGAGAIN7 PGA GAIN code for index 7 24 4 read-write PGAGAIN8 PGA GAIN code for index 8 28 4 read-write PGACODE1 No Description 0x80 -1 read-write n 0x0 0x0 PGAGAIN10 PGA GAIN code for index 10 4 4 read-write PGAGAIN11 PGA GAIN code for index 11 8 4 read-write PGAGAIN9 PGA GAIN code for index 9 0 4 read-write PNRFATT0 No Description 0x68 -1 read-write n 0x0 0x0 LNAMIXRFATT1 PN RF attenuation code for index 1 0 6 read-write LNAMIXRFATT2 PN RF attenuation code for index 2 6 6 read-write LNAMIXRFATT3 PN RF attenuation code for index 3 12 6 read-write LNAMIXRFATT4 PN RF attenuation code for index 4 18 6 read-write LNAMIXRFATT5 PN RF attenuation code for index 5 24 6 read-write PNRFATT1 No Description 0x6C -1 read-write n 0x0 0x0 LNAMIXRFATT10 PN RF attenuation code for index 10 24 6 read-write LNAMIXRFATT6 PN RF attenuation code for index 6 0 6 read-write LNAMIXRFATT7 PN RF attenuation code for index 7 6 6 read-write LNAMIXRFATT8 PN RF attenuation code for index 8 12 6 read-write LNAMIXRFATT9 PN RF attenuation code for index 9 18 6 read-write PNRFATT2 No Description 0x70 -1 read-write n 0x0 0x0 LNAMIXRFATT11 PN RF attenuation code for index 11 0 6 read-write LNAMIXRFATT12 PN RF attenuation code for index 12 6 6 read-write LNAMIXRFATT13 PN RF attenuation code for index 13 12 6 read-write LNAMIXRFATT14 PN RF attenuation code for index 14 18 6 read-write RSSI No Description 0x10 -1 read-only n 0x0 0x0 RSSIFRAC RSSI fractional part 6 2 read-only RSSIINT RSSI integer part 8 8 read-only RSSISTEPTHR No Description 0x2C read-write n 0x0 0x0 DEMODRESTARTPER Demodulator Restart Period 17 4 read-write DEMODRESTARTTHR Demodulator Restart Threshold 21 8 read-write NEGSTEPTHR Negative Step Threshold 8 8 read-write POSSTEPTHR Positive Step Threshold 0 8 read-write RSSIFAST RSSI fast startup 29 1 read-write STEPPER Step Period 16 1 read-write STATUS0 No Description 0x8 read-write n 0x0 0x0 ADCINDEX ADC Attenuator INDEX 23 2 read-write CCA Clear Channel Assessment 9 1 read-only GAININDEX Gain Table Index 0 6 read-only GAINOK Gain OK 10 1 read-only IFPKDHILAT IFPKD Hi threshold pass Latch 8 1 read-only IFPKDLOLAT IFPKD Lo threshold pass Latch 7 1 read-only LNAINDEX LNA GAIN INDEX 15 4 read-only PGAINDEX PGA GAIN INDEX 11 4 read-only PNINDEX PN GAIN INDEX 19 4 read-only RFPKDLAT RFPKD Latch 6 1 read-only STEPDWN No Description 0x5C -1 read-write n 0x0 0x0 STEPDWN0 AGC gain step size 0 0 3 read-write STEPDWN1 AGC gain step size 1 3 3 read-write STEPDWN2 AGC gain step size 2 6 3 read-write STEPDWN3 AGC gain step size 3 9 3 read-write STEPDWN4 AGC gain step size 4 12 3 read-write STEPDWN5 AGC gain step size 5 15 3 read-write AMUXCP0_NS AMUXCP0_NS Registers AMUXCP0_NS 0x0 0x0 0x1000 registers n CTRL Control 0x8 read-write n 0x0 0x0 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write IPVERSION IPVERSION 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only STATUS Status 0xC read-only n 0x0 0x0 HICAP high cap 1 1 read-only RUN running 0 1 read-only TEST Test 0x10 read-write n 0x0 0x0 FORCEBOOSTOFF Force Boost Off 13 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEREQUEST Force Request 4 1 read-write SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write TRIM No Description 0x14 -1 read-write n 0x0 0x0 BIAS2XHI Bias 2x High Power 9 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIASCTRLHI Bias Control High Power 20 3 read-write BIASCTRLLO Bias Control Low Power 16 3 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160 8.0us @ 20 MHz 3 AMUXCP0_S AMUXCP0_S Registers AMUXCP0_S 0x0 0x0 0x1000 registers n CTRL Control 0x8 read-write n 0x0 0x0 FORCEHP Force High Power 0 1 read-write FORCELP Force Low Power 1 1 read-write FORCERUN Force run 4 1 read-write FORCESTOP Force stop 5 1 read-write IPVERSION IPVERSION 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only STATUS Status 0xC read-only n 0x0 0x0 HICAP high cap 1 1 read-only RUN running 0 1 read-only TEST Test 0x10 read-write n 0x0 0x0 FORCEBOOSTOFF Force Boost Off 13 1 read-write FORCEBOOSTON Force Boost On 12 1 read-write FORCEHICAP Force high capacitance driver 8 1 read-write FORCELOCAP Force low capacitance driver 9 1 read-write FORCEREQUEST Force Request 4 1 read-write SYNCCLK Sync Clock 0 1 read-write SYNCMODE Sync Mode 1 1 read-write TRIM No Description 0x14 -1 read-write n 0x0 0x0 BIAS2XHI Bias 2x High Power 9 1 read-write BIAS2XLO Bias 2x Low Power 8 1 read-write BIASCTRLHI Bias Control High Power 20 3 read-write BIASCTRLLO Bias Control Low Power 16 3 read-write BUMP0P5XHI Bump 0.5X High Power 7 1 read-write BUMP0P5XLO Bump 0.5X Low Power 6 1 read-write BYPASSDIV2HI Bypass Div2 High Power 5 1 read-write BYPASSDIV2LO Bypass Div2 Low Power 4 1 read-write FLOATVDDCPHI Float VDDCP High Power 3 1 read-write FLOATVDDCPLO Float VDDCP Low Power 2 1 read-write PUMPCAPHI Pump Cap High Power 28 3 read-write PUMPCAPLO Pump Cap Low Power 24 3 read-write VOLTAGECTRLHI Charge Pump Voltage Control High Power 13 2 read-write VOLTAGECTRLLO Charge Pump Voltage Control Low Power 10 2 read-write WARMUPTIME Warm up time 0 2 read-write WUCYCLES72 Warm up cycle = 72 3.6us @20 MHz 0 WUCYCLES96 Warm up cycle = 96 4.8us @ 20 MHz 1 WUCYCLES128 Warm up cycle = 128 6.4us @ 20 MHz 2 WUCYCLES160 Warm up cycle = 160 8.0us @ 20 MHz 3 BUFC_NS BUFC_NS Registers BUFC_NS 0x0 0x0 0x1000 registers n BUFC 32 BUF0_ADDR No Description 0xC read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF0_CMD No Description 0x30 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF0_CTRL No Description 0x8 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF0_FIFOASYNC No Description 0x34 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF0_READDATA No Description 0x1C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF0_READOFFSET No Description 0x14 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF0_STATUS No Description 0x28 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF0_THRESHOLDCTRL No Description 0x2C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF0_WRITEDATA No Description 0x20 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF0_WRITEOFFSET No Description 0x10 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF0_XWRITE No Description 0x24 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF1_ADDR No Description 0x3C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF1_CMD No Description 0x60 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF1_CTRL No Description 0x38 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF1_FIFOASYNC No Description 0x64 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF1_READDATA No Description 0x4C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF1_READOFFSET No Description 0x44 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF1_STATUS No Description 0x58 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF1_THRESHOLDCTRL No Description 0x5C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF1_WRITEDATA No Description 0x50 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF1_WRITEOFFSET No Description 0x40 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF1_XWRITE No Description 0x54 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF2_ADDR No Description 0x6C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF2_CMD No Description 0x90 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF2_CTRL No Description 0x68 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF2_FIFOASYNC No Description 0x94 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF2_READDATA No Description 0x7C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF2_READOFFSET No Description 0x74 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF2_STATUS No Description 0x88 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF2_THRESHOLDCTRL No Description 0x8C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF2_WRITEDATA No Description 0x80 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF2_WRITEOFFSET No Description 0x70 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF2_XWRITE No Description 0x84 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF3_ADDR No Description 0x9C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF3_CMD No Description 0xC0 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF3_CTRL No Description 0x98 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF3_FIFOASYNC No Description 0xC4 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF3_READDATA No Description 0xAC read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF3_READOFFSET No Description 0xA4 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF3_STATUS No Description 0xB8 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF3_THRESHOLDCTRL No Description 0xBC read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF3_WRITEDATA No Description 0xB0 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF3_WRITEOFFSET No Description 0xA0 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF3_XWRITE No Description 0xB4 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write IEN No Description 0xEC read-write n 0x0 0x0 BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write IF No Description 0xE0 read-write n 0x0 0x0 BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0OF Buffer 0 Overflow 0 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1THR Buffer 2 Threshold Event 10 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUSERROR Bus Error 31 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only RAMBASEADDR No Description 0xF0 -1 read-write n 0x0 0x0 RAMBASEADDR RAM BASE ADDR 16 16 read-write BUFC_S BUFC_S Registers BUFC_S 0x0 0x0 0x1000 registers n BUFC 32 BUF0_ADDR No Description 0xC read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF0_CMD No Description 0x30 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF0_CTRL No Description 0x8 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF0_FIFOASYNC No Description 0x34 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF0_READDATA No Description 0x1C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF0_READOFFSET No Description 0x14 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF0_STATUS No Description 0x28 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF0_THRESHOLDCTRL No Description 0x2C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF0_WRITEDATA No Description 0x20 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF0_WRITEOFFSET No Description 0x10 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF0_XWRITE No Description 0x24 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF1_ADDR No Description 0x3C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF1_CMD No Description 0x60 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF1_CTRL No Description 0x38 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF1_FIFOASYNC No Description 0x64 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF1_READDATA No Description 0x4C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF1_READOFFSET No Description 0x44 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF1_STATUS No Description 0x58 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF1_THRESHOLDCTRL No Description 0x5C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF1_WRITEDATA No Description 0x50 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF1_WRITEOFFSET No Description 0x40 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF1_XWRITE No Description 0x54 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF2_ADDR No Description 0x6C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF2_CMD No Description 0x90 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF2_CTRL No Description 0x68 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF2_FIFOASYNC No Description 0x94 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF2_READDATA No Description 0x7C read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF2_READOFFSET No Description 0x74 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF2_STATUS No Description 0x88 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF2_THRESHOLDCTRL No Description 0x8C read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF2_WRITEDATA No Description 0x80 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF2_WRITEOFFSET No Description 0x70 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF2_XWRITE No Description 0x84 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only BUF3_ADDR No Description 0x9C read-write n 0x0 0x0 ADDR Buffer Address 0 24 read-write BUF3_CMD No Description 0xC0 write-only n 0x0 0x0 CLEAR Buffer Clear 0 1 write-only PREFETCH Prefetch 1 1 write-only BUF3_CTRL No Description 0x98 read-write n 0x0 0x0 SIZE Buffer Size 0 3 read-write SIZE64 Sets Buffer size to 64 bytes 0 SIZE128 Sets Buffer size to 128 bytes 1 SIZE256 Sets Buffer size to 256 bytes 2 SIZE512 Sets Buffer size to 512 bytes 3 SIZE1024 Sets Buffer size to 1024 bytes 4 SIZE2048 Sets Buffer size to 2048 bytes 5 SIZE4096 Sets Buffer size to 4096 bytes 6 BUF3_FIFOASYNC No Description 0xC4 write-only n 0x0 0x0 RST Reset ASYNC 0 1 write-only BUF3_READDATA No Description 0xAC read-only n 0x0 0x0 READDATA Buffer Read Data 0 8 read-only BUF3_READOFFSET No Description 0xA4 read-write n 0x0 0x0 READOFFSET Read Offset 0 13 read-write BUF3_STATUS No Description 0xB8 read-only n 0x0 0x0 BYTES Number of Bytes in the Buffer 0 13 read-only THRESHOLDFLAG Buffer Threshold Flag 20 1 read-only BUF3_THRESHOLDCTRL No Description 0xBC read-write n 0x0 0x0 THRESHOLD Buffer Threshold Value 0 12 read-write THRESHOLDMODE Buffer Threshold Mode 13 1 read-write LARGER THRESHOLDIF will be set if BYTES is larger than THRESHOLD 0 LESSOREQUAL THRESHOLDIF will be set if BYTES is less than or equal to THRESHOLD 1 BUF3_WRITEDATA No Description 0xB0 write-only n 0x0 0x0 WRITEDATA Buffer Write Data 0 8 write-only BUF3_WRITEOFFSET No Description 0xA0 read-write n 0x0 0x0 WRITEOFFSET Write Offset 0 13 read-write BUF3_XWRITE No Description 0xB4 write-only n 0x0 0x0 XORWRITEDATA Buffer XOR Write Data 0 8 write-only EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write IEN No Description 0xEC read-write n 0x0 0x0 BUF0CORR BUF0CORR Interrupt Enable 3 1 read-write BUF0OF BUF0OF Interrupt Enable 0 1 read-write BUF0THR BUF0THR Interrupt Enable 2 1 read-write BUF0UF BUF0UF Interrupt Enable 1 1 read-write BUF1CORR BUF1CORR Interrupt Enable 11 1 read-write BUF1OF BUF1OF Interrupt Enable 8 1 read-write BUF1THR BUF1THR Interrupt Enable 10 1 read-write BUF1UF BUF1UF Interrupt Enable 9 1 read-write BUF2CORR BUF2CORR Interrupt Enable 19 1 read-write BUF2OF BUF2OF Interrupt Enable 16 1 read-write BUF2THR BUF2THR Interrupt Enable 18 1 read-write BUF2UF BUF2UF Interrupt Enable 17 1 read-write BUF3CORR BUF3CORR Interrupt Enable 27 1 read-write BUF3OF BUF3OF Interrupt Enable 24 1 read-write BUF3THR BUF3THR Interrupt Enable 26 1 read-write BUF3UF BUF3UF Interrupt Enable 25 1 read-write BUSERROR BUSERROR Interrupt Enable 31 1 read-write IF No Description 0xE0 read-write n 0x0 0x0 BUF0CORR Buffer 0 Corrupt 3 1 read-write BUF0OF Buffer 0 Overflow 0 1 read-write BUF0THR Buffer 0 Threshold Event 2 1 read-write BUF0UF Buffer 0 Underflow 1 1 read-write BUF1CORR Buffer 1 Corrupt 11 1 read-write BUF1OF Buffer 1 Overflow 8 1 read-write BUF1THR Buffer 2 Threshold Event 10 1 read-write BUF1UF Buffer 1 Underflow 9 1 read-write BUF2CORR Buffer 2 Corrupt 19 1 read-write BUF2OF Buffer 2 Overflow 16 1 read-write BUF2THR Buffer 2 Threshold Event 18 1 read-write BUF2UF Buffer 2 Underflow 17 1 read-write BUF3CORR Buffer 3 Corrupt 27 1 read-write BUF3OF Buffer 3 Overflow 24 1 read-write BUF3THR Buffer 3 Threshold Event 26 1 read-write BUF3UF Buffer 3 Underflow 25 1 read-write BUSERROR Bus Error 31 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only RAMBASEADDR No Description 0xF0 -1 read-write n 0x0 0x0 RAMBASEADDR RAM BASE ADDR 16 16 read-write BURAM_NS BURAM_NS Registers BURAM_NS 0x0 0x0 0x1000 registers n RET0_REG No Description 0x0 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x28 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x2C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x30 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x34 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x38 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x3C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x40 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x44 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x48 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x4C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x4 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x50 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x54 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x58 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x5C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x60 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x64 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x68 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x6C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x70 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x74 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x8 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x78 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x7C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0xC read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x10 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x14 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x18 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x1C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x20 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x24 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write BURAM_S BURAM_S Registers BURAM_S 0x0 0x0 0x1000 registers n RET0_REG No Description 0x0 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET10_REG No Description 0x28 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET11_REG No Description 0x2C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET12_REG No Description 0x30 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET13_REG No Description 0x34 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET14_REG No Description 0x38 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET15_REG No Description 0x3C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET16_REG No Description 0x40 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET17_REG No Description 0x44 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET18_REG No Description 0x48 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET19_REG No Description 0x4C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET1_REG No Description 0x4 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET20_REG No Description 0x50 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET21_REG No Description 0x54 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET22_REG No Description 0x58 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET23_REG No Description 0x5C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET24_REG No Description 0x60 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET25_REG No Description 0x64 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET26_REG No Description 0x68 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET27_REG No Description 0x6C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET28_REG No Description 0x70 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET29_REG No Description 0x74 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET2_REG No Description 0x8 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET30_REG No Description 0x78 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET31_REG No Description 0x7C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET3_REG No Description 0xC read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET4_REG No Description 0x10 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET5_REG No Description 0x14 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET6_REG No Description 0x18 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET7_REG No Description 0x1C read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET8_REG No Description 0x20 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write RET9_REG No Description 0x24 read-write n 0x0 0x0 RETREG Latch based Retention register 0 32 read-write BURTC_NS BURTC_NS Registers BURTC_NS 0x0 0x0 0x1000 registers n BURTC 18 CFG No Description 0x8 read-write n 0x0 0x0 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 CMD No Description 0xC write-only n 0x0 0x0 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only CNT No Description 0x20 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMP No Description 0x30 read-write n 0x0 0x0 COMP Compare Value 0 32 read-write EM4WUEN No Description 0x24 read-write n 0x0 0x0 COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN BURTC Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 COMP Compare Match Interrupt Flag 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 COMP Compare Match Interrupt Flag 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 PRECNT No Description 0x1C read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 read-only n 0x0 0x0 LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 RUNNING BURTC running status 0 1 read-only SYNCBUSY No Description 0x28 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only BURTC_S BURTC_S Registers BURTC_S 0x0 0x0 0x1000 registers n BURTC 18 CFG No Description 0x8 read-write n 0x0 0x0 CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (BURTC LF CLK)/1 0 DIV2 CLK_CNT = (BURTC LF CLK)/2 1 DIV1024 CLK_CNT = (BURTC LF CLK)/1024 10 DIV2048 CLK_CNT = (BURTC LF CLK)/2048 11 DIV4096 CLK_CNT = (BURTC LF CLK)/4096 12 DIV8192 CLK_CNT = (BURTC LF CLK)/8192 13 DIV16384 CLK_CNT = (BURTC LF CLK)/16384 14 DIV32768 CLK_CNT = (BURTC LF CLK)/32768 15 DIV4 CLK_CNT = (BURTC LF CLK)/4 2 DIV8 CLK_CNT = (BURTC LF CLK)/8 3 DIV16 CLK_CNT = (BURTC LF CLK)/16 4 DIV32 CLK_CNT = (BURTC LF CLK)/32 5 DIV64 CLK_CNT = (BURTC LF CLK)/64 6 DIV128 CLK_CNT = (BURTC LF CLK)/128 7 DIV256 CLK_CNT = (BURTC LF CLK)/256 8 DIV512 CLK_CNT = (BURTC LF CLK)/512 9 COMPTOP Compare Channel is Top Value 1 1 read-write DISABLE The top value of the BURTC is 4294967295 (0xFFFFFFFF) 0 ENABLE The top value of the BURTC is given by COMP 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write DISABLE BURTC is frozen in debug mode 0 ENABLE BURTC is running in debug mode 1 CMD No Description 0xC write-only n 0x0 0x0 START Start BURTC counter 0 1 write-only STOP Stop BURTC counter 1 1 write-only CNT No Description 0x20 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMP No Description 0x30 read-write n 0x0 0x0 COMP Compare Value 0 32 read-write EM4WUEN No Description 0x24 read-write n 0x0 0x0 COMPEM4WUEN Compare Match EM4 Wakeup Enable 1 1 read-write OFEM4WUEN Overflow EM4 Wakeup Enable 0 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN BURTC Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 COMP Compare Match Interrupt Flag 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 COMP Compare Match Interrupt Flag 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock all BURTC lockable registers 44776 PRECNT No Description 0x1C read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 read-only n 0x0 0x0 LOCK Configuration Lock Status 1 1 read-only UNLOCKED All BURTC lockable registers are unlocked. 0 LOCKED All BURTC lockable registers are locked. 1 RUNNING BURTC running status 0 1 read-only SYNCBUSY No Description 0x28 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only COMP Sync busy for COMP 4 1 read-only EN Sync busy for EN 5 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only CMU_NS CMU_NS Registers CMU_NS 0x0 0x0 0x1000 registers n CMU 48 CALCMD No Description 0x50 write-only n 0x0 0x0 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCNT No Description 0x58 read-only n 0x0 0x0 CALCNT Calibration Result Counter Value 0 20 read-only CALCTRL No Description 0x54 read-write n 0x0 0x0 CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 HFRCOEM23 HFRCOEM23 is clocking down-counter 6 FSRCO FSRCO is clocking down-counter 9 UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 ULFRCO ULFRCO is clocking up-counter 10 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 HFRCOEM23 HFRCOEM23 is clocking up-counter 5 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 DPLLREFCLKCTRL No Description 0x100 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 HFRCOEM23 HFRCOEM23 is clocking EM01GRPACLK 3 FSRCO FSRCO is clocking EM01GRPACLK 4 EM23GRPACLKCTRL No Description 0x140 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 EXPORTCLKCTRL No Description 0x90 read-write n 0x0 0x0 CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK HFEXPCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT0 7 HFXO HFXO is clocking CLKOUT0 8 FSRCO FSRCO is clocking CLKOUT0 9 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK HFEXPCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT1 7 HFXO HFXO is clocking CLKOUT1 8 FSRCO FSRCO is clocking CLKOUT1 9 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK HFEXPCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT2 7 HFXO HFXO is clocking CLKOUT2 8 FSRCO FSRCO is clocking CLKOUT2 9 PRESC EXPORTCLK Prescaler 24 5 read-write IADCCLKCTRL No Description 0x180 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 HFRCOEM23 HFRCOEM23 is clocking IADCCLK 2 FSRCO FSRCO is clocking IADCCLK 3 IEN No Description 0x24 read-write n 0x0 0x0 CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALRDY Calibration Ready Interrupt Enable 0 1 read-write IF No Description 0x20 read-write n 0x0 0x0 CALOF Calibration Overflow Interrupt Flag 1 1 read-write CALRDY Calibration Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x10 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 37879 PRORTCCLKCTRL No Description 0x248 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking PRORTCCLK 1 LFXO LFXO is clocking PRORTCCLK 2 ULFRCO ULFRCO is clocking PRORTCCLK 3 RADIOCLKCTRL No Description 0x280 read-write n 0x0 0x0 EN Enable 0 1 read-write RTCCCLKCTRL No Description 0x240 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 STATUS No Description 0x8 read-only n 0x0 0x0 CALRDY Calibration Ready 0 1 read-only LOCK Configuration Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED 0 LOCKED 1 SYSCLKCTRL No Description 0x70 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 HCLKPRESC HCLK Prescaler 12 2 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 TRACECLKCTRL No Description 0x80 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write HCLK HCLK is clocking TRACECLK 2 HFRCOEM23 HFRCOEM23 is clocking TRACECLK 3 WDOG0CLKCTRL No Description 0x200 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 WDOG1CLKCTRL No Description 0x208 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG1CLK 1 LFXO LFXO is clocking WDOG1CLK 2 ULFRCO ULFRCO is clocking WDOG1CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG1CLK 4 WDOGLOCK No Description 0x14 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 37879 CMU_S CMU_S Registers CMU_S 0x0 0x0 0x1000 registers n CMU 48 CALCMD No Description 0x50 write-only n 0x0 0x0 CALSTART Calibration Start 0 1 write-only CALSTOP Calibration Stop 1 1 write-only CALCNT No Description 0x58 read-only n 0x0 0x0 CALCNT Calibration Result Counter Value 0 20 read-only CALCTRL No Description 0x54 read-write n 0x0 0x0 CALTOP Calibration Counter Top Value 0 20 read-write CONT Continuous Calibration 23 1 read-write DOWNSEL Calibration Down-counter Select 28 4 read-write DISABLED Down-counter is not clocked 0 HCLK HCLK is clocking down-counter 1 LFRCO LFRCO is clocking down-counter 10 ULFRCO ULFRCO is clocking down-counter 11 PRS PRS CMU_CALDN consumer is clocking down-counter 2 HFXO HFXO is clocking down-counter 3 LFXO LFXO is clocking down-counter 4 HFRCODPLL HFRCODPLL is clocking down-counter 5 HFRCOEM23 HFRCOEM23 is clocking down-counter 6 FSRCO FSRCO is clocking down-counter 9 UPSEL Calibration Up-counter Select 24 4 read-write DISABLED Up-counter is not clocked 0 PRS PRS CMU_CALUP consumer is clocking up-counter 1 ULFRCO ULFRCO is clocking up-counter 10 HFXO HFXO is clocking up-counter 2 LFXO LFXO is clocking up-counter 3 HFRCODPLL HFRCODPLL is clocking up-counter 4 HFRCOEM23 HFRCOEM23 is clocking up-counter 5 FSRCO FSRCO is clocking up-counter 8 LFRCO LFRCO is clocking up-counter 9 DPLLREFCLKCTRL No Description 0x100 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write DISABLED DPLLREFCLK is not clocked 0 HFXO HFXO is clocking DPLLREFCLK 1 LFXO LFXO is clocking DPLLREFCLK 2 CLKIN0 CLKIN0 is clocking DPLLREFCLK 3 EM01GRPACLKCTRL No Description 0x120 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write HFRCODPLL HFRCODPLL is clocking EM01GRPACLK 1 HFXO HFXO is clocking EM01GRPACLK 2 HFRCOEM23 HFRCOEM23 is clocking EM01GRPACLK 3 FSRCO FSRCO is clocking EM01GRPACLK 4 EM23GRPACLKCTRL No Description 0x140 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM23GRPACLK 1 LFXO LFXO is clocking EM23GRPACLK 2 ULFRCO ULFRCO is clocking EM23GRPACLK 3 EM4GRPACLKCTRL No Description 0x160 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking EM4GRPACLK 1 LFXO LFXO is clocking EM4GRPACLK 2 ULFRCO ULFRCO is clocking EM4GRPACLK 3 EXPORTCLKCTRL No Description 0x90 read-write n 0x0 0x0 CLKOUTSEL0 Clock Output Select 0 0 4 read-write DISABLED CLKOUT0 is not clocked 0 HCLK HCLK is clocking CLKOUT0 1 HFEXPCLK HFEXPCLK is clocking CLKOUT0 2 ULFRCO ULFRCO is clocking CLKOUT0 3 LFRCO LFRCO is clocking CLKOUT0 4 LFXO LFXO is clocking CLKOUT0 5 HFRCODPLL HFRCODPLL is clocking CLKOUT0 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT0 7 HFXO HFXO is clocking CLKOUT0 8 FSRCO FSRCO is clocking CLKOUT0 9 CLKOUTSEL1 Clock Output Select 1 8 4 read-write DISABLED CLKOUT1 is not clocked 0 HCLK HCLK is clocking CLKOUT1 1 HFEXPCLK HFEXPCLK is clocking CLKOUT1 2 ULFRCO ULFRCO is clocking CLKOUT1 3 LFRCO LFRCO is clocking CLKOUT1 4 LFXO LFXO is clocking CLKOUT1 5 HFRCODPLL HFRCODPLL is clocking CLKOUT1 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT1 7 HFXO HFXO is clocking CLKOUT1 8 FSRCO FSRCO is clocking CLKOUT1 9 CLKOUTSEL2 Clock Output Select 2 16 4 read-write DISABLED CLKOUT2 is not clocked 0 HCLK HCLK is clocking CLKOUT2 1 HFEXPCLK HFEXPCLK is clocking CLKOUT2 2 ULFRCO ULFRCO is clocking CLKOUT2 3 LFRCO LFRCO is clocking CLKOUT2 4 LFXO LFXO is clocking CLKOUT2 5 HFRCODPLL HFRCODPLL is clocking CLKOUT2 6 HFRCOEM23 HFRCOEM23 is clocking CLKOUT2 7 HFXO HFXO is clocking CLKOUT2 8 FSRCO FSRCO is clocking CLKOUT2 9 PRESC EXPORTCLK Prescaler 24 5 read-write IADCCLKCTRL No Description 0x180 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write EM01GRPACLK EM01GRPACLK is clocking IADCCLK 1 HFRCOEM23 HFRCOEM23 is clocking IADCCLK 2 FSRCO FSRCO is clocking IADCCLK 3 IEN No Description 0x24 read-write n 0x0 0x0 CALOF Calibration Overflow Interrupt Enable 1 1 read-write CALRDY Calibration Ready Interrupt Enable 0 1 read-write IF No Description 0x20 read-write n 0x0 0x0 CALOF Calibration Overflow Interrupt Flag 1 1 read-write CALRDY Calibration Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x10 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 37879 PRORTCCLKCTRL No Description 0x248 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking PRORTCCLK 1 LFXO LFXO is clocking PRORTCCLK 2 ULFRCO ULFRCO is clocking PRORTCCLK 3 RADIOCLKCTRL No Description 0x280 read-write n 0x0 0x0 EN Enable 0 1 read-write RTCCCLKCTRL No Description 0x240 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write LFRCO LFRCO is clocking RTCCCLK 1 LFXO LFXO is clocking RTCCCLK 2 ULFRCO ULFRCO is clocking RTCCCLK 3 STATUS No Description 0x8 read-only n 0x0 0x0 CALRDY Calibration Ready 0 1 read-only LOCK Configuration Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 WDOGLOCK Configuration Lock Status for WDOG 30 1 read-only UNLOCKED 0 LOCKED 1 SYSCLKCTRL No Description 0x70 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write FSRCO FSRCO is clocking SYSCLK 1 HFRCODPLL HFRCODPLL is clocking SYSCLK 2 HFXO HFXO is clocking SYSCLK 3 CLKIN0 CLKIN0 is clocking SYSCLK 4 HCLKPRESC HCLK Prescaler 12 2 read-write DIV1 HCLK is SYSCLK divided by 1 0 DIV2 HCLK is SYSCLK divided by 2 1 DIV4 HCLK is SYSCLK divided by 4 3 PCLKPRESC PCLK Prescaler 10 1 read-write DIV1 PCLK is HCLK divided by 1 0 DIV2 PCLK is HCLK divided by 2 1 TRACECLKCTRL No Description 0x80 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 2 read-write HCLK HCLK is clocking TRACECLK 2 HFRCOEM23 HFRCOEM23 is clocking TRACECLK 3 WDOG0CLKCTRL No Description 0x200 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG0CLK 1 LFXO LFXO is clocking WDOG0CLK 2 ULFRCO ULFRCO is clocking WDOG0CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG0CLK 4 WDOG1CLKCTRL No Description 0x208 -1 read-write n 0x0 0x0 CLKSEL Clock Select 0 3 read-write LFRCO LFRCO is clocking WDOG1CLK 1 LFXO LFXO is clocking WDOG1CLK 2 ULFRCO ULFRCO is clocking WDOG1CLK 3 HCLKDIV1024 HCLKDIV1024 is clocking WDOG1CLK 4 WDOGLOCK No Description 0x14 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 37879 DEVINFO DEVINFO Registers DEVINFO 0x0 0x0 0x1000 registers n CALTEMP Calibration Temperature Information 0x50 read-only n 0x0 0x0 TEMP Cal Temp 0 8 read-only CUSTOMINFO Custom information 0x14 read-only n 0x0 0x0 PARTNO Part Number 16 16 read-only EMUTEMP EMU Temperature Sensor Calibration 0x54 read-only n 0x0 0x0 EMUTEMPROOM Emu Room Temperature 2 9 read-only EUI48H MA-L compliant EUI48 OUI (high bits) 0x44 -1 read-only n 0x0 0x0 OUI48H OUI48H 0 16 read-only RESERVED RESERVED 16 16 read-only EUI48L MA-L compliant EUI48 OUI (low bits) and Unique Identifier (24-bit) 0x40 read-only n 0x0 0x0 OUI48L OUI48L 24 8 read-only UNIQUEID Unique ID 0 24 read-only EUI64H MA-L compliant EUI64 OUI and Unique Identifier (high bits) 0x4C read-only n 0x0 0x0 OUI64 OUI64 8 24 read-only UNIQUEH UNIQUEH 0 8 read-only EUI64L MA-L compliant EUI64 Unique Identifier (low bits) 0x48 read-only n 0x0 0x0 UNIQUEL UNIQUEL 0 32 read-only EXTINFO External component description 0x28 read-only n 0x0 0x0 CONNECTION Connection 8 8 read-only SPI SPI control interface 0 NONE No interface 255 REV Revision 16 8 read-only TYPE Type 0 8 read-only NONE 255 HFRCODPLLCAL0 HFRCODPLL Calibration 0x58 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL1 HFRCODPLL Calibration 0x5C read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL10 HFRCODPLL Calibration 0x80 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL11 HFRCODPLL Calibration 0x84 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL12 HFRCODPLL Calibration 0x88 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL13 HFRCODPLL Calibration 0x8C read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL14 HFRCODPLL Calibration 0x90 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL15 HFRCODPLL Calibration 0x94 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL16 HFRCODPLL Calibration 0x98 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL17 HFRCODPLL Calibration 0x9C read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL2 HFRCODPLL Calibration 0x60 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL3 HFRCODPLL Calibration 0x64 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL4 HFRCODPLL Calibration 0x68 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL5 HFRCODPLL Calibration 0x6C read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL6 HFRCODPLL Calibration 0x70 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL7 HFRCODPLL Calibration 0x74 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL8 HFRCODPLL Calibration 0x78 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCODPLLCAL9 HFRCODPLL Calibration 0x7C read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL0 HFRCOEM23 Calibration 0xA0 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL1 HFRCOEM23 Calibration 0xA4 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL10 HFRCOEM23 Calibration 0xC8 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL11 HFRCOEM23 Calibration 0xCC read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL12 HFRCOEM23 Calibration 0xD0 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL13 HFRCOEM23 Calibration 0xD4 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL14 HFRCOEM23 Calibration 0xD8 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL15 HFRCOEM23 Calibration 0xDC read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL16 HFRCOEM23 Calibration 0xE0 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL17 HFRCOEM23 Calibration 0xE4 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL2 HFRCOEM23 Calibration 0xA8 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL3 HFRCOEM23 Calibration 0xAC read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL4 HFRCOEM23 Calibration 0xB0 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL5 HFRCOEM23 Calibration 0xB4 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL6 HFRCOEM23 Calibration 0xB8 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL7 HFRCOEM23 Calibration 0xBC read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL8 HFRCOEM23 Calibration 0xC0 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only HFRCOEM23CAL9 HFRCOEM23 Calibration 0xC4 read-only n 0x0 0x0 CLKDIV None 24 2 read-only CMPBIAS None 21 3 read-only CMPSEL None 26 2 read-only FINETUNING None 8 6 read-only FREQRANGE None 16 5 read-only IREFTC None 28 4 read-only LDOHP None 15 1 read-only TUNING None 0 7 read-only IADC0GAIN0 IADC0 Gain Calibration Info 0x180 read-only n 0x0 0x0 GAINCANA1 None 0 16 read-only GAINCANA2 None 16 16 read-only IADC0GAIN1 IADC0 Gain Calibration Info 0x184 read-only n 0x0 0x0 GAINCANA3 None 0 16 read-only GAINCANA4 None 16 16 read-only IADC0HISPDOFFSETCAL0 IADC High Speed Offset Calibration Info 0x194 read-only n 0x0 0x0 OFFSETANA1HISPD None 0 16 read-only OFFSETANA2HISPD None 16 16 read-only IADC0HISPDOFFSETCAL1 IADC High Speed Offset Calibration Info 0x198 read-only n 0x0 0x0 OFFSETANA3HISPD None 0 16 read-only IADC0NORMALOFFSETCAL0 IADC0 Normal Offset Calibration Info 0x18C read-only n 0x0 0x0 OFFSETANA1NORM None 0 16 read-only OFFSETANA2NORM None 16 16 read-only IADC0NORMALOFFSETCAL1 IADC0 Normal Offset Calibration Info 0x190 read-only n 0x0 0x0 OFFSETANA3NORM None 0 16 read-only IADC0OFFSETCAL0 IADC0 Offset Calibration Info 0x188 read-only n 0x0 0x0 OFFSETANA1HIACC None 16 16 read-only OFFSETANABASE None 0 16 read-only INFO Version of the device info structure being used 0x0 -1 read-only n 0x0 0x0 CRC CRC 0 16 read-only DEVINFOREV DI Page Version 24 8 read-only PRODREV Production Revision 16 8 read-only LEGACY This is the legacy device detection information for tools compatability 0x1FC -1 read-only n 0x0 0x0 DEVICEFAMILY Device Family 16 8 read-only EFM32GG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 100 EFM32TG11B EFM32 Giant Gecko Device Family Series 1 Device Config 1 103 EZR32LG EZR32 Leopard Gecko Device Family 120 EZR32WG EZR32 Wonder Gecko Device Family 121 EZR32HG EZR32 Happy Gecko Device Family 122 SERIES2V0 DI page is encoded with the series 2 layout. Check alternate location. 128 EFR32MG1P EFR32 Mighty Gecko Family Series 1 Device Config 1 16 EFR32MG1B EFR32 Mighty Gecko Family Series 1 Device Config 1 17 EFR32MG1V EFR32 Mighty Gecko Family Series 1 Device Config 1 18 EFR32BG1P EFR32 Blue Gecko Family Series 1 Device Config 1 19 EFR32BG1B EFR32 Blue Gecko Family Series 1 Device Config 1 20 EFR32BG1V EFR32 Blue Gecko Family Series 1 Device Config 1 21 EFR32FG1P EFR32 Flex Gecko Family Series 1 Device Config 1 25 EFR32FG1B EFR32 Flex Gecko Family Series 1 Device Config 1 26 EFR32FG1V EFR32 Flex Gecko Family Series 1 Device Config 1 27 EFR32MG12P EFR32 Mighty Gecko Family Series 1 Device Config 2 28 EFR32MG12B EFR32 Mighty Gecko Family Series 1 Device Config 2 29 EFR32MG12V EFR32 Mighty Gecko Family Series 1 Device Config 2 30 EFR32BG12P EFR32 Blue Gecko Family Series 1 Device Config 2 31 EFR32BG12B EFR32 Blue Gecko Family Series 1 Device Config 2 32 EFR32BG12V EFR32 Blue Gecko Family Series 1 Device Config 2 33 EFR32FG12P EFR32 Flex Gecko Family Series 1 Device Config 2 37 EFR32FG12B EFR32 Flex Gecko Family Series 1 Device Config 2 38 EFR32FG12V EFR32 Flex Gecko Family Series 1 Device Config 2 39 EFR32MG13P EFR32 Mighty Gecko Family Series 13 Device Config 3 40 EFR32MG13B EFR32 Mighty Gecko Family Series 13 Device Config 3 41 EFR32MG13V EFR32 Mighty Gecko Family Series 1 Device Config 3 42 EFR32BG13P EFR32 Blue Gecko Family Series 1 Device Config 3 43 EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3 44 EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 45 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 49 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 50 EFR32FG13V EFR32 Flex Gecko Family Series 1 Device Config 3 51 EFR32MG14P EFR32 Mighty Gecko Family Series 1 Device Config 4 52 EFR32MG14B EFR32 Mighty Gecko Family Series 1 Device Config 4 53 EFR32MG14V EFR32 Mighty Gecko Family Series 1 Device Config 4 54 EFR32BG14P EFR32 Blue Gecko Family Series 1 Device Config 4 55 EFR32BG14B EFR32 Blue Gecko Family Series 1 Device Config 4 56 EFR32BG14V EFR32 Blue Gecko Family Series 1 Device Config 4 57 EFR32FG14P EFR32 Flex Gecko Family Series 1 Device Config 4 61 EFR32FG14B EFR32 Flex Gecko Family Series 1 Device Config 4 62 EFR32FG14V EFR32 Flex Gecko Family Series 1 Device Config 4 63 EFM32G EFM32 Gecko Device Family 71 EFM32GG EFM32 Giant Gecko Device Family 72 EFM32TG EFM32 Tiny Gecko Device Family 73 EFM32LG EFM32 Leopard Gecko Device Family 74 EFM32WG EFM32 Wonder Gecko Device Family 75 EFM32ZG EFM32 Zero Gecko Device Family 76 EFM32HG EFM32 Happy Gecko Device Family 77 EFM32PG1B EFM32 Pearl Gecko Device Family Series 1 Device Config 1 81 EFM32JG1B EFM32 Jade Gecko Device Family Series 1 Device Config 1 83 EFM32PG12B EFM32 Pearl Gecko Device Family Series 1 Device Config 2 85 EFM32JG12B EFM32 Jade Gecko Device Family Series 1 Device Config 2 87 EFM32PG13B EFM32 Pearl Gecko Device Family Series 1 Device Config 3 89 EFM32JG13B EFM32 Jade Gecko Device Family Series 1 Device Config 3 91 MEMINFO Flash page size and misc. chip information 0x8 read-only n 0x0 0x0 DILEN Length of DI Page 16 16 read-only FLASHPAGESIZE Flash Page Size 0 8 read-only UDPAGESIZE User Data Page Size 8 8 read-only MODULEINFO Module Information 0x14C -1 read-only n 0x0 0x0 ANTENNA None 5 3 read-only BUILTIN Built-in Antenna 0 CONNECTOR RF Connector 1 RFPAD RF Pad 2 INVERTEDF F-invert PCB 3 EXPRESS None 17 1 read-only SUPPORTED Blue Gecko Express is supported 0 NONE Blue Gecko Express is not supported 1 EXTVALID None 31 1 read-only EXTUSED EXT used 0 EXTUNUSED EXT not used 1 HFXOCALVAL None 19 1 read-only VALID HFXO calibration in MODXOCAL is valid 0 NOTVALID HFXO calibration in MODXOCAL is not valid 1 HWREV None 0 5 read-only LFXO None 16 1 read-only NONE LFXO is not installed 0 PRESENT LFXO is installed 1 LFXOCALVAL None 18 1 read-only VALID LFXO Tuning in MODXOCAL is valid 0 NOTVALID LFXO Tuning value in MODXOCAL is not valid 1 MODNUMBER None 8 7 read-only MODNUMBERMSB None 20 9 read-only PADCDC None 29 1 read-only VDCDC PAVDD connected to Vdcdc 0 OTHER PAVDD connected to Vdd or other 1 PHYLIMITED None 30 1 read-only LIMITED 0 UNLIMITED 1 TYPE None 15 1 read-only PCB PCB 0 SIP SIP 1 MODULENAME0 Characters 1-4 of Module Name stored as a null terminated string 0x130 -1 read-only n 0x0 0x0 MODCHAR1 None 0 8 read-only MODCHAR2 None 8 8 read-only MODCHAR3 None 16 8 read-only MODCHAR4 None 24 8 read-only MODULENAME1 Characters 5-8 of Module Name stored as a null terminated string 0x134 -1 read-only n 0x0 0x0 MODCHAR5 None 0 8 read-only MODCHAR6 None 8 8 read-only MODCHAR7 None 16 8 read-only MODCHAR8 None 24 8 read-only MODULENAME2 Characters 9-12 of Module Name stored as a null terminated string 0x138 -1 read-only n 0x0 0x0 MODCHAR10 None 8 8 read-only MODCHAR11 None 16 8 read-only MODCHAR12 None 24 8 read-only MODCHAR9 None 0 8 read-only MODULENAME3 Characters 13-16 of Module Name stored as a null terminated string 0x13C -1 read-only n 0x0 0x0 MODCHAR13 None 0 8 read-only MODCHAR14 None 8 8 read-only MODCHAR15 None 16 8 read-only MODCHAR16 None 24 8 read-only MODULENAME4 Characters 17-20 of Module Name stored as a null terminated string 0x140 -1 read-only n 0x0 0x0 MODCHAR17 None 0 8 read-only MODCHAR18 None 8 8 read-only MODCHAR19 None 16 8 read-only MODCHAR20 None 24 8 read-only MODULENAME5 Characters 21-24 of Module Name stored as a null terminated string 0x144 -1 read-only n 0x0 0x0 MODCHAR21 None 0 8 read-only MODCHAR22 None 8 8 read-only MODCHAR23 None 16 8 read-only MODCHAR24 None 24 8 read-only MODULENAME6 Characters 25-26 of Module Name stored as a null terminated string 0x148 -1 read-only n 0x0 0x0 MODCHAR25 None 0 8 read-only MODCHAR26 None 8 8 read-only RSV None 16 16 read-only MODXOCAL Module Crystal Oscillator Calibration 0x150 -1 read-only n 0x0 0x0 HFXOCTUNEXIANA None 0 8 read-only HFXOCTUNEXOANA None 8 8 read-only LFXOCAPTUNE None 16 7 read-only MSIZE Flash and SRAM Memory size in kB 0xC read-only n 0x0 0x0 FLASH Flash Size 0 16 read-only SRAM Sram Size 16 11 read-only PART Part description 0x4 read-only n 0x0 0x0 DEVICENUM Device Number 0 16 read-only FAMILY Device Family 24 6 read-only FG Flex Gecko 0 MG Mighty Gecko 1 BG BlueGecko 2 FAMILYNUM Device Family 16 6 read-only PKGINFO Miscellaneous device information 0x10 read-only n 0x0 0x0 PINCOUNT Pin Count 16 8 read-only PKGTYPE Package Type 8 8 read-only WLCSP WLCSP package 74 BGA BGA package 76 QFN QFN package 77 QFP QFP package 81 TEMPGRADE Temperature Grade 0 8 read-only N40TO85 -40 to 85 degC 0 N40TO125 -40 to 125 degC 1 N40TO105 -40 to 105 degC 2 N0TO70 0 to 70 degC 3 SWCAPA0 Software Capability Vector 0 0x1C read-only n 0x0 0x0 BTSMART Bluetooth Smart Capability 12 2 read-only LEVEL0 Bluetooth SMART stack capability not available 0 LEVEL1 Bluetooth SMART enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 CONNECT Connect Capability 16 2 read-only LEVEL0 Connect stack capability not available 0 LEVEL1 Connect enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 RF4CE RF4CE Capability 8 2 read-only LEVEL0 RF4CE stack capability not available 0 LEVEL1 RF4CE stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 SRI RAIL Capability 20 2 read-only LEVEL0 RAIL capability not available 0 LEVEL1 RAIL enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 THREAD Thread Capability 4 2 read-only LEVEL0 Thread stack capability not available 0 LEVEL1 Thread stack enabled 1 LEVEL2 N/A 2 LEVEL3 N/A 3 ZIGBEE Zigbee Capability 0 2 read-only LEVEL0 Zigbee stack capability not available 0 LEVEL1 Green Power only 1 LEVEL2 Zigbee and Green Power 2 LEVEL3 Zigbee Only 3 SWCAPA1 Software Capability Vector 1 0x20 read-only n 0x0 0x0 GWEN Gateway 2 1 read-only NCPEN NCP 1 1 read-only RFMCUEN RF-MCU 0 1 read-only SWFIX Used to track s/w workaround info 0x18 -1 read-only n 0x0 0x0 RSV Reserved 0 32 read-only DPLL0_NS DPLL0_NS Registers DPLL0_NS 0x0 0x0 0x1000 registers n DPLL0 52 CFG No Description 0x8 read-write n 0x0 0x0 AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write EDGESEL Reference Edge Select 1 1 read-write MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 CFG1 No Description 0xC read-write n 0x0 0x0 M Factor M 0 12 read-write N Factor N 16 12 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write IF No Description 0x10 read-write n 0x0 0x0 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x24 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 28930 STATUS No Description 0x18 read-only n 0x0 0x0 ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED DPLL is unlocked 0 LOCKED DPLL is locked 1 RDY Ready Status 0 1 read-only DPLL0_S DPLL0_S Registers DPLL0_S 0x0 0x0 0x1000 registers n DPLL0 52 CFG No Description 0x8 read-write n 0x0 0x0 AUTORECOVER Automatic Recovery Control 2 1 read-write DITHEN Dither Enable Control 6 1 read-write EDGESEL Reference Edge Select 1 1 read-write MODE Operating Mode Control 0 1 read-write FLL Frequency Lock Mode 0 PLL Phase Lock Mode 1 CFG1 No Description 0xC read-write n 0x0 0x0 M Factor M 0 12 read-write N Factor N 16 12 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 LOCK LOCK interrupt Enable 0 1 read-write LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable 2 1 read-write LOCKFAILLOW LOCKFAILLOW Interrupe Enable 1 1 read-write IF No Description 0x10 read-write n 0x0 0x0 LOCK Lock Interrupt Flag 0 1 read-write LOCKFAILHIGH Lock Failure High Interrupt Flag 2 1 read-write LOCKFAILLOW Lock Failure Low Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x24 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock code 28930 STATUS No Description 0x18 read-only n 0x0 0x0 ENS Enable Status 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED DPLL is unlocked 0 LOCKED DPLL is locked 1 RDY Ready Status 0 1 read-only EMU_NS EMU_NS Registers EMU_NS 0x0 0x0 0x1000 registers n EMU 5 EMUDG 29 EMUSE 30 BOD3SENSE No Description 0x20 read-write n 0x0 0x0 AVDDBODEN AVDD BOD enable 0 1 read-write IOVDD0BODEN VDDIO0 BOD enable 1 1 read-write IOVDD1BODEN VDDIO1 BOD enable 2 1 read-write CMD No Description 0x70 write-only n 0x0 0x0 EM4UNLATCH EM4 unlatch 1 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x74 -1 read-write n 0x0 0x0 EM2DBGEN Enable debugging in EM2 0 1 read-write FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write DECBOD No Description 0x10 -1 read-write n 0x0 0x0 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write DGIEN No Description 0xA4 read-write n 0x0 0x0 EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write DGIF No Description 0xA0 read-write n 0x0 0x0 EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write EM4CTRL No Description 0x6C read-write n 0x0 0x0 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software sets EM4UNLATCH in EMU_CMD register to remove retention 2 IEN No Description 0x68 read-write n 0x0 0x0 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write IF No Description 0x64 read-write n 0x0 0x0 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write LOCK No Description 0x60 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 RSTCAUSE No Description 0x94 read-only n 0x0 0x0 AVDDBOD LEBOD1 Reset 10 1 read-only DECBOD LVBOD Reset 9 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only PIN Pin Reset 1 1 read-only POR Power On Reset 0 1 read-only SELOCKUP SE Lockup Reset 15 1 read-only SESYSREQ SE System Reset 14 1 read-only SETAMPER SE Tamper event Reset 13 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only WDOG1 Watchdog 1 Reset 4 1 read-only RSTCTRL No Description 0x90 -1 read-write n 0x0 0x0 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 SELOCKUPRMODE Enable SE Lockup reset 15 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SESYSRMODE Enable SE System reset 14 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 WDOG1RMODE Enable WDOG1 reset 1 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SEIEN No Description 0xAC read-write n 0x0 0x0 TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write SEIF No Description 0xA8 read-write n 0x0 0x0 TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature low Interrupt flag 31 1 read-write TEMPLOW Temperature Interrupt flag 30 1 read-write STATUS No Description 0x84 -1 read-only n 0x0 0x0 EM2ENTERED EM2 entered 14 1 read-only EM4IORET EM4 IO retention status 12 1 read-only FIRSTTEMPDONE First Temp done 1 1 read-only LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 RACACTIVE RAC active 10 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMP No Description 0x88 read-only n 0x0 0x0 TEMP Temperature measured 2 9 read-only TEMPLSB Temperature measured decimal part 0 2 read-only TEMPLIMITS No Description 0x78 -1 read-write n 0x0 0x0 TEMPHIGH Temp High limit 16 9 read-write TEMPLOW Temp Low limit 0 9 read-write EMU_S EMU_S Registers EMU_S 0x0 0x0 0x1000 registers n EMU 5 EMUDG 29 EMUSE 30 BOD3SENSE No Description 0x20 read-write n 0x0 0x0 AVDDBODEN AVDD BOD enable 0 1 read-write IOVDD0BODEN VDDIO0 BOD enable 1 1 read-write IOVDD1BODEN VDDIO1 BOD enable 2 1 read-write CMD No Description 0x70 write-only n 0x0 0x0 EM4UNLATCH EM4 unlatch 1 1 write-only RSTCAUSECLR Reset Cause Clear 17 1 write-only CTRL No Description 0x74 -1 read-write n 0x0 0x0 EM2DBGEN Enable debugging in EM2 0 1 read-write FLASHPWRUPONDEMAND Enable flash on demand wakeup 16 1 read-write DECBOD No Description 0x10 -1 read-write n 0x0 0x0 DECBODEN DECBOD enable 0 1 read-write DECBODMASK DECBOD Mask 1 1 read-write DECOVMBODEN Over Voltage Monitor enable 4 1 read-write DECOVMBODMASK Over Voltage Monitor Mask 5 1 read-write DGIEN No Description 0xA4 read-write n 0x0 0x0 EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write DGIF No Description 0xA0 read-write n 0x0 0x0 EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write EM4CTRL No Description 0x6C read-write n 0x0 0x0 EM4ENTRY EM4 entry request 0 2 read-write EM4IORETMODE EM4 IO retention mode 4 2 read-write DISABLE No Retention: Pads enter reset state when entering EM4 0 EM4EXIT Retention through EM4: Pads enter reset state when exiting EM4 1 SWUNLATCH Retention through EM4 and Wakeup: software sets EM4UNLATCH in EMU_CMD register to remove retention 2 IEN No Description 0x68 read-write n 0x0 0x0 AVDDBOD AVDD BOD Interrupt enable 16 1 read-write EM23WAKEUP EM23 Wake up Interrupt enable 24 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt enable 17 1 read-write TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write IF No Description 0x64 read-write n 0x0 0x0 AVDDBOD AVDD BOD Interrupt flag 16 1 read-write EM23WAKEUP EM23 Wake up Interrupt flag 24 1 read-write IOVDD0BOD VDDIO0 BOD Interrupt flag 17 1 read-write TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature high Interrupt flag 31 1 read-write TEMPLOW Temperature low Interrupt flag 30 1 read-write LOCK No Description 0x60 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock EMU register 44520 RSTCAUSE No Description 0x94 read-only n 0x0 0x0 AVDDBOD LEBOD1 Reset 10 1 read-only DECBOD LVBOD Reset 9 1 read-only DVDDBOD HVBOD Reset 7 1 read-only DVDDLEBOD LEBOD Reset 8 1 read-only EM4 EM4 Wakeup Reset 2 1 read-only IOVDD0BOD LEBOD2 Reset 11 1 read-only LOCKUP M33 Core Lockup Reset 5 1 read-only PIN Pin Reset 1 1 read-only POR Power On Reset 0 1 read-only SELOCKUP SE Lockup Reset 15 1 read-only SESYSREQ SE System Reset 14 1 read-only SETAMPER SE Tamper event Reset 13 1 read-only SYSREQ M33 Core Sys Reset 6 1 read-only WDOG0 Watchdog 0 Reset 3 1 read-only WDOG1 Watchdog 1 Reset 4 1 read-only RSTCTRL No Description 0x90 -1 read-write n 0x0 0x0 AVDDBODRMODE Enable AVDD BOD reset 6 1 read-write DISABLED Reset Request is block 0 ENABLED The entire device is reset except some EMU registers 1 DECBODRMODE Enable DECBOD reset 10 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset 1 IOVDD0BODRMODE Enable VDDIO0 BOD reset 7 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 LOCKUPRMODE Enable M33 Lockup reset 3 1 read-write DISABLED Reset Request is Block 0 ENABLED The entire device is reset except some EMU registers 1 SELOCKUPRMODE Enable SE Lockup reset 15 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SESYSRMODE Enable SE System reset 14 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SYSRMODE Enable M33 System reset 2 1 read-write DISABLED Reset request is blocked 0 ENABLED Device is reset except some EMU registers 1 WDOG0RMODE Enable WDOG0 reset 0 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 WDOG1RMODE Enable WDOG1 reset 1 1 read-write DISABLED Reset request is blocked 0 ENABLED The entire device is reset except some EMU registers 1 SEIEN No Description 0xAC read-write n 0x0 0x0 TEMP Temperature Interrupt enable 29 1 read-write TEMPHIGH Temperature high Interrupt enable 31 1 read-write TEMPLOW Temperature low Interrupt enable 30 1 read-write SEIF No Description 0xA8 read-write n 0x0 0x0 TEMP Temperature Interrupt flag 29 1 read-write TEMPHIGH Temperature low Interrupt flag 31 1 read-write TEMPLOW Temperature Interrupt flag 30 1 read-write STATUS No Description 0x84 -1 read-only n 0x0 0x0 EM2ENTERED EM2 entered 14 1 read-only EM4IORET EM4 IO retention status 12 1 read-only FIRSTTEMPDONE First Temp done 1 1 read-only LOCK Lock status 0 1 read-only UNLOCKED All EMU lockable registers are unlocked. 0 LOCKED All EMU lockable registers are locked. 1 RACACTIVE RAC active 10 1 read-only TEMPACTIVE Temp active 2 1 read-only TEMP No Description 0x88 read-only n 0x0 0x0 TEMP Temperature measured 2 9 read-only TEMPLSB Temperature measured decimal part 0 2 read-only TEMPLIMITS No Description 0x78 -1 read-write n 0x0 0x0 TEMPHIGH Temp High limit 16 9 read-write TEMPLOW Temp Low limit 0 9 read-write FRC_NS FRC_NS Registers FRC_NS 0x0 0x0 0x1000 registers n FRC_PRI 33 FRC 34 ADDRFILTCTRL No Description 0x14 read-write n 0x0 0x0 ADDRESS Address 8 8 read-write BRDCST00EN Broadcast Address 0x00 Enable 1 1 read-write BRDCSTFFEN Broadcast Address 0xFF Enable 2 1 read-write EN Address Filter Enable 0 1 read-write AUTOCG No Description 0xA8 read-write n 0x0 0x0 AUTOCGEN Automatic clock gate enable 0 16 read-write AUXDATA No Description 0x88 write-only n 0x0 0x0 AUXDATA Auxiliary sniffer data output 0 9 write-only BLOCKRAMADDR No Description 0x40 read-write n 0x0 0x0 BLOCKRAMADDR Block decoding RAM address 2 17 read-write BUFFERMODE No Description 0x78 read-write n 0x0 0x0 RXBUFFERMODE Receive Buffer Mode 1 2 read-write BUFC The Frame Controller write data to the Buffer Controller (BUFC) in receive mode. 0 REGISTER The Frame Controller does not write data to the Buffer Controller in receive mode. Instead, data must be read from the DATABUFFER register when the RXWORD interrupt flag is set. 1 DISABLE The Frame Controller will not output demodulated data. This mode can, for instance, be used together with storing RAW frame data. 2 RXFRCBUFMUX RX FRC Buffer Mux 3 1 read-write TXBUFFERMODE Transmit Buffer Mode 0 1 read-write BUFC The Frame Controller fetches data from the Buffer Controller (BUFC) in transmit mode. 0 REGISTER The Frame Controller does not fetch data from the Buffer Controller in transmit mode. Instead, data must be written to the DATABUFFER register when the TXWORD interrupt flag is set. 1 CGCLKSTOP No Description 0xAC read-write n 0x0 0x0 FORCEOFF Force off 0 16 read-write CMD No Description 0x2C write-only n 0x0 0x0 BLOCKINIT Block coder initialize 10 1 write-only CONVINIT Convolutional coder initialize 9 1 write-only CONVRESUME Convolutional coder resume 4 1 write-only CONVTERMINATE Convolutional coder termination 5 1 write-only FRAMEDETRESUME FRAMEDET resume 1 1 write-only INTERLEAVECNTCLEAR Interleaver counter clear 8 1 write-only INTERLEAVEINIT Interleaver initialization 7 1 write-only INTERLEAVEREADRESUME Interleaver read resume 3 1 write-only INTERLEAVEWRITERESUME Interleaver write resume 2 1 write-only RXABORT RX Abort 0 1 write-only RXRAWUNBLOCK Clear RXRAWBLOCKED status flag 12 1 write-only STATEINIT FRC State initialize 11 1 write-only TXSUBFRAMERESUME TX subframe resume 6 1 write-only CONVGENERATOR No Description 0x5C read-write n 0x0 0x0 GENERATOR0 Output 0 Generator Polynomial 0 7 read-write GENERATOR1 Output 1 Generator Polynomial 8 7 read-write NONSYSTEMATIC Non systematic recursive code 17 1 read-write X0 The recursive code is systematic 0 X1 The recursive code is not systematic 1 RECURSIVE Convolutional encoding 16 1 read-write X0 Non-recursive convolutional coding is used 0 X1 Recursive convolutional coding is used 1 CONVRAMADDR No Description 0x44 read-write n 0x0 0x0 CONVRAMADDR Convolutional decoding RAM address 2 17 read-write CTRL No Description 0x48 -1 read-write n 0x0 0x0 BITORDER Data Bit Order. 2 1 read-write LSBFIRST Least Significant bit in each word is sent/received first. 0 MSBFIRST Most Significant bit in each word is sent/received first. 1 BITSPERWORD Bits Per Word, for first word in a frame 8 3 read-write PRBSTEST Pseudo-Random Bit Sequence Testmode 17 1 read-write RANDOMTX Random TX Mode 0 1 read-write RATESELECT MODEM rate select 11 2 read-write RXFCDMODE RX Frame Control Descriptor Mode 6 2 read-write FCDMODE0 FCD2 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames 1 FCDMODE2 Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD2 / FCD3 for each complete frame 3 SEQHANDSHAKE Sequencer data handshake 16 1 read-write X0 The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data. 0 X1 The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set. 1 TXFCDMODE TX Frame Control Descriptor Mode 4 2 read-write FCDMODE0 FCD0 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames 1 FCDMODE2 Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD0 / FCD1 for each complete frame 3 TXPREFETCH Transmit prefetch data 13 1 read-write X0 The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases. 0 X1 The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set). 1 UARTMODE Data Uart Mode 1 1 read-write DATABUFFER No Description 0x18 read-write n 0x0 0x0 DATABUFFER Frame Controller data buffer 0 8 read-write DFLCTRL No Description 0xC read-write n 0x0 0x0 DFLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DFLBITS Length field number of bits 12 4 read-write DFLINCLUDECRC Length field includes CRC values or not 20 1 read-write X0 The CRC values are not included in the frame length 0 X1 The CRC values are included in the frame length 1 DFLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DFLOFFSET Length Field Offset Value 8 4 read-write DFLSHIFT Dynamic Frame Length bitshift 4 3 read-write MINLENGTH Minimum decoded length 16 4 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FCD0 No Description 0xB4 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD1 No Description 0xB8 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD2 No Description 0xBC -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD3 No Description 0xC0 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FECCTRL No Description 0x3C read-write n 0x0 0x0 BLOCKWHITEMODE Block Coder Whitener Mode 0 3 read-write DIRECT The input data is passed directly to the output without any other operations. 0 WHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every bit period. 1 BYTEWHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every byte period, recommended only for compatibility purposes. 2 INTERLEAVEDWHITE0 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. 3 INTERLEAVEDWHITE1 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. The first 16 (if INTERLEAVEWIDTH is 0) or 32 (if INTERLEAVEWIDTH is 1) RF symbols are not whitened or de-whitened. 4 BLOCKCODEINSERT Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will insert parity bits between the bit stream provided from the transmit buffer. In receive mode, the block decoder will remove parity bits and they will not further be provided to the receive buffer. 5 BLOCKCODEREPLACE Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will replace bits provided by the transmit buffer with parity bits. In receive mode, the block decoder will output both data bits and parity bits to the receive buffer. 6 BLOCKLOOKUP A lookup table is used to implement table lookup block coding in TX, and table lookup block decoding in RX. 7 CONVBUSLOCK Convolutional decoding bus lock 17 1 read-write CONVDECODEMODE Convolutional decoding mode setting. 6 1 read-write SOFT Use soft decision convolutional decoding, recommended in most cases. 0 HARD Use hard decision convolutional decoding. 1 CONVHARDERROR Enable convolutional decoding hard error 21 1 read-write X0 Convolutional hard error decoding is disabled. 0 X1 Convolutional hard error decoding is enabled. 1 CONVINV Convolutional code symbol inversion 8 2 read-write CONVMODE Convolutional Encoder / Decoder mode. 4 2 read-write DISABLE Convolutional encoding / decoding is disabled 0 CONVOLUTIONAL Normal convolutional encoding / decoding is enabled 1 REPEAT Repeat-mode convolutional encoding / decoding is enabled 2 CONVSUBFRAMETERMINATE Enable trellis termination for subframes 18 1 read-write X0 Trellis termination is applied at the end of the frame. 0 X1 Trellis termination is applied at the end of each subframe and at the end of the frame. 1 CONVTRACEBACKDISABLE Convolutional traceback disabling 7 1 read-write X0 Traceback history is enabled, and convolutional decoding will use RAM to store state information. In receive mode, output from convolutional decoding will be generated after the traceback history has reached a certain level. 0 X1 Traceback history is disabled, and convolutional decoding will not use RAM to store state information. No trellis termination sequence will be automatically appended to the transmit data. In receive mode, output from convolutional decoding will be generated after every state transition. This will not provide any convolutional decoding gain, but can be used to decode very simple codes without using any RAM memory. 1 FORCE2FSK Force use of 2-FSK 20 1 read-write INTERLEAVEFIRSTINDEX 4-bit index of the first interleaver 12 4 read-write INTERLEAVEMODE Interleaver mode. 10 2 read-write DISABLE Interleaving is disabled 0 ENABLE Interleaving is enabled 1 RXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive mode. This may, for instance, be used for receiver pause functionality. 2 RXTXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive and transmit mode. This may, for instance, be used for receiver and transmitter pause functionality. 3 INTERLEAVEWIDTH Interleave symbol width. 16 1 read-write ONE Each interleaver element consists of one RF symbol 0 TWO Each interleaver element consists of two RF symbols 1 SINGLEBLOCK Single block code per frame 19 1 read-write IEN No Description 0x6C read-write n 0x0 0x0 ADDRERROR Receive address error enable 12 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write BUSERROR Bus error enable 13 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXDONE TX Done Interrupt Enable 0 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write IF No Description 0x68 read-write n 0x0 0x0 ADDRERROR Receive address error event 12 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write BUSERROR A bus error event occurred 13 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXDONE TX Done Interrupt Flag 0 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write INTELEMENT0 No Description 0x100 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT1 No Description 0x104 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT10 No Description 0x128 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT11 No Description 0x12C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT12 No Description 0x130 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT13 No Description 0x134 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT14 No Description 0x138 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT15 No Description 0x13C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT2 No Description 0x108 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT3 No Description 0x10C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT4 No Description 0x110 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT5 No Description 0x114 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT6 No Description 0x118 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT7 No Description 0x11C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT8 No Description 0x120 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT9 No Description 0x124 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENTNEXT No Description 0x9C read-only n 0x0 0x0 INTELEMENTNEXT Interleaver element value 0 8 read-only INTREADPOINT No Description 0xA4 read-write n 0x0 0x0 INTREADPOINT Interleaver buffer read pointer 0 5 read-write INTWRITEPOINT No Description 0xA0 read-write n 0x0 0x0 INTWRITEPOINT Interleaver buffer write pointer 0 5 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LIKELYCONVSTATE No Description 0x98 read-only n 0x0 0x0 LIKELYCONVSTATE Most likely convolutional decoder state 0 6 read-only MAXLENGTH No Description 0x10 -1 read-write n 0x0 0x0 INILENGTH Initial Frame Length Value 12 4 read-write MAXLENGTH Max Frame Length Value 0 12 read-write MIRRORIF No Description 0x70 read-write n 0x0 0x0 ADDRERROR Receive address error event 9 1 read-only BLOCKERROR Block Error Interrupt Flag 7 1 read-only BUSERROR A bus error event occurred 10 1 read-only CONVPAUSED Convolutional coder pause event active 16 1 read-only FRAMEDETPAUSED Frame detected pause event active 12 1 read-only FRAMEERROR Frame Error Interrupt Flag 6 1 read-only IFMIRRORCLEAR Clear bit for the FRC IF MIRROR Register 17 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 14 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 13 1 read-only RXABORTED RX Aborted Interrupt Flag 5 1 read-only RXDONE RX Done Interrupt Flag 4 1 read-only RXOF Receive Overflow Interrupt Flag 8 1 read-only SNIFFOF Data sniffer overflow 11 1 read-only TXABORTED Transmit Aborted Interrupt Flag 2 1 read-only TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-only TXDONE TX Done Interrupt Flag 0 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 15 1 read-only TXUF Transmit Underflow Interrupt Flag 3 1 read-only PAUSECTRL No Description 0x64 read-write n 0x0 0x0 CONVPAUSECNT Convolutional decoder pause setting 5 6 read-write FRAMEDETPAUSEEN Frame detect pause enable 0 1 read-write INTERLEAVEREADPAUSECNT Interleaver read pause count 16 5 read-write INTERLEAVEREADPAUSEEN Interleaver read pause enable 3 1 read-write INTERLEAVEWRITEPAUSECNT Interleaver write pause count 11 5 read-write RXINTERLEAVEWRITEPAUSEEN Receive interleaver write pause enable 2 1 read-write TXINTERLEAVEWRITEPAUSEEN Transmit interleaver write pause enable 1 1 read-write TXSUBFRAMEPAUSEEN Transmit subframe pause enable 4 1 read-write PAUSEDATA No Description 0x94 read-only n 0x0 0x0 PAUSEDATA Receiver pause data register 0 32 read-only PUNCTCTRL No Description 0x60 -1 read-write n 0x0 0x0 PUNCT0 Puncturing Matrix Row for Output 0 0 7 read-write PUNCT1 Puncturing Matrix Row for Output 1 8 7 read-write RAMBASEADDR No Description 0xB0 -1 read-write n 0x0 0x0 RAMBASEADDR RAM BASE ADDR 12 20 read-write RAWCTRL No Description 0x8C read-write n 0x0 0x0 DEMODRAWDATAMUX Raw data mux control 13 1 read-write DEMODRAWDATASEL RAW data is selected using modem register DEMODRAWDATASEL. 0 DEMODRAWDATASEL2 RAW data is selected using modem register DEMODRAWDATASEL2. 1 RXRAWMODE Receiver raw data mode 2 3 read-write DISABLE RAW receive mode is disabled 0 SINGLEITEM RAW receive mode is enabled, fetching a single item which is stored in the RXRAWDATA register. A new item is fetched when the RXRAWBLOCKED flag is cleared. In this mode, the flag is cleared automatically when RXRAWDATA is read. 1 SINGLEBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 2 SINGLEBUFFERFRAME This mode is identical to the SINGLEBUFFER mode, except that the FRC will treat the end of the filled buffer as the end of a frame reception (i.e. also trigger the RXDONE interrupt and signal to the RAC that frame reception is complete.) 3 REPEATBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 4 RXRAWRANDOM Receive raw data random number generator 5 1 read-write RXRAWTRIGGER Receiver raw data trigger setting 7 1 read-write IMMEDIATE RAW data storage is triggered immediately when demodulator is enabled. 0 PRS RAW data storage is triggered by the selected RXRAWPRSSEL PRS channel. 1 TXRAWMODE Transmitter raw data mode 0 2 read-write DISABLE RAW transmit mode is disabled 0 SINGLEBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) once before transmit is completed. 1 REPEATBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) repeatedly until the transmitter is disabled. 2 RXCTRL No Description 0x4C read-write n 0x0 0x0 ACCEPTBLOCKERRORS Accept Block Decoding Errors. 2 1 read-write REJECT Frame reception will be stopped when a block decoding error is found. 0 ACCEPT Frame reception will continue even in the case of a block decoding error. 1 ACCEPTCRCERRORS Accept CRC Errors. 1 1 read-write REJECT Frames with one or more detected CRC errors will be cleared from the receiver buffer. 0 ACCEPT Frames will always be written to the receive buffer, regardless of CRC errors. 1 BUFCLEAR Buffer Clear 4 1 read-write BUFRESTOREFRAMEERROR Buffer restore on frame error 5 1 read-write BUFRESTORERXABORTED Buffer restore on RXABORTED 6 1 read-write RXFRAMEENDAHEADBYTES RX frame almost end of packet timing 7 4 read-write STORECRC Store CRC value. 0 1 read-write TRACKABFRAME Track Aborted RX Frame 3 1 read-write X0 When a frame abort is triggered, the frame reception is immediately aborted, the RXABORTED interrupt flag is set, and the receiver may start searching for a new frame. 0 X1 When a frame abort is triggered, the receiver is still enabled for the duration of the frame (as defined by the frame length), but no data output is generated. Only when the complete frame is received, the RXABORTED interrupt flag is set and a new frame reception may begin. This mode may, for instance, be used to avoid finding a new FRAMEDET event inside the payload data of a discarded frame. 1 RXRAWDATA No Description 0x90 read-only n 0x0 0x0 RXRAWDATA Receiver RAW data register 0 32 read-only SCNT No Description 0x58 read-only n 0x0 0x0 SCNT Sub-Frame Counter Value 0 8 read-only SNIFFCTRL No Description 0x84 -1 read-write n 0x0 0x0 SNIFFAUXDATA Enable sniffing of auxiliary data 7 1 read-write SNIFFBITS Data sniff data bits 2 1 read-write EIGHT Each sniffer output word contains 8 data bits 0 NINE Each sniffer output word contains 9 data bits 1 SNIFFBR Sniffer baudrate setting 8 8 read-write SNIFFMODE Data Sniff Mode 0 2 read-write OFF FRC Packet Sniffer mode is disabled 0 UART UART encoded data is transmitted on the DOUT pin. 1 SPI SPI data is transmitted on the DOUT pin and a data clock is output to the DCLK pin. 2 SNIFFRSSI Enable sniffing of RSSI 5 1 read-write SNIFFRXDATA Enable sniffing of received data. 3 1 read-write SNIFFSTATE Enable sniffing of state information 6 1 read-write SNIFFSYNCWORD Sniffer baudrate setting 17 1 read-write SNIFFTXDATA Enable sniffing of transmitted data. 4 1 read-write STATUS No Description 0x8 read-only n 0x0 0x0 ACTIVERXFCD Active Receive Frame Descriptor 6 1 read-only FCD2 FCD2 is active 0 FCD3 FCD3 is active 1 ACTIVETXFCD Active Transmit Frame Descriptor 5 1 read-only FCD0 FCD0 is active 0 FCD1 FCD1 is active 1 CONVPAUSED Convolutional coder pause event active 13 1 read-only DEMODERROR Demod Error in RX 19 1 read-only FRAMEDETPAUSED Frame detected pause event active 17 1 read-only FRAMELENGTHERROR Frame Length Error for RX and TX 18 1 read-only FRAMEOK Frame valid 9 1 read-only INTERLEAVEREADPAUSED Interleaver read pause event active 15 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 16 1 read-only RXABORTINPROGRESS Receive aborted in progress status flag 10 1 read-only RXRAWBLOCKED Receiver raw trigger block is active 8 1 read-only RXWORD Receive Word Flag 12 1 read-only SNIFFDCOUNT Sniffer data count 0 5 read-only SNIFFDFRAME Sniffer data frame active status 7 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 14 1 read-only TXWORD Transmit Word Flag 11 1 read-only TRAILRXDATA No Description 0x54 read-write n 0x0 0x0 CRCOK Append CRC OK Indicator 1 1 read-write PROTIMERCC0BASE PROTIMER Capture Compare channel 0 Base 2 1 read-write PROTIMERCC0WRAPH PROTIMER Capture Compare channel 0 WrapH 4 1 read-write PROTIMERCC0WRAPL PROTIMER Capture Compare channel 0 WrapL 3 1 read-write RSSI Append RSSI 0 1 read-write RTCSTAMP RTCC Time Stamp 5 1 read-write TRAILTXDATACTRL No Description 0x50 read-write n 0x0 0x0 TRAILTXDATA Trailing Data value 0 8 read-write TRAILTXDATACNT Trailing data bit count 8 3 read-write TRAILTXDATAFORCE Force trailing TX data insertion 11 1 read-write X0 Trailing data in transmit is only applied in order to fill up an integer number of block coding and interleaver buffers. If block coding and interleaving is not used, no trailing data is transmitted. 0 X1 The number of bits defined by TRAILTXDATACNT is always appended to the transmit data, in addition to the necessary bits to fill up an integer number of block coding and interleaver buffers. 1 WCNT No Description 0x1C read-only n 0x0 0x0 WCNT Word Counter Value 0 12 read-only WCNTCMP0 No Description 0x20 read-write n 0x0 0x0 FRAMELENGTH Word Counter Frame Length Value 0 12 read-write WCNTCMP1 No Description 0x24 read-write n 0x0 0x0 LENGTHFIELDLOC Length field location 0 12 read-write WCNTCMP2 No Description 0x28 read-write n 0x0 0x0 ADDRFIELDLOC Address field location 0 12 read-write WHITECTRL No Description 0x30 read-write n 0x0 0x0 BLOCKERRORCORRECT Block Errors Correction enable 12 1 read-write X0 Block decoding errors are not corrected, only the BLOCKERR interrupt is set on detection. 0 X1 Block decoding errors are attempted corrected by memory lookup tables. The BLOCKERR interrupt is also set on error detection. 1 FEEDBACKSEL LFSR Feedback selector 0 5 read-write BIT0 Select bit 0 as feedback 0 BIT1 Select bit 1 as feedback 1 BIT10 Select bit 10 as feedback 10 BIT11 Select bit 11 as feedback 11 BIT12 Select bit 12 as feedback 12 BIT13 Select bit 13 as feedback 13 BIT14 Select bit 14 as feedback 14 BIT15 Select bit 15 as feedback 15 INPUT Select data input as feedback 16 ZERO Select zero as feedback 17 ONE Select one as feedback 18 TXLASTWORD In transmit mode, the feedback is one during the last transmit word and zero otherwise. In receive mode, the feedback is always zero. 19 BIT2 Select bit 2 as feedback 2 BIT3 Select bit 3 as feedback 3 BIT4 Select bit 4 as feedback 4 BIT5 Select bit 5 as feedback 5 BIT6 Select bit 6 as feedback 6 BIT7 Select bit 7 as feedback 7 BIT8 Select bit 8 as feedback 8 BIT9 Select bit 9 as feedback 9 SHROUTPUTSEL Shift Register Output Selector 8 4 read-write XORFEEDBACK LFSR Feedback XOR setting 5 2 read-write DIRECT The signal defined by FEEDBACKSEL is used directly as Feedback. 0 XOR The signal defined by FEEDBACKSEL is XOR'ed with bit 15, and the result is used as Feedback 1 ZERO Feedback is set to 0 2 WHITEINIT No Description 0x38 read-write n 0x0 0x0 WHITEINIT Whitener Initial Value 0 16 read-write WHITEPOLY No Description 0x34 read-write n 0x0 0x0 POLY Whitener Polynomial 0 16 read-write FRC_S FRC_S Registers FRC_S 0x0 0x0 0x1000 registers n FRC_PRI 33 FRC 34 ADDRFILTCTRL No Description 0x14 read-write n 0x0 0x0 ADDRESS Address 8 8 read-write BRDCST00EN Broadcast Address 0x00 Enable 1 1 read-write BRDCSTFFEN Broadcast Address 0xFF Enable 2 1 read-write EN Address Filter Enable 0 1 read-write AUTOCG No Description 0xA8 read-write n 0x0 0x0 AUTOCGEN Automatic clock gate enable 0 16 read-write AUXDATA No Description 0x88 write-only n 0x0 0x0 AUXDATA Auxiliary sniffer data output 0 9 write-only BLOCKRAMADDR No Description 0x40 read-write n 0x0 0x0 BLOCKRAMADDR Block decoding RAM address 2 17 read-write BUFFERMODE No Description 0x78 read-write n 0x0 0x0 RXBUFFERMODE Receive Buffer Mode 1 2 read-write BUFC The Frame Controller write data to the Buffer Controller (BUFC) in receive mode. 0 REGISTER The Frame Controller does not write data to the Buffer Controller in receive mode. Instead, data must be read from the DATABUFFER register when the RXWORD interrupt flag is set. 1 DISABLE The Frame Controller will not output demodulated data. This mode can, for instance, be used together with storing RAW frame data. 2 RXFRCBUFMUX RX FRC Buffer Mux 3 1 read-write TXBUFFERMODE Transmit Buffer Mode 0 1 read-write BUFC The Frame Controller fetches data from the Buffer Controller (BUFC) in transmit mode. 0 REGISTER The Frame Controller does not fetch data from the Buffer Controller in transmit mode. Instead, data must be written to the DATABUFFER register when the TXWORD interrupt flag is set. 1 CGCLKSTOP No Description 0xAC read-write n 0x0 0x0 FORCEOFF Force off 0 16 read-write CMD No Description 0x2C write-only n 0x0 0x0 BLOCKINIT Block coder initialize 10 1 write-only CONVINIT Convolutional coder initialize 9 1 write-only CONVRESUME Convolutional coder resume 4 1 write-only CONVTERMINATE Convolutional coder termination 5 1 write-only FRAMEDETRESUME FRAMEDET resume 1 1 write-only INTERLEAVECNTCLEAR Interleaver counter clear 8 1 write-only INTERLEAVEINIT Interleaver initialization 7 1 write-only INTERLEAVEREADRESUME Interleaver read resume 3 1 write-only INTERLEAVEWRITERESUME Interleaver write resume 2 1 write-only RXABORT RX Abort 0 1 write-only RXRAWUNBLOCK Clear RXRAWBLOCKED status flag 12 1 write-only STATEINIT FRC State initialize 11 1 write-only TXSUBFRAMERESUME TX subframe resume 6 1 write-only CONVGENERATOR No Description 0x5C read-write n 0x0 0x0 GENERATOR0 Output 0 Generator Polynomial 0 7 read-write GENERATOR1 Output 1 Generator Polynomial 8 7 read-write NONSYSTEMATIC Non systematic recursive code 17 1 read-write X0 The recursive code is systematic 0 X1 The recursive code is not systematic 1 RECURSIVE Convolutional encoding 16 1 read-write X0 Non-recursive convolutional coding is used 0 X1 Recursive convolutional coding is used 1 CONVRAMADDR No Description 0x44 read-write n 0x0 0x0 CONVRAMADDR Convolutional decoding RAM address 2 17 read-write CTRL No Description 0x48 -1 read-write n 0x0 0x0 BITORDER Data Bit Order. 2 1 read-write LSBFIRST Least Significant bit in each word is sent/received first. 0 MSBFIRST Most Significant bit in each word is sent/received first. 1 BITSPERWORD Bits Per Word, for first word in a frame 8 3 read-write PRBSTEST Pseudo-Random Bit Sequence Testmode 17 1 read-write RANDOMTX Random TX Mode 0 1 read-write RATESELECT MODEM rate select 11 2 read-write RXFCDMODE RX Frame Control Descriptor Mode 6 2 read-write FCDMODE0 FCD2 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames 1 FCDMODE2 Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD2 / FCD3 for each complete frame 3 SEQHANDSHAKE Sequencer data handshake 16 1 read-write X0 The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data. 0 X1 The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set. 1 TXFCDMODE TX Frame Control Descriptor Mode 4 2 read-write FCDMODE0 FCD0 is reloaded when SCNT reaches 0 0 FCDMODE1 Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames 1 FCDMODE2 Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames 2 FCDMODE3 Use alternating FCD0 / FCD1 for each complete frame 3 TXPREFETCH Transmit prefetch data 13 1 read-write X0 The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases. 0 X1 The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set). 1 UARTMODE Data Uart Mode 1 1 read-write DATABUFFER No Description 0x18 read-write n 0x0 0x0 DATABUFFER Frame Controller data buffer 0 8 read-write DFLCTRL No Description 0xC read-write n 0x0 0x0 DFLBITORDER Dynamic Frame Length Bit order 3 1 read-write NORMAL Bit ordering is defined by the BITORDER field 0 REVERSE Bit ordering is reversed, compared to what is defined by the BITORDER field 1 DFLBITS Length field number of bits 12 4 read-write DFLINCLUDECRC Length field includes CRC values or not 20 1 read-write X0 The CRC values are not included in the frame length 0 X1 The CRC values are included in the frame length 1 DFLMODE Dynamic Frame Length Mode 0 3 read-write DISABLE Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field 0 SINGLEBYTE Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field 1 SINGLEBYTEMSB Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field 2 DUALBYTELSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first 3 DUALBYTEMSBFIRST Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first 4 INFINITE Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations. 5 BLOCKERROR In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found. 6 DFLOFFSET Length Field Offset Value 8 4 read-write DFLSHIFT Dynamic Frame Length bitshift 4 3 read-write MINLENGTH Minimum decoded length 16 4 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FCD0 No Description 0xB4 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD1 No Description 0xB8 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD2 No Description 0xBC -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FCD3 No Description 0xC0 -1 read-write n 0x0 0x0 ADDTRAILTXDATA Add trailing TX data in this subframe 15 1 read-write BUFFER Buffer to Access 8 2 read-write CALCCRC Calculate CRC 11 1 read-write EXCLUDESUBFRAMEWCNT Exclude subframe from WCNT 16 1 read-write INCLUDECRC Include CRC 10 1 read-write SKIPCRC Skip First Words in CRC Calculation 12 2 read-write SKIPWHITE Skip data whitening in this subframe 14 1 read-write WORDS No of Words in sub-frame 0 8 read-write FECCTRL No Description 0x3C read-write n 0x0 0x0 BLOCKWHITEMODE Block Coder Whitener Mode 0 3 read-write DIRECT The input data is passed directly to the output without any other operations. 0 WHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every bit period. 1 BYTEWHITE Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every byte period, recommended only for compatibility purposes. 2 INTERLEAVEDWHITE0 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. 3 INTERLEAVEDWHITE1 Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. The first 16 (if INTERLEAVEWIDTH is 0) or 32 (if INTERLEAVEWIDTH is 1) RF symbols are not whitened or de-whitened. 4 BLOCKCODEINSERT Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will insert parity bits between the bit stream provided from the transmit buffer. In receive mode, the block decoder will remove parity bits and they will not further be provided to the receive buffer. 5 BLOCKCODEREPLACE Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will replace bits provided by the transmit buffer with parity bits. In receive mode, the block decoder will output both data bits and parity bits to the receive buffer. 6 BLOCKLOOKUP A lookup table is used to implement table lookup block coding in TX, and table lookup block decoding in RX. 7 CONVBUSLOCK Convolutional decoding bus lock 17 1 read-write CONVDECODEMODE Convolutional decoding mode setting. 6 1 read-write SOFT Use soft decision convolutional decoding, recommended in most cases. 0 HARD Use hard decision convolutional decoding. 1 CONVHARDERROR Enable convolutional decoding hard error 21 1 read-write X0 Convolutional hard error decoding is disabled. 0 X1 Convolutional hard error decoding is enabled. 1 CONVINV Convolutional code symbol inversion 8 2 read-write CONVMODE Convolutional Encoder / Decoder mode. 4 2 read-write DISABLE Convolutional encoding / decoding is disabled 0 CONVOLUTIONAL Normal convolutional encoding / decoding is enabled 1 REPEAT Repeat-mode convolutional encoding / decoding is enabled 2 CONVSUBFRAMETERMINATE Enable trellis termination for subframes 18 1 read-write X0 Trellis termination is applied at the end of the frame. 0 X1 Trellis termination is applied at the end of each subframe and at the end of the frame. 1 CONVTRACEBACKDISABLE Convolutional traceback disabling 7 1 read-write X0 Traceback history is enabled, and convolutional decoding will use RAM to store state information. In receive mode, output from convolutional decoding will be generated after the traceback history has reached a certain level. 0 X1 Traceback history is disabled, and convolutional decoding will not use RAM to store state information. No trellis termination sequence will be automatically appended to the transmit data. In receive mode, output from convolutional decoding will be generated after every state transition. This will not provide any convolutional decoding gain, but can be used to decode very simple codes without using any RAM memory. 1 FORCE2FSK Force use of 2-FSK 20 1 read-write INTERLEAVEFIRSTINDEX 4-bit index of the first interleaver 12 4 read-write INTERLEAVEMODE Interleaver mode. 10 2 read-write DISABLE Interleaving is disabled 0 ENABLE Interleaving is enabled 1 RXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive mode. This may, for instance, be used for receiver pause functionality. 2 RXTXBUFFER No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive and transmit mode. This may, for instance, be used for receiver and transmitter pause functionality. 3 INTERLEAVEWIDTH Interleave symbol width. 16 1 read-write ONE Each interleaver element consists of one RF symbol 0 TWO Each interleaver element consists of two RF symbols 1 SINGLEBLOCK Single block code per frame 19 1 read-write IEN No Description 0x6C read-write n 0x0 0x0 ADDRERROR Receive address error enable 12 1 read-write BLOCKERROR Block Error Interrupt Enable 7 1 read-write BUSERROR Bus error enable 13 1 read-write CONVPAUSED Convolutional coder pause event enable 28 1 read-write FRAMEDETPAUSED Frame detected pause event enable 24 1 read-write FRAMEERROR Frame Error Interrupt Enable 6 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event enable 26 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event enable 25 1 read-write RXABORTED RX Aborted Interrupt Enable 5 1 read-write RXDONE RX Done Interrupt Enable 4 1 read-write RXOF Receive Overflow Interrupt Enable 8 1 read-write RXRAWEVENT Receiver raw data enable 14 1 read-write RXWORD Receive Word Interrupt Enable 29 1 read-write SNIFFOF Data sniffer overflow enable 16 1 read-write TXABORTED Transmit Aborted Interrupt Enable 2 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Enable 1 1 read-write TXDONE TX Done Interrupt Enable 0 1 read-write TXRAWEVENT Transmit raw data enable 15 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event enable 27 1 read-write TXUF Transmit Underflow Interrupt Enable 3 1 read-write TXWORD Transmit Word Interrupt Enable 30 1 read-write WCNTCMP0 Word Counter Compare 0 Enable 9 1 read-write WCNTCMP1 Word Counter Compare 1 Enable 10 1 read-write WCNTCMP2 Word Counter Compare 2 Enable 11 1 read-write IF No Description 0x68 read-write n 0x0 0x0 ADDRERROR Receive address error event 12 1 read-write BLOCKERROR Block Error Interrupt Flag 7 1 read-write BUSERROR A bus error event occurred 13 1 read-write CONVPAUSED Convolutional coder pause event active 28 1 read-write FRAMEDETPAUSED Frame detected pause event active 24 1 read-write FRAMEERROR Frame Error Interrupt Flag 6 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 26 1 read-write INTERLEAVEWRITEPAUSED Interleaver write pause event active 25 1 read-write RXABORTED RX Aborted Interrupt Flag 5 1 read-write RXDONE RX Done Interrupt Flag 4 1 read-write RXOF Receive Overflow Interrupt Flag 8 1 read-write RXRAWEVENT Receiver raw data event 14 1 read-write RXWORD Receive Word Interrupt Flag 29 1 read-write SNIFFOF Data sniffer overflow 16 1 read-write TXABORTED Transmit Aborted Interrupt Flag 2 1 read-write TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-write TXDONE TX Done Interrupt Flag 0 1 read-write TXRAWEVENT Transmit raw data event 15 1 read-write TXSUBFRAMEPAUSED Transmit subframe pause event active 27 1 read-write TXUF Transmit Underflow Interrupt Flag 3 1 read-write TXWORD Transmit Word Interrupt Flag 30 1 read-write WCNTCMP0 Word Counter Compare 0 Event 9 1 read-write WCNTCMP1 Word Counter Compare 1 Event 10 1 read-write WCNTCMP2 Word Counter Compare 2 Event 11 1 read-write INTELEMENT0 No Description 0x100 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT1 No Description 0x104 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT10 No Description 0x128 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT11 No Description 0x12C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT12 No Description 0x130 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT13 No Description 0x134 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT14 No Description 0x138 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT15 No Description 0x13C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT2 No Description 0x108 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT3 No Description 0x10C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT4 No Description 0x110 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT5 No Description 0x114 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT6 No Description 0x118 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT7 No Description 0x11C read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT8 No Description 0x120 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENT9 No Description 0x124 read-only n 0x0 0x0 INTELEMENT Interleaver element data 0 8 read-only INTELEMENTNEXT No Description 0x9C read-only n 0x0 0x0 INTELEMENTNEXT Interleaver element value 0 8 read-only INTREADPOINT No Description 0xA4 read-write n 0x0 0x0 INTREADPOINT Interleaver buffer read pointer 0 5 read-write INTWRITEPOINT No Description 0xA0 read-write n 0x0 0x0 INTWRITEPOINT Interleaver buffer write pointer 0 5 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LIKELYCONVSTATE No Description 0x98 read-only n 0x0 0x0 LIKELYCONVSTATE Most likely convolutional decoder state 0 6 read-only MAXLENGTH No Description 0x10 -1 read-write n 0x0 0x0 INILENGTH Initial Frame Length Value 12 4 read-write MAXLENGTH Max Frame Length Value 0 12 read-write MIRRORIF No Description 0x70 read-write n 0x0 0x0 ADDRERROR Receive address error event 9 1 read-only BLOCKERROR Block Error Interrupt Flag 7 1 read-only BUSERROR A bus error event occurred 10 1 read-only CONVPAUSED Convolutional coder pause event active 16 1 read-only FRAMEDETPAUSED Frame detected pause event active 12 1 read-only FRAMEERROR Frame Error Interrupt Flag 6 1 read-only IFMIRRORCLEAR Clear bit for the FRC IF MIRROR Register 17 1 read-write INTERLEAVEREADPAUSED Interleaver read pause event active 14 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 13 1 read-only RXABORTED RX Aborted Interrupt Flag 5 1 read-only RXDONE RX Done Interrupt Flag 4 1 read-only RXOF Receive Overflow Interrupt Flag 8 1 read-only SNIFFOF Data sniffer overflow 11 1 read-only TXABORTED Transmit Aborted Interrupt Flag 2 1 read-only TXAFTERFRAMEDONE TX after frame Done Interrupt Flag 1 1 read-only TXDONE TX Done Interrupt Flag 0 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 15 1 read-only TXUF Transmit Underflow Interrupt Flag 3 1 read-only PAUSECTRL No Description 0x64 read-write n 0x0 0x0 CONVPAUSECNT Convolutional decoder pause setting 5 6 read-write FRAMEDETPAUSEEN Frame detect pause enable 0 1 read-write INTERLEAVEREADPAUSECNT Interleaver read pause count 16 5 read-write INTERLEAVEREADPAUSEEN Interleaver read pause enable 3 1 read-write INTERLEAVEWRITEPAUSECNT Interleaver write pause count 11 5 read-write RXINTERLEAVEWRITEPAUSEEN Receive interleaver write pause enable 2 1 read-write TXINTERLEAVEWRITEPAUSEEN Transmit interleaver write pause enable 1 1 read-write TXSUBFRAMEPAUSEEN Transmit subframe pause enable 4 1 read-write PAUSEDATA No Description 0x94 read-only n 0x0 0x0 PAUSEDATA Receiver pause data register 0 32 read-only PUNCTCTRL No Description 0x60 -1 read-write n 0x0 0x0 PUNCT0 Puncturing Matrix Row for Output 0 0 7 read-write PUNCT1 Puncturing Matrix Row for Output 1 8 7 read-write RAMBASEADDR No Description 0xB0 -1 read-write n 0x0 0x0 RAMBASEADDR RAM BASE ADDR 12 20 read-write RAWCTRL No Description 0x8C read-write n 0x0 0x0 DEMODRAWDATAMUX Raw data mux control 13 1 read-write DEMODRAWDATASEL RAW data is selected using modem register DEMODRAWDATASEL. 0 DEMODRAWDATASEL2 RAW data is selected using modem register DEMODRAWDATASEL2. 1 RXRAWMODE Receiver raw data mode 2 3 read-write DISABLE RAW receive mode is disabled 0 SINGLEITEM RAW receive mode is enabled, fetching a single item which is stored in the RXRAWDATA register. A new item is fetched when the RXRAWBLOCKED flag is cleared. In this mode, the flag is cleared automatically when RXRAWDATA is read. 1 SINGLEBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 2 SINGLEBUFFERFRAME This mode is identical to the SINGLEBUFFER mode, except that the FRC will treat the end of the filled buffer as the end of a frame reception (i.e. also trigger the RXDONE interrupt and signal to the RAC that frame reception is complete.) 3 REPEATBUFFER RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception. 4 RXRAWRANDOM Receive raw data random number generator 5 1 read-write RXRAWTRIGGER Receiver raw data trigger setting 7 1 read-write IMMEDIATE RAW data storage is triggered immediately when demodulator is enabled. 0 PRS RAW data storage is triggered by the selected RXRAWPRSSEL PRS channel. 1 TXRAWMODE Transmitter raw data mode 0 2 read-write DISABLE RAW transmit mode is disabled 0 SINGLEBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) once before transmit is completed. 1 REPEATBUFFER RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) repeatedly until the transmitter is disabled. 2 RXCTRL No Description 0x4C read-write n 0x0 0x0 ACCEPTBLOCKERRORS Accept Block Decoding Errors. 2 1 read-write REJECT Frame reception will be stopped when a block decoding error is found. 0 ACCEPT Frame reception will continue even in the case of a block decoding error. 1 ACCEPTCRCERRORS Accept CRC Errors. 1 1 read-write REJECT Frames with one or more detected CRC errors will be cleared from the receiver buffer. 0 ACCEPT Frames will always be written to the receive buffer, regardless of CRC errors. 1 BUFCLEAR Buffer Clear 4 1 read-write BUFRESTOREFRAMEERROR Buffer restore on frame error 5 1 read-write BUFRESTORERXABORTED Buffer restore on RXABORTED 6 1 read-write RXFRAMEENDAHEADBYTES RX frame almost end of packet timing 7 4 read-write STORECRC Store CRC value. 0 1 read-write TRACKABFRAME Track Aborted RX Frame 3 1 read-write X0 When a frame abort is triggered, the frame reception is immediately aborted, the RXABORTED interrupt flag is set, and the receiver may start searching for a new frame. 0 X1 When a frame abort is triggered, the receiver is still enabled for the duration of the frame (as defined by the frame length), but no data output is generated. Only when the complete frame is received, the RXABORTED interrupt flag is set and a new frame reception may begin. This mode may, for instance, be used to avoid finding a new FRAMEDET event inside the payload data of a discarded frame. 1 RXRAWDATA No Description 0x90 read-only n 0x0 0x0 RXRAWDATA Receiver RAW data register 0 32 read-only SCNT No Description 0x58 read-only n 0x0 0x0 SCNT Sub-Frame Counter Value 0 8 read-only SNIFFCTRL No Description 0x84 -1 read-write n 0x0 0x0 SNIFFAUXDATA Enable sniffing of auxiliary data 7 1 read-write SNIFFBITS Data sniff data bits 2 1 read-write EIGHT Each sniffer output word contains 8 data bits 0 NINE Each sniffer output word contains 9 data bits 1 SNIFFBR Sniffer baudrate setting 8 8 read-write SNIFFMODE Data Sniff Mode 0 2 read-write OFF FRC Packet Sniffer mode is disabled 0 UART UART encoded data is transmitted on the DOUT pin. 1 SPI SPI data is transmitted on the DOUT pin and a data clock is output to the DCLK pin. 2 SNIFFRSSI Enable sniffing of RSSI 5 1 read-write SNIFFRXDATA Enable sniffing of received data. 3 1 read-write SNIFFSTATE Enable sniffing of state information 6 1 read-write SNIFFSYNCWORD Sniffer baudrate setting 17 1 read-write SNIFFTXDATA Enable sniffing of transmitted data. 4 1 read-write STATUS No Description 0x8 read-only n 0x0 0x0 ACTIVERXFCD Active Receive Frame Descriptor 6 1 read-only FCD2 FCD2 is active 0 FCD3 FCD3 is active 1 ACTIVETXFCD Active Transmit Frame Descriptor 5 1 read-only FCD0 FCD0 is active 0 FCD1 FCD1 is active 1 CONVPAUSED Convolutional coder pause event active 13 1 read-only DEMODERROR Demod Error in RX 19 1 read-only FRAMEDETPAUSED Frame detected pause event active 17 1 read-only FRAMELENGTHERROR Frame Length Error for RX and TX 18 1 read-only FRAMEOK Frame valid 9 1 read-only INTERLEAVEREADPAUSED Interleaver read pause event active 15 1 read-only INTERLEAVEWRITEPAUSED Interleaver write pause event active 16 1 read-only RXABORTINPROGRESS Receive aborted in progress status flag 10 1 read-only RXRAWBLOCKED Receiver raw trigger block is active 8 1 read-only RXWORD Receive Word Flag 12 1 read-only SNIFFDCOUNT Sniffer data count 0 5 read-only SNIFFDFRAME Sniffer data frame active status 7 1 read-only TXSUBFRAMEPAUSED Transmit subframe pause event active 14 1 read-only TXWORD Transmit Word Flag 11 1 read-only TRAILRXDATA No Description 0x54 read-write n 0x0 0x0 CRCOK Append CRC OK Indicator 1 1 read-write PROTIMERCC0BASE PROTIMER Capture Compare channel 0 Base 2 1 read-write PROTIMERCC0WRAPH PROTIMER Capture Compare channel 0 WrapH 4 1 read-write PROTIMERCC0WRAPL PROTIMER Capture Compare channel 0 WrapL 3 1 read-write RSSI Append RSSI 0 1 read-write RTCSTAMP RTCC Time Stamp 5 1 read-write TRAILTXDATACTRL No Description 0x50 read-write n 0x0 0x0 TRAILTXDATA Trailing Data value 0 8 read-write TRAILTXDATACNT Trailing data bit count 8 3 read-write TRAILTXDATAFORCE Force trailing TX data insertion 11 1 read-write X0 Trailing data in transmit is only applied in order to fill up an integer number of block coding and interleaver buffers. If block coding and interleaving is not used, no trailing data is transmitted. 0 X1 The number of bits defined by TRAILTXDATACNT is always appended to the transmit data, in addition to the necessary bits to fill up an integer number of block coding and interleaver buffers. 1 WCNT No Description 0x1C read-only n 0x0 0x0 WCNT Word Counter Value 0 12 read-only WCNTCMP0 No Description 0x20 read-write n 0x0 0x0 FRAMELENGTH Word Counter Frame Length Value 0 12 read-write WCNTCMP1 No Description 0x24 read-write n 0x0 0x0 LENGTHFIELDLOC Length field location 0 12 read-write WCNTCMP2 No Description 0x28 read-write n 0x0 0x0 ADDRFIELDLOC Address field location 0 12 read-write WHITECTRL No Description 0x30 read-write n 0x0 0x0 BLOCKERRORCORRECT Block Errors Correction enable 12 1 read-write X0 Block decoding errors are not corrected, only the BLOCKERR interrupt is set on detection. 0 X1 Block decoding errors are attempted corrected by memory lookup tables. The BLOCKERR interrupt is also set on error detection. 1 FEEDBACKSEL LFSR Feedback selector 0 5 read-write BIT0 Select bit 0 as feedback 0 BIT1 Select bit 1 as feedback 1 BIT10 Select bit 10 as feedback 10 BIT11 Select bit 11 as feedback 11 BIT12 Select bit 12 as feedback 12 BIT13 Select bit 13 as feedback 13 BIT14 Select bit 14 as feedback 14 BIT15 Select bit 15 as feedback 15 INPUT Select data input as feedback 16 ZERO Select zero as feedback 17 ONE Select one as feedback 18 TXLASTWORD In transmit mode, the feedback is one during the last transmit word and zero otherwise. In receive mode, the feedback is always zero. 19 BIT2 Select bit 2 as feedback 2 BIT3 Select bit 3 as feedback 3 BIT4 Select bit 4 as feedback 4 BIT5 Select bit 5 as feedback 5 BIT6 Select bit 6 as feedback 6 BIT7 Select bit 7 as feedback 7 BIT8 Select bit 8 as feedback 8 BIT9 Select bit 9 as feedback 9 SHROUTPUTSEL Shift Register Output Selector 8 4 read-write XORFEEDBACK LFSR Feedback XOR setting 5 2 read-write DIRECT The signal defined by FEEDBACKSEL is used directly as Feedback. 0 XOR The signal defined by FEEDBACKSEL is XOR'ed with bit 15, and the result is used as Feedback 1 ZERO Feedback is set to 0 2 WHITEINIT No Description 0x38 read-write n 0x0 0x0 WHITEINIT Whitener Initial Value 0 16 read-write WHITEPOLY No Description 0x34 read-write n 0x0 0x0 POLY Whitener Polynomial 0 16 read-write FSRCO_NS FSRCO_NS Registers FSRCO_NS 0x0 0x0 0x1000 registers n IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only FSRCO_S FSRCO_S Registers FSRCO_S 0x0 0x0 0x1000 registers n IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only GPCRC_NS GPCRC_NS Registers GPCRC_NS 0x0 0x0 0x1000 registers n CMD No Description 0xC write-only n 0x0 0x0 INIT Initialization Enable 0 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOINIT Auto Init Enable 13 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEMODE Byte Mode Enable 8 1 read-write BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3 For 16-bit: 0, 0, B0, B1 1 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 DATA No Description 0x24 read-only n 0x0 0x0 DATA CRC Data Register 0 32 read-only DATABYTEREV No Description 0x2C read-only n 0x0 0x0 DATABYTEREV Data Byte Reverse Value 0 32 read-only DATAREV No Description 0x28 read-only n 0x0 0x0 DATAREV Data Reverse Value 0 32 read-only EN No Description 0x4 read-write n 0x0 0x0 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 INIT No Description 0x10 read-write n 0x0 0x0 INIT CRC Initialization Value 0 32 read-write INPUTDATA No Description 0x18 write-only n 0x0 0x0 INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATABYTE No Description 0x20 write-only n 0x0 0x0 INPUTDATABYTE Input Data for 8-bit 0 8 write-only INPUTDATAHWORD No Description 0x1C write-only n 0x0 0x0 INPUTDATAHWORD Input Data for 16-bit 0 16 write-only IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only POLY No Description 0x14 read-write n 0x0 0x0 POLY CRC Polynomial Value 0 16 read-write GPCRC_S GPCRC_S Registers GPCRC_S 0x0 0x0 0x1000 registers n CMD No Description 0xC write-only n 0x0 0x0 INIT Initialization Enable 0 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOINIT Auto Init Enable 13 1 read-write BITREVERSE Byte-level Bit Reverse Enable 9 1 read-write NORMAL No reverse 0 REVERSED Reverse bit order in each byte 1 BYTEMODE Byte Mode Enable 8 1 read-write BYTEREVERSE Byte Reverse Mode 10 1 read-write NORMAL No reverse: B3, B2, B1, B0 0 REVERSED Reverse byte order. For 32-bit: B0, B1, B2, B3 For 16-bit: 0, 0, B0, B1 1 POLYSEL Polynomial Select 4 1 read-write CRC32 CRC-32 (0x04C11DB7) polynomial selected 0 CRC16 16-bit CRC programmable polynomial selected 1 DATA No Description 0x24 read-only n 0x0 0x0 DATA CRC Data Register 0 32 read-only DATABYTEREV No Description 0x2C read-only n 0x0 0x0 DATABYTEREV Data Byte Reverse Value 0 32 read-only DATAREV No Description 0x28 read-only n 0x0 0x0 DATAREV Data Reverse Value 0 32 read-only EN No Description 0x4 read-write n 0x0 0x0 EN CRC Enable 0 1 read-write DISABLE Disable CRC function. Reordering functions are still available. Only BITREVERSE and BYTEREVERSE bits are configurable in this mode. 0 ENABLE Writes to INPUTDATA registers will result in CRC operations. 1 INIT No Description 0x10 read-write n 0x0 0x0 INIT CRC Initialization Value 0 32 read-write INPUTDATA No Description 0x18 write-only n 0x0 0x0 INPUTDATA Input Data for 32-bit 0 32 write-only INPUTDATABYTE No Description 0x20 write-only n 0x0 0x0 INPUTDATABYTE Input Data for 8-bit 0 8 write-only INPUTDATAHWORD No Description 0x1C write-only n 0x0 0x0 INPUTDATAHWORD Input Data for 16-bit 0 16 write-only IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only POLY No Description 0x14 read-write n 0x0 0x0 POLY CRC Polynomial Value 0 16 read-write GPIO_NS GPIO_NS Registers GPIO_NS 0x0 0x0 0x1000 registers n GPIO_ODD 25 GPIO_EVEN 26 ABUSALLOC A Bus allocation 0x320 read-write n 0x0 0x0 AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DIAGA The bus is allocated to DIAGA 14 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DIAGA The bus is allocated to DIAGA 14 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 ACMP0_ACMPOUTROUTE No Description 0x454 read-write n 0x0 0x0 PIN ACMPOUT pin select register 16 4 read-write PORT ACMPOUT port select register 0 2 read-write ACMP0_ROUTEEN No Description 0x450 read-write n 0x0 0x0 ACMPOUTPEN ACMPOUT pin enable control bit 0 1 read-write ACMP1_ACMPOUTROUTE No Description 0x460 read-write n 0x0 0x0 PIN ACMPOUT pin select register 16 4 read-write PORT ACMPOUT port select register 0 2 read-write ACMP1_ROUTEEN No Description 0x45C read-write n 0x0 0x0 ACMPOUTPEN ACMPOUT pin enable control bit 0 1 read-write BBUSALLOC B Bus allocation 0x324 read-write n 0x0 0x0 BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDBUSALLOC CD Bus allocation 0x328 read-write n 0x0 0x0 CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 PMON The bus is allocated to Process Monitor 12 EFUSE The bus is allocated for EFUSE programming voltage 13 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 PMON The bus is allocated to Process Monitor 12 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CMU_CLKIN0ROUTE No Description 0x46C read-write n 0x0 0x0 PIN CLKIN0 pin select register 16 4 read-write PORT CLKIN0 port select register 0 2 read-write CMU_CLKOUT0ROUTE No Description 0x470 read-write n 0x0 0x0 PIN CLKOUT0 pin select register 16 4 read-write PORT CLKOUT0 port select register 0 2 read-write CMU_CLKOUT1ROUTE No Description 0x474 read-write n 0x0 0x0 PIN CLKOUT1 pin select register 16 4 read-write PORT CLKOUT1 port select register 0 2 read-write CMU_CLKOUT2ROUTE No Description 0x478 read-write n 0x0 0x0 PIN CLKOUT2 pin select register 16 4 read-write PORT CLKOUT2 port select register 0 2 read-write CMU_ROUTEEN No Description 0x468 read-write n 0x0 0x0 CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write DBGROUTEPEN No Description 0x440 -1 read-write n 0x0 0x0 SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write EM4WUEN No Description 0x42C read-write n 0x0 0x0 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write n 0x0 0x0 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write n 0x0 0x0 EXTIFALL EXT Int FALL 0 8 read-write EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write n 0x0 0x0 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPSELL External Interrupt Port Select Low 0x400 read-write n 0x0 0x0 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write n 0x0 0x0 EXTIRISE EXT Int Rise 0 8 read-write FRC_DCLKROUTE No Description 0x488 read-write n 0x0 0x0 PIN DCLK pin select register 16 4 read-write PORT DCLK port select register 0 2 read-write FRC_DFRAMEROUTE No Description 0x48C read-write n 0x0 0x0 PIN DFRAME pin select register 16 4 read-write PORT DFRAME port select register 0 2 read-write FRC_DOUTROUTE No Description 0x490 read-write n 0x0 0x0 PIN DOUT pin select register 16 4 read-write PORT DOUT port select register 0 2 read-write FRC_ROUTEEN No Description 0x484 read-write n 0x0 0x0 DCLKPEN DCLK pin enable control bit 0 1 read-write DFRAMEPEN DFRAME pin enable control bit 1 1 read-write DOUTPEN DOUT pin enable control bit 2 1 read-write GPIOLOCKSTATUS No Description 0x310 read-only n 0x0 0x0 LOCK GPIO LOCK Status 0 1 read-only UNLOCKED 0 LOCKED 1 I2C0_ROUTEEN No Description 0x498 read-write n 0x0 0x0 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE No Description 0x49C read-write n 0x0 0x0 PIN SCL pin select register 16 4 read-write PORT SCL port select register 0 2 read-write I2C0_SDAROUTE No Description 0x4A0 read-write n 0x0 0x0 PIN SDA pin select register 16 4 read-write PORT SDA port select register 0 2 read-write I2C1_ROUTEEN No Description 0x4A8 read-write n 0x0 0x0 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE No Description 0x4AC read-write n 0x0 0x0 PIN SCL pin select register 16 4 read-write PORT SCL port select register 0 2 read-write I2C1_SDAROUTE No Description 0x4B0 read-write n 0x0 0x0 PIN SDA pin select register 16 4 read-write PORT SDA port select register 0 2 read-write IEN Interrupt Enable 0x424 read-write n 0x0 0x0 EM4WUIEN EM4 Wake Up Interrupt En 16 16 read-write EXTIEN External Pin Enable 0 16 read-write IF Interrupt Flag 0x420 read-write n 0x0 0x0 EM4WU EM4 wake up 16 16 read-write EXT External Pin Flag 0 16 read-write LETIMER0_OUT0ROUTE No Description 0x4BC read-write n 0x0 0x0 PIN OUT0 pin select register 16 4 read-write PORT OUT0 port select register 0 2 read-write LETIMER0_OUT1ROUTE No Description 0x4C0 read-write n 0x0 0x0 PIN OUT1 pin select register 16 4 read-write PORT OUT1 port select register 0 2 read-write LETIMER0_ROUTEEN No Description 0x4B8 read-write n 0x0 0x0 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LOCK No Description 0x300 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 42292 MODEM_ANT0ROUTE No Description 0x4CC read-write n 0x0 0x0 PIN ANT0 pin select register 16 4 read-write PORT ANT0 port select register 0 2 read-write MODEM_ANT1ROUTE No Description 0x4D0 read-write n 0x0 0x0 PIN ANT1 pin select register 16 4 read-write PORT ANT1 port select register 0 2 read-write MODEM_DCLKROUTE No Description 0x4D4 read-write n 0x0 0x0 PIN DCLK pin select register 16 4 read-write PORT DCLK port select register 0 2 read-write MODEM_DINROUTE No Description 0x4D8 read-write n 0x0 0x0 PIN DIN pin select register 16 4 read-write PORT DIN port select register 0 2 read-write MODEM_DOUTROUTE No Description 0x4DC read-write n 0x0 0x0 PIN DOUT pin select register 16 4 read-write PORT DOUT port select register 0 2 read-write MODEM_ROUTEEN No Description 0x4C8 read-write n 0x0 0x0 ANT0PEN ANT0 pin enable control bit 0 1 read-write ANT1PEN ANT1 pin enable control bit 1 1 read-write DCLKPEN DCLK pin enable control bit 2 1 read-write DOUTPEN DOUT pin enable control bit 3 1 read-write PORTA_CTRL Port control 0x0 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTA_DIN data in 0x14 read-only n 0x0 0x0 DIN Data input 0 7 read-only PORTA_DOUT data out 0x10 read-write n 0x0 0x0 DOUT Data output 0 7 read-write PORTA_MODEL mode low 0x4 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTB_CTRL Port control 0x30 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTB_DIN data in 0x44 read-only n 0x0 0x0 DIN Data input 0 2 read-only PORTB_DOUT data out 0x40 read-write n 0x0 0x0 DOUT Data output 0 2 read-write PORTB_MODEL mode low 0x34 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTC_CTRL Port control 0x60 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTC_DIN data in 0x74 read-only n 0x0 0x0 DIN Data input 0 6 read-only PORTC_DOUT data out 0x70 read-write n 0x0 0x0 DOUT Data output 0 6 read-write PORTC_MODEL mode low 0x64 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTD_CTRL Port control 0x90 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTD_DIN data in 0xA4 read-only n 0x0 0x0 DIN Data input 0 5 read-only PORTD_DOUT data out 0xA0 read-write n 0x0 0x0 DOUT Data output 0 5 read-write PORTD_MODEL mode low 0x94 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PRS0_ASYNCH0ROUTE No Description 0x4E8 read-write n 0x0 0x0 PIN ASYNCH0 pin select register 16 4 read-write PORT ASYNCH0 port select register 0 2 read-write PRS0_ASYNCH10ROUTE No Description 0x510 read-write n 0x0 0x0 PIN ASYNCH10 pin select register 16 4 read-write PORT ASYNCH10 port select register 0 2 read-write PRS0_ASYNCH11ROUTE No Description 0x514 read-write n 0x0 0x0 PIN ASYNCH11 pin select register 16 4 read-write PORT ASYNCH11 port select register 0 2 read-write PRS0_ASYNCH1ROUTE No Description 0x4EC read-write n 0x0 0x0 PIN ASYNCH1 pin select register 16 4 read-write PORT ASYNCH1 port select register 0 2 read-write PRS0_ASYNCH2ROUTE No Description 0x4F0 read-write n 0x0 0x0 PIN ASYNCH2 pin select register 16 4 read-write PORT ASYNCH2 port select register 0 2 read-write PRS0_ASYNCH3ROUTE No Description 0x4F4 read-write n 0x0 0x0 PIN ASYNCH3 pin select register 16 4 read-write PORT ASYNCH3 port select register 0 2 read-write PRS0_ASYNCH4ROUTE No Description 0x4F8 read-write n 0x0 0x0 PIN ASYNCH4 pin select register 16 4 read-write PORT ASYNCH4 port select register 0 2 read-write PRS0_ASYNCH5ROUTE No Description 0x4FC read-write n 0x0 0x0 PIN ASYNCH5 pin select register 16 4 read-write PORT ASYNCH5 port select register 0 2 read-write PRS0_ASYNCH6ROUTE No Description 0x500 read-write n 0x0 0x0 PIN ASYNCH6 pin select register 16 4 read-write PORT ASYNCH6 port select register 0 2 read-write PRS0_ASYNCH7ROUTE No Description 0x504 read-write n 0x0 0x0 PIN ASYNCH7 pin select register 16 4 read-write PORT ASYNCH7 port select register 0 2 read-write PRS0_ASYNCH8ROUTE No Description 0x508 read-write n 0x0 0x0 PIN ASYNCH8 pin select register 16 4 read-write PORT ASYNCH8 port select register 0 2 read-write PRS0_ASYNCH9ROUTE No Description 0x50C read-write n 0x0 0x0 PIN ASYNCH9 pin select register 16 4 read-write PORT ASYNCH9 port select register 0 2 read-write PRS0_ROUTEEN No Description 0x4E4 read-write n 0x0 0x0 ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_SYNCH0ROUTE No Description 0x518 read-write n 0x0 0x0 PIN SYNCH0 pin select register 16 4 read-write PORT SYNCH0 port select register 0 2 read-write PRS0_SYNCH1ROUTE No Description 0x51C read-write n 0x0 0x0 PIN SYNCH1 pin select register 16 4 read-write PORT SYNCH1 port select register 0 2 read-write PRS0_SYNCH2ROUTE No Description 0x520 read-write n 0x0 0x0 PIN SYNCH2 pin select register 16 4 read-write PORT SYNCH2 port select register 0 2 read-write PRS0_SYNCH3ROUTE No Description 0x524 read-write n 0x0 0x0 PIN SYNCH3 pin select register 16 4 read-write PORT SYNCH3 port select register 0 2 read-write TIMER0_CC0ROUTE No Description 0x530 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER0_CC1ROUTE No Description 0x534 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER0_CC2ROUTE No Description 0x538 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER0_CDTI0ROUTE No Description 0x53C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER0_CDTI1ROUTE No Description 0x540 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER0_CDTI2ROUTE No Description 0x544 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER0_ROUTEEN No Description 0x52C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE No Description 0x550 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER1_CC1ROUTE No Description 0x554 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER1_CC2ROUTE No Description 0x558 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER1_CDTI0ROUTE No Description 0x55C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER1_CDTI1ROUTE No Description 0x560 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER1_CDTI2ROUTE No Description 0x564 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER1_ROUTEEN No Description 0x54C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE No Description 0x570 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER2_CC1ROUTE No Description 0x574 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER2_CC2ROUTE No Description 0x578 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER2_CDTI0ROUTE No Description 0x57C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER2_CDTI1ROUTE No Description 0x580 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER2_CDTI2ROUTE No Description 0x584 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER2_ROUTEEN No Description 0x56C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE No Description 0x590 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER3_CC1ROUTE No Description 0x594 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER3_CC2ROUTE No Description 0x598 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER3_CDTI0ROUTE No Description 0x59C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER3_CDTI1ROUTE No Description 0x5A0 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER3_CDTI2ROUTE No Description 0x5A4 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER3_ROUTEEN No Description 0x58C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TRACEROUTEPEN No Description 0x444 read-write n 0x0 0x0 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write USART0_CLKROUTE No Description 0x5C0 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART0_CSROUTE No Description 0x5B0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART0_CTSROUTE No Description 0x5B4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART0_ROUTEEN No Description 0x5AC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_RTSROUTE No Description 0x5B8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART0_RXROUTE No Description 0x5BC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART0_TXROUTE No Description 0x5C4 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write USART1_CLKROUTE No Description 0x5E0 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART1_CSROUTE No Description 0x5D0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART1_CTSROUTE No Description 0x5D4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART1_ROUTEEN No Description 0x5CC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_RTSROUTE No Description 0x5D8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART1_RXROUTE No Description 0x5DC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART1_TXROUTE No Description 0x5E4 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write USART2_CLKROUTE No Description 0x600 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART2_CSROUTE No Description 0x5F0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART2_CTSROUTE No Description 0x5F4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART2_ROUTEEN No Description 0x5EC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART2_RTSROUTE No Description 0x5F8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART2_RXROUTE No Description 0x5FC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART2_TXROUTE No Description 0x604 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write GPIO_S GPIO_S Registers GPIO_S 0x0 0x0 0x1000 registers n GPIO_ODD 25 GPIO_EVEN 26 ABUSALLOC A Bus allocation 0x320 read-write n 0x0 0x0 AEVEN0 A Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DIAGA The bus is allocated to DIAGA 14 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AEVEN1 A Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AODD0 A Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DIAGA The bus is allocated to DIAGA 14 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 AODD1 A Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 ACMP0_ACMPOUTROUTE No Description 0x454 read-write n 0x0 0x0 PIN ACMPOUT pin select register 16 4 read-write PORT ACMPOUT port select register 0 2 read-write ACMP0_ROUTEEN No Description 0x450 read-write n 0x0 0x0 ACMPOUTPEN ACMPOUT pin enable control bit 0 1 read-write ACMP1_ACMPOUTROUTE No Description 0x460 read-write n 0x0 0x0 PIN ACMPOUT pin select register 16 4 read-write PORT ACMPOUT port select register 0 2 read-write ACMP1_ROUTEEN No Description 0x45C read-write n 0x0 0x0 ACMPOUTPEN ACMPOUT pin enable control bit 0 1 read-write BBUSALLOC B Bus allocation 0x324 read-write n 0x0 0x0 BEVEN0 B Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BEVEN1 B Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BODD0 B Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 BODD1 B Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDBUSALLOC CD Bus allocation 0x328 read-write n 0x0 0x0 CDEVEN0 CD Bus Even 0 0 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 PMON The bus is allocated to Process Monitor 12 EFUSE The bus is allocated for EFUSE programming voltage 13 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDEVEN1 CD Bus Even 1 8 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDODD0 CD Bus Odd 0 16 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 PMON The bus is allocated to Process Monitor 12 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CDODD1 CD Bus Odd 1 24 4 read-write TRISTATE The bus is not allocated 0 ADC0 The bus is allocated to ADC0 1 DEBUG DEBUG mode, bus allocated to all clients 15 ACMP0 The bus is allocated to ACMP0 2 ACMP1 The bus is allocated to ACMP1 3 CMU_CLKIN0ROUTE No Description 0x46C read-write n 0x0 0x0 PIN CLKIN0 pin select register 16 4 read-write PORT CLKIN0 port select register 0 2 read-write CMU_CLKOUT0ROUTE No Description 0x470 read-write n 0x0 0x0 PIN CLKOUT0 pin select register 16 4 read-write PORT CLKOUT0 port select register 0 2 read-write CMU_CLKOUT1ROUTE No Description 0x474 read-write n 0x0 0x0 PIN CLKOUT1 pin select register 16 4 read-write PORT CLKOUT1 port select register 0 2 read-write CMU_CLKOUT2ROUTE No Description 0x478 read-write n 0x0 0x0 PIN CLKOUT2 pin select register 16 4 read-write PORT CLKOUT2 port select register 0 2 read-write CMU_ROUTEEN No Description 0x468 read-write n 0x0 0x0 CLKOUT0PEN CLKOUT0 pin enable control bit 0 1 read-write CLKOUT1PEN CLKOUT1 pin enable control bit 1 1 read-write CLKOUT2PEN CLKOUT2 pin enable control bit 2 1 read-write DBGROUTEPEN No Description 0x440 -1 read-write n 0x0 0x0 SWCLKTCKPEN Route Pin Enable 0 1 read-write SWDIOTMSPEN Route Location 0 1 1 read-write TDIPEN JTAG Test Debug Input Pin Enable 3 1 read-write TDOPEN JTAG Test Debug Output Pin Enable 2 1 read-write EM4WUEN No Description 0x42C read-write n 0x0 0x0 EM4WUEN EM4 wake up enable 16 12 read-write EM4WUPOL No Description 0x430 read-write n 0x0 0x0 EM4WUPOL EM4 Wake-Up Polarity 16 12 read-write EXTIFALL External Interrupt Falling Edge Trigger 0x414 read-write n 0x0 0x0 EXTIFALL EXT Int FALL 0 8 read-write EXTIPINSELL External Interrupt Pin Select Low 0x408 read-write n 0x0 0x0 EXTIPINSEL0 External Interrupt Pin select 0 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL1 External Interrupt Pin select 4 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL2 External Interrupt Pin select 8 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL3 External Interrupt Pin select 12 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL4 External Interrupt Pin select 16 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL5 External Interrupt Pin select 20 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL6 External Interrupt Pin select 24 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPINSEL7 External Interrupt Pin select 28 2 read-write OFFSET0 OFFSET=0 0 OFFSET1 OFFSET=1 1 OFFSET2 OFFSET=2 2 OFFSET3 OFFSET=3 3 EXTIPSELL External Interrupt Port Select Low 0x400 read-write n 0x0 0x0 EXTIPSEL0 External Interrupt Port Select 0 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL1 External Interrupt Port Select 4 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL2 External Interrupt Port Select 8 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL3 External Interrupt Port Select 12 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL4 External Interrupt Port Select 16 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL5 External Interrupt Port Select 20 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL6 External Interrupt Port Select 24 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIPSEL7 External Interrupt Port Select 28 2 read-write PORTA Port A group selected 0 PORTB Port B group selected 1 PORTC Port C group selected 2 PORTD Port D group selected 3 EXTIRISE External Interrupt Rising Edge Trigger 0x410 read-write n 0x0 0x0 EXTIRISE EXT Int Rise 0 8 read-write FRC_DCLKROUTE No Description 0x488 read-write n 0x0 0x0 PIN DCLK pin select register 16 4 read-write PORT DCLK port select register 0 2 read-write FRC_DFRAMEROUTE No Description 0x48C read-write n 0x0 0x0 PIN DFRAME pin select register 16 4 read-write PORT DFRAME port select register 0 2 read-write FRC_DOUTROUTE No Description 0x490 read-write n 0x0 0x0 PIN DOUT pin select register 16 4 read-write PORT DOUT port select register 0 2 read-write FRC_ROUTEEN No Description 0x484 read-write n 0x0 0x0 DCLKPEN DCLK pin enable control bit 0 1 read-write DFRAMEPEN DFRAME pin enable control bit 1 1 read-write DOUTPEN DOUT pin enable control bit 2 1 read-write GPIOLOCKSTATUS No Description 0x310 read-only n 0x0 0x0 LOCK GPIO LOCK Status 0 1 read-only UNLOCKED 0 LOCKED 1 I2C0_ROUTEEN No Description 0x498 read-write n 0x0 0x0 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C0_SCLROUTE No Description 0x49C read-write n 0x0 0x0 PIN SCL pin select register 16 4 read-write PORT SCL port select register 0 2 read-write I2C0_SDAROUTE No Description 0x4A0 read-write n 0x0 0x0 PIN SDA pin select register 16 4 read-write PORT SDA port select register 0 2 read-write I2C1_ROUTEEN No Description 0x4A8 read-write n 0x0 0x0 SCLPEN SCL pin enable control bit 0 1 read-write SDAPEN SDA pin enable control bit 1 1 read-write I2C1_SCLROUTE No Description 0x4AC read-write n 0x0 0x0 PIN SCL pin select register 16 4 read-write PORT SCL port select register 0 2 read-write I2C1_SDAROUTE No Description 0x4B0 read-write n 0x0 0x0 PIN SDA pin select register 16 4 read-write PORT SDA port select register 0 2 read-write IEN Interrupt Enable 0x424 read-write n 0x0 0x0 EM4WUIEN EM4 Wake Up Interrupt En 16 16 read-write EXTIEN External Pin Enable 0 16 read-write IF Interrupt Flag 0x420 read-write n 0x0 0x0 EM4WU EM4 wake up 16 16 read-write EXT External Pin Flag 0 16 read-write LETIMER0_OUT0ROUTE No Description 0x4BC read-write n 0x0 0x0 PIN OUT0 pin select register 16 4 read-write PORT OUT0 port select register 0 2 read-write LETIMER0_OUT1ROUTE No Description 0x4C0 read-write n 0x0 0x0 PIN OUT1 pin select register 16 4 read-write PORT OUT1 port select register 0 2 read-write LETIMER0_ROUTEEN No Description 0x4B8 read-write n 0x0 0x0 OUT0PEN OUT0 pin enable control bit 0 1 read-write OUT1PEN OUT1 pin enable control bit 1 1 read-write LOCK No Description 0x300 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 42292 MODEM_ANT0ROUTE No Description 0x4CC read-write n 0x0 0x0 PIN ANT0 pin select register 16 4 read-write PORT ANT0 port select register 0 2 read-write MODEM_ANT1ROUTE No Description 0x4D0 read-write n 0x0 0x0 PIN ANT1 pin select register 16 4 read-write PORT ANT1 port select register 0 2 read-write MODEM_DCLKROUTE No Description 0x4D4 read-write n 0x0 0x0 PIN DCLK pin select register 16 4 read-write PORT DCLK port select register 0 2 read-write MODEM_DINROUTE No Description 0x4D8 read-write n 0x0 0x0 PIN DIN pin select register 16 4 read-write PORT DIN port select register 0 2 read-write MODEM_DOUTROUTE No Description 0x4DC read-write n 0x0 0x0 PIN DOUT pin select register 16 4 read-write PORT DOUT port select register 0 2 read-write MODEM_ROUTEEN No Description 0x4C8 read-write n 0x0 0x0 ANT0PEN ANT0 pin enable control bit 0 1 read-write ANT1PEN ANT1 pin enable control bit 1 1 read-write DCLKPEN DCLK pin enable control bit 2 1 read-write DOUTPEN DOUT pin enable control bit 3 1 read-write PORTA_CTRL Port control 0x0 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTA_DIN data in 0x14 read-only n 0x0 0x0 DIN Data input 0 7 read-only PORTA_DOUT data out 0x10 read-write n 0x0 0x0 DOUT Data output 0 7 read-write PORTA_MODEL mode low 0x4 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE6 MODE n 24 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTB_CTRL Port control 0x30 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTB_DIN data in 0x44 read-only n 0x0 0x0 DIN Data input 0 2 read-only PORTB_DOUT data out 0x40 read-write n 0x0 0x0 DOUT Data output 0 2 read-write PORTB_MODEL mode low 0x34 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTC_CTRL Port control 0x60 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTC_DIN data in 0x74 read-only n 0x0 0x0 DIN Data input 0 6 read-only PORTC_DOUT data out 0x70 read-write n 0x0 0x0 DOUT Data output 0 6 read-write PORTC_MODEL mode low 0x64 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE5 MODE n 20 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PORTD_CTRL Port control 0x90 -1 read-write n 0x0 0x0 DINDIS Data In Disable 12 1 read-write DINDISALT Data In Disable Alt 28 1 read-write SLEWRATE Slew Rate 4 3 read-write SLEWRATEALT Slew Rate Alt 20 3 read-write PORTD_DIN data in 0xA4 read-only n 0x0 0x0 DIN Data input 0 5 read-only PORTD_DOUT data out 0xA0 read-write n 0x0 0x0 DOUT Data output 0 5 read-write PORTD_MODEL mode low 0x94 read-write n 0x0 0x0 MODE0 MODE n 0 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE1 MODE n 4 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE2 MODE n 8 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE3 MODE n 12 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 MODE4 MODE n 16 4 read-write DISABLED Input disabled. Pullup if DOUT is set. 0 INPUT Input enabled. Filter if DOUT is set. 1 WIREDANDPULLUP Open-drain output with pullup. 10 WIREDANDPULLUPFILTER Open-drain output with filter and pullup. 11 WIREDANDALT Open-drain output using alternate control. 12 WIREDANDALTFILTER Open-drain output using alternate control with filter. 13 WIREDANDALTPULLUP Open-drain output using alternate control with pullup. 14 WIREDANDALTPULLUPFILTER Open-drain output using alternate control with filter and pullup. 15 INPUTPULL Input enabled. DOUT determines pull direction. 2 INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. 3 PUSHPULL Push-pull output. 4 PUSHPULLALT Push-pull using alternate control. 5 WIREDOR Wired-or output. 6 WIREDORPULLDOWN Wired-or output with pull-down. 7 WIREDAND Open-drain output. 8 WIREDANDFILTER Open-drain output with filter. 9 PRS0_ASYNCH0ROUTE No Description 0x4E8 read-write n 0x0 0x0 PIN ASYNCH0 pin select register 16 4 read-write PORT ASYNCH0 port select register 0 2 read-write PRS0_ASYNCH10ROUTE No Description 0x510 read-write n 0x0 0x0 PIN ASYNCH10 pin select register 16 4 read-write PORT ASYNCH10 port select register 0 2 read-write PRS0_ASYNCH11ROUTE No Description 0x514 read-write n 0x0 0x0 PIN ASYNCH11 pin select register 16 4 read-write PORT ASYNCH11 port select register 0 2 read-write PRS0_ASYNCH1ROUTE No Description 0x4EC read-write n 0x0 0x0 PIN ASYNCH1 pin select register 16 4 read-write PORT ASYNCH1 port select register 0 2 read-write PRS0_ASYNCH2ROUTE No Description 0x4F0 read-write n 0x0 0x0 PIN ASYNCH2 pin select register 16 4 read-write PORT ASYNCH2 port select register 0 2 read-write PRS0_ASYNCH3ROUTE No Description 0x4F4 read-write n 0x0 0x0 PIN ASYNCH3 pin select register 16 4 read-write PORT ASYNCH3 port select register 0 2 read-write PRS0_ASYNCH4ROUTE No Description 0x4F8 read-write n 0x0 0x0 PIN ASYNCH4 pin select register 16 4 read-write PORT ASYNCH4 port select register 0 2 read-write PRS0_ASYNCH5ROUTE No Description 0x4FC read-write n 0x0 0x0 PIN ASYNCH5 pin select register 16 4 read-write PORT ASYNCH5 port select register 0 2 read-write PRS0_ASYNCH6ROUTE No Description 0x500 read-write n 0x0 0x0 PIN ASYNCH6 pin select register 16 4 read-write PORT ASYNCH6 port select register 0 2 read-write PRS0_ASYNCH7ROUTE No Description 0x504 read-write n 0x0 0x0 PIN ASYNCH7 pin select register 16 4 read-write PORT ASYNCH7 port select register 0 2 read-write PRS0_ASYNCH8ROUTE No Description 0x508 read-write n 0x0 0x0 PIN ASYNCH8 pin select register 16 4 read-write PORT ASYNCH8 port select register 0 2 read-write PRS0_ASYNCH9ROUTE No Description 0x50C read-write n 0x0 0x0 PIN ASYNCH9 pin select register 16 4 read-write PORT ASYNCH9 port select register 0 2 read-write PRS0_ROUTEEN No Description 0x4E4 read-write n 0x0 0x0 ASYNCH0PEN ASYNCH0 pin enable control bit 0 1 read-write ASYNCH10PEN ASYNCH10 pin enable control bit 10 1 read-write ASYNCH11PEN ASYNCH11 pin enable control bit 11 1 read-write ASYNCH1PEN ASYNCH1 pin enable control bit 1 1 read-write ASYNCH2PEN ASYNCH2 pin enable control bit 2 1 read-write ASYNCH3PEN ASYNCH3 pin enable control bit 3 1 read-write ASYNCH4PEN ASYNCH4 pin enable control bit 4 1 read-write ASYNCH5PEN ASYNCH5 pin enable control bit 5 1 read-write ASYNCH6PEN ASYNCH6 pin enable control bit 6 1 read-write ASYNCH7PEN ASYNCH7 pin enable control bit 7 1 read-write ASYNCH8PEN ASYNCH8 pin enable control bit 8 1 read-write ASYNCH9PEN ASYNCH9 pin enable control bit 9 1 read-write SYNCH0PEN SYNCH0 pin enable control bit 12 1 read-write SYNCH1PEN SYNCH1 pin enable control bit 13 1 read-write SYNCH2PEN SYNCH2 pin enable control bit 14 1 read-write SYNCH3PEN SYNCH3 pin enable control bit 15 1 read-write PRS0_SYNCH0ROUTE No Description 0x518 read-write n 0x0 0x0 PIN SYNCH0 pin select register 16 4 read-write PORT SYNCH0 port select register 0 2 read-write PRS0_SYNCH1ROUTE No Description 0x51C read-write n 0x0 0x0 PIN SYNCH1 pin select register 16 4 read-write PORT SYNCH1 port select register 0 2 read-write PRS0_SYNCH2ROUTE No Description 0x520 read-write n 0x0 0x0 PIN SYNCH2 pin select register 16 4 read-write PORT SYNCH2 port select register 0 2 read-write PRS0_SYNCH3ROUTE No Description 0x524 read-write n 0x0 0x0 PIN SYNCH3 pin select register 16 4 read-write PORT SYNCH3 port select register 0 2 read-write TIMER0_CC0ROUTE No Description 0x530 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER0_CC1ROUTE No Description 0x534 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER0_CC2ROUTE No Description 0x538 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER0_CDTI0ROUTE No Description 0x53C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER0_CDTI1ROUTE No Description 0x540 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER0_CDTI2ROUTE No Description 0x544 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER0_ROUTEEN No Description 0x52C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER1_CC0ROUTE No Description 0x550 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER1_CC1ROUTE No Description 0x554 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER1_CC2ROUTE No Description 0x558 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER1_CDTI0ROUTE No Description 0x55C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER1_CDTI1ROUTE No Description 0x560 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER1_CDTI2ROUTE No Description 0x564 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER1_ROUTEEN No Description 0x54C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER2_CC0ROUTE No Description 0x570 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER2_CC1ROUTE No Description 0x574 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER2_CC2ROUTE No Description 0x578 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER2_CDTI0ROUTE No Description 0x57C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER2_CDTI1ROUTE No Description 0x580 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER2_CDTI2ROUTE No Description 0x584 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER2_ROUTEEN No Description 0x56C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TIMER3_CC0ROUTE No Description 0x590 read-write n 0x0 0x0 PIN CC0 pin select register 16 4 read-write PORT CC0 port select register 0 2 read-write TIMER3_CC1ROUTE No Description 0x594 read-write n 0x0 0x0 PIN CC1 pin select register 16 4 read-write PORT CC1 port select register 0 2 read-write TIMER3_CC2ROUTE No Description 0x598 read-write n 0x0 0x0 PIN CC2 pin select register 16 4 read-write PORT CC2 port select register 0 2 read-write TIMER3_CDTI0ROUTE No Description 0x59C read-write n 0x0 0x0 PIN CCC0 pin select register 16 4 read-write PORT CCC0 port select register 0 2 read-write TIMER3_CDTI1ROUTE No Description 0x5A0 read-write n 0x0 0x0 PIN CCC1 pin select register 16 4 read-write PORT CCC1 port select register 0 2 read-write TIMER3_CDTI2ROUTE No Description 0x5A4 read-write n 0x0 0x0 PIN CCC2 pin select register 16 4 read-write PORT CCC2 port select register 0 2 read-write TIMER3_ROUTEEN No Description 0x58C read-write n 0x0 0x0 CC0PEN CC0 pin enable control bit 0 1 read-write CC1PEN CC1 pin enable control bit 1 1 read-write CC2PEN CC2 pin enable control bit 2 1 read-write CDTI0PEN CDTI0 pin enable control bit 3 1 read-write CDTI1PEN CDTI1 pin enable control bit 4 1 read-write CDTI2PEN CDTI2 pin enable control bit 5 1 read-write TRACEROUTEPEN No Description 0x444 read-write n 0x0 0x0 SWVPEN Serial Wire Viewer Output Pin Enable 0 1 read-write TRACECLKPEN Trace Clk Pin Enable 1 1 read-write TRACEDATA0PEN Trace Data0 Pin Enable 2 1 read-write USART0_CLKROUTE No Description 0x5C0 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART0_CSROUTE No Description 0x5B0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART0_CTSROUTE No Description 0x5B4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART0_ROUTEEN No Description 0x5AC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART0_RTSROUTE No Description 0x5B8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART0_RXROUTE No Description 0x5BC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART0_TXROUTE No Description 0x5C4 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write USART1_CLKROUTE No Description 0x5E0 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART1_CSROUTE No Description 0x5D0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART1_CTSROUTE No Description 0x5D4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART1_ROUTEEN No Description 0x5CC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART1_RTSROUTE No Description 0x5D8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART1_RXROUTE No Description 0x5DC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART1_TXROUTE No Description 0x5E4 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write USART2_CLKROUTE No Description 0x600 read-write n 0x0 0x0 PIN SCLK pin select register 16 4 read-write PORT SCLK port select register 0 2 read-write USART2_CSROUTE No Description 0x5F0 read-write n 0x0 0x0 PIN CS pin select register 16 4 read-write PORT CS port select register 0 2 read-write USART2_CTSROUTE No Description 0x5F4 read-write n 0x0 0x0 PIN CTS pin select register 16 4 read-write PORT CTS port select register 0 2 read-write USART2_ROUTEEN No Description 0x5EC read-write n 0x0 0x0 CLKPEN CLK pin enable control bit 3 1 read-write CSPEN CS pin enable control bit 0 1 read-write RTSPEN RTS pin enable control bit 1 1 read-write RXPEN RX pin enable control bit 2 1 read-write TXPEN TX pin enable control bit 4 1 read-write USART2_RTSROUTE No Description 0x5F8 read-write n 0x0 0x0 PIN RTS pin select register 16 4 read-write PORT RTS port select register 0 2 read-write USART2_RXROUTE No Description 0x5FC read-write n 0x0 0x0 PIN RX pin select register 16 4 read-write PORT RX port select register 0 2 read-write USART2_TXROUTE No Description 0x604 read-write n 0x0 0x0 PIN TX pin select register 16 4 read-write PORT TX port select register 0 2 read-write HFRCO0_NS HFRCO0_NS Registers HFRCO0_NS 0x0 0x0 0x1000 registers n HFRCO0 46 CAL No Description 0x8 -1 read-write n 0x0 0x0 CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPBIAS Comparator Bias Current 21 3 read-write CMPSEL Comparator Load Select 26 2 read-write FINETUNING Fine Tuning Value 8 6 read-write FREQRANGE Frequency Range 16 5 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write LDOHP LDO High Power Mode 15 1 read-write TUNING Tuning Value 0 7 read-write CTRL No Description 0x4 read-write n 0x0 0x0 DISONDEMAND Disable On-demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 RDY RDY Interrupt Enable 0 1 read-write IF No Description 0x10 read-write n 0x0 0x0 RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x1C -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK 33173 STATUS No Description 0xC read-only n 0x0 0x0 ENS Enable Status 16 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready 0 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only HFRCO0_S HFRCO0_S Registers HFRCO0_S 0x0 0x0 0x1000 registers n HFRCO0 46 CAL No Description 0x8 -1 read-write n 0x0 0x0 CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPBIAS Comparator Bias Current 21 3 read-write CMPSEL Comparator Load Select 26 2 read-write FINETUNING Fine Tuning Value 8 6 read-write FREQRANGE Frequency Range 16 5 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write LDOHP LDO High Power Mode 15 1 read-write TUNING Tuning Value 0 7 read-write CTRL No Description 0x4 read-write n 0x0 0x0 DISONDEMAND Disable On-demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 RDY RDY Interrupt Enable 0 1 read-write IF No Description 0x10 read-write n 0x0 0x0 RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x1C -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK 33173 STATUS No Description 0xC read-only n 0x0 0x0 ENS Enable Status 16 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready 0 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only HFRCOEM23_NS HFRCOEM23_NS Registers HFRCOEM23_NS 0x0 0x0 0x1000 registers n HFRCOEM23 47 CAL No Description 0x8 -1 read-write n 0x0 0x0 CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPBIAS Comparator Bias Current 21 3 read-write CMPSEL Comparator Load Select 26 2 read-write FINETUNING Fine Tuning Value 8 6 read-write FREQRANGE Frequency Range 16 5 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write LDOHP LDO High Power Mode 15 1 read-write TUNING Tuning Value 0 7 read-write CTRL No Description 0x4 read-write n 0x0 0x0 DISONDEMAND Disable On-demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 RDY RDY Interrupt Enable 0 1 read-write IF No Description 0x10 read-write n 0x0 0x0 RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x1C -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK 33173 STATUS No Description 0xC read-only n 0x0 0x0 ENS Enable Status 16 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready 0 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only HFRCOEM23_S HFRCOEM23_S Registers HFRCOEM23_S 0x0 0x0 0x1000 registers n HFRCOEM23 47 CAL No Description 0x8 -1 read-write n 0x0 0x0 CLKDIV Locally Divide HFRCO Clock Output 24 2 read-write DIV1 Divide by 1. 0 DIV2 Divide by 2. 1 DIV4 Divide by 4. 2 CMPBIAS Comparator Bias Current 21 3 read-write CMPSEL Comparator Load Select 26 2 read-write FINETUNING Fine Tuning Value 8 6 read-write FREQRANGE Frequency Range 16 5 read-write IREFTC Tempco Trim on Comparator Current 28 4 read-write LDOHP LDO High Power Mode 15 1 read-write TUNING Tuning Value 0 7 read-write CTRL No Description 0x4 read-write n 0x0 0x0 DISONDEMAND Disable On-demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN No Description 0x14 read-write n 0x0 0x0 RDY RDY Interrupt Enable 0 1 read-write IF No Description 0x10 read-write n 0x0 0x0 RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x1C -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK 33173 STATUS No Description 0xC read-only n 0x0 0x0 ENS Enable Status 16 1 read-only FREQBSY Frequency Updating Busy 1 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready 0 1 read-only SYNCBUSY Synchronization Busy 2 1 read-only HFXO0_NS HFXO0_NS Registers HFXO0_NS 0x0 0x0 0x1000 registers n HFXO00 45 CFG No Description 0x20 -1 read-write n 0x0 0x0 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE 0 ENABLE 1 CMD No Description 0x50 write-only n 0x0 0x0 COREBIASOPT Core Bias Optimizaton 0 1 write-only CTRL No Description 0x28 -1 read-write n 0x0 0x0 DISONDEMAND Disable On-demand Mode 1 1 read-write FORCEEN Force Enable 0 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 IEN No Description 0x74 read-write n 0x0 0x0 COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write RDY Ready Interrupt 0 1 read-write IF No Description 0x70 read-write n 0x0 0x0 COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write RDY Ready Interrupt 0 1 read-write IPVERSION No Description 0x0 -1 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x80 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 22542 STATUS No Description 0x58 read-only n 0x0 0x0 COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED 0 LOCKED 1 HWREQ Oscillator Requested by Hardware 17 1 read-only LOCK Configuration Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready Status 0 1 read-only XTALCFG No Description 0x10 -1 read-write n 0x0 0x0 COREBIASSTARTUP Startup Core Bias Current 6 6 read-write COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US 0 T20US 1 T333US 10 T416US 11 T833US 12 T1250US 13 T2083US 14 T3750US 15 T41US 2 T62US 3 T83US 4 T104US 5 T125US 6 T166US 7 T208US 8 T250US 9 TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US 0 T41US 1 T666US 10 T833US 11 T1666US 12 T2500US 13 T4166US 14 T7500US 15 T83US 2 T125US 3 T166US 4 T208US 5 T250US 6 T333US 7 T416US 8 T500US 9 XTALCTRL No Description 0x18 -1 read-write n 0x0 0x0 COREBIASANA Core Bias Current 0 8 read-write COREDGENANA Core Degeneration 26 2 read-write NONE 0 DGEN33 1 DGEN50 2 DGEN100 3 CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE 0 XI 1 XO 2 BOTH 3 CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write HFXO0_S HFXO0_S Registers HFXO0_S 0x0 0x0 0x1000 registers n HFXO00 45 CFG No Description 0x20 -1 read-write n 0x0 0x0 ENXIDCBIASANA Enable XI Internal DC Bias 2 1 read-write MODE Crystal Oscillator Mode 0 1 read-write XTAL crystal oscillator 0 EXTCLK external sinusoidal clock can be supplied on XI pin. 1 SQBUFSCHTRGANA Squaring Buffer Schmitt Trigger 3 1 read-write DISABLE 0 ENABLE 1 CMD No Description 0x50 write-only n 0x0 0x0 COREBIASOPT Core Bias Optimizaton 0 1 write-only CTRL No Description 0x28 -1 read-write n 0x0 0x0 DISONDEMAND Disable On-demand Mode 1 1 read-write FORCEEN Force Enable 0 1 read-write FORCEXI2GNDANA Force XI Pin to Ground 4 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 FORCEXO2GNDANA Force XO Pin to Ground 5 1 read-write DISABLE Disabled (not pulled) 0 ENABLE Enabled (pulled) 1 IEN No Description 0x74 read-write n 0x0 0x0 COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write RDY Ready Interrupt 0 1 read-write IF No Description 0x70 read-write n 0x0 0x0 COREBIASOPTERR Core Bias Optimization Error Interrupt 31 1 read-write COREBIASOPTRDY Core Bias Optimization Ready Interrupt 1 1 read-write DNSERR Did Not Start Error Interrupt 29 1 read-write RDY Ready Interrupt 0 1 read-write IPVERSION No Description 0x0 -1 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x80 -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK 22542 STATUS No Description 0x58 read-only n 0x0 0x0 COREBIASOPTRDY Core Bias Optimization Ready 1 1 read-only ENS Enabled Status 16 1 read-only FSMLOCK FSM Lock Status 30 1 read-only UNLOCKED 0 LOCKED 1 HWREQ Oscillator Requested by Hardware 17 1 read-only LOCK Configuration Lock Status 31 1 read-only UNLOCKED 0 LOCKED 1 RDY Ready Status 0 1 read-only XTALCFG No Description 0x10 -1 read-write n 0x0 0x0 COREBIASSTARTUP Startup Core Bias Current 6 6 read-write COREBIASSTARTUPI Intermediate Startup Core Bias Current 0 6 read-write CTUNEXISTARTUP Startup Tuning Capacitance on XI 12 4 read-write CTUNEXOSTARTUP Startup Tuning Capacitance on XO 16 4 read-write TIMEOUTCBLSB Core Bias LSB Change Timeout 24 4 read-write T8US 0 T20US 1 T333US 10 T416US 11 T833US 12 T1250US 13 T2083US 14 T3750US 15 T41US 2 T62US 3 T83US 4 T104US 5 T125US 6 T166US 7 T208US 8 T250US 9 TIMEOUTSTEADY Steady State Timeout 20 4 read-write T16US 0 T41US 1 T666US 10 T833US 11 T1666US 12 T2500US 13 T4166US 14 T7500US 15 T83US 2 T125US 3 T166US 4 T208US 5 T250US 6 T333US 7 T416US 8 T500US 9 XTALCTRL No Description 0x18 -1 read-write n 0x0 0x0 COREBIASANA Core Bias Current 0 8 read-write COREDGENANA Core Degeneration 26 2 read-write NONE 0 DGEN33 1 DGEN50 2 DGEN100 3 CTUNEFIXANA Fixed Tuning Capacitance 24 2 read-write NONE 0 XI 1 XO 2 BOTH 3 CTUNEXIANA Tuning Capacitance on XI 8 8 read-write CTUNEXOANA Tuning Capacitance on XO 16 8 read-write SKIPCOREBIASOPT Skip Core Bias Optimization 31 1 read-write I2C0_NS I2C0_NS Registers I2C0_NS 0x0 0x0 0x1000 registers n I2C0 27 CLKDIV No Description 0x18 read-write n 0x0 0x0 DIV Clock Divider 0 9 read-write CMD No Description 0xC write-only n 0x0 0x0 ABORT Abort transmission 5 1 write-only ACK Send ACK 2 1 write-only CLEARPC Clear Pending Commands 7 1 write-only CLEARTX Clear TX 6 1 write-only CONT Continue transmission 4 1 write-only NACK Send NACK 3 1 write-only START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The master automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a slave. 0 ENABLE The master automatically sends a STOP if a NACK is received from a slave. 1 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the slave address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 SLAVE Addressable as Slave 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 EN No Description 0x4 read-write n 0x0 0x0 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 IEN No Description 0x40 read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IF No Description 0x3C read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAP No Description 0x2C read-only n 0x0 0x0 RXDATAP RX Data Peek 0 8 read-only RXDOUBLE No Description 0x28 read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEP No Description 0x30 read-only n 0x0 0x0 RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only SADDR No Description 0x1C read-write n 0x0 0x0 ADDR Slave address 1 7 read-write SADDRMASK No Description 0x20 read-write n 0x0 0x0 SADDRMASK Slave Address Mask 1 7 read-write STATE No Description 0x10 -1 read-only n 0x0 0x0 BUSHOLD Bus Held 4 1 read-only BUSY Bus Busy 0 1 read-only MASTER Master 1 1 read-only NACKED Nack Received 3 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 TRANSMITTER Transmitter 2 1 read-only STATUS No Description 0x14 -1 read-only n 0x0 0x0 PABORT Pending abort 5 1 read-only PACK Pending ACK 2 1 read-only PCONT Pending continue 4 1 read-only PNACK Pending NACK 3 1 read-only PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBL TX Buffer Level 7 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only TXC TX Complete 6 1 read-only TXDATA No Description 0x34 write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x38 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only I2C0_S I2C0_S Registers I2C0_S 0x0 0x0 0x1000 registers n I2C0 27 CLKDIV No Description 0x18 read-write n 0x0 0x0 DIV Clock Divider 0 9 read-write CMD No Description 0xC write-only n 0x0 0x0 ABORT Abort transmission 5 1 write-only ACK Send ACK 2 1 write-only CLEARPC Clear Pending Commands 7 1 write-only CLEARTX Clear TX 6 1 write-only CONT Continue transmission 4 1 write-only NACK Send NACK 3 1 write-only START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The master automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a slave. 0 ENABLE The master automatically sends a STOP if a NACK is received from a slave. 1 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the slave address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 SLAVE Addressable as Slave 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 EN No Description 0x4 read-write n 0x0 0x0 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 IEN No Description 0x40 read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IF No Description 0x3C read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAP No Description 0x2C read-only n 0x0 0x0 RXDATAP RX Data Peek 0 8 read-only RXDOUBLE No Description 0x28 read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEP No Description 0x30 read-only n 0x0 0x0 RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only SADDR No Description 0x1C read-write n 0x0 0x0 ADDR Slave address 1 7 read-write SADDRMASK No Description 0x20 read-write n 0x0 0x0 SADDRMASK Slave Address Mask 1 7 read-write STATE No Description 0x10 -1 read-only n 0x0 0x0 BUSHOLD Bus Held 4 1 read-only BUSY Bus Busy 0 1 read-only MASTER Master 1 1 read-only NACKED Nack Received 3 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 TRANSMITTER Transmitter 2 1 read-only STATUS No Description 0x14 -1 read-only n 0x0 0x0 PABORT Pending abort 5 1 read-only PACK Pending ACK 2 1 read-only PCONT Pending continue 4 1 read-only PNACK Pending NACK 3 1 read-only PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBL TX Buffer Level 7 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only TXC TX Complete 6 1 read-only TXDATA No Description 0x34 write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x38 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only I2C1_NS I2C1_NS Registers I2C1_NS 0x0 0x0 0x1000 registers n I2C1 28 CLKDIV No Description 0x18 read-write n 0x0 0x0 DIV Clock Divider 0 9 read-write CMD No Description 0xC write-only n 0x0 0x0 ABORT Abort transmission 5 1 write-only ACK Send ACK 2 1 write-only CLEARPC Clear Pending Commands 7 1 write-only CLEARTX Clear TX 6 1 write-only CONT Continue transmission 4 1 write-only NACK Send NACK 3 1 write-only START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The master automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a slave. 0 ENABLE The master automatically sends a STOP if a NACK is received from a slave. 1 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the slave address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 SLAVE Addressable as Slave 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 EN No Description 0x4 read-write n 0x0 0x0 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 IEN No Description 0x40 read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IF No Description 0x3C read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAP No Description 0x2C read-only n 0x0 0x0 RXDATAP RX Data Peek 0 8 read-only RXDOUBLE No Description 0x28 read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEP No Description 0x30 read-only n 0x0 0x0 RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only SADDR No Description 0x1C read-write n 0x0 0x0 ADDR Slave address 1 7 read-write SADDRMASK No Description 0x20 read-write n 0x0 0x0 SADDRMASK Slave Address Mask 1 7 read-write STATE No Description 0x10 -1 read-only n 0x0 0x0 BUSHOLD Bus Held 4 1 read-only BUSY Bus Busy 0 1 read-only MASTER Master 1 1 read-only NACKED Nack Received 3 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 TRANSMITTER Transmitter 2 1 read-only STATUS No Description 0x14 -1 read-only n 0x0 0x0 PABORT Pending abort 5 1 read-only PACK Pending ACK 2 1 read-only PCONT Pending continue 4 1 read-only PNACK Pending NACK 3 1 read-only PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBL TX Buffer Level 7 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only TXC TX Complete 6 1 read-only TXDATA No Description 0x34 write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x38 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only I2C1_S I2C1_S Registers I2C1_S 0x0 0x0 0x1000 registers n I2C1 28 CLKDIV No Description 0x18 read-write n 0x0 0x0 DIV Clock Divider 0 9 read-write CMD No Description 0xC write-only n 0x0 0x0 ABORT Abort transmission 5 1 write-only ACK Send ACK 2 1 write-only CLEARPC Clear Pending Commands 7 1 write-only CLEARTX Clear TX 6 1 write-only CONT Continue transmission 4 1 write-only NACK Send NACK 3 1 write-only START Send start condition 0 1 write-only STOP Send stop condition 1 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 ARBDIS Arbitration Disable 5 1 read-write DISABLE When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released. 0 ENABLE When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds. 1 AUTOACK Automatic Acknowledge 2 1 read-write DISABLE Software must give one ACK command for each ACK transmitted on the I2C bus. 0 ENABLE Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 AUTOSE Automatic STOP when Empty 3 1 read-write DISABLE A stop must be sent manually when no more data is to be transmitted. 0 ENABLE The master automatically sends a STOP when no more data is available for transmission. 1 AUTOSN Automatic STOP on NACK 4 1 read-write DISABLE Stop is not automatically sent if a NACK is received from a slave. 0 ENABLE The master automatically sends a STOP if a NACK is received from a slave. 1 BITO Bus Idle Timeout 12 2 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 CLHR Clock Low High Ratio 8 2 read-write STANDARD Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4 0 ASYMMETRIC Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3 1 FAST Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6 2 CLTO Clock Low Timeout 16 3 read-write OFF Timeout disabled 0 I2C40PCC Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout. 1 I2C80PCC Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout. 2 I2C160PCC Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout. 3 I2C320PCC Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout. 4 I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. 5 CORERST Soft Reset the internal state registers 0 1 read-write DISABLE No change to internal state registers 0 ENABLE Reset the internal state registers 1 GCAMEN General Call Address Match Enable 6 1 read-write DISABLE General call address will be NACK'ed if it is not included by the slave address and address mask. 0 ENABLE When a general call address is received, a software response is required 1 GIBITO Go Idle on Bus Idle Timeout 15 1 read-write DISABLE A bus idle timeout has no effect on the bus state. 0 ENABLE A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated. 1 SCLMONEN SCL Monitor Enable 20 1 read-write DISABLE Disable SCL monitor 0 ENABLE Enable SCL monitor 1 SDAMONEN SDA Monitor Enable 21 1 read-write DISABLE Disable SDA Monitor 0 ENABLE Enable SDA Monitor 1 SLAVE Addressable as Slave 1 1 read-write DISABLE All addresses will be responded to with a NACK 0 ENABLE Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK. 1 TXBIL TX Buffer Interrupt Level 7 1 read-write EMPTY TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALF_FULL TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full 1 EN No Description 0x4 read-write n 0x0 0x0 EN module enable 0 1 read-write DISABLE Disable Peripheral Clock 0 ENABLE Enable Peripheral Clock 1 IEN No Description 0x40 read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IF No Description 0x3C read-write n 0x0 0x0 ACK Acknowledge Received Interrupt Flag 6 1 read-write ADDR Address Interrupt Flag 2 1 read-write ARBLOST Arbitration Lost Interrupt Flag 9 1 read-write BITO Bus Idle Timeout Interrupt Flag 14 1 read-write BUSERR Bus Error Interrupt Flag 10 1 read-write BUSHOLD Bus Held Interrupt Flag 11 1 read-write CLERR Clock Low Error Interrupt Flag 18 1 read-write CLTO Clock Low Timeout Interrupt Flag 15 1 read-write MSTOP Master STOP Condition Interrupt Flag 8 1 read-write NACK Not Acknowledge Received Interrupt Flag 7 1 read-write RSTART Repeated START condition Interrupt Flag 1 1 read-write RXDATAV Receive Data Valid Interrupt Flag 5 1 read-write RXFULL Receive Buffer Full Interrupt Flag 17 1 read-write RXUF Receive Buffer Underflow Interrupt Flag 13 1 read-write SCLERR SCL Error Interrupt Flag 19 1 read-write SDAERR SDA Error Interrupt Flag 20 1 read-write SSTOP Slave STOP condition Interrupt Flag 16 1 read-write START START condition Interrupt Flag 0 1 read-write TXBL Transmit Buffer Level Interrupt Flag 4 1 read-write TXC Transfer Completed Interrupt Flag 3 1 read-write TXOF Transmit Buffer Overflow Interrupt Flag 12 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAP No Description 0x2C read-only n 0x0 0x0 RXDATAP RX Data Peek 0 8 read-only RXDOUBLE No Description 0x28 read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEP No Description 0x30 read-only n 0x0 0x0 RXDATAP0 RX Data 0 Peek 0 8 read-only RXDATAP1 RX Data 1 Peek 8 8 read-only SADDR No Description 0x1C read-write n 0x0 0x0 ADDR Slave address 1 7 read-write SADDRMASK No Description 0x20 read-write n 0x0 0x0 SADDRMASK Slave Address Mask 1 7 read-write STATE No Description 0x10 -1 read-only n 0x0 0x0 BUSHOLD Bus Held 4 1 read-only BUSY Bus Busy 0 1 read-only MASTER Master 1 1 read-only NACKED Nack Received 3 1 read-only STATE Transmission State 5 3 read-only IDLE No transmission is being performed. 0 WAIT Waiting for idle. Will send a start condition as soon as the bus is idle. 1 START Start transmit phase 2 ADDR Address transmit or receive phase 3 ADDRACK Address ack/nack transmit or receive phase 4 DATA Data transmit or receive phase 5 DATAACK Data ack/nack transmit or receive phase 6 TRANSMITTER Transmitter 2 1 read-only STATUS No Description 0x14 -1 read-only n 0x0 0x0 PABORT Pending abort 5 1 read-only PACK Pending ACK 2 1 read-only PCONT Pending continue 4 1 read-only PNACK Pending NACK 3 1 read-only PSTART Pending START 0 1 read-only PSTOP Pending STOP 1 1 read-only RXDATAV RX Data Valid 8 1 read-only RXFULL RX FIFO Full 9 1 read-only TXBL TX Buffer Level 7 1 read-only TXBUFCNT TX Buffer Count 10 2 read-only TXC TX Complete 6 1 read-only TXDATA No Description 0x34 write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDOUBLE No Description 0x38 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only IADC0_NS IADC0_NS Registers IADC0_NS 0x0 0x0 0x1000 registers n IADC 50 CFG0 Configration 0x48 -1 read-write n 0x0 0x0 ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 CFG1 Configration 0x58 -1 read-write n 0x0 0x0 ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 CMD Command 0xC write-only n 0x0 0x0 SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only TIMERDIS Timer Disable 17 1 write-only TIMEREN Timer Enable 16 1 write-only CMPTHR Comparator Threshold 0x20 read-write n 0x0 0x0 ADGT ADC Greater Than or Equal to Threshold 16 16 read-write ADLT ADC Less Than or Equal to Threshold 0 16 read-write CTRL Control 0x8 read-write n 0x0 0x0 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 TIMEBASE Time Base 16 7 read-write WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 EN Enable 0x4 read-write n 0x0 0x0 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 IEN Interrupt Enable 0x28 read-write n 0x0 0x0 EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write IF Interrupt Flag 0x24 read-write n 0x0 0x0 EM23ABORTERROR EM2/3 Abort Error 31 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write IPVERSION IPVERSION 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only MASKREQ Mask Request 0x18 read-write n 0x0 0x0 MASKREQ Scan Queue Mask Request 0 16 read-write SCALE0 Scale 0x50 -1 read-write n 0x0 0x0 GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 OFFSET Offset 0 18 read-write SCALE1 Scale 0x60 -1 read-write n 0x0 0x0 GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 OFFSET Offset 0 18 read-write SCAN0 No Description 0xA0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN1 No Description 0xA4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN10 No Description 0xC8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN11 No Description 0xCC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN12 No Description 0xD0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN13 No Description 0xD4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN14 No Description 0xD8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN15 No Description 0xDC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN2 No Description 0xA8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN3 No Description 0xAC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN4 No Description 0xB0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN5 No Description 0xB4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN6 No Description 0xB8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN7 No Description 0xBC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN8 No Description 0xC0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN9 No Description 0xC4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCANDATA Most recent data data from scan queue conversion 0x8C read-only n 0x0 0x0 DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x80 -1 read-write n 0x0 0x0 ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 SHOWID Show ID 3 1 read-write SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x84 read-only n 0x0 0x0 DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x88 read-only n 0x0 0x0 FIFOREADCNT FIFO Read Count 0 3 read-only SCHED0 Scheduling 0x54 read-write n 0x0 0x0 PRESCALE Prescale 0 10 read-write SCHED1 Scheduling 0x64 read-write n 0x0 0x0 PRESCALE Prescale 0 10 read-write SINGLE No Description 0x98 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SINGLEDATA latest single queue conversion data 0x7C read-only n 0x0 0x0 DATA Data 0 32 read-only SINGLEFIFOCFG Single FIFO Configuration 0x70 -1 read-write n 0x0 0x0 ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 SHOWID Show ID 3 1 read-write SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x74 read-only n 0x0 0x0 DATA Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x78 read-only n 0x0 0x0 FIFOREADCNT FIFO Read Count 0 3 read-only STATUS Status 0x14 read-only n 0x0 0x0 ADCWARM ADCWARM 30 1 read-only CONVERTING Converting 6 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only TIMERACTIVE Timer Active 16 1 read-only STMASK Scan Table Mask 0x1C read-only n 0x0 0x0 STMASK Scan Table Mask 0 16 read-only TIMER Timer 0x10 read-write n 0x0 0x0 TIMER Timer Period 0 16 read-write TRIGGER Trigger 0x2C read-write n 0x0 0x0 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 IADC0_S IADC0_S Registers IADC0_S 0x0 0x0 0x1000 registers n IADC 50 CFG0 Configration 0x48 -1 read-write n 0x0 0x0 ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 CFG1 Configration 0x58 -1 read-write n 0x0 0x0 ADCMODE ADC Mode 0 2 read-write NORMAL High speed mode with a maximum CLK_ADC of 10 MHz. 0 ANALOGGAIN Analog Gain 12 3 read-write ANAGAIN0P5 Analog gain of 0.5x. 1 ANAGAIN1 Analog gain of 1x. 2 ANAGAIN2 Analog gain of 2x. 3 ANAGAIN3 Analog gain of 3x. 4 ANAGAIN4 Analog gain of 4x. 5 OSRHS High Speed OSR 2 3 read-write HISPD2 High speed over sampling of 2x. 0 HISPD4 High speed over sampling of 4x. 1 HISPD8 High speed over sampling of 8x. 2 HISPD16 High speed over sampling of 16x. 3 HISPD32 HIgh speed over sampling of 32x. 4 HISPD64 High speed over sampling of 64x. 5 REFSEL Reference Select 16 3 read-write VBGR Internal 1.21 V reference. 0 VREF External Reference. (Calibrated for 1.25V nominal.) 1 VDDX AVDD (unbuffered) 3 VDDX0P8BUF AVDD (buffered) * 0.8 4 TWOSCOMPL Two's Complement 28 2 read-write AUTO Automatic: Single ended measurements are reported as unipolar and differential measurements are reported as bipolar. 0 FORCEUNIPOLAR Force all measurements to result in unipolar output. Negative differential numbers will saturate to 0. 1 FORCEBIPOLAR Force all measurements to result in bipolar output. Single ended measurements are half the range, but allow for small negative measurements. 2 CMD Command 0xC write-only n 0x0 0x0 SCANSTART Scan Queue Start 3 1 write-only SCANSTOP Scan Queue Stop 4 1 write-only SINGLESTART Single Queue Start 0 1 write-only SINGLESTOP Single Queue Stop 1 1 write-only TIMERDIS Timer Disable 17 1 write-only TIMEREN Timer Enable 16 1 write-only CMPTHR Comparator Threshold 0x20 read-write n 0x0 0x0 ADGT ADC Greater Than or Equal to Threshold 16 16 read-write ADLT ADC Less Than or Equal to Threshold 0 16 read-write CTRL Control 0x8 read-write n 0x0 0x0 ADCCLKSUSPEND0 ADC_CLK Suspend - PRS0 1 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1 2 1 read-write PRSWUDIS Normal mode which does not disable the ADC_CLK. 0 PRSWUEN ADCCLKWUEN will gate off ADC_CLK until the trigger is detected provided the internal timer is not selected as the trigger. Once the trigger is detected the ADC_CLK will be started, the band gap will be started, the ADC will be warmed up, and the SCAN Table and the Single entry will be converted. Once the conversions are done, the ADC_CLK will be gated off. 1 DBGHALT Debug Halt 3 1 read-write NORMAL Continue operation as normal during debug mode 0 HALT Complete the current conversion and then halt during debug mode 1 HSCLKRATE High Speed Clock Rate 28 3 read-write DIV1 Use CMU_CLK_ADC directly. The source clock must be 40 MHz or less. 0 DIV2 Divide CMU_CLK_ADC by 2 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 1 DIV3 Divide CMU_CLK_ADC by 3 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 2 DIV4 Divide CMU_CLK_ADC by 4 before using it. The resulting CLK_SRC_ADC must be 40 MHz or less. 3 TIMEBASE Time Base 16 7 read-write WARMUPMODE Warmup Mode 4 2 read-write NORMAL Shut down the IADC after conversions have completed. 0 KEEPINSTANDBY Switch to standby mode after conversions have completed. The next warmup time will require 1us. 1 KEEPWARM Keep IADC fully powered after conversions have completed. 2 EN Enable 0x4 read-write n 0x0 0x0 EN Enable IADC Module 0 1 read-write DISABLE Disable 0 ENABLE Enable 1 IEN Interrupt Enable 0x28 read-write n 0x0 0x0 EM23ABORTERROR EM2/3 Abort Error Enable 31 1 read-write POLARITYERR Polarity Error Enable 12 1 read-write PORTALLOCERR Port Allocation Error Enable 13 1 read-write SCANCMP Scan Result Window Compare Enable 3 1 read-write SCANENTRYDONE Scan Entry Done Enable 7 1 read-write SCANFIFODVL Scan FIFO Data Valid Level Enable 1 1 read-write SCANFIFOOF Scan FIFO Overflow Enable 17 1 read-write SCANFIFOUF Scan FIFO Underflow Enable 19 1 read-write SCANTABLEDONE Scan Table Done Enable 8 1 read-write SINGLECMP Single Result Window Compare Enable 2 1 read-write SINGLEDONE Single Conversion Done Enable 9 1 read-write SINGLEFIFODVL Single FIFO Data Valid Level Enable 0 1 read-write SINGLEFIFOOF Single FIFO Overflow Enable 16 1 read-write SINGLEFIFOUF Single FIFO Underflow Enable 18 1 read-write IF Interrupt Flag 0x24 read-write n 0x0 0x0 EM23ABORTERROR EM2/3 Abort Error 31 1 read-write POLARITYERR Polarity Error 12 1 read-write PORTALLOCERR Port Allocation Error 13 1 read-write SCANCMP Scan Result Window Compare 3 1 read-write SCANENTRYDONE Scan Entry Done 7 1 read-write SCANFIFODVL Scan FIFO Data Valid Level 1 1 read-write SCANFIFOOF Scan FIFO Overflow 17 1 read-write SCANFIFOUF Scan FIFO Underflow 19 1 read-write SCANTABLEDONE Scan Table Done 8 1 read-write SINGLECMP Single Result Window Compare 2 1 read-write SINGLEDONE Single Conversion Done 9 1 read-write SINGLEFIFODVL Single FIFO Data Valid Level 0 1 read-write SINGLEFIFOOF Single FIFO Overflow 16 1 read-write SINGLEFIFOUF Single FIFO Underflow 18 1 read-write IPVERSION IPVERSION 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only MASKREQ Mask Request 0x18 read-write n 0x0 0x0 MASKREQ Scan Queue Mask Request 0 16 read-write SCALE0 Scale 0x50 -1 read-write n 0x0 0x0 GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 OFFSET Offset 0 18 read-write SCALE1 Scale 0x60 -1 read-write n 0x0 0x0 GAIN13LSB Gain 13 LSBs 18 13 read-write GAIN3MSB Gain 3 MSBs 31 1 read-write GAIN011 Upper 3 bits of gain = 011 (0.75x) 0 GAIN100 Upper 3 bits of gain = 100 (1.00x) 1 OFFSET Offset 0 18 read-write SCAN0 No Description 0xA0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN1 No Description 0xA4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN10 No Description 0xC8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN11 No Description 0xCC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN12 No Description 0xD0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN13 No Description 0xD4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN14 No Description 0xD8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN15 No Description 0xDC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN2 No Description 0xA8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN3 No Description 0xAC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN4 No Description 0xB0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN5 No Description 0xB4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN6 No Description 0xB8 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN7 No Description 0xBC read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN8 No Description 0xC0 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCAN9 No Description 0xC4 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SCANDATA Most recent data data from scan queue conversion 0x8C read-only n 0x0 0x0 DATA Data 0 32 read-only SCANFIFOCFG Scan FIFO Configuration 0x80 -1 read-write n 0x0 0x0 ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 DMAWUFIFOSCAN Scan FIFO DMA Wakeup 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA. 3 SHOWID Show ID 3 1 read-write SCANFIFODATA Read the oldest valid data from the scan FIFO and pop the FIFO 0x84 read-only n 0x0 0x0 DATA Data 0 32 read-only SCANFIFOSTAT Scan FIFO status 0x88 read-only n 0x0 0x0 FIFOREADCNT FIFO Read Count 0 3 read-only SCHED0 Scheduling 0x54 read-write n 0x0 0x0 PRESCALE Prescale 0 10 read-write SCHED1 Scheduling 0x64 read-write n 0x0 0x0 PRESCALE Prescale 0 10 read-write SINGLE No Description 0x98 read-write n 0x0 0x0 CFG Configuration Group Select 16 1 read-write CONFIG0 Use configuration group 0 0 CONFIG1 Use configuration group 1 1 CMP Comparison Enable 17 1 read-write PINNEG Negative Pin Select 0 4 read-write PINPOS Positive Pin Select 8 4 read-write PORTNEG Negative Port Select 4 4 read-write GND Ground (single-ended) 0 PORTC Port C - Select pin number using PINNEG 10 PORTD Port D - Select pin number using PINNEG 11 PADREFNEG External Negative Reference Pin 6 PORTA Port A - Select pin number using PINNEG 8 PORTB Port B - Select pin number using PINNEG 9 PORTPOS Positive Port Select 12 4 read-write GND Ground 0 SUPPLY Supply Pin - Select specific supply using PINPOS 1 PORTC Port C - Select pin number using PINPOS 10 PORTD Port D - Select pin number using PINPOS 11 PADREFPOS External Positive Reference Pin 6 PORTA Port A - Select pin number using PINPOS 8 PORTB Port B - Select pin number using PINPOS 9 SINGLEDATA latest single queue conversion data 0x7C read-only n 0x0 0x0 DATA Data 0 32 read-only SINGLEFIFOCFG Single FIFO Configuration 0x70 -1 read-write n 0x0 0x0 ALIGNMENT Alignment 0 3 read-write RIGHT12 ID[7:0], SIGN_EXT, DATA[11:0] 0 LEFT12 DATA[11:0], 000000000000, ID[7:0] 3 DMAWUFIFOSINGLE Single FIFO DMA wakeup. 8 1 read-write DISABLED While in EM2 or EM3, the DMA controller will not be requested. 0 ENABLED While in EM2 or EM3, the DMA controller will be requested when the single FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).] 1 DVL Data Valid Level 4 2 read-write VALID1 When 1 entry in the single FIFO is valid, set the SINGLEFIFODVL interrupt and request DMA. 0 VALID2 When 2 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 1 VALID3 When 3 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 2 VALID4 When 4 entries in the single FIFO are valid, set the SINGLEFIFODVL interrupt and request DMA. 3 SHOWID Show ID 3 1 read-write SINGLEFIFODATA Read the oldest valid data from the single FIFO and pop the FIFO 0x74 read-only n 0x0 0x0 DATA Data 0 32 read-only SINGLEFIFOSTAT Single FIFO status 0x78 read-only n 0x0 0x0 FIFOREADCNT FIFO Read Count 0 3 read-only STATUS Status 0x14 read-only n 0x0 0x0 ADCWARM ADCWARM 30 1 read-only CONVERTING Converting 6 1 read-only MASKREQWRITEPENDING MASKREQ write pending 21 1 read-only SCANFIFODV SCANFIFO Data Valid 9 1 read-only SCANQEN Scan Queued Enabled 3 1 read-only SCANQUEUEPENDING Scan Queue Pending 4 1 read-only SINGLEFIFODV SINGLEFIFO Data Valid 8 1 read-only SINGLEQEN Single Queue Enabled 0 1 read-only SINGLEQUEUEPENDING Single Queue Pending 1 1 read-only SINGLEWRITEPENDING SINGLE write pending 20 1 read-only TIMERACTIVE Timer Active 16 1 read-only STMASK Scan Table Mask 0x1C read-only n 0x0 0x0 STMASK Scan Table Mask 0 16 read-only TIMER Timer 0x10 read-write n 0x0 0x0 TIMER Timer Period 0 16 read-write TRIGGER Trigger 0x2C read-write n 0x0 0x0 SCANTRIGACTION Scan Trigger Action 4 1 read-write ONCE For TRIGSEL=IMMEDIATE, goes through the scan table once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, goes through the scan table once per trigger. 0 CONTINUOUS Goes through the scan table, converts each entry with a mask bit set, and puts it back into the scan queue to repeat again continuously. The queues are first come first serve. If both queues are triggered, the single queue will get to convert after each scan table completes. The scan queue will get to convert after each single conversion completes. 1 SCANTRIGSEL Scan Trigger Select 0 3 read-write IMMEDIATE Immediate triggering. The scan queue will be disabled once all conversions in the scan table are complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the local timer count reaches zero. 1 PRSCLKGRP Triggers on PRS0 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS0 negative edge. Requires PRS0 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 SINGLETAILGATE Single Tailgate Enable 16 1 read-write TAILGATEOFF The single queue is ready to start warming up and converting once the trigger had been detected. 0 TAILGATEON After the single queue's trigger is detected, it must wait until the end of a scan operation before the Single queue can be converted. 1 SINGLETRIGACTION Single Trigger Action 12 1 read-write ONCE For TRIGSEL=IMMEDIATE, converts the single queue once and disables queue. For TRIGSEL = TIMER, PRSCLKGRP, PRSPOS, PRSNEG, converts the single queue once per trigger.ask. 0 CONTINUOUS Converts the single queue, then checks for a pending scan queue before converting the single queue again continuously. The queues are first come first serve. If both queues are continuous, the IADC alternates between them. 1 SINGLETRIGSEL Single Trigger Select 8 3 read-write IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. 0 TIMER Triggers when the timer count reaches zero. 1 PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the same clock source as the ADC. The prescale may be different between the ADC and the timer module. 2 PRSPOS Triggers on asynchronous PRS1 positive edge. Requires PRS1 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. 3 PRSNEG Triggers on asynchronous PRS1 negative edge. Requires PRS1 to go high for 3 ADC_CLKs before another negative edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization. PRSNEG should only be used when the trigger source is from a module that remains powered during EM23. For modules (ie: TIMER) that power down during EM23, PRSPOS should be used for an asynchronous trigger, and PRSCLKGRP should be used for a synchronous trigger. 4 ICACHE0_NS ICACHE0_NS Registers ICACHE0_NS 0x0 0x0 0x1000 registers n ICACHE0 17 CMD No Description 0x18 write-only n 0x0 0x0 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only CTRL No Description 0x4 read-write n 0x0 0x0 AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write IEN No Description 0x24 read-write n 0x0 0x0 AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write RAMERRORIEN RAM error Interrupt Enable 8 1 read-write IF No Description 0x20 read-write n 0x0 0x0 AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only LPMODE No Description 0x1C -1 read-write n 0x0 0x0 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write PCAHITS No Description 0x10 read-only n 0x0 0x0 PCAHITS Performance Counter Advanced Hits 0 32 read-only PCHITS No Description 0x8 read-only n 0x0 0x0 PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0xC read-only n 0x0 0x0 PCMISSES Performance Counter Misses 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 PCRUNNING PC Running 0 1 read-only ICACHE0_S ICACHE0_S Registers ICACHE0_S 0x0 0x0 0x1000 registers n ICACHE0 17 CMD No Description 0x18 write-only n 0x0 0x0 FLUSH Flush 0 1 write-only STARTPC Start Performance Counters 1 1 write-only STOPPC Stop Performance Counters 2 1 write-only CTRL No Description 0x4 read-write n 0x0 0x0 AUTOFLUSHDIS Automatic Flushing Disable 2 1 read-write CACHEDIS Cache Disable 0 1 read-write USEMPU Use MPU 1 1 read-write IEN No Description 0x24 read-write n 0x0 0x0 AHITOF Advanced Hit Overflow Interrupt Enable 2 1 read-write HITOF Hit Overflow Interrupt Enable 0 1 read-write MISSOF Miss Overflow Interrupt Enable 1 1 read-write RAMERROR RAM error Interrupt Enable 8 1 read-write RAMERRORIEN RAM error Interrupt Enable 8 1 read-write IF No Description 0x20 read-write n 0x0 0x0 AHITOF Advanced Hit Overflow Interrupt Flag 2 1 read-write HITOF Hit Overflow Interrupt Flag 0 1 read-write MISSOF Miss Overflow Interrupt Flag 1 1 read-write RAMERROR RAM error Interrupt Flag 8 1 read-write IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION. 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only LPMODE No Description 0x1C -1 read-write n 0x0 0x0 LPLEVEL Low Power Level 0 2 read-write BASIC Base instruction cache functionality 0 ADVANCED Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory 1 MINACTIVITY Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality. 3 NESTFACTOR Low Power Nest Factor 4 4 read-write PCAHITS No Description 0x10 read-only n 0x0 0x0 PCAHITS Performance Counter Advanced Hits 0 32 read-only PCHITS No Description 0x8 read-only n 0x0 0x0 PCHITS Performance Counter Hits 0 32 read-only PCMISSES No Description 0xC read-only n 0x0 0x0 PCMISSES Performance Counter Misses 0 32 read-only STATUS No Description 0x14 read-only n 0x0 0x0 PCRUNNING PC Running 0 1 read-only LDMAXBAR_NS LDMAXBAR_NS Registers LDMAXBAR_NS 0x0 0x0 0x1000 registers n CH0_REQSEL No Description 0x0 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x4 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x8 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0xC read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x10 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x14 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x18 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x1C read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write LDMAXBAR_S LDMAXBAR_S Registers LDMAXBAR_S 0x0 0x0 0x1000 registers n CH0_REQSEL No Description 0x0 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH1_REQSEL No Description 0x4 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH2_REQSEL No Description 0x8 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH3_REQSEL No Description 0xC read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH4_REQSEL No Description 0x10 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH5_REQSEL No Description 0x14 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH6_REQSEL No Description 0x18 read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write CH7_REQSEL No Description 0x1C read-write n 0x0 0x0 SIGSEL Signal Select 0 4 read-write SOURCESEL Source Select 16 6 read-write LDMA_NS LDMA_NS Registers LDMA_NS 0x0 0x0 0x1000 registers n LDMA 21 CH0_CFG No Description 0x5C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH0_CTRL No Description 0x64 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH0_DST No Description 0x6C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x70 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH0_LOOP No Description 0x60 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_SRC No Description 0x68 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH1_CFG No Description 0x8C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH1_CTRL No Description 0x94 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH1_DST No Description 0x9C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0xA0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH1_LOOP No Description 0x90 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_SRC No Description 0x98 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH2_CFG No Description 0xBC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH2_CTRL No Description 0xC4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH2_DST No Description 0xCC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0xD0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH2_LOOP No Description 0xC0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_SRC No Description 0xC8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH3_CFG No Description 0xEC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH3_CTRL No Description 0xF4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH3_DST No Description 0xFC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH3_LOOP No Description 0xF0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_SRC No Description 0xF8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH4_CFG No Description 0x11C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH4_CTRL No Description 0x124 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH4_DST No Description 0x12C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH4_LOOP No Description 0x120 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_SRC No Description 0x128 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH5_CFG No Description 0x14C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH5_CTRL No Description 0x154 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH5_DST No Description 0x15C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH5_LOOP No Description 0x150 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_SRC No Description 0x158 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH6_CFG No Description 0x17C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH6_CTRL No Description 0x184 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH6_DST No Description 0x18C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH6_LOOP No Description 0x180 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_SRC No Description 0x188 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH7_CFG No Description 0x1AC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH7_CTRL No Description 0x1B4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH7_DST No Description 0x1BC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH7_LOOP No Description 0x1B0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_SRC No Description 0x1B8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CHBUSY No Description 0x30 read-only n 0x0 0x0 BUSY Channels Busy 0 8 read-only CHDIS No Description 0x28 write-only n 0x0 0x0 CHDIS DMA Channel disable 0 8 write-only CHDONE No Description 0x34 read-write n 0x0 0x0 CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write CHEN No Description 0x24 write-only n 0x0 0x0 CHEN Channel Enables 0 8 write-only CHSTATUS No Description 0x2C read-only n 0x0 0x0 CHSTATUS DMA Channel Status 0 8 read-only CTRL No Description 0x8 -1 read-write n 0x0 0x0 CORERST Reset DMA controller 31 1 read-write NUMFIXED Number of Fixed Priority Channels 24 5 read-write DBGHALT No Description 0x38 read-write n 0x0 0x0 DBGHALT DMA Debug Halt 0 8 read-write EN No Description 0x4 read-write n 0x0 0x0 EN LDMA module enable and disable register 0 1 read-write IEN No Description 0x54 read-write n 0x0 0x0 CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write IF No Description 0x50 read-write n 0x0 0x0 DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 8 read-only LINKLOAD No Description 0x48 write-only n 0x0 0x0 LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x4C write-only n 0x0 0x0 REQCLEAR DMA Request Clear 0 8 write-only REQDIS No Description 0x40 read-write n 0x0 0x0 REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x44 read-only n 0x0 0x0 REQPEND DMA Requests Pending 0 8 read-only STATUS No Description 0xC -1 read-only n 0x0 0x0 ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHERROR Errant Channel Number 8 5 read-only CHGRANT Granted Channel Number 3 5 read-only CHNUM Number of Channels 24 5 read-only FIFOLEVEL FIFO Level 16 5 read-only SWREQ No Description 0x3C write-only n 0x0 0x0 SWREQ Software Transfer Requests 0 8 write-only SYNCHWEN No Description 0x18 read-write n 0x0 0x0 SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCHWSEL No Description 0x1C read-write n 0x0 0x0 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x20 read-only n 0x0 0x0 SYNCTRIG sync trig status 0 8 read-only SYNCSWCLR No Description 0x14 write-only n 0x0 0x0 SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCSWSET No Description 0x10 write-only n 0x0 0x0 SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only LDMA_S LDMA_S Registers LDMA_S 0x0 0x0 0x1000 registers n LDMA 21 CH0_CFG No Description 0x5C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH0_CTRL No Description 0x64 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH0_DST No Description 0x6C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH0_LINK No Description 0x70 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH0_LOOP No Description 0x60 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH0_SRC No Description 0x68 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH1_CFG No Description 0x8C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH1_CTRL No Description 0x94 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH1_DST No Description 0x9C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH1_LINK No Description 0xA0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH1_LOOP No Description 0x90 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH1_SRC No Description 0x98 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH2_CFG No Description 0xBC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH2_CTRL No Description 0xC4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH2_DST No Description 0xCC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH2_LINK No Description 0xD0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH2_LOOP No Description 0xC0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH2_SRC No Description 0xC8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH3_CFG No Description 0xEC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH3_CTRL No Description 0xF4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH3_DST No Description 0xFC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH3_LINK No Description 0x100 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH3_LOOP No Description 0xF0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH3_SRC No Description 0xF8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH4_CFG No Description 0x11C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH4_CTRL No Description 0x124 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH4_DST No Description 0x12C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH4_LINK No Description 0x130 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH4_LOOP No Description 0x120 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH4_SRC No Description 0x128 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH5_CFG No Description 0x14C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH5_CTRL No Description 0x154 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH5_DST No Description 0x15C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH5_LINK No Description 0x160 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH5_LOOP No Description 0x150 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH5_SRC No Description 0x158 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH6_CFG No Description 0x17C read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH6_CTRL No Description 0x184 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH6_DST No Description 0x18C read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH6_LINK No Description 0x190 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH6_LOOP No Description 0x180 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH6_SRC No Description 0x188 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CH7_CFG No Description 0x1AC read-write n 0x0 0x0 ARBSLOTS Arbitration Slot Number Select 16 2 read-write ONE One arbitration slot selected 0 TWO Two arbitration slots selected 1 FOUR Four arbitration slots selected 2 EIGHT Eight arbitration slots selected 3 DSTINCSIGN Destination Address Increment Sign 21 1 read-write POSITIVE Increment destination address 0 NEGATIVE Decrement destination address 1 SRCINCSIGN Source Address Increment Sign 20 1 read-write POSITIVE Increment source address 0 NEGATIVE Decrement source address 1 CH7_CTRL No Description 0x1B4 read-write n 0x0 0x0 BLOCKSIZE Block Transfer Size 16 4 read-write UNIT1 One unit transfer per arbitration 0 UNIT2 Two unit transfers per arbitration 1 UNIT64 64 unit transfers per arbitration 10 UNIT128 128 unit transfers per arbitration 11 UNIT256 256 unit transfers per arbitration 12 UNIT512 512 unit transfers per arbitration 13 UNIT1024 1024 unit transfers per arbitration 14 ALL Transfer all units as specified by the XFRCNT field 15 UNIT3 Three unit transfers per arbitration 2 UNIT4 Four unit transfers per arbitration 3 UNIT6 Six unit transfers per arbitration 4 UNIT8 Eight unit transfers per arbitration 5 UNIT16 Sixteen unit transfers per arbitration 7 UNIT32 32 unit transfers per arbitration 9 BYTESWAP Endian Byte Swap 15 1 read-write DECLOOPCNT Decrement Loop Count 22 1 read-write DONEIEN DMA Operation Done Interrupt Flag Set En 20 1 read-write DSTINC Destination Address Increment Size 28 2 read-write ONE Increment destination address by one unit data size after each write 0 TWO Increment destination address by two unit data sizes after each write 1 FOUR Increment destination address by four unit data sizes after each write 2 NONE Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO. 3 DSTMODE Destination Addressing Mode 31 1 read-only ABSOLUTE The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data. 0 RELATIVE The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data. 1 IGNORESREQ Ignore Sreq 23 1 read-write REQMODE DMA Request Transfer Mode Select 21 1 read-write BLOCK The LDMA transfers one BLOCKSIZE per transfer request. 0 ALL One transfer request transfers all units as defined by the XFRCNT field. 1 SIZE Unit Data Transfer Size 26 2 read-write BYTE Each unit transfer is a byte 0 HALFWORD Each unit transfer is a half-word 1 WORD Each unit transfer is a word 2 SRCINC Source Address Increment Size 24 2 read-write ONE Increment source address by one unit data size after each read 0 TWO Increment source address by two unit data sizes after each read 1 FOUR Increment source address by four unit data sizes after each read 2 NONE Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO. 3 SRCMODE Source Addressing Mode 30 1 read-only ABSOLUTE The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data. 0 RELATIVE The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data. 1 STRUCTREQ Structure DMA Transfer Request 3 1 read-only STRUCTTYPE DMA Structure Type 0 2 read-write TRANSFER DMA transfer structure type selected. 0 SYNCHRONIZE Synchronization structure type selected. 1 WRITE Write immediate value structure type selected. 2 XFERCNT DMA Unit Data Transfer Count 4 11 read-write CH7_DST No Description 0x1BC read-write n 0x0 0x0 DSTADDR Destination Data Address 0 32 read-write CH7_LINK No Description 0x1C0 read-write n 0x0 0x0 LINK Link Next Structure 1 1 read-write LINKADDR Link Structure Address 2 30 read-write LINKMODE Link Structure Addressing Mode 0 1 read-only ABSOLUTE The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor. 0 RELATIVE The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor. 1 CH7_LOOP No Description 0x1B0 read-write n 0x0 0x0 LOOPCNT Linked Structure Sequence Loop Counter 0 8 read-write CH7_SRC No Description 0x1B8 read-write n 0x0 0x0 SRCADDR Source Data Address 0 32 read-write CHBUSY No Description 0x30 read-only n 0x0 0x0 BUSY Channels Busy 0 8 read-only CHDIS No Description 0x28 write-only n 0x0 0x0 CHDIS DMA Channel disable 0 8 write-only CHDONE No Description 0x34 read-write n 0x0 0x0 CHDONE0 DMA Channel Link done intr flag 0 1 read-write CHDONE1 DMA Channel Link done intr flag 1 1 read-write CHDONE2 DMA Channel Link done intr flag 2 1 read-write CHDONE3 DMA Channel Link done intr flag 3 1 read-write CHDONE4 DMA Channel Link done intr flag 4 1 read-write CHDONE5 DMA Channel Link done intr flag 5 1 read-write CHDONE6 DMA Channel Link done intr flag 6 1 read-write CHDONE7 DMA Channel Link done intr flag 7 1 read-write CHEN No Description 0x24 write-only n 0x0 0x0 CHEN Channel Enables 0 8 write-only CHSTATUS No Description 0x2C read-only n 0x0 0x0 CHSTATUS DMA Channel Status 0 8 read-only CTRL No Description 0x8 -1 read-write n 0x0 0x0 CORERST Reset DMA controller 31 1 read-write NUMFIXED Number of Fixed Priority Channels 24 5 read-write DBGHALT No Description 0x38 read-write n 0x0 0x0 DBGHALT DMA Debug Halt 0 8 read-write EN No Description 0x4 read-write n 0x0 0x0 EN LDMA module enable and disable register 0 1 read-write IEN No Description 0x54 read-write n 0x0 0x0 CHDONE Enable or disable the done interrupt 0 8 read-write ERROR Enable or disable the error interrupt 31 1 read-write IF No Description 0x50 read-write n 0x0 0x0 DONE0 DMA Structure Operation Done 0 1 read-write DONE1 DMA Structure Operation Done 1 1 read-write DONE2 DMA Structure Operation Done 2 1 read-write DONE3 DMA Structure Operation Done 3 1 read-write DONE4 DMA Structure Operation Done 4 1 read-write DONE5 DMA Structure Operation Done 5 1 read-write DONE6 DMA Structure Operation Done 6 1 read-write DONE7 DMA Structure Operation Done 7 1 read-write ERROR Error Flag 31 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 8 read-only LINKLOAD No Description 0x48 write-only n 0x0 0x0 LINKLOAD DMA Link Loads 0 8 write-only REQCLEAR No Description 0x4C write-only n 0x0 0x0 REQCLEAR DMA Request Clear 0 8 write-only REQDIS No Description 0x40 read-write n 0x0 0x0 REQDIS DMA Request Disables 0 8 read-write REQPEND No Description 0x44 read-only n 0x0 0x0 REQPEND DMA Requests Pending 0 8 read-only STATUS No Description 0xC -1 read-only n 0x0 0x0 ANYBUSY Any DMA Channel Busy 0 1 read-only ANYREQ Any DMA Channel Request Pending 1 1 read-only CHERROR Errant Channel Number 8 5 read-only CHGRANT Granted Channel Number 3 5 read-only CHNUM Number of Channels 24 5 read-only FIFOLEVEL FIFO Level 16 5 read-only SWREQ No Description 0x3C write-only n 0x0 0x0 SWREQ Software Transfer Requests 0 8 write-only SYNCHWEN No Description 0x18 read-write n 0x0 0x0 SYNCCLREN Hardware Sync Trigger Clear Enable 16 8 read-write SYNCSETEN Hardware Sync Trigger Set Enable 0 8 read-write SYNCHWSEL No Description 0x1C read-write n 0x0 0x0 SYNCCLREDGE Hardware Sync Trigger Clear Edge Select 16 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSETEDGE Hardware Sync Trigger Set Edge Select 0 8 read-write RISE Use rising edge detection 0 FALL Use falling edge detection 1 SYNCSTATUS No Description 0x20 read-only n 0x0 0x0 SYNCTRIG sync trig status 0 8 read-only SYNCSWCLR No Description 0x14 write-only n 0x0 0x0 SYNCSWCLR DMA SYNC Software Trigger Clear 0 8 write-only SYNCSWSET No Description 0x10 write-only n 0x0 0x0 SYNCSWSET DMA SYNC Software Trigger Set 0 8 write-only LETIMER0_NS LETIMER0_NS Registers LETIMER0_NS 0x0 0x0 0x1000 registers n LETIMER0 19 CMD No Description 0xC write-only n 0x0 0x0 CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CNT No Description 0x18 read-write n 0x0 0x0 CNT Counter Value 0 24 read-write COMP0 No Description 0x1C read-write n 0x0 0x0 COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x20 read-write n 0x0 0x0 COMP1 Compare Value 1 0 24 read-write CTRL No Description 0x8 read-write n 0x0 0x0 BUFTOP Buffered Top 8 1 read-write DISABLE COMP0 is only written by software 0 ENABLE COMP0 is set to COMP1 when REP0 reaches 0 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 65535 (0xFFFF) 0 ENABLE The top value of the LETIMER is given by COMP0 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 EN No Description 0x4 read-write n 0x0 0x0 EN module en 0 1 read-write IEN No Description 0x38 read-write n 0x0 0x0 COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write UF Underflow Interrupt Enable 2 1 read-write IF No Description 0x34 read-write n 0x0 0x0 COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write UF Underflow Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only PRSMODE No Description 0x50 read-write n 0x0 0x0 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 REP0 No Description 0x2C read-write n 0x0 0x0 REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x30 read-write n 0x0 0x0 REP1 Repeat Counter 1 0 8 read-write STATUS No Description 0x10 read-only n 0x0 0x0 RUNNING LETIMER Running 0 1 read-only SYNCBUSY No Description 0x40 read-only n 0x0 0x0 CLEAR Sync busy for CLEAR 7 1 read-only CNT Sync busy for CNT 0 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only TOP Sync busy for TOP 2 1 read-only TOP No Description 0x24 read-write n 0x0 0x0 TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x28 read-write n 0x0 0x0 TOPBUFF Buffered Counter TOP Value 0 24 read-write LETIMER0_S LETIMER0_S Registers LETIMER0_S 0x0 0x0 0x1000 registers n LETIMER0 19 CMD No Description 0xC write-only n 0x0 0x0 CLEAR Clear LETIMER 2 1 write-only CTO0 Clear Toggle Output 0 3 1 write-only CTO1 Clear Toggle Output 1 4 1 write-only START Start LETIMER 0 1 write-only STOP Stop LETIMER 1 1 write-only CNT No Description 0x18 read-write n 0x0 0x0 CNT Counter Value 0 24 read-write COMP0 No Description 0x1C read-write n 0x0 0x0 COMP0 Compare Value 0 0 24 read-write COMP1 No Description 0x20 read-write n 0x0 0x0 COMP1 Compare Value 1 0 24 read-write CTRL No Description 0x8 read-write n 0x0 0x0 BUFTOP Buffered Top 8 1 read-write DISABLE COMP0 is only written by software 0 ENABLE COMP0 is set to COMP1 when REP0 reaches 0 1 CNTPRESC Counter prescaler value 16 4 read-write DIV1 CLK_CNT = (LETIMER LF CLK)/1 0 DIV2 CLK_CNT = (LETIMER LF CLK)/2 1 DIV4 CLK_CNT = (LETIMER LF CLK)/4 2 DIV8 CLK_CNT = (LETIMER LF CLK)/8 3 DIV16 CLK_CNT = (LETIMER LF CLK)/16 4 DIV32 CLK_CNT = (LETIMER LF CLK)/32 5 DIV64 CLK_CNT = (LETIMER LF CLK)/64 6 DIV128 CLK_CNT = (LETIMER LF CLK)/128 7 DIV256 CLK_CNT = (LETIMER LF CLK)/256 8 CNTTOPEN Compare Value 0 Is Top Value 9 1 read-write DISABLE The top value of the LETIMER is 65535 (0xFFFF) 0 ENABLE The top value of the LETIMER is given by COMP0 1 DEBUGRUN Debug Mode Run Enable 12 1 read-write DISABLE LETIMER is frozen in debug mode 0 ENABLE LETIMER is running in debug mode 1 OPOL0 Output 0 Polarity 6 1 read-write OPOL1 Output 1 Polarity 7 1 read-write REPMODE Repeat Mode 0 2 read-write FREE When started, the LETIMER counts down until it is stopped by software 0 ONESHOT The counter counts REP0 times. When REP0 reaches zero, the counter stops 1 BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops 2 DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero 3 UFOA0 Underflow Output Action 0 2 2 read-write NONE LETIMERn_OUT0 is held at its idle value as defined by OPOL0 0 TOGGLE LETIMERn_OUT0 is toggled on CNT underflow 1 PULSE LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0 2 PWM LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1 3 UFOA1 Underflow Output Action 1 4 2 read-write NONE LETIMERn_OUT1 is held at its idle value as defined by OPOL1 0 TOGGLE LETIMERn_OUT1 is toggled on CNT underflow 1 PULSE LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1 2 PWM LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1 3 EN No Description 0x4 read-write n 0x0 0x0 EN module en 0 1 read-write IEN No Description 0x38 read-write n 0x0 0x0 COMP0 Compare Match 0 Interrupt Enable 0 1 read-write COMP1 Compare Match 1 Interrupt Enable 1 1 read-write REP0 Repeat Counter 0 Interrupt Enable 3 1 read-write REP1 Repeat Counter 1 Interrupt Enable 4 1 read-write UF Underflow Interrupt Enable 2 1 read-write IF No Description 0x34 read-write n 0x0 0x0 COMP0 Compare Match 0 Interrupt Flag 0 1 read-write COMP1 Compare Match 1 Interrupt Flag 1 1 read-write REP0 Repeat Counter 0 Interrupt Flag 3 1 read-write REP1 Repeat Counter 1 Interrupt Flag 4 1 read-write UF Underflow Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only PRSMODE No Description 0x50 read-write n 0x0 0x0 PRSCLEARMODE PRS Clear Mode 26 2 read-write NONE PRS cannot clear the LETIMER 0 RISING Rising edge of selected PRS input can clear the LETIMER 1 FALLING Falling edge of selected PRS input can clear the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can clear the LETIMER 3 PRSSTARTMODE PRS Start Mode 18 2 read-write NONE PRS cannot start the LETIMER 0 RISING Rising edge of selected PRS input can start the LETIMER 1 FALLING Falling edge of selected PRS input can start the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 3 PRSSTOPMODE PRS Stop Mode 22 2 read-write NONE PRS cannot stop the LETIMER 0 RISING Rising edge of selected PRS input can stop the LETIMER 1 FALLING Falling edge of selected PRS input can stop the LETIMER 2 BOTH Both the rising or falling edge of the selected PRS input can stop the LETIMER 3 REP0 No Description 0x2C read-write n 0x0 0x0 REP0 Repeat Counter 0 0 8 read-write REP1 No Description 0x30 read-write n 0x0 0x0 REP1 Repeat Counter 1 0 8 read-write STATUS No Description 0x10 read-only n 0x0 0x0 RUNNING LETIMER Running 0 1 read-only SYNCBUSY No Description 0x40 read-only n 0x0 0x0 CLEAR Sync busy for CLEAR 7 1 read-only CNT Sync busy for CNT 0 1 read-only CTO0 Sync busy for CTO0 8 1 read-only CTO1 Sync busy for CTO1 9 1 read-only REP0 Sync busy for REP0 3 1 read-only REP1 Sync busy for REP1 4 1 read-only START Sync busy for START 5 1 read-only STOP Sync busy for STOP 6 1 read-only TOP Sync busy for TOP 2 1 read-only TOP No Description 0x24 read-write n 0x0 0x0 TOP Counter TOP Value 0 24 read-write TOPBUFF No Description 0x28 read-write n 0x0 0x0 TOPBUFF Buffered Counter TOP Value 0 24 read-write LFRCO_NS LFRCO_NS Registers LFRCO_NS 0x0 0x0 0x1000 registers n LFRCO 23 CAL Calibration register 0xC -1 read-write n 0x0 0x0 FREQTRIM Frequency Trim 0 8 read-write CTRL Control register 0x4 -1 read-write n 0x0 0x0 DISONDEMAND Disable On-Demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN Interrupt enable register. 0x18 read-write n 0x0 0x0 NEGEDGE Falling Edge Interrupt Enable 2 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write RDY Ready Interrupt Enable 0 1 read-write IF Interrupt flag register 0x14 read-write n 0x0 0x0 NEGEDGE Falling Edge Interrupt Flag 2 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write RDY Ready Interrupt Flag 0 1 read-write IPVERSION Contains the LFRCO ip version. 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only LOCK Configuration lock register. Locks/unlocks access to cofiguration registers. 0x20 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuaration Registers 9731 STATUS Status register 0x8 read-only n 0x0 0x0 ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 RDY Ready Status 0 1 read-only SYNCBUSY Synchronization busy register 0x1C read-only n 0x0 0x0 CAL CAL Busy 0 1 read-only LFRCO_S LFRCO_S Registers LFRCO_S 0x0 0x0 0x1000 registers n LFRCO 23 CAL Calibration register 0xC -1 read-write n 0x0 0x0 FREQTRIM Frequency Trim 0 8 read-write CTRL Control register 0x4 -1 read-write n 0x0 0x0 DISONDEMAND Disable On-Demand 1 1 read-write FORCEEN Force Enable 0 1 read-write IEN Interrupt enable register. 0x18 read-write n 0x0 0x0 NEGEDGE Falling Edge Interrupt Enable 2 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write RDY Ready Interrupt Enable 0 1 read-write IF Interrupt flag register 0x14 read-write n 0x0 0x0 NEGEDGE Falling Edge Interrupt Flag 2 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write RDY Ready Interrupt Flag 0 1 read-write IPVERSION Contains the LFRCO ip version. 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only LOCK Configuration lock register. Locks/unlocks access to cofiguration registers. 0x20 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only LOCK Lock Configuration Registers 0 UNLOCK Unlock Configuaration Registers 9731 STATUS Status register 0x8 read-only n 0x0 0x0 ENS Enabled Status 16 1 read-only LOCK Lock Status 31 1 read-only UNLOCKED Access to configuration registers not locked 0 LOCKED Access to configuration registers locked 1 RDY Ready Status 0 1 read-only SYNCBUSY Synchronization busy register 0x1C read-only n 0x0 0x0 CAL CAL Busy 0 1 read-only LFXO_NS LFXO_NS Registers LFXO_NS 0x0 0x0 0x1000 registers n LFXO 22 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x14 -1 read-write n 0x0 0x0 CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x8 -1 read-write n 0x0 0x0 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 CTRL No Description 0x4 -1 read-write n 0x0 0x0 DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FORCEEN LFXO Force Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 FAIL LFXO Failure Interrupt Enable 3 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write RDY LFXO Ready Interrupt Enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 FAIL LFXO Failure Interrupt Flag 3 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write RDY LFXO Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x24 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 STATUS No Description 0x10 read-only n 0x0 0x0 ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 RDY LFXO Ready Status 0 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 CAL LFXO Synchronization status 0 1 read-only LFXO_S LFXO_S Registers LFXO_S 0x0 0x0 0x1000 registers n LFXO 22 CAL Do not write to this register unless CALBSY in SYNCBUSY register is low. 0x14 -1 read-write n 0x0 0x0 CAPTUNE Internal Capacitance Tuning 0 7 read-write GAIN LFXO Startup Gain 8 2 read-write CFG Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared. 0x8 -1 read-write n 0x0 0x0 AGC LFXO AGC Enable 0 1 read-write HIGHAMPL LFXO High Amplitude Enable 1 1 read-write MODE LFXO Mode 4 2 read-write XTAL A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO. 0 BUFEXTCLK An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO. 1 DIGEXTCLK An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO. 2 TIMEOUT LFXO Start-up Delay 8 3 read-write CYCLES2 Timeout period of 2 cycles 0 CYCLES256 Timeout period of 256 cycles 1 CYCLES1K Timeout period of 1024 cycles 2 CYCLES2K Timeout period of 2048 cycles 3 CYCLES4K Timeout period of 4096 cycles 4 CYCLES8K Timeout period of 8192 cycles 5 CYCLES16K Timeout period of 16384 cycles 6 CYCLES32K Timeout period of 32768 cycles 7 CTRL No Description 0x4 -1 read-write n 0x0 0x0 DISONDEMAND LFXO Disable On-demand requests 1 1 read-write FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable 5 1 read-write FAILDETEN LFXO Failure Detection Enable 4 1 read-write FORCEEN LFXO Force Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 FAIL LFXO Failure Interrupt Enable 3 1 read-write NEGEDGE Falling Edge Interrupt Enable 2 1 read-write POSEDGE Rising Edge Interrupt Enable 1 1 read-write RDY LFXO Ready Interrupt Enable 0 1 read-write IF No Description 0x18 read-write n 0x0 0x0 FAIL LFXO Failure Interrupt Flag 3 1 read-write NEGEDGE Falling Edge Interrupt Flag 2 1 read-write POSEDGE Rising Edge Interrupt Flag 1 1 read-write RDY LFXO Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x24 -1 write-only n 0x0 0x0 LOCKKEY Lock Key 0 16 write-only UNLOCK Unlock LFXO lockable registers 6688 STATUS No Description 0x10 read-only n 0x0 0x0 ENS LFXO Enable Status 16 1 read-only LOCK LFXO Locked Status 31 1 read-only UNLOCKED LFXO lockable registers are not locked 0 LOCKED LFXO lockable registers are locked 1 RDY LFXO Ready Status 0 1 read-only SYNCBUSY No Description 0x20 read-only n 0x0 0x0 CAL LFXO Synchronization status 0 1 read-only MODEM_NS MODEM_NS Registers MODEM_NS 0x0 0x0 0x1000 registers n MODEM 35 AFC No Description 0x8C read-write n 0x0 0x0 AFCAVGPER AFC average period 21 3 read-write AFCDEL AFC delay 16 5 read-write AFCDELDET Delay Detection state machine 28 1 read-write AFCDSAFREQOFFEST Consider frequency offset estimation 27 1 read-write AFCENINTCOMP Internal frequency offset compensation 26 1 read-write AFCLIMRESET Reset AFCADJRX value 24 1 read-write AFCONESHOT AFC One-Shot feature 25 1 read-write AFCRXCLR AFCRX clear mode 15 1 read-write AFCRXMODE AFC RX mode 10 3 read-write DIS Disabled. 0 FREE Free running. AFCADJRX constantly updated. 1 FREEPRESTART Free running. AFCADJRX not updated before preamble is detected. 2 TIMLOCK AFCADJRX locked when timing is detected. 3 PRELOCK AFCADJRX locked when preamble is detected. 4 FRAMELOCK AFCADJRX locked when frame is detected. 5 FRAMELOCKPRESTART AFCADJRX not updated before preamble is detected and locked when frame is detected. 6 AFCSCALEE AFC scaling exponent 5 4 read-write AFCSCALEM AFC scaling mantissa 0 5 read-write AFCTXMODE AFC TX mode 13 2 read-write DIS Disabled. 0 PRELOCK AFCADJTX loaded from AFCADJRX when preamble is detected. 1 FRAMELOCK AFCADJTX loaded from AFCADJRX when frame is detected. 2 AFCADJLIM No Description 0x90 read-write n 0x0 0x0 AFCADJLIM AFC adjustment limit 0 18 read-write AFCADJRX No Description 0x14 read-only n 0x0 0x0 AFCADJRX AFC adjustment for RX 0 19 read-only AFCADJTX No Description 0x18 read-only n 0x0 0x0 AFCADJTX AFC adjustment for TX 0 19 read-only AUTOCG No Description 0x124 read-write n 0x0 0x0 AUTOCGEN Enable automatic clock gating 0 16 read-write BLEIQDSA No Description 0x230 read-write n 0x0 0x0 BLEIQDSADIFFTH1 BLEIQDSA BLEIQDSADIFFTH1 18 14 read-write BLEIQDSAEN BLEIQDSA Enable 0 1 read-write BLEIQDSAIIRCOEFPWR BLEIQDSA IIRCOEFPWR 15 3 read-write BLEIQDSATH BLEIQDSA Threshold 1 14 read-write BLEIQDSAEXT1 No Description 0x234 -1 read-write n 0x0 0x0 BLEIQDSAADDRBIAS BLEIQDSA ADDRBIAS 7 4 read-write BLEIQDSATHCOMB Threshold when i and q are added 11 14 read-write CHPWRFIRAVGEN Channel Power FIR Avg Enable 2 1 read-write CHPWRFIRAVGVAL Channel Power FIR Avg Value 3 2 read-write AVG0 No Avg 0 AVG2 2 sample avg 1 AVG4 4 sample avg 2 AVG8 8 sample avg 3 CORRIIRAVGMULFACT Corr IIR Avg Multiplication Factor 5 2 read-write FREQSCALEIQDSA I/Q DSA Frequency scale 0 2 read-write IIRRST IIR Reset 29 1 read-write MAXCORRCNTIQDSA Max Corr Cnt IQDSA 25 4 read-write BREST No Description 0x118 read-only n 0x0 0x0 BRESTINT Integer part of estimated baudrate 0 6 read-only BRESTNUM Fractional part of estimated baudrate 6 5 read-only CF No Description 0x60 read-write n 0x0 0x0 CFOSR Center Frequency Oversampling Ratio 23 3 read-write CF7 Oversampling ratio = 7 0 CF8 Oversampling ratio = 8 1 CF12 Oversampling ratio = 12 2 CF16 Oversampling ratio = 16 3 CF32 Oversampling ratio = 32 4 CF0 Center frequency set to 0 5 DEC0 First decimation 0 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO. 4 DEC1 Second decimation 3 14 read-write DEC1GAIN Second decimation filter gain 26 2 read-write ADD0 No additional gain. Suggested setting for BW higher than 1kHz 0 ADD6 6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz 1 ADD12 12 dB additional gain. Suggested setting for BW less than 250 Hz 2 DEC2 Third decimation 17 6 read-write CGCLKSTOP No Description 0x128 read-write n 0x0 0x0 FORCEOFF Manual control clocks 0 16 read-write CMD No Description 0x218 write-only n 0x0 0x0 AFCRXCLEAR Clear AFC RX compensation. 5 1 write-only AFCTXCLEAR Clear AFC TX compensation. 4 1 write-only AFCTXLOCK Lock AFC TX compensation 3 1 write-only PRESTOP Preamble stop 0 1 write-only COH0 No Description 0x158 read-write n 0x0 0x0 COHCHPWRTH0 Channel power threshold 8 8 read-write COHCHPWRTH1 Channel power threshold 16 8 read-write COHCHPWRTH2 Channel power threshold 24 8 read-write COHDYNAMICBBSSEN Dynamic BBSS enable bit 0 1 read-write COHDYNAMICPRETHRESH Dynamic preamble threshold enable bit 2 1 read-write COHDYNAMICPRETHRESHSEL Dynamic preamble threshold selection 5 3 read-write SEL0 1x sync coeff 0 SEL1 0.94x sync coeff 1 SEL2 0.88x sync coeff 2 SEL3 0.74x sync coeff 3 SEL4 0.5x sync coeff 4 COHDYNAMICSYNCTHRESH Dynamic syncword threshold enable bit 1 1 read-write COH1 No Description 0x15C read-write n 0x0 0x0 SYNCTHRESH0 Minimum correlation threshold 0 8 read-write SYNCTHRESH1 Minimum correlation threshold 8 8 read-write SYNCTHRESH2 Minimum correlation threshold 16 8 read-write SYNCTHRESH3 Minimum correlation threshold 24 8 read-write COH2 No Description 0x160 read-write n 0x0 0x0 DSAPEAKCHPWRTH DSA Peak Check CHpwr Threshold 16 8 read-write FIXEDCDTHFORIIR . 24 8 read-write SYNCTHRESHDELTA0 Syncword correlation delta threshold 0 4 read-write SYNCTHRESHDELTA1 Syncword correlation delta threshold 4 4 read-write SYNCTHRESHDELTA2 Syncword correlation delta threshold 8 4 read-write SYNCTHRESHDELTA3 Syncword correlation delta threshold 12 4 read-write COH3 No Description 0x164 read-write n 0x0 0x0 CDSS DSA Signal Selection 11 3 read-write COHDSAADDWNDSIZE DSA additional window size 1 10 read-write COHDSADETDIS DSA Detection Disable 28 1 read-write COHDSAEN DSA enable bit 0 1 read-write DSAPEAKCHKEN DSA Peak Checking Enable 14 1 read-write DSAPEAKCHPWREN DSA Peak Check channel power enable 18 1 read-write DSAPEAKINDLEN DSA Peak Index length 15 3 read-write DYNIIRCOEFOPTION Dynamic IIR 20 2 read-write LOGICBASEDCOHDEMODGATE Logic Based clock gate 19 1 read-write ONEPEAKQUALEN One Peak 22 1 read-write PEAKCHKTIMOUT Peak Check Time Out 23 5 read-write CTRL0 No Description 0x20 read-write n 0x0 0x0 CODING Symbol coding 4 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 DEMODRAWDATASEL Demod raw data select 27 3 read-write DIS Disabled. 0 ENTROPY 1-bit entropy source extracted from the RF receive chain, to be used for random number generation. 1 ADC 2 * 3-bit I and Q ADC data. 2 FILTLSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation). 3 FILTMSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation). 4 FILTFULL 2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits. 5 FREQ 8-bit received frequency data (or logarithmic amplitude for ASK/OOK). 6 DEMOD 8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected. 7 DETDIS Detection disable 21 1 read-write DIFFENCMODE Differential encoding mode 22 3 read-write DIS Differential Encoding is disabled. 0 RR0 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0. 1 RE0 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0. 2 RR1 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1. 3 RE1 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1. 4 DSSSDOUBLE DSSS double 19 2 read-write DIS Doubling is disabled. 0 INV Doubling is enabled by using inverted symbols. 1 CONJ Doubling is enabled by using complex conjugated symbols. 2 DSSSLEN DSSS length 11 5 read-write DSSSSHIFTS DSSS shifts 16 3 read-write NOSHIFT No symbols are defined by shifting. 0 SHIFT1 Next symbol generated by 1 cyclic shift. 1 SHIFT2 Next symbol generated by 2 cyclic shifts. 2 SHIFT4 Next symbol generated by 4 cyclic shifts. 3 SHIFT8 Next symbol generated by 8 cyclic shifts. 4 SHIFT16 Next symbol generated by 16 cyclic shifts. 5 DUALCORROPTDIS Dual Correlation Optimization Disable 9 1 read-write FDM0DIFFDIS Frame Detection Mode 0 disable 0 1 read-write FRAMEDETDEL FRAMEDET delay 30 2 read-write DEL0 No delay 0 DEL8 8 baud delay 1 DEL16 16 baud delay 2 DEL32 32 baud delay 3 MAPFSK Mapping of FSK symbols 1 3 read-write MAP0 4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude. 0 MAP1 4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude. 1 MAP2 4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 2 MAP3 4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 3 MAP4 4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 4 MAP5 4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 5 MAP6 4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 6 MAP7 4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 7 MODFORMAT Modulation format 6 3 read-write FSK2 Frequency Shift Keying with 2 symbols 0 FSK4 Frequency Shift Keying with 4 symbols 1 BPSK Binary Phase Shift Keying 2 DBPSK Differentially encoded Binary Phase Shift Keying 3 OQPSK Half Sine Shaped Offset Quadrature Phase Shift Keying 4 MSK Minimum Shift Keying 5 OOKASK On Off Keying and Amplitude Shift Keying 6 OOKASYNCPIN OOK asynchronous pin mode 10 1 read-write SHAPING Shaping filter 25 2 read-write DISABLED Filter disabled. 0 ODDLENGTH Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0. 1 EVENLENGTH Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0. 2 ASYMMETRIC Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7. 3 CTRL1 No Description 0x24 read-write n 0x0 0x0 COMPMODE Compensation mode 14 2 read-write DIS Compensation is disabled. 0 PRELOCK Compensation locks when preamble is detected. 1 FRAMELOCK Compensation locks when frame is detected. 2 NOLOCK Compensation is always running 3 DUALSYNC Dual sync words. 9 1 read-write DISABLED Demodulator only searches for SYNC0. 0 ENABLED Demodulator searches for SYNC0 and SYNC1 in parallel. 1 FREQOFFESTLIM Frequency offset limit 25 7 read-write FREQOFFESTPER Frequency offset estimation period 22 3 read-write PHASEDEMOD Phase demodulation 20 2 read-write BDD Bit Differential Detection. 0 MBDD Multibit Differential Detection. 1 COH Coherent Detection. 2 RESYNCPER Resync period 16 4 read-write SYNC1INV SYNC1 invert. 12 1 read-write SYNCBITS Number of sync-word bits 0 5 read-write SYNCDATA Sync data. 11 1 read-write DISABLED SYNC is not part of transmit payload. Modulator adds SYNC in transmit. 0 ENABLED SYNC is part of transmit payload. Modulator does not add SYNC in transmit. 1 SYNCERRORS Maximum number of sync errors 5 4 read-write TXSYNC Transmit sync word. 10 1 read-write SYNC0 Modulator transmits SYNC0. 0 SYNC1 Modulator transmits SYNC1. 1 CTRL2 No Description 0x28 -1 read-write n 0x0 0x0 BRDIVA Baudrate division factor A 15 4 read-write BRDIVB Baudrate division factor B 19 4 read-write DATAFILTER Datafilter 12 3 read-write DISABLED Datafilter disabled 0 SHORT Short datafilter enabled. 2*RXBRFRAC should be more than 3. 1 MEDIUM Medium datafilter enabled. 2*RXBRFRAC should be more than 4. 2 LONG Long datafilter enabled. 2*RXBRFRAC should be more than 5. 3 LEN6 Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6. 4 LEN7 Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7. 5 LEN8 Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8. 6 LEN9 Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9. 7 DEVMULA Deviation multiplication factor A 23 2 read-write DEVMULB Deviation multiplication factor B 25 2 read-write DEVWEIGHTDIS Deviation weighting disable. 29 1 read-write DMASEL DMA select. 30 2 read-write SOFT SOFTVAL field 0 CORR CORRVAL field 1 FREQOFFEST FREQOFFEST field 2 POE POE field 3 RATESELMODE Rate select mode 27 2 read-write NOCHANGE No rate change. BRDIVA/DEVMULA is used for entire frame. 0 PAYLOAD Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload. 1 FRC FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA. 2 SYNC The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA. 3 RXFRCDIS Receive FRC disable 8 1 read-write RXPINMODE Receive pin mode 9 1 read-write SYNCHRONOUS Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported. 0 ASYNCHRONOUS DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported. 1 SQITHRESH Signal Quality Indicator threshold 0 8 read-write TXPINMODE Transmit pin mode 10 2 read-write OFF Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data. 0 UNUSED Unused mode 1 ASYNCHRONOUS DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used. 2 SYNCHRONOUS DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported. 3 CTRL3 No Description 0x2C -1 read-write n 0x0 0x0 ANTDIVMODE Antenna Diversity mode 8 3 read-write ANTENNA0 Antenna 0 (ANT0=1, ANT1=0) is used 0 ANTENNA1 Antenna 1 (ANT0=0, ANT1=1) is used 1 ANTSELFIRST Select-First algorithm. 2 ANTSELCORR Select-Best algorithm based on correlation value. 3 ANTSELRSSI Select-Best algorithm based on RSSI value. 4 ANTDIVREPEATDIS Antenna diversity repeat disable 11 1 read-write PRSDINEN DIN PRS enable 0 1 read-write TSAMPDEL Timing Search Amplitude delay 14 2 read-write TSAMPLIM Timing Search Amplitude limit 16 16 read-write TSAMPMODE Timing Search Amplitude Mode 12 2 read-write OFF Amplitude is not used during timing search. 0 ON Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM. 1 DIFF Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM. 2 CTRL4 No Description 0x30 -1 read-write n 0x0 0x0 ADCSATDENS ADC Saturation Density setting 26 2 read-write ADCSATLEVEL ADC Saturation Level setting 23 3 read-write CONS1 AGC enters fast loop after first saturation sample. 0 CONS2 2 saturation samples required before AGC enters fast loop. 1 CONS4 4 saturation samples required before AGC enters fast loop. 2 CONS8 8 saturation samples required before AGC enters fast loop. 3 CONS16 16 saturation samples required before AGC enters fast loop. 4 CONS32 32 saturation samples required before AGC enters fast loop. 5 CONS64 64 saturation samples required before AGC enters fast loop. 6 DEVOFFCOMP Deviation offset compensation 4 1 read-write ISICOMP Inter Symbol Interference compensation 0 4 read-write OFFSETPHASEMASKING Offset phase masking 28 1 read-write OFFSETPHASESCALING Offset phase scaling 29 1 read-write PHASECLICKFILT Phase click filter 15 7 read-write PREDISTAVG Predistortion Average 13 1 read-write AVG8 Average over 8 samples. 0 AVG16 Average over 16 samples. 1 PREDISTDEB Predistortion debounce 10 3 read-write PREDISTGAIN Predistortion gain 5 5 read-write PREDISTRST Predistortion Reset 14 1 read-write SOFTDSSSMODE Soft DSSS mode 22 1 read-write CORR0INV Soft value is inverted value of symbol-0 correlation value. 0 CORRDIFF Soft value is difference between correlation values for symbol-0 and symbol-1. 1 CTRL5 No Description 0x34 read-write n 0x0 0x0 BBSS Baseband Signal Selection 12 4 read-write BRCALAVG Baudrate calibration averaging 4 2 read-write BRCALEN Baudrate calibration enable 1 1 read-write BRCALMODE Baudrate calibration mode 2 2 read-write PEAK Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering. 0 ZERO Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets. 1 PEAKZERO Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes. 2 DEMODRAWDATASEL2 Demod raw data select 2 20 3 read-write DIS Disabled. 0 COH Coherent demod 5-bit I and Q input data, 10-bit I and Q data after FOE/POE. 1 CORR 4-bit max_corr_index and 17-bit max_corr . 2 CHPW 8-bit channel power and 4-bit BBSSMUX 3 BBPF 11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod 4 FSM 5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes 5 DETDEL Detection delay 6 3 read-write DSSSCTD DSSS Correlation Threshold Disable 11 1 read-write FOEPREAVG Frequency Offset Estimate Pre-Averaging 24 3 read-write LINCORR Linear Correlation 27 1 read-write POEPER Phase Offset Estimation Period 16 4 read-write RESYNCBAUDTRANS Resynchronization Baud Transitions 29 1 read-write RESYNCLIMIT Resynchronization Limit 30 1 read-write HALF Adjust timing if accumulated timing is higher/lower than RESYNCPER/2. 0 ALWAYS Adjust timing if accumulated timing is non-zero. 1 TDEDGE Timing detection edge mode 9 1 read-write TREDGE Timing resynchronization edge mode 10 1 read-write CTRL6 No Description 0x38 read-write n 0x0 0x0 ARW Allow Received Window 15 2 read-write SMALLWND Allow received windows when window size is less than half the RAM size. 0 ALWAYS Always allow received windows. 1 NEVER Never allow received windows. 2 PSABORT Allow received windows right after PSTIMABORTn tests have aborted timing and coherent detection is enabled, or when window size is less than half the RAM size. 3 CODINGB Coding format 25 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 CPLXCORREN Enable Complex Correlation 20 1 read-write DSSS3SYMBOLSYNCEN Enable three symbol sync detection 21 1 read-write PREBASES Preamble Bases 7 4 read-write PSTIMABORT0 Preamble Search Timing Abort Criteria 0 11 1 read-write PSTIMABORT1 Preamble Search Timing Abort Criteria 1 12 1 read-write PSTIMABORT2 Preamble Search Timing Abort Criteria 2 13 1 read-write PSTIMABORT3 Preamble Search Timing Abort Criteria 3 14 1 read-write RXBRCALCDIS RX Baudrate Calculation Disable 30 1 read-write TDREW Timing Detection Rewind 0 7 read-write TIMTHRESHGAIN Timing Threshold Gain 17 3 read-write DCCOMP No Description 0xE0 -1 read-write n 0x0 0x0 DCCOMPEN DC Offset Compensation Enable 1 1 read-write DCCOMPFREEZE DC Offset Compensation Filter Freeze 3 1 read-write DCCOMPGEAR DC Offset Compensation Filter Gear 4 3 read-write DCESTIEN DC Offset Estimation Enable 0 1 read-write DCLIMIT DC offset limit 7 2 read-write FULLSCALE 1000 mV 0 FULLSCALEBY4 250 mV 1 FULLSCALEBY8 125 mV 2 FULLSCALEBY16 62 mV 3 DCRSTEN DC Compensation Filter Reset Enable 2 1 read-write DCCOMPFILTINIT No Description 0xE4 read-write n 0x0 0x0 DCCOMPINIT Initialize filter state 30 1 read-write DCCOMPINITVALI I-channel initialization value 0 15 read-write DCCOMPINITVALQ Q-channel initialization value 15 15 read-write DCESTI No Description 0xE8 read-only n 0x0 0x0 DCCOMPESTIVALI I-channel DC-Offset Estimated value 0 15 read-only DCCOMPESTIVALQ Q-channel DC-Offset Estimated value 15 15 read-only DIGIGAINCTRL No Description 0x23C read-write n 0x0 0x0 DEC0GAIN DEC0 Gain Select 8 1 read-write DIGIGAINDOUBLE Digital Gain Doubled 6 1 read-write DIGIGAINEN Digital Gain Enable 0 1 read-write DIGIGAINHALF Digital Gain Halved 7 1 read-write DIGIGAINSEL Digital Gain Select 1 5 read-write GAINM3 GAINM3 0 GAINM2P75 GAINM2P75 1 GAINM0P5 GAINM0P5 10 GAINM0P25 GAINM0P25 11 GAINM0 GAINM0 12 GAINP0P25 GAINP0P25 13 GAINP0P5 GAINP0P5 14 GAINP0P75 GAINP0P75 15 GAINP1 GAINP1 16 GAINP1P25 GAINP1P25 17 GAINP1P5 GAINP1P5 18 GAINP1P75 GAINP1P75 19 GAINM2P5 GAINM2P5 2 GAINP2 GAINP2 20 GAINP2P25 GAINP2P25 21 GAINP2P5 GAINP2P5 22 GAINP2P75 GAINP2P75 23 GAINP3 GAINP3 24 GAINM2P25 GAINM2P25 3 GAINM2 GAINM2 4 GAINM1P75 GAINM1P75 5 GAINM1P5 GAINM1P5 6 GAINM1P25 GAINM1P25 7 GAINM1 GAINM1 8 GAINM0P75 GAINM0P75 9 DIGMIXCTRL No Description 0x10C read-write n 0x0 0x0 DIGMIXFREQ Digital mixer frequency control word 0 20 read-write DIGMIXMODE Digital mixer frequency control 20 1 read-write CFOSR Mixer frequency specified by CFOSR. 0 DIGMIXFREQ Mixer frequency specified by DIGMIXFREQ. 1 MIXERCONJ Digital mixer input conjugate 21 1 read-write DIRECTMODE No Description 0x134 -1 read-write n 0x0 0x0 CLKWIDTH Synchronous mode clock pulse width 8 5 read-write DMENABLE Enable Direct Mode 0 1 read-write SYNCASYNC Choose Synchronous or Asynchronous mode 1 1 read-write SYNCPREAM Synchronous mode preamble 2 2 read-write ADD0 No preamble bits appended 0 ADD8 8 preamble bits appended 1 ADD16 16 preamble bits appended 2 ADD32 32 preamble bits appended 3 DSACTRL No Description 0xFC -1 read-write n 0x0 0x0 AGCBAUDEN Consider Baud_en from AGC 27 1 read-write AMPJUPTHD Amplitude jump detection thrshold 28 4 read-write ARRTHD Signal arrival valid counter threshold 2 4 read-write ARRTOLERTHD0 Arrival tolerance threshold 0 6 5 read-write ARRTOLERTHD1 Arrival tolerance threshold 1 11 5 read-write DSAMODE Mode of Digital Signal Arrival detector 0 2 read-write DISABLED DSA is disabled 0 ENABLED DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects. 1 DSARSTON DSA detection reset 19 1 read-write FREQAVGSYM DSA frequency estimation averaging 17 1 read-write AVG2TS Frequency estimation over 2 symbol periods. 0 AVG4TS Frequency estimation over 4 symbol periods. 1 GAINREDUCDLY Detection Delay of AGC gain reduction 21 2 read-write LOWDUTY Low duty cycle delay 23 3 read-write RESTORE Power detector reset of DSA 26 1 read-write SCHPRD Search period window length 16 1 read-write TS2 The search period is 2 symbol periods. 0 TS4 The search period is 4 symbol periods. 1 TRANRSTDSA power transient detector Reset DSA 18 1 read-write DSATHD0 No Description 0xF4 -1 read-write n 0x0 0x0 FDEVMAXTHD Frequency deviation maximum threshold 20 12 read-write FDEVMINTHD Frequency deviation minimum threshold 14 6 read-write SPIKETHD Spike threshold 0 8 read-write UNMODTHD Unmodulated carrier detector threshold 8 6 read-write DSATHD1 No Description 0xF8 -1 read-write n 0x0 0x0 AMPFLTBYP Amplitude filter bypass 28 1 read-write DSARSTCNT DSA reset counter 18 3 read-write FREQLATDLY Frequency late delay 25 2 read-write FREQSCALE Frequency scale factor 30 1 read-write POWABSTHD Power absolute threshold 0 16 read-write POWRELTHD Relative power detector threshold 16 2 read-write DISABLED Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI. 0 MODE1 Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI. 1 MODE2 Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI. 2 MODE3 Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI. 3 PWRDETDIS Power detection disabled 29 1 read-write PWRFLTBYP Power filter bypass 27 1 read-write RSSIJMPTHD RSSI jump detector threshold 21 4 read-write DSATHD2 No Description 0x130 -1 read-write n 0x0 0x0 FDADJTHD Frequency deviation ripple threshold 10 6 read-write FREQESTTHD Frequency Estimation Timeout Threshold 20 5 read-write INTERFERDET Interference detection threshold 25 5 read-write JUMPDETEN Power jump detection enable 9 1 read-write PMDETFORCE Force DSA preamble detector 30 1 read-write PMDETPASSTHD DSA Preamble detection counter threshold 16 4 read-write POWABSTHDLOG Power threshold in logarithm-scale 0 8 read-write DSATHD3 No Description 0x168 -1 read-write n 0x0 0x0 FDEVMAXTHDLO Frequency deviation maximum threshold 20 12 read-write FDEVMINTHDLO Frequency deviation minimum threshold 14 6 read-write SPIKETHDLO Spike threshold 0 8 read-write UNMODTHDLO Unmodulated carrier detector threshold 8 6 read-write DSATHD4 No Description 0x16C -1 read-write n 0x0 0x0 ARRTOLERTHD0LO Arrival tolerance threshold 0 16 5 read-write ARRTOLERTHD1LO Arrival tolerance threshold 1 21 5 read-write POWABSTHDLO Power absolute threshold for low power 0 16 read-write SWTHD Enable switch threshold for low power 26 1 read-write DSSS0 No Description 0x84 read-write n 0x0 0x0 DSSS0 DSSS symbol 0 0 32 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FREQOFFEST No Description 0x10 read-only n 0x0 0x0 CORRVAL Correlation value 16 8 read-only FREQOFFEST Frequency offset estimate 0 13 read-only SOFTVAL Soft detection value 24 8 read-only FSMSTATUS No Description 0x21C read-only n 0x0 0x0 DETSTATE Detection FSM state 0 7 read-only OFF Off state 0 TIMINGSEARCH Timing search 10 PRESEARCH Preamble search 20 FRAMESEARCH Frame search 30 RXFRAME Payload Detection 40 FRAMEDETMODE0 Timing search with sliding window (FDM0) 50 DSASTATE Demodulator DSA FSM state 7 3 read-only IDLE IDLE state 0 ARRIVALCHK Arrival Check 1 STATUSCHK Status Check 2 SAMPPW SAMP_PW 3 WAITPWRUP WAIT_PWRUP 4 WAITDSALO WAIT_DSALO 5 WAITABORT WAIT_ABORT 6 STOP STOP 7 LRBLESTATE Demodulator long-range BLE FSM state 10 5 read-only IDLE IDLE state 0 CLEANUP CLEANUP 1 FEC2ACK FEC2_ACK 10 TRACKCUR TRACK_CUR 11 TRACKEAR TRACK_EAR 12 TRACKLAT TRACK_LAT 13 TRACKDONE TRACK_DONE 14 TDECISION T_DECISION 15 STOP STOP 16 CORRCOE CORRCOE 2 WAITLRDSA WAIT_LR_DSA 3 MAXCORR MAXCORR 4 WAITRDY WAIT_RDY 5 FEC1DATA FEC1_DATA 6 FEC1ACK FEC1_ACK 7 PAUSE PAUSE 8 FEC2DATA FEC2_DATA 9 NBBLESTATE Demodulator Narrow-band BLE FSM state 15 5 read-only IDLE IDLE state 0 VTINITI VTINITI 1 TIMINGACQUEARLY TIMING_ACQU_EARLY 10 TIMINGACQUCURR TIMING_ACQU_CURR 11 TIMINGACQULATE TIMING_ACQU_LATE 12 TIMINGACQUDONE TIMING_ACQU_DONE 13 VIRTBIINIT0 VIRTBI_INIT0 14 VIRTBIINIT1 VIRTBI_INIT1 15 VIRTBIRXSYNC VIRTBI_RXSYNC 16 VIRTBIRXPAYLOAD VIRTBI_RXPAYLOAD 17 HARDRXSYNC HARD_RXSYNC 18 HARDXPAYLOAD HARD_RXPAYLOAD 19 ADDRNXT ADDR_NXT 2 TRACKFREQ TRACK_FREQ 20 TRACKTIMEARLY TRACK_TIM_EARLY 21 TRACKTIMCURR TRACK_TIM_CURR 22 TRACKTIMLATE TRACK_TIM_LATE 23 TRACKDONE TRACK_DONE 24 TRACKDECISION TRACK_DECISION 25 STOP STOP 26 WAITACK WAIT_ACK 27 DEBUG DEBUG 28 INICOST INI_COST 3 CALCCOST CALC_COST 4 INITALACQU INITAL_ACQU 5 INITALCOSTCALC INITAL_COST_CALC 6 MINCOSTCALC MIN_COST_CALC 7 FREQACQU FREQ_ACQU 8 FREQACQUDONE FREQ_ACQU_DONE 9 IEN No Description 0x20C read-write n 0x0 0x0 FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXPREDET Preamble detected 9 1 read-write RXPRELOST Preamble lost 13 1 read-write RXTIMDET Timing detected 8 1 read-write RXTIMLOST Timing lost 12 1 read-write RXTIMNF Timing not found 15 1 read-write TXFRAMESENT Frame sent 0 1 read-write TXPRESENT Preamble sent 2 1 read-write TXSYNCSENT Sync word sent 1 1 read-write IF No Description 0x208 read-write n 0x0 0x0 FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXPREDET Preamble detected 9 1 read-write RXPRELOST Preamble lost 13 1 read-write RXTIMDET Timing detected 8 1 read-write RXTIMLOST Timing lost 12 1 read-write RXTIMNF Timing not found 15 1 read-write TXFRAMESENT Frame sent 0 1 read-write TXPRESENT Preamble sent 2 1 read-write TXSYNCSENT Sync word sent 1 1 read-write INTAFC No Description 0xF0 read-write n 0x0 0x0 FOEPREAVG0 First estimate 0 3 read-write FOEPREAVG1 Second estimate 3 3 read-write FOEPREAVG2 Third estimate 6 3 read-write FOEPREAVG3 Fourth estimate 9 3 read-write FOEPREAVG4 Fifth estimate 12 3 read-write FOEPREAVG5 Sixth estimate 15 3 read-write FOEPREAVG6 Seventh estimate 18 3 read-write FOEPREAVG7 Eighth estimate 21 3 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only IRCAL No Description 0x228 read-write n 0x0 0x0 IRCALEN IRCAL enable bit 0 1 read-write IRCORREN IR Correction enable bit 13 1 read-write MUISHF MUI shift value 7 6 read-write MURSHF MUR shift value 1 5 read-write IRCALCOEF No Description 0x22C read-only n 0x0 0x0 CIV CIV coefficient 16 15 read-only CRV CRV coefficient 0 15 read-only IRCALCOEFWR0 No Description 0x250 read-write n 0x0 0x0 CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write IRCALCOEFWR1 No Description 0x254 read-write n 0x0 0x0 CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write LONGRANGE No Description 0x138 -1 read-write n 0x0 0x0 LRBLE Enable 15 1 read-write LRBLEDSA DSA enable 27 1 read-write LRCORRSCHWIN Window size 11 4 read-write LRCORRTHD Correlator threshold 0 11 read-write LRCORRTHDDYNEN Correlator THD dynamic enable 31 1 read-write LRDEC DEC value 28 3 read-write LRTIMCORRTHD Correlator threshold 16 11 read-write LONGRANGE1 No Description 0x13C read-write n 0x0 0x0 AVGWIN Average window 21 3 read-write CHPWRACCUDEL Channel Power Accumulated Delay 16 2 read-write DEL0 Use accumulated channel power value 0 DEL32 Delayed by 32 chips 1 DEL64 Delayed by 64 chips 2 HYSVAL Hysteresis Value for BBSS 18 3 read-write LOGICBASEDLRDEMODGATE Logic Based Long Range Demod Gating 29 1 read-write LOGICBASEDPUGATE Logic Based Phase Unwrap Gating 28 1 read-write LRSPIKETHADD Long Range DSA spike threshold addition 24 4 read-write LRSS Long Range Signal Selection 0 4 read-write LRTIMEOUTTHD Long Range Time Out Threshold 4 11 read-write LONGRANGE2 No Description 0x140 read-write n 0x0 0x0 LRCHPWRTH1 Long Range channel power threshold 0 8 read-write LRCHPWRTH2 Long Range channel power threshold 8 8 read-write LRCHPWRTH3 Long Range channel power threshold 16 8 read-write LRCHPWRTH4 Long Range channel power threshold 24 8 read-write LONGRANGE3 No Description 0x144 read-write n 0x0 0x0 LRCHPWRTH5 Long Range channel power threshold 0 8 read-write LRCHPWRTH6 Long Range channel power threshold 8 8 read-write LRCHPWRTH7 Long Range channel power threshold 16 8 read-write LRCHPWRTH8 Long Range channel power threshold 24 8 read-write LONGRANGE4 No Description 0x148 read-write n 0x0 0x0 LRCHPWRSH1 Long Range channel power shift 16 4 read-write LRCHPWRSH2 Long Range channel power shift 20 4 read-write LRCHPWRSH3 Long Range channel power shift 24 4 read-write LRCHPWRSH4 Long Range channel power shift 28 4 read-write LRCHPWRTH10 Long Range channel power threshold 8 8 read-write LRCHPWRTH9 Long Range channel power threshold 0 8 read-write LONGRANGE5 No Description 0x14C read-write n 0x0 0x0 LRCHPWRSH10 Long Range channel power shift 20 4 read-write LRCHPWRSH11 Long Range channel power shift 24 4 read-write LRCHPWRSH5 Long Range channel power shift 0 4 read-write LRCHPWRSH6 Long Range channel power shift 4 4 read-write LRCHPWRSH7 Long Range channel power shift 8 4 read-write LRCHPWRSH8 Long Range channel power shift 12 4 read-write LRCHPWRSH9 Long Range channel power shift 16 4 read-write LONGRANGE6 No Description 0x150 read-write n 0x0 0x0 LRCHPWRSH12 Long Range channel power shift 28 4 read-write LRCHPWRSPIKETH Long Range channel power spike threshold 0 8 read-write LRCHPWRTH11 Long Range channel power threshold 20 8 read-write LRSPIKETHD Long Range spike threshold 8 11 read-write LRFRC No Description 0x154 -1 read-write n 0x0 0x0 CI500 Long Range CI mapping for 500kbps 0 2 read-write FRCACKTIMETHD FRC acknowledge timeout threshold 2 6 read-write MIXCTRL No Description 0x1C read-write n 0x0 0x0 ANAMIXMODE Analog receiver mixer mode of operation 0 4 read-write NORMAL The analog mixer operates in its normal mode 0 IPQPIQSWAP I path is positive, Q path is positive, I and Q are swapped 1 IPQN I path is positive, Q path is negative 2 IPQNIQSWAP I path is positive, Q path is negative, I and Q are swapped 3 INQP I path is negative, Q path is positive 4 INQPIQSWAP I path is negative, Q path is positive, I and Q are swapped 5 INQN I path is negative, Q path is negative 6 INQNIQSWAP I path is negative, Q path is negative, I and Q are swapped 7 UPCONVERT Control the analog receiver mixer such that the analog mixer performs a digital up-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. This mode may be used to perform RF loopback using the normal synthesizer both for transmit and receive, and still get a positive IF frequency on the IF receive signal. 8 DOWNCONVERT Control the analog receiver mixer such that the analog mixer performs a digital down-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. 9 DIGIQSWAPEN Digital I/Q swap enable 4 1 read-write MODINDEX No Description 0x88 read-write n 0x0 0x0 FREQGAINE Frequency demodulation gain - exponent 16 3 read-write FREQGAINM Frequency demodulation gain - mantissa 19 3 read-write MODINDEXE Modulation index exponent. 5 5 read-write MODINDEXM Modulation index mantissa. 0 5 read-write POE No Description 0x12C read-only n 0x0 0x0 POEI In-phase component of POE. 0 10 read-only POEQ Quadrature component of POE. 16 10 read-only PRE No Description 0x64 read-write n 0x0 0x0 BASE Preamble base 0 4 read-write BASEBITS BASE bits 4 2 read-write DSSSPRE DSSS preamble 11 1 read-write PREERRORS Preamble errors 7 4 read-write PRESYMB4FSK Preamble symbols 4-FSK 6 1 read-write OUTER Symbols corresponding to +/- 3dev. 0 INNER Symbols corresponding to +/- dev. 1 SYNCSYMB4FSK Sync symbols 4FSK 12 1 read-write FSK2 The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK. 0 FSK4 The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol. 1 TXBASES TX bases 16 16 read-write PRSCTRL No Description 0x240 read-write n 0x0 0x0 ADVANCESEL None 2 2 read-write ANT0SEL None 14 2 read-write ANT1SEL None 16 2 read-write LOWCORRSEL None 12 2 read-write NEWWNDSEL None 4 2 read-write POSTPONESEL None 0 2 read-write PRESENTSEL None 10 2 read-write SYNCSENTSEL None 8 2 read-write WEAKSEL None 6 2 read-write RAMPCTRL No Description 0xC0 -1 read-write n 0x0 0x0 RAMPRATE0 Ramp rate 0 0 4 read-write RAMPRATE1 Ramp rate 1 4 4 read-write RAMPRATE2 Ramp rate 2 8 4 read-write RAMPLEV No Description 0xC4 -1 read-write n 0x0 0x0 RAMPLEV0 Ramp level 0 0 8 read-write RAMPLEV1 Ramp level 1 8 8 read-write RAMPLEV2 Ramp level 2 16 8 read-write RXBR No Description 0x5C read-write n 0x0 0x0 RXBRDEN Receive baudrate denominator 5 5 read-write RXBRINT Receive baudrate integer 10 3 read-write RXBRNUM Receive baudrate numerator 0 5 read-write SHAPING0 No Description 0x94 -1 read-write n 0x0 0x0 COEFF0 Shaping Coefficient 0 0 8 read-write COEFF1 Shaping Coefficient 1 8 8 read-write COEFF2 Shaping Coefficient 2 16 8 read-write COEFF3 Shaping Coefficient 3 24 8 read-write SHAPING1 No Description 0x98 -1 read-write n 0x0 0x0 COEFF4 Shaping Coefficient 4 0 8 read-write COEFF5 Shaping Coefficient 5 8 8 read-write COEFF6 Shaping Coefficient 6 16 8 read-write COEFF7 Shaping Coefficient 7 24 8 read-write SHAPING2 No Description 0x9C read-write n 0x0 0x0 COEFF10 Shaping Coefficient 10 16 8 read-write COEFF11 Shaping Coefficient 11 24 8 read-write COEFF8 Shaping Coefficient 8 0 8 read-write COEFF9 Shaping Coefficient 9 8 8 read-write SHAPING3 No Description 0xA0 read-write n 0x0 0x0 COEFF12 Shaping Coefficient 12 0 8 read-write COEFF13 Shaping Coefficient 13 8 8 read-write COEFF14 Shaping Coefficient 14 16 8 read-write COEFF15 Shaping Coefficient 15 24 8 read-write SHAPING4 No Description 0xA4 read-write n 0x0 0x0 COEFF16 Shaping Coefficient 16 0 6 read-write COEFF17 Shaping Coefficient 17 6 6 read-write COEFF18 Shaping Coefficient 18 12 6 read-write COEFF19 Shaping Coefficient 19 18 5 read-write COEFF20 Shaping Coefficient 20 23 5 read-write COEFF21 Shaping Coefficient 21 28 4 read-write SHAPING5 No Description 0xA8 read-write n 0x0 0x0 COEFF22 Shaping Coefficient 22 0 4 read-write COEFF23 Shaping Coefficient 23 4 4 read-write COEFF24 Shaping Coefficient 24 8 4 read-write COEFF25 Shaping Coefficient 25 12 4 read-write COEFF26 Shaping Coefficient 26 16 4 read-write COEFF27 Shaping Coefficient 27 20 4 read-write COEFF28 Shaping Coefficient 28 24 4 read-write COEFF29 Shaping Coefficient 29 28 4 read-write SHAPING6 No Description 0xAC read-write n 0x0 0x0 COEFF30 Shaping Coefficient 30 0 4 read-write COEFF31 Shaping Coefficient 31 4 4 read-write COEFF32 Shaping Coefficient 32 8 3 read-write COEFF33 Shaping Coefficient 33 11 3 read-write COEFF34 Shaping Coefficient 34 14 3 read-write COEFF35 Shaping Coefficient 35 17 3 read-write COEFF36 Shaping Coefficient 36 20 3 read-write COEFF37 Shaping Coefficient 37 23 3 read-write COEFF38 Shaping Coefficient 38 26 3 read-write COEFF39 Shaping Coefficient 39 29 3 read-write SRCCHF No Description 0xEC read-write n 0x0 0x0 BWSEL Channel filter bandwidth 29 2 read-write X0 wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor 0 X1 wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor 1 X2 narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor 2 X3 narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor 3 INTOSR Forcing Integer OSR 31 1 read-write SRCENABLE1 SRC1 enable 11 1 read-write SRCENABLE2 SRC2 enable 27 1 read-write SRCRATIO1 I-channel SRC ratio 0 8 read-write SRCRATIO2 Q-channel SRC ratio 12 15 read-write STATUS No Description 0x8 read-only n 0x0 0x0 ANTSEL Selected Antenna 5 1 read-only ANTENNA0 Antenna 0 is selected (ANT0 = 1 and ANT1 = 0). 0 ANTENNA1 Antenna 1 is selected (ANT0 = 0 and ANT1 = 1). 1 CORR Correlation 16 8 read-only DEMODSTATE DEMOD state 0 3 read-only OFF Off state 0 TIMINGSEARCH Timing search 1 PRESEARCH Preamble search 2 FRAMESEARCH Frame search 3 RXFRAME Payload Detection 4 FRAMEDETMODE0 Timing search with sliding window (FDM0) 5 DSADETECTED DSA detected 8 1 read-only DSAFREQESTDONE DSA frequency estimation complete 9 1 read-only FRAMEDETID Frame Detected ID 4 1 read-only FRAMEDET0 Last frame was detected with sync word defined in SYNC0. 0 FRAMEDET1 Last frame was detected with sync word defined in SYNC1. 1 STAMPSTATE BLE Viterbi Demod Timing Stamp 12 3 read-only TIMLOSTCAUSE Timing Lost Cause 7 1 read-only LOWCORR Timing lost during Preamble Search or due to low correlation value during Frame Search. 0 TIMEOUT Timing lost due to incorrect symbols detected during Frame Search. 1 TIMSEQINV Timing Sequence Inverted 6 1 read-only VITERBIDEMODFRAMEDET Viterbi Demod frame detected 11 1 read-only VITERBIDEMODTIMDET Viterbi Demod timing detected 10 1 read-only WEAKSYMBOLS Weak symbols 24 8 read-only STATUS2 No Description 0x220 read-only n 0x0 0x0 BBSSMUX Actual Baseband Signal Selection 8 4 read-only CHPWRACCUMUX Channel power 0 8 read-only LRBLECI RXed packet's LR BLE coding indicator 12 2 read-only LR125k FEC block 2 coded using C=8, 125kbps 0 LR500k FEC block 2 coded using C=2, 500kbps 1 STATUS3 No Description 0x224 read-only n 0x0 0x0 BBPFOUTABS Pre-filter Correlation Output for BLR 11 11 read-only BBPFOUTABS1 Pre-filter Correlation Output 0 11 read-only COHDSADET DSA prefilter above CDTH 25 1 read-only COHDSALIVE COHDSA Prefilter above CDTH 23 1 read-only LRDSADET DSA prefilter above LRSPIKETHD 24 1 read-only LRDSALIVE BLRDSA Prefilter above LRSPIKETHD 22 1 read-only SYNCSECPEAKABTH SYNC second peak above threshold 26 1 read-only SYNC0 No Description 0x68 read-write n 0x0 0x0 SYNC0 Sync-word 0 0 32 read-write SYNC1 No Description 0x6C read-write n 0x0 0x0 SYNC1 Sync word 1 0 32 read-write SYNCPROPERTIES No Description 0x238 read-write n 0x0 0x0 SYNCCORRCLR Sync auto corr clear bit 0 1 read-write SYNCSECPEAKTH SYNC auto corr second peak threshold 1 7 read-write TIMDETSTATUS No Description 0xC read-only n 0x0 0x0 TIMDETCORR Correlation value 0 8 read-only TIMDETFREQOFFEST Frequency offset estimate 8 8 read-only TIMDETINDEX Timing detection index 25 4 read-only TIMDETPASS Timing detection pass 24 1 read-only TIMDETPREERRORS Preamble errors 16 4 read-only TIMING No Description 0x80 read-write n 0x0 0x0 ADDTIMSEQ Additional timing sequences 12 4 read-write FASTRESYNC Fast timing resynchronization 30 2 read-write DIS Disabled. 0 PREDET Allow fast resynchronization until preamble is detected. 1 FRAMEDET Allow fast resynchronization until frame is detected. 2 FDM0THRESH Frame Detection Mode 0 threshold 18 3 read-write OFFSUBDEN Offset subperiod denominator 25 4 read-write OFFSUBNUM Offset subperiod numerator 21 4 read-write TIMINGBASES Timing bases 8 4 read-write TIMSEQINVEN Timing sequence inversion enable 16 1 read-write TIMSEQSYNC Timing sequence part of sync-word 17 1 read-write TIMTHRESH Timing threshold 0 8 read-write TSAGCDEL Timing Search AGC delay 29 1 read-write TXBR No Description 0x58 read-write n 0x0 0x0 TXBRDEN Transmit baudrate denominator 16 8 read-write TXBRNUM Transmit baudrate numerator 0 16 read-write VITERBIDEMOD No Description 0x100 -1 read-write n 0x0 0x0 CORRCYCLE Correction cycles 23 4 read-write CORRSTPSIZE Correction step size 27 4 read-write DISDEMODOF Disable Demod Over Flow Detection 31 1 read-write HARDDECISION Hard decision 1 1 read-write SYNTHAFC Synthesizer AFC in Viterbi demod 22 1 read-write VITERBIKSI1 VITERBI KSI1 2 7 read-write VITERBIKSI2 VITERBI KSI2 9 7 read-write VITERBIKSI3 VITERBI KSI3 16 6 read-write VTDEMODEN Viterbi demodulator enable 0 1 read-write VTBLETIMING No Description 0x170 read-write n 0x0 0x0 FLENOFF Timing Stamp Frame Length Offset 12 4 read-write TIMINGDELAY Viterbi BLE Delay timer 4 8 read-write VTBLETIMINGSEL Viterbi BLE timing stamp selection 0 2 read-write FRAMEDET_DELAY Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod. 0 END_FRAME_PULSE The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle. 1 END_FRAME The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal 2 INV_END_FRAME For testing only. 3 VTCORRCFG0 No Description 0x104 -1 read-write n 0x0 0x0 EXPECTPATT Expected pattern 0 32 read-write VTCORRCFG1 No Description 0x110 -1 read-write n 0x0 0x0 BUFFHEAD Buffer header 23 4 read-write CORRSHFTLEN Correlator shift length 0 6 read-write EXPECTHT Expected patterns head and tail 27 4 read-write EXPSYNCLEN Expected sync length 15 8 read-write VTFRQLIM Viterbi frequency limiter 6 9 read-write VTTRACK No Description 0x114 -1 read-write n 0x0 0x0 FREQBIAS Frequency estimation bias 18 4 read-write FREQTRACKMODE Frequency tracking mode 0 2 read-write DISABLED Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA. 0 MODE1 Frequency tracking enabled with one correction, when needed, every 16 symbol periods. 1 MODE2 Frequency tracking enabled with one correction, when needed, every 32 symbol periods. 2 MODE3 Frequency tracking enabled with one correction, when needed, every 48 symbol periods. 3 HIPWRTHD High Power detection threshold 22 8 read-write TIMCHK Time check 14 1 read-write TIMEACQUTHD Time acquisition threshold 6 8 read-write TIMEOUTMODE Timeout mode 15 1 read-write TIMGEAR Timing Gear 16 2 read-write GEAR0 Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3 0 GEAR1 Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear. 1 GEAR2 Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear. 2 TIMTRACKTHD Timing tracking threshold 2 4 read-write MODEM_S MODEM_S Registers MODEM_S 0x0 0x0 0x1000 registers n MODEM 35 AFC No Description 0x8C read-write n 0x0 0x0 AFCAVGPER AFC average period 21 3 read-write AFCDEL AFC delay 16 5 read-write AFCDELDET Delay Detection state machine 28 1 read-write AFCDSAFREQOFFEST Consider frequency offset estimation 27 1 read-write AFCENINTCOMP Internal frequency offset compensation 26 1 read-write AFCLIMRESET Reset AFCADJRX value 24 1 read-write AFCONESHOT AFC One-Shot feature 25 1 read-write AFCRXCLR AFCRX clear mode 15 1 read-write AFCRXMODE AFC RX mode 10 3 read-write DIS Disabled. 0 FREE Free running. AFCADJRX constantly updated. 1 FREEPRESTART Free running. AFCADJRX not updated before preamble is detected. 2 TIMLOCK AFCADJRX locked when timing is detected. 3 PRELOCK AFCADJRX locked when preamble is detected. 4 FRAMELOCK AFCADJRX locked when frame is detected. 5 FRAMELOCKPRESTART AFCADJRX not updated before preamble is detected and locked when frame is detected. 6 AFCSCALEE AFC scaling exponent 5 4 read-write AFCSCALEM AFC scaling mantissa 0 5 read-write AFCTXMODE AFC TX mode 13 2 read-write DIS Disabled. 0 PRELOCK AFCADJTX loaded from AFCADJRX when preamble is detected. 1 FRAMELOCK AFCADJTX loaded from AFCADJRX when frame is detected. 2 AFCADJLIM No Description 0x90 read-write n 0x0 0x0 AFCADJLIM AFC adjustment limit 0 18 read-write AFCADJRX No Description 0x14 read-only n 0x0 0x0 AFCADJRX AFC adjustment for RX 0 19 read-only AFCADJTX No Description 0x18 read-only n 0x0 0x0 AFCADJTX AFC adjustment for TX 0 19 read-only AUTOCG No Description 0x124 read-write n 0x0 0x0 AUTOCGEN Enable automatic clock gating 0 16 read-write BLEIQDSA No Description 0x230 read-write n 0x0 0x0 BLEIQDSADIFFTH1 BLEIQDSA BLEIQDSADIFFTH1 18 14 read-write BLEIQDSAEN BLEIQDSA Enable 0 1 read-write BLEIQDSAIIRCOEFPWR BLEIQDSA IIRCOEFPWR 15 3 read-write BLEIQDSATH BLEIQDSA Threshold 1 14 read-write BLEIQDSAEXT1 No Description 0x234 -1 read-write n 0x0 0x0 BLEIQDSAADDRBIAS BLEIQDSA ADDRBIAS 7 4 read-write BLEIQDSATHCOMB Threshold when i and q are added 11 14 read-write CHPWRFIRAVGEN Channel Power FIR Avg Enable 2 1 read-write CHPWRFIRAVGVAL Channel Power FIR Avg Value 3 2 read-write AVG0 No Avg 0 AVG2 2 sample avg 1 AVG4 4 sample avg 2 AVG8 8 sample avg 3 CORRIIRAVGMULFACT Corr IIR Avg Multiplication Factor 5 2 read-write FREQSCALEIQDSA I/Q DSA Frequency scale 0 2 read-write IIRRST IIR Reset 29 1 read-write MAXCORRCNTIQDSA Max Corr Cnt IQDSA 25 4 read-write BREST No Description 0x118 read-only n 0x0 0x0 BRESTINT Integer part of estimated baudrate 0 6 read-only BRESTNUM Fractional part of estimated baudrate 6 5 read-only CF No Description 0x60 read-write n 0x0 0x0 CFOSR Center Frequency Oversampling Ratio 23 3 read-write CF7 Oversampling ratio = 7 0 CF8 Oversampling ratio = 8 1 CF12 Oversampling ratio = 12 2 CF16 Oversampling ratio = 16 3 CF32 Oversampling ratio = 32 4 CF0 Center frequency set to 0 5 DEC0 First decimation 0 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO. 4 DEC1 Second decimation 3 14 read-write DEC1GAIN Second decimation filter gain 26 2 read-write ADD0 No additional gain. Suggested setting for BW higher than 1kHz 0 ADD6 6 dB additional gain. Suggested setting for BW between 250 Hz and 1 kHz 1 ADD12 12 dB additional gain. Suggested setting for BW less than 250 Hz 2 DEC2 Third decimation 17 6 read-write CGCLKSTOP No Description 0x128 read-write n 0x0 0x0 FORCEOFF Manual control clocks 0 16 read-write CMD No Description 0x218 write-only n 0x0 0x0 AFCRXCLEAR Clear AFC RX compensation. 5 1 write-only AFCTXCLEAR Clear AFC TX compensation. 4 1 write-only AFCTXLOCK Lock AFC TX compensation 3 1 write-only PRESTOP Preamble stop 0 1 write-only COH0 No Description 0x158 read-write n 0x0 0x0 COHCHPWRTH0 Channel power threshold 8 8 read-write COHCHPWRTH1 Channel power threshold 16 8 read-write COHCHPWRTH2 Channel power threshold 24 8 read-write COHDYNAMICBBSSEN Dynamic BBSS enable bit 0 1 read-write COHDYNAMICPRETHRESH Dynamic preamble threshold enable bit 2 1 read-write COHDYNAMICPRETHRESHSEL Dynamic preamble threshold selection 5 3 read-write SEL0 1x sync coeff 0 SEL1 0.94x sync coeff 1 SEL2 0.88x sync coeff 2 SEL3 0.74x sync coeff 3 SEL4 0.5x sync coeff 4 COHDYNAMICSYNCTHRESH Dynamic syncword threshold enable bit 1 1 read-write COH1 No Description 0x15C read-write n 0x0 0x0 SYNCTHRESH0 Minimum correlation threshold 0 8 read-write SYNCTHRESH1 Minimum correlation threshold 8 8 read-write SYNCTHRESH2 Minimum correlation threshold 16 8 read-write SYNCTHRESH3 Minimum correlation threshold 24 8 read-write COH2 No Description 0x160 read-write n 0x0 0x0 DSAPEAKCHPWRTH DSA Peak Check CHpwr Threshold 16 8 read-write FIXEDCDTHFORIIR . 24 8 read-write SYNCTHRESHDELTA0 Syncword correlation delta threshold 0 4 read-write SYNCTHRESHDELTA1 Syncword correlation delta threshold 4 4 read-write SYNCTHRESHDELTA2 Syncword correlation delta threshold 8 4 read-write SYNCTHRESHDELTA3 Syncword correlation delta threshold 12 4 read-write COH3 No Description 0x164 read-write n 0x0 0x0 CDSS DSA Signal Selection 11 3 read-write COHDSAADDWNDSIZE DSA additional window size 1 10 read-write COHDSADETDIS DSA Detection Disable 28 1 read-write COHDSAEN DSA enable bit 0 1 read-write DSAPEAKCHKEN DSA Peak Checking Enable 14 1 read-write DSAPEAKCHPWREN DSA Peak Check channel power enable 18 1 read-write DSAPEAKINDLEN DSA Peak Index length 15 3 read-write DYNIIRCOEFOPTION Dynamic IIR 20 2 read-write LOGICBASEDCOHDEMODGATE Logic Based clock gate 19 1 read-write ONEPEAKQUALEN One Peak 22 1 read-write PEAKCHKTIMOUT Peak Check Time Out 23 5 read-write CTRL0 No Description 0x20 read-write n 0x0 0x0 CODING Symbol coding 4 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 DEMODRAWDATASEL Demod raw data select 27 3 read-write DIS Disabled. 0 ENTROPY 1-bit entropy source extracted from the RF receive chain, to be used for random number generation. 1 ADC 2 * 3-bit I and Q ADC data. 2 FILTLSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTLSB setting outputs the 16 least significant bits (with saturation). 3 FILTMSB 2 * 16-bit I and Q channel filtered data downmixed to zero-IF. The receive signal chain has 19 bits dynamic range at this point, and the FILTMSB setting outputs the 16 most significant bits (with truncation). 4 FILTFULL 2 * 19-bit I and Q channel filtered data downmixed to zero-IF. The FILTFULL option will output all 19 bits of dynamic range, sign extended to 32 bits. 5 FREQ 8-bit received frequency data (or logarithmic amplitude for ASK/OOK). 6 DEMOD 8-bit demodulated data (freq/amp/phase). When coherent detection is enabled, only the in-phase component is selected. 7 DETDIS Detection disable 21 1 read-write DIFFENCMODE Differential encoding mode 22 3 read-write DIS Differential Encoding is disabled. 0 RR0 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 0. 1 RE0 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 0. 2 RR1 Transmit the XOR-ed value of the Raw symbol and the last Raw symbol. Initial Raw symbol is 1. 3 RE1 Transmit the XOR-ed value of the Raw symbol and the last Encoded symbol. Initial Encoded symbol is 1. 4 DSSSDOUBLE DSSS double 19 2 read-write DIS Doubling is disabled. 0 INV Doubling is enabled by using inverted symbols. 1 CONJ Doubling is enabled by using complex conjugated symbols. 2 DSSSLEN DSSS length 11 5 read-write DSSSSHIFTS DSSS shifts 16 3 read-write NOSHIFT No symbols are defined by shifting. 0 SHIFT1 Next symbol generated by 1 cyclic shift. 1 SHIFT2 Next symbol generated by 2 cyclic shifts. 2 SHIFT4 Next symbol generated by 4 cyclic shifts. 3 SHIFT8 Next symbol generated by 8 cyclic shifts. 4 SHIFT16 Next symbol generated by 16 cyclic shifts. 5 DUALCORROPTDIS Dual Correlation Optimization Disable 9 1 read-write FDM0DIFFDIS Frame Detection Mode 0 disable 0 1 read-write FRAMEDETDEL FRAMEDET delay 30 2 read-write DEL0 No delay 0 DEL8 8 baud delay 1 DEL16 16 baud delay 2 DEL32 32 baud delay 3 MAPFSK Mapping of FSK symbols 1 3 read-write MAP0 4FSK: Symbol 11, 10, 00, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 1 is high/positive frequency or high amplitude, symbol 0 is low/negative frequency or low amplitude. 0 MAP1 4FSK: Symbol 01, 00, 10, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Symbol 0 is high/negative frequency or high amplitude, symbol 1 is low/negative frequency or low amplitude. 1 MAP2 4FSK: Symbol 10, 11, 01, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 2 MAP3 4FSK: Symbol 00, 01, 11, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 3 MAP4 4FSK: Symbol 11, 01, 00, 10 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 4 MAP5 4FSK: Symbol 10, 00, 01, 11 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 5 MAP6 4FSK: Symbol 01, 11, 10, 00 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 6 MAP7 4FSK: Symbol 00, 10, 11, 01 for decreasing frequency. 2FSK/MSK/ASK/OOK: Undefined. 7 MODFORMAT Modulation format 6 3 read-write FSK2 Frequency Shift Keying with 2 symbols 0 FSK4 Frequency Shift Keying with 4 symbols 1 BPSK Binary Phase Shift Keying 2 DBPSK Differentially encoded Binary Phase Shift Keying 3 OQPSK Half Sine Shaped Offset Quadrature Phase Shift Keying 4 MSK Minimum Shift Keying 5 OOKASK On Off Keying and Amplitude Shift Keying 6 OOKASYNCPIN OOK asynchronous pin mode 10 1 read-write SHAPING Shaping filter 25 2 read-write DISABLED Filter disabled. 0 ODDLENGTH Filter has odd length. Filter uses coefficients 0,1,2,3,4,5,6,7,8,7,6,5,4,3,2,1,0. 1 EVENLENGTH Filter has even length. Filter uses coefficients 0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0. 2 ASYMMETRIC Filter has asymmetrical coefficients. Filter uses coefficients 0,1,2,3,4,5,6,7. 3 CTRL1 No Description 0x24 read-write n 0x0 0x0 COMPMODE Compensation mode 14 2 read-write DIS Compensation is disabled. 0 PRELOCK Compensation locks when preamble is detected. 1 FRAMELOCK Compensation locks when frame is detected. 2 NOLOCK Compensation is always running 3 DUALSYNC Dual sync words. 9 1 read-write DISABLED Demodulator only searches for SYNC0. 0 ENABLED Demodulator searches for SYNC0 and SYNC1 in parallel. 1 FREQOFFESTLIM Frequency offset limit 25 7 read-write FREQOFFESTPER Frequency offset estimation period 22 3 read-write PHASEDEMOD Phase demodulation 20 2 read-write BDD Bit Differential Detection. 0 MBDD Multibit Differential Detection. 1 COH Coherent Detection. 2 RESYNCPER Resync period 16 4 read-write SYNC1INV SYNC1 invert. 12 1 read-write SYNCBITS Number of sync-word bits 0 5 read-write SYNCDATA Sync data. 11 1 read-write DISABLED SYNC is not part of transmit payload. Modulator adds SYNC in transmit. 0 ENABLED SYNC is part of transmit payload. Modulator does not add SYNC in transmit. 1 SYNCERRORS Maximum number of sync errors 5 4 read-write TXSYNC Transmit sync word. 10 1 read-write SYNC0 Modulator transmits SYNC0. 0 SYNC1 Modulator transmits SYNC1. 1 CTRL2 No Description 0x28 -1 read-write n 0x0 0x0 BRDIVA Baudrate division factor A 15 4 read-write BRDIVB Baudrate division factor B 19 4 read-write DATAFILTER Datafilter 12 3 read-write DISABLED Datafilter disabled 0 SHORT Short datafilter enabled. 2*RXBRFRAC should be more than 3. 1 MEDIUM Medium datafilter enabled. 2*RXBRFRAC should be more than 4. 2 LONG Long datafilter enabled. 2*RXBRFRAC should be more than 5. 3 LEN6 Datafilter with length 6 enabled. 2*RXBRFRAC should be more than 6. 4 LEN7 Datafilter with length 7 enabled. 2*RXBRFRAC should be more than 7. 5 LEN8 Datafilter with length 8 enabled. 2*RXBRFRAC should be more than 8. 6 LEN9 Datafilter with length 9 enabled. 2*RXBRFRAC should be more than 9. 7 DEVMULA Deviation multiplication factor A 23 2 read-write DEVMULB Deviation multiplication factor B 25 2 read-write DEVWEIGHTDIS Deviation weighting disable. 29 1 read-write DMASEL DMA select. 30 2 read-write SOFT SOFTVAL field 0 CORR CORRVAL field 1 FREQOFFEST FREQOFFEST field 2 POE POE field 3 RATESELMODE Rate select mode 27 2 read-write NOCHANGE No rate change. BRDIVA/DEVMULA is used for entire frame. 0 PAYLOAD Change rate for payload. BRDIVA/DEVMULA is used for header and BRDIVB/DEVMULB is used for payload. 1 FRC FRC selects between BRDIVA/DEVMULA and BRDIVB/DEVMULB for each symbol in the payload. Header uses BRDIVA/DEVMULA. 2 SYNC The configured/detected syncword decides the settings used for the payload. SYNC0 uses BRDIVA/DEVMULA and SYNC1 uses BRDIVB/DEVMULB. Header uses BRDIVA/DEVMULA. 3 RXFRCDIS Receive FRC disable 8 1 read-write RXPINMODE Receive pin mode 9 1 read-write SYNCHRONOUS Detected payload bits are clocked out on DOUT. Only setups with 1 bit per symbol are supported. 0 ASYNCHRONOUS DOUT is continuously providing the sign of the detected frequency deviation before offset compensation. Only 2/4-FSK is supported. 1 SQITHRESH Signal Quality Indicator threshold 0 8 read-write TXPINMODE Transmit pin mode 10 2 read-write OFF Pinmode is turned off. Data is gathered from FRC. DOUT/DCLK clocks out transmitted data. 0 UNUSED Unused mode 1 ASYNCHRONOUS DIN/PRS controls transmitted baud directly. DCLK is set to 0. No support for frame handling nor coding. Only 2-FSK and OOK/ASK can be used. 2 SYNCHRONOUS DIN/PRS is sampled on the rising edge of DCLK and used as payload. Frame handling and coding is supported. Only setups with 1 bit per symbol is supported. 3 CTRL3 No Description 0x2C -1 read-write n 0x0 0x0 ANTDIVMODE Antenna Diversity mode 8 3 read-write ANTENNA0 Antenna 0 (ANT0=1, ANT1=0) is used 0 ANTENNA1 Antenna 1 (ANT0=0, ANT1=1) is used 1 ANTSELFIRST Select-First algorithm. 2 ANTSELCORR Select-Best algorithm based on correlation value. 3 ANTSELRSSI Select-Best algorithm based on RSSI value. 4 ANTDIVREPEATDIS Antenna diversity repeat disable 11 1 read-write PRSDINEN DIN PRS enable 0 1 read-write TSAMPDEL Timing Search Amplitude delay 14 2 read-write TSAMPLIM Timing Search Amplitude limit 16 16 read-write TSAMPMODE Timing Search Amplitude Mode 12 2 read-write OFF Amplitude is not used during timing search. 0 ON Timing detection is disabled for windows where at least one sample is below limit set by TSAMPLIM. 1 DIFF Timing detection is disabled for windows where the difference between samples is higher than the limit set by TSAMPLIM. 2 CTRL4 No Description 0x30 -1 read-write n 0x0 0x0 ADCSATDENS ADC Saturation Density setting 26 2 read-write ADCSATLEVEL ADC Saturation Level setting 23 3 read-write CONS1 AGC enters fast loop after first saturation sample. 0 CONS2 2 saturation samples required before AGC enters fast loop. 1 CONS4 4 saturation samples required before AGC enters fast loop. 2 CONS8 8 saturation samples required before AGC enters fast loop. 3 CONS16 16 saturation samples required before AGC enters fast loop. 4 CONS32 32 saturation samples required before AGC enters fast loop. 5 CONS64 64 saturation samples required before AGC enters fast loop. 6 DEVOFFCOMP Deviation offset compensation 4 1 read-write ISICOMP Inter Symbol Interference compensation 0 4 read-write OFFSETPHASEMASKING Offset phase masking 28 1 read-write OFFSETPHASESCALING Offset phase scaling 29 1 read-write PHASECLICKFILT Phase click filter 15 7 read-write PREDISTAVG Predistortion Average 13 1 read-write AVG8 Average over 8 samples. 0 AVG16 Average over 16 samples. 1 PREDISTDEB Predistortion debounce 10 3 read-write PREDISTGAIN Predistortion gain 5 5 read-write PREDISTRST Predistortion Reset 14 1 read-write SOFTDSSSMODE Soft DSSS mode 22 1 read-write CORR0INV Soft value is inverted value of symbol-0 correlation value. 0 CORRDIFF Soft value is difference between correlation values for symbol-0 and symbol-1. 1 CTRL5 No Description 0x34 read-write n 0x0 0x0 BBSS Baseband Signal Selection 12 4 read-write BRCALAVG Baudrate calibration averaging 4 2 read-write BRCALEN Baudrate calibration enable 1 1 read-write BRCALMODE Baudrate calibration mode 2 2 read-write PEAK Measure period between peaks in demodulated signal. This mode can give false peaks for high oversampling ratios without sufficient datafiltering. 0 ZERO Measure period between zero-crossings in demodulated signal. This mode can miss zero-crossings for high frequency offsets. 1 PEAKZERO Combine peak-period and zero-crossing periods. This mode gives best accuracy, but includes weaknesses from both PEAK and ZERO modes. 2 DEMODRAWDATASEL2 Demod raw data select 2 20 3 read-write DIS Disabled. 0 COH Coherent demod 5-bit I and Q input data, 10-bit I and Q data after FOE/POE. 1 CORR 4-bit max_corr_index and 17-bit max_corr . 2 CHPW 8-bit channel power and 4-bit BBSSMUX 3 BBPF 11-bit pre-filter correlation output for BLR and 11-bit pre-filter correlation output for COH demod 4 FSM 5-bit Narrow-band BLE FSM state, 5-bit Long-range BLE FSM state, 3-bit DSA FSM state, 7-bit Detection FSM State. Captured each time state changes 5 DETDEL Detection delay 6 3 read-write DSSSCTD DSSS Correlation Threshold Disable 11 1 read-write FOEPREAVG Frequency Offset Estimate Pre-Averaging 24 3 read-write LINCORR Linear Correlation 27 1 read-write POEPER Phase Offset Estimation Period 16 4 read-write RESYNCBAUDTRANS Resynchronization Baud Transitions 29 1 read-write RESYNCLIMIT Resynchronization Limit 30 1 read-write HALF Adjust timing if accumulated timing is higher/lower than RESYNCPER/2. 0 ALWAYS Adjust timing if accumulated timing is non-zero. 1 TDEDGE Timing detection edge mode 9 1 read-write TREDGE Timing resynchronization edge mode 10 1 read-write CTRL6 No Description 0x38 read-write n 0x0 0x0 ARW Allow Received Window 15 2 read-write SMALLWND Allow received windows when window size is less than half the RAM size. 0 ALWAYS Always allow received windows. 1 NEVER Never allow received windows. 2 PSABORT Allow received windows right after PSTIMABORTn tests have aborted timing and coherent detection is enabled, or when window size is less than half the RAM size. 3 CODINGB Coding format 25 2 read-write NRZ Non Return to Zero 0 MANCHESTER Manchester Coding 1 DSSS Direct Sequence Spread Spectrum 2 LINECODE Line code. Maps 0 to 0011 symbol and 1 to 1100 symbols 3 CPLXCORREN Enable Complex Correlation 20 1 read-write DSSS3SYMBOLSYNCEN Enable three symbol sync detection 21 1 read-write PREBASES Preamble Bases 7 4 read-write PSTIMABORT0 Preamble Search Timing Abort Criteria 0 11 1 read-write PSTIMABORT1 Preamble Search Timing Abort Criteria 1 12 1 read-write PSTIMABORT2 Preamble Search Timing Abort Criteria 2 13 1 read-write PSTIMABORT3 Preamble Search Timing Abort Criteria 3 14 1 read-write RXBRCALCDIS RX Baudrate Calculation Disable 30 1 read-write TDREW Timing Detection Rewind 0 7 read-write TIMTHRESHGAIN Timing Threshold Gain 17 3 read-write DCCOMP No Description 0xE0 -1 read-write n 0x0 0x0 DCCOMPEN DC Offset Compensation Enable 1 1 read-write DCCOMPFREEZE DC Offset Compensation Filter Freeze 3 1 read-write DCCOMPGEAR DC Offset Compensation Filter Gear 4 3 read-write DCESTIEN DC Offset Estimation Enable 0 1 read-write DCLIMIT DC offset limit 7 2 read-write FULLSCALE 1000 mV 0 FULLSCALEBY4 250 mV 1 FULLSCALEBY8 125 mV 2 FULLSCALEBY16 62 mV 3 DCRSTEN DC Compensation Filter Reset Enable 2 1 read-write DCCOMPFILTINIT No Description 0xE4 read-write n 0x0 0x0 DCCOMPINIT Initialize filter state 30 1 read-write DCCOMPINITVALI I-channel initialization value 0 15 read-write DCCOMPINITVALQ Q-channel initialization value 15 15 read-write DCESTI No Description 0xE8 read-only n 0x0 0x0 DCCOMPESTIVALI I-channel DC-Offset Estimated value 0 15 read-only DCCOMPESTIVALQ Q-channel DC-Offset Estimated value 15 15 read-only DIGIGAINCTRL No Description 0x23C read-write n 0x0 0x0 DEC0GAIN DEC0 Gain Select 8 1 read-write DIGIGAINDOUBLE Digital Gain Doubled 6 1 read-write DIGIGAINEN Digital Gain Enable 0 1 read-write DIGIGAINHALF Digital Gain Halved 7 1 read-write DIGIGAINSEL Digital Gain Select 1 5 read-write GAINM3 GAINM3 0 GAINM2P75 GAINM2P75 1 GAINM0P5 GAINM0P5 10 GAINM0P25 GAINM0P25 11 GAINM0 GAINM0 12 GAINP0P25 GAINP0P25 13 GAINP0P5 GAINP0P5 14 GAINP0P75 GAINP0P75 15 GAINP1 GAINP1 16 GAINP1P25 GAINP1P25 17 GAINP1P5 GAINP1P5 18 GAINP1P75 GAINP1P75 19 GAINM2P5 GAINM2P5 2 GAINP2 GAINP2 20 GAINP2P25 GAINP2P25 21 GAINP2P5 GAINP2P5 22 GAINP2P75 GAINP2P75 23 GAINP3 GAINP3 24 GAINM2P25 GAINM2P25 3 GAINM2 GAINM2 4 GAINM1P75 GAINM1P75 5 GAINM1P5 GAINM1P5 6 GAINM1P25 GAINM1P25 7 GAINM1 GAINM1 8 GAINM0P75 GAINM0P75 9 DIGMIXCTRL No Description 0x10C read-write n 0x0 0x0 DIGMIXFREQ Digital mixer frequency control word 0 20 read-write DIGMIXMODE Digital mixer frequency control 20 1 read-write CFOSR Mixer frequency specified by CFOSR. 0 DIGMIXFREQ Mixer frequency specified by DIGMIXFREQ. 1 MIXERCONJ Digital mixer input conjugate 21 1 read-write DIRECTMODE No Description 0x134 -1 read-write n 0x0 0x0 CLKWIDTH Synchronous mode clock pulse width 8 5 read-write DMENABLE Enable Direct Mode 0 1 read-write SYNCASYNC Choose Synchronous or Asynchronous mode 1 1 read-write SYNCPREAM Synchronous mode preamble 2 2 read-write ADD0 No preamble bits appended 0 ADD8 8 preamble bits appended 1 ADD16 16 preamble bits appended 2 ADD32 32 preamble bits appended 3 DSACTRL No Description 0xFC -1 read-write n 0x0 0x0 AGCBAUDEN Consider Baud_en from AGC 27 1 read-write AMPJUPTHD Amplitude jump detection thrshold 28 4 read-write ARRTHD Signal arrival valid counter threshold 2 4 read-write ARRTOLERTHD0 Arrival tolerance threshold 0 6 5 read-write ARRTOLERTHD1 Arrival tolerance threshold 1 11 5 read-write DSAMODE Mode of Digital Signal Arrival detector 0 2 read-write DISABLED DSA is disabled 0 ENABLED DSA is enabled by the relative/absolute RSSI detector and is reset by using detectors for spike content and frequency deviation. The RSSI jump detector is used to recover from false detects. 1 DSARSTON DSA detection reset 19 1 read-write FREQAVGSYM DSA frequency estimation averaging 17 1 read-write AVG2TS Frequency estimation over 2 symbol periods. 0 AVG4TS Frequency estimation over 4 symbol periods. 1 GAINREDUCDLY Detection Delay of AGC gain reduction 21 2 read-write LOWDUTY Low duty cycle delay 23 3 read-write RESTORE Power detector reset of DSA 26 1 read-write SCHPRD Search period window length 16 1 read-write TS2 The search period is 2 symbol periods. 0 TS4 The search period is 4 symbol periods. 1 TRANRSTDSA power transient detector Reset DSA 18 1 read-write DSATHD0 No Description 0xF4 -1 read-write n 0x0 0x0 FDEVMAXTHD Frequency deviation maximum threshold 20 12 read-write FDEVMINTHD Frequency deviation minimum threshold 14 6 read-write SPIKETHD Spike threshold 0 8 read-write UNMODTHD Unmodulated carrier detector threshold 8 6 read-write DSATHD1 No Description 0xF8 -1 read-write n 0x0 0x0 AMPFLTBYP Amplitude filter bypass 28 1 read-write DSARSTCNT DSA reset counter 18 3 read-write FREQLATDLY Frequency late delay 25 2 read-write FREQSCALE Frequency scale factor 30 1 read-write POWABSTHD Power absolute threshold 0 16 read-write POWRELTHD Relative power detector threshold 16 2 read-write DISABLED Threshold is 6dB. The relative power detector will trigger when the current RSSI is 6dB stronger than the previously detected RSSI. 0 MODE1 Threshold is 9dB. The relative power detector will trigger when the current RSSI is 9dB stronger than the previously detected RSSI. 1 MODE2 Threshold is 12dB. The relative power detector will trigger when the current RSSI is 12dB stronger than the previously detected RSSI. 2 MODE3 Threshold is 15dB. The relative power detector will trigger when the current RSSI is 15dB stronger than the previously detected RSSI. 3 PWRDETDIS Power detection disabled 29 1 read-write PWRFLTBYP Power filter bypass 27 1 read-write RSSIJMPTHD RSSI jump detector threshold 21 4 read-write DSATHD2 No Description 0x130 -1 read-write n 0x0 0x0 FDADJTHD Frequency deviation ripple threshold 10 6 read-write FREQESTTHD Frequency Estimation Timeout Threshold 20 5 read-write INTERFERDET Interference detection threshold 25 5 read-write JUMPDETEN Power jump detection enable 9 1 read-write PMDETFORCE Force DSA preamble detector 30 1 read-write PMDETPASSTHD DSA Preamble detection counter threshold 16 4 read-write POWABSTHDLOG Power threshold in logarithm-scale 0 8 read-write DSATHD3 No Description 0x168 -1 read-write n 0x0 0x0 FDEVMAXTHDLO Frequency deviation maximum threshold 20 12 read-write FDEVMINTHDLO Frequency deviation minimum threshold 14 6 read-write SPIKETHDLO Spike threshold 0 8 read-write UNMODTHDLO Unmodulated carrier detector threshold 8 6 read-write DSATHD4 No Description 0x16C -1 read-write n 0x0 0x0 ARRTOLERTHD0LO Arrival tolerance threshold 0 16 5 read-write ARRTOLERTHD1LO Arrival tolerance threshold 1 21 5 read-write POWABSTHDLO Power absolute threshold for low power 0 16 read-write SWTHD Enable switch threshold for low power 26 1 read-write DSSS0 No Description 0x84 read-write n 0x0 0x0 DSSS0 DSSS symbol 0 0 32 read-write EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FREQOFFEST No Description 0x10 read-only n 0x0 0x0 CORRVAL Correlation value 16 8 read-only FREQOFFEST Frequency offset estimate 0 13 read-only SOFTVAL Soft detection value 24 8 read-only FSMSTATUS No Description 0x21C read-only n 0x0 0x0 DETSTATE Detection FSM state 0 7 read-only OFF Off state 0 TIMINGSEARCH Timing search 10 PRESEARCH Preamble search 20 FRAMESEARCH Frame search 30 RXFRAME Payload Detection 40 FRAMEDETMODE0 Timing search with sliding window (FDM0) 50 DSASTATE Demodulator DSA FSM state 7 3 read-only IDLE IDLE state 0 ARRIVALCHK Arrival Check 1 STATUSCHK Status Check 2 SAMPPW SAMP_PW 3 WAITPWRUP WAIT_PWRUP 4 WAITDSALO WAIT_DSALO 5 WAITABORT WAIT_ABORT 6 STOP STOP 7 LRBLESTATE Demodulator long-range BLE FSM state 10 5 read-only IDLE IDLE state 0 CLEANUP CLEANUP 1 FEC2ACK FEC2_ACK 10 TRACKCUR TRACK_CUR 11 TRACKEAR TRACK_EAR 12 TRACKLAT TRACK_LAT 13 TRACKDONE TRACK_DONE 14 TDECISION T_DECISION 15 STOP STOP 16 CORRCOE CORRCOE 2 WAITLRDSA WAIT_LR_DSA 3 MAXCORR MAXCORR 4 WAITRDY WAIT_RDY 5 FEC1DATA FEC1_DATA 6 FEC1ACK FEC1_ACK 7 PAUSE PAUSE 8 FEC2DATA FEC2_DATA 9 NBBLESTATE Demodulator Narrow-band BLE FSM state 15 5 read-only IDLE IDLE state 0 VTINITI VTINITI 1 TIMINGACQUEARLY TIMING_ACQU_EARLY 10 TIMINGACQUCURR TIMING_ACQU_CURR 11 TIMINGACQULATE TIMING_ACQU_LATE 12 TIMINGACQUDONE TIMING_ACQU_DONE 13 VIRTBIINIT0 VIRTBI_INIT0 14 VIRTBIINIT1 VIRTBI_INIT1 15 VIRTBIRXSYNC VIRTBI_RXSYNC 16 VIRTBIRXPAYLOAD VIRTBI_RXPAYLOAD 17 HARDRXSYNC HARD_RXSYNC 18 HARDXPAYLOAD HARD_RXPAYLOAD 19 ADDRNXT ADDR_NXT 2 TRACKFREQ TRACK_FREQ 20 TRACKTIMEARLY TRACK_TIM_EARLY 21 TRACKTIMCURR TRACK_TIM_CURR 22 TRACKTIMLATE TRACK_TIM_LATE 23 TRACKDONE TRACK_DONE 24 TRACKDECISION TRACK_DECISION 25 STOP STOP 26 WAITACK WAIT_ACK 27 DEBUG DEBUG 28 INICOST INI_COST 3 CALCCOST CALC_COST 4 INITALACQU INITAL_ACQU 5 INITALCOSTCALC INITAL_COST_CALC 6 MINCOSTCALC MIN_COST_CALC 7 FREQACQU FREQ_ACQU 8 FREQACQUDONE FREQ_ACQU_DONE 9 IEN No Description 0x20C read-write n 0x0 0x0 FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXPREDET Preamble detected 9 1 read-write RXPRELOST Preamble lost 13 1 read-write RXTIMDET Timing detected 8 1 read-write RXTIMLOST Timing lost 12 1 read-write RXTIMNF Timing not found 15 1 read-write TXFRAMESENT Frame sent 0 1 read-write TXPRESENT Preamble sent 2 1 read-write TXSYNCSENT Sync word sent 1 1 read-write IF No Description 0x208 read-write n 0x0 0x0 FRCTIMOUT DEMOD-FRC req/ack timeout 16 1 read-write RXFRAMEDET0 Frame with sync-word 0 detected 10 1 read-write RXFRAMEDET1 Frame with sync-word 1 detected 11 1 read-write RXFRAMEDETOF Frame detection overflow 14 1 read-write RXPREDET Preamble detected 9 1 read-write RXPRELOST Preamble lost 13 1 read-write RXTIMDET Timing detected 8 1 read-write RXTIMLOST Timing lost 12 1 read-write RXTIMNF Timing not found 15 1 read-write TXFRAMESENT Frame sent 0 1 read-write TXPRESENT Preamble sent 2 1 read-write TXSYNCSENT Sync word sent 1 1 read-write INTAFC No Description 0xF0 read-write n 0x0 0x0 FOEPREAVG0 First estimate 0 3 read-write FOEPREAVG1 Second estimate 3 3 read-write FOEPREAVG2 Third estimate 6 3 read-write FOEPREAVG3 Fourth estimate 9 3 read-write FOEPREAVG4 Fifth estimate 12 3 read-write FOEPREAVG5 Sixth estimate 15 3 read-write FOEPREAVG6 Seventh estimate 18 3 read-write FOEPREAVG7 Eighth estimate 21 3 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only IRCAL No Description 0x228 read-write n 0x0 0x0 IRCALEN IRCAL enable bit 0 1 read-write IRCORREN IR Correction enable bit 13 1 read-write MUISHF MUI shift value 7 6 read-write MURSHF MUR shift value 1 5 read-write IRCALCOEF No Description 0x22C read-only n 0x0 0x0 CIV CIV coefficient 16 15 read-only CRV CRV coefficient 0 15 read-only IRCALCOEFWR0 No Description 0x250 read-write n 0x0 0x0 CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write IRCALCOEFWR1 No Description 0x254 read-write n 0x0 0x0 CIVWD CIV coefficient 16 15 read-write CIVWEN CIV Coefficient Write Enable 31 1 read-write CRVWD CRV coefficient 0 15 read-write CRVWEN CIV Coefficient Write Enable 15 1 read-write LONGRANGE No Description 0x138 -1 read-write n 0x0 0x0 LRBLE Enable 15 1 read-write LRBLEDSA DSA enable 27 1 read-write LRCORRSCHWIN Window size 11 4 read-write LRCORRTHD Correlator threshold 0 11 read-write LRCORRTHDDYNEN Correlator THD dynamic enable 31 1 read-write LRDEC DEC value 28 3 read-write LRTIMCORRTHD Correlator threshold 16 11 read-write LONGRANGE1 No Description 0x13C read-write n 0x0 0x0 AVGWIN Average window 21 3 read-write CHPWRACCUDEL Channel Power Accumulated Delay 16 2 read-write DEL0 Use accumulated channel power value 0 DEL32 Delayed by 32 chips 1 DEL64 Delayed by 64 chips 2 HYSVAL Hysteresis Value for BBSS 18 3 read-write LOGICBASEDLRDEMODGATE Logic Based Long Range Demod Gating 29 1 read-write LOGICBASEDPUGATE Logic Based Phase Unwrap Gating 28 1 read-write LRSPIKETHADD Long Range DSA spike threshold addition 24 4 read-write LRSS Long Range Signal Selection 0 4 read-write LRTIMEOUTTHD Long Range Time Out Threshold 4 11 read-write LONGRANGE2 No Description 0x140 read-write n 0x0 0x0 LRCHPWRTH1 Long Range channel power threshold 0 8 read-write LRCHPWRTH2 Long Range channel power threshold 8 8 read-write LRCHPWRTH3 Long Range channel power threshold 16 8 read-write LRCHPWRTH4 Long Range channel power threshold 24 8 read-write LONGRANGE3 No Description 0x144 read-write n 0x0 0x0 LRCHPWRTH5 Long Range channel power threshold 0 8 read-write LRCHPWRTH6 Long Range channel power threshold 8 8 read-write LRCHPWRTH7 Long Range channel power threshold 16 8 read-write LRCHPWRTH8 Long Range channel power threshold 24 8 read-write LONGRANGE4 No Description 0x148 read-write n 0x0 0x0 LRCHPWRSH1 Long Range channel power shift 16 4 read-write LRCHPWRSH2 Long Range channel power shift 20 4 read-write LRCHPWRSH3 Long Range channel power shift 24 4 read-write LRCHPWRSH4 Long Range channel power shift 28 4 read-write LRCHPWRTH10 Long Range channel power threshold 8 8 read-write LRCHPWRTH9 Long Range channel power threshold 0 8 read-write LONGRANGE5 No Description 0x14C read-write n 0x0 0x0 LRCHPWRSH10 Long Range channel power shift 20 4 read-write LRCHPWRSH11 Long Range channel power shift 24 4 read-write LRCHPWRSH5 Long Range channel power shift 0 4 read-write LRCHPWRSH6 Long Range channel power shift 4 4 read-write LRCHPWRSH7 Long Range channel power shift 8 4 read-write LRCHPWRSH8 Long Range channel power shift 12 4 read-write LRCHPWRSH9 Long Range channel power shift 16 4 read-write LONGRANGE6 No Description 0x150 read-write n 0x0 0x0 LRCHPWRSH12 Long Range channel power shift 28 4 read-write LRCHPWRSPIKETH Long Range channel power spike threshold 0 8 read-write LRCHPWRTH11 Long Range channel power threshold 20 8 read-write LRSPIKETHD Long Range spike threshold 8 11 read-write LRFRC No Description 0x154 -1 read-write n 0x0 0x0 CI500 Long Range CI mapping for 500kbps 0 2 read-write FRCACKTIMETHD FRC acknowledge timeout threshold 2 6 read-write MIXCTRL No Description 0x1C read-write n 0x0 0x0 ANAMIXMODE Analog receiver mixer mode of operation 0 4 read-write NORMAL The analog mixer operates in its normal mode 0 IPQPIQSWAP I path is positive, Q path is positive, I and Q are swapped 1 IPQN I path is positive, Q path is negative 2 IPQNIQSWAP I path is positive, Q path is negative, I and Q are swapped 3 INQP I path is negative, Q path is positive 4 INQPIQSWAP I path is negative, Q path is positive, I and Q are swapped 5 INQN I path is negative, Q path is negative 6 INQNIQSWAP I path is negative, Q path is negative, I and Q are swapped 7 UPCONVERT Control the analog receiver mixer such that the analog mixer performs a digital up-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. This mode may be used to perform RF loopback using the normal synthesizer both for transmit and receive, and still get a positive IF frequency on the IF receive signal. 8 DOWNCONVERT Control the analog receiver mixer such that the analog mixer performs a digital down-conversion on the mixer output, with the frequency set by the DEC0 and CFOSR settings. 9 DIGIQSWAPEN Digital I/Q swap enable 4 1 read-write MODINDEX No Description 0x88 read-write n 0x0 0x0 FREQGAINE Frequency demodulation gain - exponent 16 3 read-write FREQGAINM Frequency demodulation gain - mantissa 19 3 read-write MODINDEXE Modulation index exponent. 5 5 read-write MODINDEXM Modulation index mantissa. 0 5 read-write POE No Description 0x12C read-only n 0x0 0x0 POEI In-phase component of POE. 0 10 read-only POEQ Quadrature component of POE. 16 10 read-only PRE No Description 0x64 read-write n 0x0 0x0 BASE Preamble base 0 4 read-write BASEBITS BASE bits 4 2 read-write DSSSPRE DSSS preamble 11 1 read-write PREERRORS Preamble errors 7 4 read-write PRESYMB4FSK Preamble symbols 4-FSK 6 1 read-write OUTER Symbols corresponding to +/- 3dev. 0 INNER Symbols corresponding to +/- dev. 1 SYNCSYMB4FSK Sync symbols 4FSK 12 1 read-write FSK2 The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK. 0 FSK4 The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol. 1 TXBASES TX bases 16 16 read-write PRSCTRL No Description 0x240 read-write n 0x0 0x0 ADVANCESEL None 2 2 read-write ANT0SEL None 14 2 read-write ANT1SEL None 16 2 read-write LOWCORRSEL None 12 2 read-write NEWWNDSEL None 4 2 read-write POSTPONESEL None 0 2 read-write PRESENTSEL None 10 2 read-write SYNCSENTSEL None 8 2 read-write WEAKSEL None 6 2 read-write RAMPCTRL No Description 0xC0 -1 read-write n 0x0 0x0 RAMPRATE0 Ramp rate 0 0 4 read-write RAMPRATE1 Ramp rate 1 4 4 read-write RAMPRATE2 Ramp rate 2 8 4 read-write RAMPLEV No Description 0xC4 -1 read-write n 0x0 0x0 RAMPLEV0 Ramp level 0 0 8 read-write RAMPLEV1 Ramp level 1 8 8 read-write RAMPLEV2 Ramp level 2 16 8 read-write RXBR No Description 0x5C read-write n 0x0 0x0 RXBRDEN Receive baudrate denominator 5 5 read-write RXBRINT Receive baudrate integer 10 3 read-write RXBRNUM Receive baudrate numerator 0 5 read-write SHAPING0 No Description 0x94 -1 read-write n 0x0 0x0 COEFF0 Shaping Coefficient 0 0 8 read-write COEFF1 Shaping Coefficient 1 8 8 read-write COEFF2 Shaping Coefficient 2 16 8 read-write COEFF3 Shaping Coefficient 3 24 8 read-write SHAPING1 No Description 0x98 -1 read-write n 0x0 0x0 COEFF4 Shaping Coefficient 4 0 8 read-write COEFF5 Shaping Coefficient 5 8 8 read-write COEFF6 Shaping Coefficient 6 16 8 read-write COEFF7 Shaping Coefficient 7 24 8 read-write SHAPING2 No Description 0x9C read-write n 0x0 0x0 COEFF10 Shaping Coefficient 10 16 8 read-write COEFF11 Shaping Coefficient 11 24 8 read-write COEFF8 Shaping Coefficient 8 0 8 read-write COEFF9 Shaping Coefficient 9 8 8 read-write SHAPING3 No Description 0xA0 read-write n 0x0 0x0 COEFF12 Shaping Coefficient 12 0 8 read-write COEFF13 Shaping Coefficient 13 8 8 read-write COEFF14 Shaping Coefficient 14 16 8 read-write COEFF15 Shaping Coefficient 15 24 8 read-write SHAPING4 No Description 0xA4 read-write n 0x0 0x0 COEFF16 Shaping Coefficient 16 0 6 read-write COEFF17 Shaping Coefficient 17 6 6 read-write COEFF18 Shaping Coefficient 18 12 6 read-write COEFF19 Shaping Coefficient 19 18 5 read-write COEFF20 Shaping Coefficient 20 23 5 read-write COEFF21 Shaping Coefficient 21 28 4 read-write SHAPING5 No Description 0xA8 read-write n 0x0 0x0 COEFF22 Shaping Coefficient 22 0 4 read-write COEFF23 Shaping Coefficient 23 4 4 read-write COEFF24 Shaping Coefficient 24 8 4 read-write COEFF25 Shaping Coefficient 25 12 4 read-write COEFF26 Shaping Coefficient 26 16 4 read-write COEFF27 Shaping Coefficient 27 20 4 read-write COEFF28 Shaping Coefficient 28 24 4 read-write COEFF29 Shaping Coefficient 29 28 4 read-write SHAPING6 No Description 0xAC read-write n 0x0 0x0 COEFF30 Shaping Coefficient 30 0 4 read-write COEFF31 Shaping Coefficient 31 4 4 read-write COEFF32 Shaping Coefficient 32 8 3 read-write COEFF33 Shaping Coefficient 33 11 3 read-write COEFF34 Shaping Coefficient 34 14 3 read-write COEFF35 Shaping Coefficient 35 17 3 read-write COEFF36 Shaping Coefficient 36 20 3 read-write COEFF37 Shaping Coefficient 37 23 3 read-write COEFF38 Shaping Coefficient 38 26 3 read-write COEFF39 Shaping Coefficient 39 29 3 read-write SRCCHF No Description 0xEC read-write n 0x0 0x0 BWSEL Channel filter bandwidth 29 2 read-write X0 wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor 0 X1 wide bandwidth selected BW = 0.263*Fxtal/dec0-factor/dec1-factor 1 X2 narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor 2 X3 narrow bandwidth selected BW = 0.196*Fxtal/dec0-factor/dec1-factor 3 INTOSR Forcing Integer OSR 31 1 read-write SRCENABLE1 SRC1 enable 11 1 read-write SRCENABLE2 SRC2 enable 27 1 read-write SRCRATIO1 I-channel SRC ratio 0 8 read-write SRCRATIO2 Q-channel SRC ratio 12 15 read-write STATUS No Description 0x8 read-only n 0x0 0x0 ANTSEL Selected Antenna 5 1 read-only ANTENNA0 Antenna 0 is selected (ANT0 = 1 and ANT1 = 0). 0 ANTENNA1 Antenna 1 is selected (ANT0 = 0 and ANT1 = 1). 1 CORR Correlation 16 8 read-only DEMODSTATE DEMOD state 0 3 read-only OFF Off state 0 TIMINGSEARCH Timing search 1 PRESEARCH Preamble search 2 FRAMESEARCH Frame search 3 RXFRAME Payload Detection 4 FRAMEDETMODE0 Timing search with sliding window (FDM0) 5 DSADETECTED DSA detected 8 1 read-only DSAFREQESTDONE DSA frequency estimation complete 9 1 read-only FRAMEDETID Frame Detected ID 4 1 read-only FRAMEDET0 Last frame was detected with sync word defined in SYNC0. 0 FRAMEDET1 Last frame was detected with sync word defined in SYNC1. 1 STAMPSTATE BLE Viterbi Demod Timing Stamp 12 3 read-only TIMLOSTCAUSE Timing Lost Cause 7 1 read-only LOWCORR Timing lost during Preamble Search or due to low correlation value during Frame Search. 0 TIMEOUT Timing lost due to incorrect symbols detected during Frame Search. 1 TIMSEQINV Timing Sequence Inverted 6 1 read-only VITERBIDEMODFRAMEDET Viterbi Demod frame detected 11 1 read-only VITERBIDEMODTIMDET Viterbi Demod timing detected 10 1 read-only WEAKSYMBOLS Weak symbols 24 8 read-only STATUS2 No Description 0x220 read-only n 0x0 0x0 BBSSMUX Actual Baseband Signal Selection 8 4 read-only CHPWRACCUMUX Channel power 0 8 read-only LRBLECI RXed packet's LR BLE coding indicator 12 2 read-only LR125k FEC block 2 coded using C=8, 125kbps 0 LR500k FEC block 2 coded using C=2, 500kbps 1 STATUS3 No Description 0x224 read-only n 0x0 0x0 BBPFOUTABS Pre-filter Correlation Output for BLR 11 11 read-only BBPFOUTABS1 Pre-filter Correlation Output 0 11 read-only COHDSADET DSA prefilter above CDTH 25 1 read-only COHDSALIVE COHDSA Prefilter above CDTH 23 1 read-only LRDSADET DSA prefilter above LRSPIKETHD 24 1 read-only LRDSALIVE BLRDSA Prefilter above LRSPIKETHD 22 1 read-only SYNCSECPEAKABTH SYNC second peak above threshold 26 1 read-only SYNC0 No Description 0x68 read-write n 0x0 0x0 SYNC0 Sync-word 0 0 32 read-write SYNC1 No Description 0x6C read-write n 0x0 0x0 SYNC1 Sync word 1 0 32 read-write SYNCPROPERTIES No Description 0x238 read-write n 0x0 0x0 SYNCCORRCLR Sync auto corr clear bit 0 1 read-write SYNCSECPEAKTH SYNC auto corr second peak threshold 1 7 read-write TIMDETSTATUS No Description 0xC read-only n 0x0 0x0 TIMDETCORR Correlation value 0 8 read-only TIMDETFREQOFFEST Frequency offset estimate 8 8 read-only TIMDETINDEX Timing detection index 25 4 read-only TIMDETPASS Timing detection pass 24 1 read-only TIMDETPREERRORS Preamble errors 16 4 read-only TIMING No Description 0x80 read-write n 0x0 0x0 ADDTIMSEQ Additional timing sequences 12 4 read-write FASTRESYNC Fast timing resynchronization 30 2 read-write DIS Disabled. 0 PREDET Allow fast resynchronization until preamble is detected. 1 FRAMEDET Allow fast resynchronization until frame is detected. 2 FDM0THRESH Frame Detection Mode 0 threshold 18 3 read-write OFFSUBDEN Offset subperiod denominator 25 4 read-write OFFSUBNUM Offset subperiod numerator 21 4 read-write TIMINGBASES Timing bases 8 4 read-write TIMSEQINVEN Timing sequence inversion enable 16 1 read-write TIMSEQSYNC Timing sequence part of sync-word 17 1 read-write TIMTHRESH Timing threshold 0 8 read-write TSAGCDEL Timing Search AGC delay 29 1 read-write TXBR No Description 0x58 read-write n 0x0 0x0 TXBRDEN Transmit baudrate denominator 16 8 read-write TXBRNUM Transmit baudrate numerator 0 16 read-write VITERBIDEMOD No Description 0x100 -1 read-write n 0x0 0x0 CORRCYCLE Correction cycles 23 4 read-write CORRSTPSIZE Correction step size 27 4 read-write DISDEMODOF Disable Demod Over Flow Detection 31 1 read-write HARDDECISION Hard decision 1 1 read-write SYNTHAFC Synthesizer AFC in Viterbi demod 22 1 read-write VITERBIKSI1 VITERBI KSI1 2 7 read-write VITERBIKSI2 VITERBI KSI2 9 7 read-write VITERBIKSI3 VITERBI KSI3 16 6 read-write VTDEMODEN Viterbi demodulator enable 0 1 read-write VTBLETIMING No Description 0x170 read-write n 0x0 0x0 FLENOFF Timing Stamp Frame Length Offset 12 4 read-write TIMINGDELAY Viterbi BLE Delay timer 4 8 read-write VTBLETIMINGSEL Viterbi BLE timing stamp selection 0 2 read-write FRAMEDET_DELAY Delayed frame detection will be used as Timing stamp. This mode should be selected for legacy demod and Long Range BLE demod. 0 END_FRAME_PULSE The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a narrow pulse signal and pulse width is one xo clock cycle. 1 END_FRAME The end of frame detection from Narrow Viterbi demod will be used as Timing stamp. This signal is a wdie pulse signal 2 INV_END_FRAME For testing only. 3 VTCORRCFG0 No Description 0x104 -1 read-write n 0x0 0x0 EXPECTPATT Expected pattern 0 32 read-write VTCORRCFG1 No Description 0x110 -1 read-write n 0x0 0x0 BUFFHEAD Buffer header 23 4 read-write CORRSHFTLEN Correlator shift length 0 6 read-write EXPECTHT Expected patterns head and tail 27 4 read-write EXPSYNCLEN Expected sync length 15 8 read-write VTFRQLIM Viterbi frequency limiter 6 9 read-write VTTRACK No Description 0x114 -1 read-write n 0x0 0x0 FREQBIAS Frequency estimation bias 18 4 read-write FREQTRACKMODE Frequency tracking mode 0 2 read-write DISABLED Frequency tracking disabled. Only a one-time frequency offset compensation applied through DSA. 0 MODE1 Frequency tracking enabled with one correction, when needed, every 16 symbol periods. 1 MODE2 Frequency tracking enabled with one correction, when needed, every 32 symbol periods. 2 MODE3 Frequency tracking enabled with one correction, when needed, every 48 symbol periods. 3 HIPWRTHD High Power detection threshold 22 8 read-write TIMCHK Time check 14 1 read-write TIMEACQUTHD Time acquisition threshold 6 8 read-write TIMEOUTMODE Timeout mode 15 1 read-write TIMGEAR Timing Gear 16 2 read-write GEAR0 Execute timing tracking regardless of difference between Early/Late and Current correlation values. Referred to as fast gear. Same as GEAR3 0 GEAR1 Execute timing tracking only when correlation value of Early/Late is 75% or less of the Current correlation value. Referred to as medium gear. 1 GEAR2 Execute timing tracking only when correlation value of Early/Late is 50% or less of the Current correlation value. Referred to as slow gear. 2 TIMTRACKTHD Timing tracking threshold 2 4 read-write MSC_NS MSC_NS Registers MSC_NS 0x0 0x0 0x1000 registers n MSC 51 ADDRB No Description 0x14 read-write n 0x0 0x0 ADDRB Page Erase or Write Address Buffer 0 32 read-write CMD No Description 0x38 write-only n 0x0 0x0 PWRUP Flash Power Up Command 0 1 write-only IEN No Description 0x24 read-write n 0x0 0x0 ERASE Erase Done Interrupt enable 0 1 read-write PWRUPF Flash Power Up Sequence Complete 8 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write WRITE Write Done Interrupt enable 1 1 read-write IF No Description 0x20 read-write n 0x0 0x0 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write WDATAOV Host write buffer overflow 2 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x3C write-only n 0x0 0x0 LOCKKEY Configuration Lock 0 16 write-only LOCK 0 UNLOCK 7025 MISCLOCKWORD No Description 0x40 -1 read-write n 0x0 0x0 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PAGELOCK0 No Description 0x120 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK2 No Description 0x128 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK3 No Description 0x12C read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write READCTRL No Description 0x8 -1 read-write n 0x0 0x0 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer. 1 WS2 Two wait-states inserted for eatch fetch or read transfer. 2 WS3 Three wait-states inserted for eatch fetch or read transfer. 3 STATUS No Description 0x1C -1 read-only n 0x0 0x0 BUSY Erase/Write Busy 0 1 read-only ERASEABORTED The Current Flash Erase Operation Aborted 4 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only LOCKED Access Locked 1 1 read-only PENDING Write command is in queue 5 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED 0 LOCKED 1 TIMEOUT Write command timeout flag 6 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only WREADY Flash Write Ready 27 1 read-only TESTCTRL register locked by TESTLOCK 0x1A0 -1 read-write n 0x0 0x0 XADRINC Pattern check XADR Inc Mode 23 1 read-write ONE 0 TWO 1 USERDATASIZE No Description 0x34 -1 read-only n 0x0 0x0 USERDATASIZE User Data Size 0 6 read-only WDATA No Description 0x18 read-write n 0x0 0x0 DATAW Write Data 0 32 read-write WRITECMD No Description 0x10 write-only n 0x0 0x0 CLEARWDATA Clear WDATA state 12 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only WRITECTRL No Description 0xC read-write n 0x0 0x0 IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WREN Enable Write/Erase Controller 0 1 read-write MSC_S MSC_S Registers MSC_S 0x0 0x0 0x1000 registers n MSC 51 ADDRB No Description 0x14 read-write n 0x0 0x0 ADDRB Page Erase or Write Address Buffer 0 32 read-write CMD No Description 0x38 write-only n 0x0 0x0 PWRUP Flash Power Up Command 0 1 write-only IEN No Description 0x24 read-write n 0x0 0x0 ERASE Erase Done Interrupt enable 0 1 read-write PWRUPF Flash Power Up Sequence Complete 8 1 read-write WDATAOV write data buffer overflow irq enable 2 1 read-write WRITE Write Done Interrupt enable 1 1 read-write IF No Description 0x20 read-write n 0x0 0x0 ERASE Host Erase Done Interrupt Read Flag 0 1 read-write PWRUPF Flash Power Up Sequence Complete Flag 8 1 read-write WDATAOV Host write buffer overflow 2 1 read-write WRITE Host Write Done Interrupt Read Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x3C write-only n 0x0 0x0 LOCKKEY Configuration Lock 0 16 write-only LOCK 0 UNLOCK 7025 MISCLOCKWORD No Description 0x40 -1 read-write n 0x0 0x0 MELOCKBIT Mass Erase Lock 0 1 read-write UDLOCKBIT User Data Lock 4 1 read-write PAGELOCK0 No Description 0x120 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK1 No Description 0x124 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK2 No Description 0x128 read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write PAGELOCK3 No Description 0x12C read-write n 0x0 0x0 LOCKBIT page lock bit 0 32 read-write READCTRL No Description 0x8 -1 read-write n 0x0 0x0 DOUTBUFEN Flash dout pipeline buffer enable 12 1 read-write MODE Read Mode 20 2 read-write WS0 Zero wait-states inserted in fetch or read transfers 0 WS1 One wait-state inserted for each fetch or read transfer. 1 WS2 Two wait-states inserted for eatch fetch or read transfer. 2 WS3 Three wait-states inserted for eatch fetch or read transfer. 3 STATUS No Description 0x1C -1 read-only n 0x0 0x0 BUSY Erase/Write Busy 0 1 read-only ERASEABORTED The Current Flash Erase Operation Aborted 4 1 read-only INVADDR Invalid Write Address or Erase Page 2 1 read-only LOCKED Access Locked 1 1 read-only PENDING Write command is in queue 5 1 read-only PWRUPCKBDFAILCOUNT Flash power up checkerboard pattern chec 28 4 read-only REGLOCK Register Lock Status 16 1 read-only UNLOCKED 0 LOCKED 1 TIMEOUT Write command timeout flag 6 1 read-only WDATAREADY WDATA Write Ready 3 1 read-only WREADY Flash Write Ready 27 1 read-only TESTCTRL register locked by TESTLOCK 0x1A0 -1 read-write n 0x0 0x0 XADRINC Pattern check XADR Inc Mode 23 1 read-write ONE 0 TWO 1 USERDATASIZE No Description 0x34 -1 read-only n 0x0 0x0 USERDATASIZE User Data Size 0 6 read-only WDATA No Description 0x18 read-write n 0x0 0x0 DATAW Write Data 0 32 read-write WRITECMD No Description 0x10 write-only n 0x0 0x0 CLEARWDATA Clear WDATA state 12 1 write-only ERASEABORT Abort erase sequence 5 1 write-only ERASEMAIN0 Mass erase region 0 8 1 write-only ERASEPAGE Erase Page 1 1 write-only WRITEEND End Write Mode 2 1 write-only WRITECTRL No Description 0xC read-write n 0x0 0x0 IRQERASEABORT Abort Page Erase on Interrupt 1 1 read-write LPWRITE Low-Power Erase 3 1 read-write WREN Enable Write/Erase Controller 0 1 read-write PRORTC_NS PRORTC_NS Registers PRORTC_NS 0x0 0x0 0x1000 registers n PRORTC 39 CC0_CTRL No Description 0x30 -1 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC0_ICVALUE No Description 0x38 -1 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC0_OCVALUE No Description 0x34 -1 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_CTRL No Description 0x3C -1 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC1_ICVALUE No Description 0x44 -1 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC1_OCVALUE No Description 0x40 -1 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CFG No Description 0x8 -1 read-write n 0x0 0x0 CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0] 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CMD No Description 0xC -1 write-only n 0x0 0x0 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only CNT No Description 0x20 -1 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMBCNT No Description 0x24 -1 read-only n 0x0 0x0 CNTLSB Counter Value 15 17 read-only PRECNT Pre-Counter Value 0 15 read-only EN No Description 0x4 -1 read-write n 0x0 0x0 EN RTCC Enable 0 1 read-write IEN No Description 0x18 -1 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Enable 2 1 read-write CC1 CC Channel n Interrupt Enable 3 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write OF OF Interrupt Enable 0 1 read-write IF No Description 0x14 -1 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Flag 2 1 read-write CC1 CC Channel n Interrupt Flag 3 1 read-write CNTTICK Main counter tick 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 -1 read-only n 0x0 0x0 IPVERSION IP VERSION 0 32 read-only LOCK No Description 0x2C -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 PRECNT No Description 0x1C -1 read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 -1 read-only n 0x0 0x0 RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 RUNNING RTCC running status 0 1 read-only SYNCBUSY No Description 0x28 -1 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PRORTC_S PRORTC_S Registers PRORTC_S 0x0 0x0 0x1000 registers n PRORTC 39 CC0_CTRL No Description 0x30 -1 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC0_ICVALUE No Description 0x38 -1 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC0_OCVALUE No Description 0x34 -1 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_CTRL No Description 0x3C -1 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC1_ICVALUE No Description 0x44 -1 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC1_OCVALUE No Description 0x40 -1 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CFG No Description 0x8 -1 read-write n 0x0 0x0 CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0] 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CMD No Description 0xC -1 write-only n 0x0 0x0 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only CNT No Description 0x20 -1 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMBCNT No Description 0x24 -1 read-only n 0x0 0x0 CNTLSB Counter Value 15 17 read-only PRECNT Pre-Counter Value 0 15 read-only EN No Description 0x4 -1 read-write n 0x0 0x0 EN RTCC Enable 0 1 read-write IEN No Description 0x18 -1 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Enable 2 1 read-write CC1 CC Channel n Interrupt Enable 3 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write OF OF Interrupt Enable 0 1 read-write IF No Description 0x14 -1 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Flag 2 1 read-write CC1 CC Channel n Interrupt Flag 3 1 read-write CNTTICK Main counter tick 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 -1 read-only n 0x0 0x0 IPVERSION IP VERSION 0 32 read-only LOCK No Description 0x2C -1 write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 PRECNT No Description 0x1C -1 read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 -1 read-only n 0x0 0x0 RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 RUNNING RTCC running status 0 1 read-only SYNCBUSY No Description 0x28 -1 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only PROTIMER_NS PROTIMER_NS Registers PROTIMER_NS 0x0 0x0 0x1000 registers n PROTIMER 36 BASECNT No Description 0x1C read-write n 0x0 0x0 BASECNT Base Counter Value 0 16 read-write BASECNTTOP No Description 0x34 -1 read-write n 0x0 0x0 BASECNTTOP BASECNT Top Value 0 16 read-write BASEPRE No Description 0x24 read-only n 0x0 0x0 BASECNTV Base counter value 16 16 read-only PRECNTV Pre counter value 0 16 read-only CC0_BASE No Description 0x108 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC0_CTRL No Description 0x100 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC0_PRE No Description 0x104 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC0_WRAP No Description 0x10C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC1_BASE No Description 0x118 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC1_CTRL No Description 0x110 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC1_PRE No Description 0x114 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC1_WRAP No Description 0x11C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC2_BASE No Description 0x128 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC2_CTRL No Description 0x120 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC2_PRE No Description 0x124 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC2_WRAP No Description 0x12C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC3_BASE No Description 0x138 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC3_CTRL No Description 0x130 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC3_PRE No Description 0x134 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC3_WRAP No Description 0x13C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC4_BASE No Description 0x148 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC4_CTRL No Description 0x140 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC4_PRE No Description 0x144 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC4_WRAP No Description 0x14C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC5_BASE No Description 0x158 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC5_CTRL No Description 0x150 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC5_PRE No Description 0x154 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC5_WRAP No Description 0x15C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC6_BASE No Description 0x168 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC6_CTRL No Description 0x160 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC6_PRE No Description 0x164 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC6_WRAP No Description 0x16C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC7_BASE No Description 0x178 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC7_CTRL No Description 0x170 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC7_PRE No Description 0x174 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC7_WRAP No Description 0x17C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CMD No Description 0xC write-only n 0x0 0x0 LBTPAUSE Pause LBT sequence 17 1 write-only LBTSTART LBT sequence start 16 1 write-only LBTSTOP LBT sequence stop 18 1 write-only RTCSYNCSTART Start PROTIMER Synchronized with RTCC 1 1 write-only START Start PROTIMER 0 1 write-only STOP Stop PROTIMER 2 1 write-only TOUT0START Start Timeout counter 0 4 1 write-only TOUT0STOP Stop Timeout counter 0 5 1 write-only TOUT1START Start Timeout counter 1 6 1 write-only TOUT1STOP Stop Timeout counter 0 7 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 BASECNTSRC Selects clock to Base counter 12 2 read-write DISABLED Disable base counter 0 PRECNTOF Pre-counter overflow events 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 DEBUGRUN Debug Mode Run Enable 1 1 read-write X0 PROTIMER is frozen in debug mode 0 X1 PROTIMER is running in debug mode 1 DMACLRACT DMA Request Clear on Active 2 1 read-write OSMEN One-Shot Mode Enable 4 1 read-write X0 Protimer continues to count when WRAP counter overflows. 0 X1 Protimer stops counting when WRAP counter overflows. 1 PRECNTSRC Selects clock to Pre-counter 8 2 read-write DISABLED Disable Pre-counter 0 CLOCK Module clock 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 TOUT0MODE Repeat Mode 28 1 read-write FREE When started, the TOUT0 counts down until it is stopped by software 0 ONESHOT TOUT0 is stopped after it reaches zero 1 TOUT0SRC Selects clock to timeout counter 0 20 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT0SYNCSRC Select timeout counter 0 event 22 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT1MODE Repeat Mode 29 1 read-write FREE When started, the TOUT1 counts down until it is stopped by software 0 ONESHOT TOUT1 is stopped after it reaches zero 1 TOUT1SRC Selects clock to timeout counter 1 24 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT1SYNCSRC Select timeout counter 1 event 26 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 WRAPCNTSRC Selects clock to Wrap counter 16 2 read-write DISABLED Disable Wrap counter 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 UNUSED Do not use 3 ZEROSTARTEN Start from zero enable 5 1 read-write X0 Protimer starts from the previous count value 0 X1 Protimer starts counting from zero 1 EN No Description 0x4 read-write n 0x0 0x0 EN EN 0 1 read-write ETSI No Description 0x7C read-write n 0x0 0x0 CCAFIXED Fixed listening time 10 16 read-write ETSIEN ETSI LBT enabling 0 1 read-write GRANULARLESSTHANRXWARM Granular less than RXWARM 1 1 read-write RXWARMTHLD Minimum backoff period for RXWARM 2 8 read-write IEN No Description 0x70 read-write n 0x0 0x0 BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write IF No Description 0x64 read-write n 0x0 0x0 BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only LBTCTRL No Description 0x54 read-write n 0x0 0x0 CCADELAY Clear Channel Assessment Delay 8 5 read-write CCAREPEAT Clear Channel Assessment Repeat 16 4 read-write FIXEDBACKOFF Fixed backoff 20 1 read-write MAXEXP Maximum Exponent 4 4 read-write EXP0 MAXEXP value = 0 0 EXP1 MAXEXP value = 1 1 EXP2 MAXEXP value = 2 2 EXP3 MAXEXP value = 3 3 EXP4 MAXEXP value = 4 4 EXP5 MAXEXP value = 5 5 EXP6 MAXEXP value = 6 6 EXP7 MAXEXP value = 7 7 EXP8 MAXEXP value = 8 8 RETRYLIMIT Retry Limit 24 4 read-write STARTEXP Start Exponent 0 4 read-write EXP0 STARTEXP value = 0 (used for Fast TX) 0 EXP1 STARTEXP value = 1 1 EXP2 STARTEXP value = 2 2 EXP3 STARTEXP value = 3 3 EXP4 STARTEXP value = 4 4 EXP5 STARTEXP value = 5 5 EXP6 STARTEXP value = 6 6 EXP7 STARTEXP value = 7 7 EXP8 STARTEXP value = 8 8 LBTPRSCTRL No Description 0x58 read-write n 0x0 0x0 LBTPAUSEPRSEN Enable LBT pause commands from PRS. 16 1 read-write LBTSTARTPRSEN Enable LBT start commands from PRS. 8 1 read-write LBTSTOPPRSEN Enable LBT stop commands from PRS. 24 1 read-write LBTSTATE No Description 0x5C read-write n 0x0 0x0 TOUT0CNT TOUT0CNT value to be saved 16 16 read-write TOUT0PCNT TOUT0PCNT value to be saved 0 16 read-write LBTSTATE1 No Description 0x80 read-write n 0x0 0x0 CCACNT Current CCA counter value 0 4 read-write EXP LBT Exponent 4 4 read-write RETRYCNT LBT Retry counter 8 4 read-write LWRAPCNT No Description 0x28 read-only n 0x0 0x0 LWRAPCNT Latched Wrap Counter Value 0 32 read-only PRECNT No Description 0x18 read-write n 0x0 0x0 PRECNT Pre Counter Value 0 16 read-write PRECNTTOP No Description 0x30 -1 read-write n 0x0 0x0 PRECNTTOP PRECNT Top Value 8 16 read-write PRECNTTOPFRAC PRECNT Top Fractional Value 0 8 read-write PRECNTTOPADJ No Description 0x2C read-write n 0x0 0x0 PRECNTTOPADJ PRECNT Top Adjust Value 0 16 read-write PRSCTRL No Description 0x10 read-write n 0x0 0x0 RTCCTRIGGEREDGE RTCC Trigger Edge Select 18 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 RTCCTRIGGERPRSEN Enable RTCC Trigger from PRS. 17 1 read-write STARTEDGE Start Command Edge Select 2 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STARTPRSEN Enable Protimer start commands from PRS. 1 1 read-write STOPEDGE Stop Command Edge Select 10 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STOPPRSEN Enable Protimer stop commands from PRS. 9 1 read-write RANDOM No Description 0x60 read-write n 0x0 0x0 RANDOM Pseudo Random Value 0 16 read-write RANDOMFW0 No Description 0x84 read-write n 0x0 0x0 RANDOM0 Linear random backoff period from FW 0 9 read-write RANDOM1 Linear random backoff period from FW 9 9 read-write RANDOM2 Linear random backoff period from FW 18 9 read-write RANDOMFW1 No Description 0x88 read-write n 0x0 0x0 RANDOM3 Linear random backoff period from FW 0 9 read-write RANDOM4 Linear random backoff period from FW 9 9 read-write RANDOM5 Linear random backoff period from FW 18 9 read-write RANDOMFW2 No Description 0x8C read-write n 0x0 0x0 RANDOM6 Linear random backoff period from FW 0 9 read-write RANDOM7 Linear random backoff period from FW 9 9 read-write RXCTRL No Description 0x74 read-write n 0x0 0x0 RXCLREVENT1 First event that clears RX req signal 16 5 read-write RXCLREVENT2 Second event that clears RX req signal 24 5 read-write RXSETEVENT1 First event that sets RX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 PRECNTOF Pre counter overflow 2 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 RXSETEVENT2 Second event that sets RX req signal 8 5 read-write STATUS No Description 0x14 read-only n 0x0 0x0 ICV0 CC0 Capture Valid 8 1 read-only X0 PROTIMER_CC0_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC0_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV1 CC1 Capture Valid 9 1 read-only X0 PROTIMER_CC1_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC1_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV2 CC2 Capture Valid 10 1 read-only X0 PROTIMER_CC2_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC2_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV3 CC3 Capture Valid 11 1 read-only X0 PROTIMER_CC3_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC3_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV4 CC4 Capture Valid 12 1 read-only X0 PROTIMER_CC4_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC4_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV5 CC5 Capture Valid 13 1 read-only ICV6 CC6 Capture Valid 14 1 read-only ICV7 CC7 Capture Valid 15 1 read-only LBTPAUSED LBT has been paused. 3 1 read-only LBTRUNNING LBT Running 2 1 read-only LBTSYNC LBT Synchronizing 1 1 read-only RUNNING Running 0 1 read-only TOUT0RUNNING Timeout Counter 0 Running 4 1 read-only TOUT0SYNC Timeout Counter 0 Synchronizing 5 1 read-only TOUT1RUNNING Timeout Counter 1 Running 6 1 read-only TOUT1SYNC Timeout Counter 1 Synchronizing 7 1 read-only TOUT0CNT No Description 0x3C read-write n 0x0 0x0 TOUT0CNT TOUT0CNT Value 16 16 read-write TOUT0PCNT TOUT0PCNT Value 0 16 read-write TOUT0CNTTOP No Description 0x40 -1 read-write n 0x0 0x0 TOUT0CNTTOP TOUT0CNTTOP Value 16 16 read-write TOUT0PCNTTOP TOUT0PCNTTOP Value 0 16 read-write TOUT0COMP No Description 0x44 read-write n 0x0 0x0 TOUT0CNTCOMP TOUT0CNTCOMP Value 16 16 read-write TOUT0PCNTCOMP TOUT0PCNTCOMP 0 16 read-write TOUT1CNT No Description 0x48 read-write n 0x0 0x0 TOUT1CNT TOUT1CNT Value 16 16 read-write TOUT1PCNT TOUT1PCNT Value 0 16 read-write TOUT1CNTTOP No Description 0x4C -1 read-write n 0x0 0x0 TOUT1CNTTOP TOUT1CNTTOP Value 16 16 read-write TOUT1PCNTTOP TOUT1PCNTTOP Value 0 16 read-write TOUT1COMP No Description 0x50 read-write n 0x0 0x0 TOUT1CNTCOMP TOUT1CNTCOMP Value 16 16 read-write TOUT1PCNTCOMP TOUT1PCNTCOMP 0 16 read-write TXCTRL No Description 0x78 read-write n 0x0 0x0 TXSETEVENT1 First event that sets TX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 PRECNTOF Pre counter overflow 2 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 TXSETEVENT2 Second event that sets TX req signal 8 5 read-write WRAPCNT No Description 0x20 read-write n 0x0 0x0 WRAPCNT Wrap Counter Value 0 32 read-write WRAPCNTTOP No Description 0x38 -1 read-write n 0x0 0x0 WRAPCNTTOP WRAPCNT Top Value 0 32 read-write PROTIMER_S PROTIMER_S Registers PROTIMER_S 0x0 0x0 0x1000 registers n PROTIMER 36 BASECNT No Description 0x1C read-write n 0x0 0x0 BASECNT Base Counter Value 0 16 read-write BASECNTTOP No Description 0x34 -1 read-write n 0x0 0x0 BASECNTTOP BASECNT Top Value 0 16 read-write BASEPRE No Description 0x24 read-only n 0x0 0x0 BASECNTV Base counter value 16 16 read-only PRECNTV Pre counter value 0 16 read-only CC0_BASE No Description 0x108 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC0_CTRL No Description 0x100 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC0_PRE No Description 0x104 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC0_WRAP No Description 0x10C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC1_BASE No Description 0x118 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC1_CTRL No Description 0x110 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC1_PRE No Description 0x114 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC1_WRAP No Description 0x11C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC2_BASE No Description 0x128 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC2_CTRL No Description 0x120 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC2_PRE No Description 0x124 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC2_WRAP No Description 0x12C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC3_BASE No Description 0x138 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC3_CTRL No Description 0x130 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC3_PRE No Description 0x134 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC3_WRAP No Description 0x13C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC4_BASE No Description 0x148 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC4_CTRL No Description 0x140 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC4_PRE No Description 0x144 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC4_WRAP No Description 0x14C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC5_BASE No Description 0x158 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC5_CTRL No Description 0x150 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC5_PRE No Description 0x154 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC5_WRAP No Description 0x15C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC6_BASE No Description 0x168 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC6_CTRL No Description 0x160 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC6_PRE No Description 0x164 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC6_WRAP No Description 0x16C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CC7_BASE No Description 0x178 read-write n 0x0 0x0 BASE CC Channel BASE Value 0 16 read-write CC7_CTRL No Description 0x170 read-write n 0x0 0x0 BASEMATCHEN Enable BASECNT matching 3 1 read-write CCMODE Compare/Capture mode 1 1 read-write COMPARE Compare mode selected 0 CAPTURE Capture mode selected 1 ENABLE Channel Enable 0 1 read-write ICEDGE Input Capture Edge Select 25 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 INSEL Capture input selection 21 4 read-write PRS Use the selected PRS channel 0 TXDONE TX completed 1 PRORTC1 PRORTC capture/compare 1 10 RXDONE RX completed 2 TXORRXDONE TX or RX completed 3 FRAMEDET0 Demodulator found sync word 0 4 FRAMEDET1 Demodulator found sync word 1 5 FDET0OR1 Demodulator found sync word 0 or 1 6 MODSYNCSENT Modulator sync word sent 7 RXEOF RX at end of frame from demodulator 8 PRORTC0 PRORTC capture/compare 0 9 MOA Match Output Action 8 2 read-write DISABLED No action on compare match 0 TOGGLE Toggle output on compare match in COMPARE mode. 1 CLEAR Clear output on compare match in COMPARE mode. 2 SET Set output on compare match in COMPARE mode. 3 OFOA Overflow Output Action 10 2 read-write DISABLED No action 0 TOGGLE Toggle output when the selected counter has an overflow event. 1 CLEAR Clear output when the selected counter has an overflow event. 2 SET Set output when the selected counter has an overflow event. 3 OFSEL Select counter for OFOA bits 12 2 read-write PRECNT Use PRECNT overflow 0 BASECNT Use BASECNT overflow 1 WRAPCNT Use WRAPCNT overflow 2 DISABLED Disabled 3 OIST Output Initial State 5 1 read-write OUTINV Output Invert 6 1 read-write PREMATCHEN Enable PRECNT matching 2 1 read-write PRSCONF PRS Configuration 14 1 read-write PULSE Each CC event will generate a one HFRADIOCLK cycle high pulse 0 LEVEL Should be used when OFSEL, OFOA or MOA are specified. 1 WRAPMATCHEN Enable WRAPCNT matching 4 1 read-write CC7_PRE No Description 0x174 read-write n 0x0 0x0 PRE CC Channel PRE Value 0 16 read-write CC7_WRAP No Description 0x17C read-write n 0x0 0x0 WRAP CC Channel WRAP Value 0 32 read-write CMD No Description 0xC write-only n 0x0 0x0 LBTPAUSE Pause LBT sequence 17 1 write-only LBTSTART LBT sequence start 16 1 write-only LBTSTOP LBT sequence stop 18 1 write-only RTCSYNCSTART Start PROTIMER Synchronized with RTCC 1 1 write-only START Start PROTIMER 0 1 write-only STOP Stop PROTIMER 2 1 write-only TOUT0START Start Timeout counter 0 4 1 write-only TOUT0STOP Stop Timeout counter 0 5 1 write-only TOUT1START Start Timeout counter 1 6 1 write-only TOUT1STOP Stop Timeout counter 0 7 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 BASECNTSRC Selects clock to Base counter 12 2 read-write DISABLED Disable base counter 0 PRECNTOF Pre-counter overflow events 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 DEBUGRUN Debug Mode Run Enable 1 1 read-write X0 PROTIMER is frozen in debug mode 0 X1 PROTIMER is running in debug mode 1 DMACLRACT DMA Request Clear on Active 2 1 read-write OSMEN One-Shot Mode Enable 4 1 read-write X0 Protimer continues to count when WRAP counter overflows. 0 X1 Protimer stops counting when WRAP counter overflows. 1 PRECNTSRC Selects clock to Pre-counter 8 2 read-write DISABLED Disable Pre-counter 0 CLOCK Module clock 1 UNUSED0 Do not use 2 UNUSED1 Do not use 3 TOUT0MODE Repeat Mode 28 1 read-write FREE When started, the TOUT0 counts down until it is stopped by software 0 ONESHOT TOUT0 is stopped after it reaches zero 1 TOUT0SRC Selects clock to timeout counter 0 20 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT0SYNCSRC Select timeout counter 0 event 22 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 TOUT1MODE Repeat Mode 29 1 read-write FREE When started, the TOUT1 counts down until it is stopped by software 0 ONESHOT TOUT1 is stopped after it reaches zero 1 TOUT1SRC Selects clock to timeout counter 1 24 2 read-write DISABLED No counting 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 WRAPCNTOF Wrap counter overflow events 3 TOUT1SYNCSRC Select timeout counter 1 event 26 2 read-write DISABLED No synchronization 0 PRECNTOF Pre-counter overflow event 1 BASECNTOF Base counter overflow event 2 WRAPCNTOF Wrap counter overflow event 3 WRAPCNTSRC Selects clock to Wrap counter 16 2 read-write DISABLED Disable Wrap counter 0 PRECNTOF Pre-counter overflow events 1 BASECNTOF Base counter overflow events 2 UNUSED Do not use 3 ZEROSTARTEN Start from zero enable 5 1 read-write X0 Protimer starts from the previous count value 0 X1 Protimer starts counting from zero 1 EN No Description 0x4 read-write n 0x0 0x0 EN EN 0 1 read-write ETSI No Description 0x7C read-write n 0x0 0x0 CCAFIXED Fixed listening time 10 16 read-write ETSIEN ETSI LBT enabling 0 1 read-write GRANULARLESSTHANRXWARM Granular less than RXWARM 1 1 read-write RXWARMTHLD Minimum backoff period for RXWARM 2 8 read-write IEN No Description 0x70 read-write n 0x0 0x0 BASECNTOF BASECNTOF Interrupt Enable 1 1 read-write CC0 CC0 Interrupt Enable 8 1 read-write CC1 CC1 Interrupt Enable 9 1 read-write CC2 CC2 Interrupt Enable 10 1 read-write CC3 CC3 Interrupt Enable 11 1 read-write CC4 CC4 Interrupt Enable 12 1 read-write CC5 CC5 Interrupt Enable 13 1 read-write CC6 CC6 Interrupt Enable 14 1 read-write CC7 CC7 Interrupt Enable 15 1 read-write COF0 COF0 Interrupt Enable 16 1 read-write COF1 COF1 Interrupt Enable 17 1 read-write COF2 COF2 Interrupt Enable 18 1 read-write COF3 COF3 Interrupt Enable 19 1 read-write COF4 COF4 Interrupt Enable 20 1 read-write COF5 COF5 Interrupt Enable 21 1 read-write COF6 COF6 Interrupt Enable 22 1 read-write COF7 COF7 Interrupt Enable 23 1 read-write LBTFAILURE LBTFAILURE Interrupt Enable 25 1 read-write LBTPAUSED LBTPAUSED Interrupt Enable 26 1 read-write LBTRETRY LBTRETRY Interrupt Enable 27 1 read-write LBTSUCCESS LBTSUCCESS Interrupt Enable 24 1 read-write PRECNTOF PRECNTOF Interrupt Enable 0 1 read-write RTCCSYNCHED RTCCSYNCHED Interrupt Enable 28 1 read-write TOUT0 TOUT0 Interrupt Enable 4 1 read-write TOUT0MATCH TOUT0MATCH Interrupt Enable 6 1 read-write TOUT0MATCHLBT TOUT0MATCHLBT Interrupt Enable 29 1 read-write TOUT1 TOUT1 Interrupt Enable 5 1 read-write TOUT1MATCH TOUT1MATCH Interrupt Enable 7 1 read-write WRAPCNTOF WRAPCNTOF Interrupt Enable 2 1 read-write IF No Description 0x64 read-write n 0x0 0x0 BASECNTOF BASECNT Overflow Interrupt Flag 1 1 read-write CC0 CC Channel 0 Interrupt Flag 8 1 read-write CC1 CC Channel 1 Interrupt Flag 9 1 read-write CC2 CC Channel 2 Interrupt Flag 10 1 read-write CC3 CC Channel 3 Interrupt Flag 11 1 read-write CC4 CC Channel 4 Interrupt Flag 12 1 read-write CC5 CC Channel 5 Interrupt Flag 13 1 read-write CC6 CC Channel 6 Interrupt Flag 14 1 read-write CC7 CC Channel 7 Interrupt Flag 15 1 read-write COF0 CC Channel 0 Overflow Interrupt Flag 16 1 read-write COF1 CC Channel 1 Overflow Interrupt Flag 17 1 read-write COF2 CC Channel 2 Overflow Interrupt Flag 18 1 read-write COF3 CC Channel 3 Overflow Interrupt Flag 19 1 read-write COF4 CC Channel 4 Overflow Interrupt Flag 20 1 read-write COF5 CC Channel 5 Overflow Interrupt Flag 21 1 read-write COF6 CC Channel 6 Overflow Interrupt Flag 22 1 read-write COF7 CC Channel 7 Overflow Interrupt Flag 23 1 read-write LBTFAILURE Listen Before Talk Failure 25 1 read-write LBTPAUSED Listen Before Talk Paused 26 1 read-write LBTRETRY Listen Before Talk Retry 27 1 read-write LBTSUCCESS Listen Before Talk Success 24 1 read-write PRECNTOF PRECNT Overflow Interrupt Flag 0 1 read-write RTCCSYNCHED PROTIMER synchronized with the RTCC 28 1 read-write TOUT0 TOUT0 underflow interrupt flag 4 1 read-write TOUT0MATCH TOUT0 compare match interrupt flag 6 1 read-write TOUT0MATCHLBT TOUT0 compare match interrupt flag 29 1 read-write TOUT1 TOUT1 underflow interrupt flag 5 1 read-write TOUT1MATCH TOUT1 compare match interrupt flag 7 1 read-write WRAPCNTOF WRAPCNT Overflow Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only LBTCTRL No Description 0x54 read-write n 0x0 0x0 CCADELAY Clear Channel Assessment Delay 8 5 read-write CCAREPEAT Clear Channel Assessment Repeat 16 4 read-write FIXEDBACKOFF Fixed backoff 20 1 read-write MAXEXP Maximum Exponent 4 4 read-write EXP0 MAXEXP value = 0 0 EXP1 MAXEXP value = 1 1 EXP2 MAXEXP value = 2 2 EXP3 MAXEXP value = 3 3 EXP4 MAXEXP value = 4 4 EXP5 MAXEXP value = 5 5 EXP6 MAXEXP value = 6 6 EXP7 MAXEXP value = 7 7 EXP8 MAXEXP value = 8 8 RETRYLIMIT Retry Limit 24 4 read-write STARTEXP Start Exponent 0 4 read-write EXP0 STARTEXP value = 0 (used for Fast TX) 0 EXP1 STARTEXP value = 1 1 EXP2 STARTEXP value = 2 2 EXP3 STARTEXP value = 3 3 EXP4 STARTEXP value = 4 4 EXP5 STARTEXP value = 5 5 EXP6 STARTEXP value = 6 6 EXP7 STARTEXP value = 7 7 EXP8 STARTEXP value = 8 8 LBTPRSCTRL No Description 0x58 read-write n 0x0 0x0 LBTPAUSEPRSEN Enable LBT pause commands from PRS. 16 1 read-write LBTSTARTPRSEN Enable LBT start commands from PRS. 8 1 read-write LBTSTOPPRSEN Enable LBT stop commands from PRS. 24 1 read-write LBTSTATE No Description 0x5C read-write n 0x0 0x0 TOUT0CNT TOUT0CNT value to be saved 16 16 read-write TOUT0PCNT TOUT0PCNT value to be saved 0 16 read-write LBTSTATE1 No Description 0x80 read-write n 0x0 0x0 CCACNT Current CCA counter value 0 4 read-write EXP LBT Exponent 4 4 read-write RETRYCNT LBT Retry counter 8 4 read-write LWRAPCNT No Description 0x28 read-only n 0x0 0x0 LWRAPCNT Latched Wrap Counter Value 0 32 read-only PRECNT No Description 0x18 read-write n 0x0 0x0 PRECNT Pre Counter Value 0 16 read-write PRECNTTOP No Description 0x30 -1 read-write n 0x0 0x0 PRECNTTOP PRECNT Top Value 8 16 read-write PRECNTTOPFRAC PRECNT Top Fractional Value 0 8 read-write PRECNTTOPADJ No Description 0x2C read-write n 0x0 0x0 PRECNTTOPADJ PRECNT Top Adjust Value 0 16 read-write PRSCTRL No Description 0x10 read-write n 0x0 0x0 RTCCTRIGGEREDGE RTCC Trigger Edge Select 18 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 RTCCTRIGGERPRSEN Enable RTCC Trigger from PRS. 17 1 read-write STARTEDGE Start Command Edge Select 2 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STARTPRSEN Enable Protimer start commands from PRS. 1 1 read-write STOPEDGE Stop Command Edge Select 10 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 DISABLED No edge detection, signal is left as it is 3 STOPPRSEN Enable Protimer stop commands from PRS. 9 1 read-write RANDOM No Description 0x60 read-write n 0x0 0x0 RANDOM Pseudo Random Value 0 16 read-write RANDOMFW0 No Description 0x84 read-write n 0x0 0x0 RANDOM0 Linear random backoff period from FW 0 9 read-write RANDOM1 Linear random backoff period from FW 9 9 read-write RANDOM2 Linear random backoff period from FW 18 9 read-write RANDOMFW1 No Description 0x88 read-write n 0x0 0x0 RANDOM3 Linear random backoff period from FW 0 9 read-write RANDOM4 Linear random backoff period from FW 9 9 read-write RANDOM5 Linear random backoff period from FW 18 9 read-write RANDOMFW2 No Description 0x8C read-write n 0x0 0x0 RANDOM6 Linear random backoff period from FW 0 9 read-write RANDOM7 Linear random backoff period from FW 9 9 read-write RXCTRL No Description 0x74 read-write n 0x0 0x0 RXCLREVENT1 First event that clears RX req signal 16 5 read-write RXCLREVENT2 Second event that clears RX req signal 24 5 read-write RXSETEVENT1 First event that sets RX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 PRECNTOF Pre counter overflow 2 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 RXSETEVENT2 Second event that sets RX req signal 8 5 read-write STATUS No Description 0x14 read-only n 0x0 0x0 ICV0 CC0 Capture Valid 8 1 read-only X0 PROTIMER_CC0_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC0_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV1 CC1 Capture Valid 9 1 read-only X0 PROTIMER_CC1_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC1_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV2 CC2 Capture Valid 10 1 read-only X0 PROTIMER_CC2_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC2_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV3 CC3 Capture Valid 11 1 read-only X0 PROTIMER_CC3_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC3_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV4 CC4 Capture Valid 12 1 read-only X0 PROTIMER_CC4_PRE, -BASE or -WRAP does not contain a valid capture value 0 X1 PROTIMER_CC4_PRE, -BASE or -WRAP contains a valid and unread capture value 1 ICV5 CC5 Capture Valid 13 1 read-only ICV6 CC6 Capture Valid 14 1 read-only ICV7 CC7 Capture Valid 15 1 read-only LBTPAUSED LBT has been paused. 3 1 read-only LBTRUNNING LBT Running 2 1 read-only LBTSYNC LBT Synchronizing 1 1 read-only RUNNING Running 0 1 read-only TOUT0RUNNING Timeout Counter 0 Running 4 1 read-only TOUT0SYNC Timeout Counter 0 Synchronizing 5 1 read-only TOUT1RUNNING Timeout Counter 1 Running 6 1 read-only TOUT1SYNC Timeout Counter 1 Synchronizing 7 1 read-only TOUT0CNT No Description 0x3C read-write n 0x0 0x0 TOUT0CNT TOUT0CNT Value 16 16 read-write TOUT0PCNT TOUT0PCNT Value 0 16 read-write TOUT0CNTTOP No Description 0x40 -1 read-write n 0x0 0x0 TOUT0CNTTOP TOUT0CNTTOP Value 16 16 read-write TOUT0PCNTTOP TOUT0PCNTTOP Value 0 16 read-write TOUT0COMP No Description 0x44 read-write n 0x0 0x0 TOUT0CNTCOMP TOUT0CNTCOMP Value 16 16 read-write TOUT0PCNTCOMP TOUT0PCNTCOMP 0 16 read-write TOUT1CNT No Description 0x48 read-write n 0x0 0x0 TOUT1CNT TOUT1CNT Value 16 16 read-write TOUT1PCNT TOUT1PCNT Value 0 16 read-write TOUT1CNTTOP No Description 0x4C -1 read-write n 0x0 0x0 TOUT1CNTTOP TOUT1CNTTOP Value 16 16 read-write TOUT1PCNTTOP TOUT1PCNTTOP Value 0 16 read-write TOUT1COMP No Description 0x50 read-write n 0x0 0x0 TOUT1CNTCOMP TOUT1CNTCOMP Value 16 16 read-write TOUT1PCNTCOMP TOUT1PCNTCOMP 0 16 read-write TXCTRL No Description 0x78 read-write n 0x0 0x0 TXSETEVENT1 First event that sets TX req signal 0 5 read-write DISABLED Request is never set 0 ALWAYS Does not wait for any particular event 1 CC1 Channel 1 Capture/Compare event 10 CC2 Channel 2 Capture/Compare event 11 CC3 Channel 3 Capture/Compare event 12 CC4 Channel 4 Capture/Compare event 13 TXDONE MOD indicated that TX completed 14 RXDONE FRC indicated that RX completed 15 TXORRXDONE MOD/FRC indicated that TX or RX completed 16 FDET0 DEMOD indicated that syncword 0 was detected 17 FDET1 DEMOD indicated that syncword 1 was detected 18 FDET0OR1 DEMOD indicated that syncword 0 or 1 was detected 19 PRECNTOF Pre counter overflow 2 LBTSUCCESS LBT completed successfully 20 LBTRETRY LBT detected occupied channel and will try again 21 LBTFAILURE LBT could not start transmission 22 ANYLBT Any LBT event 23 CCAACK A CCA measurement completed 24 CCA A CCA measurement completed, and channel was clear 25 NOTCCA A CCA measurement completed, and channel was busy 26 TOUT0MATCHLBT Timeout counter 0 match occurred during LBT operation 27 BASECNTOF Base counter overflow 3 WRAPCNTOF Wrap counter overflow 4 TOUT0UF Timeout counter 0 underflow 5 TOUT1UF Timeout counter 1 underflow 6 TOUT0MATCH Timeout counter 0 match 7 TOUT1MATCH Timeout counter 1 match 8 CC0 Channel 0 Capture/Compare event 9 TXSETEVENT2 Second event that sets TX req signal 8 5 read-write WRAPCNT No Description 0x20 read-write n 0x0 0x0 WRAPCNT Wrap Counter Value 0 32 read-write WRAPCNTTOP No Description 0x38 -1 read-write n 0x0 0x0 WRAPCNTTOP WRAPCNT Top Value 0 32 read-write PRS_NS PRS_NS Registers PRS_NS 0x0 0x0 0x1000 registers n ASYNC_CH0_CTRL No Description 0x18 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH10_CTRL No Description 0x40 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH11_CTRL No Description 0x44 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH1_CTRL No Description 0x1C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH2_CTRL No Description 0x20 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH3_CTRL No Description 0x24 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH4_CTRL No Description 0x28 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH5_CTRL No Description 0x2C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH6_CTRL No Description 0x30 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH7_CTRL No Description 0x34 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH8_CTRL No Description 0x38 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH9_CTRL No Description 0x3C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_PEEK No Description 0x10 read-only n 0x0 0x0 CH0VAL Channel 0 Current Value 0 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only ASYNC_SWLEVEL No Description 0xC read-write n 0x0 0x0 CH0LEVEL Channel Level 0 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write ASYNC_SWPULSE No Description 0x8 write-only n 0x0 0x0 CH0PULSE Channel pulse 0 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CONSUMER_CMU_CALDN No Description 0x58 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CMU_CALUP No Description 0x5C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN0 No Description 0x108 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN1 No Description 0x10C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN2 No Description 0x110 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN3 No Description 0x114 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_M33RXEV No Description 0x118 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_IADC0_SCANTRIGGER No Description 0x64 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER No Description 0x68 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 No Description 0x6C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 No Description 0x70 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_CLEAR No Description 0x74 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_START No Description 0x78 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_STOP No Description 0x7C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_MODEM_DIN No Description 0x80 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_CLR No Description 0xB8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_FORCETX No Description 0xBC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_RXDIS No Description 0xC0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_RXEN No Description 0xC4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_SEQ No Description 0xC8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_TXEN No Description 0xCC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC0 No Description 0xD0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC1 No Description 0xD4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC2 No Description 0xD8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC0 No Description 0xE0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC1 No Description 0xE4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC2 No Description 0xE8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC3 No Description 0xEC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC4 No Description 0xF0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC5 No Description 0xF4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC6 No Description 0xF8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC7 No Description 0xFC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_CC0 No Description 0x11C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_CC1 No Description 0x120 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_CC2 No Description 0x124 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_DTI No Description 0x128 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_DTIFS1 No Description 0x12C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_DTIFS2 No Description 0x130 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_CC0 No Description 0x134 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_CC1 No Description 0x138 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_CC2 No Description 0x13C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_DTI No Description 0x140 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_DTIFS1 No Description 0x144 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_DTIFS2 No Description 0x148 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_CC0 No Description 0x14C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_CC1 No Description 0x150 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_CC2 No Description 0x154 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_DTI No Description 0x158 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_DTIFS1 No Description 0x15C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_DTIFS2 No Description 0x160 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_CC0 No Description 0x164 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_CC1 No Description 0x168 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_CC2 No Description 0x16C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_DTI No Description 0x170 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_DTIFS1 No Description 0x174 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_DTIFS2 No Description 0x178 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_CLK No Description 0x17C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_IR No Description 0x180 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_RX No Description 0x184 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_TRIGGER No Description 0x188 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_CLK No Description 0x18C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_IR No Description 0x190 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_RX No Description 0x194 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_TRIGGER No Description 0x198 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_CLK No Description 0x19C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_IR No Description 0x1A0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_RX No Description 0x1A4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_TRIGGER No Description 0x1A8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG0_SRC0 No Description 0x1AC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG0_SRC1 No Description 0x1B0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG1_SRC0 No Description 0x1B4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG1_SRC1 No Description 0x1B8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only SYNC_CH0_CTRL No Description 0x48 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x4C read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x50 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x54 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_PEEK No Description 0x14 read-only n 0x0 0x0 CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only PRS_S PRS_S Registers PRS_S 0x0 0x0 0x1000 registers n ASYNC_CH0_CTRL No Description 0x18 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH10_CTRL No Description 0x40 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH11_CTRL No Description 0x44 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH1_CTRL No Description 0x1C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH2_CTRL No Description 0x20 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH3_CTRL No Description 0x24 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH4_CTRL No Description 0x28 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH5_CTRL No Description 0x2C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH6_CTRL No Description 0x30 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH7_CTRL No Description 0x34 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH8_CTRL No Description 0x38 -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_CH9_CTRL No Description 0x3C -1 read-write n 0x0 0x0 FNSEL Function Select 16 4 read-write LOGICAL_ZERO Logical 0 0 A_NOR_B A NOR B 1 B B 10 NOT_A_OR_B (!A) OR B 11 A A 12 A_OR_NOT_B A OR (!B) 13 A_OR_B A OR B 14 LOGICAL_ONE Logical 1 15 NOT_A_AND_B (!A) AND B 2 NOT_A !A 3 A_AND_NOT_B A AND (!B) 4 NOT_B !B 5 A_XOR_B A XOR B 6 A_NAND_B A NAND B 7 A_AND_B A AND B 8 A_XNOR_B A XNOR B 9 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write ASYNC_PEEK No Description 0x10 read-only n 0x0 0x0 CH0VAL Channel 0 Current Value 0 1 read-only CH10VAL Channel 10 Current Value 10 1 read-only CH11VAL Channel 11 Current Value 11 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only CH4VAL Channel 4 Current Value 4 1 read-only CH5VAL Channel 5 Current Value 5 1 read-only CH6VAL Channel 6 Current Value 6 1 read-only CH7VAL Channel 7 Current Value 7 1 read-only CH8VAL Channel 8 Current Value 8 1 read-only CH9VAL Channel 9 Current Value 9 1 read-only ASYNC_SWLEVEL No Description 0xC read-write n 0x0 0x0 CH0LEVEL Channel Level 0 1 read-write CH10LEVEL Channel Level 10 1 read-write CH11LEVEL Channel Level 11 1 read-write CH1LEVEL Channel Level 1 1 read-write CH2LEVEL Channel Level 2 1 read-write CH3LEVEL Channel Level 3 1 read-write CH4LEVEL Channel Level 4 1 read-write CH5LEVEL Channel Level 5 1 read-write CH6LEVEL Channel Level 6 1 read-write CH7LEVEL Channel Level 7 1 read-write CH8LEVEL Channel Level 8 1 read-write CH9LEVEL Channel Level 9 1 read-write ASYNC_SWPULSE No Description 0x8 write-only n 0x0 0x0 CH0PULSE Channel pulse 0 1 write-only CH10PULSE Channel pulse 10 1 write-only CH11PULSE Channel pulse 11 1 write-only CH1PULSE Channel pulse 1 1 write-only CH2PULSE Channel pulse 2 1 write-only CH3PULSE Channel pulse 3 1 write-only CH4PULSE Channel pulse 4 1 write-only CH5PULSE Channel pulse 5 1 write-only CH6PULSE Channel pulse 6 1 write-only CH7PULSE Channel pulse 7 1 write-only CH8PULSE Channel pulse 8 1 write-only CH9PULSE Channel pulse 9 1 write-only CONSUMER_CMU_CALDN No Description 0x58 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CMU_CALUP No Description 0x5C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN0 No Description 0x108 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN1 No Description 0x10C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN2 No Description 0x110 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_CTIIN3 No Description 0x114 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_CORE_M33RXEV No Description 0x118 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_IADC0_SCANTRIGGER No Description 0x64 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_IADC0_SINGLETRIGGER No Description 0x68 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_LDMAXBAR_DMAREQ0 No Description 0x6C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LDMAXBAR_DMAREQ1 No Description 0x70 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_CLEAR No Description 0x74 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_START No Description 0x78 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_LETIMER0_STOP No Description 0x7C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_MODEM_DIN No Description 0x80 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_CLR No Description 0xB8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_FORCETX No Description 0xBC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_RXDIS No Description 0xC0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_RXEN No Description 0xC4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_SEQ No Description 0xC8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RAC_TXEN No Description 0xCC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC0 No Description 0xD0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC1 No Description 0xD4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_RTCC_CC2 No Description 0xD8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC0 No Description 0xE0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC1 No Description 0xE4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC2 No Description 0xE8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC3 No Description 0xEC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC4 No Description 0xF0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC5 No Description 0xF4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC6 No Description 0xF8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_SE_TAMPERSRC7 No Description 0xFC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_CC0 No Description 0x11C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_CC1 No Description 0x120 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_CC2 No Description 0x124 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER0_DTI No Description 0x128 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_DTIFS1 No Description 0x12C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER0_DTIFS2 No Description 0x130 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_CC0 No Description 0x134 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_CC1 No Description 0x138 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_CC2 No Description 0x13C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER1_DTI No Description 0x140 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_DTIFS1 No Description 0x144 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER1_DTIFS2 No Description 0x148 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_CC0 No Description 0x14C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_CC1 No Description 0x150 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_CC2 No Description 0x154 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER2_DTI No Description 0x158 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_DTIFS1 No Description 0x15C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER2_DTIFS2 No Description 0x160 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_CC0 No Description 0x164 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_CC1 No Description 0x168 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_CC2 No Description 0x16C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write SPRSSEL Synchronous Channel Selection 8 2 read-write CONSUMER_TIMER3_DTI No Description 0x170 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_DTIFS1 No Description 0x174 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_TIMER3_DTIFS2 No Description 0x178 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_CLK No Description 0x17C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_IR No Description 0x180 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_RX No Description 0x184 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART0_TRIGGER No Description 0x188 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_CLK No Description 0x18C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_IR No Description 0x190 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_RX No Description 0x194 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART1_TRIGGER No Description 0x198 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_CLK No Description 0x19C read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_IR No Description 0x1A0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_RX No Description 0x1A4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_USART2_TRIGGER No Description 0x1A8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG0_SRC0 No Description 0x1AC read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG0_SRC1 No Description 0x1B0 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG1_SRC0 No Description 0x1B4 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write CONSUMER_WDOG1_SRC1 No Description 0x1B8 read-write n 0x0 0x0 PRSSEL Asynchronous Channel Selection 0 4 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP version ID 0 32 read-only SYNC_CH0_CTRL No Description 0x48 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH1_CTRL No Description 0x4C read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH2_CTRL No Description 0x50 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_CH3_CTRL No Description 0x54 read-write n 0x0 0x0 SIGSEL Signal Select 0 3 read-write NONE 0 SOURCESEL Source Select 8 7 read-write SYNC_PEEK No Description 0x14 read-only n 0x0 0x0 CH0VAL Channel 0 Current Value 0 1 read-only CH1VAL Channel 1 Current Value 1 1 read-only CH2VAL Channel 2 Current Value 2 1 read-only CH3VAL Channel 3 Current Value 3 1 read-only RAC_NS RAC_NS Registers RAC_NS 0x0 0x0 0x1000 registers n RAC_RSM 37 RAC_SEQ 38 ANTDIV No Description 0x174 read-write n 0x0 0x0 EN EN 0 8 read-write OFF All controls off 0 PAENANT1 Control pa_en_ant1 1 SYLODIVRLO22G4EN Control sy_lodiv_rlo2_2g4_en 128 PAENANT2 Control pa_en_ant2 16 LNAMIXEN1 Control lnamix_en1 2 ON All controls on 255 LNAMIXEN2 Control lnamix_en2 32 LNAMIXRFPKDENRF1 Control lnamix_rfpkd_en_rf1 4 LNAMIXRFPKDENRF2 Control lnamix_rfpkd_en_rf2 64 SYLODIVRLO12G4EN Control sy_lodiv_rlo1_2g4_en 8 STATUS STATUS 8 2 read-only OFF Both antenna disabled 0 ANT1 Antenna 1 enabled 1 ANT2 Antenna 2 enabled 2 BOTH Both antenna enabled 3 APC No Description 0xA8 -1 read-write n 0x0 0x0 AMPCONTROLLIMITSW software amp_control top limit 24 8 read-write ENAPCSW software control bit for apc 2 1 read-write DISABLE 0 ENABLE 1 AUXADCCTRL0 No Description 0xB4 -1 read-write n 0x0 0x0 CLRCOUNTER Clear counter 12 1 read-write CLRFILTER Clear accumulators 13 1 read-write CYCLES Cycle number to run 0 10 read-write INPUTRESSEL Select input resource 14 4 read-write MUXSEL Select accumulator 10 2 read-write AUXADCCTRL1 0xB8 read-write n 0x0 0x0 AUXADCINPUTRESSEL AUXADCINPUTRESSEL 0 4 read-write RES640kOhm 0 RES320kOhm 1 RES0p6kOhm 10 RES_switch 11 RES160kOhm 2 RES80kOhm 3 RES40kOhm 4 RES20kOhm 5 RES10kOhm 6 RES5kOhm 7 RES2p5kOhm 8 RES1p25kOhm 9 AUXADCINPUTSELECT AUXADCINPUTSELECT 4 4 read-write SEL0 0 SEL1 1 SEL2 2 SEL3 3 SEL4 4 SEL5 5 SEL6 6 SEL7 7 SEL8 8 SEL9 9 AUXADCPMONSELECT AUXADCPMONSELECT 8 4 read-write AUXADCRESET AUXADCRESET 24 1 read-write Reset_Enabled 0 Reset_Disabled 1 AUXADCTSENSESELCURR AUXADCTSENSESELCURR 16 5 read-write AUXADCTSENSESELVBE AUXADCTSENSESELVBE 25 1 read-write VBE1 0 VBE2 1 AUXADCEN 0xB0 read-write n 0x0 0x0 AUXADCENAUXADC AUXADCENAUXADC 0 1 read-write Disabled 0 Enabled 1 AUXADCENINPUTBUFFER AUXADCENINPUTBUFFER 1 1 read-write Disabled 0 Enabled 1 AUXADCENLDO AUXADCENLDO 2 1 read-write Disabled 0 Enabled 1 AUXADCENOUTPUTDRV AUXADCENOUTPUTDRV 3 1 read-write Disabled 0 Enabled 1 AUXADCENPMON AUXADCENPMON 4 1 read-write Disabled 0 Enabled 1 AUXADCENRESONDIAGA AUXADCENRESONDIAGA 5 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSE AUXADCENTSENSE 6 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSECAL AUXADCENTSENSECAL 7 1 read-write Disabled 0 Enabled 1 AUXADCINPUTBUFFERBYPASS AUXADCINPUTBUFFERBYPASS 8 1 read-write Not_Bypassed 0 Bypassed 1 AUXADCOUT No Description 0xBC read-only n 0x0 0x0 AUXADCOUT AUXADC output 0 28 read-only AUXADCTRIM 0xAC -1 read-write n 0x0 0x0 AUXADCCLKINVERT AUXADCCLKINVERT 0 1 read-write Disable_Invert 0 Enable_Invert 1 AUXADCLDOVREFTRIM AUXADCLDOVREFTRIM 1 2 read-write TRIM1p27 0 TRIM1p3 1 TRIM1p35 2 TRIM1p4 3 AUXADCOUTPUTINVERT AUXADCOUTPUTINVERT 3 1 read-write Disabled 0 Enabled 1 AUXADCRCTUNE AUXADCRCTUNE 4 5 read-write AUXADCTRIMADCINPUTRES AUXADCTRIMADCINPUTRES 9 2 read-write RES200k 0 RES250k 1 RES300k 2 RES350k 3 AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURRINPUTBUF 11 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA1 13 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA2 AUXADCTRIMCURROPA2 15 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRREFBUF 17 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRTSENSE AUXADCTRIMCURRTSENSE 19 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRVCMBUF AUXADCTRIMCURRVCMBUF 21 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMLDOHIGHCURRENT 23 1 read-write LowCurrentMode 0 HighCurrentMode 1 AUXADCTRIMREFP AUXADCTRIMREFP 24 2 read-write REF1p05 0 REF1p16 1 REF1p2 2 REF1p25 3 AUXADCTRIMVREFVCM AUXADCTRIMVREFVCM 26 2 read-write Trim0p6 0 Trim0p65 1 Trim0p7 2 Trim0p75 3 AUXADCTSENSETRIMVBE2 AUXADCTSENSETRIMVBE2 28 1 read-write VBE_16uA 0 VBE_32uA 1 BREAKPOINT No Description 0x30 read-write n 0x0 0x0 BKPADDR Sequencer Breakpoint Address 0 32 read-write CLKMULTCTRL 0xC8 -1 read-write n 0x0 0x0 CLKMULTDIVN CLKMULTDIVN 0 7 read-write CLKMULTDIVR CLKMULTDIVR 7 3 read-write CLKMULTDIVX CLKMULTDIVX 10 3 read-write div_1 0 div_2 1 div_4 2 div_6 3 div_8 4 div10 5 div12 6 div14 7 CLKMULTENRESYNC CLKMULTENRESYNC 13 1 read-write disable_sync 0 enable_sync 1 CLKMULTVALID CLKMULTVALID 14 1 read-write invalid 0 valid 1 CLKMULTEN0 0xC0 -1 read-write n 0x0 0x0 CLKMULTBWCAL CLKMULTBWCAL 0 2 read-write bw_1lsb 0 bw_2lsb 1 bw_3lsb 2 bw_4lsb 3 CLKMULTDISICO CLKMULTDISICO 2 1 read-write enable 0 disable 1 CLKMULTENBBDET CLKMULTENBBDET 3 1 read-write disable 0 enable 1 CLKMULTENBBXLDET CLKMULTENBBXLDET 4 1 read-write disable 0 enable 1 CLKMULTENBBXMDET CLKMULTENBBXMDET 5 1 read-write disable 0 enable 1 CLKMULTENCFDET CLKMULTENCFDET 6 1 read-write disable 0 enable 1 CLKMULTENDITHER CLKMULTENDITHER 7 1 read-write disable 0 enable 1 CLKMULTENDRVADC CLKMULTENDRVADC 8 1 read-write disable 0 enable 1 CLKMULTENDRVDIFF CLKMULTENDRVDIFF 9 1 read-write Single_ended 0 Differential 1 CLKMULTENDRVRX2P4G CLKMULTENDRVRX2P4G 10 1 read-write disable 0 enable 1 CLKMULTENFBDIV CLKMULTENFBDIV 13 1 read-write disable 0 enable 1 CLKMULTENREFDIV CLKMULTENREFDIV 14 1 read-write disable 0 enable 1 CLKMULTENREG1 CLKMULTENREG1 15 1 read-write disable 0 enable 1 CLKMULTENREG2 CLKMULTENREG2 16 1 read-write disable 0 enable 1 CLKMULTENROTDET CLKMULTENROTDET 17 1 read-write disable 0 enable 1 CLKMULTFREQCAL CLKMULTFREQCAL 18 2 read-write pedes_14uA 0 pedes_22uA 1 pedes_30uA 2 pedes_38uA 3 CLKMULTREG1ADJV CLKMULTREG1ADJV 20 2 read-write v1p28 0 v1p32 1 v1p33 2 v1p38 3 CLKMULTREG2ADJI CLKMULTREG2ADJI 22 2 read-write I_200uA 0 I_480uA 1 I_760uA 2 I_1040uA 3 CLKMULTREG2ADJV CLKMULTREG2ADJV 24 2 read-write v1p03 0 v1p09 1 v1p10 2 v1p16 3 CLKMULTEN1 0xC4 -1 read-write n 0x0 0x0 CLKMULTINNIBBLE CLKMULTINNIBBLE 0 4 read-write CLKMULTLDCNIB CLKMULTLDCNIB 4 1 read-write disable 0 enable 1 CLKMULTLDFNIB CLKMULTLDFNIB 5 1 read-write disable 0 enable 1 CLKMULTLDMNIB CLKMULTLDMNIB 6 1 read-write disable 0 enable 1 CLKMULTRDNIBBLE CLKMULTRDNIBBLE 7 2 read-write quarter_nibble 0 fine_nibble 1 moderate_nibble 2 coarse_nibble 3 CLKMULTSTATUS 0xCC read-only n 0x0 0x0 CLKMULTACKVALID CLKMULTACKVALID 4 1 read-only invalid 0 valid 1 CLKMULTOUTNIBBLE CLKMULTOUTNIBBLE 0 4 read-only CMD No Description 0x10 write-only n 0x0 0x0 CLEARRXOVERFLOW Clear RX Overflow 6 1 write-only CLEARTXEN Clear TX Enable 3 1 write-only FORCETX Force TX Command 1 1 write-only LNAENCLEAR LNAEN Clear 15 1 write-only LNAENSET LNAEN Set 14 1 write-only PAENCLEAR PAEN Clear 13 1 write-only PAENSET PAEN Set 12 1 write-only RXCAL Start an RX Calibration 7 1 write-only RXDIS RX Disable 8 1 write-only TXAFTERFRAME TX After Frame 4 1 write-only TXDIS TX Disable 5 1 write-only TXEN Transmitter Enable 0 1 write-only TXONCCA Transmit On CCA 2 1 write-only CTRL No Description 0x14 read-write n 0x0 0x0 ACTIVEPOL ACTIVE signal polarity 7 1 read-write X0 Active low 0 X1 Active high 1 FORCEDISABLE Force Radio Disable 0 1 read-write LNAENPOL LNAEN signal polarity 9 1 read-write X0 Active low 0 X1 Active high 1 PAENPOL PAEN signal polarity 8 1 read-write X0 Active low 0 X1 Active high 1 PRSCLR PRS RXEN Clear 5 1 read-write RXSEARCH The PRS RXEN signal is cleared when the RSM state enters RXSEARCH 0 PRSCH The Selected PRS channel in PRSCLRSEL is used as a disable pulse 1 PRSFORCETX PRS Force RX 16 1 read-write X0 PRS will not force TX 0 X1 The channel selected by PRSFORCETXSEL will generate a force TX pulse 1 PRSMODE PRS RXEN Mode 3 1 read-write DIRECT The PRS signal is used directly 0 PULSE The PRS signal is used as an RX enable pulse 1 PRSRXDIS PRS RX Disable 10 1 read-write X0 PRS will not disable RX 0 X1 The channel selected by PRSRXDISSEL will generate a disable RX pulse 1 PRSTXEN PRS TX Enable 1 1 read-write TXAFTERRX TX After RX 2 1 read-write X0 TX will not be started automatically. 0 X1 A transition to TX is automatically started when a received frame is accepted by the FRC. 1 TXPOSTPONE TX Postpone 6 1 read-write X0 In the TX state transmit data is output. 0 X1 In the TX state an unmodulated carrier is output until this bit is cleared. 1 DIGCLKRETIMECTRL No Description 0x15C read-write n 0x0 0x0 DIGCLKRETIMEDISRETIME DIGCLKRETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 DIGCLKRETIMEENRETIME DIGCLKRETIMEENRETIME 0 1 read-write disable 0 enable 1 DIGCLKRETIMELIMITH DIGCLKRETIMELIMITH 4 3 read-write DIGCLKRETIMELIMITL DIGCLKRETIMELIMITL 8 3 read-write DIGCLKRETIMERESETN DIGCLKRETIMERESETN 2 1 read-write operate 0 reset 1 DIGCLKRETIMESTATUS No Description 0x160 read-only n 0x0 0x0 DIGCLKRETIMECLKSEL DIGCLKRETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 DIGCLKRETIMERESETNLO DIGCLKRETIMERESETNLO 1 1 read-only lo 0 hi 1 EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FORCESTATE No Description 0x18 read-write n 0x0 0x0 FORCESTATE Force RAC state transition 0 4 read-write IEN No Description 0x20 read-write n 0x0 0x0 BUSERROR Bus Error Interrupt Enable 2 1 read-write SEQ Sequencer Flags Interrupt Enable 16 8 read-write STATECHANGE Radio State Change Interrupt Enable 0 1 read-write STIMCMPEV STIMER Compare Event Interrupt Enable 1 1 read-write IF No Description 0x1C read-write n 0x0 0x0 BUSERROR Bus Error 2 1 read-write SEQ Sequencer Interrupt Flags 16 8 read-write STATECHANGE Radio State Change 0 1 read-write STIMCMPEV STIMER Compare Event 1 1 read-write IFADCCAL 0xD8 -1 read-write n 0x0 0x0 IFADCENRCCAL IFADCENRCCAL 0 1 read-write rccal_disable 0 rccal_enable 1 IFADCTUNERC IFADCTUNERC 8 5 read-write IFADCTUNERCCALMODE IFADCTUNERCCALMODE 1 1 read-write SYmode 0 ADCmode 1 IFADCSTATUS 0xDC read-only n 0x0 0x0 IFADCRCCALOUT IFADCRCCALOUT 0 1 read-only lo 0 hi 1 IFADCTRIM 0xD4 -1 read-write n 0x0 0x0 IFADCCLKSEL IFADCCLKSEL 0 1 read-write clk_2p4g 0 clk_subg 1 IFADCENHALFMODE IFADCENHALFMODE 1 1 read-write full_speed_mode 0 half_speed_mode 1 IFADCLDOSERIESAMPLVL IFADCLDOSERIESAMPLVL 2 3 read-write v1p20 0 v1p24 1 v1p28 2 v1p32 3 v1p35 4 v1p39 5 v1p42 6 v1p46 7 IFADCLDOSHUNTAMPLVL IFADCLDOSHUNTAMPLVL 5 3 read-write v1p20 0 v1p24 1 v1p28 2 v1p32 3 v1p35 4 v1p39 5 v1p42 6 v1p46 7 IFADCLDOSHUNTCURLP IFADCLDOSHUNTCURLP 8 1 read-write low_power_disabled 0 low_power_enabled 1 IFADCLDOSHUNTCURLVL IFADCLDOSHUNTCURLVL 9 2 read-write current_180uA 0 current_190uA 1 current_200uA 2 current_210uA 3 IFADCOTAST1CURRENT IFADCOTAST1CURRENT 11 2 read-write negative_20p 0 negative_11p 1 nominal 2 positive_15p 3 IFADCOTAST2CURRENT IFADCOTAST2CURRENT 13 2 read-write negative_20p 0 negative_11p 1 nominal 2 positive_15p 3 IFADCREFBUFAMPLVL IFADCREFBUFAMPLVL 15 3 read-write v0p88 0 v0p91 1 v0p94 2 v0p97 3 v1p00 4 v1p03 5 v1p06 6 v1p09 7 IFADCREFBUFCURLVL IFADCREFBUFCURLVL 18 2 read-write current_65uA 0 current_75uA 1 current_85uA 2 current_95uA 3 IFADCSIDETONEAMP IFADCSIDETONEAMP 20 2 read-write diff_pk_10mV 0 diff_pk_20mV 1 diff_pk_50mV 2 diff_pk_100mV 3 IFADCSIDETONEFREQ IFADCSIDETONEFREQ 22 3 read-write na0 0 div_128 1 div_64 2 div_32 3 div_16 4 div_8 5 div_4 6 na7 7 IFADCTUNEZERO IFADCTUNEZERO 25 1 read-write nominal_zero 0 half_freq_zero 1 IFADCVCMLVL IFADCVCMLVL 26 2 read-write ratio_0p48 0 ratio_0p49 1 ratio_0p5 2 ratio_0p52 3 IFPGACTRL No Description 0xA0 read-write n 0x0 0x0 DCCALDCGEAR DC COMP GEAR Value for DCCAL 25 3 read-write DCCALDEC0 DEC0 Value for DCCAL 22 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO. 4 DCCALON Enable/Disable DCCAL in DEMOD 19 1 read-write DISABLE DC ESTI DISABLED 0 ENABLE DC ESTI ENABLED 1 DCESTIEN DCESTIEN Override for RAC 21 1 read-write DISABLE DCESTI Disabled in MODEM 0 ENABLE DCESTI Enabled in MODEM 1 DCRSTEN DC Compensation Filter Reset Enable 20 1 read-write DISABLE DC Comp out of Reset 0 ENABLE DC Comp in Reset 1 IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LNAMIXCAL 0xF0 -1 read-write n 0x0 0x0 LNAMIXCALEN LNAMIXCALEN 0 1 read-write cal_disable 0 cal_enable 1 LNAMIXCALVMODE LNAMIXCALVMODE 1 1 read-write current_mode 0 voltage_mode 1 LNAMIXENIRCAL1 LNAMIXENIRCAL1 2 1 read-write disable 0 enable 1 LNAMIXENIRCAL2 LNAMIXENIRCAL2 3 1 read-write disable 0 enable 1 LNAMIXIRCAL1AMP LNAMIXIRCAL1AMP 4 3 read-write LNAMIXIRCAL2AMP LNAMIXIRCAL2AMP 7 3 read-write LNAMIXEN 0xF4 read-write n 0x0 0x0 LNAMIXENLDO LNAMIXENLDO 0 1 read-write disable 0 enable 1 LNAMIXTRIM0 0xE4 -1 read-write n 0x0 0x0 LNAMIXCURCTRL LNAMIXCURCTRL 0 6 read-write LNAMIXHIGHCUR LNAMIXHIGHCUR 6 2 read-write current_470uA 0 current_530uA 1 unused 2 current_590uA 3 LNAMIXLOWCUR LNAMIXLOWCUR 8 2 read-write current_nom 0 unused 1 current_80percent 2 current_60percent 3 LNAMIXRFPKDBWSEL LNAMIXRFPKDBWSEL 10 2 read-write LNAMIXRFPKDCALCM LNAMIXRFPKDCALCM 12 6 read-write LNAMIXRFPKDCALDM LNAMIXRFPKDCALDM 18 5 read-write LNAMIXTRIMVREG LNAMIXTRIMVREG 23 4 read-write LNAMIXTRIM1 0xE8 -1 read-write n 0x0 0x0 LNAMIXIBIAS1ADJ LNAMIXIBIAS1ADJ 0 4 read-write LNAMIXLNA1CAPSEL LNAMIXLNA1CAPSEL 4 3 read-write LNAMIXMXRBIAS1 LNAMIXMXRBIAS1 7 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCAS1ADJ LNAMIXNCAS1ADJ 9 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCAS1ADJ LNAMIXPCAS1ADJ 11 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUT1ADJ LNAMIXVOUT1ADJ 13 4 read-write LNAMIXTRIM2 No Description 0xEC -1 read-write n 0x0 0x0 LNAMIXIBIAS2ADJ LNAMIXIBIAS2ADJ 0 4 read-write LNAMIXLNA2CAPSEL LNAMIXLNA2CAPSEL 4 3 read-write LNAMIXMXRBIAS2 LNAMIXMXRBIAS2 7 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCAS2ADJ LNAMIXNCAS2ADJ 9 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCAS2ADJ LNAMIXPCAS2ADJ 11 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUT2ADJ LNAMIXVOUT2ADJ 13 4 read-write PACTRL 0x108 read-write n 0x0 0x0 PAEN10DBMVMID PAEN10DBMVMID 0 1 read-write disable 0 enable 1 PAEN20DBMVMID PAEN20DBMVMID 1 1 read-write disable 0 enable 1 PAENCAPATT PAENCAPATT 2 1 read-write disable 0 enable 1 PAENLATCHBYPASS PAENLATCHBYPASS 3 1 read-write disable 0 enable 1 PAENPOWERRAMPINGCLK PAENPOWERRAMPINGCLK 4 1 read-write silence_clk 0 en_clk 1 PAPOWER PAPOWER 16 4 read-write t0stripeon 0 t1stripeon 1 t10stripeon 10 t11stripeon 11 t12stripeon 12 t13stripeon 13 t14stripeon 14 t15stripeon 15 t2stripeon 2 t3stripeon 3 t4stripeon 4 t5stripeon 5 t6stripeon 6 t7stripeon 7 t8stripeon 8 t9stripeon 9 PAPULLDOWNVDDPA PAPULLDOWNVDDPA 5 1 read-write not_pull_down 0 pull_down_vddpa 1 PAREGBYPASSPDRVLDO PAREGBYPASSPDRVLDO 6 1 read-write not_bypass 0 bypass 1 PAREGBYPASSPREREG PAREGBYPASSPREREG 7 1 read-write not_bypass 0 bypass 1 PASELLDOVDDPA PASELLDOVDDPA 8 1 read-write not_selected 0 selected 1 PASELLDOVDDRF PASELLDOVDDRF 9 1 read-write not_selected 0 selected 1 PASELSLICE PASELSLICE 20 4 read-write PASLICERST PASLICERST 10 1 read-write disable 0 enable 1 PAENCTRL No Description 0xA4 read-write n 0x0 0x0 PARAMP PA output level ramping 8 1 read-write PATRIM0 0xFC -1 read-write n 0x0 0x0 PATRIMDRVREGIBCORE0DBM PATRIMDRVREGIBCORE0DBM 0 2 read-write i_4u 0 i_5u 1 i_6u 2 i_7u 3 PATRIMDRVREGIBNDIO0DBM PATRIMDRVREGIBNDIO0DBM 2 4 read-write vreg_1p09 0 vreg_1p13 1 NA_10 10 NA_11 11 NA_12 12 NA_13 13 NA_14 14 NA_15 15 vreg_1p16 2 vreg_1p20 3 vreg_1p23 4 vreg_1p25 5 vreg_1p28 6 vreg_1p31 7 vreg_1p33 8 vreg_1p36 9 PATRIMDRVREGPSR0DBM PATRIMDRVREGPSR0DBM 6 1 read-write disable 0 enable 1 PATRIMDRVSLICE0DBM PATRIMDRVSLICE0DBM 7 2 read-write on_0_slice 0 on_1_slice 1 on_2_slice 2 on_3_slice 3 PATRIMFB0DBM PATRIMFB0DBM 9 4 read-write vo_vi_0p475 0 vo_vi_0p500 1 vo_vi_0p725 10 vo_vi_0p750 11 vo_vi_0p775 12 vo_vi_0p80 13 vo_vi_0p825 14 vo_vi_0p85 15 vo_vi_0p525 2 vo_vi_0p550 3 vo_vi_0p575 4 vo_vi_0p600 5 vo_vi_0p625 6 vo_vi_0p650 7 vo_vi_0p675 8 vo_vi_0p700 9 PATRIMPABIASN0DBM PATRIMPABIASN0DBM 13 4 read-write v_450m 0 v_462p5m 1 v_575m 10 v_587p5m 11 v_600m 12 v_612p5m 13 v_625m 14 v_637p5m 15 v_475m 2 v_487p5m 3 v_500m 4 v_512p5m 5 v_525m 6 v_537p5m 7 v_550m 8 v_562p5m 9 PATRIMPABIASP0DBM PATRIMPABIASP0DBM 17 4 read-write v_450m 0 v_462p5m 1 v_575m 10 v_587p5m 11 v_600m 12 v_612p5m 13 v_625m 14 v_637p5m 15 v_475m 2 v_487p5m 3 v_500m 4 v_512p5m 5 v_525m 6 v_537p5m 7 v_550m 8 v_562p5m 9 PATRIMPASLICE0DBM PATRIMPASLICE0DBM 21 6 read-write on_slice_0 0 on_slice_63 63 PATRIMVREF0DBM PATRIMVREF0DBM 27 3 read-write v_900m 0 v_912p5m 1 v_925m 2 v_937p5m 3 v_950m 4 v_962p5m 5 v_975m 6 v_987p5m 7 PATRIM1 0x100 -1 read-write n 0x0 0x0 PATRIM10DBMDUTYCYN PATRIM10DBMDUTYCYN 0 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 PATRIM10DBMDUTYCYP PATRIM10DBMDUTYCYP 3 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM20DBMPREDRV PATRIM20DBMPREDRV 6 3 read-write trise_137ps 0 trise_127ps 1 trise_117ps 2 trise_110ps 3 trise_75ps 4 trise_73ps 5 trise_71ps 6 trise_70ps 7 PATRIMANTSWBIAS PATRIMANTSWBIAS 9 2 read-write vb_at_vdd 0 vb_at_vdd_mp6v 1 vb_at_vdd_m1p2v 2 vb_at_vdd_m1p8v 3 PATRIMBLEEDAUTOPREREG PATRIMBLEEDAUTOPREREG 11 1 read-write not_automatic 0 automatic 1 PATRIMCAPPAOUTM PATRIMCAPPAOUTM 12 4 read-write PATRIMCAPPAOUTP PATRIMCAPPAOUTP 16 4 read-write PATRIMCMGAIN PATRIMCMGAIN 20 2 read-write PATRIMDLY0 PATRIMDLY0 22 3 read-write tdly_0ps 0 tdly_64ps 1 tdly_65ps 2 tdly_66ps 3 tdly_68ps 4 tdly_70ps 5 tdly_75ps 6 tdly_83ps 7 PATRIMDLY1 PATRIMDLY1 25 3 read-write tdly_0ps 0 tdly_64ps 1 tdly_65ps 2 tdly_66ps 3 tdly_68ps 4 tdly_70ps 5 tdly_75ps 6 tdly_83ps 7 PATRIMFBKATTPDRVLDO PATRIMFBKATTPDRVLDO 28 1 read-write less_bw 0 more_bw 1 PATRIMIBIASMASTER PATRIMIBIASMASTER 29 2 read-write Ibias_is_45u 0 Ibias_is_47p5u 1 Ibias_is_50u 2 Ibias_is_52p5u 3 PATRIM2 0x104 -1 read-write n 0x0 0x0 PATRIMLDOFBHVPDRVLDO PATRIMLDOFBHVPDRVLDO 0 2 read-write vreg_1p22 0 vreg_1p28 1 vreg_1p35 2 vreg_1p44 3 PATRIMLDOFBHVPREREG PATRIMLDOFBHVPREREG 2 3 read-write vreg_1p678 0 vreg_1p735 1 vreg_1p801 2 vreg_1p875 3 vreg_3p00 4 vreg_3p14 5 vreg_3p3 6 vreg_3p477 7 PATRIMLDOHVPDRVLDO PATRIMLDOHVPDRVLDO 5 3 read-write vref_0p675 0 vref_0p700 1 vref_0p725 2 vref_0p750 3 vref_0p775 4 vref_0p800 5 vref_0p825 6 vref_0p850 7 PATRIMLDOHVPREREG PATRIMLDOHVPREREG 8 4 read-write vref_0p651 0 vref_0p663 1 vref_0p776 10 vref_0p788 11 vref_0p801 12 vref_0p813 13 vref_0p826 14 vref_0p838 15 vref_0p676 2 vref_0p688 3 vref_0p701 4 vref_0p713 5 vref_0p726 6 vref_0p738 7 vref_0p751 8 vref_0p763 9 PATRIMLDOPSRPDRVLDO PATRIMLDOPSRPDRVLDO 12 1 read-write low_psr 0 high_psr 1 PATRIMLDOPSRPREREG PATRIMLDOPSRPREREG 13 1 read-write low_psr 0 high_psr 1 PATRIMLDOSLICESPDRVLDO PATRIMLDOSLICESPDRVLDO 14 2 read-write iload_7p5mA 0 iload_15mA 1 iload_22p5mA 2 iload_30mA 3 PATRIMLDOSLICESPREREG PATRIMLDOSLICESPREREG 16 2 read-write spare1 0 spare2 1 spare3 2 spare4 3 PATRIMNBIAS PATRIMNBIAS 19 4 read-write vnbias_dn104mv 0 vnbias_dn91mv 1 vnbias_up26mv 10 vnbias_up39mv 11 vnbias_up52mv 12 vnbias_up65mv 13 vnbias_up78mv 14 vnbias_up91mv 15 vnbias_dn78mv 2 vnbias_dn65mv 3 vnbias_dn52mv 4 vnbias_dn39mv 5 vnbias_dn26mv 6 vnbias_dn13mv 7 vnbias_default 8 vnbias_up13mv 9 PATRIMNCASC PATRIMNCASC 23 2 read-write ncbias_m50mv 0 ncbias_default 1 ncbias_p50mv 2 ncbias_p100mv 3 PATRIMPADACGLITCH PATRIMPADACGLITCH 18 1 read-write larger_glitch 0 smaller_glitch 1 PATRIMPBIAS PATRIMPBIAS 25 4 read-write vpbias_up104mv 0 vpbias_up91mv 1 vpbias_dn26mv 10 vpbias_dn38mv 11 vpbias_dn52mv 12 vpbias_dn65mv 13 vpbias_dn78mv 14 vpbias_dn91mv 15 vpbias_up78mv 2 vpbias_up65mv 3 vpbias_up52mv 4 vpbias_up39mv 5 vpbias_up26mv 6 vpbias_up13mv 7 vpbias_default 8 vpbias_dn13mv 9 PATRIMPCASC PATRIMPCASC 29 2 read-write pcbias_p50mv 0 pcbias_default 1 pcbias_m50mv 2 pcbias_m100mv 3 PGACAL 0x114 -1 read-write n 0x0 0x0 PGAOFFNCALI PGAOFFNCALI 0 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFNCALQ PGAOFFNCALQ 8 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALI PGAOFFPCALI 16 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALQ PGAOFFPCALQ 24 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGACTRL 0x118 -1 read-write n 0x0 0x0 LNAMIXRFPKDTHRESHSEL LNAMIXRFPKDTHRESHSEL 24 3 read-write PGABWMODE PGABWMODE 0 2 read-write bw_5MHz 0 bw_2p5MHz 1 bw_1p67MHz 2 bw_1p25MHz 3 PGAENBIAS PGAENBIAS 2 1 read-write bias_disable 0 bias_enable 1 PGAENGHZ PGAENGHZ 3 1 read-write ghz_disable 0 ghz_enable 1 PGAENHYST PGAENHYST 4 1 read-write pkd_hyst_disable 0 pkd_hyst_enable 1 PGAENLATCHI PGAENLATCHI 5 1 read-write pkd_latch_i_disable 0 pkd_latch_i_enable 1 PGAENLATCHQ PGAENLATCHQ 6 1 read-write pkd_latch_q_disable 0 pkd_latch_q_enable 1 PGAENLDOLOAD PGAENLDOLOAD 7 1 read-write disable_ldo_load 0 enable_ldo_load 1 PGAENOFFD PGAENOFFD 8 1 read-write pkd_offd_disable 0 pkd_offd_enable 1 PGAENPGAI PGAENPGAI 9 1 read-write pgai_disable 0 pgai_enable 1 PGAENPGAQ PGAENPGAQ 10 1 read-write pgaq_disable 0 pgaq_enable 1 PGAENPKD PGAENPKD 11 1 read-write pkd_disable 0 pkd_enable 1 PGAENRCMOUT PGAENRCMOUT 12 1 read-write rcm_out_disable 0 rcm_out_enable 1 PGAPOWERMODE PGAPOWERMODE 14 2 read-write pm_typ 0 pm_0p8 1 pm_1p2 2 pm_0p5 3 PGATHRPKDHISEL PGATHRPKDHISEL 20 4 read-write vref50mv 0 vref75mv 1 vref300mv 10 vref100mv 2 vref125mv 3 verf150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 PGATHRPKDLOSEL PGATHRPKDLOSEL 16 4 read-write vref50mv 0 vref75mv 1 vref300mv 10 vref100mv 2 vref125mv 3 vref150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 PGATRIM 0x110 -1 read-write n 0x0 0x0 PGACTUNE PGACTUNE 0 4 read-write cfb_0p7 0 cfb_1p32 15 cfb_nominal 7 PGADISANTILOCK PGADISANTILOCK 4 1 read-write antilock_enable 0 antilock_disable 1 PGAVCMOUTTRIM PGAVCMOUTTRIM 5 3 read-write vcm_out_0p4 0 vcm_out_0p45 1 vcm_out_0p5 2 vcm_out_0p55 3 vcm_out_0p6 4 vcm_out_0p65 5 vcm_out_0p7 6 vcm_out_0p75 7 PGAVLDOTRIM PGAVLDOTRIM 8 3 read-write vdda_1p15 0 vdda_1p2 1 vdda_1p25 2 vdda_1p3 3 vdda_1p35 4 vdda_1p4 5 vdda_1p5 6 vdda_1p55 7 PRECTRL 0xF8 -1 read-write n 0x0 0x0 PREBYPFORCE PREBYPFORCE 0 1 read-write not_forced 0 forced 1 PREREGTRIM PREREGTRIM 1 3 read-write v1p61 0 v1p68 1 v1p74 2 v1p80 3 v1p86 4 v1p91 5 v1p96 6 v2p00 7 PREVREFTRIM PREVREFTRIM 4 2 read-write v0p675 0 v0p688 1 v0p700 2 v0p713 3 PRESC No Description 0x6C -1 read-write n 0x0 0x0 STIMER STIMER Prescaler 0 7 read-write R0 No Description 0x34 read-write n 0x0 0x0 R0 Sequencer Register 0 0 32 read-write R1 No Description 0x38 read-write n 0x0 0x0 R1 Sequencer Register 1 0 32 read-write R2 No Description 0x3C read-write n 0x0 0x0 R2 Sequencer Register 2 0 32 read-write R3 No Description 0x40 read-write n 0x0 0x0 R3 Sequencer Register 3 0 32 read-write R4 No Description 0x44 read-write n 0x0 0x0 R4 Sequencer Register 4 0 32 read-write R5 No Description 0x48 read-write n 0x0 0x0 R5 Sequencer Register 5 0 32 read-write R6 No Description 0x4C read-write n 0x0 0x0 R6 Sequencer Register 6 0 32 read-write R7 No Description 0x50 read-write n 0x0 0x0 R7 Sequencer Register 7 0 32 read-write RADIOEN 0x124 read-write n 0x0 0x0 PREEN PREEN 0 1 read-write powered_off 0 powered_on 1 PRESTB100UDIS PRESTB100UDIS 1 1 read-write i100ua_enabled 0 i100ua_disabled 1 RFBIASEN RFBIASEN 2 1 read-write disable_dualbis_vtr 0 enable_dualbis_vtr 1 RFBIASCAL 0x11C -1 read-write n 0x0 0x0 RFBIASCALBIAS RFBIASCALBIAS 0 6 read-write RFBIASCALTC RFBIASCALTC 8 6 read-write RFBIASCALVREF RFBIASCALVREF 16 6 read-write RFBIASCALVREFSTARTUP RFBIASCALVREFSTARTUP 24 6 read-write RFBIASCTRL 0x120 -1 read-write n 0x0 0x0 RFBIASDISABLEBOOTSTRAP RFBIASDISABLEBOOTSTRAP 0 1 read-write enable_startup 0 disable_startup 1 RFBIASLDOHIGHCURRENT RFBIASLDOHIGHCURRENT 1 1 read-write low_current 0 high_current 1 RFBIASLDOVREFTRIM RFBIASLDOVREFTRIM 16 4 read-write vref_v0p800 0 vref_v0p813 1 vref_v0p925 10 vref_v0p938 11 vref_v0p950 12 vref_v0p963 13 vref_v0p975 14 vref_v0p988 15 vref_v0p825 2 vref_v0p837 3 vref_v0p850 4 vref_v0p863 5 vref_v0p875 6 vref_v0p887 7 vref_v0p900 8 vref_v0p913 9 RFBIASNONFLASHMODE RFBIASNONFLASHMODE 2 1 read-write flash_process 0 non_flash_process 1 RFBIASSTARTUPCORE RFBIASSTARTUPCORE 3 1 read-write default 0 force_start 1 RFBIASSTARTUPSUPPLY RFBIASSTARTUPSUPPLY 4 1 read-write default 0 forc_start 1 RFPATHEN1 No Description 0x128 -1 read-write n 0x0 0x0 LNAMIXEN0DBMPA1 LNAMIXEN0DBMPA1 0 1 read-write disable 0 enable 1 LNAMIXEN1 LNAMIXEN1 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN1 LNAMIXRFATTDCEN1 2 1 read-write disable_dc 0 enable_dc 1 LNAMIXRFPKDENRF1 LNAMIXRFPKDENRF1 3 1 read-write disable 0 enable_path1 1 LNAMIXTRSW1 LNAMIXTRSW1 4 1 read-write disabled 0 enabled 1 PAENANT1 PAENANT1 5 1 read-write disable 0 enable 1 PAENPA10DBM PAENPA10DBM 6 1 read-write disable 0 enable 1 PAENPAPREDRV10DBM PAENPAPREDRV10DBM 7 1 read-write disable 0 enable 1 RFPATHEN2 No Description 0x12C -1 read-write n 0x0 0x0 LNAMIXEN0DBMPA2 LNAMIXEN0DBMPA2 0 1 read-write disable 0 enable 1 LNAMIXEN2 LNAMIXEN2 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN2 LNAMIXRFATTDCEN2 2 1 read-write disable 0 enable 1 LNAMIXRFPKDENRF2 LNAMIXRFPKDENRF2 3 1 read-write disable 0 enable_path2 1 LNAMIXTRSW2 LNAMIXTRSW2 4 1 read-write disable 0 enable 1 PAENANT2 PAENANT2 5 1 read-write disable 0 enable 1 PAENPA20DBM PAENPA20DBM 6 1 read-write disable 0 enable 1 PAENPAPREDRV20DBM PAENPAPREDRV20DBM 7 1 read-write disable 0 enable 1 RX 0x130 -1 read-write n 0x0 0x0 IFADCCAPRESET IFADCCAPRESET 0 1 read-write cap_reset_disable 0 cap_reset_enable 1 IFADCENLDOSERIES IFADCENLDOSERIES 1 1 read-write series_ldo_disable 0 series_ldo_enable 1 IFADCENLDOSHUNT IFADCENLDOSHUNT 2 1 read-write shunt_ldo_disable 0 shunt_ldo_enable 1 LNAMIXENRFPKD LNAMIXENRFPKD 3 1 read-write disable 0 enable 1 LNAMIXLDOLOWCUR LNAMIXLDOLOWCUR 4 1 read-write regular_mode 0 low_current_mode 1 LNAMIXREGLOADEN LNAMIXREGLOADEN 5 1 read-write disable_resistor 0 enable_resistor 1 PGAENLDO PGAENLDO 6 1 read-write disable_ldo 0 enable_ldo 1 SYCHPBIASTRIMBUF SYCHPBIASTRIMBUF 7 1 read-write i_tail_10u 0 i_tail_20u 1 SYCHPQNC3EN SYCHPQNC3EN 8 1 read-write qnc_2 0 qnc_3 1 SYMMDMODE SYMMDMODE 9 3 read-write rx_w_swctrl 0 rx_wo_swctrl 1 qnc_dsm2 2 qnc_dsm3 3 rxlp_wo_swctrl 4 notuse_5 5 notuse_6 6 notuse_7 7 SYPFDCHPLPEN SYPFDCHPLPEN 12 1 read-write disable 0 enable 1 SYPFDFPWEN SYPFDFPWEN 13 1 read-write disable 0 enable 1 RXENSRCEN No Description 0x8 read-write n 0x0 0x0 CHANNELBUSYEN Channel Busy Enable 8 1 read-write DEMODRXREQEN DEMOD RX Request Enable 12 1 read-write FRAMEDETEN Frame Detected Enable 11 1 read-write PREDETEN Preamble Detected Enable 10 1 read-write PRSRXEN PRS RX Enable 13 1 read-write SWRXEN SW RX Enable 0 8 read-write TIMDETEN Timing Detected Enable 9 1 read-write SCRATCH0 No Description 0x3E0 read-write n 0x0 0x0 SCRATCH0 SCRATCH0 0 32 read-write SCRATCH1 No Description 0x3E4 read-write n 0x0 0x0 SCRATCH1 SCRATCH1 0 32 read-write SCRATCH2 No Description 0x3E8 read-write n 0x0 0x0 SCRATCH2 SCRATCH2 0 32 read-write SCRATCH3 No Description 0x3EC read-write n 0x0 0x0 SCRATCH3 SCRATCH3 0 32 read-write SCRATCH4 No Description 0x3F0 read-write n 0x0 0x0 SCRATCH4 SCRATCH4 0 32 read-write SCRATCH5 No Description 0x3F4 read-write n 0x0 0x0 SCRATCH5 SCRATCH5 0 32 read-write SCRATCH6 No Description 0x3F8 read-write n 0x0 0x0 SCRATCH6 SCRATCH6 0 32 read-write SCRATCH7 No Description 0x3FC read-write n 0x0 0x0 SCRATCH7 SCRATCH7 0 32 read-write SEQCMD No Description 0x2C write-only n 0x0 0x0 ABORT Sequencer Execution Abort 5 1 write-only ABORTENCLEAR Clear Sequencer Abort Enable 7 1 write-only ABORTENSET Set Sequencer Abort Enable 6 1 write-only BKPTDIS Breakpoint Disable 4 1 write-only BKPTEN Breakpoint Enable 3 1 write-only HALT Sequencer Halt 0 1 write-only RESUME Sequencer Resume 2 1 write-only STEP Sequencer Step 1 1 write-only SEQCTRL No Description 0x68 read-write n 0x0 0x0 COMPACT STIMER Compare Action 0 1 read-write WRAP STIMER wraps when reaching STIMERCOMP 0 CONTINUE STIMER continues when reaching STIMERCOMP 1 COMPINVALMODE STIMER Comp Invalid Mode 1 2 read-write NEVER STIMERCOMP is always valid 0 STATECHANGE STIMERCOMP is invalidated when the RSM changes state 1 COMPEVENT STIMERCOMP is invalidated when an STIMER compare event occurs 2 STATECOMP STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs 3 CPUHALTREQEN CPU Halt Request Enable 11 1 read-write X0 Main CPU is not halted when the Sequencer is halted. 0 X1 Main CPU is halted when the Sequencer is halted. 1 SEQHALTUPONCPUHALTEN Sequencer Halt Upon CPU Halt Enable 12 1 read-write X0 Sequencer is not halted when the main CPU is halted. 0 X1 Sequencer is halted when the main CPU is halted. 1 STIMERDEBUGRUN STIMER Debug Run 10 1 read-write X0 STIMER is not running when the Sequencer is halted. 0 X1 STIMER is running when the Sequencer is halted. 1 SEQSTATUS No Description 0x28 -1 read-only n 0x0 0x0 ABORTEN Sequencer Program Execution Abort Enable 10 1 read-only X0 Sequencer Program Execution can not be aborted. 0 X1 Sequencer Program Execution can be aborted. 1 BKPT Breakpoint Enabled 1 1 read-only CARRY Carry Flag 8 1 read-only DONE Sequencer Done Signal 4 1 read-only NEG Negative Flag 5 1 read-only POS Positive Flag 6 1 read-only STOPPED Sequencer Stopped 0 1 read-only WAITING Sequencer Waiting 2 1 read-only WAITMODE Sequencer Waiting Mode 3 1 read-only ANY Sequencer is waiting for any of the events indicated SEQ_WAITMASK. 0 ALL Sequencer is waiting for all the events indicated SEQ_WAITMASK. 1 ZERO Zero Flag 7 1 read-only SR0 No Description 0x70 read-write n 0x0 0x0 SR0 Sequencer Storage Register 0 0 32 read-write SR1 No Description 0x74 read-write n 0x0 0x0 SR1 Sequencer Storage Register 1 0 32 read-write SR2 No Description 0x78 read-write n 0x0 0x0 SR2 Sequencer Storage Register 2 0 32 read-write SR3 No Description 0x7C read-write n 0x0 0x0 SR3 Sequencer Storage Register 3 0 32 read-write STATUS No Description 0xC read-only n 0x0 0x0 FORCESTATEACTIVE FSM state force active 19 1 read-only X0 No special state transition is currently in progress 0 X1 A forced state transition is currently in progress 1 RXENS RXEN Status 31 1 read-only X0 RXEN is not set. 0 X1 RXEN is set. 1 RXMASK Receive Enable Mask 0 16 read-only STATE Radio State 24 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXAFTERFRAMEACTIVE TX After Frame Active 21 1 read-only X0 The currently ongoing TX was not initiated by a TXAFTERFRAME command. 0 X1 The currently ongoing TX was initiated by a TXAFTERFRAME command. 1 TXAFTERFRAMEPEND TX After Frame Pending 20 1 read-only X0 A transmit after frame operation is currently not pending. 0 X1 A transmit after frame operation is currently pending. 1 TXENS TXEN Status 30 1 read-only X0 TXEN is not set. 0 X1 TXEN is set. 1 STATUS2 No Description 0x9C read-only n 0x0 0x0 PREVSTATE1 Previous Radio State 0 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 PREVSTATE2 Previous Radio State 2 4 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 PREVSTATE3 Previous Radio State 3 8 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 STIMER No Description 0x5C read-only n 0x0 0x0 STIMER STIMER Register 0 16 read-only STIMERCOMP No Description 0x60 read-write n 0x0 0x0 STIMERCOMP STIMER Compare Register 0 16 read-write SYCAL 0x144 -1 read-write n 0x0 0x0 SYHILOADCHPREG SYHILOADCHPREG 24 2 read-write i_350uA 0 i_500uA 1 i_550uA 2 i_700uA 3 SYVCOMODEPKD SYVCOMODEPKD 8 1 read-write t_openloop_0 0 t_pkdetect_1 1 SYVCOMORECURRENT SYVCOMORECURRENT 9 1 read-write more_current_0 0 more_current_1 1 SYVCOSLOWNOISEFILTER SYVCOSLOWNOISEFILTER 10 1 read-write slow_noise_filter_0 0 slow_noise_filter_1 1 SYVCOVCAPVCM SYVCOVCAPVCM 15 2 read-write SYEN 0x148 read-write n 0x0 0x0 SYCHPEN SYCHPEN 0 1 read-write disable 0 enable 1 SYCHPLPEN SYCHPLPEN 1 1 read-write disable 0 enable 1 SYENCHPREG SYENCHPREG 2 1 read-write Disable 0 Enable 1 SYENCHPREPLICA SYENCHPREPLICA 3 1 read-write disable 0 enable 1 SYENMMDREG SYENMMDREG 4 1 read-write Disable 0 Enable 1 SYENMMDREPLICA1 SYENMMDREPLICA1 5 1 read-write disable 0 enable 1 SYENMMDREPLICA2 SYENMMDREPLICA2 6 1 read-write Disable 0 Enable 1 SYENVCOBIAS SYENVCOBIAS 7 1 read-write en_vco_bias_0 0 en_vco_bias_1 1 SYENVCOPFET SYENVCOPFET 8 1 read-write en_vco_pfet_0 0 en_vco_pfet_1 1 SYENVCOREG SYENVCOREG 9 1 read-write en_vco_reg_0 0 en_vco_reg_1 1 SYLODIVEN SYLODIVEN 10 1 read-write disable 0 enable 1 SYLODIVLDOBIASEN SYLODIVLDOBIASEN 11 1 read-write disable 0 enable 1 SYLODIVLDOEN SYLODIVLDOEN 12 1 read-write disable 0 enable 1 SYSTARTCHPREG SYSTARTCHPREG 13 1 read-write no_fast_startup 0 fast_startup 1 SYSTARTMMDREG SYSTARTMMDREG 14 1 read-write no_fast_startup 0 fast_startup 1 SYLOEN 0x14C read-write n 0x0 0x0 SYLODIVRLO12G4EN SYLODIVRLO12G4EN 1 1 read-write disable 0 enable 1 SYLODIVRLO22G4EN SYLODIVRLO22G4EN 3 1 read-write disable 0 enable 1 SYLODIVRLOADCCLK2G4EN SYLODIVRLOADCCLK2G4EN 0 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4AUXEN 5 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4EN SYLODIVTLO0DBM2G4EN 6 1 read-write disable 0 enable 1 SYLODIVTLO20DBM2G4AUXEN SYLODIVTLO20DBM2G4AUXEN 9 1 read-write disable 0 enable 1 SYLODIVTLO20DBM2G4EN SYLODIVTLO20DBM2G4EN 10 1 read-write disable 0 enable 1 SYMMDCTRL 0x158 read-write n 0x0 0x0 SYMMDDIVRSDIG SYMMDDIVRSDIG 1 2 read-write Divideby1 0 Divideby2 1 Divideby4 2 Divideby8 3 SYMMDENRSDIG SYMMDENRSDIG 0 1 read-write disable 0 enable 1 SYNTHCTRL No Description 0x94 read-write n 0x0 0x0 MMDPOWERBALANCEDISABLE SYMMDPOWERBALANCEENB 10 1 read-write EnablePowerbleed 0 DisablePowerBleed 1 SYNTHENCTRL No Description 0x84 read-write n 0x0 0x0 LPFBWSEL LPF bandwidth register selection 20 1 read-write LPFBWRX Select LPFBWRX 0 LPFBWTX Select LPFBWTX 1 VCBUFEN SYLPFVCBUFEN 7 1 read-write Disabled 0 Enabled 1 VCOSTARTUP SYVCOFASTSTARTUP 1 1 read-write fast_start_up_0 0 fast_start_up_1 1 SYNTHREGCTRL No Description 0x88 -1 read-write n 0x0 0x0 CHPLDOVREFTRIM SYTRIMCHPREGVREF 24 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 MMDLDOVREFTRIM SYTRIMMMDREGVREF 10 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 SYTRIM0 0x13C -1 read-write n 0x0 0x0 SYCHPBIAS SYCHPBIAS 0 3 read-write bias_0 0 bias_1 1 bias_2 3 bias_3 7 SYCHPCURR SYCHPCURR 3 3 read-write curr_1p5uA 0 curr_2p0uA 1 curr_2p5uA 2 curr_3p0uA 3 curr_3p5uA 4 curr_4p0uA 5 curr_4p5uA 6 curr_5p0uA 7 SYCHPLEVNSRC SYCHPLEVNSRC 6 3 read-write SYCHPLEVPSRC SYCHPLEVPSRC 9 3 read-write vsrcp_n105m 0 vsrcp_n90m 1 vsrcp_n75m 2 vsrcp_n60m 3 vsrcp_n45m 4 vsrcp_n30m 5 vsrcp_n15m 6 vsrcp_n0m 7 SYCHPREPLICACURRADJ SYCHPREPLICACURRADJ 14 3 read-write load_8ua 0 load_16ua 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYCHPSRCEN SYCHPSRCEN 13 1 read-write disable 0 enable 1 SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBIAS 17 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMCHPREGAMPBW SYTRIMCHPREGAMPBW 20 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYTRIM1 0x140 -1 read-write n 0x0 0x0 SYLODIVLDOTRIMCORE SYLODIVLDOTRIMCORE 0 2 read-write RXLO 0 TXLO 3 SYLODIVLDOTRIMNDIO SYLODIVLDOTRIMNDIO 2 4 read-write vreg_1p08 0 vreg_1p11 1 vreg_1p15 2 vreg_1p18 3 vreg_1p21 4 vreg_1p24 5 vreg_1p27 6 vreg_1p29 7 vreg_1p32 8 vreg_1p34 9 SYMMDREPLICA1CURRADJ SYMMDREPLICA1CURRADJ 6 3 read-write load_8ua 0 load_16u 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYMMDREPLICA2CURRADJ SYMMDREPLICA2CURRADJ 9 3 read-write load_32u 0 load_64u 1 load_96u 2 load_128u 3 load_160u 4 load_192u 5 load_224u 6 load_256u 7 SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBIAS 12 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMMMDREGAMPBW SYTRIMMMDREGAMPBW 15 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 TESTCTRL No Description 0x24 read-write n 0x0 0x0 AUX2RFSENSE Enable auxiliary synthesizer output 2 1 read-write X0 The auxiliary synthesizer is not connected to the RFSENSE input 0 X1 The auxiliary synthesizer is connected to the RFSENSE input 1 DEMODEN Demodulator enable 1 1 read-write LOOPBACK2LNAINPUT Enable RF loopback 3 1 read-write LOOPBACK2LNAOUTPUT Enable RF loopback 4 1 read-write MODEN Modulator enable 0 1 read-write TX 0x134 read-write n 0x0 0x0 ENPAPOWER Override 30 1 read-write ENPASELSLICE Override 31 1 read-write ENPATRIMPASLICE0DBM Override 10 1 read-write ENXOSQBUFFILT Override 29 1 read-write PABLEEDDRVREG0DBM PABLEEDDRVREG0DBM 0 1 read-write disable 0 enable 1 PABLEEDREG0DBM PABLEEDREG0DBM 1 1 read-write disable 0 enable 1 PAEN10DBMM PAEN10DBMM 16 1 read-write disable 0 enable 1 PAEN10DBMP PAEN10DBMP 17 1 read-write disable 0 enable 1 PAEN10DBMPDRV PAEN10DBMPDRV 18 1 read-write disable 0 enable 1 PAEN20DBM PAEN20DBM 20 1 read-write disable 0 enable 1 PAEN20DBMPDRV PAEN20DBMPDRV 21 1 read-write disable 0 enable 1 PAENBIAS0DBM PAENBIAS0DBM 2 1 read-write disable 0 enable 1 PAENBLEEDPDRVLDO PAENBLEEDPDRVLDO 24 1 read-write disable 0 enable 1 PAENBLEEDPREREG PAENBLEEDPREREG 25 1 read-write disable 0 enable 1 PAENDRVREG0DBM PAENDRVREG0DBM 3 1 read-write disable 0 enable 1 PAENDRVREGBIAS0DBM PAENDRVREGBIAS0DBM 4 1 read-write disable 0 enable 1 PAENLDOHVPDRVLDO PAENLDOHVPDRVLDO 26 1 read-write disable 0 enable 1 PAENLDOHVPREREG PAENLDOHVPREREG 27 1 read-write disable 0 enable 1 PAENLO0DBM PAENLO0DBM 5 1 read-write disable 0 enable 1 PAENPAOUT PAENPAOUT 28 1 read-write disable 0 enable 1 PAENREG0DBM PAENREG0DBM 6 1 read-write disable 0 enable 1 PAENTAPCAP0DBM PAENTAPCAP0DBM 7 3 read-write cap_0f 0 cap_0p35pF 1 cap_0p7pF 2 cap_1p05pF 3 cap_1p4pF 4 cap_1p75pF 5 cap_2p1pF 6 cap_2p45pF 7 VCOCTRL No Description 0x8C -1 read-write n 0x0 0x0 VCOAMPLITUDE SYVCOAMPLOPEN 0 4 read-write VCODETAMPLITUDE SYVCOAMPLPKD 4 4 read-write VECTADDR No Description 0x64 read-write n 0x0 0x0 VECTADDR Vector Table Address 0 32 read-write WAITMASK No Description 0x54 read-only n 0x0 0x0 ANTSWITCH Active antenna has switched 8 1 read-only DEMODRXREQCLR Demodulator RX Request Clear 4 1 read-only FRCPAUSED FRC Paused 7 1 read-only FRCRX FRC RXWord 1 1 read-only FRCTX FRC TXWord 2 1 read-only PRSEVENT PRS Event 3 1 read-only RAMPDONE Ramp Done 6 1 read-only STCMP STIMER Compare Event 0 1 read-only SYNTHRDY SYNTH Ready 5 1 read-only WAITSNSH No Description 0x58 read-only n 0x0 0x0 WAITSNSH Wait Event Snapshot 0 10 read-only XORETIMECTRL No Description 0x164 read-write n 0x0 0x0 XORETIMEDISRETIME XORETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 XORETIMEENRETIME XORETIMEENRETIME 0 1 read-write disable 0 enable 1 XORETIMELIMITH XORETIMELIMITH 4 3 read-write XORETIMELIMITL XORETIMELIMITL 8 3 read-write XORETIMERESETN XORETIMERESETN 2 1 read-write operate 0 reset 1 XORETIMESTATUS No Description 0x168 read-only n 0x0 0x0 XORETIMECLKSEL XORETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 XORETIMERESETNLO XORETIMERESETNLO 1 1 read-only lo 0 hi 1 XOSQBUFFILT 0x16C read-write n 0x0 0x0 XOSQBUFFILT XOSQBUFFILT 0 2 read-write bypass 0 filter_1 1 filter_2 2 filter_3 3 RAC_S RAC_S Registers RAC_S 0x0 0x0 0x1000 registers n RAC_RSM 37 RAC_SEQ 38 ANTDIV No Description 0x174 read-write n 0x0 0x0 EN EN 0 8 read-write OFF All controls off 0 PAENANT1 Control pa_en_ant1 1 SYLODIVRLO22G4EN Control sy_lodiv_rlo2_2g4_en 128 PAENANT2 Control pa_en_ant2 16 LNAMIXEN1 Control lnamix_en1 2 ON All controls on 255 LNAMIXEN2 Control lnamix_en2 32 LNAMIXRFPKDENRF1 Control lnamix_rfpkd_en_rf1 4 LNAMIXRFPKDENRF2 Control lnamix_rfpkd_en_rf2 64 SYLODIVRLO12G4EN Control sy_lodiv_rlo1_2g4_en 8 STATUS STATUS 8 2 read-only OFF Both antenna disabled 0 ANT1 Antenna 1 enabled 1 ANT2 Antenna 2 enabled 2 BOTH Both antenna enabled 3 APC No Description 0xA8 -1 read-write n 0x0 0x0 AMPCONTROLLIMITSW software amp_control top limit 24 8 read-write ENAPCSW software control bit for apc 2 1 read-write DISABLE 0 ENABLE 1 AUXADCCTRL0 No Description 0xB4 -1 read-write n 0x0 0x0 CLRCOUNTER Clear counter 12 1 read-write CLRFILTER Clear accumulators 13 1 read-write CYCLES Cycle number to run 0 10 read-write INPUTRESSEL Select input resource 14 4 read-write MUXSEL Select accumulator 10 2 read-write AUXADCCTRL1 0xB8 read-write n 0x0 0x0 AUXADCINPUTRESSEL AUXADCINPUTRESSEL 0 4 read-write RES640kOhm 0 RES320kOhm 1 RES0p6kOhm 10 RES_switch 11 RES160kOhm 2 RES80kOhm 3 RES40kOhm 4 RES20kOhm 5 RES10kOhm 6 RES5kOhm 7 RES2p5kOhm 8 RES1p25kOhm 9 AUXADCINPUTSELECT AUXADCINPUTSELECT 4 4 read-write SEL0 0 SEL1 1 SEL2 2 SEL3 3 SEL4 4 SEL5 5 SEL6 6 SEL7 7 SEL8 8 SEL9 9 AUXADCPMONSELECT AUXADCPMONSELECT 8 4 read-write AUXADCRESET AUXADCRESET 24 1 read-write Reset_Enabled 0 Reset_Disabled 1 AUXADCTSENSESELCURR AUXADCTSENSESELCURR 16 5 read-write AUXADCTSENSESELVBE AUXADCTSENSESELVBE 25 1 read-write VBE1 0 VBE2 1 AUXADCEN 0xB0 read-write n 0x0 0x0 AUXADCENAUXADC AUXADCENAUXADC 0 1 read-write Disabled 0 Enabled 1 AUXADCENINPUTBUFFER AUXADCENINPUTBUFFER 1 1 read-write Disabled 0 Enabled 1 AUXADCENLDO AUXADCENLDO 2 1 read-write Disabled 0 Enabled 1 AUXADCENOUTPUTDRV AUXADCENOUTPUTDRV 3 1 read-write Disabled 0 Enabled 1 AUXADCENPMON AUXADCENPMON 4 1 read-write Disabled 0 Enabled 1 AUXADCENRESONDIAGA AUXADCENRESONDIAGA 5 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSE AUXADCENTSENSE 6 1 read-write Disabled 0 Enabled 1 AUXADCENTSENSECAL AUXADCENTSENSECAL 7 1 read-write Disabled 0 Enabled 1 AUXADCINPUTBUFFERBYPASS AUXADCINPUTBUFFERBYPASS 8 1 read-write Not_Bypassed 0 Bypassed 1 AUXADCOUT No Description 0xBC read-only n 0x0 0x0 AUXADCOUT AUXADC output 0 28 read-only AUXADCTRIM 0xAC -1 read-write n 0x0 0x0 AUXADCCLKINVERT AUXADCCLKINVERT 0 1 read-write Disable_Invert 0 Enable_Invert 1 AUXADCLDOVREFTRIM AUXADCLDOVREFTRIM 1 2 read-write TRIM1p27 0 TRIM1p3 1 TRIM1p35 2 TRIM1p4 3 AUXADCOUTPUTINVERT AUXADCOUTPUTINVERT 3 1 read-write Disabled 0 Enabled 1 AUXADCRCTUNE AUXADCRCTUNE 4 5 read-write AUXADCTRIMADCINPUTRES AUXADCTRIMADCINPUTRES 9 2 read-write RES200k 0 RES250k 1 RES300k 2 RES350k 3 AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURRINPUTBUF 11 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA1 13 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURROPA2 AUXADCTRIMCURROPA2 15 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRREFBUF 17 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRTSENSE AUXADCTRIMCURRTSENSE 19 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMCURRVCMBUF AUXADCTRIMCURRVCMBUF 21 2 read-write Typ_minus_40pct 0 Typ_minus_20pct 1 Typ 2 Typ_plus_20pct 3 AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMLDOHIGHCURRENT 23 1 read-write LowCurrentMode 0 HighCurrentMode 1 AUXADCTRIMREFP AUXADCTRIMREFP 24 2 read-write REF1p05 0 REF1p16 1 REF1p2 2 REF1p25 3 AUXADCTRIMVREFVCM AUXADCTRIMVREFVCM 26 2 read-write Trim0p6 0 Trim0p65 1 Trim0p7 2 Trim0p75 3 AUXADCTSENSETRIMVBE2 AUXADCTSENSETRIMVBE2 28 1 read-write VBE_16uA 0 VBE_32uA 1 BREAKPOINT No Description 0x30 read-write n 0x0 0x0 BKPADDR Sequencer Breakpoint Address 0 32 read-write CLKMULTCTRL 0xC8 -1 read-write n 0x0 0x0 CLKMULTDIVN CLKMULTDIVN 0 7 read-write CLKMULTDIVR CLKMULTDIVR 7 3 read-write CLKMULTDIVX CLKMULTDIVX 10 3 read-write div_1 0 div_2 1 div_4 2 div_6 3 div_8 4 div10 5 div12 6 div14 7 CLKMULTENRESYNC CLKMULTENRESYNC 13 1 read-write disable_sync 0 enable_sync 1 CLKMULTVALID CLKMULTVALID 14 1 read-write invalid 0 valid 1 CLKMULTEN0 0xC0 -1 read-write n 0x0 0x0 CLKMULTBWCAL CLKMULTBWCAL 0 2 read-write bw_1lsb 0 bw_2lsb 1 bw_3lsb 2 bw_4lsb 3 CLKMULTDISICO CLKMULTDISICO 2 1 read-write enable 0 disable 1 CLKMULTENBBDET CLKMULTENBBDET 3 1 read-write disable 0 enable 1 CLKMULTENBBXLDET CLKMULTENBBXLDET 4 1 read-write disable 0 enable 1 CLKMULTENBBXMDET CLKMULTENBBXMDET 5 1 read-write disable 0 enable 1 CLKMULTENCFDET CLKMULTENCFDET 6 1 read-write disable 0 enable 1 CLKMULTENDITHER CLKMULTENDITHER 7 1 read-write disable 0 enable 1 CLKMULTENDRVADC CLKMULTENDRVADC 8 1 read-write disable 0 enable 1 CLKMULTENDRVDIFF CLKMULTENDRVDIFF 9 1 read-write Single_ended 0 Differential 1 CLKMULTENDRVRX2P4G CLKMULTENDRVRX2P4G 10 1 read-write disable 0 enable 1 CLKMULTENFBDIV CLKMULTENFBDIV 13 1 read-write disable 0 enable 1 CLKMULTENREFDIV CLKMULTENREFDIV 14 1 read-write disable 0 enable 1 CLKMULTENREG1 CLKMULTENREG1 15 1 read-write disable 0 enable 1 CLKMULTENREG2 CLKMULTENREG2 16 1 read-write disable 0 enable 1 CLKMULTENROTDET CLKMULTENROTDET 17 1 read-write disable 0 enable 1 CLKMULTFREQCAL CLKMULTFREQCAL 18 2 read-write pedes_14uA 0 pedes_22uA 1 pedes_30uA 2 pedes_38uA 3 CLKMULTREG1ADJV CLKMULTREG1ADJV 20 2 read-write v1p28 0 v1p32 1 v1p33 2 v1p38 3 CLKMULTREG2ADJI CLKMULTREG2ADJI 22 2 read-write I_200uA 0 I_480uA 1 I_760uA 2 I_1040uA 3 CLKMULTREG2ADJV CLKMULTREG2ADJV 24 2 read-write v1p03 0 v1p09 1 v1p10 2 v1p16 3 CLKMULTEN1 0xC4 -1 read-write n 0x0 0x0 CLKMULTINNIBBLE CLKMULTINNIBBLE 0 4 read-write CLKMULTLDCNIB CLKMULTLDCNIB 4 1 read-write disable 0 enable 1 CLKMULTLDFNIB CLKMULTLDFNIB 5 1 read-write disable 0 enable 1 CLKMULTLDMNIB CLKMULTLDMNIB 6 1 read-write disable 0 enable 1 CLKMULTRDNIBBLE CLKMULTRDNIBBLE 7 2 read-write quarter_nibble 0 fine_nibble 1 moderate_nibble 2 coarse_nibble 3 CLKMULTSTATUS 0xCC read-only n 0x0 0x0 CLKMULTACKVALID CLKMULTACKVALID 4 1 read-only invalid 0 valid 1 CLKMULTOUTNIBBLE CLKMULTOUTNIBBLE 0 4 read-only CMD No Description 0x10 write-only n 0x0 0x0 CLEARRXOVERFLOW Clear RX Overflow 6 1 write-only CLEARTXEN Clear TX Enable 3 1 write-only FORCETX Force TX Command 1 1 write-only LNAENCLEAR LNAEN Clear 15 1 write-only LNAENSET LNAEN Set 14 1 write-only PAENCLEAR PAEN Clear 13 1 write-only PAENSET PAEN Set 12 1 write-only RXCAL Start an RX Calibration 7 1 write-only RXDIS RX Disable 8 1 write-only TXAFTERFRAME TX After Frame 4 1 write-only TXDIS TX Disable 5 1 write-only TXEN Transmitter Enable 0 1 write-only TXONCCA Transmit On CCA 2 1 write-only CTRL No Description 0x14 read-write n 0x0 0x0 ACTIVEPOL ACTIVE signal polarity 7 1 read-write X0 Active low 0 X1 Active high 1 FORCEDISABLE Force Radio Disable 0 1 read-write LNAENPOL LNAEN signal polarity 9 1 read-write X0 Active low 0 X1 Active high 1 PAENPOL PAEN signal polarity 8 1 read-write X0 Active low 0 X1 Active high 1 PRSCLR PRS RXEN Clear 5 1 read-write RXSEARCH The PRS RXEN signal is cleared when the RSM state enters RXSEARCH 0 PRSCH The Selected PRS channel in PRSCLRSEL is used as a disable pulse 1 PRSFORCETX PRS Force RX 16 1 read-write X0 PRS will not force TX 0 X1 The channel selected by PRSFORCETXSEL will generate a force TX pulse 1 PRSMODE PRS RXEN Mode 3 1 read-write DIRECT The PRS signal is used directly 0 PULSE The PRS signal is used as an RX enable pulse 1 PRSRXDIS PRS RX Disable 10 1 read-write X0 PRS will not disable RX 0 X1 The channel selected by PRSRXDISSEL will generate a disable RX pulse 1 PRSTXEN PRS TX Enable 1 1 read-write TXAFTERRX TX After RX 2 1 read-write X0 TX will not be started automatically. 0 X1 A transition to TX is automatically started when a received frame is accepted by the FRC. 1 TXPOSTPONE TX Postpone 6 1 read-write X0 In the TX state transmit data is output. 0 X1 In the TX state an unmodulated carrier is output until this bit is cleared. 1 DIGCLKRETIMECTRL No Description 0x15C read-write n 0x0 0x0 DIGCLKRETIMEDISRETIME DIGCLKRETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 DIGCLKRETIMEENRETIME DIGCLKRETIMEENRETIME 0 1 read-write disable 0 enable 1 DIGCLKRETIMELIMITH DIGCLKRETIMELIMITH 4 3 read-write DIGCLKRETIMELIMITL DIGCLKRETIMELIMITL 8 3 read-write DIGCLKRETIMERESETN DIGCLKRETIMERESETN 2 1 read-write operate 0 reset 1 DIGCLKRETIMESTATUS No Description 0x160 read-only n 0x0 0x0 DIGCLKRETIMECLKSEL DIGCLKRETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 DIGCLKRETIMERESETNLO DIGCLKRETIMERESETNLO 1 1 read-only lo 0 hi 1 EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FORCESTATE No Description 0x18 read-write n 0x0 0x0 FORCESTATE Force RAC state transition 0 4 read-write IEN No Description 0x20 read-write n 0x0 0x0 BUSERROR Bus Error Interrupt Enable 2 1 read-write SEQ Sequencer Flags Interrupt Enable 16 8 read-write STATECHANGE Radio State Change Interrupt Enable 0 1 read-write STIMCMPEV STIMER Compare Event Interrupt Enable 1 1 read-write IF No Description 0x1C read-write n 0x0 0x0 BUSERROR Bus Error 2 1 read-write SEQ Sequencer Interrupt Flags 16 8 read-write STATECHANGE Radio State Change 0 1 read-write STIMCMPEV STIMER Compare Event 1 1 read-write IFADCCAL 0xD8 -1 read-write n 0x0 0x0 IFADCENRCCAL IFADCENRCCAL 0 1 read-write rccal_disable 0 rccal_enable 1 IFADCTUNERC IFADCTUNERC 8 5 read-write IFADCTUNERCCALMODE IFADCTUNERCCALMODE 1 1 read-write SYmode 0 ADCmode 1 IFADCSTATUS 0xDC read-only n 0x0 0x0 IFADCRCCALOUT IFADCRCCALOUT 0 1 read-only lo 0 hi 1 IFADCTRIM 0xD4 -1 read-write n 0x0 0x0 IFADCCLKSEL IFADCCLKSEL 0 1 read-write clk_2p4g 0 clk_subg 1 IFADCENHALFMODE IFADCENHALFMODE 1 1 read-write full_speed_mode 0 half_speed_mode 1 IFADCLDOSERIESAMPLVL IFADCLDOSERIESAMPLVL 2 3 read-write v1p20 0 v1p24 1 v1p28 2 v1p32 3 v1p35 4 v1p39 5 v1p42 6 v1p46 7 IFADCLDOSHUNTAMPLVL IFADCLDOSHUNTAMPLVL 5 3 read-write v1p20 0 v1p24 1 v1p28 2 v1p32 3 v1p35 4 v1p39 5 v1p42 6 v1p46 7 IFADCLDOSHUNTCURLP IFADCLDOSHUNTCURLP 8 1 read-write low_power_disabled 0 low_power_enabled 1 IFADCLDOSHUNTCURLVL IFADCLDOSHUNTCURLVL 9 2 read-write current_180uA 0 current_190uA 1 current_200uA 2 current_210uA 3 IFADCOTAST1CURRENT IFADCOTAST1CURRENT 11 2 read-write negative_20p 0 negative_11p 1 nominal 2 positive_15p 3 IFADCOTAST2CURRENT IFADCOTAST2CURRENT 13 2 read-write negative_20p 0 negative_11p 1 nominal 2 positive_15p 3 IFADCREFBUFAMPLVL IFADCREFBUFAMPLVL 15 3 read-write v0p88 0 v0p91 1 v0p94 2 v0p97 3 v1p00 4 v1p03 5 v1p06 6 v1p09 7 IFADCREFBUFCURLVL IFADCREFBUFCURLVL 18 2 read-write current_65uA 0 current_75uA 1 current_85uA 2 current_95uA 3 IFADCSIDETONEAMP IFADCSIDETONEAMP 20 2 read-write diff_pk_10mV 0 diff_pk_20mV 1 diff_pk_50mV 2 diff_pk_100mV 3 IFADCSIDETONEFREQ IFADCSIDETONEFREQ 22 3 read-write na0 0 div_128 1 div_64 2 div_32 3 div_16 4 div_8 5 div_4 6 na7 7 IFADCTUNEZERO IFADCTUNEZERO 25 1 read-write nominal_zero 0 half_freq_zero 1 IFADCVCMLVL IFADCVCMLVL 26 2 read-write ratio_0p48 0 ratio_0p49 1 ratio_0p5 2 ratio_0p52 3 IFPGACTRL No Description 0xA0 read-write n 0x0 0x0 DCCALDCGEAR DC COMP GEAR Value for DCCAL 25 3 read-write DCCALDEC0 DEC0 Value for DCCAL 22 3 read-write DF3 Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO. 0 DF4WIDE Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO. 1 DF4NARROW Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO. 2 DF8WIDE Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO. 3 DF8NARROW Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO. 4 DCCALON Enable/Disable DCCAL in DEMOD 19 1 read-write DISABLE DC ESTI DISABLED 0 ENABLE DC ESTI ENABLED 1 DCESTIEN DCESTIEN Override for RAC 21 1 read-write DISABLE DCESTI Disabled in MODEM 0 ENABLE DCESTI Enabled in MODEM 1 DCRSTEN DC Compensation Filter Reset Enable 20 1 read-write DISABLE DC Comp out of Reset 0 ENABLE DC Comp in Reset 1 IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LNAMIXCAL 0xF0 -1 read-write n 0x0 0x0 LNAMIXCALEN LNAMIXCALEN 0 1 read-write cal_disable 0 cal_enable 1 LNAMIXCALVMODE LNAMIXCALVMODE 1 1 read-write current_mode 0 voltage_mode 1 LNAMIXENIRCAL1 LNAMIXENIRCAL1 2 1 read-write disable 0 enable 1 LNAMIXENIRCAL2 LNAMIXENIRCAL2 3 1 read-write disable 0 enable 1 LNAMIXIRCAL1AMP LNAMIXIRCAL1AMP 4 3 read-write LNAMIXIRCAL2AMP LNAMIXIRCAL2AMP 7 3 read-write LNAMIXEN 0xF4 read-write n 0x0 0x0 LNAMIXENLDO LNAMIXENLDO 0 1 read-write disable 0 enable 1 LNAMIXTRIM0 0xE4 -1 read-write n 0x0 0x0 LNAMIXCURCTRL LNAMIXCURCTRL 0 6 read-write LNAMIXHIGHCUR LNAMIXHIGHCUR 6 2 read-write current_470uA 0 current_530uA 1 unused 2 current_590uA 3 LNAMIXLOWCUR LNAMIXLOWCUR 8 2 read-write current_nom 0 unused 1 current_80percent 2 current_60percent 3 LNAMIXRFPKDBWSEL LNAMIXRFPKDBWSEL 10 2 read-write LNAMIXRFPKDCALCM LNAMIXRFPKDCALCM 12 6 read-write LNAMIXRFPKDCALDM LNAMIXRFPKDCALDM 18 5 read-write LNAMIXTRIMVREG LNAMIXTRIMVREG 23 4 read-write LNAMIXTRIM1 0xE8 -1 read-write n 0x0 0x0 LNAMIXIBIAS1ADJ LNAMIXIBIAS1ADJ 0 4 read-write LNAMIXLNA1CAPSEL LNAMIXLNA1CAPSEL 4 3 read-write LNAMIXMXRBIAS1 LNAMIXMXRBIAS1 7 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCAS1ADJ LNAMIXNCAS1ADJ 9 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCAS1ADJ LNAMIXPCAS1ADJ 11 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUT1ADJ LNAMIXVOUT1ADJ 13 4 read-write LNAMIXTRIM2 No Description 0xEC -1 read-write n 0x0 0x0 LNAMIXIBIAS2ADJ LNAMIXIBIAS2ADJ 0 4 read-write LNAMIXLNA2CAPSEL LNAMIXLNA2CAPSEL 4 3 read-write LNAMIXMXRBIAS2 LNAMIXMXRBIAS2 7 2 read-write bias_1V 0 unused 1 bias_900m 2 bias_800m 3 LNAMIXNCAS2ADJ LNAMIXNCAS2ADJ 9 2 read-write ncas_1V 0 unused 1 ncas_950m 2 ncas_900m 3 LNAMIXPCAS2ADJ LNAMIXPCAS2ADJ 11 2 read-write pcas_250m 0 unused 1 pcas_300m 2 pcas_350m 3 LNAMIXVOUT2ADJ LNAMIXVOUT2ADJ 13 4 read-write PACTRL 0x108 read-write n 0x0 0x0 PAEN10DBMVMID PAEN10DBMVMID 0 1 read-write disable 0 enable 1 PAEN20DBMVMID PAEN20DBMVMID 1 1 read-write disable 0 enable 1 PAENCAPATT PAENCAPATT 2 1 read-write disable 0 enable 1 PAENLATCHBYPASS PAENLATCHBYPASS 3 1 read-write disable 0 enable 1 PAENPOWERRAMPINGCLK PAENPOWERRAMPINGCLK 4 1 read-write silence_clk 0 en_clk 1 PAPOWER PAPOWER 16 4 read-write t0stripeon 0 t1stripeon 1 t10stripeon 10 t11stripeon 11 t12stripeon 12 t13stripeon 13 t14stripeon 14 t15stripeon 15 t2stripeon 2 t3stripeon 3 t4stripeon 4 t5stripeon 5 t6stripeon 6 t7stripeon 7 t8stripeon 8 t9stripeon 9 PAPULLDOWNVDDPA PAPULLDOWNVDDPA 5 1 read-write not_pull_down 0 pull_down_vddpa 1 PAREGBYPASSPDRVLDO PAREGBYPASSPDRVLDO 6 1 read-write not_bypass 0 bypass 1 PAREGBYPASSPREREG PAREGBYPASSPREREG 7 1 read-write not_bypass 0 bypass 1 PASELLDOVDDPA PASELLDOVDDPA 8 1 read-write not_selected 0 selected 1 PASELLDOVDDRF PASELLDOVDDRF 9 1 read-write not_selected 0 selected 1 PASELSLICE PASELSLICE 20 4 read-write PASLICERST PASLICERST 10 1 read-write disable 0 enable 1 PAENCTRL No Description 0xA4 read-write n 0x0 0x0 PARAMP PA output level ramping 8 1 read-write PATRIM0 0xFC -1 read-write n 0x0 0x0 PATRIMDRVREGIBCORE0DBM PATRIMDRVREGIBCORE0DBM 0 2 read-write i_4u 0 i_5u 1 i_6u 2 i_7u 3 PATRIMDRVREGIBNDIO0DBM PATRIMDRVREGIBNDIO0DBM 2 4 read-write vreg_1p09 0 vreg_1p13 1 NA_10 10 NA_11 11 NA_12 12 NA_13 13 NA_14 14 NA_15 15 vreg_1p16 2 vreg_1p20 3 vreg_1p23 4 vreg_1p25 5 vreg_1p28 6 vreg_1p31 7 vreg_1p33 8 vreg_1p36 9 PATRIMDRVREGPSR0DBM PATRIMDRVREGPSR0DBM 6 1 read-write disable 0 enable 1 PATRIMDRVSLICE0DBM PATRIMDRVSLICE0DBM 7 2 read-write on_0_slice 0 on_1_slice 1 on_2_slice 2 on_3_slice 3 PATRIMFB0DBM PATRIMFB0DBM 9 4 read-write vo_vi_0p475 0 vo_vi_0p500 1 vo_vi_0p725 10 vo_vi_0p750 11 vo_vi_0p775 12 vo_vi_0p80 13 vo_vi_0p825 14 vo_vi_0p85 15 vo_vi_0p525 2 vo_vi_0p550 3 vo_vi_0p575 4 vo_vi_0p600 5 vo_vi_0p625 6 vo_vi_0p650 7 vo_vi_0p675 8 vo_vi_0p700 9 PATRIMPABIASN0DBM PATRIMPABIASN0DBM 13 4 read-write v_450m 0 v_462p5m 1 v_575m 10 v_587p5m 11 v_600m 12 v_612p5m 13 v_625m 14 v_637p5m 15 v_475m 2 v_487p5m 3 v_500m 4 v_512p5m 5 v_525m 6 v_537p5m 7 v_550m 8 v_562p5m 9 PATRIMPABIASP0DBM PATRIMPABIASP0DBM 17 4 read-write v_450m 0 v_462p5m 1 v_575m 10 v_587p5m 11 v_600m 12 v_612p5m 13 v_625m 14 v_637p5m 15 v_475m 2 v_487p5m 3 v_500m 4 v_512p5m 5 v_525m 6 v_537p5m 7 v_550m 8 v_562p5m 9 PATRIMPASLICE0DBM PATRIMPASLICE0DBM 21 6 read-write on_slice_0 0 on_slice_63 63 PATRIMVREF0DBM PATRIMVREF0DBM 27 3 read-write v_900m 0 v_912p5m 1 v_925m 2 v_937p5m 3 v_950m 4 v_962p5m 5 v_975m 6 v_987p5m 7 PATRIM1 0x100 -1 read-write n 0x0 0x0 PATRIM10DBMDUTYCYN PATRIM10DBMDUTYCYN 0 3 read-write up_0pct 0 up_1pct 1 up_2pct 2 up_3pct 3 up_4pct 4 up_5pct 5 up_6pct 6 na 7 PATRIM10DBMDUTYCYP PATRIM10DBMDUTYCYP 3 3 read-write dn_0pct 0 dn_1pct 1 dn_2pct 2 dn_3pct 3 dn_4pct 4 dn_5pct 5 dn_6pct 6 na 7 PATRIM20DBMPREDRV PATRIM20DBMPREDRV 6 3 read-write trise_137ps 0 trise_127ps 1 trise_117ps 2 trise_110ps 3 trise_75ps 4 trise_73ps 5 trise_71ps 6 trise_70ps 7 PATRIMANTSWBIAS PATRIMANTSWBIAS 9 2 read-write vb_at_vdd 0 vb_at_vdd_mp6v 1 vb_at_vdd_m1p2v 2 vb_at_vdd_m1p8v 3 PATRIMBLEEDAUTOPREREG PATRIMBLEEDAUTOPREREG 11 1 read-write not_automatic 0 automatic 1 PATRIMCAPPAOUTM PATRIMCAPPAOUTM 12 4 read-write PATRIMCAPPAOUTP PATRIMCAPPAOUTP 16 4 read-write PATRIMCMGAIN PATRIMCMGAIN 20 2 read-write PATRIMDLY0 PATRIMDLY0 22 3 read-write tdly_0ps 0 tdly_64ps 1 tdly_65ps 2 tdly_66ps 3 tdly_68ps 4 tdly_70ps 5 tdly_75ps 6 tdly_83ps 7 PATRIMDLY1 PATRIMDLY1 25 3 read-write tdly_0ps 0 tdly_64ps 1 tdly_65ps 2 tdly_66ps 3 tdly_68ps 4 tdly_70ps 5 tdly_75ps 6 tdly_83ps 7 PATRIMFBKATTPDRVLDO PATRIMFBKATTPDRVLDO 28 1 read-write less_bw 0 more_bw 1 PATRIMIBIASMASTER PATRIMIBIASMASTER 29 2 read-write Ibias_is_45u 0 Ibias_is_47p5u 1 Ibias_is_50u 2 Ibias_is_52p5u 3 PATRIM2 0x104 -1 read-write n 0x0 0x0 PATRIMLDOFBHVPDRVLDO PATRIMLDOFBHVPDRVLDO 0 2 read-write vreg_1p22 0 vreg_1p28 1 vreg_1p35 2 vreg_1p44 3 PATRIMLDOFBHVPREREG PATRIMLDOFBHVPREREG 2 3 read-write vreg_1p678 0 vreg_1p735 1 vreg_1p801 2 vreg_1p875 3 vreg_3p00 4 vreg_3p14 5 vreg_3p3 6 vreg_3p477 7 PATRIMLDOHVPDRVLDO PATRIMLDOHVPDRVLDO 5 3 read-write vref_0p675 0 vref_0p700 1 vref_0p725 2 vref_0p750 3 vref_0p775 4 vref_0p800 5 vref_0p825 6 vref_0p850 7 PATRIMLDOHVPREREG PATRIMLDOHVPREREG 8 4 read-write vref_0p651 0 vref_0p663 1 vref_0p776 10 vref_0p788 11 vref_0p801 12 vref_0p813 13 vref_0p826 14 vref_0p838 15 vref_0p676 2 vref_0p688 3 vref_0p701 4 vref_0p713 5 vref_0p726 6 vref_0p738 7 vref_0p751 8 vref_0p763 9 PATRIMLDOPSRPDRVLDO PATRIMLDOPSRPDRVLDO 12 1 read-write low_psr 0 high_psr 1 PATRIMLDOPSRPREREG PATRIMLDOPSRPREREG 13 1 read-write low_psr 0 high_psr 1 PATRIMLDOSLICESPDRVLDO PATRIMLDOSLICESPDRVLDO 14 2 read-write iload_7p5mA 0 iload_15mA 1 iload_22p5mA 2 iload_30mA 3 PATRIMLDOSLICESPREREG PATRIMLDOSLICESPREREG 16 2 read-write spare1 0 spare2 1 spare3 2 spare4 3 PATRIMNBIAS PATRIMNBIAS 19 4 read-write vnbias_dn104mv 0 vnbias_dn91mv 1 vnbias_up26mv 10 vnbias_up39mv 11 vnbias_up52mv 12 vnbias_up65mv 13 vnbias_up78mv 14 vnbias_up91mv 15 vnbias_dn78mv 2 vnbias_dn65mv 3 vnbias_dn52mv 4 vnbias_dn39mv 5 vnbias_dn26mv 6 vnbias_dn13mv 7 vnbias_default 8 vnbias_up13mv 9 PATRIMNCASC PATRIMNCASC 23 2 read-write ncbias_m50mv 0 ncbias_default 1 ncbias_p50mv 2 ncbias_p100mv 3 PATRIMPADACGLITCH PATRIMPADACGLITCH 18 1 read-write larger_glitch 0 smaller_glitch 1 PATRIMPBIAS PATRIMPBIAS 25 4 read-write vpbias_up104mv 0 vpbias_up91mv 1 vpbias_dn26mv 10 vpbias_dn38mv 11 vpbias_dn52mv 12 vpbias_dn65mv 13 vpbias_dn78mv 14 vpbias_dn91mv 15 vpbias_up78mv 2 vpbias_up65mv 3 vpbias_up52mv 4 vpbias_up39mv 5 vpbias_up26mv 6 vpbias_up13mv 7 vpbias_default 8 vpbias_dn13mv 9 PATRIMPCASC PATRIMPCASC 29 2 read-write pcbias_p50mv 0 pcbias_default 1 pcbias_m50mv 2 pcbias_m100mv 3 PGACAL 0x114 -1 read-write n 0x0 0x0 PGAOFFNCALI PGAOFFNCALI 0 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFNCALQ PGAOFFNCALQ 8 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALI PGAOFFPCALI 16 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGAOFFPCALQ PGAOFFPCALQ 24 6 read-write offset_m_300mv 0 offset_p_300mv 63 PGACTRL 0x118 -1 read-write n 0x0 0x0 LNAMIXRFPKDTHRESHSEL LNAMIXRFPKDTHRESHSEL 24 3 read-write PGABWMODE PGABWMODE 0 2 read-write bw_5MHz 0 bw_2p5MHz 1 bw_1p67MHz 2 bw_1p25MHz 3 PGAENBIAS PGAENBIAS 2 1 read-write bias_disable 0 bias_enable 1 PGAENGHZ PGAENGHZ 3 1 read-write ghz_disable 0 ghz_enable 1 PGAENHYST PGAENHYST 4 1 read-write pkd_hyst_disable 0 pkd_hyst_enable 1 PGAENLATCHI PGAENLATCHI 5 1 read-write pkd_latch_i_disable 0 pkd_latch_i_enable 1 PGAENLATCHQ PGAENLATCHQ 6 1 read-write pkd_latch_q_disable 0 pkd_latch_q_enable 1 PGAENLDOLOAD PGAENLDOLOAD 7 1 read-write disable_ldo_load 0 enable_ldo_load 1 PGAENOFFD PGAENOFFD 8 1 read-write pkd_offd_disable 0 pkd_offd_enable 1 PGAENPGAI PGAENPGAI 9 1 read-write pgai_disable 0 pgai_enable 1 PGAENPGAQ PGAENPGAQ 10 1 read-write pgaq_disable 0 pgaq_enable 1 PGAENPKD PGAENPKD 11 1 read-write pkd_disable 0 pkd_enable 1 PGAENRCMOUT PGAENRCMOUT 12 1 read-write rcm_out_disable 0 rcm_out_enable 1 PGAPOWERMODE PGAPOWERMODE 14 2 read-write pm_typ 0 pm_0p8 1 pm_1p2 2 pm_0p5 3 PGATHRPKDHISEL PGATHRPKDHISEL 20 4 read-write vref50mv 0 vref75mv 1 vref300mv 10 vref100mv 2 vref125mv 3 verf150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 PGATHRPKDLOSEL PGATHRPKDLOSEL 16 4 read-write vref50mv 0 vref75mv 1 vref300mv 10 vref100mv 2 vref125mv 3 vref150mv 4 vref175mv 5 vref200mv 6 vref225mv 7 vref250mv 8 vref275mv 9 PGATRIM 0x110 -1 read-write n 0x0 0x0 PGACTUNE PGACTUNE 0 4 read-write cfb_0p7 0 cfb_1p32 15 cfb_nominal 7 PGADISANTILOCK PGADISANTILOCK 4 1 read-write antilock_enable 0 antilock_disable 1 PGAVCMOUTTRIM PGAVCMOUTTRIM 5 3 read-write vcm_out_0p4 0 vcm_out_0p45 1 vcm_out_0p5 2 vcm_out_0p55 3 vcm_out_0p6 4 vcm_out_0p65 5 vcm_out_0p7 6 vcm_out_0p75 7 PGAVLDOTRIM PGAVLDOTRIM 8 3 read-write vdda_1p15 0 vdda_1p2 1 vdda_1p25 2 vdda_1p3 3 vdda_1p35 4 vdda_1p4 5 vdda_1p5 6 vdda_1p55 7 PRECTRL 0xF8 -1 read-write n 0x0 0x0 PREBYPFORCE PREBYPFORCE 0 1 read-write not_forced 0 forced 1 PREREGTRIM PREREGTRIM 1 3 read-write v1p61 0 v1p68 1 v1p74 2 v1p80 3 v1p86 4 v1p91 5 v1p96 6 v2p00 7 PREVREFTRIM PREVREFTRIM 4 2 read-write v0p675 0 v0p688 1 v0p700 2 v0p713 3 PRESC No Description 0x6C -1 read-write n 0x0 0x0 STIMER STIMER Prescaler 0 7 read-write R0 No Description 0x34 read-write n 0x0 0x0 R0 Sequencer Register 0 0 32 read-write R1 No Description 0x38 read-write n 0x0 0x0 R1 Sequencer Register 1 0 32 read-write R2 No Description 0x3C read-write n 0x0 0x0 R2 Sequencer Register 2 0 32 read-write R3 No Description 0x40 read-write n 0x0 0x0 R3 Sequencer Register 3 0 32 read-write R4 No Description 0x44 read-write n 0x0 0x0 R4 Sequencer Register 4 0 32 read-write R5 No Description 0x48 read-write n 0x0 0x0 R5 Sequencer Register 5 0 32 read-write R6 No Description 0x4C read-write n 0x0 0x0 R6 Sequencer Register 6 0 32 read-write R7 No Description 0x50 read-write n 0x0 0x0 R7 Sequencer Register 7 0 32 read-write RADIOEN 0x124 read-write n 0x0 0x0 PREEN PREEN 0 1 read-write powered_off 0 powered_on 1 PRESTB100UDIS PRESTB100UDIS 1 1 read-write i100ua_enabled 0 i100ua_disabled 1 RFBIASEN RFBIASEN 2 1 read-write disable_dualbis_vtr 0 enable_dualbis_vtr 1 RFBIASCAL 0x11C -1 read-write n 0x0 0x0 RFBIASCALBIAS RFBIASCALBIAS 0 6 read-write RFBIASCALTC RFBIASCALTC 8 6 read-write RFBIASCALVREF RFBIASCALVREF 16 6 read-write RFBIASCALVREFSTARTUP RFBIASCALVREFSTARTUP 24 6 read-write RFBIASCTRL 0x120 -1 read-write n 0x0 0x0 RFBIASDISABLEBOOTSTRAP RFBIASDISABLEBOOTSTRAP 0 1 read-write enable_startup 0 disable_startup 1 RFBIASLDOHIGHCURRENT RFBIASLDOHIGHCURRENT 1 1 read-write low_current 0 high_current 1 RFBIASLDOVREFTRIM RFBIASLDOVREFTRIM 16 4 read-write vref_v0p800 0 vref_v0p813 1 vref_v0p925 10 vref_v0p938 11 vref_v0p950 12 vref_v0p963 13 vref_v0p975 14 vref_v0p988 15 vref_v0p825 2 vref_v0p837 3 vref_v0p850 4 vref_v0p863 5 vref_v0p875 6 vref_v0p887 7 vref_v0p900 8 vref_v0p913 9 RFBIASNONFLASHMODE RFBIASNONFLASHMODE 2 1 read-write flash_process 0 non_flash_process 1 RFBIASSTARTUPCORE RFBIASSTARTUPCORE 3 1 read-write default 0 force_start 1 RFBIASSTARTUPSUPPLY RFBIASSTARTUPSUPPLY 4 1 read-write default 0 forc_start 1 RFPATHEN1 No Description 0x128 -1 read-write n 0x0 0x0 LNAMIXEN0DBMPA1 LNAMIXEN0DBMPA1 0 1 read-write disable 0 enable 1 LNAMIXEN1 LNAMIXEN1 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN1 LNAMIXRFATTDCEN1 2 1 read-write disable_dc 0 enable_dc 1 LNAMIXRFPKDENRF1 LNAMIXRFPKDENRF1 3 1 read-write disable 0 enable_path1 1 LNAMIXTRSW1 LNAMIXTRSW1 4 1 read-write disabled 0 enabled 1 PAENANT1 PAENANT1 5 1 read-write disable 0 enable 1 PAENPA10DBM PAENPA10DBM 6 1 read-write disable 0 enable 1 PAENPAPREDRV10DBM PAENPAPREDRV10DBM 7 1 read-write disable 0 enable 1 RFPATHEN2 No Description 0x12C -1 read-write n 0x0 0x0 LNAMIXEN0DBMPA2 LNAMIXEN0DBMPA2 0 1 read-write disable 0 enable 1 LNAMIXEN2 LNAMIXEN2 1 1 read-write disable 0 enable 1 LNAMIXRFATTDCEN2 LNAMIXRFATTDCEN2 2 1 read-write disable 0 enable 1 LNAMIXRFPKDENRF2 LNAMIXRFPKDENRF2 3 1 read-write disable 0 enable_path2 1 LNAMIXTRSW2 LNAMIXTRSW2 4 1 read-write disable 0 enable 1 PAENANT2 PAENANT2 5 1 read-write disable 0 enable 1 PAENPA20DBM PAENPA20DBM 6 1 read-write disable 0 enable 1 PAENPAPREDRV20DBM PAENPAPREDRV20DBM 7 1 read-write disable 0 enable 1 RX 0x130 -1 read-write n 0x0 0x0 IFADCCAPRESET IFADCCAPRESET 0 1 read-write cap_reset_disable 0 cap_reset_enable 1 IFADCENLDOSERIES IFADCENLDOSERIES 1 1 read-write series_ldo_disable 0 series_ldo_enable 1 IFADCENLDOSHUNT IFADCENLDOSHUNT 2 1 read-write shunt_ldo_disable 0 shunt_ldo_enable 1 LNAMIXENRFPKD LNAMIXENRFPKD 3 1 read-write disable 0 enable 1 LNAMIXLDOLOWCUR LNAMIXLDOLOWCUR 4 1 read-write regular_mode 0 low_current_mode 1 LNAMIXREGLOADEN LNAMIXREGLOADEN 5 1 read-write disable_resistor 0 enable_resistor 1 PGAENLDO PGAENLDO 6 1 read-write disable_ldo 0 enable_ldo 1 SYCHPBIASTRIMBUF SYCHPBIASTRIMBUF 7 1 read-write i_tail_10u 0 i_tail_20u 1 SYCHPQNC3EN SYCHPQNC3EN 8 1 read-write qnc_2 0 qnc_3 1 SYMMDMODE SYMMDMODE 9 3 read-write rx_w_swctrl 0 rx_wo_swctrl 1 qnc_dsm2 2 qnc_dsm3 3 rxlp_wo_swctrl 4 notuse_5 5 notuse_6 6 notuse_7 7 SYPFDCHPLPEN SYPFDCHPLPEN 12 1 read-write disable 0 enable 1 SYPFDFPWEN SYPFDFPWEN 13 1 read-write disable 0 enable 1 RXENSRCEN No Description 0x8 read-write n 0x0 0x0 CHANNELBUSYEN Channel Busy Enable 8 1 read-write DEMODRXREQEN DEMOD RX Request Enable 12 1 read-write FRAMEDETEN Frame Detected Enable 11 1 read-write PREDETEN Preamble Detected Enable 10 1 read-write PRSRXEN PRS RX Enable 13 1 read-write SWRXEN SW RX Enable 0 8 read-write TIMDETEN Timing Detected Enable 9 1 read-write SCRATCH0 No Description 0x3E0 read-write n 0x0 0x0 SCRATCH0 SCRATCH0 0 32 read-write SCRATCH1 No Description 0x3E4 read-write n 0x0 0x0 SCRATCH1 SCRATCH1 0 32 read-write SCRATCH2 No Description 0x3E8 read-write n 0x0 0x0 SCRATCH2 SCRATCH2 0 32 read-write SCRATCH3 No Description 0x3EC read-write n 0x0 0x0 SCRATCH3 SCRATCH3 0 32 read-write SCRATCH4 No Description 0x3F0 read-write n 0x0 0x0 SCRATCH4 SCRATCH4 0 32 read-write SCRATCH5 No Description 0x3F4 read-write n 0x0 0x0 SCRATCH5 SCRATCH5 0 32 read-write SCRATCH6 No Description 0x3F8 read-write n 0x0 0x0 SCRATCH6 SCRATCH6 0 32 read-write SCRATCH7 No Description 0x3FC read-write n 0x0 0x0 SCRATCH7 SCRATCH7 0 32 read-write SEQCMD No Description 0x2C write-only n 0x0 0x0 ABORT Sequencer Execution Abort 5 1 write-only ABORTENCLEAR Clear Sequencer Abort Enable 7 1 write-only ABORTENSET Set Sequencer Abort Enable 6 1 write-only BKPTDIS Breakpoint Disable 4 1 write-only BKPTEN Breakpoint Enable 3 1 write-only HALT Sequencer Halt 0 1 write-only RESUME Sequencer Resume 2 1 write-only STEP Sequencer Step 1 1 write-only SEQCTRL No Description 0x68 read-write n 0x0 0x0 COMPACT STIMER Compare Action 0 1 read-write WRAP STIMER wraps when reaching STIMERCOMP 0 CONTINUE STIMER continues when reaching STIMERCOMP 1 COMPINVALMODE STIMER Comp Invalid Mode 1 2 read-write NEVER STIMERCOMP is always valid 0 STATECHANGE STIMERCOMP is invalidated when the RSM changes state 1 COMPEVENT STIMERCOMP is invalidated when an STIMER compare event occurs 2 STATECOMP STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs 3 CPUHALTREQEN CPU Halt Request Enable 11 1 read-write X0 Main CPU is not halted when the Sequencer is halted. 0 X1 Main CPU is halted when the Sequencer is halted. 1 SEQHALTUPONCPUHALTEN Sequencer Halt Upon CPU Halt Enable 12 1 read-write X0 Sequencer is not halted when the main CPU is halted. 0 X1 Sequencer is halted when the main CPU is halted. 1 STIMERDEBUGRUN STIMER Debug Run 10 1 read-write X0 STIMER is not running when the Sequencer is halted. 0 X1 STIMER is running when the Sequencer is halted. 1 SEQSTATUS No Description 0x28 -1 read-only n 0x0 0x0 ABORTEN Sequencer Program Execution Abort Enable 10 1 read-only X0 Sequencer Program Execution can not be aborted. 0 X1 Sequencer Program Execution can be aborted. 1 BKPT Breakpoint Enabled 1 1 read-only CARRY Carry Flag 8 1 read-only DONE Sequencer Done Signal 4 1 read-only NEG Negative Flag 5 1 read-only POS Positive Flag 6 1 read-only STOPPED Sequencer Stopped 0 1 read-only WAITING Sequencer Waiting 2 1 read-only WAITMODE Sequencer Waiting Mode 3 1 read-only ANY Sequencer is waiting for any of the events indicated SEQ_WAITMASK. 0 ALL Sequencer is waiting for all the events indicated SEQ_WAITMASK. 1 ZERO Zero Flag 7 1 read-only SR0 No Description 0x70 read-write n 0x0 0x0 SR0 Sequencer Storage Register 0 0 32 read-write SR1 No Description 0x74 read-write n 0x0 0x0 SR1 Sequencer Storage Register 1 0 32 read-write SR2 No Description 0x78 read-write n 0x0 0x0 SR2 Sequencer Storage Register 2 0 32 read-write SR3 No Description 0x7C read-write n 0x0 0x0 SR3 Sequencer Storage Register 3 0 32 read-write STATUS No Description 0xC read-only n 0x0 0x0 FORCESTATEACTIVE FSM state force active 19 1 read-only X0 No special state transition is currently in progress 0 X1 A forced state transition is currently in progress 1 RXENS RXEN Status 31 1 read-only X0 RXEN is not set. 0 X1 RXEN is set. 1 RXMASK Receive Enable Mask 0 16 read-only STATE Radio State 24 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 TXAFTERFRAMEACTIVE TX After Frame Active 21 1 read-only X0 The currently ongoing TX was not initiated by a TXAFTERFRAME command. 0 X1 The currently ongoing TX was initiated by a TXAFTERFRAME command. 1 TXAFTERFRAMEPEND TX After Frame Pending 20 1 read-only X0 A transmit after frame operation is currently not pending. 0 X1 A transmit after frame operation is currently pending. 1 TXENS TXEN Status 30 1 read-only X0 TXEN is not set. 0 X1 TXEN is set. 1 STATUS2 No Description 0x9C read-only n 0x0 0x0 PREVSTATE1 Previous Radio State 0 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 PREVSTATE2 Previous Radio State 2 4 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 PREVSTATE3 Previous Radio State 3 8 4 read-only OFF Radio is off 0 RXWARM Radio is enabling receiver 1 TXPD Radio is powering down transmitter and going to OFF state 10 TX2RX Radio is disabling transmitter and enabling reception 11 TX2TX Radio is preparing for a transmission after the previous transmission was ended 12 SHUTDOWN Radio is powering down receiver and going to OFF state 13 RXSEARCH Radio is listening for incoming frames 2 RXFRAME Radio is receiving a frame 3 RXPD Radio is powering down receiver and going to OFF state 4 RX2RX Radio remains in receive mode after frame reception is completed 5 RXOVERFLOW Received data was lost due to full receive buffer 6 RX2TX Radio is disabling receiver and enabling transmitter 7 TXWARM Radio is enabling transmitter 8 TX Radio is transmitting data 9 STIMER No Description 0x5C read-only n 0x0 0x0 STIMER STIMER Register 0 16 read-only STIMERCOMP No Description 0x60 read-write n 0x0 0x0 STIMERCOMP STIMER Compare Register 0 16 read-write SYCAL 0x144 -1 read-write n 0x0 0x0 SYHILOADCHPREG SYHILOADCHPREG 24 2 read-write i_350uA 0 i_500uA 1 i_550uA 2 i_700uA 3 SYVCOMODEPKD SYVCOMODEPKD 8 1 read-write t_openloop_0 0 t_pkdetect_1 1 SYVCOMORECURRENT SYVCOMORECURRENT 9 1 read-write more_current_0 0 more_current_1 1 SYVCOSLOWNOISEFILTER SYVCOSLOWNOISEFILTER 10 1 read-write slow_noise_filter_0 0 slow_noise_filter_1 1 SYVCOVCAPVCM SYVCOVCAPVCM 15 2 read-write SYEN 0x148 read-write n 0x0 0x0 SYCHPEN SYCHPEN 0 1 read-write disable 0 enable 1 SYCHPLPEN SYCHPLPEN 1 1 read-write disable 0 enable 1 SYENCHPREG SYENCHPREG 2 1 read-write Disable 0 Enable 1 SYENCHPREPLICA SYENCHPREPLICA 3 1 read-write disable 0 enable 1 SYENMMDREG SYENMMDREG 4 1 read-write Disable 0 Enable 1 SYENMMDREPLICA1 SYENMMDREPLICA1 5 1 read-write disable 0 enable 1 SYENMMDREPLICA2 SYENMMDREPLICA2 6 1 read-write Disable 0 Enable 1 SYENVCOBIAS SYENVCOBIAS 7 1 read-write en_vco_bias_0 0 en_vco_bias_1 1 SYENVCOPFET SYENVCOPFET 8 1 read-write en_vco_pfet_0 0 en_vco_pfet_1 1 SYENVCOREG SYENVCOREG 9 1 read-write en_vco_reg_0 0 en_vco_reg_1 1 SYLODIVEN SYLODIVEN 10 1 read-write disable 0 enable 1 SYLODIVLDOBIASEN SYLODIVLDOBIASEN 11 1 read-write disable 0 enable 1 SYLODIVLDOEN SYLODIVLDOEN 12 1 read-write disable 0 enable 1 SYSTARTCHPREG SYSTARTCHPREG 13 1 read-write no_fast_startup 0 fast_startup 1 SYSTARTMMDREG SYSTARTMMDREG 14 1 read-write no_fast_startup 0 fast_startup 1 SYLOEN 0x14C read-write n 0x0 0x0 SYLODIVRLO12G4EN SYLODIVRLO12G4EN 1 1 read-write disable 0 enable 1 SYLODIVRLO22G4EN SYLODIVRLO22G4EN 3 1 read-write disable 0 enable 1 SYLODIVRLOADCCLK2G4EN SYLODIVRLOADCCLK2G4EN 0 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4AUXEN 5 1 read-write disable 0 enable 1 SYLODIVTLO0DBM2G4EN SYLODIVTLO0DBM2G4EN 6 1 read-write disable 0 enable 1 SYLODIVTLO20DBM2G4AUXEN SYLODIVTLO20DBM2G4AUXEN 9 1 read-write disable 0 enable 1 SYLODIVTLO20DBM2G4EN SYLODIVTLO20DBM2G4EN 10 1 read-write disable 0 enable 1 SYMMDCTRL 0x158 read-write n 0x0 0x0 SYMMDDIVRSDIG SYMMDDIVRSDIG 1 2 read-write Divideby1 0 Divideby2 1 Divideby4 2 Divideby8 3 SYMMDENRSDIG SYMMDENRSDIG 0 1 read-write disable 0 enable 1 SYNTHCTRL No Description 0x94 read-write n 0x0 0x0 MMDPOWERBALANCEDISABLE SYMMDPOWERBALANCEENB 10 1 read-write EnablePowerbleed 0 DisablePowerBleed 1 SYNTHENCTRL No Description 0x84 read-write n 0x0 0x0 LPFBWSEL LPF bandwidth register selection 20 1 read-write LPFBWRX Select LPFBWRX 0 LPFBWTX Select LPFBWTX 1 VCBUFEN SYLPFVCBUFEN 7 1 read-write Disabled 0 Enabled 1 VCOSTARTUP SYVCOFASTSTARTUP 1 1 read-write fast_start_up_0 0 fast_start_up_1 1 SYNTHREGCTRL No Description 0x88 -1 read-write n 0x0 0x0 CHPLDOVREFTRIM SYTRIMCHPREGVREF 24 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 MMDLDOVREFTRIM SYTRIMMMDREGVREF 10 3 read-write vref0p6000 0 vref0p6125 1 vref0p6250 2 vref0p6375 3 vref0p6500 4 vref0p6625 5 vref0p6750 6 vref0p6875 7 SYTRIM0 0x13C -1 read-write n 0x0 0x0 SYCHPBIAS SYCHPBIAS 0 3 read-write bias_0 0 bias_1 1 bias_2 3 bias_3 7 SYCHPCURR SYCHPCURR 3 3 read-write curr_1p5uA 0 curr_2p0uA 1 curr_2p5uA 2 curr_3p0uA 3 curr_3p5uA 4 curr_4p0uA 5 curr_4p5uA 6 curr_5p0uA 7 SYCHPLEVNSRC SYCHPLEVNSRC 6 3 read-write SYCHPLEVPSRC SYCHPLEVPSRC 9 3 read-write vsrcp_n105m 0 vsrcp_n90m 1 vsrcp_n75m 2 vsrcp_n60m 3 vsrcp_n45m 4 vsrcp_n30m 5 vsrcp_n15m 6 vsrcp_n0m 7 SYCHPREPLICACURRADJ SYCHPREPLICACURRADJ 14 3 read-write load_8ua 0 load_16ua 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYCHPSRCEN SYCHPSRCEN 13 1 read-write disable 0 enable 1 SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBIAS 17 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMCHPREGAMPBW SYTRIMCHPREGAMPBW 20 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 SYTRIM1 0x140 -1 read-write n 0x0 0x0 SYLODIVLDOTRIMCORE SYLODIVLDOTRIMCORE 0 2 read-write RXLO 0 TXLO 3 SYLODIVLDOTRIMNDIO SYLODIVLDOTRIMNDIO 2 4 read-write vreg_1p08 0 vreg_1p11 1 vreg_1p15 2 vreg_1p18 3 vreg_1p21 4 vreg_1p24 5 vreg_1p27 6 vreg_1p29 7 vreg_1p32 8 vreg_1p34 9 SYMMDREPLICA1CURRADJ SYMMDREPLICA1CURRADJ 6 3 read-write load_8ua 0 load_16u 1 load_20ua 2 load_28ua 3 load_24ua 4 load_32ua 5 load_36ua 6 load_44ua 7 SYMMDREPLICA2CURRADJ SYMMDREPLICA2CURRADJ 9 3 read-write load_32u 0 load_64u 1 load_96u 2 load_128u 3 load_160u 4 load_192u 5 load_224u 6 load_256u 7 SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBIAS 12 3 read-write bias_14uA 0 bias_20uA 1 bias_26uA 2 bias_32uA 3 bias_38uA 4 bias_44uA 5 bias_50uA 6 bias_56uA 7 SYTRIMMMDREGAMPBW SYTRIMMMDREGAMPBW 15 2 read-write C_000f 0 C_300f 1 C_600f 2 C_900f 3 TESTCTRL No Description 0x24 read-write n 0x0 0x0 AUX2RFSENSE Enable auxiliary synthesizer output 2 1 read-write X0 The auxiliary synthesizer is not connected to the RFSENSE input 0 X1 The auxiliary synthesizer is connected to the RFSENSE input 1 DEMODEN Demodulator enable 1 1 read-write LOOPBACK2LNAINPUT Enable RF loopback 3 1 read-write LOOPBACK2LNAOUTPUT Enable RF loopback 4 1 read-write MODEN Modulator enable 0 1 read-write TX 0x134 read-write n 0x0 0x0 ENPAPOWER Override 30 1 read-write ENPASELSLICE Override 31 1 read-write ENPATRIMPASLICE0DBM Override 10 1 read-write ENXOSQBUFFILT Override 29 1 read-write PABLEEDDRVREG0DBM PABLEEDDRVREG0DBM 0 1 read-write disable 0 enable 1 PABLEEDREG0DBM PABLEEDREG0DBM 1 1 read-write disable 0 enable 1 PAEN10DBMM PAEN10DBMM 16 1 read-write disable 0 enable 1 PAEN10DBMP PAEN10DBMP 17 1 read-write disable 0 enable 1 PAEN10DBMPDRV PAEN10DBMPDRV 18 1 read-write disable 0 enable 1 PAEN20DBM PAEN20DBM 20 1 read-write disable 0 enable 1 PAEN20DBMPDRV PAEN20DBMPDRV 21 1 read-write disable 0 enable 1 PAENBIAS0DBM PAENBIAS0DBM 2 1 read-write disable 0 enable 1 PAENBLEEDPDRVLDO PAENBLEEDPDRVLDO 24 1 read-write disable 0 enable 1 PAENBLEEDPREREG PAENBLEEDPREREG 25 1 read-write disable 0 enable 1 PAENDRVREG0DBM PAENDRVREG0DBM 3 1 read-write disable 0 enable 1 PAENDRVREGBIAS0DBM PAENDRVREGBIAS0DBM 4 1 read-write disable 0 enable 1 PAENLDOHVPDRVLDO PAENLDOHVPDRVLDO 26 1 read-write disable 0 enable 1 PAENLDOHVPREREG PAENLDOHVPREREG 27 1 read-write disable 0 enable 1 PAENLO0DBM PAENLO0DBM 5 1 read-write disable 0 enable 1 PAENPAOUT PAENPAOUT 28 1 read-write disable 0 enable 1 PAENREG0DBM PAENREG0DBM 6 1 read-write disable 0 enable 1 PAENTAPCAP0DBM PAENTAPCAP0DBM 7 3 read-write cap_0f 0 cap_0p35pF 1 cap_0p7pF 2 cap_1p05pF 3 cap_1p4pF 4 cap_1p75pF 5 cap_2p1pF 6 cap_2p45pF 7 VCOCTRL No Description 0x8C -1 read-write n 0x0 0x0 VCOAMPLITUDE SYVCOAMPLOPEN 0 4 read-write VCODETAMPLITUDE SYVCOAMPLPKD 4 4 read-write VECTADDR No Description 0x64 read-write n 0x0 0x0 VECTADDR Vector Table Address 0 32 read-write WAITMASK No Description 0x54 read-only n 0x0 0x0 ANTSWITCH Active antenna has switched 8 1 read-only DEMODRXREQCLR Demodulator RX Request Clear 4 1 read-only FRCPAUSED FRC Paused 7 1 read-only FRCRX FRC RXWord 1 1 read-only FRCTX FRC TXWord 2 1 read-only PRSEVENT PRS Event 3 1 read-only RAMPDONE Ramp Done 6 1 read-only STCMP STIMER Compare Event 0 1 read-only SYNTHRDY SYNTH Ready 5 1 read-only WAITSNSH No Description 0x58 read-only n 0x0 0x0 WAITSNSH Wait Event Snapshot 0 10 read-only XORETIMECTRL No Description 0x164 read-write n 0x0 0x0 XORETIMEDISRETIME XORETIMEDISRETIME 1 1 read-write enable_retime 0 disable_retime 1 XORETIMEENRETIME XORETIMEENRETIME 0 1 read-write disable 0 enable 1 XORETIMELIMITH XORETIMELIMITH 4 3 read-write XORETIMELIMITL XORETIMELIMITL 8 3 read-write XORETIMERESETN XORETIMERESETN 2 1 read-write operate 0 reset 1 XORETIMESTATUS No Description 0x168 read-only n 0x0 0x0 XORETIMECLKSEL XORETIMECLKSEL 0 1 read-only use_raw_clk 0 use_retimed_clk 1 XORETIMERESETNLO XORETIMERESETNLO 1 1 read-only lo 0 hi 1 XOSQBUFFILT 0x16C read-write n 0x0 0x0 XOSQBUFFILT XOSQBUFFILT 0 2 read-write bypass 0 filter_1 1 filter_2 2 filter_3 3 RADIOAES_NS RADIOAES_NS Registers RADIOAES_NS 0x0 0x0 0x50 registers n AES 49 CMD Command register for starting the fetcher and pusher 0x38 write-only n 0x0 0x0 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x34 read-write n 0x0 0x0 FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write FETCHADDR Fetcher: Start address of data block 0x0 read-write n 0x0 0x0 ADDR Start address of data block 0 32 read-write FETCHDESCR Fetcher: Descriptor address (Should be renamed to match Barco doc after PG) 0x4 read-write n 0x0 0x0 DESCR Descriptor address 0 32 read-write FETCHLEN Fetcher: Length of data block 0x8 read-write n 0x0 0x0 CONSTADDR Constant address 28 1 read-write LENGTH Length of data block 0 28 read-write REALIGN Realign lengh 29 1 read-write FETCHTAG Fetcher: User tag 0xC read-write n 0x0 0x0 TAG User tag 0 32 read-write IEN Interrupt enable 0x1C read-write n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write IF Interrupt flag register 0x28 read-only n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only IFC Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x30 write-only n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only PUSHERENDOFBLOCK New BitField 3 1 write-only PUSHERERROR New BitField 5 1 write-only PUSHERSTOPPED New BitField 4 1 write-only PUSHADDR Pusher: Start address of data block 0x10 read-write n 0x0 0x0 ADDR Start address of data block 0 32 read-write PUSHDESCR Pusher: Descriptor address (Should be renamed to match Barco doc after PG) 0x14 read-write n 0x0 0x0 DESCR Descriptor address 0 32 read-write PUSHLEN Pusher: Length of data block 0x18 read-write n 0x0 0x0 CONSTADDR Constant address 28 1 read-write DISCARD Discard data 30 1 read-write LENGTH Start address of data block 0 28 read-write REALIGN Realign length 29 1 read-write STATUS Status register 0x3C read-only n 0x0 0x0 FETCHERBSY Fetcher busy 0 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only PUSHERBSY Pusher busy 1 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only RADIOAES_S RADIOAES_S Registers RADIOAES_S 0x0 0x0 0x50 registers n AES 49 CMD Command register for starting the fetcher and pusher 0x38 write-only n 0x0 0x0 STARTFETCHER Start fetch 0 1 write-only STARTPUSHER Start push 1 1 write-only CTRL Control register, called CONFIG in Barco datasheet. 0x34 read-write n 0x0 0x0 FETCHERSCATTERGATHER Fetcher scatter/gather 0 1 read-write PUSHERSCATTERGATHER Pusher scatter/gather 1 1 read-write STOPFETCHER Stop fetcher 2 1 read-write STOPPUSHER Stop pusher 3 1 read-write SWRESET Software reset 4 1 read-write FETCHADDR Fetcher: Start address of data block 0x0 read-write n 0x0 0x0 ADDR Start address of data block 0 32 read-write FETCHDESCR Fetcher: Descriptor address (Should be renamed to match Barco doc after PG) 0x4 read-write n 0x0 0x0 DESCR Descriptor address 0 32 read-write FETCHLEN Fetcher: Length of data block 0x8 read-write n 0x0 0x0 CONSTADDR Constant address 28 1 read-write LENGTH Length of data block 0 28 read-write REALIGN Realign lengh 29 1 read-write FETCHTAG Fetcher: User tag 0xC read-write n 0x0 0x0 TAG User tag 0 32 read-write IEN Interrupt enable 0x1C read-write n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt enable 0 1 read-write FETCHERERROR Error interrupt enable 2 1 read-write FETCHERSTOPPED Stopped interrupt enable 1 1 read-write PUSHERENDOFBLOCK End of block interrupt enable 3 1 read-write PUSHERERROR Error interrupt enable 5 1 read-write PUSHERSTOPPED Stopped interrupt enable 4 1 read-write IF Interrupt flag register 0x28 read-only n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt flag 0 1 read-only FETCHERERROR Error interrupt flag 2 1 read-only FETCHERSTOPPED Stopped interrupt flag 1 1 read-only PUSHERENDOFBLOCK End of block interrupt flag 3 1 read-only PUSHERERROR Error interrupt flag 5 1 read-only PUSHERSTOPPED Stopped interrupt flag 4 1 read-only IFC Writing a '1' clears the interrupt status. Writing a '0' has no effect. 0x30 write-only n 0x0 0x0 FETCHERENDOFBLOCK End of block interrupt flag clear 0 1 write-only FETCHERERROR Error interrupt flag clear 2 1 write-only FETCHERSTOPPED Stopped interrupt flag clear 1 1 write-only PUSHERENDOFBLOCK New BitField 3 1 write-only PUSHERERROR New BitField 5 1 write-only PUSHERSTOPPED New BitField 4 1 write-only PUSHADDR Pusher: Start address of data block 0x10 read-write n 0x0 0x0 ADDR Start address of data block 0 32 read-write PUSHDESCR Pusher: Descriptor address (Should be renamed to match Barco doc after PG) 0x14 read-write n 0x0 0x0 DESCR Descriptor address 0 32 read-write PUSHLEN Pusher: Length of data block 0x18 read-write n 0x0 0x0 CONSTADDR Constant address 28 1 read-write DISCARD Discard data 30 1 read-write LENGTH Start address of data block 0 28 read-write REALIGN Realign length 29 1 read-write STATUS Status register 0x3C read-only n 0x0 0x0 FETCHERBSY Fetcher busy 0 1 read-only FIFODATANUM Number of data in output FIFO 16 16 read-only NOTEMPTY Not empty flag from input FIFO (fetcher) 4 1 read-only PUSHERBSY Pusher busy 1 1 read-only SOFTRSTBSY Software reset busy 6 1 read-only WAITING Pusher waiting for FIFO 5 1 read-only RFCRC_NS RFCRC_NS Registers RFCRC_NS 0x0 0x0 0x1000 registers n CMD No Description 0x10 write-only n 0x0 0x0 INITIALIZE Initialize CRC 0 1 write-only CTRL No Description 0x8 -1 read-write n 0x0 0x0 BITREVERSE Reverse CRC bit ordering over air 7 1 read-write NORMAL The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller. 0 REVERSED The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller. 1 BITSPERWORD Number of bits per input word 8 4 read-write BYTEREVERSE Reverse CRC byte ordering over air 6 1 read-write NORMAL The least significant byte of the CRC register is transferred first over air via the Frame Controller. 0 REVERSED The most significant byte of the CRC register is transferred first over air via the Frame Controller. 1 CRCWIDTH None 2 2 read-write CRCWIDTH8 8 bit (1 Byte) CRC code 0 CRCWIDTH16 16 bit (2 Bytes) CRC code 1 CRCWIDTH24 24 bit (3 Bytes) CRC code 2 CRCWIDTH32 32 bit (4 Bytes) CRC code 3 INPUTBITORDER CRC input bit ordering setting 5 1 read-write LSBFIRST The least significant data bit is first input to the CRC generator. 0 MSBFIRST The most significant data bit is first input to the CRC generator. 1 INPUTINV Input Invert 0 1 read-write OUTPUTINV Output Invert 1 1 read-write PADCRCINPUT Pad CRC input data 12 1 read-write X0 No zero-padding of CRC input data is applied 0 X1 CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value. 1 DATA No Description 0x1C read-only n 0x0 0x0 DATA CRC Data Register 0 32 read-only EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write INIT No Description 0x18 read-write n 0x0 0x0 INIT CRC Initialization Value 0 32 read-write INPUTDATA No Description 0x14 write-only n 0x0 0x0 INPUTDATA Input Data 0 16 write-only IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only POLY No Description 0x20 read-write n 0x0 0x0 POLY CRC Polynomial Value 0 32 read-write STATUS No Description 0xC read-only n 0x0 0x0 BUSY CRC Running 0 1 read-only RFCRC_S RFCRC_S Registers RFCRC_S 0x0 0x0 0x1000 registers n CMD No Description 0x10 write-only n 0x0 0x0 INITIALIZE Initialize CRC 0 1 write-only CTRL No Description 0x8 -1 read-write n 0x0 0x0 BITREVERSE Reverse CRC bit ordering over air 7 1 read-write NORMAL The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller. 0 REVERSED The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller. 1 BITSPERWORD Number of bits per input word 8 4 read-write BYTEREVERSE Reverse CRC byte ordering over air 6 1 read-write NORMAL The least significant byte of the CRC register is transferred first over air via the Frame Controller. 0 REVERSED The most significant byte of the CRC register is transferred first over air via the Frame Controller. 1 CRCWIDTH None 2 2 read-write CRCWIDTH8 8 bit (1 Byte) CRC code 0 CRCWIDTH16 16 bit (2 Bytes) CRC code 1 CRCWIDTH24 24 bit (3 Bytes) CRC code 2 CRCWIDTH32 32 bit (4 Bytes) CRC code 3 INPUTBITORDER CRC input bit ordering setting 5 1 read-write LSBFIRST The least significant data bit is first input to the CRC generator. 0 MSBFIRST The most significant data bit is first input to the CRC generator. 1 INPUTINV Input Invert 0 1 read-write OUTPUTINV Output Invert 1 1 read-write PADCRCINPUT Pad CRC input data 12 1 read-write X0 No zero-padding of CRC input data is applied 0 X1 CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value. 1 DATA No Description 0x1C read-only n 0x0 0x0 DATA CRC Data Register 0 32 read-only EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write INIT No Description 0x18 read-write n 0x0 0x0 INIT CRC Initialization Value 0 32 read-write INPUTDATA No Description 0x14 write-only n 0x0 0x0 INPUTDATA Input Data 0 16 write-only IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only POLY No Description 0x20 read-write n 0x0 0x0 POLY CRC Polynomial Value 0 32 read-write STATUS No Description 0xC read-only n 0x0 0x0 BUSY CRC Running 0 1 read-only RTCC_NS RTCC_NS Registers RTCC_NS 0x0 0x0 0x1000 registers n RTCC 10 CC0_CTRL No Description 0x30 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC0_ICVALUE No Description 0x38 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC0_OCVALUE No Description 0x34 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_CTRL No Description 0x3C read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC1_ICVALUE No Description 0x44 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC1_OCVALUE No Description 0x40 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC2_CTRL No Description 0x48 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC2_ICVALUE No Description 0x50 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC2_OCVALUE No Description 0x4C read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CFG No Description 0x8 read-write n 0x0 0x0 CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0] 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CMD No Description 0xC write-only n 0x0 0x0 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only CNT No Description 0x20 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMBCNT No Description 0x24 read-only n 0x0 0x0 CNTLSB Counter Value 15 17 read-only PRECNT Pre-Counter Value 0 15 read-only EN No Description 0x4 read-write n 0x0 0x0 EN RTCC Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Enable 2 1 read-write CC1 CC Channel n Interrupt Enable 3 1 read-write CC2 CC Channel n Interrupt Enable 4 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write OF OF Interrupt Enable 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Flag 2 1 read-write CC1 CC Channel n Interrupt Flag 3 1 read-write CC2 CC Channel n Interrupt Flag 4 1 read-write CNTTICK Main counter tick 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP VERSION 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 PRECNT No Description 0x1C read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 read-only n 0x0 0x0 RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 RUNNING RTCC running status 0 1 read-only SYNCBUSY No Description 0x28 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only RTCC_S RTCC_S Registers RTCC_S 0x0 0x0 0x1000 registers n RTCC 10 CC0_CTRL No Description 0x30 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC0_ICVALUE No Description 0x38 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC0_OCVALUE No Description 0x34 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_CTRL No Description 0x3C read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC1_ICVALUE No Description 0x44 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC1_OCVALUE No Description 0x40 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC2_CTRL No Description 0x48 read-write n 0x0 0x0 CMOA Compare Match Output Action 2 2 read-write PULSE A single clock cycle pulse is generated on output 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COMPBASE Capture compare channel comparison base. 4 1 read-write CNT RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register. 0 PRECNT Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT. 1 ICEDGE Input Capture Edge Select 5 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input capture 1 OUTPUTCOMPARE Output compare 2 CC2_ICVALUE No Description 0x50 read-only n 0x0 0x0 IC Input Capture Value 0 32 read-only CC2_OCVALUE No Description 0x4C read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CFG No Description 0x8 read-write n 0x0 0x0 CNTCCV1TOP CCV1 top value enable 2 1 read-write CNTPRESC Counter prescaler value. 4 4 read-write DIV1 CLK_CNT = (RTCC LF CLK)/1 0 DIV2 CLK_CNT = (RTCC LF CLK)/2 1 DIV1024 CLK_CNT = (RTCC LF CLK)/1024 10 DIV2048 CLK_CNT = (RTCC LF CLK)/2048 11 DIV4096 CLK_CNT = (RTCC LF CLK)/4096 12 DIV8192 CLK_CNT = (RTCC LF CLK)/8192 13 DIV16384 CLK_CNT = (RTCC LF CLK)/16384 14 DIV32768 CLK_CNT = (RTCC LF CLK)/32768 15 DIV4 CLK_CNT = (RTCC LF CLK)/4 2 DIV8 CLK_CNT = (RTCC LF CLK)/8 3 DIV16 CLK_CNT = (RTCC LF CLK)/16 4 DIV32 CLK_CNT = (RTCC LF CLK)/32 5 DIV64 CLK_CNT = (RTCC LF CLK)/64 6 DIV128 CLK_CNT = (RTCC LF CLK)/128 7 DIV256 CLK_CNT = (RTCC LF CLK)/256 8 DIV512 CLK_CNT = (RTCC LF CLK)/512 9 CNTTICK Counter prescaler mode. 3 1 read-write PRESC CNT register ticks according to configuration in CNTPRESC. 0 CCV0MATCH CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0] 1 DEBUGRUN Debug Mode Run Enable 0 1 read-write X0 RTCC is frozen in debug mode 0 X1 RTCC is running in debug mode 1 PRECNTCCV0TOP Pre-counter CCV0 top value enable. 1 1 read-write CMD No Description 0xC write-only n 0x0 0x0 START Start RTCC main counter 0 1 write-only STOP Stop RTCC main counter 1 1 write-only CNT No Description 0x20 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write COMBCNT No Description 0x24 read-only n 0x0 0x0 CNTLSB Counter Value 15 17 read-only PRECNT Pre-Counter Value 0 15 read-only EN No Description 0x4 read-write n 0x0 0x0 EN RTCC Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Enable 2 1 read-write CC1 CC Channel n Interrupt Enable 3 1 read-write CC2 CC Channel n Interrupt Enable 4 1 read-write CNTTICK CNTTICK Interrupt Enable 1 1 read-write OF OF Interrupt Enable 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 CC Channel n Interrupt Flag 2 1 read-write CC1 CC Channel n Interrupt Flag 3 1 read-write CC2 CC Channel n Interrupt Flag 4 1 read-write CNTTICK Main counter tick 1 1 read-write OF Overflow Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP VERSION 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Configuration Lock Key 0 16 write-only UNLOCK Write to unlock RTCC lockable registers 44776 PRECNT No Description 0x1C read-write n 0x0 0x0 PRECNT Pre-Counter Value 0 15 read-write STATUS No Description 0x10 read-only n 0x0 0x0 RTCCLOCKSTATUS Lock Status 1 1 read-only UNLOCKED RTCC registers are unlocked 0 LOCKED RTCC registers are locked 1 RUNNING RTCC running status 0 1 read-only SYNCBUSY No Description 0x28 read-only n 0x0 0x0 CNT Sync busy for CNT 3 1 read-only PRECNT Sync busy for PRECNT 2 1 read-only START Sync busy for START 0 1 read-only STOP Sync busy for STOP 1 1 read-only SEMAILBOX_NS_HOST SEMAILBOX_NS_HOST Registers SEMAILBOX_NS_HOST 0x0 0x0 0x1000 registers n CONFIGURATION No Description 0x58 read-write n 0x0 0x0 RXINTEN RX Interrupt Enable 1 1 read-write TXINTEN TX Interrupt Enable 0 1 read-write DATA0 No Description 0x0 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA1 No Description 0x4 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA10 No Description 0x28 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA11 No Description 0x2C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA12 No Description 0x30 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA13 No Description 0x34 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA14 No Description 0x38 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA15 No Description 0x3C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA2 No Description 0x8 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA3 No Description 0xC read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA4 No Description 0x10 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA5 No Description 0x14 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA6 No Description 0x18 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA7 No Description 0x1C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA8 No Description 0x20 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA9 No Description 0x24 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write RX_HEADER No Description 0x54 read-only n 0x0 0x0 SIZE SIZE 0 16 read-only STATUS Command Status 16 4 read-only UNPROTECTED Unprotected 21 1 read-only RX_PROT No Description 0x4C read-only n 0x0 0x0 NONSEC Non-Secure Access 23 1 read-only PRIV Privileged Access 22 1 read-only UNPROTECTED Unprotected 21 1 read-only USER User Bits 24 8 read-only RX_STATUS No Description 0x44 read-only n 0x0 0x0 BYTEREM Bytes Remaining 0 16 read-only RXEMPTY RX FIFO Empty 21 1 read-only RXERROR RX Error Flag 23 1 read-only RXHEADER RX Header 22 1 read-only RXINT Interrupt Status 20 1 read-only STATUS Message Status 16 4 read-only TX_HEADER No Description 0x50 write-only n 0x0 0x0 SIZE Command Size 0 16 write-only UNPROTECTED Unprotected 21 1 write-only TX_PROT No Description 0x48 read-only n 0x0 0x0 NONSEC Non-Secure Access 23 1 read-only PRIV Privileged Access 22 1 read-only UNPROTECTED Unprotected 21 1 read-only USER User Bits 24 8 read-only TX_STATUS No Description 0x40 read-only n 0x0 0x0 BYTEREM Bytes Remaining 0 16 read-only TXERROR TX Error Flag 23 1 read-only TXFULL TX FIFO Full 21 1 read-only TXINT Interrupt Status 20 1 read-only SEMAILBOX_S_HOST SEMAILBOX_S_HOST Registers SEMAILBOX_S_HOST 0x0 0x0 0x1000 registers n CONFIGURATION No Description 0x58 read-write n 0x0 0x0 RXINTEN RX Interrupt Enable 1 1 read-write TXINTEN TX Interrupt Enable 0 1 read-write DATA0 No Description 0x0 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA1 No Description 0x4 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA10 No Description 0x28 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA11 No Description 0x2C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA12 No Description 0x30 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA13 No Description 0x34 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA14 No Description 0x38 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA15 No Description 0x3C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA2 No Description 0x8 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA3 No Description 0xC read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA4 No Description 0x10 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA5 No Description 0x14 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA6 No Description 0x18 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA7 No Description 0x1C read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA8 No Description 0x20 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write DATA9 No Description 0x24 read-write n 0x0 0x0 DATA FIFO Data 0 32 read-write RX_HEADER No Description 0x54 read-only n 0x0 0x0 SIZE SIZE 0 16 read-only STATUS Command Status 16 4 read-only UNPROTECTED Unprotected 21 1 read-only RX_PROT No Description 0x4C read-only n 0x0 0x0 NONSEC Non-Secure Access 23 1 read-only PRIV Privileged Access 22 1 read-only UNPROTECTED Unprotected 21 1 read-only USER User Bits 24 8 read-only RX_STATUS No Description 0x44 read-only n 0x0 0x0 BYTEREM Bytes Remaining 0 16 read-only RXEMPTY RX FIFO Empty 21 1 read-only RXERROR RX Error Flag 23 1 read-only RXHEADER RX Header 22 1 read-only RXINT Interrupt Status 20 1 read-only STATUS Message Status 16 4 read-only TX_HEADER No Description 0x50 write-only n 0x0 0x0 SIZE Command Size 0 16 write-only UNPROTECTED Unprotected 21 1 write-only TX_PROT No Description 0x48 read-only n 0x0 0x0 NONSEC Non-Secure Access 23 1 read-only PRIV Privileged Access 22 1 read-only UNPROTECTED Unprotected 21 1 read-only USER User Bits 24 8 read-only TX_STATUS No Description 0x40 read-only n 0x0 0x0 BYTEREM Bytes Remaining 0 16 read-only TXERROR TX Error Flag 23 1 read-only TXFULL TX FIFO Full 21 1 read-only TXINT Interrupt Status 20 1 read-only SMU_NS SMU_NS Registers SMU_NS 0x0 0x0 0x1000 registers n SMU_SECURE 3 SMU_PRIVILEGED 4 BMPUFS No Description 0x250 read-only n 0x0 0x0 BMPUFSMASTERID Fault 0 8 read-only BMPUFSADDR No Description 0x254 read-only n 0x0 0x0 BMPUFSADDR Fault Address 0 32 read-only BMPUPATD0 No Description 0x150 -1 read-write n 0x0 0x0 BUFC RADIO BUFFER controller privileged mode 2 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RADIOAES RADIO AES DMA privileged mode 0 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 1 1 read-write SEDMA SE mailbox DMA privileged mode 5 1 read-write BMPUSATD0 No Description 0x170 -1 read-write n 0x0 0x0 BUFC RADIO BUFFER controller secure mode 2 1 read-write LDMA MCU LDMA secure mode 4 1 read-write RADIOAES RADIO AES DMA secure mode 0 1 read-write RADIOIFADCDEBUG RADIO IFADC debug secure mode 3 1 read-write RADIOSUBSYSTEM RADIO subsystem masters secure mode 1 1 read-write SEDMA MCU to SE mailbox DMA secure mode 5 1 read-write ESAUMRB01 No Description 0x270 -1 read-write n 0x0 0x0 ESAUMRB01 Moveable Region Boundary 12 16 read-write ESAUMRB12 No Description 0x274 -1 read-write n 0x0 0x0 ESAUMRB12 Moveable Region Boundary 12 16 read-write ESAUMRB45 No Description 0x280 -1 read-write n 0x0 0x0 ESAUMRB45 Moveable Region Boundary 12 16 read-write ESAUMRB56 No Description 0x284 -1 read-write n 0x0 0x0 ESAUMRB56 Moveable Region Boundary 12 16 read-write ESAURTYPES0 No Description 0x260 read-write n 0x0 0x0 ESAUR3NS Region 3 Non-Secure 12 1 read-write ESAURTYPES1 No Description 0x264 read-write n 0x0 0x0 ESAUR11NS Region 11 Non-Secure 12 1 read-write IEN No Description 0x10 read-write n 0x0 0x0 BMPUSEC BMPU Security Interrupt Flag 17 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write IF No Description 0xC read-write n 0x0 0x0 BMPUSEC BMPU Security Interrupt Flag 17 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x8 write-only n 0x0 0x0 SMULOCKKEY None 0 24 write-only UNLOCK Unlocks Registers 11325013 M33CTRL Holds the M33 control settings 0x20 read-write n 0x0 0x0 LOCKNSMPU NSMPU LOCK bit 3 1 read-write LOCKNSVTOR NSVTOR LOCK bit 1 1 read-write LOCKSAU SAU LOCK bit 4 1 read-write LOCKSMPU SMPU LOCK bit 2 1 read-write LOCKSVTAIRCR SVTAIRCR LOCK bit 0 1 read-write PPUFS No Description 0x140 read-only n 0x0 0x0 PPUFSPERIPHID Peripheral I 0 8 read-only PPUPATD0 Set peripheral bits to 1 to mark as privileged access only 0x40 read-write n 0x0 0x0 BURAM BURAM Privileged Access 28 1 read-write BURTC BURTC Privileged Access 23 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write CMU CMU Privileged Access 2 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write EMU EMU Privileged Access 1 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write GPIO GPIO Privileged Access 13 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write LFXO LFXO Privileged Access 7 1 read-write LVGD LVGD Privileged Access 26 1 read-write MSC MSC Privileged Access 10 1 read-write PRS PRS Privileged Access 12 1 read-write RTCC RTCC Privileged Access 31 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write USART0 USART0 Privileged Access 20 1 read-write USART1 USART1 Privileged Access 21 1 read-write USART2 USART2 Privileged Access 22 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only 0x44 read-write n 0x0 0x0 ACMP0 ACMP0 Privileged Access 2 1 read-write ACMP1 ACMP1 Privileged Access 3 1 read-write AHBRADIO AHBRADIO Privileged Access 12 1 read-write AMUXCP0 AMUXCP0 Privileged Access 8 1 read-write BUFC BUFC Privileged Access 10 1 read-write HFRCOEM23 HFRCOEM23 Privileged Access 5 1 read-write I2C0 I2C0 Privileged Access 4 1 read-write IADC0 IADC0 Privileged Access 1 1 read-write LETIMER0 LETIMER0 Privileged Access 0 1 read-write RADIOAES RADIOAES Privileged Access 9 1 read-write SEMAILBOX SE MAILBOX Privileged Access 13 1 read-write SMU SMU Privileged Access 11 1 read-write WDOG0 WDOG0 Privileged Access 6 1 read-write WDOG1 WDOG1 Privileged Access 7 1 read-write PPUSATD0 No Description 0x60 read-write n 0x0 0x0 BURAM BURAM Secure Access 28 1 read-write BURTC BURTC Secure Access 23 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write CMU CMU Secure Access 2 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write EMU EMU Secure Access 1 1 read-write FSRCO FSRCO Secure Access 5 1 read-write GPCRC GPCRC Secure Access 30 1 read-write GPIO GPIO Secure Access 13 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write I2C1 I2C1 Secure Access 24 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write IFADCDEBUG IFADCDEBUG Secure Access 29 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write LFRCO LFRCO Secure Access 8 1 read-write LFXO LFXO Secure Access 7 1 read-write LVGD LVGD Secure Access 26 1 read-write MSC MSC Secure Access 10 1 read-write PRS PRS Secure Access 12 1 read-write RTCC RTCC Secure Access 31 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write USART0 USART0 Secure Access 20 1 read-write USART1 USART1 Secure Access 21 1 read-write USART2 USART2 Secure Access 22 1 read-write PPUSATD1 No Description 0x64 read-write n 0x0 0x0 ACMP0 ACMP0 Secure Access 2 1 read-write ACMP1 ACMP1 Secure Access 3 1 read-write AHBRADIO AHBRADIO Secure Access 12 1 read-write AMUXCP0 AMUXCP0 Secure Access 8 1 read-write BUFC BUFC Secure Access 10 1 read-write HFRCOEM23 HFRCOEM23 Secure Access 5 1 read-write I2C0 I2C0 Secure Access 4 1 read-write IADC0 IADC0 Secure Access 1 1 read-write LETIMER0 LETIMER0 Secure Access 0 1 read-write RADIOAES RADIOAES Secure Access 9 1 read-write SEMAILBOX SE MAILBOX Secure Access 13 1 read-write SMU SMU Secure Access 11 1 read-write WDOG0 WDOG0 Secure Access 6 1 read-write WDOG1 WDOG1 Secure Access 7 1 read-write STATUS No Description 0x4 read-only n 0x0 0x0 SMULOCK SMU Lock 0 1 read-only UNLOCKED 0 LOCKED 1 SMUPRGERR SMU Programming Error 1 1 read-only SMU_S SMU_S Registers SMU_S 0x0 0x0 0x1000 registers n SMU_SECURE 3 SMU_PRIVILEGED 4 BMPUFS No Description 0x250 read-only n 0x0 0x0 BMPUFSMASTERID Fault 0 8 read-only BMPUFSADDR No Description 0x254 read-only n 0x0 0x0 BMPUFSADDR Fault Address 0 32 read-only BMPUPATD0 No Description 0x150 -1 read-write n 0x0 0x0 BUFC RADIO BUFFER controller privileged mode 2 1 read-write LDMA MCU LDMA privileged mode 4 1 read-write RADIOAES RADIO AES DMA privileged mode 0 1 read-write RADIOIFADCDEBUG RADIO IFADC debug privileged mode 3 1 read-write RADIOSUBSYSTEM RADIO subsystem masters privileged mode 1 1 read-write SEDMA SE mailbox DMA privileged mode 5 1 read-write BMPUSATD0 No Description 0x170 -1 read-write n 0x0 0x0 BUFC RADIO BUFFER controller secure mode 2 1 read-write LDMA MCU LDMA secure mode 4 1 read-write RADIOAES RADIO AES DMA secure mode 0 1 read-write RADIOIFADCDEBUG RADIO IFADC debug secure mode 3 1 read-write RADIOSUBSYSTEM RADIO subsystem masters secure mode 1 1 read-write SEDMA MCU to SE mailbox DMA secure mode 5 1 read-write ESAUMRB01 No Description 0x270 -1 read-write n 0x0 0x0 ESAUMRB01 Moveable Region Boundary 12 16 read-write ESAUMRB12 No Description 0x274 -1 read-write n 0x0 0x0 ESAUMRB12 Moveable Region Boundary 12 16 read-write ESAUMRB45 No Description 0x280 -1 read-write n 0x0 0x0 ESAUMRB45 Moveable Region Boundary 12 16 read-write ESAUMRB56 No Description 0x284 -1 read-write n 0x0 0x0 ESAUMRB56 Moveable Region Boundary 12 16 read-write ESAURTYPES0 No Description 0x260 read-write n 0x0 0x0 ESAUR3NS Region 3 Non-Secure 12 1 read-write ESAURTYPES1 No Description 0x264 read-write n 0x0 0x0 ESAUR11NS Region 11 Non-Secure 12 1 read-write IEN No Description 0x10 read-write n 0x0 0x0 BMPUSEC BMPU Security Interrupt Flag 17 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write IF No Description 0xC read-write n 0x0 0x0 BMPUSEC BMPU Security Interrupt Flag 17 1 read-write PPUINST PPU Instruction Interrupt Flag 2 1 read-write PPUPRIV PPU Privilege Interrupt Flag 0 1 read-write PPUSEC PPU Security Interrupt Flag 16 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x8 write-only n 0x0 0x0 SMULOCKKEY None 0 24 write-only UNLOCK Unlocks Registers 11325013 M33CTRL Holds the M33 control settings 0x20 read-write n 0x0 0x0 LOCKNSMPU NSMPU LOCK bit 3 1 read-write LOCKNSVTOR NSVTOR LOCK bit 1 1 read-write LOCKSAU SAU LOCK bit 4 1 read-write LOCKSMPU SMPU LOCK bit 2 1 read-write LOCKSVTAIRCR SVTAIRCR LOCK bit 0 1 read-write PPUFS No Description 0x140 read-only n 0x0 0x0 PPUFSPERIPHID Peripheral I 0 8 read-only PPUPATD0 Set peripheral bits to 1 to mark as privileged access only 0x40 read-write n 0x0 0x0 BURAM BURAM Privileged Access 28 1 read-write BURTC BURTC Privileged Access 23 1 read-write CHIPTESTCTRL CHIPTESTCTRL Privileged Access 25 1 read-write CMU CMU Privileged Access 2 1 read-write DPLL0 DPLL0 Privileged Access 6 1 read-write EMU EMU Privileged Access 1 1 read-write FSRCO FSRCO Privileged Access 5 1 read-write GPCRC GPCRC Privileged Access 30 1 read-write GPIO GPIO Privileged Access 13 1 read-write HFRCO0 HFRCO0 Privileged Access 4 1 read-write HFXO0 HFXO0 Privileged Access 3 1 read-write I2C1 I2C1 Privileged Access 24 1 read-write ICACHE0 ICACHE0 Privileged Access 11 1 read-write IFADCDEBUG IFADCDEBUG Privileged Access 29 1 read-write LDMA LDMA Privileged Access 14 1 read-write LDMAXBAR LDMAXBAR Privileged Access 15 1 read-write LFRCO LFRCO Privileged Access 8 1 read-write LFXO LFXO Privileged Access 7 1 read-write LVGD LVGD Privileged Access 26 1 read-write MSC MSC Privileged Access 10 1 read-write PRS PRS Privileged Access 12 1 read-write RTCC RTCC Privileged Access 31 1 read-write SYSCFG SYSCFG Privileged Access 27 1 read-write TIMER0 TIMER0 Privileged Access 16 1 read-write TIMER1 TIMER1 Privileged Access 17 1 read-write TIMER2 TIMER2 Privileged Access 18 1 read-write TIMER3 TIMER3 Privileged Access 19 1 read-write ULFRCO ULFRCO Privileged Access 9 1 read-write USART0 USART0 Privileged Access 20 1 read-write USART1 USART1 Privileged Access 21 1 read-write USART2 USART2 Privileged Access 22 1 read-write PPUPATD1 Set peripheral bits to 1 to mark as privileged access only 0x44 read-write n 0x0 0x0 ACMP0 ACMP0 Privileged Access 2 1 read-write ACMP1 ACMP1 Privileged Access 3 1 read-write AHBRADIO AHBRADIO Privileged Access 12 1 read-write AMUXCP0 AMUXCP0 Privileged Access 8 1 read-write BUFC BUFC Privileged Access 10 1 read-write HFRCOEM23 HFRCOEM23 Privileged Access 5 1 read-write I2C0 I2C0 Privileged Access 4 1 read-write IADC0 IADC0 Privileged Access 1 1 read-write LETIMER0 LETIMER0 Privileged Access 0 1 read-write RADIOAES RADIOAES Privileged Access 9 1 read-write SEMAILBOX SE MAILBOX Privileged Access 13 1 read-write SMU SMU Privileged Access 11 1 read-write WDOG0 WDOG0 Privileged Access 6 1 read-write WDOG1 WDOG1 Privileged Access 7 1 read-write PPUSATD0 No Description 0x60 read-write n 0x0 0x0 BURAM BURAM Secure Access 28 1 read-write BURTC BURTC Secure Access 23 1 read-write CHIPTESTCTRL CHIPTESTCTRL Secure Access 25 1 read-write CMU CMU Secure Access 2 1 read-write DPLL0 DPLL0 Secure Access 6 1 read-write EMU EMU Secure Access 1 1 read-write FSRCO FSRCO Secure Access 5 1 read-write GPCRC GPCRC Secure Access 30 1 read-write GPIO GPIO Secure Access 13 1 read-write HFRCO0 HFRCO0 Secure Access 4 1 read-write HFXO0 HFXO0 Secure Access 3 1 read-write I2C1 I2C1 Secure Access 24 1 read-write ICACHE0 ICACHE0 Secure Access 11 1 read-write IFADCDEBUG IFADCDEBUG Secure Access 29 1 read-write LDMA LDMA Secure Access 14 1 read-write LDMAXBAR LDMAXBAR Secure Access 15 1 read-write LFRCO LFRCO Secure Access 8 1 read-write LFXO LFXO Secure Access 7 1 read-write LVGD LVGD Secure Access 26 1 read-write MSC MSC Secure Access 10 1 read-write PRS PRS Secure Access 12 1 read-write RTCC RTCC Secure Access 31 1 read-write SYSCFG SYSCFG Secure Access 27 1 read-write TIMER0 TIMER0 Secure Access 16 1 read-write TIMER1 TIMER1 Secure Access 17 1 read-write TIMER2 TIMER2 Secure Access 18 1 read-write TIMER3 TIMER3 Secure Access 19 1 read-write ULFRCO ULFRCO Secure Access 9 1 read-write USART0 USART0 Secure Access 20 1 read-write USART1 USART1 Secure Access 21 1 read-write USART2 USART2 Secure Access 22 1 read-write PPUSATD1 No Description 0x64 read-write n 0x0 0x0 ACMP0 ACMP0 Secure Access 2 1 read-write ACMP1 ACMP1 Secure Access 3 1 read-write AHBRADIO AHBRADIO Secure Access 12 1 read-write AMUXCP0 AMUXCP0 Secure Access 8 1 read-write BUFC BUFC Secure Access 10 1 read-write HFRCOEM23 HFRCOEM23 Secure Access 5 1 read-write I2C0 I2C0 Secure Access 4 1 read-write IADC0 IADC0 Secure Access 1 1 read-write LETIMER0 LETIMER0 Secure Access 0 1 read-write RADIOAES RADIOAES Secure Access 9 1 read-write SEMAILBOX SE MAILBOX Secure Access 13 1 read-write SMU SMU Secure Access 11 1 read-write WDOG0 WDOG0 Secure Access 6 1 read-write WDOG1 WDOG1 Secure Access 7 1 read-write STATUS No Description 0x4 read-only n 0x0 0x0 SMULOCK SMU Lock 0 1 read-only UNLOCKED 0 LOCKED 1 SMUPRGERR SMU Programming Error 1 1 read-only SYNTH_NS SYNTH_NS Registers SYNTH_NS 0x0 0x0 0x1000 registers n SYNTH 40 CALOFFSET No Description 0x48 read-write n 0x0 0x0 CALOFFSET Carrier calibration offset 0 15 read-write CHCTRL No Description 0x40 read-write n 0x0 0x0 CHNO Channel number 0 6 read-write CHPDACINIT No Description 0x98 read-write n 0x0 0x0 DACINIT Initial CHP DAC Value 0 12 read-write CHSP No Description 0x44 read-write n 0x0 0x0 CHSP Channel spacing 0 18 read-write CMD No Description 0xC write-only n 0x0 0x0 CAPCALSTART Start VCO capacitor array calibration 4 1 write-only DISABLEIF Disable the synthesizer IF frequency 3 1 write-only ENABLEIF Enable the synthesizer IF frequency 2 1 write-only SYNTHSTART Starts the RF synthesizer 0 1 write-only SYNTHSTOP Stops the RF synthesizer 1 1 write-only CTRL No Description 0x10 -1 read-write n 0x0 0x0 LOCKTHRESHOLD Frequency synthesizer lock threshold 0 3 read-write MMDMANRSTN Manual MMD reset 31 1 read-write RESET Reset MMD and DSM logic 0 NORESET Allow MMD and DSM to run 1 MMDRSTNOVERRIDEEN Enable MMD reset override 30 1 read-write DISABLE Disable MMD reset override 0 ENABLE Enable MMD reset override 1 PRSMUX0 PRS output mux 0 selector 16 3 read-write DISABLED PRS output 0 is disabled 0 INLOCK Synthesizer is in lock 1 LOCK_WINDOW PLL Lock Window, sampled by PFD 2 FPLL Divided PLL clock 3 VCCMP_HI VCO voltage high detected 4 VCO_AMPLITUDE_OK Obsolete. Read returns 1. 5 VCO_DET_OUT_D Obsolete. Read returns 0. 6 PRSMUX1 PRS output mux 1 selector 20 3 read-write DISABLED PRS output 1 is disabled 0 AUXINLOCK Obsolete. read returns 0. 1 REF_IS_LEADING Disabled. Read returns 0. 2 FPLL Divided PLL clock 3 VCCMP_LOW VCO voltage low detected 4 MMD_PRESCALER_RESET_N MMD prescaler reset, active low 5 CLK_SYNTH_DIV2 MMD next denom output, corresponding to the delta-sigma clock, divided by 2. 6 DIVCTRL No Description 0x3C -1 read-write n 0x0 0x0 LODIVFREQCTRL Frequency division 0 9 read-write LODIV1 Divide LO frequency by 1. 1 LODIV18 Divide LO frequency by 18. 155 LODIV24 Divide LO frequency by 24. 156 LODIV6 Divide LO frequency by 6. 19 LODIV2 Divide LO frequency by 2. 2 LODIV8 Divide LO frequency by 8. 20 LODIV10 Divide LO frequency by 10. 21 LODIV14 Divide LO frequency by 14. 23 LODIV9 Divide LO frequency by 9. 27 LODIV12 Divide LO frequency by 12. 28 LODIV15 Divide LO frequency by 15. 29 LODIV3 Divide LO frequency by 3. 3 LODIV16 Divide LO frequency by 16. 36 LODIV20 Divide LO frequency by 20. 37 LODIV4 Divide LO frequency by 4. 4 LODIV5 Divide LO frequency by 5. 5 LODIV7 Divide LO frequency by 7. 7 DSMCTRLRX No Description 0xB0 -1 read-write n 0x0 0x0 DEMMODERX DEM Mode for RX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 DITHERDACRX Dithering of charge pump DAC for RX mode 4 4 read-write DITHERDSMINPUTRX Dithering of DSM input for RX mode 0 1 read-write DITHERDSMOUTPUTRX Dithering of DSM output for RX mode 1 3 read-write DSMMODERX Delta-sigma topology for RX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCERX Delta-sigma input force LSB for RX mode 9 1 read-write MASHORDERRX MASH order for RX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERRX ReQuant order for RX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 DSMCTRLTX No Description 0xB4 -1 read-write n 0x0 0x0 DEMMODETX DEM Mode for TX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 DITHERDACTX Dithering of charge pump DAC for TX mode 4 4 read-write DITHERDSMINPUTTX Dithering of DSM input for TX mode 0 1 read-write DITHERDSMOUTPUTTX Dithering of DSM output for TX mode 1 3 read-write DSMMODETX Delta-sigma topology for TX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCETX Delta-sigma input force LSB for TX mode 9 1 read-write MASHORDERTX MASH order for TX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERTX ReQuant order for TX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FREQ No Description 0x34 read-write n 0x0 0x0 FREQ RF Carrier Frequency. 0 28 read-write IEN No Description 0x84 read-write n 0x0 0x0 CAPCALDONE CAPCALDONE Interrupt Enable 2 1 read-write LOCKED LOCKED Interrupt Enable 0 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write IF No Description 0x78 read-write n 0x0 0x0 CAPCALDONE Capacitor calibration Interrupt Flag 2 1 read-write LOCKED Synthesizer locked Interrupt Flag 0 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write IFFREQ No Description 0x38 read-write n 0x0 0x0 IFFREQ IF used in receive mode 0 20 read-write LOSIDE Configure LO in receive 20 1 read-write LOW The local oscillator (LO) is lower in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to NORMAL and DIGIQSWAPEN must be cleared. 0 HIGH The local oscillator (LO) is higher in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to CONJUGATE and DIGIQSWAPEN must be set. 1 IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCNTCTRL No Description 0x88 read-write n 0x0 0x0 CLEAR Clear LO Counter 1 1 write-only OFF Do not clear LO counter 0 ON Clear LO counter 1 ENABLE Enable LO Counter 0 1 read-write OFF LO counter is disabled 0 ON LO counter is enabled 1 LOCNTMANCLEAR Manual Control of LO counter CLEAR 9 1 read-write NOCLEAR Don't clear LO counter 0 CLEAR Clear LO counter 1 LOCNTMANRUN Manual Control of the LO counter RUN 10 1 read-write NORUN Don't initiate start/stop LO counter 0 RUN Initiate start/stop of LO counter 1 LOCNTOVERRIDEEN Enable manual override of CLEAR and RUN 8 1 read-write DISABLE Disable manual override 0 ENABLE Enable manual override 1 NUMCYCLE Number of Clock Cycles to Run LO Counter 4 4 read-write CNT_2 Set count length to 2 XO clock cycles 0 CNT_4 Set count length to 4 XO clock cycles 1 CNT_2048 Set count length to 2048 XO clock cycles 10 CNT_4096 Set count length to 4096 XO clock cycles 11 CNT_8192 Set count length to 8192 XO clock cycles 12 CNT_8 Set count length to 8 XO clock cycles 2 CNT_16 Set count length to 16 XO clock cycles 3 CNT_32 Set count length to 32 XO clock cycles 4 CNT_64 Set count length to 64 XO clock cycles 5 CNT_128 Set count length to 128 XO clock cycles 6 CNT_256 Set count length to 256 XO clock cycles 7 CNT_512 Set count length to 512 XO clock cycles 8 CNT_1024 Set count length to 1024 XO clock cycles 9 READ Read LO Counter 3 1 read-write OFF LOCOUNT register read returns all 0's 0 ON LOCOUNT register read returns count value 1 RUN Run LO Counter 2 1 write-only OFF Do not run LO counter 0 ON Run LO counter 1 LOCNTSTATUS No Description 0x8C read-only n 0x0 0x0 BUSY LO Counter is Busy 19 1 read-only LOCOUNT LO Counter Value 0 19 read-only LOCNTTARGET No Description 0x90 read-only n 0x0 0x0 TARGET LO Counter Measurement Target 0 19 read-only LPFCTRL1CAL No Description 0x9C read-write n 0x0 0x0 OP1BWCAL LPF Op1 BW Control in Cal Mode 0 4 read-write OP1COMPCAL LPF Op1 Comp Control in Cal Mode 4 4 read-write RFBVALCAL LPF Rfb Value Select in Cal Mode 8 3 read-write RPVALCAL LPF Rp Value Select in Cal Mode 11 3 read-write RZVALCAL LPF Rz Value Select in Cal Mode 14 4 read-write LPFCTRL1RX No Description 0xA0 read-write n 0x0 0x0 OP1BWRX LPF Op1 BW Control in RX Mode 0 4 read-write OP1COMPRX LPF Op1 Comp Control in RX Mode 4 4 read-write RFBVALRX LPF Rfb Value Select in RX Mode 8 3 read-write RPVALRX LPF Rp Value Select in RX Mode 11 3 read-write RZVALRX LPF Rz Value Select in RX Mode 14 4 read-write LPFCTRL1TX No Description 0xA4 read-write n 0x0 0x0 OP1BWTX LPF Op1 BW Control in TX Mode 0 4 read-write OP1COMPTX LPF Op1 Comp Control in TX Mode 4 4 read-write RFBVALTX LPF Rfb Value Select in TX Mode 8 3 read-write RPVALTX LPF Rp Value Select in TX Mode 11 3 read-write RZVALTX LPF Rz Value Select in TX Mode 14 4 read-write LPFCTRL2RX No Description 0xA8 read-write n 0x0 0x0 CALCRX LPF Cap Cal Select in RX Mode 4 5 read-write CASELRX LPF Ca Select in RX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALRX LPF Ca Value Select in RX Mode 10 5 read-write CFBSELRX LPF Cfb Select in RX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELRX LPF Cz Select in RX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALRX LPF Cz Value Select in RX Mode 17 8 read-write LPFGNDSWENRX LPF Gnd Switch Enable in RX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 LPFINCAPRX LPF Input Cap Select in RX Mode 1 2 read-write LPFSWENRX LPF Switching Enable in RX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 MODESELRX LPF Filter Mode Select in RX Mode 25 1 read-write ONEOP Sets 1 opamp configuration 0 TWOOP Sets 2 opamp configuration 1 VCMLVLRX LPF Vcm Level Select in RX Mode 26 3 read-write LPFCTRL2TX No Description 0xAC read-write n 0x0 0x0 CALCTX LPF Cap Cal Select in TX Mode 4 5 read-write CASELTX LPF Ca Select in TX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALTX LPF Ca Value Select in TX Mode 10 5 read-write CFBSELTX LPF Cfb Select in TX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELTX LPF Cz Select in TX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALTX LPF Cz Value Select in TX Mode 17 8 read-write LPFGNDSWENTX LPF Gnd Switch Enable in TX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 LPFINCAPTX LPF Input Cap Select in TX Mode 1 2 read-write LPFSWENTX LPF Switching Enable in TX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 MODESELTX LPF Filter Mode Select in TX Mode 25 1 read-write ONEOP 1 opamp configuration 0 TWOOP 2 opamp configuration 1 VCMLVLTX LPF Vcm Level Select in TX Mode 26 3 read-write MMDDENOMINIT No Description 0x94 read-write n 0x0 0x0 DENOMINIT0 New BitField 0 9 read-write DENOMINIT1 New BitField 9 9 read-write DENOMINIT2 New BitField 18 9 read-write STATUS No Description 0x8 read-only n 0x0 0x0 IFFREQEN Synthesizer IF frequency enable status 1 1 read-only INLOCK RF Synthesizer in Lock 0 1 read-only VCDACCTRL No Description 0x2C -1 read-write n 0x0 0x0 LPFEN LPF Enable Control 7 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 LPFQSEN LPF Quickstart Control 8 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 VCDACEN Enable VCDAC 6 1 read-write DISABLE VC DAC disabled 0 ENABLE VC DAC enabled 1 VCDACVAL Control voltage to VCO 0 6 read-write VCOGAIN No Description 0x58 -1 read-write n 0x0 0x0 VCOKVCOARSE VCO varactor coarse gain setting 0 4 read-write VCOKVFINE VCO varactor fine gain setting 4 4 read-write VCOTUNING No Description 0x4C -1 read-write n 0x0 0x0 VCAPSEL VCO varactor cap select 11 5 read-write VCOTUNING VCO capacitor array calibration value. 0 11 read-write SYNTH_S SYNTH_S Registers SYNTH_S 0x0 0x0 0x1000 registers n SYNTH 40 CALOFFSET No Description 0x48 read-write n 0x0 0x0 CALOFFSET Carrier calibration offset 0 15 read-write CHCTRL No Description 0x40 read-write n 0x0 0x0 CHNO Channel number 0 6 read-write CHPDACINIT No Description 0x98 read-write n 0x0 0x0 DACINIT Initial CHP DAC Value 0 12 read-write CHSP No Description 0x44 read-write n 0x0 0x0 CHSP Channel spacing 0 18 read-write CMD No Description 0xC write-only n 0x0 0x0 CAPCALSTART Start VCO capacitor array calibration 4 1 write-only DISABLEIF Disable the synthesizer IF frequency 3 1 write-only ENABLEIF Enable the synthesizer IF frequency 2 1 write-only SYNTHSTART Starts the RF synthesizer 0 1 write-only SYNTHSTOP Stops the RF synthesizer 1 1 write-only CTRL No Description 0x10 -1 read-write n 0x0 0x0 LOCKTHRESHOLD Frequency synthesizer lock threshold 0 3 read-write MMDMANRSTN Manual MMD reset 31 1 read-write RESET Reset MMD and DSM logic 0 NORESET Allow MMD and DSM to run 1 MMDRSTNOVERRIDEEN Enable MMD reset override 30 1 read-write DISABLE Disable MMD reset override 0 ENABLE Enable MMD reset override 1 PRSMUX0 PRS output mux 0 selector 16 3 read-write DISABLED PRS output 0 is disabled 0 INLOCK Synthesizer is in lock 1 LOCK_WINDOW PLL Lock Window, sampled by PFD 2 FPLL Divided PLL clock 3 VCCMP_HI VCO voltage high detected 4 VCO_AMPLITUDE_OK Obsolete. Read returns 1. 5 VCO_DET_OUT_D Obsolete. Read returns 0. 6 PRSMUX1 PRS output mux 1 selector 20 3 read-write DISABLED PRS output 1 is disabled 0 AUXINLOCK Obsolete. read returns 0. 1 REF_IS_LEADING Disabled. Read returns 0. 2 FPLL Divided PLL clock 3 VCCMP_LOW VCO voltage low detected 4 MMD_PRESCALER_RESET_N MMD prescaler reset, active low 5 CLK_SYNTH_DIV2 MMD next denom output, corresponding to the delta-sigma clock, divided by 2. 6 DIVCTRL No Description 0x3C -1 read-write n 0x0 0x0 LODIVFREQCTRL Frequency division 0 9 read-write LODIV1 Divide LO frequency by 1. 1 LODIV18 Divide LO frequency by 18. 155 LODIV24 Divide LO frequency by 24. 156 LODIV6 Divide LO frequency by 6. 19 LODIV2 Divide LO frequency by 2. 2 LODIV8 Divide LO frequency by 8. 20 LODIV10 Divide LO frequency by 10. 21 LODIV14 Divide LO frequency by 14. 23 LODIV9 Divide LO frequency by 9. 27 LODIV12 Divide LO frequency by 12. 28 LODIV15 Divide LO frequency by 15. 29 LODIV3 Divide LO frequency by 3. 3 LODIV16 Divide LO frequency by 16. 36 LODIV20 Divide LO frequency by 20. 37 LODIV4 Divide LO frequency by 4. 4 LODIV5 Divide LO frequency by 5. 5 LODIV7 Divide LO frequency by 7. 7 DSMCTRLRX No Description 0xB0 -1 read-write n 0x0 0x0 DEMMODERX DEM Mode for RX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 DITHERDACRX Dithering of charge pump DAC for RX mode 4 4 read-write DITHERDSMINPUTRX Dithering of DSM input for RX mode 0 1 read-write DITHERDSMOUTPUTRX Dithering of DSM output for RX mode 1 3 read-write DSMMODERX Delta-sigma topology for RX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCERX Delta-sigma input force LSB for RX mode 9 1 read-write MASHORDERRX MASH order for RX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERRX ReQuant order for RX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 DSMCTRLTX No Description 0xB4 -1 read-write n 0x0 0x0 DEMMODETX DEM Mode for TX mode 24 1 read-write DISABLED DEM is disabled 0 ENABLED DEM is enabled 1 DITHERDACTX Dithering of charge pump DAC for TX mode 4 4 read-write DITHERDSMINPUTTX Dithering of DSM input for TX mode 0 1 read-write DITHERDSMOUTPUTTX Dithering of DSM output for TX mode 1 3 read-write DSMMODETX Delta-sigma topology for TX mode 8 1 read-write FEEDFORWARD Feed forward architecture 0 MASH MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode. 1 LSBFORCETX Delta-sigma input force LSB for TX mode 9 1 read-write MASHORDERTX MASH order for TX mode 25 1 read-write SECOND 2nd Order Mash 0 THIRD 3rd Order Mash 1 REQORDERTX ReQuant order for TX mode 26 1 read-write FIRST 1st Order DAC 0 SECOND 2rd Order DAC 1 EN No Description 0x4 read-write n 0x0 0x0 EN Enable peripheral clock to this module 0 1 read-write FREQ No Description 0x34 read-write n 0x0 0x0 FREQ RF Carrier Frequency. 0 28 read-write IEN No Description 0x84 read-write n 0x0 0x0 CAPCALDONE CAPCALDONE Interrupt Enable 2 1 read-write LOCKED LOCKED Interrupt Enable 0 1 read-write LOCNTDONE LOCNTDONE Interrupt Enable 9 1 read-write UNLOCKED UNLOCKED Interrupt Enable 1 1 read-write VCOHIGH VCOHIGH Interrupt Enable 4 1 read-write VCOLOW VCOLOW Interrupt Enable 5 1 read-write IF No Description 0x78 read-write n 0x0 0x0 CAPCALDONE Capacitor calibration Interrupt Flag 2 1 read-write LOCKED Synthesizer locked Interrupt Flag 0 1 read-write LOCNTDONE LOCNT measurement done Interrupt Flag 9 1 read-write UNLOCKED Synthesizer unlocked Interrupt Flag 1 1 read-write VCOHIGH VCO high voltage Interrupt Flag 4 1 read-write VCOLOW VCO low voltage Interrupt Flag 5 1 read-write IFFREQ No Description 0x38 read-write n 0x0 0x0 IFFREQ IF used in receive mode 0 20 read-write LOSIDE Configure LO in receive 20 1 read-write LOW The local oscillator (LO) is lower in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to NORMAL and DIGIQSWAPEN must be cleared. 0 HIGH The local oscillator (LO) is higher in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to CONJUGATE and DIGIQSWAPEN must be set. 1 IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCNTCTRL No Description 0x88 read-write n 0x0 0x0 CLEAR Clear LO Counter 1 1 write-only OFF Do not clear LO counter 0 ON Clear LO counter 1 ENABLE Enable LO Counter 0 1 read-write OFF LO counter is disabled 0 ON LO counter is enabled 1 LOCNTMANCLEAR Manual Control of LO counter CLEAR 9 1 read-write NOCLEAR Don't clear LO counter 0 CLEAR Clear LO counter 1 LOCNTMANRUN Manual Control of the LO counter RUN 10 1 read-write NORUN Don't initiate start/stop LO counter 0 RUN Initiate start/stop of LO counter 1 LOCNTOVERRIDEEN Enable manual override of CLEAR and RUN 8 1 read-write DISABLE Disable manual override 0 ENABLE Enable manual override 1 NUMCYCLE Number of Clock Cycles to Run LO Counter 4 4 read-write CNT_2 Set count length to 2 XO clock cycles 0 CNT_4 Set count length to 4 XO clock cycles 1 CNT_2048 Set count length to 2048 XO clock cycles 10 CNT_4096 Set count length to 4096 XO clock cycles 11 CNT_8192 Set count length to 8192 XO clock cycles 12 CNT_8 Set count length to 8 XO clock cycles 2 CNT_16 Set count length to 16 XO clock cycles 3 CNT_32 Set count length to 32 XO clock cycles 4 CNT_64 Set count length to 64 XO clock cycles 5 CNT_128 Set count length to 128 XO clock cycles 6 CNT_256 Set count length to 256 XO clock cycles 7 CNT_512 Set count length to 512 XO clock cycles 8 CNT_1024 Set count length to 1024 XO clock cycles 9 READ Read LO Counter 3 1 read-write OFF LOCOUNT register read returns all 0's 0 ON LOCOUNT register read returns count value 1 RUN Run LO Counter 2 1 write-only OFF Do not run LO counter 0 ON Run LO counter 1 LOCNTSTATUS No Description 0x8C read-only n 0x0 0x0 BUSY LO Counter is Busy 19 1 read-only LOCOUNT LO Counter Value 0 19 read-only LOCNTTARGET No Description 0x90 read-only n 0x0 0x0 TARGET LO Counter Measurement Target 0 19 read-only LPFCTRL1CAL No Description 0x9C read-write n 0x0 0x0 OP1BWCAL LPF Op1 BW Control in Cal Mode 0 4 read-write OP1COMPCAL LPF Op1 Comp Control in Cal Mode 4 4 read-write RFBVALCAL LPF Rfb Value Select in Cal Mode 8 3 read-write RPVALCAL LPF Rp Value Select in Cal Mode 11 3 read-write RZVALCAL LPF Rz Value Select in Cal Mode 14 4 read-write LPFCTRL1RX No Description 0xA0 read-write n 0x0 0x0 OP1BWRX LPF Op1 BW Control in RX Mode 0 4 read-write OP1COMPRX LPF Op1 Comp Control in RX Mode 4 4 read-write RFBVALRX LPF Rfb Value Select in RX Mode 8 3 read-write RPVALRX LPF Rp Value Select in RX Mode 11 3 read-write RZVALRX LPF Rz Value Select in RX Mode 14 4 read-write LPFCTRL1TX No Description 0xA4 read-write n 0x0 0x0 OP1BWTX LPF Op1 BW Control in TX Mode 0 4 read-write OP1COMPTX LPF Op1 Comp Control in TX Mode 4 4 read-write RFBVALTX LPF Rfb Value Select in TX Mode 8 3 read-write RPVALTX LPF Rp Value Select in TX Mode 11 3 read-write RZVALTX LPF Rz Value Select in TX Mode 14 4 read-write LPFCTRL2RX No Description 0xA8 read-write n 0x0 0x0 CALCRX LPF Cap Cal Select in RX Mode 4 5 read-write CASELRX LPF Ca Select in RX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALRX LPF Ca Value Select in RX Mode 10 5 read-write CFBSELRX LPF Cfb Select in RX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELRX LPF Cz Select in RX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALRX LPF Cz Value Select in RX Mode 17 8 read-write LPFGNDSWENRX LPF Gnd Switch Enable in RX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 LPFINCAPRX LPF Input Cap Select in RX Mode 1 2 read-write LPFSWENRX LPF Switching Enable in RX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 MODESELRX LPF Filter Mode Select in RX Mode 25 1 read-write ONEOP Sets 1 opamp configuration 0 TWOOP Sets 2 opamp configuration 1 VCMLVLRX LPF Vcm Level Select in RX Mode 26 3 read-write LPFCTRL2TX No Description 0xAC read-write n 0x0 0x0 CALCTX LPF Cap Cal Select in TX Mode 4 5 read-write CASELTX LPF Ca Select in TX Mode 9 1 read-write DISABLE Disable Ca 0 ENABLE Enable Ca 1 CAVALTX LPF Ca Value Select in TX Mode 10 5 read-write CFBSELTX LPF Cfb Select in TX Mode 15 1 read-write DISABLE Disable Cfb 0 ENABLE Enable Cfb 1 CZSELTX LPF Cz Select in TX Mode 16 1 read-write DISABLE Disable Cz 0 ENABLE Enable Cz 1 CZVALTX LPF Cz Value Select in TX Mode 17 8 read-write LPFGNDSWENTX LPF Gnd Switch Enable in TX Mode 3 1 read-write DISABLE Disable GND switching 0 ENABLE Enable GND switching 1 LPFINCAPTX LPF Input Cap Select in TX Mode 1 2 read-write LPFSWENTX LPF Switching Enable in TX Mode 0 1 read-write DISABLE Disable switching 0 ENABLE Enable switching 1 MODESELTX LPF Filter Mode Select in TX Mode 25 1 read-write ONEOP 1 opamp configuration 0 TWOOP 2 opamp configuration 1 VCMLVLTX LPF Vcm Level Select in TX Mode 26 3 read-write MMDDENOMINIT No Description 0x94 read-write n 0x0 0x0 DENOMINIT0 New BitField 0 9 read-write DENOMINIT1 New BitField 9 9 read-write DENOMINIT2 New BitField 18 9 read-write STATUS No Description 0x8 read-only n 0x0 0x0 IFFREQEN Synthesizer IF frequency enable status 1 1 read-only INLOCK RF Synthesizer in Lock 0 1 read-only VCDACCTRL No Description 0x2C -1 read-write n 0x0 0x0 LPFEN LPF Enable Control 7 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 LPFQSEN LPF Quickstart Control 8 1 read-write DISABLE Disable LPF 0 ENABLE Enable LPF 1 VCDACEN Enable VCDAC 6 1 read-write DISABLE VC DAC disabled 0 ENABLE VC DAC enabled 1 VCDACVAL Control voltage to VCO 0 6 read-write VCOGAIN No Description 0x58 -1 read-write n 0x0 0x0 VCOKVCOARSE VCO varactor coarse gain setting 0 4 read-write VCOKVFINE VCO varactor fine gain setting 4 4 read-write VCOTUNING No Description 0x4C -1 read-write n 0x0 0x0 VCAPSEL VCO varactor cap select 11 5 read-write VCOTUNING VCO capacitor array calibration value. 0 11 read-write SYSCFG_NS SYSCFG_NS Registers SYSCFG_NS 0x0 0x0 0x1000 registers n SYSCFG 20 SW0 53 SW1 54 SW2 55 SW3 56 CFGSYSTIC No Description 0x24 -1 read-write n 0x0 0x0 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CHIPREV No Description 0x14 read-write n 0x0 0x0 FAMILY Part Family value 6 6 read-write MAJOR Part Revision Major value 0 6 read-write MINOR Part Revision Minor value 12 8 read-write CHIPREVHW No Description 0x10 read-write n 0x0 0x0 FAMILY Chip Family value 6 6 read-write MAJOR Chip Rev Major value 0 6 read-write MINOR Chip Rev Minor value 12 8 read-write CTRL No Description 0x200 -1 read-write n 0x0 0x0 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0ECCADDR No Description 0x210 read-only n 0x0 0x0 DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL No Description 0x214 read-write n 0x0 0x0 RAMECCCHKEN RAM ECC Check Enable 1 1 read-write RAMECCEWEN RAM ECC Write Enable 0 1 read-write DMEM0RAMCTRL No Description 0x218 read-write n 0x0 0x0 RAMCACHEEN RAM CACHE Enable 0 1 read-write RAMPREFETCHEN RAM Prfetch Enable 2 1 read-write RAMWSEN RAM WAIT STATE Enable 1 1 read-write DMEM0RETNCTRL No Description 0x208 read-write n 0x0 0x0 RAMRETNCTRL DMEM0 blockset retention control 0 5 read-write ALLON None of the RAM blocks powered down 0 BLK5 Power down RAM block 5 (address range 0x20014000-0x20017FFF) 16 BLK4TO5 Power down RAM blocks 4 and above (address range 0x20010000-0x20017FFF) 24 BLK3TO5 Power down RAM blocks 3 and above (address range 0x2000C000-0x20017FFF) 28 BLK2TO5 Power down RAM blocks 2 and above (address range 0x20008000-0x20017FFF) 30 BLK1TO5 Power down RAM blocks 1 and above (address range 0x20004000-0x20017FFF) 31 FRCRAMECCADDR No Description 0x414 read-only n 0x0 0x0 FRCRAMECCADDR FRCRAM ECC Error Address 0 32 read-only IEN No Description 0x4 read-write n 0x0 0x0 FRCRAMERR1BIEN FRCRAM 1-bit ECC Error Interrupt enable 28 1 read-write FRCRAMERR2BIEN FRCRAM 2-bit ECC Error Interrupt enable 29 1 read-write RAMERR1B RAM 1-bit ECC Error Interrupt enable 16 1 read-write RAMERR2B RAM 2-bit ECC Error Interrupt enable 17 1 read-write SEQRAMERR1B SEQRAM 1-bit ECC Error Interrupt enable 24 1 read-write SEQRAMERR2B SEQRAM 2-bit ECC Error Interrupt enable 25 1 read-write SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write IF No Description 0x0 read-write n 0x0 0x0 FRCRAMERR1BIF FRCRAM 1-bit ECC Error Interrupt flag 28 1 read-write FRCRAMERR2BIF FRCRAM 2-bit ECC Error Interrupt flag 29 1 read-write RAMERR1B RAM 1-bit ECC Error Interrupt flag 16 1 read-write RAMERR2B RAM 2-bit ECC Error Interrupt flag 17 1 read-write SEQRAMERR1B SEQRAM 1-bit ECC Error Interrupt flag 24 1 read-write SEQRAMERR2B SEQRAM 2-bit ECC Error Interrupt flag 25 1 read-write SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RADIOECCCTRL No Description 0x408 read-write n 0x0 0x0 FRCRAMECCCHKEN FRCRAM ECC Check Enable 9 1 read-write FRCRAMECCEWEN FRCRAM ECC Write Enable 8 1 read-write SEQRAMECCCHKEN SEQRAM ECC Check Enable 1 1 read-write SEQRAMECCEWEN SEQRAM ECC Write Enable 0 1 read-write RADIORAMCTRL No Description 0x40C read-write n 0x0 0x0 DEMODRAMCACHEEN DEMODRAM CACHE Enable 24 1 read-write FRCRAMCACHEEN FRCRAM CACHE Enable 16 1 read-write FRCRAMPREFETCHEN FRCRAM Prfetch Enable 18 1 read-write FRCRAMWSEN FRCRAM WAIT STATE Enable 17 1 read-write SEQRAMCACHEEN SEQRAM CACHE Enable 0 1 read-write SEQRAMPREFETCHEN SEQRAM Prfetch Enable 2 1 read-write SEQRAMWSEN SEQRAM WAIT STATE Enable 1 1 read-write RADIORAMRETNCTRL No Description 0x400 read-write n 0x0 0x0 FRCRAMRETNCTRL FRCRAM Memory Shutdown Control Register 8 1 read-write ALLON FRCRAM not powered down 0 FRCBLK Power down FRCRAM (address range 0x50002000-0x50002FFF) 1 SEQRAMRETNCTRL SEQRAM Memory Shutdown Control Register 0 1 read-write ALLON SEQRAM not powered down 0 SEQBLK Power down SEQRAM (address range 0x50000000-0x50001FFF) 1 SEQRAMECCADDR No Description 0x410 read-only n 0x0 0x0 SEQRAMECCADDR SEQRAM ECC Error Address 0 32 read-only SYSCFG_S SYSCFG_S Registers SYSCFG_S 0x0 0x0 0x1000 registers n SYSCFG 20 SW0 53 SW1 54 SW2 55 SW3 56 CFGSYSTIC No Description 0x24 -1 read-write n 0x0 0x0 SYSTICEXTCLKEN SysTick External Clock Enable 0 1 read-write CHIPREV No Description 0x14 read-write n 0x0 0x0 FAMILY Part Family value 6 6 read-write MAJOR Part Revision Major value 0 6 read-write MINOR Part Revision Minor value 12 8 read-write CHIPREVHW No Description 0x10 read-write n 0x0 0x0 FAMILY Chip Family value 6 6 read-write MAJOR Chip Rev Major value 0 6 read-write MINOR Chip Rev Minor value 12 8 read-write CTRL No Description 0x200 -1 read-write n 0x0 0x0 ADDRFAULTEN Invalid Address Bus Fault Response Enable 0 1 read-write RAMECCERRFAULTEN Two bit ECC Error Bus Fault Response Enable 5 1 read-write DMEM0ECCADDR No Description 0x210 read-only n 0x0 0x0 DMEM0ECCADDR DMEM0 RAM ECC Error Address 0 32 read-only DMEM0ECCCTRL No Description 0x214 read-write n 0x0 0x0 RAMECCCHKEN RAM ECC Check Enable 1 1 read-write RAMECCEWEN RAM ECC Write Enable 0 1 read-write DMEM0RAMCTRL No Description 0x218 read-write n 0x0 0x0 RAMCACHEEN RAM CACHE Enable 0 1 read-write RAMPREFETCHEN RAM Prfetch Enable 2 1 read-write RAMWSEN RAM WAIT STATE Enable 1 1 read-write DMEM0RETNCTRL No Description 0x208 read-write n 0x0 0x0 RAMRETNCTRL DMEM0 blockset retention control 0 5 read-write ALLON None of the RAM blocks powered down 0 BLK5 Power down RAM block 5 (address range 0x20014000-0x20017FFF) 16 BLK4TO5 Power down RAM blocks 4 and above (address range 0x20010000-0x20017FFF) 24 BLK3TO5 Power down RAM blocks 3 and above (address range 0x2000C000-0x20017FFF) 28 BLK2TO5 Power down RAM blocks 2 and above (address range 0x20008000-0x20017FFF) 30 BLK1TO5 Power down RAM blocks 1 and above (address range 0x20004000-0x20017FFF) 31 FRCRAMECCADDR No Description 0x414 read-only n 0x0 0x0 FRCRAMECCADDR FRCRAM ECC Error Address 0 32 read-only IEN No Description 0x4 read-write n 0x0 0x0 FRCRAMERR1BIEN FRCRAM 1-bit ECC Error Interrupt enable 28 1 read-write FRCRAMERR2BIEN FRCRAM 2-bit ECC Error Interrupt enable 29 1 read-write RAMERR1B RAM 1-bit ECC Error Interrupt enable 16 1 read-write RAMERR2B RAM 2-bit ECC Error Interrupt enable 17 1 read-write SEQRAMERR1B SEQRAM 1-bit ECC Error Interrupt enable 24 1 read-write SEQRAMERR2B SEQRAM 2-bit ECC Error Interrupt enable 25 1 read-write SW0 Software interrupt 0 0 1 read-write SW1 Software interrupt 1 1 1 read-write SW2 Software interrupt 2 2 1 read-write SW3 Software interrupt 3 3 1 read-write IF No Description 0x0 read-write n 0x0 0x0 FRCRAMERR1BIF FRCRAM 1-bit ECC Error Interrupt flag 28 1 read-write FRCRAMERR2BIF FRCRAM 2-bit ECC Error Interrupt flag 29 1 read-write RAMERR1B RAM 1-bit ECC Error Interrupt flag 16 1 read-write RAMERR2B RAM 2-bit ECC Error Interrupt flag 17 1 read-write SEQRAMERR1B SEQRAM 1-bit ECC Error Interrupt flag 24 1 read-write SEQRAMERR2B SEQRAM 2-bit ECC Error Interrupt flag 25 1 read-write SW0 Software Interrupt 0 0 1 read-write SW1 Software Interrupt 1 1 1 read-write SW2 Software Interrupt 2 2 1 read-write SW3 Software Interrupt 3 3 1 read-write RADIOECCCTRL No Description 0x408 read-write n 0x0 0x0 FRCRAMECCCHKEN FRCRAM ECC Check Enable 9 1 read-write FRCRAMECCEWEN FRCRAM ECC Write Enable 8 1 read-write SEQRAMECCCHKEN SEQRAM ECC Check Enable 1 1 read-write SEQRAMECCEWEN SEQRAM ECC Write Enable 0 1 read-write RADIORAMCTRL No Description 0x40C read-write n 0x0 0x0 DEMODRAMCACHEEN DEMODRAM CACHE Enable 24 1 read-write FRCRAMCACHEEN FRCRAM CACHE Enable 16 1 read-write FRCRAMPREFETCHEN FRCRAM Prfetch Enable 18 1 read-write FRCRAMWSEN FRCRAM WAIT STATE Enable 17 1 read-write SEQRAMCACHEEN SEQRAM CACHE Enable 0 1 read-write SEQRAMPREFETCHEN SEQRAM Prfetch Enable 2 1 read-write SEQRAMWSEN SEQRAM WAIT STATE Enable 1 1 read-write RADIORAMRETNCTRL No Description 0x400 read-write n 0x0 0x0 FRCRAMRETNCTRL FRCRAM Memory Shutdown Control Register 8 1 read-write ALLON FRCRAM not powered down 0 FRCBLK Power down FRCRAM (address range 0x50002000-0x50002FFF) 1 SEQRAMRETNCTRL SEQRAM Memory Shutdown Control Register 0 1 read-write ALLON SEQRAM not powered down 0 SEQBLK Power down SEQRAM (address range 0x50000000-0x50001FFF) 1 SEQRAMECCADDR No Description 0x410 read-only n 0x0 0x0 SEQRAMECCADDR SEQRAM ECC Error Address 0 32 read-only TIMER0_NS TIMER0_NS Registers TIMER0_NS 0x0 0x0 0x1000 registers n TIMER0 6 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 32 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 32 read-write TIMER0_S TIMER0_S Registers TIMER0_S 0x0 0x0 0x1000 registers n TIMER0 6 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 32 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 32 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 32 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 32 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 32 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 32 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 32 read-write TIMER1_NS TIMER1_NS Registers TIMER1_NS 0x0 0x0 0x1000 registers n TIMER1 7 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write TIMER1_S TIMER1_S Registers TIMER1_S 0x0 0x0 0x1000 registers n TIMER1 7 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write TIMER2_NS TIMER2_NS Registers TIMER2_NS 0x0 0x0 0x1000 registers n TIMER2 8 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write TIMER2_S TIMER2_S Registers TIMER2_S 0x0 0x0 0x1000 registers n TIMER2 8 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write TIMER3_NS TIMER3_NS Registers TIMER3_NS 0x0 0x0 0x1000 registers n TIMER3 9 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write TIMER3_S TIMER3_S Registers TIMER3_S 0x0 0x0 0x1000 registers n TIMER3 9 CC0_CFG No Description 0x60 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC0_CTRL No Description 0x64 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC0_ICF No Description 0x74 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC0_ICOF No Description 0x78 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC0_OC No Description 0x68 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC0_OCB No Description 0x70 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC1_CFG No Description 0x80 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC1_CTRL No Description 0x84 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC1_ICF No Description 0x94 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC1_ICOF No Description 0x98 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC1_OC No Description 0x88 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC1_OCB No Description 0x90 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CC2_CFG No Description 0xA0 read-write n 0x0 0x0 COIST Compare Output Initial State 4 1 read-write FILT Digital Filter 20 1 read-write DISABLE Digital Filter Disabled 0 ENABLE Digital Filter Enabled 1 ICFWL Input Capture FIFO watermark level 21 1 read-write INSEL Input Selection 17 2 read-write PIN TIMERnCCx pin is selected 0 PRSSYNC Synchornous PRS selected 1 PRSASYNCLEVEL Asynchronous Level PRS selected 2 PRSASYNCPULSE Asynchronous Pulse PRS selected 3 MODE CC Channel Mode 0 2 read-write OFF Compare/Capture channel turned off 0 INPUTCAPTURE Input Capture 1 OUTPUTCOMPARE Output Compare 2 PWM Pulse-Width Modulation 3 PRSCONF PRS Configuration 19 1 read-write PULSE Each CC event will generate a one EM01GRPACLK cycle high pulse 0 LEVEL The PRS channel will follow CC out 1 CC2_CTRL No Description 0xA4 read-write n 0x0 0x0 CMOA Compare Match Output Action 8 2 read-write NONE No action on compare match 0 TOGGLE Toggle output on compare match 1 CLEAR Clear output on compare match 2 SET Set output on compare match 3 COFOA Counter Overflow Output Action 10 2 read-write NONE No action on counter overflow 0 TOGGLE Toggle output on counter overflow 1 CLEAR Clear output on counter overflow 2 SET Set output on counter overflow 3 CUFOA Counter Underflow Output Action 12 2 read-write NONE No action on counter underflow 0 TOGGLE Toggle output on counter underflow 1 CLEAR Clear output on counter underflow 2 SET Set output on counter underflow 3 ICEDGE Input Capture Edge Select 24 2 read-write RISING Rising edges detected 0 FALLING Falling edges detected 1 BOTH Both edges detected 2 NONE No edge detection, signal is left as it is 3 ICEVCTRL Input Capture Event Control 26 2 read-write EVERYEDGE PRS output pulse and interrupt flag set on every capture 0 EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture 1 RISING PRS output pulse and interrupt flag set on rising edge only (if ICEDGE = BOTH) 2 FALLING PRS output pulse and interrupt flag set on falling edge only (if ICEDGE = BOTH) 3 OUTINV Output Invert 2 1 read-write CC2_ICF No Description 0xB4 read-only n 0x0 0x0 ICF Input Capture FIFO 0 16 read-only CC2_ICOF No Description 0xB8 read-only n 0x0 0x0 ICOF Input Capture FIFO Overflow 0 16 read-only CC2_OC No Description 0xA8 read-write n 0x0 0x0 OC Output Compare Value 0 16 read-write CC2_OCB No Description 0xB0 read-write n 0x0 0x0 OCB Output Compare Value Buffer 0 16 read-write CFG No Description 0x4 read-write n 0x0 0x0 ATI Always Track Inputs 16 1 read-write CLKSEL Clock Source Select 8 2 read-write PRESCEM01GRPACLK Prescaled EM01GRPACLK 0 CC1 Compare/Capture Channel 1 Input 1 TIMEROUF Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer 2 DEBUGRUN Debug Mode Run Enable 6 1 read-write HALT Timer is halted in debug mode 0 RUN Timer is running in debug mode 1 DISSYNCOUT Disable Timer Start/Stop/Reload output 11 1 read-write EN Timer can start/stop/reload other timers with SYNC bit set 0 DIS Timer cannot start/stop/reload other timers with SYNC bit set 1 DMACLRACT DMA Request Clear on Active 7 1 read-write MODE Timer Mode 0 2 read-write UP Up-count mode 0 DOWN Down-count mode 1 UPDOWN Up/down-count mode 2 QDEC Quadrature decoder mode 3 OSMEN One-shot Mode Enable 4 1 read-write PRESC Prescaler Setting 18 10 read-write DIV1 No prescaling 0 DIV2 Prescale by 2 1 DIV1024 Prescale by 1024 1023 DIV128 Prescale by 128 127 DIV16 Prescale by 16 15 DIV256 Prescale by 256 255 DIV4 Prescale by 4 3 DIV32 Prescale by 32 31 DIV512 Prescale by 512 511 DIV64 Prescale by 64 63 DIV8 Prescale by 8 7 QDM Quadrature Decoder Mode Selection 5 1 read-write X2 X2 mode selected 0 X4 X4 mode selected 1 RETIMEEN PWM output retimed enable 10 1 read-write DISABLE PWM outputs are not re-timed. 0 ENABLE PWM outputs are re-timed. 1 RETIMESEL PWM output retime select 12 1 read-write RSSCOIST Reload-Start Sets COIST 17 1 read-write SYNC Timer Start/Stop/Reload Synchronization 3 1 read-write DISABLE Timer operation is unaffected by other timers. 0 ENABLE Timer may be started, stopped and re-loaded from other timer instances. 1 CMD No Description 0xC write-only n 0x0 0x0 START Start Timer 0 1 write-only STOP Stop Timer 1 1 write-only CNT No Description 0x24 read-write n 0x0 0x0 CNT Counter Value 0 16 read-write CTRL No Description 0x8 read-write n 0x0 0x0 FALLA Timer Falling Input Edge Action 2 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 RISEA Timer Rising Input Edge Action 0 2 read-write NONE No action 0 START Start counter without reload 1 STOP Stop counter without reload 2 RELOADSTART Reload and start counter 3 X2CNT 2x Count Mode 4 1 read-write DTCFG No Description 0xE0 read-write n 0x0 0x0 DTAR DTI Always Run 9 1 read-write DTDAS DTI Automatic Start-up Functionality 1 1 read-write NORESTART No DTI restart on debugger exit 0 RESTART DTI restart on debugger exit 1 DTEN DTI Enable 0 1 read-write DTFATS DTI Fault Action on Timer Stop 10 1 read-write DTPRSEN DTI PRS Source Enable 11 1 read-write DTCTRL No Description 0xEC read-write n 0x0 0x0 DTCINV DTI Complementary Output Invert. 0 1 read-write DTIPOL DTI Inactive Polarity 1 1 read-write DTFAULT No Description 0xF4 read-only n 0x0 0x0 DTDBGF DTI Debugger Fault 2 1 read-only DTEM23F DTI EM23 Entry Fault 4 1 read-only DTLOCKUPF DTI Lockup Fault 3 1 read-only DTPRS0F DTI PRS 0 Fault 0 1 read-only DTPRS1F DTI PRS 1 Fault 1 1 read-only DTFAULTC No Description 0xF8 write-only n 0x0 0x0 DTDBGFC DTI Debugger Fault Clear 2 1 write-only DTEM23FC DTI EM23 Fault Clear 4 1 write-only DTLOCKUPFC DTI Lockup Fault Clear 3 1 write-only DTPRS0FC DTI PRS0 Fault Clear 0 1 write-only DTPRS1FC DTI PRS1 Fault Clear 1 1 write-only DTFCFG No Description 0xE8 read-write n 0x0 0x0 DTDBGFEN DTI Debugger Fault Enable 26 1 read-write DTEM23FEN DTI EM23 Fault Enable 28 1 read-write DTFA DTI Fault Action 16 2 read-write NONE No action on fault 0 INACTIVE Set outputs inactive 1 CLEAR Clear outputs 2 TRISTATE Tristate outputs 3 DTLOCKUPFEN DTI Lockup Fault Enable 27 1 read-write DTPRS0FEN DTI PRS 0 Fault Enable 24 1 read-write DTPRS1FEN DTI PRS 1 Fault Enable 25 1 read-write DTLOCK No Description 0xFC write-only n 0x0 0x0 DTILOCKKEY DTI Lock Key 0 16 write-only UNLOCK Write to unlock TIMER DTI registers 52864 DTOGEN No Description 0xF0 read-write n 0x0 0x0 DTOGCC0EN DTI CCn Output Generation Enable 0 1 read-write DTOGCC1EN DTI CCn Output Generation Enable 1 1 read-write DTOGCC2EN DTI CCn Output Generation Enable 2 1 read-write DTOGCDTI0EN DTI CDTIn Output Generation Enable 3 1 read-write DTOGCDTI1EN DTI CDTIn Output Generation Enable 4 1 read-write DTOGCDTI2EN DTI CDTIn Output Generation Enable 5 1 read-write DTTIMECFG No Description 0xE4 read-write n 0x0 0x0 DTFALLT DTI Fall-time 16 6 read-write DTPRESC DTI Prescaler Setting 0 10 read-write DTRISET DTI Rise-time 10 6 read-write EN No Description 0x30 read-write n 0x0 0x0 EN Timer Module Enable 0 1 read-write IEN No Description 0x18 read-write n 0x0 0x0 CC0 CC0 Interrupt Enable 4 1 read-write CC1 CC1 Interrupt Enable 5 1 read-write CC2 CC2 Interrupt Enable 6 1 read-write DIRCHG Direction Change Detect Interrupt Enable 2 1 read-write ICFOF0 ICFOF0 Interrupt Enable 20 1 read-write ICFOF1 ICFOF1 Interrupt Enable 21 1 read-write ICFOF2 ICFOF2 Interrupt Enable 22 1 read-write ICFUF0 ICFUF0 Interrupt Enable 24 1 read-write ICFUF1 ICFUF1 Interrupt Enable 25 1 read-write ICFUF2 ICFUF2 Interrupt Enable 26 1 read-write ICFWLFULL0 ICFWLFULL0 Interrupt Enable 16 1 read-write ICFWLFULL1 ICFWLFULL1 Interrupt Enable 17 1 read-write ICFWLFULL2 ICFWLFULL2 Interrupt Enable 18 1 read-write OF Overflow Interrupt Enable 0 1 read-write UF Underflow Interrupt Enable 1 1 read-write IF No Description 0x14 read-write n 0x0 0x0 CC0 Capture Compare Channel 0 Interrupt Flag 4 1 read-write CC1 Capture Compare Channel 1 Interrupt Flag 5 1 read-write CC2 Capture Compare Channel 2 Interrupt Flag 6 1 read-write DIRCHG Direction Change Detect Interrupt Flag 2 1 read-write ICFOF0 Input Capture FIFO overflow 20 1 read-write ICFOF1 Input Capture FIFO overflow 21 1 read-write ICFOF2 Input Capture FIFO overflow 22 1 read-write ICFUF0 Input capture FIFO underflow 24 1 read-write ICFUF1 Input capture FIFO underflow 25 1 read-write ICFUF2 Input capture FIFO underflow 26 1 read-write ICFWLFULL0 Input Capture Watermark Level Full 16 1 read-write ICFWLFULL1 Input Capture Watermark Level Full 17 1 read-write ICFWLFULL2 Input Capture Watermark Level Full 18 1 read-write OF Overflow Interrupt Flag 0 1 read-write UF Underflow Interrupt Flag 1 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version ID 0 32 read-only LOCK No Description 0x2C write-only n 0x0 0x0 LOCKKEY Timer Lock Key 0 16 write-only UNLOCK Write to unlock TIMER registers 52864 STATUS No Description 0x10 read-only n 0x0 0x0 CCPOL0 CCn Polarity 24 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL1 CCn Polarity 25 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 CCPOL2 CCn Polarity 26 1 read-only LOWRISE CC0 polarity low level/rising edge 0 HIGHFALL CC0 polarity high level/falling edge 1 DIR Direction 1 1 read-only UP Counting up 0 DOWN Counting down 1 DTILOCKSTATUS DTI lock status 5 1 read-only UNLOCKED DTI registers are unlocked 0 LOCKED DTI registers are locked 1 ICFEMPTY0 Input capture fifo empty 16 1 read-only ICFEMPTY1 Input capture fifo empty 17 1 read-only ICFEMPTY2 Input capture fifo empty 18 1 read-only OCBV0 Output Compare Buffer Valid 8 1 read-only OCBV1 Output Compare Buffer Valid 9 1 read-only OCBV2 Output Compare Buffer Valid 10 1 read-only RUNNING Running 0 1 read-only SYNCBUSY Sync Busy 6 1 read-only TIMERLOCKSTATUS Timer lock status 4 1 read-only UNLOCKED TIMER registers are unlocked 0 LOCKED TIMER registers are locked 1 TOPBV TOP Buffer Valid 2 1 read-only TOP No Description 0x1C -1 read-write n 0x0 0x0 TOP Counter Top Value 0 16 read-write TOPB No Description 0x20 read-write n 0x0 0x0 TOPB Counter Top Buffer Register 0 16 read-write ULFRCO_NS ULFRCO_NS Registers ULFRCO_NS 0x0 0x0 0x1000 registers n ULFRCO 24 IEN No Description 0x18 read-write n 0x0 0x0 NEGEDGE Enable Negative Edge Interrupt 2 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write RDY Enable Ready Interrupt 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 NEGEDGE Negative Edge Interrupt Flag 2 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x8 read-only n 0x0 0x0 ENS Enable Status 16 1 read-only RDY Ready Status 0 1 read-only ULFRCO_S ULFRCO_S Registers ULFRCO_S 0x0 0x0 0x1000 registers n ULFRCO 24 IEN No Description 0x18 read-write n 0x0 0x0 NEGEDGE Enable Negative Edge Interrupt 2 1 read-write POSEDGE Enable Positive Edge Interrupt 1 1 read-write RDY Enable Ready Interrupt 0 1 read-write IF No Description 0x14 read-write n 0x0 0x0 NEGEDGE Negative Edge Interrupt Flag 2 1 read-write POSEDGE Positive Edge Interrupt Flag 1 1 read-write RDY Ready Interrupt Flag 0 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION ULFRCO IP version 0 32 read-only STATUS No Description 0x8 read-only n 0x0 0x0 ENS Enable Status 16 1 read-only RDY Ready Status 0 1 read-only USART0_NS USART0_NS Registers USART0_NS 0x0 0x0 0x1000 registers n USART0_RX 11 USART0_TX 12 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only USART0_S USART0_S Registers USART0_S 0x0 0x0 0x1000 registers n USART0_RX 11 USART0_TX 12 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only USART1_NS USART1_NS Registers USART1_NS 0x0 0x0 0x1000 registers n USART1_RX 13 USART1_TX 14 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only USART1_S USART1_S Registers USART1_S 0x0 0x0 0x1000 registers n USART1_RX 13 USART1_TX 14 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only USART2_NS USART2_NS Registers USART2_NS 0x0 0x0 0x1000 registers n USART2_RX 15 USART2_TX 16 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only USART2_S USART2_S Registers USART2_S 0x0 0x0 0x1000 registers n USART2_RX 15 USART2_TX 16 CLKDIV No Description 0x1C read-write n 0x0 0x0 AUTOBAUDEN AUTOBAUD detection enable 31 1 read-write DIV Fractional Clock Divider 3 20 read-write CMD No Description 0x14 write-only n 0x0 0x0 CLEARRX Clear RX 11 1 write-only CLEARTX Clear TX 10 1 write-only MASTERDIS Master Disable 5 1 write-only MASTEREN Master Enable 4 1 write-only RXBLOCKDIS Receiver Block Disable 7 1 write-only RXBLOCKEN Receiver Block Enable 6 1 write-only RXDIS Receiver Disable 1 1 write-only RXEN Receiver Enable 0 1 write-only TXDIS Transmitter Disable 3 1 write-only TXEN Transmitter Enable 2 1 write-only TXTRIDIS Transmitter Tristate Disable 9 1 write-only TXTRIEN Transmitter Tristate Enable 8 1 write-only CTRL No Description 0x8 read-write n 0x0 0x0 AUTOCS Automatic Chip Select 16 1 read-write AUTOTRI Automatic TX Tristate 17 1 read-write DISABLE The output on U(S)n_TX when the transmitter is idle is defined by TXINV 0 ENABLE U(S)n_TX is tristated whenever the transmitter is idle 1 AUTOTX Always Transmit When RX Not Full 29 1 read-write BIT8DV Bit 8 Default Value 21 1 read-write BYTESWAP Byteswap In Double Accesses 28 1 read-write DISABLE Normal byte order 0 ENABLE Byte order swapped 1 CCEN Collision Check Enable 2 1 read-write DISABLE Collision check is disabled 0 ENABLE Collision check is enabled. The receiver must be enabled for the check to be performed 1 CLKPHA Clock Edge For Setup/Sample 9 1 read-write SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode 0 SAMPLETRAILING Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode 1 CLKPOL Clock Polarity 8 1 read-write IDLELOW The bus clock used in synchronous mode has a low base value 0 IDLEHIGH The bus clock used in synchronous mode has a high base value 1 CSINV Chip Select Invert 15 1 read-write DISABLE Chip select is active low 0 ENABLE Chip select is active high 1 CSMA Action On Slave-Select In Master Mode 11 1 read-write NOACTION No action taken 0 GOTOSLAVEMODE Go to slave mode 1 ERRSDMA Halt DMA On Error 22 1 read-write DISABLE Framing and parity errors have no effect on DMA requests from the USART 0 ENABLE DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 1 ERRSRX Disable RX On Error 23 1 read-write DISABLE Framing and parity errors have no effect on receiver 0 ENABLE Framing and parity errors disable the receiver 1 ERRSTX Disable TX On Error 24 1 read-write DISABLE Received framing and parity errors have no effect on transmitter 0 ENABLE Received framing and parity errors disable the transmitter 1 LOOPBK Loopback Enable 1 1 read-write DISABLE The receiver is connected to and receives data from U(S)n_RX 0 ENABLE The receiver is connected to and receives data from U(S)n_TX 1 MPAB Multi-Processor Address-Bit 4 1 read-write MPM Multi-Processor Mode 3 1 read-write DISABLE The 9th bit of incoming frames has no special function 0 ENABLE An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 1 MSBF Most Significant Bit First 10 1 read-write DISABLE Data is sent with the least significant bit first 0 ENABLE Data is sent with the most significant bit first 1 MVDIS Majority Vote Disable 30 1 read-write OVS Oversampling 5 2 read-write X16 Regular UART mode with 16X oversampling in asynchronous mode 0 X8 Double speed with 8X oversampling in asynchronous mode 1 X6 6X oversampling in asynchronous mode 2 X4 Quadruple speed with 4X oversampling in asynchronous mode 3 RXINV Receiver Input Invert 13 1 read-write DISABLE Input is passed directly to the receiver 0 ENABLE Input is inverted before it is passed to the receiver 1 SCMODE SmartCard Mode 18 1 read-write SCRETRANS SmartCard Retransmit 19 1 read-write SKIPPERRF Skip Parity Error Frames 20 1 read-write SMSDELAY Synchronous Master Sample Delay 31 1 read-write SSSEARLY Synchronous Slave Setup Early 25 1 read-write SYNC USART Synchronous Mode 0 1 read-write DISABLE The USART operates in asynchronous mode 0 ENABLE The USART operates in synchronous mode 1 TXBIL TX Buffer Interrupt Level 12 1 read-write EMPTY TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty. 0 HALFFULL TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full. 1 TXINV Transmitter output Invert 14 1 read-write DISABLE Output from the transmitter is passed unchanged to U(S)n_TX 0 ENABLE Output from the transmitter is inverted before it is passed to U(S)n_TX 1 CTRLX No Description 0x5C read-write n 0x0 0x0 CLKPRSEN PRS CLK Enable 15 1 read-write CTSEN CTS Function enabled 2 1 read-write DISABLE Ingore CTS 0 ENABLE Stop transmitting when CTS is negated 1 CTSINV CTS Pin Inversion 1 1 read-write DISABLE The USn_CTS pin is low true 0 ENABLE The USn_CTS pin is high true 1 DBGHALT Debug halt 0 1 read-write DISABLE Continue to transmit until TX buffer is empty 0 ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame. 1 RTSINV RTS Pin Inversion 3 1 read-write DISABLE The USn_RTS pin is low true 0 ENABLE The USn_RTS pin is high true 1 RXPRSEN PRS RX Enable 7 1 read-write EN No Description 0x4 read-write n 0x0 0x0 EN USART Enable 0 1 read-write FRAME No Description 0xC -1 read-write n 0x0 0x0 DATABITS Data-Bit Mode 0 4 read-write FOUR Each frame contains 4 data bits 1 THIRTEEN Each frame contains 13 data bits 10 FOURTEEN Each frame contains 14 data bits 11 FIFTEEN Each frame contains 15 data bits 12 SIXTEEN Each frame contains 16 data bits 13 FIVE Each frame contains 5 data bits 2 SIX Each frame contains 6 data bits 3 SEVEN Each frame contains 7 data bits 4 EIGHT Each frame contains 8 data bits 5 NINE Each frame contains 9 data bits 6 TEN Each frame contains 10 data bits 7 ELEVEN Each frame contains 11 data bits 8 TWELVE Each frame contains 12 data bits 9 PARITY Parity-Bit Mode 8 2 read-write NONE Parity bits are not used 0 EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. 2 ODD Odd parity is used. Parity bits are automatically generated and checked by hardware. 3 STOPBITS Stop-Bit Mode 12 2 read-write HALF The transmitter generates a half stop bit. Stop-bits are not verified by receiver 0 ONE One stop bit is generated and verified 1 ONEANDAHALF The transmitter generates one and a half stop bit. The receiver verifies the first stop bit 2 TWO The transmitter generates two stop bits. The receiver checks the first stop-bit only 3 I2SCTRL No Description 0x54 read-write n 0x0 0x0 DELAY Delay on I2S data 4 1 read-write DMASPLIT Separate DMA Request For Left/Right Data 3 1 read-write EN Enable I2S Mode 0 1 read-write FORMAT I2S Word Format 8 3 read-write W32D32 32-bit word, 32-bit data 0 W32D24M 32-bit word, 32-bit data with 8 lsb masked 1 W32D24 32-bit word, 24-bit data 2 W32D16 32-bit word, 16-bit data 3 W32D8 32-bit word, 8-bit data 4 W16D16 16-bit word, 16-bit data 5 W16D8 16-bit word, 8-bit data 6 W8D8 8-bit word, 8-bit data 7 JUSTIFY Justification of I2S Data 2 1 read-write LEFT Data is left-justified 0 RIGHT Data is right-justified 1 MONO Stero or Mono 1 1 read-write IEN No Description 0x4C read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Enable 12 1 read-write FERR Framing Error Interrupt Enable 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Enable 8 1 read-write RXDATAV RX Data Valid Interrupt Enable 2 1 read-write RXFULL RX Buffer Full Interrupt Enable 3 1 read-write RXOF RX Overflow Interrupt Enable 4 1 read-write RXUF RX Underflow Interrupt Enable 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Enable 14 1 read-write TCMP1 Timer comparator 1 Interrupt Enable 15 1 read-write TCMP2 Timer comparator 2 Interrupt Enable 16 1 read-write TXBL TX Buffer Level Interrupt Enable 1 1 read-write TXC TX Complete Interrupt Enable 0 1 read-write TXIDLE TX Idle Interrupt Enable 13 1 read-write TXOF TX Overflow Interrupt Enable 6 1 read-write TXUF TX Underflow Interrupt Enable 7 1 read-write IF No Description 0x48 -1 read-write n 0x0 0x0 CCF Collision Check Fail Interrupt Flag 12 1 read-write FERR Framing Error Interrupt Flag 9 1 read-write MPAF Multi-Processor Address Frame Interrupt 10 1 read-write PERR Parity Error Interrupt Flag 8 1 read-write RXDATAV RX Data Valid Interrupt Flag 2 1 read-write RXFULL RX Buffer Full Interrupt Flag 3 1 read-write RXOF RX Overflow Interrupt Flag 4 1 read-write RXUF RX Underflow Interrupt Flag 5 1 read-write SSM Slave-Select In Master Mode Interrupt Fl 11 1 read-write TCMP0 Timer comparator 0 Interrupt Flag 14 1 read-write TCMP1 Timer comparator 1 Interrupt Flag 15 1 read-write TCMP2 Timer comparator 2 Interrupt Flag 16 1 read-write TXBL TX Buffer Level Interrupt Flag 1 1 read-write TXC TX Complete Interrupt Flag 0 1 read-write TXIDLE TX Idle Interrupt Flag 13 1 read-write TXOF TX Overflow Interrupt Flag 6 1 read-write TXUF TX Underflow Interrupt Flag 7 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IPVERSION 0 32 read-only IRCTRL No Description 0x50 read-write n 0x0 0x0 IREN Enable IrDA Module 0 1 read-write IRFILT IrDA RX Filter 3 1 read-write DISABLE No filter enabled 0 ENABLE Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected 1 IRPRSEN IrDA PRS Channel Enable 7 1 read-write IRPW IrDA TX Pulse Width 1 2 read-write ONE IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 0 TWO IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 1 THREE IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 2 FOUR IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 3 RXDATA No Description 0x24 read-only n 0x0 0x0 RXDATA RX Data 0 8 read-only RXDATAX No Description 0x20 read-only n 0x0 0x0 FERR Data Framing Error 15 1 read-only PERR Data Parity Error 14 1 read-only RXDATA RX Data 0 9 read-only RXDATAXP No Description 0x30 read-only n 0x0 0x0 FERRP Data Framing Error Peek 15 1 read-only PERRP Data Parity Error Peek 14 1 read-only RXDATAP RX Data Peek 0 9 read-only RXDOUBLE No Description 0x2C read-only n 0x0 0x0 RXDATA0 RX Data 0 0 8 read-only RXDATA1 RX Data 1 8 8 read-only RXDOUBLEX No Description 0x28 read-only n 0x0 0x0 FERR0 Data Framing Error 0 15 1 read-only FERR1 Data Framing Error 1 31 1 read-only PERR0 Data Parity Error 0 14 1 read-only PERR1 Data Parity Error 1 30 1 read-only RXDATA0 RX Data 0 0 9 read-only RXDATA1 RX Data 1 16 9 read-only RXDOUBLEXP No Description 0x34 read-only n 0x0 0x0 FERRP0 Data Framing Error 0 Peek 15 1 read-only FERRP1 Data Framing Error 1 Peek 31 1 read-only PERRP0 Data Parity Error 0 Peek 14 1 read-only PERRP1 Data Parity Error 1 Peek 30 1 read-only RXDATAP0 RX Data 0 Peek 0 9 read-only RXDATAP1 RX Data 1 Peek 16 9 read-only STATUS No Description 0x18 -1 read-only n 0x0 0x0 MASTER SPI Master Mode 2 1 read-only RXBLOCK Block Incoming Data 3 1 read-only RXDATAV RX Data Valid 7 1 read-only RXDATAVRIGHT RX Data Right 11 1 read-only RXENS Receiver Enable Status 0 1 read-only RXFULL RX FIFO Full 8 1 read-only RXFULLRIGHT RX Full of Right Data 12 1 read-only TIMERRESTARTED The USART Timer restarted itself 14 1 read-only TXBDRIGHT TX Buffer Expects Double Right Data 9 1 read-only TXBL TX Buffer Level 6 1 read-only TXBSRIGHT TX Buffer Expects Single Right Data 10 1 read-only TXBUFCNT TX Buffer Count 16 2 read-only TXC TX Complete 5 1 read-only TXENS Transmitter Enable Status 1 1 read-only TXIDLE TX Idle 13 1 read-only TXTRI Transmitter Tristated 4 1 read-only TIMECMP0 No Description 0x60 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP0 24 1 read-write DISABLE Disable the timer restarting on TCMP0 0 ENABLE Enable the timer restarting on TCMP0 1 TCMPVAL Timer comparator 0. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 0 is disabled 0 TXEOF Comparator 0 and timer are started at TX end of frame 1 TXC Comparator 0 and timer are started at TX Complete 2 RXACT Comparator 0 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 0 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 0 20 3 read-write TCMP0 Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event 0 TXST Comparator 0 is disabled at TX start TX Engine 1 RXACT Comparator 0 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 0 is disabled on RX going Inactive 3 TIMECMP1 No Description 0x64 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP1 24 1 read-write DISABLE Disable the timer restarting on TCMP1 0 ENABLE Enable the timer restarting on TCMP1 1 TCMPVAL Timer comparator 1. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 1 is disabled 0 TXEOF Comparator 1 and timer are started at TX end of frame 1 TXC Comparator 1 and timer are started at TX Complete 2 RXACT Comparator 1 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 1 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 1 20 3 read-write TCMP1 Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event 0 TXST Comparator 1 is disabled at TX start TX Engine 1 RXACT Comparator 1 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 1 is disabled on RX going Inactive 3 TIMECMP2 No Description 0x68 read-write n 0x0 0x0 RESTARTEN Restart Timer on TCMP2 24 1 read-write DISABLE Disable the timer restarting on TCMP2 0 ENABLE Enable the timer restarting on TCMP2 1 TCMPVAL Timer comparator 2. 0 8 read-write TSTART Timer start source 16 3 read-write DISABLE Comparator 2 is disabled 0 TXEOF Comparator 2 and timer are started at TX end of frame 1 TXC Comparator 2 and timer are started at TX Complete 2 RXACT Comparator 2 and timer are started at RX going going Active (default: low) 3 RXEOF Comparator 2 and timer are started at RX end of frame 4 TSTOP Source used to disable comparator 2 20 3 read-write TCMP2 Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event 0 TXST Comparator 2 is disabled at TX start TX Engine 1 RXACT Comparator 2 is disabled on RX going going Active (default: low) 2 RXACTN Comparator 2 is disabled on RX going Inactive 3 TIMING No Description 0x58 read-write n 0x0 0x0 CSHOLD Chip Select Hold 28 3 read-write ZERO Disable CS being asserted after the end of transmission 0 ONE CS is asserted for 1 baud-times after the end of transmission 1 TWO CS is asserted for 2 baud-times after the end of transmission 2 THREE CS is asserted for 3 baud-times after the end of transmission 3 SEVEN CS is asserted for 7 baud-times after the end of transmission 4 TCMP0 CS is asserted after the end of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted after the end of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted after the end of transmission for TCMPVAL2 baud-times 7 CSSETUP Chip Select Setup 20 3 read-write ZERO CS is not asserted before start of transmission 0 ONE CS is asserted for 1 baud-times before start of transmission 1 TWO CS is asserted for 2 baud-times before start of transmission 2 THREE CS is asserted for 3 baud-times before start of transmission 3 SEVEN CS is asserted for 7 baud-times before start of transmission 4 TCMP0 CS is asserted before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 CS is asserted before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 CS is asserted before the start of transmission for TCMPVAL2 baud-times 7 ICS Inter-character spacing 24 3 read-write ZERO There is no space between charcters 0 ONE Create a space of 1 baud-times before start of transmission 1 TWO Create a space of 2 baud-times before start of transmission 2 THREE Create a space of 3 baud-times before start of transmission 3 SEVEN Create a space of 7 baud-times before start of transmission 4 TCMP0 Create a space of before the start of transmission for TCMPVAL0 baud-times 5 TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times 6 TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times 7 TXDELAY TX frame start delay 16 3 read-write DISABLE Disable - TXDELAY in USARTn_CTRL can be used for legacy 0 ONE Start of transmission is delayed for 1 baud-times 1 TWO Start of transmission is delayed for 2 baud-times 2 THREE Start of transmission is delayed for 3 baud-times 3 SEVEN Start of transmission is delayed for 7 baud-times 4 TCMP0 Start of transmission is delayed for TCMPVAL0 baud-times 5 TCMP1 Start of transmission is delayed for TCMPVAL1 baud-times 6 TCMP2 Start of transmission is delayed for TCMPVAL2 baud-times 7 TRIGCTRL No Description 0x10 read-write n 0x0 0x0 AUTOTXTEN AUTOTX Trigger Enable 6 1 read-write RXATX0EN Enable Receive Trigger after TX end of f 10 1 read-write RXATX1EN Enable Receive Trigger after TX end of f 11 1 read-write RXATX2EN Enable Receive Trigger after TX end of f 12 1 read-write RXTEN Receive Trigger Enable 4 1 read-write TXARX0EN Enable Transmit Trigger after RX End of 7 1 read-write TXARX1EN Enable Transmit Trigger after RX End of 8 1 read-write TXARX2EN Enable Transmit Trigger after RX End of 9 1 read-write TXTEN Transmit Trigger Enable 5 1 read-write TXDATA No Description 0x3C write-only n 0x0 0x0 TXDATA TX Data 0 8 write-only TXDATAX No Description 0x38 write-only n 0x0 0x0 RXENAT Enable RX After Transmission 15 1 write-only TXBREAK Transmit Data As Break 13 1 write-only TXDATAX TX Data 0 9 write-only TXDISAT Clear TXEN After Transmission 14 1 write-only TXTRIAT Set TXTRI After Transmission 12 1 write-only UBRXAT Unblock RX After Transmission 11 1 write-only TXDOUBLE No Description 0x44 write-only n 0x0 0x0 TXDATA0 TX Data 0 8 write-only TXDATA1 TX Data 8 8 write-only TXDOUBLEX No Description 0x40 write-only n 0x0 0x0 RXENAT0 Enable RX After Transmission 15 1 write-only RXENAT1 Enable RX After Transmission 31 1 write-only TXBREAK0 Transmit Data As Break 13 1 write-only TXBREAK1 Transmit Data As Break 29 1 write-only TXDATA0 TX Data 0 9 write-only TXDATA1 TX Data 16 9 write-only TXDISAT0 Clear TXEN After Transmission 14 1 write-only TXDISAT1 Clear TXEN After Transmission 30 1 write-only TXTRIAT0 Set TXTRI After Transmission 12 1 write-only TXTRIAT1 Set TXTRI After Transmission 28 1 write-only UBRXAT0 Unblock RX After Transmission 11 1 write-only UBRXAT1 Unblock RX After Transmission 27 1 write-only WDOG0_NS WDOG0_NS Registers WDOG0_NS 0x0 0x0 0x1000 registers n WDOG0 43 CFG No Description 0x8 -1 read-write n 0x0 0x0 CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0xC write-only n 0x0 0x0 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write IF No Description 0x18 read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x20 -1 write-only n 0x0 0x0 LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 STATUS No Description 0x14 read-only n 0x0 0x0 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 SYNCBUSY No Description 0x24 read-only n 0x0 0x0 CMD Sync Busy for Cmd Register 0 1 read-only WDOG0_S WDOG0_S Registers WDOG0_S 0x0 0x0 0x1000 registers n WDOG0 43 CFG No Description 0x8 -1 read-write n 0x0 0x0 CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0xC write-only n 0x0 0x0 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write IF No Description 0x18 read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x20 -1 write-only n 0x0 0x0 LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 STATUS No Description 0x14 read-only n 0x0 0x0 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 SYNCBUSY No Description 0x24 read-only n 0x0 0x0 CMD Sync Busy for Cmd Register 0 1 read-only WDOG1_NS WDOG1_NS Registers WDOG1_NS 0x0 0x0 0x1000 registers n WDOG1 44 CFG No Description 0x8 -1 read-write n 0x0 0x0 CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0xC write-only n 0x0 0x0 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write IF No Description 0x18 read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x20 -1 write-only n 0x0 0x0 LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 STATUS No Description 0x14 read-only n 0x0 0x0 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 SYNCBUSY No Description 0x24 read-only n 0x0 0x0 CMD Sync Busy for Cmd Register 0 1 read-only WDOG1_S WDOG1_S Registers WDOG1_S 0x0 0x0 0x1000 registers n WDOG1 44 CFG No Description 0x8 -1 read-write n 0x0 0x0 CLRSRC WDOG Clear Source 0 1 read-write SW A write to the clear bit will clear the WDOG counter 0 PRSSRC0 A rising edge on the PRS Source 0 will clear the WDOG counter 1 DEBUGRUN Debug Mode Run 4 1 read-write DISABLE WDOG timer is frozen in debug mode 0 ENABLE WDOG timer is running in debug mode 1 EM2RUN EM2 Run 1 1 read-write DISABLE WDOG timer is frozen in EM2. 0 ENABLE WDOG timer is running in EM2. 1 EM3RUN EM3 Run 2 1 read-write DISABLE WDOG timer is frozen in EM3. 0 ENABLE WDOG timer is running in EM3. 1 EM4BLOCK EM4 Block 3 1 read-write DISABLE EM4 can be entered by software. See EMU for detailed description. 0 ENABLE EM4 cannot be entered by software. 1 PERSEL WDOG Timeout Period Select 16 4 read-write SEL0 Timeout period of 9 wdog cycles 0 SEL1 Timeout period of 17 wdog cycles 1 SEL10 Timeout period of 8k wdog cycles 10 SEL11 Timeout period of 16k wdog cycles 11 SEL12 Timeout period of 32k wdog cycles 12 SEL13 Timeout period of 64k wdog cycles 13 SEL14 Timeout period of 128k wdog cycles 14 SEL15 Timeout period of 256k wdog cycles 15 SEL2 Timeout period of 33 wdog cycles 2 SEL3 Timeout period of 65 wdog cycles 3 SEL4 Timeout period of 129 wdog cycles 4 SEL5 Timeout period of 257 wdog cycles 5 SEL6 Timeout period of 513 wdog cycles 6 SEL7 Timeout period of 1k wdog cycles 7 SEL8 Timeout period of 2k wdog cycles 8 SEL9 Timeout period of 4k wdog cycles 9 PRS0MISSRSTEN PRS Src0 Missing Event WDOG Reset 9 1 read-write PRS1MISSRSTEN PRS Src1 Missing Event WDOG Reset 10 1 read-write WARNSEL WDOG Warning Period Select 24 2 read-write DIS Disable 0 SEL1 Warning timeout is 25% of the Timeout. 1 SEL2 Warning timeout is 50% of the Timeout. 2 SEL3 Warning timeout is 75% of the Timeout. 3 WDOGRSTDIS WDOG Reset Disable 8 1 read-write EN A timeout will cause a WDOG reset 0 DIS A timeout will not cause a WDOG reset 1 WINSEL WDOG Illegal Window Select 28 3 read-write DIS Disabled. 0 SEL1 Window timeout is 12.5% of the Timeout. 1 SEL2 Window timeout is 25% of the Timeout. 2 SEL3 Window timeout is 37.5% of the Timeout. 3 SEL4 Window timeout is 50% of the Timeout. 4 SEL5 Window timeout is 62.5% of the Timeout. 5 SEL6 Window timeout is 75.5% of the Timeout. 6 SEL7 Window timeout is 87.5% of the Timeout. 7 CMD No Description 0xC write-only n 0x0 0x0 CLEAR WDOG Timer Clear 0 1 write-only UNCHANGED WDOG timer is unchanged. 0 CLEARED WDOG timer is cleared to 0. 1 EN No Description 0x4 read-write n 0x0 0x0 EN Module Enable 0 1 read-write IEN No Description 0x1C read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Enable 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Enable 4 1 read-write TOUT WDOG Timeout Interrupt Enable 0 1 read-write WARN WDOG Warning Timeout Interrupt Enable 1 1 read-write WIN WDOG Window Interrupt Enable 2 1 read-write IF No Description 0x18 read-write n 0x0 0x0 PEM0 PRS Src0 Event Missing Interrupt Flag 3 1 read-write PEM1 PRS Src1 Event Missing Interrupt Flag 4 1 read-write TOUT WDOG Timeout Interrupt Flag 0 1 read-write WARN WDOG Warning Timeout Interrupt Flag 1 1 read-write WIN WDOG Window Interrupt Flag 2 1 read-write IPVERSION No Description 0x0 read-only n 0x0 0x0 IPVERSION IP Version 0 32 read-only LOCK No Description 0x20 -1 write-only n 0x0 0x0 LOCKKEY WDOG Configuration Lock 0 16 write-only LOCK Lock WDOG lockable registers 0 UNLOCK Unlock WDOG lockable registers 44008 STATUS No Description 0x14 read-only n 0x0 0x0 LOCK WDOG Configuration Lock Status 31 1 read-only UNLOCKED All WDOG lockable registers are unlocked. 0 LOCKED All WDOG lockable registers are locked. 1 SYNCBUSY No Description 0x24 read-only n 0x0 0x0 CMD Sync Busy for Cmd Register 0 1 read-only