nuvoTon
M030GAE
2024.05.18
M030GAE SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x40
registers
n
0x100
0x4
registers
n
0x180
0x8
registers
n
0x74
0x4
registers
n
0x80
0x1C
registers
n
0xA0
0x8
registers
n
ADCALR
ADC_ADCALR
ADC Calibration Mode Register
0x180
-1
read-write
n
0x0
0x0
CALEN
Calibration Function Enable Bit
Note: If chip is powered off, calibration function should be executed again.
0
1
read-write
0
Calibration function Disabled
#0
CALIE
Calibration Interrupt Enable Bit
If calibration function is enabled and the calibration is finished, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated.
1
1
read-write
0
Calibration function Interrupt Disabled
#0
1
Calibration function Interrupt Enabled
#1
ADCALSTSR
ADC_ADCALSTSR
ADC Calibration Status Register
0x184
-1
read-write
n
0x0
0x0
CALIF
Calibration Finish Interrupt Flag
If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it.
0
1
read-write
ADCHER
ADC_ADCHER
ADC Channel Enable Register
0x84
-1
read-write
n
0x0
0x0
CHEN
Analog Input Channel Enable Control
Set ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.
Besides, setting the ADCHER[29] bit will enable internal channel for band-gap voltage. Other bits are reserved.
Note: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300 KSPS.
0
32
read-write
0
Channel Disabled
0
1
Channel Enabled
1
ADCMPR0
ADC_ADCMPR0
ADC Compare Register 0
0x88
-1
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection
3
5
read-write
0
Channel 0 conversion result is selected to be compared
#00000
1
Channel 1 conversion result is selected to be compared
#00001
2
Channel 2 conversion result is selected to be compared
#00010
3
Channel 3 conversion result is selected to be compared
#00011
4
Channel 4 conversion result is selected to be compared
#00100
5
Channel 5 conversion result is selected to be compared
#00101
6
Channel 6 conversion result is selected to be compared
#00110
7
Channel 7 conversion result is selected to be compared
#00111
8
Channel 8 conversion result is selected to be compared
#01000
9
Channel 9 conversion result is selected to be compared
#01001
10
Channel 10 conversion result is selected to be compared
#01010
11
Channel 11 conversion result is selected to be compared
#01011
12
Channel 12 conversion result is selected to be compared
#01100
13
Channel 13 conversion result is selected to be compared
#01101
14
Channel 14 conversion result is selected to be compared
#01110
15
Channel 15 conversion result is selected to be compared
#01111
28
Floating detect channel conversion result is selected to be compared
#11100
29
Band-gap voltage conversion result is selected to be compared
#11101
CMPCOND
Compare Condition
Note: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one
#1
CMPD
Comparison Data
The 12-bit data is used to compare with conversion result of specified channel.
Note: CMPD bits should be filled in unsigned format (straight binary format).
16
12
read-write
CMPEN
Compare Enable Bit
Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable Bit
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
CMPWEN
Compare Window Mode Enable Bit
Note: This bit is only presented in ADCMPR0 register.
15
1
read-write
0
Compare Window Mode Disabled
#0
1
Compare Window Mode Enabled
#1
ADCMPR1
ADC_ADCMPR1
ADC Compare Register 1
0x8C
-1
read-write
n
0x0
0x0
ADCR
ADC_ADCR
ADC Control Register
0x80
-1
read-write
n
0x0
0x0
ADEN
A/D Converter Enable Bit
Note: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
0
1
read-write
0
A/D converter Disabled
#0
1
A/D converter Enabled
#1
ADIE
A/D Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADMD
A/D Converter Operation Mode Control
Note 1: When changing the operation mode, software should clear ADST bit first.
Note 2: In Burst mode, the A/D result data is always at ADC Data Register 0.
2
2
read-write
0
Single conversion
#00
1
Burst conversion
#01
2
Single-cycle Scan
#10
3
Continuous Scan
#11
ADST
A/D Conversion Start or Calibration Start
ADST bit can be set to 1 from four sources: software, external pin STADC, BPWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
11
1
read-write
0
Conversion stops and A/D converter enters idle state
#0
1
Conversion or calibration starts
#1
DIFFEN
Differential Input Mode Control
Note: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
10
1
read-write
0
Single-end analog input mode
#0
1
Differential analog input mode
#1
DMOF
Differential Input Mode Output Format
If differential input mode is enabled, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
31
1
read-write
0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format)
#0
1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format
#1
PTEN
PDMA Transfer Enable Bit
When A/D conversion is completed, the converted data is loaded into ADDR0~15, ADDR29. Software can enable this bit to generate a PDMA data transfer request.
9
1
read-write
0
PDMA data transfer Disabled
#0
1
PDMA data transfer in ADDR0~15, ADDR29 Enabled
#1
RESET
ADC RESET (Write Protect)
If user writes this bit, the ADC analog macro will reset. Calibration data in macro will be deleted, but registers in ADC controller will keep.
Note: This bit is cleared by hardware.
12
1
read-write
TRGCOND
External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
6
2
read-write
0
Low level
#00
1
High level
#01
2
Falling edge
#10
3
Rising edge
#11
TRGEN
External Trigger Enable Bit
Enable or disable triggering of A/D conversion by external STADC pin, BPWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.
Note: The ADC external trigger function is only supported in Single-cycle Scan mode.
8
1
read-write
0
External trigger Disabled
#0
1
External trigger Enabled
#1
TRGS
Hardware Trigger Source
Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
1
Timer0 ~ Timer5 overflow pulse trigger
#01
2
A/D conversion is started by BPWM trigger
#10
3
Reserved.
#11
ADDR0
ADC_ADDR0
ADC Data Register 0
0x0
-1
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)
If converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
16
1
read-only
0
Data in RSLT bits is not overwritten
#0
1
Data in RSLT bits is overwritten
#1
RSLT
A/D Conversion Result (Read Only)
This field contains conversion result of ADC.
0
16
read-only
VALID
Valid Flag (Read Only)
This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
17
1
read-only
0
Data in RSLT bits is not valid
#0
1
Data in RSLT bits is valid
#1
ADDR1
ADC_ADDR1
ADC Data Register 1
0x4
-1
read-write
n
0x0
0x0
ADDR10
ADC_ADDR10
ADC Data Register 10
0x28
-1
read-write
n
0x0
0x0
ADDR11
ADC_ADDR11
ADC Data Register 11
0x2C
-1
read-write
n
0x0
0x0
ADDR12
ADC_ADDR12
ADC Data Register 12
0x30
-1
read-write
n
0x0
0x0
ADDR13
ADC_ADDR13
ADC Data Register 13
0x34
-1
read-write
n
0x0
0x0
ADDR14
ADC_ADDR14
ADC Data Register 14
0x38
-1
read-write
n
0x0
0x0
ADDR15
ADC_ADDR15
ADC Data Register 15
0x3C
-1
read-write
n
0x0
0x0
ADDR2
ADC_ADDR2
ADC Data Register 2
0x8
-1
read-write
n
0x0
0x0
ADDR29
ADC_ADDR29
ADC Data Register 29
0x74
-1
read-write
n
0x0
0x0
ADDR3
ADC_ADDR3
ADC Data Register 3
0xC
-1
read-write
n
0x0
0x0
ADDR4
ADC_ADDR4
ADC Data Register 4
0x10
-1
read-write
n
0x0
0x0
ADDR5
ADC_ADDR5
ADC Data Register 5
0x14
-1
read-write
n
0x0
0x0
ADDR6
ADC_ADDR6
ADC Data Register 6
0x18
-1
read-write
n
0x0
0x0
ADDR7
ADC_ADDR7
ADC Data Register 7
0x1C
-1
read-write
n
0x0
0x0
ADDR8
ADC_ADDR8
ADC Data Register 8
0x20
-1
read-write
n
0x0
0x0
ADDR9
ADC_ADDR9
ADC Data Register 9
0x24
-1
read-write
n
0x0
0x0
ADPDMA
ADC_ADPDMA
ADC PDMA Current Transfer Data Register
0x100
-1
read-only
n
0x0
0x0
CURDAT
ADC PDMA Current Transfer Data Register (Read Only)
When PDMA transferring, read this register can monitor current PDMA transfer data.
Current PDMA transfer data could be the content of ADDR0 ~ ADDR15, and ADDR29 registers.
0
18
read-only
ADSR0
ADC_ADSR0
ADC Status Register0
0x90
-1
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag
A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.
The ADF bit is set to 1 at the following three conditions:
When A/D conversion ends in Single mode.
When A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.
When more than or equal to 4 samples in FIFO in Burst mode.
0
1
read-write
BUSY
BUSY/IDLE (Read Only)
This bit is a mirror of ADST bit in ADCR register.
7
1
read-only
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
27
5
read-only
CMPF0
Compare Flag 0
When the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
1
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
CMPF1
Compare Flag 1
When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register, this bit is set to 1 it is cleared by writing 1 to it
2
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
OVERRUNF
Overrun Flag (Read Only)
If any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.
Note: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
16
1
read-only
PWURDY
ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
24
1
read-only
0
ADC is not ready for conversion may be in power down state or in the progress of start up
#0
1
ADC is ready for conversion
#1
VALIDF
Data Valid Flag (Read Only)
If any one of VALID (ADDRx[17]) is set, this flag will be set to 1.
Note: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
8
1
read-only
ADSR1
ADC_ADSR1
ADC Status Register1
0x94
-1
read-only
n
0x0
0x0
VALID
Data Valid Flag (Read Only)
VALID[29, 15:0] are the mirror of the VALID bits in ADDR29[17], ADDR15[17]~ ADDR0[17]. The other bits are reserved.
Note: When ADC is in burst mode and any conversion result is valid, VALID[29, 15:0] will be set to 1.
0
32
read-only
ADSR2
ADC_ADSR2
ADC Status Register2
0x98
-1
read-only
n
0x0
0x0
OVERRUN
Overrun Flag (Read Only)
OVERRUN[29, 15:0] are the mirror of the OVERRUN bit in ADDR29[16], ADDR15[16] ~ ADDR0[16]. The other bits are reserved.
Note: When ADC is in burst mode and the FIFO is overrun, OVERRUN[29, 15:0] will be set to 1.
0
32
read-only
CFDCTL
ADC_CFDCTL
ADC Channel Floating Detect Control Register
0xA4
-1
read-write
n
0x0
0x0
DISCHEN
Discharge Enable Bit
Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are both enabled.
1
1
read-write
0
Channel discharge Disabled
#0
1
Channel discharge Enabled
#1
FDETCHEN
Floating Detect Channel Enable Bit
Note: if FDETCHEN is enabled, internal channel is always turned on.
8
1
read-write
0
Floating Detect Channel Disabled
#0
1
Floating Detect Channel Enabled
#1
PRECHEN
Precharge Enable Bit
Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are both enabled.
0
1
read-write
0
Channel precharge Disabled
#0
1
Channel precharge Enabled
#1
ESMPCTL
ADC_ESMPCTL
ADC Extend Sample Time Control Register
0xA0
-1
read-write
n
0x0
0x0
EXTSMPT
ADC Sampling Time Extend
When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
0
8
read-write
BPWM1
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF4
0xC
registers
n
BPWM_ADCTS0
BPWM_ADCTS0
BPWM Trigger ADC Source Select Register 0
0xF8
-1
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH0 Trigger EADC function Disabled
#0
1
BPWM_CH0 Trigger EADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH1 Trigger EADC function Disabled
#0
1
BPWM_CH1 Trigger EADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
BPWM_CH2 Trigger EADC function Disabled
#0
1
BPWM_CH2 Trigger EADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
BPWM_CH3 Trigger EADC function Disabled
#0
1
BPWM_CH3 Trigger EADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger ADC Source Select
Others reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger ADC Source Select
Others reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
BPWM_ADCTS1
BPWM_ADCTS1
BPWM Trigger ADC Source Select Register 1
0xFC
-1
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
BPWM_CH4 Trigger EADC function Disabled
#0
1
BPWM_CH4 Trigger EADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
BPWM_CH5 Trigger EADC function Disabled
#0
1
BPWM_CH5 Trigger EADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger ADC Source Select
Others reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger ADC Source Select
Others reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
-1
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
Each bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
-1
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
-1
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Note: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
-1
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
-1
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
-1
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale
The clock of BPWM counter is decided by clock prescaler. All BPWM channels share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
-1
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWM1_CLK
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
5
TIMER4 overflow
#101
6
TIMER5 overflow
#110
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
-1
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)
Used as CMP active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
-1
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
-1
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
-1
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
-1
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
-1
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
-1
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register
CMPDAT is used to compare with CNT to generate BPWM waveform, interrupt and trigger ADC.
In independent mode, CMPDAT0~5 are denoted as 6 independent BPWM_CH0~5 compared points.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
-1
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
-1
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
-1
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
-1
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
-1
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
-1
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)
User can monitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is Down counting
#0
1
Counter is UP counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
-1
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0
It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
-1
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
-1
read-write
n
0x0
0x0
CTRLD0
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load
Each bit n controls the corresponding BPWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)
BPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bits
Each bit n controls the corresponding BPWM channel n.
Note: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
-1
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0
Each bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_DACTRGEN
BPWM_DACTRGEN
BPWM Trigger DAC Enable Register
0xF4
-1
read-write
n
0x0
0x0
CDTRGE0
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
24
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CDTRGE1
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
25
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CDTRGE2
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
26
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CDTRGE3
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
27
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CDTRGE4
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
28
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CDTRGE5
BPWM Compare Down Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to CMP if this bit is set to1.
Note 1: This bit should keep at 0 when BPWM counter operating in up counter type.
Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
29
1
read-write
0
BPWM Compare Down count point trigger DAC function Disabled
#0
1
BPWM Compare Down count point trigger DAC function Enabled
#1
CUTRGE0
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
16
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
CUTRGE1
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
17
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
CUTRGE2
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
18
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
CUTRGE3
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
19
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
CUTRGE4
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
20
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
CUTRGE5
BPWM Compare Up Count Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to CMP if this bit is set to1.
Note: This bit should keep at 0 when BPWM counter operating in down counter type..
21
1
read-write
0
BPWM Compare Up point trigger DAC function Disabled
#0
1
BPWM Compare Up point trigger DAC function Enabled
#1
PTE
BPWM Period Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter counts up to (PERIODn+1) if this bit is set to1.
8
1
read-write
0
BPWM period point trigger DAC function Disabled
#0
1
BPWM period point trigger DAC function Enabled
#1
ZTE
BPWM Zero Point Trigger DAC Enable Bits
BPWM can trigger DAC to start action when BPWM counter down count to zero if this bit is set to1.
0
1
read-write
0
BPWM period point trigger DAC function Disabled
#0
1
BPWM period point trigger DAC function Enabled
#1
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
-1
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)
When falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
-1
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
-1
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
-1
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit
Note: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
-1
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding BPWM channel n.
Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n
Note: If CMPDAT is equal to PERIOD, this flag is not working in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag
Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.
Note: If CMPDAT is equal to PERIOD, this flag is not working in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag
This bit is set by hardware when BPWM counter reaches BPWM_PERIOD, software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag
This bit is set by hardware when BPWM counter reaches 0, software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
-1
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit
This data bit control the state of BPWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
-1
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits
Each bit n controls the corresponding BPWM channel n.
The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
-1
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)
Used as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
-1
read-write
n
0x0
0x0
PERIOD
BPWM Period Register
Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
-1
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits
Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
-1
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control
The register controls polarity state of BPWM output. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output polar inverse Disabled
#0
1
BPWM output polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
-1
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)
When rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
-1
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
-1
read-write
n
0x0
0x0
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
-1
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
16
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG1
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
17
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG2
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
18
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG3
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
19
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG4
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
20
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
ADCTRG5
ADC Start of Conversion Status
Each bit n controls the corresponding BPWM channel n.
21
1
read-write
0
No ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred. Software can write 1 to clear this bit
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value. Software can write 1 to clear this bit
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
-1
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
PRDPCTL1
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
PRDPCTL2
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
PRDPCTL3
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
PRDPCTL4
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
PRDPCTL5
BPWM Period Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter count to (PERIOD+1).
Note: This bit is center point control when BPWM counter is operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period point output Low
#01
2
BPWM period point output High
#10
3
BPWM period point output Toggle
#11
ZPCTL0
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL1
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL2
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL3
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL4
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
ZPCTL5
BPWM Zero Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
-1
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter down count to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control
Each bit n controls the corresponding BPWM channel n.
BPWM can control output level when BPWM counter up count to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CLK
CLK Register Map
CLK
0x0
0x0
0x1C
registers
n
0x20
0x4
registers
n
0x34
0x4
registers
n
0x40
0x4
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
-1
read-write
n
0x0
0x0
ADCCKEN
ADC Clock Enable Bit
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
13
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is reset by power on reset, Watchdog reset or software chip reset.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
-1
read-write
n
0x0
0x0
BPWM1CKEN
BPWM1 Clock Enable Bit
19
1
read-write
0
BPWM1 clock Disabled
#0
1
BPWM1 clock Enabled
#1
DAC01CKEN
DAC01 Clock Enable Bit
12
1
read-write
0
DAC01 clock Disabled
#0
1
DAC01 clock Enabled
#1
DAC23CKEN
DAC23 Clock Enable Bit
13
1
read-write
0
DAC23 clock Disabled
#0
1
DAC23 clock Enabled
#1
MANCHCKEN
Manchester Codec Clock Enable Bit
24
1
read-write
0
Manchester Codec clock Disabled
#0
1
Manchester Codec clock Enabled
#1
TMR4CKEN
Timer4 Clock Enable Bit
28
1
read-write
0
Timer4 clock Disabled
#0
1
Timer4 clock Enabled
#1
TMR5CKEN
Timer5 Clock Enable Bit
29
1
read-write
0
Timer5 clock Disabled
#0
1
Timer5 clock Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
-1
read-write
n
0x0
0x0
ADCDIV
ADC Clock Divide Number From ADC Clock Source
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
-1
read-write
n
0x0
0x0
CLKOEN
Clock Output Enable Bit
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection
The formula of output frequency is
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
0
3
read-write
2
Clock source from PLL
#010
7
Clock source from HIRC
#111
STCLKSEL
Cortex-M0 SysTick Clock Source Selection (Write Protect)
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
3
3
read-write
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/2
#111
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection
4
3
read-write
2
Clock source from HCLK
#010
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from internal low speed RC oscillator (LIRC)
#100
5
Clock source from internal high speed RC oscillator (HIRC)
#101
6
Clock source from PLL
#110
TMR0SEL
TIMER0 Clock Source Selection
8
3
read-write
2
Clock source from PCLK0
#010
3
Clock source from external clock T0 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection
12
3
read-write
2
Clock source from PCLK0
#010
3
Clock source from external clock T1 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR2SEL
TIMER2 Clock Source Selection
16
3
read-write
2
Clock source from PCLK1
#010
3
Clock source from external clock TM2 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR3SEL
TIMER3 Clock Source Selection
20
3
read-write
2
Clock source from PCLK1
#010
3
Clock source from external clock TM3 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
UART0SEL
UART0 Clock Source Selection
24
3
read-write
1
Clock source from PLL
#001
3
Clock source from internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from internal low speed RC oscillator (LIRC)
#101
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is force to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.
0
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection (Write Protect)
2
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from internal low speed RC oscillator (LIRC)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
-1
read-write
n
0x0
0x0
ADCSEL
ADC Clock Source Selection
20
2
read-write
1
Clock source from PLL
#01
2
Clock source from PCLK1
#10
3
Clock source from internal high speed RC oscillator (HIRC) clock
#11
BPWM1SEL
BPWM1 Clock Source Selection
The peripheral clock source of BPWM1 is defined by BPWM1SEL.
9
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK1
#1
SPI0SEL
SPI0 Clock Source Selection
4
2
read-write
1
Clock source from PLL
#01
2
Clock source from PCLK1
#10
3
Clock source from internal high speed RC oscillator (HIRC)
#11
TMR4SEL
TIMER4 Clock Source Selection
12
3
read-write
2
Clock source from PCLK0
#010
3
Clock source from external clock TM4 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
TMR5SEL
TIMER5 Clock Source Selection
16
3
read-write
2
Clock source from PCLK0
#010
3
Clock source from external clock TM5 pin
#011
5
Clock source from internal low speed RC oscillator (LIRC)
#101
7
Clock source from internal high speed RC oscillator (HIRC)
#111
PCLKDIV
CLK_PCLKDIV
APB Clock Divider Register
0x34
-1
read-write
n
0x0
0x0
APB0DIV
APB0 Clock Divider
APB0 clock can be divided from HCLK
Others: Reserved.
0
3
read-write
APB1DIV
APB1 Clock Divider
APB1 clock can be divided from HCLK
Others: Reserved.
4
3
read-write
PLLCTL
CLK_PLLCTL
PLL Control Register
0x40
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as PLL input clock FIN
#1
FBDIV
PLL Feedback Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
9
read-write
INDIV
PLL Input Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
5
read-write
OE
PLL OE Pin Control (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
2
read-write
PD
Power-down Mode (Write Protect)
If setting the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
STBSEL
PLL Stable Counter Selection (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
PLL stable time is 6144 PLL source clock (suitable for source clock equal to or less than 12 MHz )
#0
1
PLL stable time is 16128 PLL source clock (suitable for source clock greater than 12 MHz)
#1
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Internal high speed RC oscillator (HIRC) Disabled
#0
1
Internal high speed RC oscillator (HIRC) Enabled
#1
PDEN
System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, the HIRC will be disabled, but LIRC are not controlled by Power-down mode. If user disables LIRC before entering Power-down mode, this bit should be set after LIRC is disabled at least 50us.
The clocks of peripheral are not controlled by Power-down mode if the peripheral clock source is from LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip enters Power-down mode instantly or waits CPU sleep command WFI
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 512 clock cycles when chip works at internal high speed RC oscillator (HIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status
When set by 'Power-down wake-up event', it indicates that resume from Power-down mode.
The flag is set if any wake-up source occurred. Refer to Power Modes and Wake-up Sources section.
Note 1: Write 1 to clear the bit to 0.
Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
6
1
read-write
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
-1
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
Note: Write 1 to clear the bit to 0.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x14
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
-1
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results
This field indicates the CRC checksum result.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
-1
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHKSINIT
Checksum Initialization
Note: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value
#1
CHKSREV
Checksum Bit Order Reverse
This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CRCEN
CRC Channel Enable Bit
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRCMODE
CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
26
1
read-write
0
1's complement for CRC writes data in Disabled
#0
1
1's complement for CRC writes data in Enabled
#1
DATLEN
CPU Write Data Length
This field indicates the write data length.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.
Data length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse
This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC write data in Disabled
#0
1
Bit order reversed for CRC write data in Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
-1
read-write
n
0x0
0x0
DATA
CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
POLYNOMIAL
CRC_POLYNOMIAL
CRC Polynomial Register
0x10
-1
read-write
n
0x0
0x0
POLYNOMIAL
CRC Polynomial Value Results
This field indicates the value of CRC polynomial.
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
-1
read-write
n
0x0
0x0
SEED
CRC Seed Value
This field indicates the CRC seed value.
Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
0
32
read-write
DAC
DAC Register Map
DAC
0x0
0x0
0x18
registers
n
0x1C
0x4
registers
n
0x40
0x18
registers
n
0x60
0x80
registers
n
ADCTL0
DAC_ADCTL0
DAC Auto Data Control Register0
0x60
-1
read-write
n
0x0
0x0
AUTODATA
Data Input of Auto Data Generation Function
User software needs to write appropriate data value to these bits for DAC auto data generation.
0
12
read-write
ADCTL1
DAC_ADCTL1
DAC Auto Data Control Register1
0x64
-1
read-write
n
0x0
0x0
ADCTL10
DAC_ADCTL10
DAC Auto Data Control Register10
0x88
-1
read-write
n
0x0
0x0
ADCTL11
DAC_ADCTL11
DAC Auto Data Control Register11
0x8C
-1
read-write
n
0x0
0x0
ADCTL12
DAC_ADCTL12
DAC Auto Data Control Register12
0x90
-1
read-write
n
0x0
0x0
ADCTL13
DAC_ADCTL13
DAC Auto Data Control Register13
0x94
-1
read-write
n
0x0
0x0
ADCTL14
DAC_ADCTL14
DAC Auto Data Control Register14
0x98
-1
read-write
n
0x0
0x0
ADCTL15
DAC_ADCTL15
DAC Auto Data Control Register15
0x9C
-1
read-write
n
0x0
0x0
ADCTL16
DAC_ADCTL16
DAC Auto Data Control Register16
0xA0
-1
read-write
n
0x0
0x0
ADCTL17
DAC_ADCTL17
DAC Auto Data Control Register17
0xA4
-1
read-write
n
0x0
0x0
ADCTL18
DAC_ADCTL18
DAC Auto Data Control Register18
0xA8
-1
read-write
n
0x0
0x0
ADCTL19
DAC_ADCTL19
DAC Auto Data Control Register19
0xAC
-1
read-write
n
0x0
0x0
ADCTL2
DAC_ADCTL2
DAC Auto Data Control Register2
0x68
-1
read-write
n
0x0
0x0
ADCTL20
DAC_ADCTL20
DAC Auto Data Control Register20
0xB0
-1
read-write
n
0x0
0x0
ADCTL21
DAC_ADCTL21
DAC Auto Data Control Register21
0xB4
-1
read-write
n
0x0
0x0
ADCTL22
DAC_ADCTL22
DAC Auto Data Control Register22
0xB8
-1
read-write
n
0x0
0x0
ADCTL23
DAC_ADCTL23
DAC Auto Data Control Register23
0xBC
-1
read-write
n
0x0
0x0
ADCTL24
DAC_ADCTL24
DAC Auto Data Control Register24
0xC0
-1
read-write
n
0x0
0x0
ADCTL25
DAC_ADCTL25
DAC Auto Data Control Register25
0xC4
-1
read-write
n
0x0
0x0
ADCTL26
DAC_ADCTL26
DAC Auto Data Control Register26
0xC8
-1
read-write
n
0x0
0x0
ADCTL27
DAC_ADCTL27
DAC Auto Data Control Register27
0xCC
-1
read-write
n
0x0
0x0
ADCTL28
DAC_ADCTL28
DAC Auto Data Control Register28
0xD0
-1
read-write
n
0x0
0x0
ADCTL29
DAC_ADCTL29
DAC Auto Data Control Register29
0xD4
-1
read-write
n
0x0
0x0
ADCTL3
DAC_ADCTL3
DAC Auto Data Control Register3
0x6C
-1
read-write
n
0x0
0x0
ADCTL30
DAC_ADCTL30
DAC Auto Data Control Register30
0xD8
-1
read-write
n
0x0
0x0
ADCTL31
DAC_ADCTL31
DAC Auto Data Control Register31
0xDC
-1
read-write
n
0x0
0x0
ADCTL4
DAC_ADCTL4
DAC Auto Data Control Register4
0x70
-1
read-write
n
0x0
0x0
ADCTL5
DAC_ADCTL5
DAC Auto Data Control Register5
0x74
-1
read-write
n
0x0
0x0
ADCTL6
DAC_ADCTL6
DAC Auto Data Control Register6
0x78
-1
read-write
n
0x0
0x0
ADCTL7
DAC_ADCTL7
DAC Auto Data Control Register7
0x7C
-1
read-write
n
0x0
0x0
ADCTL8
DAC_ADCTL8
DAC Auto Data Control Register8
0x80
-1
read-write
n
0x0
0x0
ADCTL9
DAC_ADCTL9
DAC Auto Data Control Register9
0x84
-1
read-write
n
0x0
0x0
DAC0_ADGCTL
DAC0_ADGCTL
DAC0 Auto Data Generator Control Register
0x1C
-1
read-write
n
0x0
0x0
AUTOEN
DAC Auto Data Generation Mode Enable Bit
0
1
read-write
0
DAC auto data generation mode Disabled
#0
1
DAC auto data generation mode Enabled
#1
CPOSEL
Carrier Polarity Selection
1
1
read-write
0
Auto data update for DAC when MANCH_TXD data high
#0
1
Auto data update for DAC when MANCH_TXD data is low
#1
SAMPSEL
Sample Points Step Selection
2
2
read-write
0
No samples
#00
1
8 sample points per MANCH_TXD carrier cycle
#01
2
16 sample points per MANCH_TXD carrier cycle
#10
3
32 sample points per MANCH_TXD carrier cycle
#11
DAC0_CTL
DAC0_CTL
DAC0 Control Register
0x0
-1
read-write
n
0x0
0x0
BWSEL
DAC Data Bit-width Selection
14
2
read-write
0
Data is 12 bits
#00
1
Data is 8 bits
#01
BYPASS
Bypass Buffer Mode
8
1
read-write
0
Output voltage buffer Enabled
#0
1
Output voltage buffer Disabled
#1
DACEN
DAC Enable Bit
0
1
read-write
0
DAC Disabled
#0
1
DAC Enabled
#1
DACIEN
DAC Interrupt Enable Bit
1
1
read-write
0
DAC interrupt Disabled
#0
1
DAC interrupt Enabled
#1
DMAEN
DMA Mode Enable Bit
2
1
read-write
0
DMA mode Disabled
#0
1
DMA mode Enabled
#1
DMAURIEN
DMA Under-run Interrupt Enable Bit
3
1
read-write
0
DMA under-run interrupt Disabled
#0
1
DMA under-run interrupt Enabled
#1
ETRGSEL
External Pin Trigger Selection
12
2
read-write
0
Low level trigger
#00
1
High level trigger
#01
2
Falling edge trigger
#10
3
Rising edge trigger
#11
GRPEN
DAC Group Mode Enable Bit
16
1
read-write
0
DAC0 and DAC1 are not grouped
#0
1
DAC0 and DAC1 are grouped
#1
LALIGN
DAC Data Left-aligned Enabled Bit
10
1
read-write
0
Right alignment
#0
1
Left alignment
#1
RETEN
DAC Reset Retention Select (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit only exists in DAC0 control register to control 4 DAC retention.
24
1
read-write
0
DAC controller registers reset by POR, NRESET, WDT, LVR, BOD, Lockup, CHIP and MCU reset sources
#0
1
DAC controller registers reset by POR, LVR, BOD and Lockup reset sources
#1
TRGEN
Trigger Mode Enable Bit
4
1
read-write
0
DAC event trigger mode Disabled
#0
1
DAC event trigger mode Enabled
#1
TRGSEL
Trigger Source Selection
5
3
read-write
0
Software trigger
#000
1
Timer 2 trigger
#001
2
Timer 0 trigger
#010
3
Timer 1 trigger
#011
4
Timer 3 trigger
#100
5
Timer 4 trigger
#101
6
BPWM 1 trigger
#110
7
Timer 5 trigger
#111
DAC0_DAT
DAC0_DAT
DAC0 Data Holding Register
0x8
-1
read-write
n
0x0
0x0
DACDAT
DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC0_DAT[3:0] in left-alignment mode and DAC0_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12-bit left alignment: user has to load data into DAC0_DAT[15:4] bits.
12-bit right alignment: user has to load data into DAC0_DAT[11:0] bits.
0
16
read-write
DAC0_DATOUT
DAC0_DATOUT
DAC0 Data Output Register
0xC
-1
read-only
n
0x0
0x0
DATOUT
DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC0_DAT register and user cannot write it directly.
0
12
read-only
DAC0_STATUS
DAC0_STATUS
DAC0 Status Register
0x10
-1
read-write
n
0x0
0x0
BUSY
DAC Busy Flag (Read Only)
8
1
read-only
0
DAC is ready for next conversion
#0
1
DAC is busy in conversion
#1
DMAUDR
DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
No DMA under-run error condition occurred
#0
1
DMA under-run error condition occurred
#1
FINISH
DAC Conversion Complete Finish Flag
Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
0
1
read-write
0
DAC is in conversion state
#0
1
DAC conversion finish
#1
DAC0_SWTRG
DAC0_SWTRG
DAC0 Software Trigger Control Register
0x4
-1
read-write
n
0x0
0x0
SWTRG
Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
0
1
read-write
0
Software trigger Disabled
#0
1
Software trigger Enabled
#1
DAC0_TCTL
DAC0_TCTL
DAC0 Timing Control Register
0x14
-1
read-write
n
0x0
0x0
SETTLET
DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles
0
10
read-write
DAC1_CTL
DAC1_CTL
DAC1 Control Register
0x40
-1
read-write
n
0x0
0x0
BWSEL
DAC Data Bit-width Selection
14
2
read-write
0
Data is 12 bits
#00
1
Data is 8 bits
#01
BYPASS
Bypass Buffer Mode
8
1
read-write
0
Output voltage buffer Enabled
#0
1
Output voltage buffer Disabled
#1
DACEN
DAC Enable Bit
0
1
read-write
0
DAC Disabled
#0
1
DAC Enabled
#1
DACIEN
DAC Interrupt Enable Bit
1
1
read-write
0
DAC interrupt Disabled
#0
1
DAC interrupt Enabled
#1
DMAEN
DMA Mode Enable Bit
2
1
read-write
0
DMA mode Disabled
#0
1
DMA mode Enabled
#1
DMAURIEN
DMA Under-run Interrupt Enable Bit
3
1
read-write
0
DMA under-run interrupt Disabled
#0
1
DMA under-run interrupt Enabled
#1
ETRGSEL
External Pin Trigger Selection
12
2
read-write
0
Low level trigger
#00
1
High level trigger
#01
2
Falling edge trigger
#10
3
Rising edge trigger
#11
LALIGN
DAC Data Left-aligned Enable Control
10
1
read-write
0
Right alignment
#0
1
Left alignment
#1
TRGEN
Trigger Mode Enable Bit
4
1
read-write
0
DAC event trigger mode Disabled
#0
1
DAC event trigger mode Enabled
#1
TRGSEL
Trigger Source Selection
5
3
read-write
0
Software trigger
#000
1
Timer 2 trigger
#001
2
Timer 0 trigger
#010
3
Timer 1 trigger
#011
4
Timer 3 trigger
#100
5
Timer 4 trigger
#101
6
BPWM 1 trigger
#110
7
Timer 5 trigger
#111
DAC1_DAT
DAC1_DAT
DAC1 Data Holding Register
0x48
-1
read-write
n
0x0
0x0
DACDAT
DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC1_DAT[3:0] in left-alignment mode and DAC1_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12-bit left alignment: user has to load data into DAC1_DAT[15:4] bits.
12-bit right alignment: user has to load data into DAC1_DAT[11:0] bits.
0
16
read-write
DAC1_DATOUT
DAC1_DATOUT
DAC1 Data Output Register
0x4C
-1
read-only
n
0x0
0x0
DATOUT
DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC1_DAT register and user cannot write it directly.
0
12
read-only
DAC1_STATUS
DAC1_STATUS
DAC1 Status Register
0x50
-1
read-write
n
0x0
0x0
BUSY
DAC Busy Flag (Read Only)
8
1
read-only
0
DAC is ready for the next conversion
#0
1
DAC is busy in conversion
#1
DMAUDR
DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
No DMA under-run error condition occurred
#0
1
DMA under-run error condition occurred
#1
FINISH
DAC Conversion Complete Finish Flag
Note: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
0
1
read-write
0
DAC is in conversion state
#0
1
DAC conversion finished
#1
DAC1_SWTRG
DAC1_SWTRG
DAC1 Software Trigger Control Register
0x44
-1
read-write
n
0x0
0x0
SWTRG
Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically Reading this bit will always get 0.
0
1
read-write
0
Software trigger Disabled
#0
1
Software trigger Enabled
#1
DAC1_TCTL
DAC1_TCTL
DAC1 Timing Control Register
0x54
-1
read-write
n
0x0
0x0
SETTLET
DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion settling time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles
0
10
read-write
DAC2
DAC Register Map
DAC
0x0
0x0
0x18
registers
n
0x40
0x18
registers
n
CTL
DAC2_CTL
DAC2 Control Register
0x0
-1
read-write
n
0x0
0x0
BWSEL
DAC Data Bit-width Selection
14
2
read-write
0
Data is 12 bits
#00
1
Data is 8 bits
#01
BYPASS
Bypass Buffer Mode
8
1
read-write
0
Output voltage buffer Enabled
#0
1
Output voltage buffer Disabled
#1
DACEN
DAC Enable Bit
0
1
read-write
0
DAC Disabled
#0
1
DAC Enabled
#1
DACIEN
DAC Interrupt Enable Bit
1
1
read-write
0
DAC interrupt Disabled
#0
1
DAC interrupt Enabled
#1
DMAEN
DMA Mode Enable Bit
2
1
read-write
0
DMA mode Disabled
#0
1
DMA mode Enabled
#1
DMAURIEN
DMA Under-run Interrupt Enable Bit
3
1
read-write
0
DMA under-run interrupt Disabled
#0
1
DMA under-run interrupt Enabled
#1
ETRGSEL
External Pin Trigger Selection
12
2
read-write
0
Low level trigger
#00
1
High level trigger
#01
2
Falling edge trigger
#10
3
Rising edge trigger
#11
GRPEN
DAC Group Mode Enable Bit
16
1
read-write
0
DAC2 and DAC3 are not grouped
#0
1
DAC2 and DAC3 are grouped
#1
LALIGN
DAC Data Left-aligned Enabled Bit
10
1
read-write
0
Right alignment
#0
1
Left alignment
#1
RETEN
DAC Reset Retention Select (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit only exists in DAC0 control register to control 4 DAC retention.
24
1
read-write
0
DAC controller registers reset by POR, NRESET, WDT, LVR, BOD, Lockup, CHIP and MCU reset sources
#0
1
DAC controller registers reset by POR, LVR, BOD and Lockup reset sources
#1
TRGEN
Trigger Mode Enable Bit
4
1
read-write
0
DAC event trigger mode Disabled
#0
1
DAC event trigger mode Enabled
#1
TRGSEL
Trigger Source Selection
5
3
read-write
0
Software trigger
#000
1
Timer 2 trigger
#001
2
Timer 0 trigger
#010
3
Timer 1 trigger
#011
4
Timer 3 trigger
#100
5
Timer 4 trigger
#101
6
BPWM 1 trigger
#110
7
Timer 5 trigger
#111
DAC3_CTL
DAC3_CTL
DAC3 Control Register
0x40
-1
read-write
n
0x0
0x0
BWSEL
DAC Data Bit-width Selection
14
2
read-write
0
Data is 12 bits
#00
1
Data is 8 bits
#01
BYPASS
Bypass Buffer Mode
8
1
read-write
0
Output voltage buffer Enabled
#0
1
Output voltage buffer Disabled
#1
DACEN
DAC Enable Bit
0
1
read-write
0
DAC Disabled
#0
1
DAC Enabled
#1
DACIEN
DAC Interrupt Enable Bit
1
1
read-write
0
DAC interrupt Disabled
#0
1
DAC interrupt Enabled
#1
DMAEN
DMA Mode Enable Bit
2
1
read-write
0
DMA mode Disabled
#0
1
DMA mode Enabled
#1
DMAURIEN
DMA Under-run Interrupt Enable Bit
3
1
read-write
0
DMA under-run interrupt Disabled
#0
1
DMA under-run interrupt Enabled
#1
ETRGSEL
External Pin Trigger Selection
12
2
read-write
0
Low level trigger
#00
1
High level trigger
#01
2
Falling edge trigger
#10
3
Rising edge trigger
#11
LALIGN
DAC Data Left-aligned Enable Control
10
1
read-write
0
Right alignment
#0
1
Left alignment
#1
TRGEN
Trigger Mode Enable Bit
4
1
read-write
0
DAC event trigger mode Disabled
#0
1
DAC event trigger mode Enabled
#1
TRGSEL
Trigger Source Selection
5
3
read-write
0
Software trigger
#000
1
Timer 2 trigger
#001
2
Timer 0 trigger
#010
3
Timer 1 trigger
#011
4
Timer 3 trigger
#100
5
Timer 4 trigger
#101
6
BPWM 1 trigger
#110
7
Timer 5 trigger
#111
DAC3_DAT
DAC3_DAT
DAC3 Data Holding Register
0x48
-1
read-write
n
0x0
0x0
DACDAT
DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC3_DAT[3:0] in left-alignment mode and DAC3_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12 bit left alignment: user has to load data into DAC3_DAT[15:4] bits.
12 bit right alignment: user has to load data into DAC3_DAT[11:0] bits.
0
16
read-write
DAC3_DATOUT
DAC3_DATOUT
DAC3 Data Output Register
0x4C
-1
read-only
n
0x0
0x0
DATOUT
DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC3_DAT register and user cannot write it directly.
0
12
read-only
DAC3_STATUS
DAC3_STATUS
DAC3 Status Register
0x50
-1
read-write
n
0x0
0x0
BUSY
DAC Busy Flag (Read Only)
8
1
read-only
0
DAC is ready for the next conversion
#0
1
DAC is busy in conversion
#1
DMAUDR
DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
No DMA under-run error condition occurred
#0
1
DMA under-run error condition occurred
#1
FINISH
DAC Conversion Complete Finish Flag
Note: This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
0
1
read-write
0
DAC is in conversion state
#0
1
DAC conversion finished
#1
DAC3_SWTRG
DAC3_SWTRG
DAC3 Software Trigger Control Register
0x44
-1
read-write
n
0x0
0x0
SWTRG
Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
0
1
read-write
0
Software trigger Disabled
#0
1
Software trigger Enabled
#1
DAC3_TCTL
DAC3_TCTL
DAC3 Timing Control Register
0x54
-1
read-write
n
0x0
0x0
SETTLET
DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion settling time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output conversion cycles is SETTLET + 1 PCLK cycles.
0
10
read-write
DAT
DAC2_DAT
DAC2 Data Holding Register
0x8
-1
read-write
n
0x0
0x0
DACDAT
DAC 12-bit Holding Data
These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC2_DAT[3:0] in left-alignment mode and DAC2_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
12 bit left alignment: user has to load data into DAC2_DAT[15:4] bits.
12 bit right alignment: user has to load data into DAC2_DAT[11:0] bits.
0
16
read-write
DATOUT
DAC2_DATOUT
DAC2 Data Output Register
0xC
-1
read-only
n
0x0
0x0
DATOUT
DAC 12-bit Output Data
These bits are current digital data for DAC output conversion.
It is loaded from DAC2_DAT register and user cannot write it directly.
0
12
read-only
STATUS
DAC2_STATUS
DAC2 Status Register
0x10
-1
read-write
n
0x0
0x0
BUSY
DAC Busy Flag (Read Only)
8
1
read-only
0
DAC is ready for next conversion
#0
1
DAC is busy in conversion
#1
DMAUDR
DMA Under-run Interrupt Flag
Note: Write 1 to clear this bit.
1
1
read-write
0
No DMA under-run error condition occurred
#0
1
DMA under-run error condition occurred
#1
FINISH
DAC Conversion Complete Finish Flag
Note: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. Write 1 to clear this bit to 0.
0
1
read-write
0
DAC is in conversion state
#0
1
DAC conversion finish
#1
SWTRG
DAC2_SWTRG
DAC2 Software Trigger Control Register
0x4
-1
read-write
n
0x0
0x0
SWTRG
Software Trigger
Note: Writing this bit will generate one shot pulse and this bit is cleared to 0 by hardware automatically reading this bit will always get 0.
0
1
read-write
0
Software trigger Disabled
#0
1
Software trigger Enabled
#1
TCTL
DAC2_TCTL
DAC2 Timing Control Register
0x14
-1
read-write
n
0x0
0x0
SETTLET
DAC Output Conversion Cycles
User software needs to write appropriate value to these bits to meet DAC conversion settling time based on PCLK (APB clock) speed.
For example, DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us, and SETTLET value must be greater than 0x48.
Note: The DAC output Conversion cycles is SETTLET + 1 PCLK cycles.
0
10
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
DFBA
FMC_DFBA
Data Flash Base Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address (Read Only)
This register indicates Data Flash start address.
The Data Flash is shared with APROM. The content of this register is loaded from CONFIG1.
0
32
read-only
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
-1
read-write
n
0x0
0x0
FOM
Frequency Optimization Mode (Write Protect)
This chip supports adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.
For 32/64 Kbytes Flash:
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
3
read-write
0
Frequency is less than or equal to 48 MHz
#000
1
Frequency is less than or equal to 24 MHz
#001
5
Frequency is less than or equal to 72 MHz
#101
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
-1
read-write
n
0x0
0x0
ISPADDR
ISP Address
This chip is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
32/64 Kbytes Flash:
ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
-1
read-write
n
0x0
0x0
CMD
ISP CMD
ISP command table is shown below:
The other commands are invalid.
0
7
read-write
0
Flash Read
0x00
4
Read Unique ID
0x04
11
Read Company ID
0x0b
13
Read CRC32 Checksum
0x0d
33
Flash 32-bit Program
0x21
34
Flash Page Erase
0x22
45
Run CRC32 Checksum Calculation
0x2d
46
Vector Remap
0x2e
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
-1
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Selection (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Booting from APROM
#0
1
Booting from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
ISPEN
ISP Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
Code is executed from APROM and tries to write APROM if APUEN is set to 0.
Code is executed from LDROM and tries to write LDROM if LDUEN is set to 0.
CONFIG is erased/programmed if CFGUEN is set to 0.
SPROM is erased/programmed if SPUEN is set to 0.
SPROM is programmed at SPROM secured mode.
Page Erase command at LOCK mode with ICE connection.
Erase or Program command at brown-out detected.
Destination address is illegal, such as over an available range.
Invalid ISP commands.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)
LDROM update enable bit.
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
SPUEN
SPROM Update Enable Bit (Write Protect)
Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
SPROM cannot be updated
#0
1
SPROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
-1
read-write
n
0x0
0x0
ISPDAT
ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
-1
read-write
n
0x0
0x0
CBS
Boot Selection of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
ISPBUSY
ISP BUSY (Read Only)
0
1
read-only
0
ISP operation is finished
#0
1
ISP operation is busy
#1
ISPFF
ISP Fail Flag (Write Protect)
This bit is set by hardware when user triggers ISPGO (FMC_ISPTRG[0]) and meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
Code is executed from APROM and tries to write APROM if APUEN is set to 0.
Code is executed from LDROM and tries to write LDROM if LDUEN is set to 0.
CONFIG is erased/programmed if CFGUEN is set to 0.
SPROM is erased/programmed if SPUEN is set to 0.
SPROM is programmed at SPROM secured mode.
Page Erase command at LOCK mode with ICE connection.
Erase or Program command at brown-out detected.
Destination address is illegal, such as over an available range.
Invalid ISP commands.
6
1
read-write
SCODE
Security Code Active Flag
This bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
31
1
read-write
0
SPROM secured code is inactive
#0
1
SPROM secured code is active
#1
VECMAP
Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.
VECMAP [18:12] should be 0.
9
21
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
-1
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed.Note: This bit is write-protected. Refer to the SYS_REGLCTL register
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x140
0x24
registers
n
0x170
0x4
registers
n
0x30
0x4
registers
n
0x40
0x24
registers
n
0x440
0x8
registers
n
0x70
0x4
registers
n
0x80
0x24
registers
n
0x800
0xBC
registers
n
0x940
0x40
registers
n
0xB0
0x4
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC)
#1
ICLKON
Interrupt Clock on Mode
Note: It is recommended to disable this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
-1
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output
Writing this bit can control one GPIO pin output value.
Read this register to get GPIO pin status.
For example, writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).
Note 1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
-1
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
-1
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output Register
0x830
-1
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output Register
0x834
-1
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output Register
0x838
-1
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output Register
0x83C
-1
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
-1
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
-1
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
-1
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
-1
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
-1
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
-1
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
-1
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
-1
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
-1
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
-1
read-write
n
0x0
0x0
DATMSK0
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A,B,C,F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.
Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control Register
0x14
-1
read-write
n
0x0
0x0
DBEN0
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A,B,C,F Pin[n] Input Signal De-bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
-1
read-write
n
0x0
0x0
DINOFF0
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A,B,C,F Pin[n] Digital Input Path Disable Bit
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A,B,C,F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
-1
read-write
n
0x0
0x0
FLIEN0
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A,B,C,F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A,B,C,F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Setting the bit to 1 also enables the pin wake-up function.
When setting the RHIEN (Px_INTEN[n+16]) bit to 1:
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
-1
read-write
n
0x0
0x0
INTSRC0
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC1
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC10
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC11
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC12
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC13
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC14
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC15
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC2
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC3
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC4
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC5
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC6
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC7
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC8
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
INTSRC9
Port A,B,C,F Pin[n] Interrupt Source Flag
Write Operation:
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
No action.
No interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.
Px.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
-1
read-write
n
0x0
0x0
TYPE0
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A,B,C,F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
-1
read-write
n
0x0
0x0
MODE0
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A,B,C,F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
-1
read-only
n
0x0
0x0
PIN0
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
0
1
read-only
PIN1
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
1
1
read-only
PIN10
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
10
1
read-only
PIN11
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
11
1
read-only
PIN12
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
12
1
read-only
PIN13
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
13
1
read-only
PIN14
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
14
1
read-only
PIN15
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
15
1
read-only
PIN2
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
2
1
read-only
PIN3
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
3
1
read-only
PIN4
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
4
1
read-only
PIN5
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
5
1
read-only
PIN6
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
6
1
read-only
PIN7
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
7
1
read-only
PIN8
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
8
1
read-only
PIN9
Port A,B,C,F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
Note: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ignored.
9
1
read-only
PA_PUSEL
PA_PUSEL
PA Pull-up Selection Register
0x30
-1
read-write
n
0x0
0x0
PUSEL0
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
0
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL1
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
1
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL10
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
10
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL11
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
11
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL12
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
12
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL13
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
13
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL14
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
14
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL15
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
15
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL2
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
2
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL3
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
3
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL4
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
4
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL5
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
5
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL6
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
6
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL7
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
7
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL8
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
8
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PUSEL9
Port A,B,C,F Pin[n] Pull-up Enable Register
Determine each I/O Pull-up of Px.n pins.
Note 1: The independent pull-up control register is only valid when MODEn is set as tri-state and open-drain mode.
Note 2: The PA.4~PA.11/PC.0/PC.2~PC.15/PF.1/PF.4~PF.15 pin is ineffective.
9
1
read-write
0
Px.n pull-up Disabled
#0
1
Px.n pull-up Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
-1
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output Register
0x868
-1
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output Register
0x86C
-1
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output Register
0x870
-1
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output Register
0x874
-1
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output Register
0x878
-1
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output Register
0x87C
-1
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
-1
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
-1
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
-1
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
-1
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
-1
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output Register
0x858
-1
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output Register
0x85C
-1
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output Register
0x860
-1
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output Register
0x864
-1
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
-1
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control Register
0x54
-1
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
-1
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
-1
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x5C
-1
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
-1
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
-1
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
-1
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
-1
read-write
n
0x0
0x0
PB_PUSEL
PB_PUSEL
PB Pull-up Selection Register
0x70
-1
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output Register
0x880
-1
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A8
-1
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8AC
-1
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B0
-1
read-write
n
0x0
0x0
PC13_PDIO
PC13_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B4
-1
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B8
-1
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output Register
0x884
-1
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output Register
0x888
-1
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output Register
0x88C
-1
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output Register
0x890
-1
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output Register
0x894
-1
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output Register
0x898
-1
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output Register
0x89C
-1
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A0
-1
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A4
-1
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
-1
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control Register
0x94
-1
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
-1
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
-1
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x9C
-1
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
-1
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
-1
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
-1
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
-1
read-write
n
0x0
0x0
PC_PUSEL
PC_PUSEL
PC Pull-up Selection Register
0xB0
-1
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output Register
0x940
-1
read-write
n
0x0
0x0
PF10_PDIO
PF10_PDIO
GPIO PF.n Pin Data Input/Output Register
0x968
-1
read-write
n
0x0
0x0
PF11_PDIO
PF11_PDIO
GPIO PF.n Pin Data Input/Output Register
0x96C
-1
read-write
n
0x0
0x0
PF12_PDIO
PF12_PDIO
GPIO PF.n Pin Data Input/Output Register
0x970
-1
read-write
n
0x0
0x0
PF13_PDIO
PF13_PDIO
GPIO PF.n Pin Data Input/Output Register
0x974
-1
read-write
n
0x0
0x0
PF14_PDIO
PF14_PDIO
GPIO PF.n Pin Data Input/Output Register
0x978
-1
read-write
n
0x0
0x0
PF15_PDIO
PF15_PDIO
GPIO PF.n Pin Data Input/Output Register
0x97C
-1
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output Register
0x944
-1
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output Register
0x948
-1
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output Register
0x94C
-1
read-write
n
0x0
0x0
PF4_PDIO
PF4_PDIO
GPIO PF.n Pin Data Input/Output Register
0x950
-1
read-write
n
0x0
0x0
PF5_PDIO
PF5_PDIO
GPIO PF.n Pin Data Input/Output Register
0x954
-1
read-write
n
0x0
0x0
PF6_PDIO
PF6_PDIO
GPIO PF.n Pin Data Input/Output Register
0x958
-1
read-write
n
0x0
0x0
PF7_PDIO
PF7_PDIO
GPIO PF.n Pin Data Input/Output Register
0x95C
-1
read-write
n
0x0
0x0
PF8_PDIO
PF8_PDIO
GPIO PF.n Pin Data Input/Output Register
0x960
-1
read-write
n
0x0
0x0
PF9_PDIO
PF9_PDIO
GPIO PF.n Pin Data Input/Output Register
0x964
-1
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
-1
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control Register
0x154
-1
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
-1
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
-1
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable Control Register
0x15C
-1
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
-1
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Control
0x158
-1
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
-1
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
-1
read-write
n
0x0
0x0
PF_PUSEL
PF_PUSEL
PF Pull-up Selection Register
0x170
-1
read-write
n
0x0
0x0
RET
GPIO_RET
GPIO Retention Control Register
0x444
-1
read-write
n
0x0
0x0
RETEN
GPIO Reset Retention Select (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
GPIO registers can be reset by POR, NRESET, WDT, LVR, BOD, Lockup, CHIP, CPU, MCU and IP reset sources
#0
1
GPIO registers can be reset only by POR, LVR, BOD, Lockup and IP reset sources
#1
I2C0
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 7'h00, the address cannot be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 7'h00, the address cannot be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exactly the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exactly the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
DPBITSEL
Data Phase Bit Count Select
8
2
read-write
0
DPCIF never set by hardware
#00
1
When I2C is transfer data and bit count equal to 6, DPCIF will be set by hardware
#01
2
When I2C is transfer data and bit count equal to 7, DPCIF will be set by hardware
#10
3
When I2C is transfer data and bit count equal to 8, DPCIF will be set by hardware
#11
DPCIF
Data Phase Count Interrupt Flag
This bit is set by hardware when I2C transfer bit count is equal to DPBITSEL setting.
Note: This bit is cleared by writing 1 to it.
14
1
read-write
DPCINTEN
Data Phase Count Interrupt Enable Bit
12
1
read-write
0
Data Phase Count Interrupt Disabled
#0
1
Data Phase Count Interrupt Enabled
#1
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SARCIF
Slave Address Read Command Interrupt Flag
This bit is set by hardware when I2C receive address is matched with read command.
Note: This bit is cleared by writing 1 to it.
15
1
read-write
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
SRCINTEN
Slave Read Command Interrupt Enable Bit
13
1
read-write
0
Slave Read Command Interrupt Disabled
#0
1
Slave Read Command Interrupt Enabled
#1
STA
I2C START Control
Setting STA to logic 1 will enter Master mode, and the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO will transmit a STOP condition to bus and then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (Only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (Only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TWOBUFEN
Two-level BUFFER Enable Bit
Set to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus. It only support in slave mode.
5
1
read-write
0
Two-level buffer Disabled
#0
1
Two-level buffer Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ONBUSY
On Bus Busy (Read Only)
Indicate that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is idle (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not cleared. It may cause error data transmitted or received. If data transmitted or received when WKIF event is not cleared, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C holds bus after wake-up
#0
1
I2C does not hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit cannot release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame is not done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wake-up frame
#0
1
Read command be record on the address match wake-up frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x34
registers
n
0x3C
0x14
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 7'h00, the address cannot be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
-1
read-write
n
0x0
0x0
ADDR
I2C Address
The content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
Note: When software set 7'h00, the address cannot be used.
1
7
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
-1
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
-1
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
-1
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask
I2C bus controllers support multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exactly the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exactly the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
-1
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
-1
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
-1
read-write
n
0x0
0x0
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
-1
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided
Note: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
-1
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
DPBITSEL
Data Phase Bit Count Select
8
2
read-write
0
DPCIF never set by hardware
#00
1
When I2C is transfer data and bit count equal to 6, DPCIF will be set by hardware
#01
2
When I2C is transfer data and bit count equal to 7, DPCIF will be set by hardware
#10
3
When I2C is transfer data and bit count equal to 8, DPCIF will be set by hardware
#11
DPCIF
Data Phase Count Interrupt Flag
This bit is set by hardware when I2C transfer bit count is equal to DPBITSEL setting.
Note: This bit is cleared by writing 1 to it.
14
1
read-write
DPCINTEN
Data Phase Count Interrupt Enable Bit
12
1
read-write
0
Data Phase Count Interrupt Disabled
#0
1
Data Phase Count Interrupt Enabled
#1
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SARCIF
Slave Address Read Command Interrupt Flag
This bit is set by hardware when I2C receive address is matched with read command.
Note: This bit is cleared by writing 1 to it.
15
1
read-write
SI
I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
3
1
read-write
SRCINTEN
Slave Read Command Interrupt Enable Bit
13
1
read-write
0
Slave Read Command Interrupt Disabled
#0
1
Slave Read Command Interrupt Enabled
#1
STA
I2C START Control
Setting STA to logic 1 will enter Master mode, and the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control
In Master mode, setting STO will transmit a STOP condition to bus and then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (Only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (Only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TWOBUFEN
Two-level BUFFER Enable Bit
Set to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus. It only support in slave mode.
5
1
read-write
0
Two-level buffer Disabled
#0
1
Two-level buffer Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
-1
read-write
n
0x0
0x0
DAT
I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
-1
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
-1
read-write
n
0x0
0x0
ONBUSY
On Bus Busy (Read Only)
Indicate that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is idle (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
-1
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control
This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control
This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
Note: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
-1
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4
When enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit
When enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
-1
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit
Note: The I2C controller could respond when WKIF event is not cleared. It may cause error data transmitted or received. If data transmitted or received when WKIF event is not cleared, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C holds bus after wake-up
#0
1
I2C does not hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
-1
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done
Note: This bit cannot release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame is not done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)
Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wake-up frame
#0
1
Read command be record on the address match wake-up frame
#1
MANCH
Manchester Register Map
Manchester
0x0
0x0
0x8
registers
n
0xC
0x20
registers
n
BITCNT
MANCH_BITCNT
Manchester Bit Count Register
0x1C
-1
read-write
n
0x0
0x0
CRBITNUM
Manchester Current Receive Reference Frequency Number per Bit (Read Only)
The bits field indicates the current number of reference frequency (Bit_Ref_Clock) for each received bit.
16
8
read-only
RBERRTN
Manchester Receive Bit Error Tolerance Number
The bits field indicates the tolerance range of RBITNUM for received bit to detect the bit error event.
24
3
read-write
0
1/4 RBITNUM as the bit error tolerance
#000
1
1/8 RBITNUM as the bit error tolerance
#001
2
1/16 RBITNUM as the bit error tolerance
#010
3
1/32 RBITNUM as the bit error tolerance
#011
4
1/64 RBITNUM as the bit error tolerance
#100
5
1/128 RBITNUM as the bit error tolerance
#101
RBITNUM
Manchester Receive Reference Clock Number per Bit
The bits field indicates the number of reference clock (Bit_Ref_Clock) for received bit.
If there is not BITERR event, user can refer to the CRBITNUM to revise the RBITNUM.
Note 1: The value of this bits field cannot be 0x00 and the tolerance value must be not 3% than the received input bit rate. Otherwise, it cannot receive the correct input data on time.
Note 2: The bits can be updated at the start of next data frame if the RBNULEN is set to 1.
Note 3: It is suggested that the RBITNUM value is not less than 0x64.
8
8
read-write
TBITNUM
Manchester Transmit Reference Clock Number per Bit
The bits field indicates the number of reference clock (Bit_Ref_Clock) for transmit bit.
Note 1: The value of this bits field cannot be 0x00.
Note 2: It is suggested the TBITNUM value is not less than 0x64.
0
8
read-write
CTL
MANCH_CTL
Manchester Function Control Register
0x0
-1
read-write
n
0x0
0x0
BITREFDIV
Manchester Bit Reference Clock Divider
The bits field indicates the reference clock frequency for Manchester bit sample.
For example, if the PCLK0 is 72 MHz, the BITREFDIV can be set as 0x23 (BITREFDIV+1). It will generate 2 MHz reference clock frequency and the Manchester transmitting or receiving data is sampled with the reference divided clock.
Note 1: The BITREFDIV minimum value is 0x03.
Note 2: It is suggested that minimize the BITREFDIV value to make the TBITNUM or RTIBNUM value be greater than 0x64.
20
12
read-write
CRBNULEN
Current Received Bit Clock Number Auto Upload Enable Bit
11
1
read-write
0
CRBITNUM is not updated in each received byte during message receiving period
#0
1
CRBITNUM is updated in each received byte during message receiving period
#1
DEGDIV
Manchester Deglitch Clock Divider
The bits field indicates the deglitched clock frequency. The detail is described in Deglitch Selection section.
12
3
read-write
DEGSEL
Received Deglitch Selection
The bits field is used to define how much width of glitch would be filtered.
2
3
read-write
0
disable to the Manchester deglitch selection
#000
1
Filter the glitches that the width is 0.25us or less
#001
2
Filter the glitches that the width is 0.50us or less
#010
3
Filter the glitches that the width is 0.75us or less
#011
4
Filter the glitches that the width is 1.00us or less
#100
5
Filter the glitches that the width is 1.25us or less
#101
LSB
Manchester Code LSB First
Note: This bit should be configured before MODSEL
6
1
read-write
0
Manchester code is MSB first
#0
1
Manchester code is LSB first
#1
MANCHTEN
Manchester Transmit Enable
19
1
read-write
0
Manchester Transmit Disabled
#0
1
Manchester Transmit Enabled. It will be cleared to 0 after the data frame transmission done
#1
MECT
Manchester Encoding Type
Level 0: the signal is half cycle high and transfer to half cycle low
Level 1: the signal is half cycle low and transfer to half cycle high.
Note: Please refer to Figure 6.165.
5
1
read-write
0
G.E Thomas format
#0
1
IEEE 802.3 format
#1
MODESEL
Manchester Mode Selection
Note: All the change of function setting shall be during Manchester Controller disabled.
0
2
read-write
0
Manchester function is disabled
#00
1
Mode 1 modulation signal format is selected
#01
2
Mode 2 modulation signal format is selected
#10
3
The other modulation signal format is selected. (The register of MANCH_PREAM shall be set according to its frame information.)
#11
MTXE2TEN
Manchester Coded Edge Output Enable Bit
17
1
read-write
0
Manchester coded edge signal outputs to Timer Controller Disabled
#0
1
Manchester coded edge signal outputs to Timer Controller Enabled
#1
RBNULEN
Received Bit Clock Number Auto Upload Enable Bit
10
1
read-write
0
RBITNUM is not updated by CRBITNUM at each data frame beginning
#0
1
RBITNUM is updated by CRBITNUM at each data frame beginning
#1
RXINV
Receive Signal Invert
9
1
read-write
0
The received data is not inverted
#0
1
The received data is inverted
#1
TXINV
Transmit Signal Invert
8
1
read-write
0
The transmitting data is not inverted
#0
1
The transmitting data is inverted
#1
DMAC
MANCH_DMAC
Manchester DMA Control Register
0x10
-1
read-write
n
0x0
0x0
MTXDMAEN
Manchester Code Transmit DMA Enable Bit
0
1
read-write
0
Manchester Code Transmit DMA Disabled
#0
1
Manchester Code Transmit DMA Enabled
#1
RXDMAEN
Received DMA Enable Bit
2
1
read-write
0
Received DMA Disabled
#0
1
Received DMA Enabled
#1
TXDMAEN
Transmit DMA Enable Bit
1
1
read-write
0
Transmit DMA Disabled
#0
1
Transmit DMA Enabled
#1
FIFOCTL
MANCH_FIFOCTL
Manchester FIFO Control Register
0xC
-1
read-write
n
0x0
0x0
MTXFCNT
Manchester Transmit Encoded FIFO Count (Read Only)
The bits field indicates the current counter number of transmitted encoded FIFO for encoded data.
16
3
read-only
RXCLR
Received FIFO Clear
Note: The received control includes the FIFO and receive state machine. For example, if there is noise in the bus, the Manchester Controller will report BITERR flag when it detects the bit width greater than the setting. If the number of bit error event is greater than the software threshold, then set RXCLR to reset the receive state machine. The Manchester Controller will re-detect the IDLEPAT again.
1
1
read-write
0
Received control is not cleared
#0
1
Received control is cleared
#1
RXFCNT
Received FIFO Count (Read Only)
The bits field indicates the current counter number of received FIFO for decoded data.
12
3
read-only
TXCLR
Transmit FIFO Clear
0
1
read-write
0
Both of Transmit FIFO and Manchester Transmit encoded FIFO are not cleared
#0
1
Both of Transmit FIFO and Manchester Transmit encoded FIFO are cleared
#1
TXFCNT
Transmitted FIFO Count (Read Only)
The bits field indicates the current counter number of transmitted FIFO for transmitting data.
8
3
read-only
INTEN
MANCH_INTEN
Manchester Interrupt Enable Register
0x14
-1
read-write
n
0x0
0x0
BITERRIE
Bit Detect Error Interrupt Enable Bit
4
1
read-write
0
The Manchester bit error detected interrupt Disabled
#0
1
The Manchester bit error detected interrupt Enabled
#1
IDLERRIE
IDLE Pattern Error Interrupt Enable Bit
7
1
read-write
0
The Idle pattern error detected interrupt Disabled
#0
1
The Idle pattern error detected interrupt Enabled
#1
RXDONEIE
Receive Frame Done Interrupt Enable Bit
2
1
read-write
0
Receive frame done interrupt Disabled
#0
1
Receive frame done interrupt Enabled
#1
RXOVERIE
Receive FIFO Overflow Interrupt Enable Bit
3
1
read-write
0
Receive FIFO overflow interrupt Disabled
#0
1
Receive FIFO overflow interrupt Enabled
#1
TXDONEIE
Transmit Done Interrupt Enable Bit
0
1
read-write
0
Transmit frame done interrupt Disabled
#0
1
Transmit frame done interrupt Enabled
#1
MTXDAT
MANCH_MTXDAT
Manchester Transmit Encoded Data Register
0x28
-1
read-only
n
0x0
0x0
MTXDAT
Manchester Encoded Data
The bits field indicates the current Manchester encoded data in FIFO.
0
16
read-only
PREAM
MANCH_PREAM
Manchester Preamble Register
0x4
-1
read-write
n
0x0
0x0
FMTNUM
Modulation Format Transmit Number
The bits field defines the number of transmitted byte number in current selected mode.
If MODESEL is 0x1, the FMTNUM will be forced as 0x1E.
If MODESEL is 0x2, the FMTNUM will be forced as 0x40.
If MODESEL is 0x3, the modulation transmit number will be FMTNUM.
Note 1: If FMTNUM is 0x00, which indicates the transmit number is 256 Bytes.
Note 2: The value of FMTNUM must be greater than PRENUM
Note 3: The minimum value of FMTNUM must be greater than 1.
24
8
read-write
IDLEPAT
Idle Pattern
The bits field indicates the bus idle pattern.
If it is 0x00, it indicates that the bus idle default is low.
If it is 0xFF, it indicates that the bus idle default is high.
Except the bus idle state is LOW, the bits field must be set before the Controller is Enabled.
16
8
read-write
PREAMBLE
Preamble Format
The bits field defines the preamble pattern in the modulation signal format.
If MODESEL is 2'b10, the PREAMBLE will be set as 0x7E.
0
8
read-write
PRENUM
Preamble Number
The bits field defines the number of preamble in the modulation signal format.
00000: means there are 32 preamble patterns.
00001: means there is 1 preamble pattern.
00010: means there are 2 preamble patterns.
00011: means there are 3 preamble patterns.
and so on
If MODESEL is 2'b01, the PRENUM will be set as 0x5.
If MODESEL is 2'b10, the PRENUM will be set as 0x4.
8
5
read-write
RXDAT
MANCH_RXDAT
Manchester Receive Data Register
0x24
-1
read-only
n
0x0
0x0
RXDAT
Manchester Receive Data
The bits field indicates the received data.
0
8
read-only
STS
MANCH_STS
Manchester Status Register
0x18
-1
read-write
n
0x0
0x0
BITERR
Manchester Bit Error
Note: This bit can be cleared by writing 1 to it.
4
1
read-write
0
The Manchester bit error is not detected
#0
1
The Manchester bit error is detected. If the counter between two receive edge is greater than (RBITNUM + bit error tolerance) or less than (RBITNUM - bit error tolerance)
#1
IDLERR
IDLE Error
Note: This bit can be cleared by writing 1 to it.
7
1
read-write
0
The receive Idle pattern error is not detected
#0
1
The receive Idle pattern error is detected
#1
MTXEMPTY
Manchester Transmit Encoded FIFO Empty
14
1
read-write
0
The Manchester transmit encoded FIFO is not empty
#0
1
The Manchester transmit encoded FIFO is empty
#1
MTXFULL
Manchester Transmit Encoded FIFO Full
15
1
read-write
0
The Manchester transmit encoded FIFO is not full
#0
1
The Manchester transmit encoded FIFO is full
#1
PRENERR
Preamble Number Error
Note: This bit can be cleared by writing 1 to it.
5
1
read-write
0
The receive preamble number error is not detected
#0
1
The receive preamble number error is detected
#1
RXBUSY
Receive Busy Flag
31
1
read-write
0
The received bus is not busy
#0
1
The received bus is busy
#1
RXCNT
Receive Frame Data Current Count
16
8
read-write
RXDONE
Receive Frame Done
Note: This bit can be cleared by writing 1 to it.
2
1
read-write
0
Receive frame is not done
#0
1
Receive frame is done
#1
RXEMPTY
Received FIFO Empty
10
1
read-write
0
The received FIFO is not empty
#0
1
The received FIFO is empty
#1
RXFULL
Received FIFO Full
11
1
read-write
0
The received FIFO is not full
#0
1
The received FIFO is full
#1
RXOVER
Receive FIFO Overflow
Note: This bit can be cleared by writing 1 to it.
3
1
read-write
0
The receive FIFO is not overflow
#0
1
The receive FIFO is overflow
#1
TXDONE
Transmit Frame Done
Note: When the MANCHTEN is set, this bit will keep 0 until the data frame transmission is done.
0
1
read-write
0
Transmit frame is not done
#0
1
Transmit frame is done
#1
TXEMPTY
Transmit FIFO Empty
8
1
read-write
0
The transmit FIFO is not empty
#0
1
The transmit FIFO is empty
#1
TXFULL
Transmit FIFO Full
9
1
read-write
0
The transmit FIFO is not full
#0
1
The transmit FIFO is full
#1
TXUNDER
Transmit FIFO Underrun
Note: This bit can be cleared by writing 1 to it.
6
1
read-write
0
The transmit FIFO is not underrun
#0
1
The transmit FIFO is underrun
#1
TXDAT
MANCH_TXDAT
Manchester Transmit Data Register
0x20
-1
read-write
n
0x0
0x0
TXDAT
Manchester Transmit Data
The bits field indicates the transmit data.
0
8
read-write
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Register
0x0
-1
read-write
n
0x0
0x0
BODOUT
BOD NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
EINT0
External Interrupt From PB.5 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt from PB.5 pin NMI source Disabled
#0
1
External interrupt from PB.5 pin NMI source Enabled
#1
EINT1
External Interrupt From PB.4 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt from PB.4 pin NMI source Disabled
#0
1
External interrupt from PB.4 pin NMI source Enabled
#1
EINT2
External Interrupt From PB.3 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
External interrupt from PB.3 pin NMI source Disabled
#0
1
External interrupt from PB.3 pin NMI source Enabled
#1
EINT3
External Interrupt From PB.2 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
11
1
read-write
0
External interrupt from PB.2 pin NMI source Disabled
#0
1
External interrupt from PB.2 pin NMI source Enabled
#1
EINT4
External Interrupt From PB.6 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
External interrupt from PB.6 pin NMI source Disabled
#0
1
External interrupt from PB.6 pin NMI source Enabled
#1
EINT5
External Interrupt From PB.7 Pin NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
External interrupt from PB.7 pin NMI source Disabled
#0
1
External interrupt from PB.7 pin NMI source Enabled
#1
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
UART0_INT
UART0 NMI Source Enable (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
-1
read-only
n
0x0
0x0
BODOUT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
EINT0
External Interrupt From PB.5 Pin Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt from PB.5 interrupt is deasserted
#0
1
External Interrupt from PB.5 interrupt is asserted
#1
EINT1
External Interrupt From PB.4 Pin Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt from PB.4 interrupt is deasserted
#0
1
External Interrupt from PB.4 interrupt is asserted
#1
EINT2
External Interrupt From PB.3 Pin Interrupt Flag (Read Only)
10
1
read-only
0
External Interrupt from PB.3 interrupt is deasserted
#0
1
External Interrupt from PB.3 interrupt is asserted
#1
EINT3
External Interrupt From PB.2 Pin Interrupt Flag (Read Only)
11
1
read-only
0
External Interrupt from PB.2 interrupt is deasserted
#0
1
External Interrupt from PB.2 interrupt is asserted
#1
EINT4
External Interrupt From PB.6 Pin Interrupt Flag (Read Only)
12
1
read-only
0
External Interrupt from PB.6 interrupt is deasserted
#0
1
External Interrupt from PB.6 interrupt is asserted
#1
EINT5
External Interrupt From PB.7 Pin Interrupt Flag (Read Only)
13
1
read-only
0
External Interrupt from PB.7 interrupt is deasserted
#0
1
External Interrupt from PB.7 interrupt is asserted
#1
PWRWU_INT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
UART0_INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART0 interrupt is deasserted
#0
1
UART0 interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x80
0x4
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x200
-1
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags
The NVIC_IABR0 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
-1
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Disabled.
Interrupt Enabled
1
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
-1
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0 registers remove the pending state from interrupts, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Removes pending state an interrupt.
Interrupt is pending
1
ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
-1
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0
32
read-write
0
No effect.
Interrupt Disabled
0
1
Interrupt Enabled
1
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
-1
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending
The NVIC_ISPR0 registers force interrupts into the pending state, and show which interrupts are pending
Write Operation:
0
32
read-write
0
No effect.
Interrupt is not pending
0
1
Changes interrupt state to pending.
Interrupt is pending
1
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x70
registers
n
0x100
0x1C
registers
n
0x400
0x44
registers
n
0x460
0x4
registers
n
0x480
0x8
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
-1
read-write
n
0x0
0x0
ABTIF0
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF1
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF2
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF3
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF4
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF5
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
5
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF6
PDMA Read/Write Target Abort Interrupt Status Flag
These bits indicate which PDMA controller has target abort error. User can write 1 to clear these bits.
6
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ALIGN
PDMA_ALIGN
PDMA Transfer Alignment Status Register
0x428
-1
read-write
n
0x0
0x0
ALIGN0
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
0
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN1
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
1
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN2
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
2
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN3
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
3
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN4
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
4
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN5
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
5
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN6
Transfer Alignment Flag
These bits indicate whether source and destination address both follow transfer width setting. User can write 1 to clear these bits.
6
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
-1
read-write
n
0x0
0x0
CHEN0
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
0
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN1
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
1
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN2
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
2
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN3
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
3
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN4
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
4
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN5
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
5
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN6
PDMA Channel Enable Bits
Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
6
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHRST
PDMA_CHRST
PDMA Channel Reset Register
0x460
-1
read-write
n
0x0
0x0
CHnRST
Channel n Reset
0
7
read-write
0
Corresponding channel n is not reset
0
1
Corresponding channel n is reset
1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x100
-1
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x104
-1
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x108
-1
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x10C
-1
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x110
-1
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x114
-1
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x118
-1
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel n
0x0
-1
read-write
n
0x0
0x0
BURSIZE
Burst Size
Note: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment
This field is used to set the destination address increment size.
Note: The fixed address function is not supported in memory to memory transfer type.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection
Note: Before filling new transfer task in the descriptor Table, user must check the PDMA_INTSTS[1] to make sure the current task is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted
#01
2
Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will load the next task to execute
#10
3
Reserved.
#11
SAINC
Source Address Increment
This field is used to set the source address increment size.
Note: The fixed address function is not supported in memory to memory transfer type.
8
2
read-write
3
No increment (fixed address)
#11
TBINTDIS
Table Interrupt Disable Bit
This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled, it will not generates TDIFn(PDMA_TDSTS[6:0]) when PDMA controller finishes transfer task.
Note: This function is only for scatter-gather mode.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1). The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finishes each transfer data, this field will be decreased immediately.
16
16
read-write
TXTYPE
Transfer Type
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection
This field is used for transfer width.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection.
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved.
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel n
0x8
-1
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address
This field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0xC
-1
read-write
n
0x0
0x0
EXENEXT
PDMA Execution Next Descriptor Table Offset
This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
Note: Write operation is useless in this field.
16
16
read-write
NEXT
PDMA Next Descriptor Table Offset
This field indicates the offset of the next descriptor table address in system memory.
Write Operation:
If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
Read Operation:
When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
Note 1: The descriptor table address must be word boundary.
Note 2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
16
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel n
0x4
-1
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address
This field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel n
0x10
-1
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel n
0x18
-1
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x1C
-1
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel n
0x14
-1
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel n
0x20
-1
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel n
0x28
-1
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x2C
-1
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel n
0x24
-1
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel n
0x30
-1
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel n
0x38
-1
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x3C
-1
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel n
0x34
-1
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel n
0x40
-1
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel n
0x48
-1
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x4C
-1
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel n
0x44
-1
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel n
0x50
-1
read-write
n
0x0
0x0
DSCT5_DA
PDMA_DSCT5_DA
Destination Address Register of PDMA Channel n
0x58
-1
read-write
n
0x0
0x0
DSCT5_NEXT
PDMA_DSCT5_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x5C
-1
read-write
n
0x0
0x0
DSCT5_SA
PDMA_DSCT5_SA
Source Address Register of PDMA Channel n
0x54
-1
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel n
0x60
-1
read-write
n
0x0
0x0
DSCT6_DA
PDMA_DSCT6_DA
Destination Address Register of PDMA Channel n
0x68
-1
read-write
n
0x0
0x0
DSCT6_NEXT
PDMA_DSCT6_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x6C
-1
read-write
n
0x0
0x0
DSCT6_SA
PDMA_DSCT6_SA
Source Address Register of PDMA Channel n
0x64
-1
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Register
0x418
-1
read-write
n
0x0
0x0
INTEN0
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
0
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN1
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
1
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN2
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
2
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN3
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
3
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN4
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
4
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN5
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
5
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN6
PDMA Interrupt Enable Bits
This field is used to enable PDMA channel[n] interrupt.
Note: The interrupt flag is time-out, abort, transfer done and align.
6
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
-1
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read Only)
This bit indicates that PDMA has target abort error. Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-only
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
2
1
read-only
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
REQTOF0
Request Time-out Flag for Channel 0
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
Note: Please disable time-out function before clearing this bit.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
Request Time-out Flag for Channel 1
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
Note: Please disable time-out function before clearing this bit.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission. User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
PAUSE
PDMA_PAUSE
PDMA Transfer Pause Control Register
0x404
-1
write-only
n
0x0
0x0
PAUSE0
PDMA Channel n Transfer Pause Control (Write Only)
0
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE1
PDMA Channel n Transfer Pause Control (Write Only)
1
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE2
PDMA Channel n Transfer Pause Control (Write Only)
2
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE3
PDMA Channel n Transfer Pause Control (Write Only)
3
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE4
PDMA Channel n Transfer Pause Control (Write Only)
4
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE5
PDMA Channel n Transfer Pause Control (Write Only)
5
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE6
PDMA Channel n Transfer Pause Control (Write Only)
6
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
-1
write-only
n
0x0
0x0
FPRICLR0
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR1
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR2
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR3
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR4
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR5
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
5
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR6
PDMA Fixed Priority Clear Bits (Write Only)
Set this bit to 1 to clear fixed priority level.
Note: User can read PDMA_PRISET register to know the channel priority.
6
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
-1
read-write
n
0x0
0x0
FPRISET0
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET1
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET2
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET3
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET4
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET5
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
5
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
FPRISET6
PDMA Fixed Priority Setting
Set this bit to 1 to enable fixed priority level.
Write Operation:
Note: This field is only set to fixed priority. To clear fixed priority use PDMA_PRICLR register.
6
1
read-write
0
No effect.
Corresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.
Corresponding PDMA channel is fixed priority
#1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Request Source Select Register 0
0x480
-1
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection
This field defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.
Note 1: A peripheral cannot be assigned to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
0
6
read-write
0
Disable PDMA peripheral request
0
1
Reserved.
1
10
Reserved.
10
11
Reserved.
11
12
Reserved.
12
13
Reserved.
13
14
Reserved.
14
15
Reserved.
15
16
Reserved.
16
17
Reserved.
17
18
Channel connects to SPI0_TX
18
19
Channel connects to SPI0_RX
19
2
Reserved.
2
20
Channel connects to ADC_RX
20
21
Reserved.
21
22
Reserved.
22
23
Reserved.
23
24
Reserved.
24
25
Reserved.
25
26
Reserved.
26
27
Reserved.
27
28
Channel connects to I2C0_TX
28
29
Channel connects to I2C0_RX
29
3
Reserved.
3
30
Channel connects to I2C1_TX
30
31
Channel connects to I2C1_RX
31
32
Channel connects to TMR0
32
33
Channel connects to TMR1
33
34
Channel connects to TMR2
34
35
Channel connects to TMR3
35
36
Reserved.
36
37
Reserved.
37
38
Reserved.
38
39
Reserved.
39
4
Channel connects to UART0_TX
4
40
Reserved.
40
41
Reserved.
41
42
Reserved.
42
43
Reserved.
43
44
Reserved.
44
45
Reserved.
45
46
Channel connects to DAC0 TX
46
47
Channel connects to DAC1 TX
47
48
Channel connects to DAC2 TX
48
49
Channel connects to DAC3 TX
49
5
Channel connects to UART0_RX
5
50
Channel connects to TMR4
50
51
Channel connects to TMR5
51
52
Channel connects to MANCH MTX
52
53
Channel connects to MANCH TX
53
54
Channel connects to MANCH RX
54
6
Reserved.
6
7
Reserved.
7
8
Reserved.
8
9
Reserved.
9
REQSRC1
Channel 1 Request Source Selection
This field defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC2
Channel 2 Request Source Selection
This field defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
REQSRC3
Channel 3 Request Source Selection
This field defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
6
read-write
REQSEL4_6
PDMA_REQSEL4_6
PDMA Request Source Select Register 1
0x484
-1
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
6
read-write
REQSRC5
Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
6
read-write
REQSRC6
Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
6
read-write
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
-1
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-gather Descriptor Table Address
In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is
Note: Only useful in Scatter-Gather mode.
16
16
read-write
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
-1
write-only
n
0x0
0x0
SWREQ0
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ1
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ2
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ3
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ4
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ5
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
5
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ6
PDMA Software Request (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.
Note 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
6
1
write-only
0
No effect
#0
1
Generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
-1
read-only
n
0x0
0x0
TXACTF0
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
0
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF1
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
1
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF2
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
2
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF3
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
3
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF4
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
4
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF5
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
5
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TXACTF6
Transfer on Active Flag (Read Only)
This bit indicates which PDMA channel is active.
6
1
read-only
0
PDMA channel is finished
#0
1
PDMA channel is active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
-1
read-write
n
0x0
0x0
TDIF0
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
0
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF1
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
1
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF2
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
2
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF3
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
3
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF4
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
4
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF5
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
5
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF6
Transfer Done Flag
These bits indicate whether PDMA controller channel transfer has been finished or not. User can write 1 to clear these bits.
6
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Time-out Counter Ch1 and Ch0 Register
0x440
-1
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0
0
16
read-write
TOC1
Time-out Counter for Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[6:4]) clock. For the example of time-out period, refer to TOC0 bit description.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
-1
read-write
n
0x0
0x0
TOUTEN0
PDMA Time-out Enable Bits
0
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTEN1
PDMA Time-out Enable Bits
1
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTIEN
PDMA_TOUTIEN
PDMA Time-out Interrupt Enable Register
0x438
-1
read-write
n
0x0
0x0
TOUTIEN0
PDMA Time-out Interrupt Enable Bits
0
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTIEN1
PDMA Time-out Interrupt Enable Bits
1
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
-1
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
-1
read-only
n
0x0
0x0
REQSTS0
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
0
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS1
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
1
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS2
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
2
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS3
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
3
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS4
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
4
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS5
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
5
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS6
PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically.
Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
6
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
SCS
SYST_SCR Register Map
SYST_SCR
0x0
0x10
0xC
registers
n
0xD04
0x10
registers
n
0xD18
0xC
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness
15
1
read-write
0
Little-endian
#0
1
Big-endian
#1
PRIGROUP
Interrupt Priority Grouping
This field determines the Split Of Group priority from subpriority,
8
3
read-write
SYSRESETREQ
System Reset Request
Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested
This bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Exception Active Status Clear Bit
Setting this bit to 1 will clear all active state information for fixed and configurable exceptions.
This bit is write only and can only be written when the core is halted.
Note: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
Register Access Key
When writing this register, this field should be 0x05FA otherwise, the write action will be unpredictable.
The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
VECTRESET
Reserved.
0
1
read-write
ICSR
ICSR
Interrupt Control and State Register
0xD04
-1
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt is not pending
#0
1
Interrupt is pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)
If set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-pending Bit
Write Operation:
Note: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.
NMI exception is not pending
#0
1
Change NMI exception state to pending.
NMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time.
25
1
read-write
0
No effect
#0
1
Remove the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit
Write Operation:
26
1
read-write
0
No effect.
SysTick exception is not pending
#0
1
Change SysTick exception state to pending.
SysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit
Write Operation:
Note: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time.
27
1
read-write
0
No effect
#0
1
Remove the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit
Write Operation:
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.
PendSV exception is not pending
#0
1
Change PendSV exception state to pending.
PendSV exception is pending
#1
RETTOBASE
Preempted Active Exceptions Indicator
Indicate whether There are Preempted Active Exceptions
11
1
read-write
0
There are preempted active exceptions to execute
#0
1
There are no active exceptions, or the currently-executing exception is the only active exception
#1
VECTACTIVE
Number of the Current Active Exception
0
6
read-write
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception
Indicate the Exception Number of the Highest Priority Pending Enabled Exception
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but does not include any effect of the PRIMASK register.
12
6
read-write
0
No pending exceptions
0
SCR
SCR
System Control Register
0xD10
-1
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection
Control whether the processor uses Sleep or Deep Sleep as its Low Power Mode.
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control
This bit indicates Sleep-On-Exit when Returning from Handler Mode to Thread Mode.
Note: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHPR1
SHPR1
System Handler Priority Register 1
0xD18
-1
read-write
n
0x0
0x0
PRI_4
Priority of system handler 4, MemManage
0
8
read-write
PRI_5
Priority of system handler 5, BusFault
8
8
read-write
PRI_6
Priority of system handler 6, UsageFault
16
8
read-write
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
-1
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall
'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
-1
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV
'0' denotes the highest priority and '3' denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick
'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SYST_CTRL
SYST_CTRL
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register was read.
COUNTFLAG is set by a count transition from 1 to 0.
COUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_LOAD
SYST_LOAD
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value
The value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYST_VAL
SYST_VAL
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
CURRENT
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
VTOR
VTOR
Vector Table Offset Register
0xD08
-1
read-write
n
0x0
0x0
TBLOFF
Table Offset Bits
The vector table address for the selected security state.
7
25
read-write
SPIx
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
-1
read-write
n
0x0
0x0
DIVIDER
Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.
where
is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
Note: The time interval must be greater than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
0
9
read-write
CTL
SPIx_CTL
SPI Control Register
0x0
-1
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control
This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width
This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can be up to 32 bits.
Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit
This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit
Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)
This bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.
Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
-1
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear
Note: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is greater than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear
Note: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset
Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit
When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity
Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
Note 2: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
-1
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit
Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
SPIx_RX
SPI Data Receive Register
0x30
-1
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)
There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
-1
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)
If AUTOSS bit is cleared to 0,
0
1
read-write
0
set the SPIx_SS line to inactive state.
Keep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.
SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
SPIx_STATUS
SPI Status Register
0x14
-1
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is greater than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
Note: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
SPI Enable Status (Read Only)
Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)
Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is greater than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag
Note: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
TX
SPIx_TX
SPI Data Transmit Register
0x20
-1
write-only
n
0x0
0x0
TX
Data Transmit Register
The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode.
In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x4
registers
n
0x140
0x8
registers
n
0x18
0x4
registers
n
0x1E8
0x4
registers
n
0x24
0x8
registers
n
0x30
0x14
registers
n
0x58
0x4
registers
n
0xC0
0x4
registers
n
0xD0
0x8
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
BOD output is sampled by LIRC/4 clock
#000
1
64 system clock (HCLK)
#001
2
128 system clock (HCLK)
#010
3
256 system clock (HCLK)
#011
4
512 system clock (HCLK)
#100
5
1024 system clock (HCLK)
#101
6
2048 system clock (HCLK)
#110
7
4096 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)
Note 1: The BOD consumes about 2uA in normal mode, the BOD low power mode can reduce the current to about 1/30 but slow the BOD response.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operate in normal mode (Default)
#0
1
BOD low power mode Enabled
#1
BODOUT
Brown-out Detector Output Status
It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)
Note 1: While the Brown-out Detector function is enabled (BODEN is 1) and BOD reset function is enabled (BODRSTEN is 1), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT is 1).
While the BOD function is enabled (BODEN is 1) and BOD interrupt function is enabled (BODRSTEN is 0), BOD will assert an interrupt if BODOUT is 1. BOD interrupt will keep untill the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN to 0).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 3: Reset by power on reset
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Select (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
16
1
read-write
0
Brown-Out Detector threshold voltage is 2.5V
#0
1
Brown-Out Detector threshold voltage is 2.7V
#1
LVRDGSEL
LVR Output De-glitch Time Select (Write Protect)
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
12
3
read-write
0
Without de-glitch function
#000
1
64 system clock (HCLK)
#001
2
128 system clock (HCLK)
#010
3
256 system clock (HCLK)
#011
4
512 system clock (HCLK)
#100
5
1024 system clock (HCLK)
#101
6
2048 system clock (HCLK)
#110
7
4096 system clock (HCLK)
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note 1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (Default).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
-1
read-write
n
0x0
0x0
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
-1
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
-1
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
-1
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
-1
read-write
n
0x0
0x0
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
GPF_MFPL
SYS_GPF_MFPL
GPIOF Low Byte Multiple Function Control Register
0x58
-1
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
-1
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to System Reset section.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after 2 clock cycles.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
-1
read-write
n
0x0
0x0
ADCRST
ADC Controller Reset
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
SPI0RST
SPI0 Controller Reset
13
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
-1
read-write
n
0x0
0x0
BPWMRST
BPWM Controller Reset
19
1
read-write
0
BPWM controller normal operation
#0
1
BPWM controller reset
#1
DAC01RST
DAC01 Controller Reset
12
1
read-write
0
DAC0 and DAC1 controller normal operation
#0
1
DAC0 and DAC1 controller reset
#1
DAC23RST
DAC23 Controller Reset
13
1
read-write
0
DAC2 and DAC3 controller normal operation
#0
1
DAC2 and DAC3 controller reset.
#1
MANCHRST
Manchester Codec Reset
24
1
read-write
0
Manchester codec normal operation
#0
1
Manchester codec reset
#1
TMR4RST
Timer4 Controller Reset
28
1
read-write
0
Timer4 controller normal operation
#0
1
Timer4 controller reset
#1
TMR5RST
Timer5 Controller Reset
29
1
read-write
0
Timer5 controller normal operation
#0
1
Timer5 controller reset
#1
TSRST
Temperature Sensor Reset
31
1
read-write
0
Temperature Sensor normal operation
#0
1
Temperature Sensor reset
#1
MODCTL
SYS_MODCTL
Modulation Control Register
0xC0
-1
read-write
n
0x0
0x0
MANCHMODEN0
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
16
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODEN1
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
17
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODEN2
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
18
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODEN3
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
19
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODEN4
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
20
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODEN5
Manchester Modulation Function Enable
Each of these bits is used to enable Manchester modulation function with BPWM1_CHn output.
21
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MANCHMODL0
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
24
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
MANCHMODL1
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
25
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
MANCHMODL2
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
26
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
MANCHMODL3
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
27
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
MANCHMODL4
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
28
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
MANCHMODL5
Manchester Modulation at Data Low
Each of these bits is used to select Manchester modulation with BPWM1_CHn at MANCH_TXD data high or low.
29
1
read-write
0
Manchester modulation with BPWM1_CHn at MANCH_TXD data high
#0
1
Manchester modulation with BPWM1_CHn at MANCH_TXD data low
#1
PDID
SYS_PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)
This register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
POR18DISAN
SYS_POR18DISAN
Analog POR18 Disable Control Register
0x1E8
-1
read-write
n
0x0
0x0
POR18OFFAN
LDO Power-on Reset Enable Bit (Write Protect)
After powered on, user can turn off internal analog POR18 circuit to save power by writing 0x5AA5 to this field.
The analog POR18 circuit will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
PORCTL
SYS_PORCTL
Power-On-reset Controller Register
0x24
-1
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
-1
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
REGLCTL[0]
Register Lock Control Disable Index
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag
The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag
Note 1: Write 1 to clear this bit to 0.
Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset.
8
1
read-write
0
No reset from CPU lockup happened
#0
1
The Cortex-M0 lockup happened and chip is reset
#1
CPURF
CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC).
Note: Write to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag
The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PORF
POR Reset Flag
The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag
The system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex- M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note 1: Write 1 to clear this bit to 0.
Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
SRAM_BISTCTL
SYS_SRAM_BISTCTL
System SRAM BIST Test Control Register
0xD0
-1
read-write
n
0x0
0x0
PDMABIST
PDMA SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for PDMA SRAM
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
PDMA SRAM BIST Disabled
#0
1
PDMA SRAM BIST Enabled
#1
SRBIST
System SRAM BIST Enable Bit (Write Protect)
This bit enables BIST test for System SRAM
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
System SRAM BIST Disabled
#0
1
System SRAM BIST Enabled
#1
SRAM_BISTSTS
SYS_SRAM_BISTSTS
System SRAM BIST Test Status Register
0xD4
-1
read-only
n
0x0
0x0
PDMABISTF
PDMA SRAM BIST Failed Flag
7
1
read-only
0
PDMA SRAM BIST pass
#0
1
PDMA SRAM BIST failed
#1
PDMAEND
PDMA SRAM BIST Test Finish
23
1
read-only
0
PDMA SRAM BIST is active
#0
1
PDMA SRAM BIST test finish
#1
SRBEND
System SRAM BIST Test Finish
16
1
read-only
0
System SRAM BIST active
#0
1
System SRAM BIST finish
#1
SRBISTFF
System SRAM BIST Fail Flag
0
1
read-only
0
System SRAM BIST test pass
#0
1
System SRAM BIST test fail
#1
TSCTL
SYS_TSCTL
Temperature Sensor Control Register
0x140
-1
read-write
n
0x0
0x0
TSDATA
SYS_TSDATA
Temperature Sensor Data Register
0x144
-1
read-write
n
0x0
0x0
TSDATA
Temperature Sensor Conversion Data Bits (Read Only)
This field present the conversion result of Temperature Sensor, ranges from -40C to 105C.
Note: Negative temperature is represented by 2's complement format, and per LSB difference is equivalent to 0.0625C
16
12
read-only
TSEOC
Temperature Sensor Conversion Finish Flag
This bit indicates the end of temperature sensor conversion.
Note: Write 1 to clear this bit to 0.
0
1
read-write
VREFCTL
SYS_VREFCTL
Voltage Reference Control Register
0x28
-1
read-write
n
0x0
0x0
PRELOADEN
VREF Pre-load Enable Bit (Write Protect)
This bit is set automatically if software set VREFEN (SYS_VREFCTL[0]) to 1.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: PRELOADEN should be cleared after 2ms of VREFEN enabled, if VREF capacitor is 4.7uF and VREF initial is 0V.
Note 3: PRELOADEN should be cleared after 480us of VREFEN enabled, if VREF capacitor is 1uF and VREF initial is 0V.
6
1
read-write
0
VREF Pre-load function Disabled. (Default)
#0
1
VREF Pre-load function Enabled
#1
SCPDIS
VREF Short Circuit Protection Disable Control (Write Protect)
8
1
read-write
0
VREF Short Circuit Protection function Enabled. (Default)
#0
1
VREF Short Circuit Protection function Disabled
#1
VREFEN
VREF Enable Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
VREF function Disabled. (Default)
#0
1
VREF function Enabled
#1
VREFSEL
VREF Output Voltage Select (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
VREF output voltage value is 2.048V. (Default)
#0
1
VREF output voltage value is 2.5V
#1
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~5) pin
#0
1
Capture Function source is from LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which LIRC as timer capture source
#1
CNTEN
Timer Counting Enable Bit
Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also, Timer1/3/5 will be in trigger-counting mode of capture function.
Note: For Timer1/3/5, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
MTRGTMEN
Manchester Edge Trigger Timer Enable Bit
11
1
read-write
0
Manchester Edge Trigger Timer Disabled
#0
1
Manchester Edge Trigger Timer Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM
Trigger BPWM Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
9
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGDAC
Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.
20
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#0
1
Capture interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~5) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~5) pin interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~5) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~5) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#00
1
A Rising edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#01
2
Either Rising or Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~5) pin de-bounce Disabled
#0
1
TMx (x= 0~5) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~5) pin
#0
1
Reserved.
#1
INTERCAPSEL
Internal Capture Source Selection to Trigger Capture Function
Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
8
3
read-write
5
Capture Function source is from LIRC
#101
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x30
-1
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x24
-1
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x20
-1
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x38
-1
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~5) pin
#0
1
Capture Function source is from LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which LIRC as timer capture source
#1
CNTEN
Timer Counting Enable Bit
Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also, Timer1/3/5 will be in trigger-counting mode of capture function.
Note: For Timer1/3/5, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
MTRGTMEN
Manchester Edge Trigger Timer Enable Bit
11
1
read-write
0
Manchester Edge Trigger Timer Disabled
#0
1
Manchester Edge Trigger Timer Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM
Trigger BPWM Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
9
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGDAC
Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.
20
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#0
1
Capture interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~5) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~5) pin interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~5) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~5) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#00
1
A Rising edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#01
2
Either Rising or Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~5) pin de-bounce Disabled
#0
1
TMx (x= 0~5) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~5) pin
#0
1
Reserved.
#1
INTERCAPSEL
Internal Capture Source Selection to Trigger Capture Function
Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
8
3
read-write
5
Capture Function source is from LIRC
#101
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x30
-1
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x24
-1
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x20
-1
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x38
-1
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
TMR45
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TIMER4_CAP
TIMER4_CAP
Timer4 Capture Data Register
0x10
-1
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER4_CMP
TIMER4_CMP
Timer4 Comparator Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value
CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER4_CNT
TIMER4_CNT
Timer4 Data Register
0xC
-1
read-only
n
0x0
0x0
CNT
Timer Data Register
Read this register to get CNT value. For example:
If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
0
24
read-only
TIMER4_CTL
TIMER4_CTL
Timer4 Control Register
0x0
-1
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
Note: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
16
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~5) pin
#0
1
Capture Function source is from LIRC. User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which LIRC as timer capture source
#1
CNTEN
Timer Counting Enable Bit
Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
Note 2: When TMR0/TMR2 INTRGEN is set to 1, this bit is forced to 1. When INTRGEN is 1 and TMR1/TMR3 CAPIF (TIMERx_EINTSTS[0]) is 1, this bit is forced to 0.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
TIMER counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit
Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit
Setting this bit will enable the inter-timer trigger capture function.
The Timer0/2/4 will be in event counter mode and counting with external clock source or event.Also, Timer1/3/5 will be in trigger-counting mode of capture function.
Note: For Timer1/3/5, this bit is ignored and the read back value is always 0.
10
1
read-write
0
Inter-Timer Trigger mode Disabled
#0
1
Inter-Timer Trigger mode Enabled
#1
MTRGTMEN
Manchester Edge Trigger Timer Enable Bit
11
1
read-write
0
Manchester Edge Trigger Timer Disabled
#0
1
Manchester Edge Trigger Timer Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PSC
Prescale Counter
Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
RSTCNT
Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
Note: This bit will be auto cleared.
26
1
read-write
0
No effect
#0
1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
#1
TGLPINSEL
Toggle-output Pin Select
22
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
TRGADC
Trigger ADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.
21
1
read-write
0
Timer interrupt trigger ADC Disabled
#0
1
Timer interrupt trigger ADC Enabled
#1
TRGBPWM
Trigger BPWM Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger BPWM.
9
1
read-write
0
Timer interrupt trigger BPWM Disabled
#0
1
Timer interrupt trigger BPWM Enabled
#1
TRGDAC
Trigger DAC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger DAC.
20
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.
8
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGSSEL
Trigger Source Select Bit
This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
18
1
read-write
0
Timer time-out interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#0
1
Capture interrupt signal is used to trigger BPWM, ADC, DAC and PDMA
#1
WKEN
Wake-up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER4_EINTSTS
TIMER4_EINTSTS
Timer4 External Interrupt Status Register
0x18
-1
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~5) pin interrupt did not occur
#0
1
TMx_EXT (x= 0~5) pin interrupt occurred
#1
TIMER4_EXTCTL
TIMER4_EXTCTL
Timer4 External Control Register
0x14
-1
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx_EXT pin output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~5) pin de-bounce Disabled
#0
1
TMx_EXT (x= 0~5) pin de-bounce Enabled
#1
CAPEDGE
Timer External Capture Pin Edge Detect
1
2
read-write
0
A Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#00
1
A Rising edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#01
2
Either Rising or Falling edge on TMx_EXT (x= 0~5) pin or LIRC will be detected
#10
3
Reserved.
#11
CAPEN
Timer Capture Enable Bit
This bit enables the capture input function.
Note: TMR1 CAPEN will be forced to 1 when TMR0 INTRGEN is enabled.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~5) pin or LIRC detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit
Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~5) pin de-bounce Disabled
#0
1
TMx (x= 0~5) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~5) pin
#0
1
Reserved.
#1
INTERCAPSEL
Internal Capture Source Selection to Trigger Capture Function
Note: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1.
8
3
read-write
5
Capture Function source is from LIRC
#101
TIMER4_INTSTS
TIMER4_INTSTS
Timer4 Interrupt Status Register
0x8
-1
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag
This bit indicates the interrupt wake-up flag status of timer.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER5_CAP
TIMER5_CAP
Timer5 Capture Data Register
0x30
-1
read-write
n
0x0
0x0
TIMER5_CMP
TIMER5_CMP
Timer5 Comparator Register
0x24
-1
read-write
n
0x0
0x0
TIMER5_CNT
TIMER5_CNT
Timer5 Data Register
0x2C
-1
read-write
n
0x0
0x0
TIMER5_CTL
TIMER5_CTL
Timer5 Control Register
0x20
-1
read-write
n
0x0
0x0
TIMER5_EINTSTS
TIMER5_EINTSTS
Timer5 External Interrupt Status Register
0x38
-1
read-write
n
0x0
0x0
TIMER5_EXTCTL
TIMER5_EXTCTL
Timer5 External Control Register
0x34
-1
read-write
n
0x0
0x0
TIMER5_INTSTS
TIMER5_INTSTS
Timer5 Interrupt Status Register
0x28
-1
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x34
registers
n
0x40
0xC
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
-1
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length
Note : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit
Note : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection is finished or the auto-baud rate counter is overflow and if ABRIEN(UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
Note: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.
24
8
read-write
RS485AAD
RS-485 Auto Address Detection Operation Mode
Note: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode
Note: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
-1
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.114.
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.114.
Note: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider
The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.114.
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.114.
24
4
read-write
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
-1
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
Parity Bit Receive/Transmit Buffer
Write Operation:
By writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
Read Operation:
If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
-1
read-write
n
0x0
0x0
STCOMP
Start Bit Compensation Value
The bits field indicates how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.
Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
-1
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
RTSTRGLV
nRTS Trigger Level for Auto-flow Control
Note: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
RXOFF
Receiver Disable Bit
The receiver is disabled or not (set 1 to disable receiver).
Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL[8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) to be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.
Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) to be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag
This bit is set to logic '1' when auto-baud rate detect function is finished.
Note: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag
This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.
Note: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag
Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
Note 2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag
This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).
Note: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.
Note: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 1, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)
This bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 1. When the using level of RX FIFO Buffer equal to 1, the RXFULL bit is set to 1. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 0.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 1, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to be logic 1.
Note: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 1. When the using level of TX FIFO Buffer equal to 1, the TXFULL bit is set to 1. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 0.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)
This bit indicates TX and RX are active or inactive.
Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller cannot transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
-1
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit
Setting this bit can disable TX and RX.
Note: The TX and RX will not disable immediately when this bit is set. The TX and RX complete current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
-1
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit
This bit can enable or disable RX PDMA service.
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit
Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit
If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit
Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)
This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)
This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
MODEMIF
MODEM Interrupt Flag (Read Only)
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN[0]) is enabled, the RDA interrupt will be generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN[4]) is enabled, the RX time-out interrupt will be generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)
This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag
This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.
Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
Note 2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)
This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag
This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only)
This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)
This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)
This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
-1
read-write
n
0x0
0x0
BCB
Break Control Bit
Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit
Note: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When selecting 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When selecting 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable Bit
Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
Parity bit generated Disabled
#0
1
Parity bit generated Enabled
#1
PSS
Parity Bit Source Selection
The parity bit can be selected to be generated and checked automatically by software.
Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.
Note 2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
Parity bit generated and checked by software
#1
RXDINV
RX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted
Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection
This field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
RTS
nRTS Signal Control
This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
Note 3: Single-wire mode supports this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
Note 1: Refer to Figure 6.119 and Figure 6.1110 for UART function mode.
Note 2: Refer to Figure 6.1113 and Figure 6.1114 for RS-485 function mode.
Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set and then wait for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, clear TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.
Note: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
-1
read-write
n
0x0
0x0
DLY
TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
-1
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit
Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit
Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
-1
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag
This bit is set if chip wake-up from power-down state by nCTS wake-up.
Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up causes this bit to set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag
This bit is set if chip wake-up from power-down state by data wake-up.
Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up causes this bit to set to '1'.
Note 2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
WDT
WDT Register Map
WDT
0x0
0x0
0xC
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
-1
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protect)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
-1
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag
This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
Note: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)
Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
SYNC
WDT Enable Control SYNC Flag Indicator (Read Only)
If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
30
1
read-only
0
Set WDTEN bit is completed
#0
1
Set WDTEN bit is synchronizing and not become active yet
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)
These four bits select the time-out interval period for the WDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
8
4
read-write
0
24 * WDT_CLK
#0000
1
26 * WDT_CLK
#0001
2
28 * WDT_CLK
#0010
3
210 * WDT_CLK
#0011
4
212 * WDT_CLK
#0100
5
214 * WDT_CLK
#0101
6
216 * WDT_CLK
#0110
7
218 * WDT_CLK
#0111
8
220 * WDT_CLK
#1000
WDTEN
WDT Enable Bit (Write Protect)
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 38.4 kHz internal low speed RC oscillator (LIRC).
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)
This bit indicates the interrupt wake-up flag status of WDT
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
RSTCNT
WDT_RSTCNT
WDT Reset Counter Register
0x8
-1
write-only
n
0x0
0x0
RSTCNT
WDT Reset Counter Register
Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.
Note: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
0
32
write-only
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
-1
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value
CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
-1
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Register
Set this register to adjust the valid reload window.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value is greater than CMPDAT, WWDT reset signal will be generated immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit
Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit
If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter starts counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
-1
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register
Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is greater than CMPDAT, WWDT reset signal will be generated immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
-1
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag
This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
Note: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag
This bit indicates the system has been reset by WWDT time-out reset or not.
Note: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1