nuvoTon M0564AE_v1 2024.04.27 M0564AE_v1 SVD file 8 32 ACMP01 ACMP Register Map ACMP 0x0 0x0 0x10 registers n ACMP_CTL0 ACMP_CTL0 Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 0 Disabled #0 1 Comparator 0 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 0 interrupt Disabled #0 1 Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse 3 1 read-write 0 Comparator 0 output inverse Disabled #0 1 Comparator 0 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function Disabled #000 1 ACMP0 output is sampled 1 consecutive PCLK #001 2 ACMP0 output is sampled 2 consecutive PCLKs #010 3 ACMP0 output is sampled 4 consecutive PCLKs #011 4 ACMP0 output is sampled 8 consecutive PCLKs #100 5 ACMP0 output is sampled 16 consecutive PCLKs #101 6 ACMP0 output is sampled 32 consecutive PCLKs #110 7 ACMP0 output is sampled 64 consecutive PCLKs #111 HYSEN Comparator Hysteresis Enable Bit 2 1 read-write 0 Comparator 0 hysteresis Disabled #0 1 Comparator 0 hysteresis Enabled #1 INTPOL Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection 4 2 read-write 0 ACMP0_N pin #00 1 Internal comparator reference voltage (CRV) #01 2 Band-gap voltage #10 3 Reserved. #11 OUTSEL Comparator Output Selection 12 1 read-write 0 Comparator 0 output to ACMP0_O pin is unfiltered comparator output #0 1 Comparator 0 output to ACMP0_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP0_P0 #00 1 Input from ACMP0_P1 #01 2 Input from ACMP0_P2 #10 3 Input from ACMP0_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window Compare Mode Disabled #0 1 Window Compare Mode Selected #1 WKEN Power-down Wake-up Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Function Enable Bit 17 1 read-write 0 Window Latch Function Disabled #0 1 Window Latch Function Enabled #1 ACMP_CTL1 ACMP_CTL1 Analog Comparator 1 Control Register 0x4 read-write n 0x0 0x0 ACMPEN Comparator Enable Bit 0 1 read-write 0 Comparator 1 Disabled #0 1 Comparator 1 Enabled #1 ACMPIE Comparator Interrupt Enable Bit 1 1 read-write 0 Comparator 1 interrupt Disabled #0 1 Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well #1 ACMPOINV Comparator Output Inverse Control 3 1 read-write 0 Comparator 1 output inverse Disabled #0 1 Comparator 1 output inverse Enabled #1 FILTSEL Comparator Output Filter Count Selection 13 3 read-write 0 Filter function Disabled #000 1 ACMP1 output is sampled 1 consecutive PCLK #001 2 ACMP1 output is sampled 2 consecutive PCLKs #010 3 ACMP1 output is sampled 4 consecutive PCLKs #011 4 ACMP1 output is sampled 8 consecutive PCLKs #100 5 ACMP1 output is sampled 16 consecutive PCLKs #101 6 ACMP1 output is sampled 32 consecutive PCLKs #110 7 ACMP1 output is sampled 64 consecutive PCLKs #111 HYSEN Comparator Hysteresis Enable Bit 2 1 read-write 0 Comparator 1 hysteresis Disabled #0 1 Comparator 1 hysteresis Enabled #1 INTPOL Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected. 8 2 read-write 0 Rising edge or falling edge #00 1 Rising edge #01 2 Falling edge #10 3 Reserved. #11 NEGSEL Comparator Negative Input Selection 4 2 read-write 0 ACMP1_N pin #00 1 Internal comparator reference voltage (CRV) #01 2 Band-gap voltage #10 3 Ground #11 OUTSEL Comparator Output Select 12 1 read-write 0 Comparator 1 output to ACMP1_O pin is unfiltered comparator output #0 1 Comparator 1 output to ACMP1_O pin is from filter output #1 POSSEL Comparator Positive Input Selection 6 2 read-write 0 Input from ACMP1_P0 #00 1 Input from ACMP1_P1 #01 2 Input from ACMP1_P2 #10 3 Input from ACMP1_P3 #11 WCMPSEL Window Compare Mode Selection 18 1 read-write 0 Window compare mode Disabled #0 1 Window compare mode is Selected #1 WKEN Power-down Wakeup Enable Bit 16 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 WLATEN Window Latch Function Enable Bit 17 1 read-write 0 Window Latch function Disabled #0 1 Window Latch function Enabled #1 ACMP_STATUS ACMP_STATUS Analog Comparator Status Register 0x8 read-write n 0x0 0x0 ACMPIF0 Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write ACMPIF1 Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write ACMPO0 Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 4 1 read-write ACMPO1 Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 5 1 read-write ACMPS0 Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. 12 1 read-write ACMPS1 Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. 13 1 read-write ACMPWO Comparator Window Output\nThis bit shows the output status of window compare mode 16 1 read-write 0 The positvie input voltage is outside the window #0 1 The positive input voltage is in the window #1 WKIF0 Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0. 8 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 WKIF1 Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0. 9 1 read-write 0 No power-down wake-up occurred #0 1 Power-down wake-up occurred #1 ACMP_VREF ACMP_VREF Analog Comparator Reference Voltage Control Register 0xC read-write n 0x0 0x0 CRVCTL Comparator Reference Voltage Setting 0 4 read-write CRVSSEL CRV Source Voltage Selection 6 1 read-write 0 AVDD is selected as CRV voltage source #0 1 The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage #1 ADC ADC Register Map ADC 0x0 0x0 0x50 registers n 0x100 0x4 registers n 0x74 0x2C registers n ADCHER ADC_ADCHER ADC Channel Enable Register 0x84 read-write n 0x0 0x0 CHEN Analog Input Channel Enable Control\nSet ADCHER[19:0] bits to enable the corresponding analog input channel 19 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\nBesides, set ADCHER[29] to ADCHER[31] bits will enable internal channel for band-gap voltage, temperature sensor and battery power respectively. Other bits are reserved.\nNote1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300k SPS.\nNote2: If the internal channel for temperature sensor (CHEN[30]) is active, the maximum sampling rate will be 300k SPS. 0 32 read-write 0 Channel Disabled 0 1 Channel Enabled 1 ADCMPR0 ADC_ADCMPR0 ADC Compare Register 0 0x88 read-write n 0x0 0x0 CMPCH Compare Channel Selection 3 5 read-write 0 Channel 0 conversion result is selected to be compared #00000 1 Channel 1 conversion result is selected to be compared #00001 2 Channel 2 conversion result is selected to be compared #00010 3 Channel 3 conversion result is selected to be compared #00011 4 Channel 4 conversion result is selected to be compared #00100 5 Channel 5 conversion result is selected to be compared #00101 6 Channel 6 conversion result is selected to be compared #00110 7 Channel 7 conversion result is selected to be compared #00111 8 Channel 8 conversion result is selected to be compared #01000 9 Channel 9 conversion result is selected to be compared #01001 10 Channel 10 conversion result is selected to be compared #01010 11 Channel 11 conversion result is selected to be compared #01011 12 Channel 12 conversion result is selected to be compared #01100 13 Channel 13 conversion result is selected to be compared #01101 14 Channel 14 conversion result is selected to be compared #01110 15 Channel 15 conversion result is selected to be compared #01111 16 Channel 16 conversion result is selected to be compared #10000 17 Channel 17 conversion result is selected to be compared #10001 18 Channel 18 conversion result is selected to be compared #10010 19 Channel 19 conversion result is selected to be compared #10011 29 Band-gap voltage conversion result is selected to be compared #11101 30 Temperature sensor conversion result is selected to be compared #11110 31 Battery power conversion result is selected to be compared #11111 CMPCOND Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one #1 CMPD Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format). 16 12 read-write CMPEN Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register. 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIE Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write CMPWEN Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register. 15 1 read-write 0 Compare Window Mode Disabled #0 1 Compare Window Mode Enabled #1 ADCMPR1 ADC_ADCMPR1 ADC Compare Register 1 0x8C read-write n 0x0 0x0 ADCR ADC_ADCR ADC Control Register 0x80 -1 read-write n 0x0 0x0 ADEN A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D converter Disabled #0 1 A/D converter Enabled #1 ADIE A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode Control\nNote1: When changing the operation mode, software should clear ADST bit first.\nNote2: In Burst mode, the A/D result data is always at ADC Data Register 0. 2 2 read-write 0 Single conversion #00 1 Burst conversion #01 2 Single-cycle Scan #10 3 Continuous Scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset. 11 1 read-write 0 Conversion stops and A/D converter enters idle state #0 1 Conversion starts #1 DIFFEN Differential Input Mode Control\nNote: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel. 10 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF Differential Input Mode Output Format\nIf user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format). 31 1 read-write 0 A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format) #0 1 A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format #1 PTEN PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADDR0~19, ADDR29~ADDR31. Software can enable this bit to generate a PDMA data transfer request. 9 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADDR0~19, ADDR29~ADDR31 Enabled #1 SMPTSEL ADC Internal Sampling Time Selection 16 3 read-write 0 4 ADC clock for sampling 16 ADC clock for complete conversion #000 1 5 ADC clock for sampling 17 ADC clock for complete conversion #001 2 6 ADC clock for sampling 18 ADC clock for complete conversion #010 3 7 ADC clock for sampling 19 ADC clock for complete conversion #011 4 8 ADC clock for sampling 20 ADC clock for complete conversion #100 5 9 ADC clock for sampling 21 ADC clock for complete conversion #101 6 10 ADC clock for sampling 22 ADC clock for complete conversion #110 7 11 ADC clock for sampling 23 ADC clock for complete conversion #111 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger. 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 TRGS Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 1 Timer0 ~ Timer3 overflow pulse trigger #01 2 Reserved. #10 3 A/D conversion is started by PWM trigger #11 ADDR0 ADC_ADDR0 ADC Data Register 0 0x0 read-only n 0x0 0x0 OVERRUN Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read. 16 1 read-only 0 Data in RSLT bits is not overwrote #0 1 Data in RSLT bits is overwrote #1 RSLT A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC. 0 16 read-only VALID Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read. 17 1 read-only 0 Data in RSLT bits is not valid #0 1 Data in RSLT bits is valid #1 ADDR1 ADC_ADDR1 ADC Data Register 1 0x4 read-write n 0x0 0x0 ADDR10 ADC_ADDR10 ADC Data Register 10 0x28 read-write n 0x0 0x0 ADDR11 ADC_ADDR11 ADC Data Register 11 0x2C read-write n 0x0 0x0 ADDR12 ADC_ADDR12 ADC Data Register 12 0x30 read-write n 0x0 0x0 ADDR13 ADC_ADDR13 ADC Data Register 13 0x34 read-write n 0x0 0x0 ADDR14 ADC_ADDR14 ADC Data Register 14 0x38 read-write n 0x0 0x0 ADDR15 ADC_ADDR15 ADC Data Register 15 0x3C read-write n 0x0 0x0 ADDR16 ADC_ADDR16 ADC Data Register 16 0x40 read-write n 0x0 0x0 ADDR17 ADC_ADDR17 ADC Data Register 17 0x44 read-write n 0x0 0x0 ADDR18 ADC_ADDR18 ADC Data Register 18 0x48 read-write n 0x0 0x0 ADDR19 ADC_ADDR19 ADC Data Register 19 0x4C read-write n 0x0 0x0 ADDR2 ADC_ADDR2 ADC Data Register 2 0x8 read-write n 0x0 0x0 ADDR29 ADC_ADDR29 ADC Data Register 29 0x74 read-write n 0x0 0x0 ADDR3 ADC_ADDR3 ADC Data Register 3 0xC read-write n 0x0 0x0 ADDR30 ADC_ADDR30 ADC Data Register 30 0x78 read-write n 0x0 0x0 ADDR31 ADC_ADDR31 ADC Data Register 31 0x7C read-write n 0x0 0x0 ADDR4 ADC_ADDR4 ADC Data Register 4 0x10 read-write n 0x0 0x0 ADDR5 ADC_ADDR5 ADC Data Register 5 0x14 read-write n 0x0 0x0 ADDR6 ADC_ADDR6 ADC Data Register 6 0x18 read-write n 0x0 0x0 ADDR7 ADC_ADDR7 ADC Data Register 7 0x1C read-write n 0x0 0x0 ADDR8 ADC_ADDR8 ADC Data Register 8 0x20 read-write n 0x0 0x0 ADDR9 ADC_ADDR9 ADC Data Register 9 0x24 read-write n 0x0 0x0 ADPDMA ADC_ADPDMA ADC PDMA Current Transfer Data Register 0x100 read-only n 0x0 0x0 CURDAT ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR19 and ADDR29 ~ ADDR31 registers. 0 18 read-only ADSR0 ADC_ADSR0 ADC Status Register0 0x90 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than or equal to 8 samples in FIFO in Burst mode. 0 1 read-write BUSY BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register. 7 1 read-only 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only) 27 5 read-only CMPF0 Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it. 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 CMPF1 Compare Flag 1 When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUNF Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1. 16 1 read-only VALIDF Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1. 8 1 read-only ADSR1 ADC_ADSR1 ADC Status Register1 0x94 read-only n 0x0 0x0 VALID Data Valid Flag (Read Only) VALID[31:29, 19:0] are the mirror of the VALID bits in ADDR31[17] ~ ADDR29[17], ADDR19[17]~ ADDR0[17]. The other bits are reserved. Note: When ADC is in burst mode and any conversion result is valid, VALID[31:29, 19:0] will be set to 1. 0 32 read-only ADSR2 ADC_ADSR2 ADC Status Register2 0x98 read-only n 0x0 0x0 OVERRUN Overrun Flag (Read Only)\nOVERRUN[31:29, 19:0] are the mirror of the OVERRUN bit in ADDR31[16] ~ADDR29[16], ADDR19[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun, OVERRUN[31:29, 19:0] will be set to 1. 0 32 read-only ADTDCR ADC_ADTDCR ADC Trigger Delay Control Register 0x9C read-write n 0x0 0x0 PTDT PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock 0 8 read-write CLK CLK Register Map CLK 0x0 0x0 0x28 registers n 0x30 0xC registers n 0x40 0x4 registers n 0x70 0x10 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 CRCCKEN CRC Generator Controller Clock Enable Bit 7 1 read-write 0 CRC peripheral clock Disabled #0 1 CRC peripheral clock Enabled #1 EBICKEN EBI Controller Clock Enable Bit 3 1 read-write 0 EBI peripheral clock Disabled #0 1 EBI peripheral clock Enabled #1 FMCIDLE Flash Memory Controller Clock Enable Bit in IDLE Mode 15 1 read-write 0 FMC peripheral clock Disabled when chip operating at IDLE mode #0 1 FMC peripheral clock Enabled when chip operating at IDLE mode #1 GPIOACKEN General Purpose I/O PA Group Clock Enable Bit 16 1 read-write 0 GPIO PA group clock Disabled #0 1 GPIO PA group clock Enabled #1 GPIOBCKEN General Purpose I/O PB Group Clock Enable Bit 17 1 read-write 0 GPIO PB group clock Disabled #0 1 GPIO PB group clock Enabled #1 GPIOCCKEN General Purpose I/O PC Group Clock Enable Bit 18 1 read-write 0 GPIO PC group clock Disabled #0 1 GPIO PC group clock Enabled #1 GPIODCKEN General Purpose I/O PD Group Clock Enable Bit 19 1 read-write 0 GPIO PD group clock Disabled #0 1 GPIO PD group clock Enabled #1 GPIOECKEN General Purpose I/O PE Group Clock Enable Bit 20 1 read-write 0 GPIO PE group clock Disabled #0 1 GPIO PE group clock Enabled #1 GPIOFCKEN General Purpose I/O PF Group Clock Enable Bit 21 1 read-write 0 GPIO PF group clock Disabled #0 1 GPIO PF group clock Enabled #1 HDIVCKEN Hardware Divider Controller Clock Enable Bit 4 1 read-write 0 Hardware divider peripheral clock Disabled #0 1 Hardware divider peripheral clock Enabled #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 -1 read-write n 0x0 0x0 ACMP01CKEN Analog Comparator 0/1 Clock Enable Bit 30 1 read-write 0 Analog Comparator 0/1 clock Disabled #0 1 Analog Comparator 0/1 clock Enabled #1 ADCCKEN Analog-digital-converter (ADC) Clock Enable Bit 28 1 read-write 0 ADC clock Disabled #0 1 ADC clock Enabled #1 CLKOCKEN CLKO Clock Enable Bit 6 1 read-write 0 CLKO Clock Disabled #0 1 CLKO Clock Enabled #1 I2C0CKEN I2C0 Clock Enable Bit 8 1 read-write 0 I2C0 Clock Disabled #0 1 I2C0 Clock Enabled #1 I2C1CKEN I2C1 Clock Enable Bit 9 1 read-write 0 I2C1 Clock Disabled #0 1 I2C1 Clock Enabled #1 PWM0CKEN PWM0 Clock Enable Bit 20 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1CKEN PWM1 Clock Enable Bit 21 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 RTCCKEN Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL2[18]). It can be selected to external 32.768 kHz low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). 1 1 read-write 0 RTC Clock Disabled #0 1 RTC Clock Enabled #1 SPI0CKEN SPI0 Clock Enable Bit 12 1 read-write 0 SPI0 Clock Disabled #0 1 SPI0 Clock Enabled #1 SPI1CKEN SPI1 Clock Enable Bit 13 1 read-write 0 SPI1 Clock Disabled #0 1 SPI1 Clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit 2 1 read-write 0 Timer0 Clock Disabled #0 1 Timer0 Clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit 3 1 read-write 0 Timer1 Clock Disabled #0 1 Timer1 Clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit 4 1 read-write 0 Timer2 Clock Disabled #0 1 Timer2 Clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit 5 1 read-write 0 Timer3 Clock Disabled #0 1 Timer3 Clock Enabled #1 UART0CKEN UART0 Clock Enable Bit 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Bit 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 UART2CKEN UART2 Clock Enable Bit 18 1 read-write 0 UART2 clock Disabled #0 1 UART2 clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog Timer Clock Disabled #0 1 Watchdog Timer Clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0x30 read-write n 0x0 0x0 SC0CKEN SC0 Clock Enable Bit 0 1 read-write 0 SC0 Clock Disabled #0 1 SC0 Clock Enabled #1 SC1CKEN SC1 Clock Enable Bit 1 1 read-write 0 SC1 clock Disabled #0 1 SC1 clock Enabled #1 USCI0CKEN USCI0 Clock Enable Bit 8 1 read-write 0 USCI0 clock Disabled #0 1 USCI0 clock Enabled #1 USCI1CKEN USCI1 Clock Enable Bit 9 1 read-write 0 USCI1 clock Disabled #0 1 USCI1 clock Enabled #1 USCI2CKEN USCI2 Clock Enable Bit 10 1 read-write 0 USCI2 clock Disabled #0 1 USCI2 clock Enabled #1 BODCLK CLK_BODCLK Clock Source Select for BOD Control Register 0x40 read-write n 0x0 0x0 VDETCKSEL Clock Source Selection for Voltage Detector\nThe Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL.\nNote1: If LIRC is selected, LIRCEN (CLK_PWRCTL[3]) must be enabled.\nNote2: If LXT is selected, LXTEN (CLK_PWRCTL[1]) must be enabled. 0 1 read-write 0 Clock source is from 10 kHz internal low speed RC oscillator (LIRC) clock #0 1 Clock source is from 32.768 kHz external low speed crystal oscillator (LXT) clock #1 CDLOWB CLK_CDLOWB Clock Frequency Detector Low Boundary Register 0x7C read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CDUPB CLK_CDUPB Clock Frequency Detector Upper Boundary Register 0x78 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit 4 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock Fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit 5 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT)clock Fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Bit 16 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit 17 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 12 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock Fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 13 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock Fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x18 read-write n 0x0 0x0 ADCDIV ADC Clock Divide Number From ADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UARTDIV UART Clock Divide Number From UART Clock Source 8 4 read-write CLKDIV1 CLK_CLKDIV1 Clock Divider Number Register 1 0x38 read-write n 0x0 0x0 SC0DIV SC0 Clock Divide Number From SC0 Clock Source 0 8 read-write SC1DIV SC1 Clock Divide Number From SC1 Clock Source 8 8 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock stop #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 4~24 MHz external high speed crystal oscillator (HXT) clock normal #0 1 4~24 MHz external high speed crystal oscillator (HXT) clock frequency abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'. \nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stop #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x24 read-write n 0x0 0x0 CLK1HZEN Clock Output 1Hz Enable Bit 6 1 read-write 0 1 Hz clock output for 32.768 kHz external low speed crystal oscillator (LXT) frequency compensation Disabled #0 1 1 Hz clock output for 32.768 kHz external low speed crystal oscillator (LXT) frequency compensation Enabled #1 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PLL clock #010 3 Clock source from LIRC #011 4 Clock source from HIRC48 #100 7 Clock source from HIRC clock #111 PCLK0SEL PCLK0 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 APB0 BUS clock source from HCLK #0 1 APB0 BUS clock source from HCLK/2 #1 PCLK1SEL PCLK1 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 APB1 BUS clock source from HCLK #0 1 APB1 BUS clock source from HCLK/2 #1 STCLKSEL Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/2 #111 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADCSEL ADC Clock Source Selection 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #11 PWM0SEL PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL. 28 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK0 #1 PWM1SEL PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. 29 1 read-write 0 Clock source from PLL clock #0 1 Clock source from PCLK1 #1 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T0 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #111 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T1 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #111 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T2 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #111 TMR3SEL TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T3 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #111 UARTSEL UART Clock Source Selection 24 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #00 1 Clock source from PLL clock #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Reserved. #00 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #01 2 Clock source from HCLK/2048 clock #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) clock #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 2 3 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) clock #001 2 Clock source from HCLK #010 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #011 5 Clock source from 48 MHz internal high speed RC oscillator (HIRC48) clock #101 RTCSEL RTC Clock Source Selection 18 1 read-write 0 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #0 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #1 SPI0SEL SPI0 Clock Source Selection 24 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK0 #10 3 Clock source from 48 MHz internal high speed RC oscillator (HIRC48) clock #11 SPI1SEL SPI1 Clock Source Selection 26 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK0 #10 3 Clock source from 48 MHz internal high speed RC oscillator (HIRC48) clock #11 WWDTSEL Window Watchdog Timer Clock Source Selection 16 2 read-write 2 Clock source from HCLK/2048 clock #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 CLKSEL3 CLK_CLKSEL3 Clock Source Select Control Register 3 0x34 read-write n 0x0 0x0 SC0SEL SC0 Clock Source Selection 0 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillato r(HXT) clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK1 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #11 SC1SEL SC1 Clock Source Selection 2 2 read-write 0 Clock source from 4~24 MHz external high speed crystal oscillator (HXT) clock #00 1 Clock source from PLL clock #01 2 Clock source from PCLK1 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) clock #11 PLLCTL CLK_PLLCTL PLL Control Register 0x20 -1 read-write n 0x0 0x0 BP PLL Bypass Control 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control \nRefer to the formulas below the table. 0 9 read-write INDIV PLL Input Divider Control \nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT Enable) Control 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control \nRefer to the formulas below the table. 14 2 read-write PD Power-down Mode \nIf set PDEN(CLK_PWRCTL[7]) bit to 1, the PLL will enter Power-down mode, too. 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in Power-down mode (default) #1 PLLSRC PLL Source Clock Selection 19 1 read-write 0 PLL source clock from external 4~24 MHz high-speed crystal (HXT) #0 1 PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC) #1 STBSEL PLL Stable Counter Selection 23 1 read-write 0 PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz) #0 1 PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz) #1 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 HIRC48EN HIRC48 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 48 MHz internal high speed RC oscillator (HIRC48) Disabled #0 1 48 MHz internal high speed RC oscillator (HIRC48) Enabled #1 HIRCEN HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled #1 HXTEN HXT Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from HXT, this bit is set to 1 automatically.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register 0 1 read-write 0 4~24 MHz External High Speed Crystal (HXT) Disabled #0 1 4~24 MHz External High Speed Crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 10 2 read-write 0 HXT frequency is lower than from 8 MHz #00 1 HXT frequency is from 8 MHz to 12 MHz #01 2 HXT frequency is from 12 MHz to 16 MHz #10 3 HXT frequency is higher than 16 MHz #11 HXTSELTYP HXT Crystal Type Select Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 Select INV type #0 1 Select GM type #1 LIRCEN LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 LXTEN LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 32.768 KHz External Low Speed Crystal (LXT) Disabled #0 1 32.768 KHz External Low Speed Crystal (LXT) Enabled #1 PDEN System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT, HIRC and the HIRC48 will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip waits CPU sleep command WFI and then enters Power-down mode #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal oscillator (HXT), 256 clock cycles when chip work at 22.1184 MHz internal high speed RC oscillator (HIRC) and 512 clock cycles when chip work at 48 MHz internal high speed RC oscillator (HIRC48).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status Set by 'Power-down wake-up event', it indicates that resume from Power-down mode' The flag is set if the EINT0~5, GPIO, UART0~2, WDT, ACMP01, BOD, VDET, RTC, TMR0~3, I2C0~1 or USCI0~2 wake-up occurred. Note1: This bit can be cleared by software writing '1'. Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write STATUS CLK_STATUS Clock Status Monitor Register 0xC read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRC48STB HIRC48 Clock Source Stable Flag (Read Only) 5 1 read-only 0 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled #0 1 48 MHz internal high speed RC oscillator (HIRC48) clock is stabe and enabled #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) clock is stabe and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal oscillator (HXT)clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only) 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only) 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 CRC CRC Register Map CRC 0x0 0x0 0x10 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0xC -1 read-only n 0x0 0x0 CHECKSUM CRC Checksum Results\nThis field indicates the CRC checksum result.\nNote: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 -1 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]). 27 1 read-write 0 1's complement for CRC CHECKSUM Disabled #0 1 1's complement for CRC CHECKSUM Enabled #1 CHKSINIT Checksum Initialization\nSet this bit will auto reolad SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.\nNote: This bit will be cleared automatically. 1 1 read-write 0 No effect #0 1 Reolad SEED value to CHECKSUM as CRC operation initial value #1 CHKSREV Checksum Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC CHECKSUM Disabled #0 1 Bit order reverse for CRC CHECKSUM Enabled #1 CRCEN CRC Generator Enable Bit\nSet this bit 1 to enable CRC generator for CRC operation. 0 1 read-write 0 No effect #0 1 CRC generator is active #1 CRCMODE CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 DATFMT Write Data 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]). 26 1 read-write 0 1's complement for CRC DATA Disabled #0 1 1's complement for CRC DATA Enabled #1 DATLEN CPU Write Data Length This field indicates the valid write data length of DATA (CRC_DAT[31:0]). Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 28 2 read-write 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode.\nData length is 32-bit mode #01 DATREV Write Data Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 24 1 read-write 0 Bit order reversed for CRC DATA Disabled #0 1 Bit order reversed for CRC DATA Enabled (per byte) #1 DAT CRC_DAT CRC Write Data Register 0x4 read-write n 0x0 0x0 DATA CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x8 -1 read-write n 0x0 0x0 SEED CRC Seed Value\nThis field indicates the CRC seed value.\nNote1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.\nNote2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). 0 32 read-write EBI EBI Register Map EBI 0x0 0x0 0x8 registers n 0x10 0x8 registers n CTL0 EBI_CTL0 External Bus Interface Bank0 Control Register 0x0 read-write n 0x0 0x0 CACCESS Continuous Data Access Mode\nWhen continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. 4 1 read-write 0 Continuous data access mode Disabled #0 1 Continuous data access mode Enabled #1 CSPOLINV Chip Select Pin Polar Inverse 2 1 read-write 0 Chip select pin (EBI_nCSx) is active low #0 1 Chip select pin (EBI_nCSx) is active high #1 DW16 EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit. 1 1 read-write 0 EBI data width is 8-bit #0 1 EBI data width is 16-bit #1 EN EBI Enable Bit\nThis bit is the functional enable bit for EBI. 0 1 read-write 0 EBI function Disabled #0 1 EBI function Enabled #1 MCLKDIV External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 8 3 read-write 0 HCLK/1 #000 1 HCLK/2 #001 2 HCLK/4 #010 3 HCLK/8 #011 4 HCLK/16 #100 5 HCLK/32 #101 6 HCLK/64 #110 7 HCLK/128 #111 TALE Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register 16 3 read-write CTL1 EBI_CTL1 External Bus Interface Bank1 Control Register 0x10 read-write n 0x0 0x0 TCTL0 EBI_TCTL0 External Bus Interface Bank0 Timing Control Register 0x4 read-write n 0x0 0x0 R2R Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle. 24 4 read-write RAHDOFF Access Hold Time Disable Control When Read 22 1 read-write 0 Data Access Hold Time (tAHD) during EBI reading Enabled #0 1 Data Access Hold Time (tAHD) during EBI reading Disabled #1 TACC EBI Data Access Time\nTACC define data access time (tACC). 3 5 read-write TAHD EBI Data Access Hold Time\nTAHD define data access hold time (tAHD). 8 3 read-write W2X Idle Cycle After Write\nThis field defines the number of W2X idle cycle. 12 4 read-write WAHDOFF Access Hold Time Disable Control When Write 23 1 read-write 0 Data Access Hold Time (tAHD) during EBI writing Enabled #0 1 Data Access Hold Time (tAHD) during EBI writing Disabled #1 TCTL1 EBI_TCTL1 External Bus Interface Bank1 Timing Control Register 0x14 read-write n 0x0 0x0 FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n 0x80 0x10 registers n 0xC0 0x8 registers n DFBA FMC_DFBA Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 0 32 read-only FTCTL FMC_FTCTL Flash Access Time Control Register 0x18 read-write n 0x0 0x0 CACHEOFF Flash Cache Disable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Flash Cache function Enabled (default) #0 1 Flash Cache function Disabled #1 FOM Frequency Optimization Mode (Write Protect)\nThe M0564 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 4 3 read-write 1 Frequency 24MHz. Frequency 72MHz #001 ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADDR ISP Address\nThe NuMicro M0564 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. 0 32 read-write ISPCMD FMC_ISPCMD ISP CMD Register 0xC read-write n 0x0 0x0 CMD ISP CMD\nISP command table is shown below:\nThe other commands are invalid. 0 7 read-write 0 FLASH Read 0x00 4 Read Unique ID 0x04 8 Read Flash All-One Result 0x08 11 Read Company ID 0x0b 12 Read Device ID 0x0c 13 Read Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase 0x22 38 FLASH Mass Erase 0x26 39 FLASH Multi-Word Program 0x27 40 Run Flash All-One Verification 0x28 45 Run Checksum Calculation 0x2d 46 Vector Remap 0x2e 64 FLASH 64-bit Read 0x40 97 FLASH 64-bit Program 0x61 ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Booting from APROM #0 1 Booting from LDROM #1 CFGUEN CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 ISPEN ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection\n(7) Erase or Program command at brown-out detected\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 SPUEN SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 SPROM cannot be updated #0 1 SPROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 ALLONE Flash All-one Verification Flag This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1 7 1 read-write 0 Flash bits are not all 1 after 'Run Flash All-One Verification' complete #0 1 All of flash bits are 1 after 'Run Flash All-One Verification' complete #1 CBS Boot Selection of CONFIG (Read Only) This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 ISPBUSY ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection\n(7) Erase or Program command at brown-out detected\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands.\n(10) system vector address is remapped to SPROM.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 6 1 read-write SCODE Security Code Active Flag This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation. 31 1 read-write 0 Secured code is inactive #0 1 Secured code is active #1 VECMAP Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.\nVECMAP [18:12] should be 0. 9 21 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 MPADDR FMC_MPADDR ISP Multi-program Address Register 0xC4 read-only n 0x0 0x0 MPADDR ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete. 0 32 read-only MPDAT0 FMC_MPDAT0 ISP Data0 Register 0x80 read-write n 0x0 0x0 ISPDAT0 ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data. 0 32 read-write MPDAT1 FMC_MPDAT1 ISP Data1 Register 0x84 read-write n 0x0 0x0 ISPDAT1 ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming. 0 32 read-write MPDAT2 FMC_MPDAT2 ISP Data2 Register 0x88 read-write n 0x0 0x0 ISPDAT2 ISP Data 2\nThis register is the third 32-bit data for multi-word programming. 0 32 read-write MPDAT3 FMC_MPDAT3 ISP Data3 Register 0x8C read-write n 0x0 0x0 ISPDAT3 ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming. 0 32 read-write MPSTS FMC_MPSTS ISP Multi-program Status Register 0xC0 read-only n 0x0 0x0 D0 ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 4 1 read-only 0 FMC_MPDAT0 register is empty, or program to flash complete #0 1 FMC_MPDAT0 register has been written, and not program to flash complete #1 D1 ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 5 1 read-only 0 FMC_MPDAT1 register is empty, or program to flash complete #0 1 FMC_MPDAT1 register has been written, and not program to flash complete #1 D2 ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 6 1 read-only 0 FMC_MPDAT2 register is empty, or program to flash complete #0 1 FMC_MPDAT2 register has been written, and not program to flash complete #1 D3 ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 7 1 read-only 0 FMC_MPDAT3 register is empty, or program to flash complete #0 1 FMC_MPDAT3 register has been written, and not program to flash complete #1 ISPFF ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands 2 1 read-only MPBUSY ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP Multi-Word program operation is finished #0 1 ISP Multi-Word program operation is progressed #1 PPGO ISP Multi-program Status (Read Only) 1 1 read-only 0 ISP multi-word program operation is not active #0 1 ISP multi-word program operation is in progress #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x30 registers n 0x140 0x2C registers n 0x180 0x4 registers n 0x200 0x138 registers n 0x340 0x20 registers n 0x40 0x2C registers n 0x80 0x2C registers n 0xC0 0x2C registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the internal 10 kHz internal low speed oscillator #1 ICLKON Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output 0x200 read-write n 0x0 0x0 PDIO GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA10_PDIO PA10_PDIO GPIO PA.n Pin Data Input/Output 0x228 read-write n 0x0 0x0 PA11_PDIO PA11_PDIO GPIO PA.n Pin Data Input/Output 0x22C read-write n 0x0 0x0 PA12_PDIO PA12_PDIO GPIO PA.n Pin Data Input/Output 0x230 read-write n 0x0 0x0 PA13_PDIO PA13_PDIO GPIO PA.n Pin Data Input/Output 0x234 read-write n 0x0 0x0 PA14_PDIO PA14_PDIO GPIO PA.n Pin Data Input/Output 0x238 read-write n 0x0 0x0 PA15_PDIO PA15_PDIO GPIO PA.n Pin Data Input/Output 0x23C read-write n 0x0 0x0 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output 0x204 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output 0x208 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output 0x20C read-write n 0x0 0x0 PA4_PDIO PA4_PDIO GPIO PA.n Pin Data Input/Output 0x210 read-write n 0x0 0x0 PA5_PDIO PA5_PDIO GPIO PA.n Pin Data Input/Output 0x214 read-write n 0x0 0x0 PA6_PDIO PA6_PDIO GPIO PA.n Pin Data Input/Output 0x218 read-write n 0x0 0x0 PA7_PDIO PA7_PDIO GPIO PA.n Pin Data Input/Output 0x21C read-write n 0x0 0x0 PA8_PDIO PA8_PDIO GPIO PA.n Pin Data Input/Output 0x220 read-write n 0x0 0x0 PA9_PDIO PA9_PDIO GPIO PA.n Pin Data Input/Output 0x224 read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC read-write n 0x0 0x0 DATMSK0 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote3: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-bounce Enable Control 0x14 read-write n 0x0 0x0 DBEN0 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nNote2: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF0 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote2: The PE.14/PE.15 pin is ignored. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT0 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control 0x1C read-write n 0x0 0x0 FLIEN0 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1:\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote2: The PE.14/PE.15 pin is ignored. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC0 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 0 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC1 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 1 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC10 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 10 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC11 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 11 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC12 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 12 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC13 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 13 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC14 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 14 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC15 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 15 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC2 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 2 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC3 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 3 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC4 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 4 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC5 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 5 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC6 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 6 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC7 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 7 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC8 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 8 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC9 Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored 9 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 read-write n 0x0 0x0 TYPE0 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored. 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 0 1 read-only PIN1 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 1 1 read-only PIN10 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 10 1 read-only PIN11 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 11 1 read-only PIN12 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 12 1 read-only PIN13 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 13 1 read-only PIN14 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 14 1 read-only PIN15 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 15 1 read-only PIN2 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 2 1 read-only PIN3 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 3 1 read-only PIN4 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 4 1 read-only PIN5 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 5 1 read-only PIN6 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 6 1 read-only PIN7 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 7 1 read-only PIN8 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 8 1 read-only PIN9 Port A-f Pin[n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note1: Note2: The PE.14/PE.15 pin is ignored. 9 1 read-only PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control 0x28 read-write n 0x0 0x0 HSREN0 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 0 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN1 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 1 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN10 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 10 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN11 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 11 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN12 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 12 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN13 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 13 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN14 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 14 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN15 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 15 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN2 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 2 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN3 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 3 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN4 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 4 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN5 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 5 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN6 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 6 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN7 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 7 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN8 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 8 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN9 Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored.. 9 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable 0x24 read-write n 0x0 0x0 SMTEN0 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored. 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output 0x240 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output 0x268 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output 0x26C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output 0x270 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output 0x274 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output 0x278 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output 0x27C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output 0x244 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output 0x248 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output 0x24C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output 0x250 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output 0x254 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output 0x258 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output 0x25C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output 0x260 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output 0x264 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-bounce Enable Control 0x54 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control 0x5C read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control 0x68 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable 0x64 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output 0x280 read-write n 0x0 0x0 PC10_PDIO PC10_PDIO GPIO PC.n Pin Data Input/Output 0x2A8 read-write n 0x0 0x0 PC11_PDIO PC11_PDIO GPIO PC.n Pin Data Input/Output 0x2AC read-write n 0x0 0x0 PC12_PDIO PC12_PDIO GPIO PC.n Pin Data Input/Output 0x2B0 read-write n 0x0 0x0 PC13_PDIO PC13_PDIO GPIO PC.n Pin Data Input/Output 0x2B4 read-write n 0x0 0x0 PC14_PDIO PC14_PDIO GPIO PC.n Pin Data Input/Output 0x2B8 read-write n 0x0 0x0 PC15_PDIO PC15_PDIO GPIO PC.n Pin Data Input/Output 0x2BC read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output 0x284 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output 0x288 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output 0x28C read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output 0x290 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output 0x294 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output 0x298 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output 0x29C read-write n 0x0 0x0 PC8_PDIO PC8_PDIO GPIO PC.n Pin Data Input/Output 0x2A0 read-write n 0x0 0x0 PC9_PDIO PC9_PDIO GPIO PC.n Pin Data Input/Output 0x2A4 read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-bounce Enable Control 0x94 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control 0x9C read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control 0xA8 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable 0xA4 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output 0x2C0 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output 0x2E8 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output 0x2EC read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output 0x2F0 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output 0x2F4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output 0x2F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output 0x2FC read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output 0x2C4 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output 0x2C8 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output 0x2CC read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output 0x2D0 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output 0x2D4 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output 0x2D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output 0x2DC read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output 0x2E0 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output 0x2E4 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-bounce Enable Control 0xD4 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control 0xDC read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control 0xE8 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable 0xE4 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output 0x300 read-write n 0x0 0x0 PE10_PDIO PE10_PDIO GPIO PE.n Pin Data Input/Output 0x328 read-write n 0x0 0x0 PE11_PDIO PE11_PDIO GPIO PE.n Pin Data Input/Output 0x32C read-write n 0x0 0x0 PE12_PDIO PE12_PDIO GPIO PE.n Pin Data Input/Output 0x330 read-write n 0x0 0x0 PE13_PDIO PE13_PDIO GPIO PE.n Pin Data Input/Output 0x334 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output 0x304 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output 0x308 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.n Pin Data Input/Output 0x30C read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.n Pin Data Input/Output 0x310 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output 0x314 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.n Pin Data Input/Output 0x318 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.n Pin Data Input/Output 0x31C read-write n 0x0 0x0 PE8_PDIO PE8_PDIO GPIO PE.n Pin Data Input/Output 0x320 read-write n 0x0 0x0 PE9_PDIO PE9_PDIO GPIO PE.n Pin Data Input/Output 0x324 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-bounce Enable Control 0x114 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 read-write n 0x0 0x0 PE_DRVCTL PE_DRVCTL PE High Drive Strength Control 0x12C read-write n 0x0 0x0 HDRVEN10 Port E Pin[n] Driving Strength Control 10 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN11 Port E Pin[n] Driving Strength Control 11 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN12 Port E Pin[n] Driving Strength Control 12 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN13 Port E Pin[n] Driving Strength Control 13 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN8 Port E Pin[n] Driving Strength Control 8 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN9 Port E Pin[n] Driving Strength Control 9 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 PE_INTEN PE_INTEN PE Interrupt Enable Control 0x11C read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control 0x128 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable 0x124 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output 0x340 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output 0x344 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output 0x348 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output 0x34C read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output 0x350 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output 0x354 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output 0x358 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output 0x35C read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-bounce Enable Control 0x154 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control 0x15C read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control 0x168 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable 0x164 read-write n 0x0 0x0 HDIV HDIV Register Map HDIV 0x0 0x0 0x14 registers n DIVIDEND HDIV_DIVIDEND Dividend Source Register 0x0 read-write n 0x0 0x0 DIVIDEND Dividend Source\nThis register is given the dividend of divider before calculation starting. 0 32 read-write DIVISOR HDIV_DIVISOR Divisor Source Resister 0x4 -1 read-write n 0x0 0x0 DIVISOR Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate. 0 16 read-write DIVQUO HDIV_DIVQUO Quotient Result Resister 0x8 read-write n 0x0 0x0 QUOTIENT Quotient Result\nThis register holds the quotient result of divider after calculation complete. 0 32 read-write DIVREM HDIV_DIVREM Remainder Result Register 0xC read-write n 0x0 0x0 REMAINDER Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.\nThis register holds the remainder result of divider after calculation complete. 0 32 read-write DIVSTS HDIV_DIVSTS Divider Status Register 0x10 -1 read-only n 0x0 0x0 DIV0 Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only. 1 1 read-only 0 The divisor is not 0 #0 1 The divisor is 0 #1 FINISH Division Finish Flag\nThe flag will become low when the divider is in calculation. The flag will go back to high once the calculation finished. 0 1 read-only 0 Under Calculation #0 1 Calculation finished #1 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x14 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C serial function Disabled #0 1 I2C serial function Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 NSTRETCH No Stretch on the I2C Bus 7 1 read-write 0 I2C SCL bus is stretched by hardware if the SI is not cleared in master mode #0 1 I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode #1 OVRIEN I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer. 3 1 read-write PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic. This bit will be cleared to 0 automatically #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C sends STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TWOBUFEN Two-level Buffer Enable Bit 5 1 read-write 0 Two-level buffer Disabled #0 1 Two-level buffer Enabled #1 TWOBUFRST Two-level Buffer Reset 6 1 read-write 0 No effect #0 1 Reset the related counters, two-level buffer state machine, and the content of data buffer #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UDRIEN I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-only n 0x0 0x0 EMPTY Two-level Buffer Empty\nThis bit is set when POINTER is equal to 0. 5 1 read-only FULL Two-level Buffer Full\nThis bit is set when POINTER is equal to 2 4 1 read-only ONBUSY on Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 OVR I2C over Run Status Bit 6 1 read-only UDR I2C Under Run Status Bit 7 1 read-only I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 6 6 read-write STCTL Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 6 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C don't hold bus after wake-up disable #0 1 I2C don't hold bus after wake-up enable #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x14 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C serial function Disabled #0 1 I2C serial function Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_CTL1 I2C_CTL1 I2C Control Register 1 0x44 read-write n 0x0 0x0 NSTRETCH No Stretch on the I2C Bus 7 1 read-write 0 I2C SCL bus is stretched by hardware if the SI is not cleared in master mode #0 1 I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode #1 OVRIEN I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer. 3 1 read-write PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic. This bit will be cleared to 0 automatically #1 PDMASTR PDMA Stretch Bit 8 1 read-write 0 I2C sends STOP automatically after PDMA transfer done. (only master TX) #0 1 I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX) #1 RXPDMAEN PDMA Receive Channel Available 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TWOBUFEN Two-level Buffer Enable Bit 5 1 read-write 0 Two-level buffer Disabled #0 1 Two-level buffer Enabled #1 TWOBUFRST Two-level Buffer Reset 6 1 read-write 0 No effect #0 1 Reset the related counters, two-level buffer state machine, and the content of data buffer #1 TXPDMAEN PDMA Transmit Channel Available 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 UDRIEN I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0 0xC -1 read-only n 0x0 0x0 STATUS I2C Status 0 8 read-only I2C_STATUS1 I2C_STATUS1 I2C Status Register 1 0x48 read-only n 0x0 0x0 EMPTY Two-level Buffer Empty\nThis bit is set when POINTER is equal to 0. 5 1 read-only FULL Two-level Buffer Full\nThis bit is set when POINTER is equal to 2 4 1 read-only ONBUSY on Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected. 8 1 read-only 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 OVR I2C over Run Status Bit 6 1 read-only UDR I2C Under Run Status Bit 7 1 read-only I2C_TMCTL I2C_TMCTL I2C Timing Configure Control Register 0x4C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 6 6 read-write STCTL Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs. 0 6 read-write I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Time-out period is extend 4 times Disabled #0 1 Time-out period is extend 4 times Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 NHDBUSEN I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 7 1 read-write 0 I2C don't hold bus after wake-up disable #0 1 I2C don't hold bus after wake-up enable #1 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit. 1 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WRSTSWK Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit. 2 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 INT INT Register Map INT 0x0 0x0 0x84 registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC IRQ12 (UART0/2) Interrupt Source Identity 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC IRQ13 (UART1) Interrupt Source Identity 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC IRQ15 (SPI1) Interrupt Source Identity 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC Reserved. 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC Reserved. 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC IRQ19 (I2C1) Interrupt Source Identity 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC Reserved. 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC Reserved. 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC IRQ22 (USCI0/1/2) Interrupt Source Identity 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC Reserved. 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC IRQ24 (SC0/1) Interrupt Source Identify 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (ACMP) Interrupt Source Identity 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC IRQ26 (PDMA) Interrupt Source Identity 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC Reserved. 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC IRQ2 (EINT0/2/4) Interrupt Source Identity 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC IRQ30 (IRC/CLKD) Interrupt Source Identity 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC IRQ31 (RTC) Interrupt Source Identity 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1/3/5) Interrupt Source Identity 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC IRQ4 (GPA/B) Interrupt Source Identity 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC IRQ5 (GPC/D/E/F) Interrupt Source Identity 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC IRQ6 (PWM0) Interrupt Source Identity 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC IRQ7 (PWM1) Interrupt Source Identity 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-write n 0x0 0x0 NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_EN NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. 0 5 read-write PDMA PDMA Register Map PDMA 0x0 0x0 0x64 registers n 0x400 0x44 registers n 0x460 0x4 registers n 0x480 0x8 registers n ABTSTS PDMA_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 read-write n 0x0 0x0 ABTIF0 PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 0 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF1 PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 1 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF2 PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 2 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF3 PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 3 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 ABTIF4 PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. 4 1 read-write 0 No AHB bus ERROR response received when channel n transfer #0 1 AHB bus ERROR response received when channel n transfer #1 CHCTL PDMA_CHCTL PDMA Channel Control Register 0x400 read-write n 0x0 0x0 CHEN0 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 0 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN1 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 1 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN2 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 2 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN3 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 3 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CHEN4 PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit. 4 1 read-write 0 PDMA channel [n] Disabled #0 1 PDMA channel [n] Enabled #1 CURSCAT0 PDMA_CURSCAT0 Current Scatter-gather Descriptor Table Address of PDMA Channel 0 0x50 read-only n 0x0 0x0 CURADDR PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 0 32 read-only CURSCAT1 PDMA_CURSCAT1 Current Scatter-gather Descriptor Table Address of PDMA Channel 1 0x54 read-write n 0x0 0x0 CURSCAT2 PDMA_CURSCAT2 Current Scatter-gather Descriptor Table Address of PDMA Channel 2 0x58 read-write n 0x0 0x0 CURSCAT3 PDMA_CURSCAT3 Current Scatter-gather Descriptor Table Address of PDMA Channel 3 0x5C read-write n 0x0 0x0 CURSCAT4 PDMA_CURSCAT4 Current Scatter-gather Descriptor Table Address of PDMA Channel 4 0x60 read-write n 0x0 0x0 DSCT0_CTL PDMA_DSCT0_CTL Descriptor Table Control Register of PDMA Channel 0 0x0 read-write n 0x0 0x0 BURSIZE Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment\nThis field is used to set the destination address increment size. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved. #11 SAINC Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size. 8 2 read-write 3 No Increment (Fixed Address) #11 TBINTDIS Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.\nNote: If this bit set to '1', the TEMPTYF will not be set. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately. 16 14 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment. The source address is aligned when TXWIDTH is byte or half-word transfer. 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved. #11 DSCT0_DA PDMA_DSCT0_DA Destination Address Register of PDMA Channel 0 0x8 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller. 0 32 read-write DSCT0_FIRST PDMA_DSCT0_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 0 0xC read-write n 0x0 0x0 FIRST PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.\nNote1: The first descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 0 16 read-write NEXT PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory. \nNote: write operation is useless in this field. 16 16 read-write DSCT0_SA PDMA_DSCT0_SA Source Address Register of PDMA Channel 0 0x4 read-write n 0x0 0x0 SA PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller. 0 32 read-write DSCT1_CTL PDMA_DSCT1_CTL Descriptor Table Control Register of PDMA Channel 1 0x10 read-write n 0x0 0x0 DSCT1_DA PDMA_DSCT1_DA Destination Address Register of PDMA Channel 1 0x18 read-write n 0x0 0x0 DSCT1_FIRST PDMA_DSCT1_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 1 0x1C read-write n 0x0 0x0 DSCT1_SA PDMA_DSCT1_SA Source Address Register of PDMA Channel 1 0x14 read-write n 0x0 0x0 DSCT2_CTL PDMA_DSCT2_CTL Descriptor Table Control Register of PDMA Channel 2 0x20 read-write n 0x0 0x0 DSCT2_DA PDMA_DSCT2_DA Destination Address Register of PDMA Channel 2 0x28 read-write n 0x0 0x0 DSCT2_FIRST PDMA_DSCT2_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 2 0x2C read-write n 0x0 0x0 DSCT2_SA PDMA_DSCT2_SA Source Address Register of PDMA Channel 2 0x24 read-write n 0x0 0x0 DSCT3_CTL PDMA_DSCT3_CTL Descriptor Table Control Register of PDMA Channel 3 0x30 read-write n 0x0 0x0 DSCT3_DA PDMA_DSCT3_DA Destination Address Register of PDMA Channel 3 0x38 read-write n 0x0 0x0 DSCT3_FIRST PDMA_DSCT3_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 3 0x3C read-write n 0x0 0x0 DSCT3_SA PDMA_DSCT3_SA Source Address Register of PDMA Channel 3 0x34 read-write n 0x0 0x0 DSCT4_CTL PDMA_DSCT4_CTL Descriptor Table Control Register of PDMA Channel 4 0x40 read-write n 0x0 0x0 DSCT4_DA PDMA_DSCT4_DA Destination Address Register of PDMA Channel 4 0x48 read-write n 0x0 0x0 DSCT4_FIRST PDMA_DSCT4_FIRST First Scatter-gather Descriptor Table Offset of PDMA Channel 4 0x4C read-write n 0x0 0x0 DSCT4_SA PDMA_DSCT4_SA Source Address Register of PDMA Channel 4 0x44 read-write n 0x0 0x0 INTEN PDMA_INTEN PDMA Interrupt Enable Register 0x418 read-write n 0x0 0x0 INTEN0 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 0 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN1 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 1 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN2 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 2 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN3 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 3 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTEN4 PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 4 1 read-write 0 PDMA channel n interrupt Disabled #0 1 PDMA channel n interrupt Enabled #1 INTSTS PDMA_INTSTS PDMA Interrupt Status Register 0x41C read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-only 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 REQTOF0 PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits. 8 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 REQTOF1 PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits. 9 1 read-write 0 No request time-out #0 1 Peripheral request time-out #1 TDIF Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 TEIF Table Empty Interrupt Flag (Read Only)\nThis bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty. 2 1 read-only 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty #1 PAUSE PDMA_PAUSE PDMA Transfer Pause Control Register 0x404 write-only n 0x0 0x0 PAUSE0 PDMA Channel N Transfer Pause Control Register (Write Only) 0 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE1 PDMA Channel N Transfer Pause Control Register (Write Only) 1 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE2 PDMA Channel N Transfer Pause Control Register (Write Only) 2 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE3 PDMA Channel N Transfer Pause Control Register (Write Only) 3 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PAUSE4 PDMA Channel N Transfer Pause Control Register (Write Only) 4 1 write-only 0 No effect #0 1 Pause PDMA channel n transfer #1 PRICLR PDMA_PRICLR PDMA Fixed Priority Clear Register 0x414 write-only n 0x0 0x0 FPRICLR0 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 0 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR1 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 1 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR2 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 2 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR3 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 3 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 FPRICLR4 PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority. 4 1 write-only 0 No effect #0 1 Clear PDMA channel [n] fixed priority setting #1 PRISET PDMA_PRISET PDMA Fixed Priority Setting Register 0x410 read-write n 0x0 0x0 FPRISET0 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 0 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET1 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 1 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET2 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 2 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET3 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 3 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 FPRISET4 PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 4 1 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority #0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority #1 REQSEL0_3 PDMA_REQSEL0_3 PDMA Channel 0 to Channel 3 Request Source Select Register 0x480 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote1: A request source can't assign to two channels at the same time.\nNote2: This field is useless when transfer between memory and memory. 0 6 read-write 0 Disable PDMA 0 16 Channel connects to SPI0_TX 16 17 Channel connects to SPI0_RX 17 18 Channel connects to SPI1_TX 18 19 Channel connects to SPI1_RX 19 20 Channel connects to ADC_RX 20 21 Channel connects to PWM0_P1_RX 21 22 Channel connects to PWM0_P2_RX 22 23 Channel connects to PWM0_P3_RX 23 24 Channel connects to PWM1_P1_RX 24 25 Channel connects to PWM1_P2_RX 25 26 Channel connects to PWM1_P3_RX 26 28 Channel connects to I2C0_TX 28 29 Channel connects to I2C0_RX 29 30 Channel connects to I2C1_TX 30 31 Channel connects to I2C1_RX 31 32 Channel connects to TMR0 32 33 Channel connects to TMR1 33 34 Channel connects to TMR2 34 35 Channel connects to TMR3 35 4 Channel connects to UART0_TX 4 5 Channel connects to UART0_RX 5 6 Channel connects to UART1_TX 6 7 Channel connects to UART1_RX 7 8 Channel connects to UART2_TX 8 9 Channel connects to UART2_RX 9 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 6 read-write REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 6 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 6 read-write REQSEL4 PDMA_REQSEL4 PDMA Channel 4 Request Source Select Register 0x484 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0 0 6 read-write RESET PDMA_RESET PDMA Channel Reset Control Register 0x460 read-write n 0x0 0x0 RESET0 PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process. 0 1 read-write 0 No effect #0 1 Reset PDMA channel n #1 RESET1 PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process. 1 1 read-write 0 No effect #0 1 Reset PDMA channel n #1 RESET2 PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process. 2 1 read-write 0 No effect #0 1 Reset PDMA channel n #1 RESET3 PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process. 3 1 read-write 0 No effect #0 1 Reset PDMA channel n #1 RESET4 PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process. 4 1 read-write 0 No effect #0 1 Reset PDMA channel n #1 SCATBA PDMA_SCATBA PDMA Scatter-gather Descriptor Table Base Address Register 0x43C -1 read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode. 16 16 read-write SCATSTS PDMA_SCATSTS PDMA Scatter-gather Table Empty Status Register 0x428 read-write n 0x0 0x0 TEMPTYF0 Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits. 0 1 read-write 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set #1 TEMPTYF1 Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits. 1 1 read-write 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set #1 TEMPTYF2 Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits. 2 1 read-write 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set #1 TEMPTYF3 Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits. 3 1 read-write 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set #1 TEMPTYF4 Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits. 4 1 read-write 0 PDMA channel scatter-gather table is not empty #0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set #1 SWREQ PDMA_SWREQ PDMA Software Request Register 0x408 write-only n 0x0 0x0 SWREQ0 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ1 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 1 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ2 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 2 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ3 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 3 1 write-only 0 No effect #0 1 Generate a software request #1 SWREQ4 PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 4 1 write-only 0 No effect #0 1 Generate a software request #1 TACTSTS PDMA_TACTSTS PDMA Transfer Active Flag Register 0x42C read-only n 0x0 0x0 TXACTF0 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 0 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF1 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 1 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF2 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 2 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF3 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 3 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TXACTF4 PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 4 1 read-only 0 PDMA channel is not finished #0 1 PDMA channel is active #1 TDSTS PDMA_TDSTS PDMA Channel Transfer Done Flag Register 0x424 read-write n 0x0 0x0 TDIF0 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF1 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 1 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF2 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 2 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF3 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 3 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TDIF4 PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 4 1 read-write 0 PDMA channel transfer has not finished #0 1 PDMA channel has finished transmission #1 TOC0_1 PDMA_TOC0_1 PDMA Channel 0 and Channel 1 Time-out Counter Register 0x440 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 0 16 read-write TOC1 Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description. 16 16 read-write TOUTEN PDMA_TOUTEN PDMA Time-out Enable Register 0x434 read-write n 0x0 0x0 TOUTEN0 PDMA Channel N Time-out Enable Bit 0 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTEN1 PDMA Channel N Time-out Enable Bit 1 1 read-write 0 PDMA Channel n time-out function Disabled #0 1 PDMA Channel n time-out function Enabled #1 TOUTIEN PDMA_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 read-write n 0x0 0x0 TOUTIEN0 PDMA Channel N Time-out Interrupt Enable Bit 0 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTIEN1 PDMA Channel N Time-out Interrupt Enable Bit 1 1 read-write 0 PDMA Channel n time-out interrupt Disabled #0 1 PDMA Channel n time-out interrupt Enabled #1 TOUTPSC PDMA_TOUTPSC PDMA Time-out Prescaler Register 0x430 read-write n 0x0 0x0 TOUTPSC0 PDMA Channel 0 Time-out Clock Source Prescaler Bits 0 3 read-write 0 PDMA channel 0 time-out clock source is HCLK/28 #000 1 PDMA channel 0 time-out clock source is HCLK/29 #001 2 PDMA channel 0 time-out clock source is HCLK/210 #010 3 PDMA channel 0 time-out clock source is HCLK/211 #011 4 PDMA channel 0 time-out clock source is HCLK/212 #100 5 PDMA channel 0 time-out clock source is HCLK/213 #101 6 PDMA channel 0 time-out clock source is HCLK/214 #110 7 PDMA channel 0 time-out clock source is HCLK/215 #111 TOUTPSC1 PDMA Channel 1 Time-out Clock Source Prescaler Bits 4 3 read-write 0 PDMA channel 1 time-out clock source is HCLK/28 #000 1 PDMA channel 1 time-out clock source is HCLK/29 #001 2 PDMA channel 1 time-out clock source is HCLK/210 #010 3 PDMA channel 1 time-out clock source is HCLK/211 #011 4 PDMA channel 1 time-out clock source is HCLK/212 #100 5 PDMA channel 1 time-out clock source is HCLK/213 #101 6 PDMA channel 1 time-out clock source is HCLK/214 #110 7 PDMA channel 1 time-out clock source is HCLK/215 #111 TRGSTS PDMA_TRGSTS PDMA Channel Request Status Register 0x40C read-only n 0x0 0x0 REQSTS0 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 0 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS1 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 1 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS2 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 2 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS3 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 3 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 REQSTS4 PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer. 4 1 read-only 0 PDMA Channel n has no request #0 1 PDMA Channel n has a request #1 PWM0 PWM Register Map PWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x4C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x44 registers n 0xF8 0x14 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC enable bit 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC enable bit 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC enable bit 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC enable bit 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count compared point #0011 4 PWM_CH0 down-count compared point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count compared point #1000 9 PWM_CH1 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL1 PWM_CH1 Trigger ADC Source Select 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count compared point #0011 4 PWM_CH0 down-count compared point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count compared point #1000 9 PWM_CH1 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL2 PWM_CH2 Trigger ADC Source Select 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count compared point #0011 4 PWM_CH2 down-count compared point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count compared point #1000 9 PWM_CH3 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL3 PWM_CH3 Trigger ADC Source Select 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count compared point #0011 4 PWM_CH2 down-count compared point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count compared point #1000 9 PWM_CH3 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC enable bit 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC enable bit 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count compared point #0011 4 PWM_CH4 down-count compared point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count compared point #1000 9 PWM_CH5 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL5 PWM_CH5 Trigger ADC Source Select 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count compared point #0011 4 PWM_CH4 down-count compared point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count compared point #1000 9 PWM_CH5 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 4 3 read-write BRK0NFEN PWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 Brake pin event will be detected if PWM0_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWM0_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN PWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 Brake pin event will be detected if PWM1_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWM1_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0/1 0xC8 read-write n 0x0 0x0 ADCEBEN Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 ADCRM as edge-detect brake source Disabled #0 1 ADCRM as edge-detect brake source Enabled #1 ADCLBEN Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 ADCRM as level-detect brake source Disabled #0 1 ADCRM as level-detect brake source Enabled #1 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWMx brake event will not affect even channels output #00 1 PWM even channel output tri-state when PWMx brake event happened #01 2 PWM even channel output low level when PWMx brake event happened #10 3 PWM even channel output high level when PWMx brake event happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWMx brake event will not affect odd channels output #00 1 PWM odd channel output tri-state when PWMx brake event happened #01 2 PWM odd channel output low level when PWMx brake event happened #10 3 PWM odd channel output high level when PWMx brake event happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2/3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4/5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN1 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN2 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN3 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN4 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN5 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPINV0 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIEN0 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIF0 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 5 1 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0/1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2/3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4/5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWMx_CH0/1 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 ECLKSRC2 PWMx_CH2/3 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 ECLKSRC4 PWMx_CH4/5 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 registers denote as first compared point, and CMPDAT1, 3, 5 register denote as second compared point for the corresponding 3 complementary pairs PWMx_CH0 and PWMx_CH1, PWMx_CH2 and PWMx_CH3, PWMx_CH4 and PWMx_CH5 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT1 PWM_CNT1 PWM Counter Register 1 0x94 read-write n 0x0 0x0 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT3 PWM_CNT3 PWM Counter Register 3 0x9C read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNT5 PWM_CNT5 PWM Counter Register 5 0xA4 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR1 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR2 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR3 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR4 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR5 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN1 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN3 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN5 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CPSCBUF0_1 PWM_CPSCBUF0_1 PWM CLKPSC0_1 Buffer 0x334 read-only n 0x0 0x0 CPSCBUF PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register. 0 12 read-only PWM_CPSCBUF2_3 PWM_CPSCBUF2_3 PWM CLKPSC2_3 Buffer 0x338 read-write n 0x0 0x0 PWM_CPSCBUF4_5 PWM_CPSCBUF4_5 PWM CLKPSC4_5 Buffer 0x33C read-write n 0x0 0x0 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each PWM channel are independent #0 1 Unify the PWMx_CH2 and PWMx_CH4 to output the same waveform as PWMx_CH0 and unify the PWMx_CH3 and PWMx_CH5 to output the same waveform as PWMx_CH1 #1 IMMLDEN0 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 16 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN1 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 17 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN2 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 18 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN3 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 19 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN4 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 20 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN5 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 21 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 WINLDEN0 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 11 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 12 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 13 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODE0 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE1 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE2 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE3 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE4 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE5 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 OUTMODE0 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 OUTMODE2 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 OUTMODE4 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0/1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from PWMx_CLK without counter clock prescale #0 1 Dead-time clock source from prescaler output with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM Pair (PWMx_CH0, PWMx_CH1) (PWMx_CH2, PWMx_CH3) (PWMx_CH4, PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2/3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4/5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup event Disabled #0 1 Brake Function triggered by Core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_FTCBUF0_1 PWM_FTCBUF0_1 PWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only PWM_FTCBUF2_3 PWM_FTCBUF2_3 PWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 PWM_FTCBUF4_5 PWM_FTCBUF4_5 PWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 PWM_FTCI PWM_FTCI PWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMD0 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 8 1 read-write FTCMD2 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 9 1 read-write FTCMD4 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 10 1 read-write FTCMU0 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 0 1 read-write FTCMU2 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 1 1 read-write FTCMU4 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 2 1 read-write PWM_FTCMPDAT0_1 PWM_FTCMPDAT0_1 PWM Free Trigger Compare Register 0/1 0x100 read-write n 0x0 0x0 FTCMP PWM Free Trigger Compare Register 0 16 read-write PWM_FTCMPDAT2_3 PWM_FTCMPDAT2_3 PWM Free Trigger Compare Register 2/3 0x104 read-write n 0x0 0x0 PWM_FTCMPDAT4_5 PWM_FTCMPDAT4_5 PWM Free Trigger Compare Register 4/5 0x108 read-write n 0x0 0x0 PWM_IFA PWM_IFA PWM Interrupt Flag Accumulator Register 0xF0 read-write n 0x0 0x0 IFAEN0_1 PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit 7 1 read-write 0 PWM Channel 0/1 interrupt flag accumulator Disabled #0 1 PWM Channel 0/1 interrupt flag accumulator Enabled #1 IFAEN2_3 PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit 15 1 read-write 0 PWM Channel 2/3 interrupt flag accumulator Disabled #0 1 PWM Channel 2/3 interrupt flag accumulator Enabled #1 IFAEN4_5 PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit 23 1 read-write 0 PWM Channel 4/5 interrupt flag accumulator Disabled #0 1 PWM Channel 4/5 interrupt flag accumulator Enabled #1 IFCNT0_1 PWM Channel 0/1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT0_1 [3:0] times of PWM period 0 4 read-write IFCNT2_3 PWM Channel 2/3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT2_3[3:0] times of PWM period. 8 4 read-write IFCNT4_5 PWM Channel 4/5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT4_5[3:0] times of PWM period. 16 4 read-write IFSEL0_1 PWM Channel 0/1 Interrupt Flag Accumulator Source Select 4 3 read-write 0 CNT equal to Zero in channel 0 #000 1 CNT equal to PERIOD in channel 0 #001 2 CNT equal to CMPU in channel 0 #010 3 CNT equal to CMPD in channel 0 #011 4 CNT equal to Zero in channel 1 #100 5 CNT equal to PERIOD in channel 1 #101 6 CNT equal to CMPU in channel 1 #110 7 CNT equal to CMPD in channel 1 #111 IFSEL2_3 PWM Channel 2/3 Interrupt Flag Accumulator Source Select 12 3 read-write 0 CNT equal to Zero in channel 2 #000 1 CNT equal to PERIOD in channel 2 #001 2 CNT equal to CMPU in channel 2 #010 3 CNT equal to CMPD in channel 2 #011 4 CNT equal to Zero in channel 3 #100 5 CNT equal to PERIOD in channel 3 #101 6 CNT equal to CMPU in channel 3 #110 7 CNT equal to CMPD in channel 3 #111 IFSEL4_5 PWM Channel 4/5 Interrupt Flag Accumulator Source Select 20 3 read-write 0 CNT equal to Zero in channel 4 #000 1 CNT equal to PERIOD in channel 4 #001 2 CNT equal to CMPU in channel 4 #010 3 CNT equal to CMPD in channel 4 #011 4 CNT equal to Zero in channel 5 #100 5 CNT equal to PERIOD in channel 5 #101 6 CNT equal to CMPU in channel 5 #110 7 CNT equal to CMPD in channel 5 #111 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIEN0 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 IFAIEN0_1 PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit 7 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2_3 PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit 15 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4_5 PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit 23 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 PIEN0 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIF0 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 24 1 read-write CMPDIF1 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 25 1 read-write CMPDIF2 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 26 1 read-write CMPDIF3 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 27 1 read-write CMPDIF4 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 28 1 read-write CMPDIF5 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 29 1 read-write CMPUIF0 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 16 1 read-write CMPUIF1 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 17 1 read-write CMPUIF2 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 18 1 read-write CMPUIF3 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 19 1 read-write CMPUIF4 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 20 1 read-write CMPUIF5 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 21 1 read-write IFAIF0_1 PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 7 1 read-write IFAIF2_3 PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 15 1 read-write IFAIF4_5 PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 23 1 read-write PIF0 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 8 1 read-write PIF1 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 9 1 read-write PIF2 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 10 1 read-write PIF3 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 11 1 read-write PIF4 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 12 1 read-write PIF5 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 13 1 read-write ZIF0 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF1 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 1 1 read-write ZIF2 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF3 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 3 1 read-write ZIF4 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write ZIF5 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 5 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel N Edge-detect Brake Status 16 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel N Edge-detect Brake Status 17 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel N Edge-detect Brake Status 18 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel N Edge-detect Brake Status 19 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel N Edge-detect Brake Status 20 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel N Edge-detect Brake Status 21 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKLIFn PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS1 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS2 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS3 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS4 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS5 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 PWM_LEBCNT PWM_LEBCNT PWM Leading Edge Blanking Counter Register 0x11C read-write n 0x0 0x0 LEBCNT PWM Leading Edge Blanking Counter\nThis counter value decides leading edge blanking window size. 0 9 read-write PWM_LEBCTL PWM_LEBCTL PWM Leading Edge Blanking Control Register 0x118 read-write n 0x0 0x0 LEBEN PWM Leading Edge Blanking Enable Bit 0 1 read-write 0 PWM Leading Edge Blanking Disabled #0 1 PWM Leading Edge Blanking Enabled #1 SRCEN0 PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit 8 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH0 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH0 Enabled #1 SRCEN2 PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit 9 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH2 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH2 Enabled #1 SRCEN4 PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit 10 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH4 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH4 Enabled #1 TRGTYPE PWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting #00 1 When detect leading edge blanking source falling edge, blanking counter start counting #01 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting #10 3 Reserved. #11 PWM_LOAD PWM_LOAD PWM Load Register 0x28 read-write n 0x0 0x0 LOAD0 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 0 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD1 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 1 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD2 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 2 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD3 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 3 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD4 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 4 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD5 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 5 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT1 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT2 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT3 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT4 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT5 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN1 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN2 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN3 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN4 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN5 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF1 PWM_PBUF1 PWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF3 PWM_PBUF3 PWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PBUF5 PWM_PBUF5 PWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 0/1 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 2/3 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 4/5 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT0/1 register #01 2 PWM_FCAPDAT0/1 register #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 registers #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT2/3 register #01 2 PWM_FCAPDAT2/3 register #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 registers #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT4/5 register #01 2 PWM_FCAPDAT4/5 register #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 registers #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3. 3 1 read-write 0 PWM_FCAPDAT0/1 register is the first captured data to memory #0 1 PWM_RCAPDAT0/1 register is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3. 11 1 read-write 0 PWM_FCAPDAT2/3 register is the first captured data to memory #0 1 PWM_RCAPDAT2/3 register is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3. 19 1 read-write 0 PWM_FCAPDAT4/5 register is the first captured data to memory #0 1 PWM_RCAPDAT4/5 register is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: \nIn this mode, PWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write PWM_PERIOD1 PWM_PERIOD1 PWM Period Register 1 0x34 read-write n 0x0 0x0 PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD3 PWM_PERIOD3 PWM Period Register 3 0x3C read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_PERIOD5 PWM_PERIOD5 PWM Period Register 5 0x44 read-write n 0x0 0x0 PWM_PHS0_1 PWM_PHS0_1 PWM Counter Phase Register 0/1 0x80 read-write n 0x0 0x0 PHS PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write PWM_PHS2_3 PWM_PHS2_3 PWM Counter Phase Register 2/3 0x84 read-write n 0x0 0x0 PWM_PHS4_5 PWM_PHS4_5 PWM Counter Phase Register 4/5 0x88 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN1 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN2 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN3 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN4 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN5 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV1 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV2 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV3 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV4 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV5 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN1 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN3 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN5 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select Bit 8 1 read-write 0 Synchronous start source come from PWM0 #0 1 Synchronous start source come from PWM1 #1 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGF0 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF1 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF2 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF3 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF4 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF5 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 SYNCINF0 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 SYNCINF2 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 SYNCINF4 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRG0 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 write-only BRKETRG2 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 write-only BRKETRG4 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 write-only BRKLTRG0 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 write-only PWM_SWSYNC PWM_SWSYNC PWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNC0 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 2 1 read-write PWM_SYNC PWM_SYNC PWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIR0 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 24 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSDIR2 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 25 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSDIR4 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 26 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 0 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 PHSEN2 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 1 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 PHSEN4 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 2 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of PWM0_SYNC_IN pin is passed to the negative edge detector #0 1 The inversed state of PWM0_SYNC_IN pin is passed to the negative edge detector #1 SINSRC0 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SINSRC2 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SINSRC4 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SNFLTEN PWM0_SYNC_IN Noise Filter Enable Bit 16 1 read-write 0 Noise filter of input PWM0_SYNC_IN pin Disabled #0 1 Noise filter of input PWM0_SYNC_IN pin Enabled #1 PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL1 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL2 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL3 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL4 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL5 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 ZPCTL0 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 0 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL1 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 2 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL2 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 4 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL3 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 6 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL4 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 8 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL5 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 10 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL1 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL2 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL3 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL4 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL5 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPUCTL0 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL1 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL2 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL3 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL4 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL5 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 PWM1 PWM Register Map PWM 0x0 0x0 0x2C registers n 0x110 0x14 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x4C registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x44 registers n 0xF8 0x14 registers n PWM_ADCTS0 PWM_ADCTS0 PWM Trigger ADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger ADC enable bit 7 1 read-write TRGEN1 PWM_CH1 Trigger ADC enable bit 15 1 read-write TRGEN2 PWM_CH2 Trigger ADC enable bit 23 1 read-write TRGEN3 PWM_CH3 Trigger ADC enable bit 31 1 read-write TRGSEL0 PWM_CH0 Trigger ADC Source Select 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count compared point #0011 4 PWM_CH0 down-count compared point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count compared point #1000 9 PWM_CH1 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL1 PWM_CH1 Trigger ADC Source Select 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count compared point #0011 4 PWM_CH0 down-count compared point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count compared point #1000 9 PWM_CH1 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL2 PWM_CH2 Trigger ADC Source Select 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count compared point #0011 4 PWM_CH2 down-count compared point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count compared point #1000 9 PWM_CH3 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL3 PWM_CH3 Trigger ADC Source Select 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count compared point #0011 4 PWM_CH2 down-count compared point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count compared point #1000 9 PWM_CH3 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 PWM_ADCTS1 PWM_ADCTS1 PWM Trigger ADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger ADC enable bit 7 1 read-write TRGEN5 PWM_CH5 Trigger ADC enable bit 15 1 read-write TRGSEL4 PWM_CH4 Trigger ADC Source Select 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count compared point #0011 4 PWM_CH4 down-count compared point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count compared point #1000 9 PWM_CH5 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 TRGSEL5 PWM_CH5 Trigger ADC Source Select 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count compared point #0011 4 PWM_CH4 down-count compared point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count compared point #1000 9 PWM_CH5 down-count compared point #1001 10 PWM_CH0 up-count free trigger compared point #1010 11 PWM_CH0 down-count free trigger compared point #1011 12 PWM_CH2 up-count free trigger compared point #1100 13 PWM_CH2 down-count free trigger compared point #1101 14 PWM_CH4 up-count free trigger compared point #1110 15 PWM_CH4 down-count free trigger compared point #1111 PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0 #0 1 Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 4 3 read-write BRK0NFEN PWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 Brake pin event will be detected if PWM0_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWM0_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN PWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 Brake pin event will be detected if PWM1_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if PWM1_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0/1 0xC8 read-write n 0x0 0x0 ADCEBEN Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 20 1 read-write 0 ADCRM as edge-detect brake source Disabled #0 1 ADCRM as edge-detect brake source Enabled #1 ADCLBEN Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 28 1 read-write 0 ADCRM as level-detect brake source Disabled #0 1 ADCRM as level-detect brake source Enabled #1 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWMx brake event will not affect even channels output #00 1 PWM even channel output tri-state when PWMx brake event happened #01 2 PWM even channel output low level when PWMx brake event happened #10 3 PWM even channel output high level when PWMx brake event happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWMx brake event will not affect odd channels output #00 1 PWM odd channel output tri-state when PWMx brake event happened #01 2 PWM odd channel output low level when PWMx brake event happened #10 3 PWM odd channel output high level when PWMx brake event happened #11 BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWMx_BRAKE0 pin as edge-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as edge-detect brake source Enabled #1 BRKP0LEN Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWMx_BRAKE1 pin as edge-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as edge-detect brake source Enabled #1 BRKP1LEN Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 CPO0EBEN Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 ACMP0_O as edge-detect brake source Disabled #0 1 ACMP0_O as edge-detect brake source Enabled #1 CPO0LBEN Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 ACMP0_O as level-detect brake source Disabled #0 1 ACMP0_O as level-detect brake source Enabled #1 CPO1EBEN Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 ACMP1_O as edge-detect brake source Disabled #0 1 ACMP1_O as edge-detect brake source Enabled #1 CPO1LBEN Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 ACMP1_O as level-detect brake source Disabled #0 1 ACMP1_O as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2/3 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4/5 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPEN0 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN1 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN2 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN3 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN4 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPEN5 Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated #0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers #1 CAPINV0 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV1 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV2 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV3 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 11 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV4 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 12 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 CAPINV5 Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 13 1 read-write 0 Capture source inverter Disabled #0 1 Capture source inverter Enabled. Reverse the input signal from GPIO #1 FCRLDEN0 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 24 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN1 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 25 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN2 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 26 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN3 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 27 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN4 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 28 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 FCRLDEN5 Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 29 1 read-write 0 Falling capture reload counter Disabled #0 1 Falling capture reload counter Enabled #1 RCRLDEN0 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN1 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN2 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN3 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN4 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 RCRLDEN5 Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Rising capture reload counter Disabled #0 1 Rising capture reload counter Enabled #1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIEN0 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 8 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN1 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 9 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN2 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 10 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN3 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 11 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN4 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 12 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPFIEN5 PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled. 13 1 read-write 0 Capture falling edge latch interrupt Disabled #0 1 Capture falling edge latch interrupt Enabled #1 CAPRIEN0 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 0 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN1 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 1 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN2 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 2 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN3 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 3 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN4 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 4 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 CAPRIEN5 PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled. 5 1 read-write 0 Capture rising edge latch interrupt Disabled #0 1 Capture rising edge latch interrupt Enabled #1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIF0 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 8 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF1 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 9 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF2 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 10 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF3 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 11 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF4 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 12 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CFLIF5 PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data. 13 1 read-write 0 No capture falling latch condition happened #0 1 Capture falling latch condition happened, this flag will be set to high #1 CRLIF0 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 0 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF1 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 1 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF2 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 2 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF3 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 3 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF4 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 4 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 CRLIF5 PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data. 5 1 read-write 0 No capture rising latch condition happened #0 1 Capture rising latch condition happened, this flag will be set to high #1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINEN0 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN1 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN2 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN3 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN4 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 CAPINEN5 Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 #0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin #1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOV0 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 8 1 read-only CFLIFOV1 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 9 1 read-only CFLIFOV2 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 10 1 read-only CFLIFOV3 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 11 1 read-only CFLIFOV4 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 12 1 read-only CFLIFOV5 Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit. 13 1 read-only CRLIFOV0 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 0 1 read-only CRLIFOV1 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 1 1 read-only CRLIFOV2 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 2 1 read-only CRLIFOV3 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 3 1 read-only CRLIFOV4 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 4 1 read-only CRLIFOV5 Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit. 5 1 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0/1 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2/3 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4/5 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWMx_CH0/1 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 ECLKSRC2 PWMx_CH2/3 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 ECLKSRC4 PWMx_CH4/5 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 time-out event #001 2 TIMER1 time-out event #010 3 TIMER2 time-out event #011 4 TIMER3 time-out event #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 registers denote as first compared point, and CMPDAT1, 3, 5 register denote as second compared point for the corresponding 3 complementary pairs PWMx_CH0 and PWMx_CH1, PWMx_CH2 and PWMx_CH3, PWMx_CH4 and PWMx_CH5 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT1 PWM_CNT1 PWM Counter Register 1 0x94 read-write n 0x0 0x0 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT3 PWM_CNT3 PWM Counter Register 3 0x9C read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNT5 PWM_CNT5 PWM Counter Register 5 0xA4 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLR0 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR1 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR2 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR3 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR4 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 CNTCLR5 Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0])) #1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTEN0 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN1 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN2 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN3 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN4 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 CNTEN5 PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM Counter and clock prescaler Stop Running #0 1 PWM Counter and clock prescaler Start Running #1 PWM_CPSCBUF0_1 PWM_CPSCBUF0_1 PWM CLKPSC0_1 Buffer 0x334 read-only n 0x0 0x0 CPSCBUF PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register. 0 12 read-only PWM_CPSCBUF2_3 PWM_CPSCBUF2_3 PWM CLKPSC2_3 Buffer 0x338 read-write n 0x0 0x0 PWM_CPSCBUF4_5 PWM_CPSCBUF4_5 PWM CLKPSC4_5 Buffer 0x33C read-write n 0x0 0x0 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLD0 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 0 1 read-write CTRLD1 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 1 1 read-write CTRLD2 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 2 1 read-write CTRLD3 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 3 1 read-write CTRLD4 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 4 1 read-write CTRLD5 Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period. 5 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each PWM channel are independent #0 1 Unify the PWMx_CH2 and PWMx_CH4 to output the same waveform as PWMx_CH0 and unify the PWMx_CH3 and PWMx_CH5 to output the same waveform as PWMx_CH1 #1 IMMLDEN0 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 16 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN1 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 17 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN2 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 18 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN3 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 19 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN4 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 20 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 IMMLDEN5 Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid. 21 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register #1 WINLDEN0 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN1 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN2 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN3 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 11 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN4 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 12 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 WINLDEN5 Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n. 13 1 read-write 0 PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit #0 1 PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success #1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODE0 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE1 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE2 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE3 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE4 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTMODE5 PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE0 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 0 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE1 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 2 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE2 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 4 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE3 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 6 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE4 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 8 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 CNTTYPE5 PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 10 2 read-write 0 Up counter type (supported in capture mode) #00 1 Down count type (supported in capture mode) #01 2 Up-down counter type #10 3 Reserved. #11 OUTMODE0 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 OUTMODE2 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 25 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 OUTMODE4 PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 26 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0/1 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from PWMx_CLK without counter clock prescale #0 1 Dead-time clock source from prescaler output with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWM Pair (PWMx_CH0, PWMx_CH1) (PWMx_CH2, PWMx_CH3) (PWMx_CH4, PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2/3 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4/5 0x78 read-write n 0x0 0x0 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup event Disabled #0 1 Brake Function triggered by Core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_FTCBUF0_1 PWM_FTCBUF0_1 PWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only PWM_FTCBUF2_3 PWM_FTCBUF2_3 PWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 PWM_FTCBUF4_5 PWM_FTCBUF4_5 PWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 PWM_FTCI PWM_FTCI PWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMD0 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 8 1 read-write FTCMD2 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 9 1 read-write FTCMD4 PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 10 1 read-write FTCMU0 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 0 1 read-write FTCMU2 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 1 1 read-write FTCMU4 PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n. 2 1 read-write PWM_FTCMPDAT0_1 PWM_FTCMPDAT0_1 PWM Free Trigger Compare Register 0/1 0x100 read-write n 0x0 0x0 FTCMP PWM Free Trigger Compare Register 0 16 read-write PWM_FTCMPDAT2_3 PWM_FTCMPDAT2_3 PWM Free Trigger Compare Register 2/3 0x104 read-write n 0x0 0x0 PWM_FTCMPDAT4_5 PWM_FTCMPDAT4_5 PWM Free Trigger Compare Register 4/5 0x108 read-write n 0x0 0x0 PWM_IFA PWM_IFA PWM Interrupt Flag Accumulator Register 0xF0 read-write n 0x0 0x0 IFAEN0_1 PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit 7 1 read-write 0 PWM Channel 0/1 interrupt flag accumulator Disabled #0 1 PWM Channel 0/1 interrupt flag accumulator Enabled #1 IFAEN2_3 PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit 15 1 read-write 0 PWM Channel 2/3 interrupt flag accumulator Disabled #0 1 PWM Channel 2/3 interrupt flag accumulator Enabled #1 IFAEN4_5 PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit 23 1 read-write 0 PWM Channel 4/5 interrupt flag accumulator Disabled #0 1 PWM Channel 4/5 interrupt flag accumulator Enabled #1 IFCNT0_1 PWM Channel 0/1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT0_1 [3:0] times of PWM period 0 4 read-write IFCNT2_3 PWM Channel 2/3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT2_3[3:0] times of PWM period. 8 4 read-write IFCNT4_5 PWM Channel 4/5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT4_5[3:0] times of PWM period. 16 4 read-write IFSEL0_1 PWM Channel 0/1 Interrupt Flag Accumulator Source Select 4 3 read-write 0 CNT equal to Zero in channel 0 #000 1 CNT equal to PERIOD in channel 0 #001 2 CNT equal to CMPU in channel 0 #010 3 CNT equal to CMPD in channel 0 #011 4 CNT equal to Zero in channel 1 #100 5 CNT equal to PERIOD in channel 1 #101 6 CNT equal to CMPU in channel 1 #110 7 CNT equal to CMPD in channel 1 #111 IFSEL2_3 PWM Channel 2/3 Interrupt Flag Accumulator Source Select 12 3 read-write 0 CNT equal to Zero in channel 2 #000 1 CNT equal to PERIOD in channel 2 #001 2 CNT equal to CMPU in channel 2 #010 3 CNT equal to CMPD in channel 2 #011 4 CNT equal to Zero in channel 3 #100 5 CNT equal to PERIOD in channel 3 #101 6 CNT equal to CMPU in channel 3 #110 7 CNT equal to CMPD in channel 3 #111 IFSEL4_5 PWM Channel 4/5 Interrupt Flag Accumulator Source Select 20 3 read-write 0 CNT equal to Zero in channel 4 #000 1 CNT equal to PERIOD in channel 4 #001 2 CNT equal to CMPU in channel 4 #010 3 CNT equal to CMPD in channel 4 #011 4 CNT equal to Zero in channel 5 #100 5 CNT equal to PERIOD in channel 5 #101 6 CNT equal to CMPU in channel 5 #110 7 CNT equal to CMPD in channel 5 #111 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIEN0 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 24 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN1 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 25 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN2 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 26 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN3 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 27 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN4 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 28 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPDIEN5 PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 29 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN0 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 16 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN1 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 17 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN2 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 18 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN3 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 19 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN4 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 20 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 CMPUIEN5 PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 21 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 IFAIEN0_1 PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit 7 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2_3 PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit 15 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4_5 PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit 23 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 PIEN0 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN1 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 9 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN2 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 10 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN3 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 11 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN4 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 12 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 PIEN5 PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 13 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN0 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN1 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 1 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN2 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 2 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN3 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 3 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN4 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 4 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 ZIEN5 PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 5 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIF0 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 24 1 read-write CMPDIF1 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 25 1 read-write CMPDIF2 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 26 1 read-write CMPDIF3 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 27 1 read-write CMPDIF4 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 28 1 read-write CMPDIF5 PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 29 1 read-write CMPUIF0 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 16 1 read-write CMPUIF1 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 17 1 read-write CMPUIF2 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 18 1 read-write CMPUIF3 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 19 1 read-write CMPUIF4 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 20 1 read-write CMPUIF5 PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 21 1 read-write IFAIF0_1 PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 7 1 read-write IFAIF2_3 PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 15 1 read-write IFAIF4_5 PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register, software can clear this bit by writing 1 to it. 23 1 read-write PIF0 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 8 1 read-write PIF1 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 9 1 read-write PIF2 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 10 1 read-write PIF3 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 11 1 read-write PIF4 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 12 1 read-write PIF5 PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n. 13 1 read-write ZIF0 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 0 1 read-write ZIF1 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 1 1 read-write ZIF2 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 2 1 read-write ZIF3 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 3 1 read-write ZIF4 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 4 1 read-write ZIF5 PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero. 5 1 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel n edge-detect brake event do not happened #0 1 When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel N Edge-detect Brake Status 16 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS1 PWM Channel N Edge-detect Brake Status 17 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS2 PWM Channel N Edge-detect Brake Status 18 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS3 PWM Channel N Edge-detect Brake Status 19 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS4 PWM Channel N Edge-detect Brake Status 20 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKESTS5 PWM Channel N Edge-detect Brake Status 21 1 read-write 0 PWM channel n edge-detect brake state is released #0 1 When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear #1 BRKLIFn PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel n level-detect brake event do not happened #0 1 When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS1 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS2 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS3 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS4 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 BRKLSTS5 PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel n level-detect brake state is released #0 1 When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state #1 PWM_LEBCNT PWM_LEBCNT PWM Leading Edge Blanking Counter Register 0x11C read-write n 0x0 0x0 LEBCNT PWM Leading Edge Blanking Counter\nThis counter value decides leading edge blanking window size. 0 9 read-write PWM_LEBCTL PWM_LEBCTL PWM Leading Edge Blanking Control Register 0x118 read-write n 0x0 0x0 LEBEN PWM Leading Edge Blanking Enable Bit 0 1 read-write 0 PWM Leading Edge Blanking Disabled #0 1 PWM Leading Edge Blanking Enabled #1 SRCEN0 PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit 8 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH0 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH0 Enabled #1 SRCEN2 PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit 9 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH2 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH2 Enabled #1 SRCEN4 PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit 10 1 read-write 0 PWM Leading Edge Blanking Source from PWMx_CH4 Disabled #0 1 PWM Leading Edge Blanking Source from PWMx_CH4 Enabled #1 TRGTYPE PWM Leading Edge Blanking Trigger Type 16 2 read-write 0 When detect leading edge blanking source rising edge, blanking counter start counting #00 1 When detect leading edge blanking source falling edge, blanking counter start counting #01 2 When detect leading edge blanking source rising or falling edge, blanking counter start counting #10 3 Reserved. #11 PWM_LOAD PWM_LOAD PWM Load Register 0x28 read-write n 0x0 0x0 LOAD0 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 0 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD1 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 1 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD2 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 2 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD3 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 3 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD4 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 4 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 LOAD5 Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 5 1 read-write 0 No effect.\nNo load window is set #0 1 Set load window of window loading mode.\nLoad window is set #1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDAT0 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT1 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT2 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT3 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT4 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 MSKDAT5 PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 Output logic low to PWMx_CHn #0 1 Output logic high to PWMx_CHn #1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKEN0 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN1 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN2 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN3 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN4 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 MSKEN5 PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM output signal is non-masked #0 1 PWM output signal is masked and output MSKDATn data #1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF1 PWM_PBUF1 PWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF3 PWM_PBUF3 PWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PBUF5 PWM_PBUF5 PWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 0/1 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 2/3 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 4/5 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT0/1 register #01 2 PWM_FCAPDAT0/1 register #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 registers #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT2/3 register #01 2 PWM_FCAPDAT2/3 register #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 registers #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT4/5 register #01 2 PWM_FCAPDAT4/5 register #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 registers #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3. 3 1 read-write 0 PWM_FCAPDAT0/1 register is the first captured data to memory #0 1 PWM_RCAPDAT0/1 register is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3. 11 1 read-write 0 PWM_FCAPDAT2/3 register is the first captured data to memory #0 1 PWM_RCAPDAT2/3 register is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3. 19 1 read-write 0 PWM_FCAPDAT4/5 register is the first captured data to memory #0 1 PWM_RCAPDAT4/5 register is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: \nIn this mode, PWM counter counts from 0 to PERIOD, and restarts from 0. 0 16 read-write PWM_PERIOD1 PWM_PERIOD1 PWM Period Register 1 0x34 read-write n 0x0 0x0 PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD3 PWM_PERIOD3 PWM Period Register 3 0x3C read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_PERIOD5 PWM_PERIOD5 PWM Period Register 5 0x44 read-write n 0x0 0x0 PWM_PHS0_1 PWM_PHS0_1 PWM Counter Phase Register 0/1 0x80 read-write n 0x0 0x0 PHS PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write PWM_PHS2_3 PWM_PHS2_3 PWM Counter Phase Register 2/3 0x84 read-write n 0x0 0x0 PWM_PHS4_5 PWM_PHS4_5 PWM Counter Phase Register 4/5 0x88 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POEN0 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN1 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN2 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN3 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN4 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 POEN5 PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWMx_CHn pin at tri-state #0 1 PWMx_CHn pin in output mode #1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINV0 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV1 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV2 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV3 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV4 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PINV5 PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWMx_CHn output pin polar inverse Disabled #0 1 PWMx_CHn output pin polar inverse Enabled #1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSEN0 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 0 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN1 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 1 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN2 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 2 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN3 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 3 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN4 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 4 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSEN5 PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 5 1 read-write 0 PWM synchronous start function Disabled #0 1 PWM synchronous start function Enabled #1 SSRC PWM Synchronous Start Source Select Bit 8 1 read-write 0 Synchronous start source come from PWM0 #0 1 Synchronous start source come from PWM1 #1 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGF0 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 16 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF1 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 17 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF2 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 18 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF3 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 19 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF4 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 20 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 ADCTRGF5 ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n. 21 1 read-write 0 Indicates no ADC start of conversion trigger event has occurred #0 1 Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit #1 CNTMAXF0 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 0 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF1 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 1 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF2 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 2 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF3 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 3 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF4 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 4 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 CNTMAXF5 Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n. 5 1 read-write 0 indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF #0 1 indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit #1 SYNCINF0 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 8 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 SYNCINF2 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 9 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 SYNCINF4 Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 10 1 read-write 0 Indicates no SYNC_IN event has occurred #0 1 Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit #1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRG0 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 0 1 write-only BRKETRG2 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 1 1 write-only BRKETRG4 PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register. 2 1 write-only BRKLTRG0 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 write-only BRKLTRG2 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 write-only BRKLTRG4 PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 write-only PWM_SWSYNC PWM_SWSYNC PWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNC0 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 0 1 read-write SWSYNC2 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 1 1 read-write SWSYNC4 Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 2 1 read-write PWM_SYNC PWM_SYNC PWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIR0 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 24 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSDIR2 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 25 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSDIR4 PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 26 1 read-write 0 Control PWM counter count decrement after synchronizing #0 1 Control PWM counter count increment after synchronizing #1 PHSEN0 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 0 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 PHSEN2 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 1 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 PHSEN4 SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5. 2 1 read-write 0 PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits #0 1 PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits #1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of PWM0_SYNC_IN pin is passed to the negative edge detector #0 1 The inversed state of PWM0_SYNC_IN pin is passed to the negative edge detector #1 SINSRC0 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 8 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SINSRC2 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 10 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SINSRC4 PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 12 2 read-write 0 Synchronize source from SYNC_IN or SWSYNC #00 1 Counter equal to 0 #01 2 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 #10 3 SYNC_OUT signal will not be generated #11 SNFLTEN PWM0_SYNC_IN Noise Filter Enable Bit 16 1 read-write 0 Noise filter of input PWM0_SYNC_IN pin Disabled #0 1 Noise filter of input PWM0_SYNC_IN pin Enabled #1 PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTL0 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL1 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 18 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL2 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 20 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL3 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 22 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL4 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 24 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 PRDPCTL5 PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type. 26 2 read-write 0 Do nothing #00 1 PWM period (center) point output Low #01 2 PWM period (center) point output High #10 3 PWM period (center) point output Toggle #11 ZPCTL0 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 0 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL1 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 2 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL2 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 4 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL3 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 6 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL4 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 8 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 ZPCTL5 PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n. 10 2 read-write 0 Do nothing #00 1 PWM zero point output Low #01 2 PWM zero point output High #10 3 PWM zero point output Toggle #11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTL0 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 16 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL1 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 18 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL2 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 20 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL3 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 22 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL4 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 24 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPDCTL5 PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 26 2 read-write 0 Do nothing #00 1 PWM compare down point output Low #01 2 PWM compare down point output High #10 3 PWM compare down point output Toggle #11 CMPUCTL0 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 0 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL1 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 2 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL2 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 4 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL3 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 6 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL4 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 8 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 CMPUCTL5 PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 10 2 read-write 0 Do nothing #00 1 PWM compare up point output Low #01 2 PWM compare up point output High #10 3 PWM compare up point output Toggle #11 RTC RTC Register Map RTC 0x0 0x0 0x3C registers n 0x100 0x14 registers n CAL RTC_CAL RTC Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 DAY 1-Day Calendar Digit (0~9) 0 4 read-write MON 1-Month Calendar Digit (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit (0~3) 4 2 read-write TENMON 10-Month Calendar Digit (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit (0~9) 20 4 read-write YEAR 1-Year Calendar Digit (0~9) 16 4 read-write CALM RTC_CALM RTC Calendar Alarm Register 0x20 read-write n 0x0 0x0 DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write TENMON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CAMSK RTC_CAMSK RTC Calendar Alarm Mask Register 0x38 read-write n 0x0 0x0 MDAY Mask 1-Day Calendar Digit of alarm setting (0~9) 0 1 read-write MMON Mask 1-Month Calendar Digit of alarm setting (0~9) 2 1 read-write MTENDAY Mask 10-Day Calendar Digit of alarm setting (0~3) 1 1 read-write MTENMON Mask 10-Month Calendar Digit of alarm setting (0~1) 3 1 read-write MTENYEAR Mask 10-Year Calendar Digit of alarm setting (0~9) 5 1 read-write MYEAR Mask 1-Year Calendar Digit of alarm setting (0~9) 4 1 read-write CLKFMT RTC_CLKFMT RTC Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 _24HEN 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM register are in 24-hour time scale or 12-hour time scale 0 1 read-write 0 12-hour time scale with AM and PM indication selected #0 1 24-hour time scale selected #1 DSTCTL RTC_DSTCTL RTC Daylight Saving Time Control Register 0x110 read-write n 0x0 0x0 ADDHR Add 1 Hour 0 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been added one hour for summer time change #1 DSBAK Daylight Saving Back 2 1 read-write 0 Daylight Saving Time function is not performed #0 1 Daylight Saving Time function is performed #1 SUBHR Subtract 1 Hour 1 1 read-write 0 No effect #0 1 Indicates RTC hour digit has been subtracted one hour for winter time change #1 FREQADJ RTC_FREQADJ RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FREQADJ Frequency Compensation Value\nUser has to get actual clock frequency of LXT, LXT frequency.\nNote: This formula is suitable only when RTCSEL (CLK_CLKSEL2[18]) is 0, RTC clock source is from LXT. 0 22 read-write INIT RTC_INIT RTC Initiation Register 0x0 read-write n 0x0 0x0 INIT RTC Initiation\nWhen RTC block is first powered on, RTC is at reset state. User has to write a special number 0xA5EB1357 to INIT to make RTC leaving reset state. Once the INIT is written as 0xA5EB1357 the RTC will be at normal active state permanently.\nThe INIT[31:1] is a write-only field and read value will be always 0. 1 31 read-write INIT_ACTIVE RTC Active Status (Read Only) 0 1 read-only 0 RTC is at reset state #0 1 RTC is at normal active state #1 INTEN RTC_INTEN RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable Bit 0 1 read-write 0 RTC alarm interrupt Disabled #0 1 RTC alarm interrupt Enabled #1 TICKIEN Time Tick Interrupt Enable Bit 1 1 read-write 0 RTC time tick interrupt Disabled #0 1 RTC time tick interrupt Enabled #1 INTSTS RTC_INTSTS RTC Interrupt Status Register 0x2C read-write n 0x0 0x0 ALMIF RTC Alarm Interrupt Flag\nWhen current RTC counter in RTC_TIME and RTC_CAL are matched RTC alarm settings in RTC_TALM and RTC_CALM, ALMIF will be set to 1 and an alarm interrupt signal will be generated if ALMIEN (RTC_INTEN[0]) is enabled. Chip will also be waken up when alarm interrupt signal occurred if chip is running at Power-down mode.\nNote: Writing 1 to clear this bit. 0 1 read-write 0 Alarm condition is not matched #0 1 Alarm condition is matched #1 TICKIF RTC Time Tick Interrupt Flag\nWhen RTC time tick event happened, TICKIF will be set to 1 and a time tick interrupt signal will be generated if TICKIEN (RTC_INTEN[1]) is enabled. Chip will also be waken up when time tick interrupt signal occurred if chip is running at Power-down mode.\nNote: Writing 1 to clear this bit. 1 1 read-write 0 Tick condition did not occur #0 1 Tick condition occurred #1 LEAPYEAR RTC_LEAPYEAR RTC Leap Year Indicaton Register 0x24 read-only n 0x0 0x0 LEAPYEAR Leap Year Indication Register (Read Only) 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 LXTCTL RTC_LXTCTL RTC 32 KHz Oscillator Control Register 0x100 -1 read-write n 0x0 0x0 GAIN Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption. 1 3 read-write 0 L0 mode #000 1 L1 mode #001 2 L2 mode #010 3 L3 mode #011 4 L4 mode #100 5 L5 mode #101 6 L6 mode #110 7 L7 mode (Default) #111 LXTICTL RTC_LXTICTL RTC X32KI Pin Control Register 0x108 read-write n 0x0 0x0 CTLSEL I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.1 function. User can program CTLSEL to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1. 3 1 read-write 0 X32KI (PF.1) pin I/O function is controlled by GPIO module #0 1 X32KI (PF.1) pin I/O function is controlled by OPMODE and DOUT in RTC_LXTICTL at VBAT power domain #1 DOUT IO Pin Output Data 2 1 read-write 0 X32KI (PF.1) will drive low in output mode #0 1 X32KI (PF.1) will drive high in output mode #1 OPMODE I/O Pin Operation Mode 0 2 read-write 0 X32KI (PF.1) is in Input mode without pull-up resistor #00 1 X32KI (PF.1) is in Push-pull output mode #01 2 X32KI (PF.1) is in Open-drain output mode #10 3 X32KI (PF.1) is in Input mode with pull-up resistor #11 LXTOCTL RTC_LXTOCTL RTC X32KO Pin Control Register 0x104 read-write n 0x0 0x0 CTLSEL I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.0 function. User can program CTLSEL to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1. 3 1 read-write 0 X32KO (PF.0) pin I/O function is controlled by GPIO module #0 1 X32KO (PF.0) pin I/O function is controlled by OPMODE and DOUT in RTC_LXTOCT at VBAT power domain #1 DOUT I/O Pin Output Data 2 1 read-write 0 X32KO (PF.0) will drive low in output mode #0 1 X32KO (PF.0) will drive high in output mode #1 OPMODE I/O Pin Operation Mode 0 2 read-write 0 X32KO (PF.0) is in Input mode without pull-up resistor #00 1 X32KO (PF.0) is in Push-pull output mode #01 2 X32KO (PF.0) is in Open-drain output mode #10 3 X32KO (PF.0) is in Input mode with pull-up resistor #11 PF2CTL RTC_PF2CTL RTC PF.2 Pin Control Register 0x10C read-write n 0x0 0x0 CTLSEL I/O Pin State Backup Selection\nUser can program CTLSEL to decide GPIO PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1. 3 1 read-write 0 GPIO PF.2 pin I/O function is controlled by GPIO module #0 1 GPIO PF.2 pin I/O function is controlled by OPMODE and DOUT in RTC_PF2CTL at VBAT power domain #1 DOUT I/O Pin Output Data 2 1 read-write 0 GPIO PF.2 will drive low in output mode #0 1 GPIO PF.2 will drive high in output mode #1 OPMODE I/O Pin Operation Mode 0 2 read-write 0 PF.2 is in Input mode without pull-up resistor #00 1 PF.2 is in Push-pull output mode #01 2 PF.2 is in Open-drain output mode #10 3 PF.2 is in Input mode with pull-up resistor #11 RWEN RTC_RWEN RTC Access Enable Register 0x4 read-write n 0x0 0x0 RTCBUSY RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not.\nNote: RTCBUSY falg will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles. 24 1 read-write 0 RTC register write Disabled #0 1 RTC register write Enabled #1 RWEN RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this field will enable RTC register access period and keep 1024 RTC clocks.\nNote: Writing others vaule will clear RWENF and disable RTC register access function immediately. 0 16 write-only RWENF RTC Register Access Enable Bit (Read Only) Note1: This bit will be set after RWEN is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired. Note2: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. 16 1 read-only 0 RTC register read/write Disabled #0 1 RTC register read/write Enabled #1 TALM RTC_TALM RTC Time Alarm Register 0x1C read-write n 0x0 0x0 HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TENHR 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write TENSEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write TAMSK RTC_TAMSK RTC Time Alarm Mask Register 0x34 read-write n 0x0 0x0 MHR Mask 1-hour Time Digit of Alarm Setting (0~9)\nNote: MHR function is only for 24-hour time scale mode. 4 1 read-write MMIN Mask 1-Min Time Digit of alarm setting (0~9) 2 1 read-write MSEC Mask 1-Sec Time Digit of alarm setting (0~9) 0 1 read-write MTENHR Mask 10-hour Time Digit of Alarm Setting (0~2)\nNote: MTENHR function is only for 24-hour time scale mode. 5 1 read-write MTENMIN Mask 10-Min Time Digit of alarm setting (0~5) 3 1 read-write MTENSEC Mask 10-Sec Time Digit of alarm setting (0~5) 1 1 read-write TICK RTC_TICK RTC Time Tick Register 0x30 read-write n 0x0 0x0 TICK Time Tick Register\nThese bits are used to select RTC time tick period for periodic time tick interrupt request. 0 3 read-write 0 Time tick is 1 second #000 1 Time tick is 1/2 second #001 2 Time tick is 1/4 second #010 3 Time tick is 1/8 second #011 4 Time tick is 1/16 second #100 5 Time tick is 1/32 second #101 6 Time tick is 1/64 second #110 7 Time tick is 1/128 second #111 TIME RTC_TIME RTC Time Loading Register 0xC read-write n 0x0 0x0 HR 1-Hour Time Digit (0~9) 16 4 read-write MIN 1-Min Time Digit (0~9) 8 4 read-write SEC 1-Sec Time Digit (0~9) 0 4 read-write TENHR 10-hour Time Digit (0~2)\nNote: When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication, RTC_TIME[21] is 0 means AM hour and RTC_TIME[21] is 1 means PM hour. 20 2 read-write TENMIN 10-Min Time Digit (0~5) 12 3 read-write TENSEC 10-Sec Time Digit (0~5) 4 3 read-write WEEKDAY RTC_WEEKDAY RTC Day of the Week Register 0x18 -1 read-write n 0x0 0x0 WEEKDAY Day of the Week Register \nNote: RTC will not check WEEKDAY setting with RTC_CAL is reasonable or not. 0 3 read-write 0 Sunday #000 1 Monday #001 2 Tuesday #010 3 Wednesday #011 4 Thursday #100 5 Friday #101 6 Saturday #110 7 Reserved. #111 SC0 SC Register Map SC 0x0 0x0 0x40 registers n 0x4C 0x4 registers n SC_ACTCTL SC_ACTCTL SC Activation Control Register 0x4C read-write n 0x0 0x0 T1EXT T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nPlease refer to SC activation sequence in Figure 6.154.\nThe cycle scaling factor is 2048 and \nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3. 0 5 read-write SC_ALTCTL SC_ALTCTL SC Alternate Control Register 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in ACTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SC_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SC_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SC_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nThis bit is usde for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SC_INTSTS[8]) also. 11 1 read-write 0 Auto deactivation Disabled #0 1 Auto deactivation Enabled #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stop counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stop counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stop counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in DACTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.154.\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.155.\nDeactivation: refer to Deactivation Sequence in Figure 6.156.\nNote: When setting activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function. 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST RX Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_ALTCTL register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_ALTCTL register #0 1 Last value is synchronizing #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and Tx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the Tx internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in WARSTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit\nThis bit is used to enable auto convention function.\nNote1: If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SC_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.\nNote2: If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SC_INTSTS[10]) and generate an interrupt signal to inform CPU when ACERRIEN (SC_INTEN[10]) is enabled. 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) SC modue clocks and de-bounce sample card removal once per 128 SC modue clocks #00 CDLV Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled. 26 1 read-write 0 When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin (SC_CD) from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN (SC_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved. #01 2 Reserved. #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Bit\nThis bit is used to disable Rx receive function.\nNote: If AUTOCEN (SC_CTL[3]) is enabled, this field is ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF (SC_INTSTS[0]) will be set. If RDAIEN (SC_INTEN[0]) is enabled, an interrupt signal will be generated to inform CPU. 6 2 read-write 0 Rx Buffer Trigger Level with 01 bytes #00 1 Rx Buffer Trigger Level with 02 bytes #01 2 Rx Buffer Trigger Level with 03 bytes #10 3 Reserved. #11 SCEN SC Controller Enable Bit\nSet this bit to 1 to enable SC operation function.\nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 0 1 read-write 0 SC will force all transition to IDLE state #0 1 SC controller is enabled and all function can work correctly #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 30 1 read-only 0 Synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Channel Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24-bit Timer0 and two 8-bit Timer0 and Timer1 are enabled. User can configure them by setting SC_TMRCTL0[23:0], SC_TMRCTL1[7:0] and SC_TMRCTL2[7:0] #11 TXOFF TX Transition Disable Bit\nThis bit is used to disable Tx transmit function. 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_DAT SC_DAT SC Receive/Transmit Holding Buffer Register 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.\nNote: If SCEN (SC_CTL[0]) is not enabled, DAT cannot be programmed. 0 8 read-write SC_EGT SC_EGT SC Extra Guard Time Register 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base. 0 8 read-write SC_ETUCTL SC_ETUCTL SC Element Time Unit Control Register 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field is used for define ETU time unit.\nThe real ETU time unit is (ETURDIV + 1) * SC clock time.\nNote: User can configure this field, but this field must be greater than 0x004. 0 12 read-write SC_INTEN SC_INTEN SC Interrupt Enable Control Register 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time. 6 1 read-write 0 Block guard time interrupt Disabled #0 1 Block guard time interrupt Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SC_STATUS[13]). \nNote: Either cared insert or card remove event will generate crad detect event. 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. 0 1 read-write 0 Received data bytes in Rx buffer reach trigger level interrupt Disabled #0 1 Received data bytes in Rx buffer reach trigger level interrupt Enabled #1 RXTOIEN Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error status is at SC_STATUS which includes receiver break error BEF (SC_STATUS[6]), frame error FEF (SC_STATUS[5]), parity error PEF (SC_STATUS[4]), receive buffer overflow error RXOV (SC_STATUS[0]), transmit buffer overflow error TXOV (SC_STATUS[8]), receiver retry over limit error RXOVERR (SC_STATUS[22]) or transmitter retry over limit error TXOVERR (SC_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 TXEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 SC_INTSTS SC_INTSTS SC Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it. 10 1 read-write 0 Received TS at ATR state is 0x3B or 0x3F #0 1 Received TS at ATR state is neither 0x3B nor 0x3F #1 BGTIF None 6 1 read-write 0 Block guard time interrupt did not occur #0 1 Block guard time interrupt occurred #1 CDIF Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag. The actual card detect status is in CINSERT (SC_STATUS[12]) and CREMOVE (SCn_STATUS[11]). Note1: This bit is read only, and will be cleared after CINSERT or CREMOVE status has been cleared. Note2: Either cared insert or card remove event will generate crad detect event. 7 1 read-only 0 Card detect event did not occur #0 1 Card detect event occurred #1 INITIF Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Initial sequence is not complete #0 1 Initial sequence is completed #1 RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from DAT (SC_DAT[7:0]) and remains receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 0 1 read-only 0 Number of receive buffer is less than RXTRGLV setting #0 1 Number of receive buffer data equals the RXTRGLV setting #1 RXTOIF Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading DAT (SC_DAT[7:0]) to clear it. 9 1 read-only 0 Receive buffer time-out interrupt did not occur #0 1 Receive buffer time-out interrupt occurred #1 TERRIF Transfer Error Interrupt Status Flag\nThis field is used for indicate transfer error interrupt status flag. The transfer error status is at SC_STATUS which includes receiver break error BEF (SC_STATUS[6]), frame error FEF (SC_STATUS[5]), parity error PEF (SC_STATUS[4]), receive buffer overflow error RXOV (SC_STATUS[0]), transmit buffer overflow error TXOV (SC_STATUS[8]), receiver retry over limit error RXOVERR (SC_STATUS[22]) or transmitter retry over limit error TXOVERR (SC_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it. 2 1 read-write 0 Transfer error interrupt did not occur #0 1 Transfer error interrupt occurred #1 TMR0IF Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 3 1 read-write 0 Timer0 interrupt did not occur #0 1 Timer0 interrupt occurred #1 TMR1IF Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 4 1 read-write 0 Timer1 interrupt did not occur #0 1 Timer1 interrupt occurred #1 TMR2IF Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 5 1 read-write 0 Timer2 interrupt did not occur #0 1 Timer2 interrupt occurred #1 TXEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit, user must write data to DAT (SC_DAT[7:0]) and then this bit will be cleared automatically. 1 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 SC_PINCTL SC_PINCTL SC Pin Control State Register 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATSTS SC_DATA Pin Status (Read Only) 16 1 read-only 0 The SC_DATA pin status is low #0 1 The SC_DATA pin status is high #1 PWREN SC_PWR Pin Signal\nUser can set PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0]) to decide SC_PWR pin is in high or low level.\nWrite this bit can drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. \nRead this bit to get SC_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes 0 1 read-write 0 SC_PWR signal status is low #0 1 SC_PWR signal status is high #1 PWRINV SC_PWR Pin Inverse\nThis bit is used for inverse the SC_PWR pin.\nThere are four kinds of combination for SC_PWR pin setting by PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0]). And all conditions as below list.\nNote: User must select PWRINV (SC_PINCTL[11]) before smart card is enabled by SCEN (SC_CTL[0]). 11 1 read-write PWRSTS SC_PWR Pin Status (Read Only)\nThis bit is the pin status of SC_PWR. 17 1 read-only 0 SC_PWR pin to low #0 1 SC_PWR pin to high #1 RSTSTS SC_RST Pin Status (Read Only)\nThis bit is the pin status of SC_RST. 18 1 read-only 0 SC_RST pin is low #0 1 SC_RST pin is high #1 SCDATA SC_DATA Pin Signal \nThis bit is the signal status of SC_DATA but user can also drive SC_DATA pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SC_DATA pin to low.\nSC_DATA signal status is low #0 1 Drive SC_DATA pin to high.\nSC_DATA signal status is high #1 SCRST SC_RST Pin Signal\nThis bit is the signal status of SC_RST but user can drive SC_RST pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST signal status is low #0 1 Drive SC_RST pin to high.\nSC_RST signal status is high #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SC_PINCTL register #0 1 Last value is synchronizing #1 SC_RXTOUT SC_RXTOUT SC Receive Buffer Time-out Counter Register 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the Rx buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading DAT (SC_DAT[7:0]), a receiver time-out flag RXTOIF (SC_INTSTS[9]) will be set, and hardware will generate an interrupt signal to inform CPU when RXTOIEN (SC_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is (RFTM + 0.5) ETU time.\nNote2: Filling in all 0 to this field will disable this function. 0 9 read-write SC_STATUS SC_STATUS SC Transfer Status Register 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits').\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 6 1 read-write 0 Receiver break error flag did not occur #0 1 Receiver break error flag occurred #1 CDPINSTS Card Detect Pin Status (Read Only)\nThis bit is the pin status of SC_CD. 13 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CINSERT Card Insert Status of SC_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: The card detect function will start after SCEN (SC_CTL[0]) is set. 12 1 read-write 0 No effect #0 1 Card insert #1 CREMOVE Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: Card detect function will start after SCEN (SC_CTL[0]) is set. 11 1 read-write 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SC_CTL[19]), hardware will not set this flag. 5 1 read-write 0 Receiver frame error flag did not occur #0 1 Receiver frame error flag occurred #1 PEF Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SC_CTL[19]), hardware will not set this flag. 4 1 read-write 0 Receiver parity error flag did not occur #0 1 Receiver parity error flag occurred #1 RXACT Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status. 23 1 read-only 0 This bit is cleared automatically when Rx transfer is finished #0 1 This bit is set by hardware when Rx transfer is in active #1 RXEMPTY Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer is empty or not. 1 1 read-only 0 Rx buffer is not empty #0 1 Rx buffer is empty, it means the last byte in Rx buffer has been read from DAT (SC_DAT[7:0]) #1 RXFULL Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer is full or not. 2 1 read-only 0 Rx buffer count is less than 4 #0 1 Rx buffer count equals to 4 #1 RXOV Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it. 0 1 read-write 0 Rx buffer is not overflow #0 1 Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes) #1 RXOVERR Receiver over Retry Error\nThis bit is used for indicate receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF (SC_STATUS[4]) bit will not set. 22 1 read-write 0 Receiver retries counts is not over than RXRTY (SC_CTL[18:16]) + 1 #0 1 Receiver retries counts over than RXRTY (SC_CTL[18:16]) + 1 #1 RXPOINT Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte in Rx buffer is read by reading DAT (SC_DAT[7:0]), RXPOINT decreases one. 16 3 read-only RXRTYERR Receiver Retry Error\nThis bit is used for indicate receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU.\nNote3: If user enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF (SC_STATUS[4]) bit will not set. 21 1 read-write 0 No Rx retry transfer #0 1 Rx has any error and retries transfer #1 TXACT Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status. 31 1 read-only 0 This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed #0 1 Transmit is active or the STOP bit of last byte has not been transmitted when Tx transfer is in active #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer is empty or not.\nNote: This bit will be cleared when writing data into DAT (SC_DAT[7:0]). 9 1 read-only 0 Tx buffer is not empty #0 1 Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register #1 TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer is full or not. 10 1 read-only 0 Tx buffer count is less than 4 #0 1 Tx buffer count equals to 4 #1 TXOV Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Tx buffer is not overflow #0 1 Tx buffer is overflow, it means an additional write operation to DAT (SC_DAT[7:0]) when Tx buffer is already full #1 TXOVERR Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it. 30 1 read-write 0 Transmitter retries counts is not over than TXRTY (SC_CTL[22:20]) + 1 #0 1 Transmitter retries counts over than TXRTY (SC_CTL[22:20]) + 1 #1 TXPOINT Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into DAT (SC_DAT[7:0]), TXPOINT increases one. When one byte of Tx buffer is transferred to Transmitter Shift Register, TXPOINT decreases one. 24 3 read-only TXRTYERR Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU. 29 1 read-write 0 No Tx retry transfer #0 1 Tx has any error and retries transfer #1 SC_TMRCTL0 SC_TMRCTL0 SC Timer0 Control Register 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value\nThis field indicates the internal Timer0 counter values. \nNote: Unit of Timer0 counter is ETU base. 0 24 read-write OPMODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.1528 for programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL0 register #0 1 Last value is synchronizing #1 SC_TMRCTL1 SC_TMRCTL1 SC Timer1 Control Register 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.1528 for programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL1 register #0 1 Last value is synchronizing #1 SC_TMRCTL2 SC_TMRCTL2 SC Timer2 Control Register 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.1528 for programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL2 register #0 1 Last value is synchronizing #1 SC_TMRDAT0 SC_TMRDAT0 SC Timer0 Current Data Register 0x38 -1 read-only n 0x0 0x0 CNT0 Timer0 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer0. 0 24 read-only SC_TMRDAT12 SC_TMRDAT12 SC Timer1/2 Current Data Register 0x3C -1 read-only n 0x0 0x0 CNT1 Timer1 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer1. 0 8 read-only CNT2 Timer2 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer2. 8 8 read-only SC_UARTCTL SC_UARTCTL SC UART Mode Control Register 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Control\nThis bit is used to disable parity check function.\nNote: In smart card mode, this bit must be 0 (default setting is with parity bit). 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset SC event to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nThis field is used to select UART data transfer length.\nNote: In smart card mode, this field must be 00. 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SC1 SC Register Map SC 0x0 0x0 0x40 registers n 0x4C 0x4 registers n SC_ACTCTL SC_ACTCTL SC Activation Control Register 0x4C read-write n 0x0 0x0 T1EXT T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nPlease refer to SC activation sequence in Figure 6.154.\nThe cycle scaling factor is 2048 and \nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3. 0 5 read-write SC_ALTCTL SC_ALTCTL SC Alternate Control Register 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in ACTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SC_TMRCTL0[23:0]). 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SC_TMRCTL1[7:0]). 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SC_TMRCTL2[7:0]). 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nThis bit is usde for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SC_INTSTS[8]) also. 11 1 read-write 0 Auto deactivation Disabled #0 1 Auto deactivation Enabled #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stop counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stop counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop count and set 1 to reload and start count. The counter unit is ETU base.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stop counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in DACTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.154.\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.155.\nDeactivation: refer to Deactivation Sequence in Figure 6.156.\nNote: When setting activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function. 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST RX Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_ALTCTL register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_ALTCTL register #0 1 Last value is synchronizing #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and Tx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the Tx internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by set TXRST (SC_ALTCTL[0]) or RXRST (SC_ALTCTL[1]). Thus, do not fill in WARSTEN, TXRST or RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit\nThis bit is used to enable auto convention function.\nNote1: If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SC_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.\nNote2: If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SC_INTSTS[10]) and generate an interrupt signal to inform CPU when ACERRIEN (SC_INTEN[10]) is enabled. 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) SC modue clocks and de-bounce sample card removal once per 128 SC modue clocks #00 CDLV Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled. 26 1 read-write 0 When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin (SC_CD) from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN (SC_CTL[3]) is enabled, this field is ignored. 4 2 read-write 0 Direct convention #00 1 Reserved. #01 2 Reserved. #10 3 Inverse convention #11 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Bit\nThis bit is used to disable Rx receive function.\nNote: If AUTOCEN (SC_CTL[3]) is enabled, this field is ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF (SC_INTSTS[0]) will be set. If RDAIEN (SC_INTEN[0]) is enabled, an interrupt signal will be generated to inform CPU. 6 2 read-write 0 Rx Buffer Trigger Level with 01 bytes #00 1 Rx Buffer Trigger Level with 02 bytes #01 2 Rx Buffer Trigger Level with 03 bytes #10 3 Reserved. #11 SCEN SC Controller Enable Bit\nSet this bit to 1 to enable SC operation function.\nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 0 1 read-write 0 SC will force all transition to IDLE state #0 1 SC controller is enabled and all function can work correctly #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 30 1 read-only 0 Synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Channel Selection \nOther configurations are reserved 13 2 read-write 0 All internal timer function Disabled #00 3 Internal 24-bit Timer0 and two 8-bit Timer0 and Timer1 are enabled. User can configure them by setting SC_TMRCTL0[23:0], SC_TMRCTL1[7:0] and SC_TMRCTL2[7:0] #11 TXOFF TX Transition Disable Bit\nThis bit is used to disable Tx transmit function. 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_DAT SC_DAT SC Receive/Transmit Holding Buffer Register 0x0 read-write n 0x0 0x0 DAT Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.\nNote: If SCEN (SC_CTL[0]) is not enabled, DAT cannot be programmed. 0 8 read-write SC_EGT SC_EGT SC Extra Guard Time Register 0xC read-write n 0x0 0x0 EGT Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base. 0 8 read-write SC_ETUCTL SC_ETUCTL SC Element Time Unit Control Register 0x14 -1 read-write n 0x0 0x0 ETURDIV ETU Rate Divider\nThe field is used for define ETU time unit.\nThe real ETU time unit is (ETURDIV + 1) * SC clock time.\nNote: User can configure this field, but this field must be greater than 0x004. 0 12 read-write SC_INTEN SC_INTEN SC Interrupt Enable Control Register 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time. 6 1 read-write 0 Block guard time interrupt Disabled #0 1 Block guard time interrupt Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SC_STATUS[13]). \nNote: Either cared insert or card remove event will generate crad detect event. 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt. 0 1 read-write 0 Received data bytes in Rx buffer reach trigger level interrupt Disabled #0 1 Received data bytes in Rx buffer reach trigger level interrupt Enabled #1 RXTOIEN Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error status is at SC_STATUS which includes receiver break error BEF (SC_STATUS[6]), frame error FEF (SC_STATUS[5]), parity error PEF (SC_STATUS[4]), receive buffer overflow error RXOV (SC_STATUS[0]), transmit buffer overflow error TXOV (SC_STATUS[8]), receiver retry over limit error RXOVERR (SC_STATUS[22]) or transmitter retry over limit error TXOVERR (SC_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 TXEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 SC_INTSTS SC_INTSTS SC Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it. 10 1 read-write 0 Received TS at ATR state is 0x3B or 0x3F #0 1 Received TS at ATR state is neither 0x3B nor 0x3F #1 BGTIF None 6 1 read-write 0 Block guard time interrupt did not occur #0 1 Block guard time interrupt occurred #1 CDIF Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag. The actual card detect status is in CINSERT (SC_STATUS[12]) and CREMOVE (SCn_STATUS[11]). Note1: This bit is read only, and will be cleared after CINSERT or CREMOVE status has been cleared. Note2: Either cared insert or card remove event will generate crad detect event. 7 1 read-only 0 Card detect event did not occur #0 1 Card detect event occurred #1 INITIF Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Initial sequence is not complete #0 1 Initial sequence is completed #1 RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from DAT (SC_DAT[7:0]) and remains receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. 0 1 read-only 0 Number of receive buffer is less than RXTRGLV setting #0 1 Number of receive buffer data equals the RXTRGLV setting #1 RXTOIF Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading DAT (SC_DAT[7:0]) to clear it. 9 1 read-only 0 Receive buffer time-out interrupt did not occur #0 1 Receive buffer time-out interrupt occurred #1 TERRIF Transfer Error Interrupt Status Flag\nThis field is used for indicate transfer error interrupt status flag. The transfer error status is at SC_STATUS which includes receiver break error BEF (SC_STATUS[6]), frame error FEF (SC_STATUS[5]), parity error PEF (SC_STATUS[4]), receive buffer overflow error RXOV (SC_STATUS[0]), transmit buffer overflow error TXOV (SC_STATUS[8]), receiver retry over limit error RXOVERR (SC_STATUS[22]) or transmitter retry over limit error TXOVERR (SC_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it. 2 1 read-write 0 Transfer error interrupt did not occur #0 1 Transfer error interrupt occurred #1 TMR0IF Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 3 1 read-write 0 Timer0 interrupt did not occur #0 1 Timer0 interrupt occurred #1 TMR1IF Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 4 1 read-write 0 Timer1 interrupt did not occur #0 1 Timer1 interrupt occurred #1 TMR2IF Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it. 5 1 read-write 0 Timer2 interrupt did not occur #0 1 Timer2 interrupt occurred #1 TXEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit, user must write data to DAT (SC_DAT[7:0]) and then this bit will be cleared automatically. 1 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 SC_PINCTL SC_PINCTL SC Pin Control State Register 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATSTS SC_DATA Pin Status (Read Only) 16 1 read-only 0 The SC_DATA pin status is low #0 1 The SC_DATA pin status is high #1 PWREN SC_PWR Pin Signal\nUser can set PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0]) to decide SC_PWR pin is in high or low level.\nWrite this bit can drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. \nRead this bit to get SC_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes 0 1 read-write 0 SC_PWR signal status is low #0 1 SC_PWR signal status is high #1 PWRINV SC_PWR Pin Inverse\nThis bit is used for inverse the SC_PWR pin.\nThere are four kinds of combination for SC_PWR pin setting by PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0]). And all conditions as below list.\nNote: User must select PWRINV (SC_PINCTL[11]) before smart card is enabled by SCEN (SC_CTL[0]). 11 1 read-write PWRSTS SC_PWR Pin Status (Read Only)\nThis bit is the pin status of SC_PWR. 17 1 read-only 0 SC_PWR pin to low #0 1 SC_PWR pin to high #1 RSTSTS SC_RST Pin Status (Read Only)\nThis bit is the pin status of SC_RST. 18 1 read-only 0 SC_RST pin is low #0 1 SC_RST pin is high #1 SCDATA SC_DATA Pin Signal \nThis bit is the signal status of SC_DATA but user can also drive SC_DATA pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes. 9 1 read-write 0 Drive SC_DATA pin to low.\nSC_DATA signal status is low #0 1 Drive SC_DATA pin to high.\nSC_DATA signal status is high #1 SCRST SC_RST Pin Signal\nThis bit is the signal status of SC_RST but user can drive SC_RST pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST signal status is low #0 1 Drive SC_RST pin to high.\nSC_RST signal status is high #1 SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_PINCTL register. 30 1 read-only 0 Synchronizing is completion, user can write new data to SC_PINCTL register #0 1 Last value is synchronizing #1 SC_RXTOUT SC_RXTOUT SC Receive Buffer Time-out Counter Register 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the Rx buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading DAT (SC_DAT[7:0]), a receiver time-out flag RXTOIF (SC_INTSTS[9]) will be set, and hardware will generate an interrupt signal to inform CPU when RXTOIEN (SC_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is (RFTM + 0.5) ETU time.\nNote2: Filling in all 0 to this field will disable this function. 0 9 read-write SC_STATUS SC_STATUS SC Transfer Status Register 0x20 -1 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits').\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. 6 1 read-write 0 Receiver break error flag did not occur #0 1 Receiver break error flag occurred #1 CDPINSTS Card Detect Pin Status (Read Only)\nThis bit is the pin status of SC_CD. 13 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CINSERT Card Insert Status of SC_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: The card detect function will start after SCEN (SC_CTL[0]) is set. 12 1 read-write 0 No effect #0 1 Card insert #1 CREMOVE Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: Card detect function will start after SCEN (SC_CTL[0]) is set. 11 1 read-write 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SC_CTL[19]), hardware will not set this flag. 5 1 read-write 0 Receiver frame error flag did not occur #0 1 Receiver frame error flag occurred #1 PEF Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN (SC_CTL[19]), hardware will not set this flag. 4 1 read-write 0 Receiver parity error flag did not occur #0 1 Receiver parity error flag occurred #1 RXACT Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status. 23 1 read-only 0 This bit is cleared automatically when Rx transfer is finished #0 1 This bit is set by hardware when Rx transfer is in active #1 RXEMPTY Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer is empty or not. 1 1 read-only 0 Rx buffer is not empty #0 1 Rx buffer is empty, it means the last byte in Rx buffer has been read from DAT (SC_DAT[7:0]) #1 RXFULL Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer is full or not. 2 1 read-only 0 Rx buffer count is less than 4 #0 1 Rx buffer count equals to 4 #1 RXOV Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it. 0 1 read-write 0 Rx buffer is not overflow #0 1 Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes) #1 RXOVERR Receiver over Retry Error\nThis bit is used for indicate receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF (SC_STATUS[4]) bit will not set. 22 1 read-write 0 Receiver retries counts is not over than RXRTY (SC_CTL[18:16]) + 1 #0 1 Receiver retries counts over than RXRTY (SC_CTL[18:16]) + 1 #1 RXPOINT Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte in Rx buffer is read by reading DAT (SC_DAT[7:0]), RXPOINT decreases one. 16 3 read-only RXRTYERR Receiver Retry Error\nThis bit is used for indicate receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU.\nNote3: If user enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF (SC_STATUS[4]) bit will not set. 21 1 read-write 0 No Rx retry transfer #0 1 Rx has any error and retries transfer #1 TXACT Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status. 31 1 read-only 0 This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed #0 1 Transmit is active or the STOP bit of last byte has not been transmitted when Tx transfer is in active #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer is empty or not.\nNote: This bit will be cleared when writing data into DAT (SC_DAT[7:0]). 9 1 read-only 0 Tx buffer is not empty #0 1 Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register #1 TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer is full or not. 10 1 read-only 0 Tx buffer count is less than 4 #0 1 Tx buffer count equals to 4 #1 TXOV Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it. 8 1 read-write 0 Tx buffer is not overflow #0 1 Tx buffer is overflow, it means an additional write operation to DAT (SC_DAT[7:0]) when Tx buffer is already full #1 TXOVERR Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it. 30 1 read-write 0 Transmitter retries counts is not over than TXRTY (SC_CTL[22:20]) + 1 #0 1 Transmitter retries counts over than TXRTY (SC_CTL[22:20]) + 1 #1 TXPOINT Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into DAT (SC_DAT[7:0]), TXPOINT increases one. When one byte of Tx buffer is transferred to Transmitter Shift Register, TXPOINT decreases one. 24 3 read-only TXRTYERR Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU. 29 1 read-write 0 No Tx retry transfer #0 1 Tx has any error and retries transfer #1 SC_TMRCTL0 SC_TMRCTL0 SC Timer0 Control Register 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value\nThis field indicates the internal Timer0 counter values. \nNote: Unit of Timer0 counter is ETU base. 0 24 read-write OPMODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.1528 for programming Timer0. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL0 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL0 register #0 1 Last value is synchronizing #1 SC_TMRCTL1 SC_TMRCTL1 SC Timer1 Control Register 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.1528 for programming Timer1. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL1 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL1 register #0 1 Last value is synchronizing #1 SC_TMRCTL2 SC_TMRCTL2 SC Timer2 Control Register 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.1528 for programming Timer2. 24 4 read-write SYNC SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SC_TMRCTL2 register. 31 1 read-only 0 Synchronizing is completion, user can write new data to SC_TMRCTL2 register #0 1 Last value is synchronizing #1 SC_TMRDAT0 SC_TMRDAT0 SC Timer0 Current Data Register 0x38 -1 read-only n 0x0 0x0 CNT0 Timer0 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer0. 0 24 read-only SC_TMRDAT12 SC_TMRDAT12 SC Timer1/2 Current Data Register 0x3C -1 read-only n 0x0 0x0 CNT1 Timer1 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer1. 0 8 read-only CNT2 Timer2 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer2. 8 8 read-only SC_UARTCTL SC_UARTCTL SC UART Mode Control Register 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Control\nThis bit is used to disable parity check function.\nNote: In smart card mode, this bit must be 0 (default setting is with parity bit). 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset SC event to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nThis field is used to select UART data transfer length.\nNote: In smart card mode, this field must be 00. 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SCS SYST_NVIC_SCS Register Map SYST_NVIC_SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05. 16 16 read-write CPUID CPUID CPUID Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code Assigned by ARM 24 8 read-only PART Architecture of the Processor\nRead as 0xC for ARMv6-M parts 16 4 read-only PARTNO Part Number of the Processor\nRead as 0xC20. 4 12 read-only REVISION Revision Number\nRead as 0x0 0 4 read-only ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults:\nThis bit is read only. 22 1 read-write 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT If Set, a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only. 23 1 read-write NMIPENDSET NMI Set-pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation: 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit\nWrite Operation:\nThis is a write only bit. When you want to clear PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the Active Exception Number 0 6 read-write 0 Thread mode 0 VECTPENDING Indicates the Exception Number of the Highest Priority Pending Enabled Exception: 12 6 read-write 0 No pending exceptions 0 NVIC_ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status Enabled 1 NVIC_ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 NVIC_IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_1 Priority of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_2 Priority of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_3 Priority of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_5 Priority of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_6 Priority of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_7 Priority of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_11 Priority of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write PRI_8 Priority of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_9 Priority of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_13 Priority of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority 14 2 read-write PRI_14 Priority of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_15 Priority of IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_17 Priority of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_18 Priority of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_19 Priority of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_21 Priority of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority 14 2 read-write PRI_22 Priority of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_23 Priority of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_25 Priority of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_26 Priority of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_27 Priority of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority. 6 2 read-write PRI_29 Priority of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority. 14 2 read-write PRI_30 Priority of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_31 Priority of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0 ~ IRQ31 Set-enable Control Register 0x100 read-write n 0x0 0x0 SETENA Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status Enabled 1 NVIC_ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Set Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode: 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority 30 2 read-write SYST_CSR SYST_CSR SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 8 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer. 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 24 2 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 28 2 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 9 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 6 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If this bit is enabled, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from the M0564 series to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 SPI/I2S control logic Disabled #0 1 SPI/I2S control logic Enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurs #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurs #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote1: This bit will be cleared by writing 1 to it.\nNote2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n 0x60 0xC registers n SPIx_CLKDIV SPIx_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: Not supported in I2S mode. 0 8 read-write SPIx_CTL SPIx_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DATDIR Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer. 20 1 read-write 0 SPI data is input direction #0 1 SPI data is output direction #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. 8 5 read-write HALFDPX SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 14 1 read-write 0 SPI operates in full-duplex transfer #0 1 SPI operates in half-duplex transfer #1 LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 REORDER Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 RXONLY Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 15 1 read-write 0 Receive-only mode Disabled #0 1 Receive-only mode Enabled #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample: 4 4 read-write TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPIx_FIFOCTL SPIx_FIFOCTL SPI FIFO Control Register 0x10 -1 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. 24 2 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. 28 2 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote:\n1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\n2. This bit should be set as 0 in I2S mode.\n3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 6 1 read-write 0 The SPI data out is keep 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is keep 1 if there is TX underflow event in Slave mode #1 SPIx_I2SCLK SPIx_I2SCLK I2S Clock Divider Control Register 0x64 read-write n 0x0 0x0 BCLKDIV Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . \nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 8 9 read-write MCLKDIV Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate. 0 6 read-write SPIx_I2SCTL SPIx_I2SCTL I2S Control Register 0x60 read-write n 0x0 0x0 FORMAT Data Format Selection 28 2 read-write 0 I2S data format #00 1 MSB justified data format #01 2 PCM mode A #10 3 PCM mode B #11 I2SEN I2S Controller Enable Bit\nNote:\n1. If this bit is enabled, I2Sx_BCLK will start to output in Master mode.\n2. Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 0 1 read-write 0 I2S mode Disabled #0 1 I2S mode Enabled #1 LZCEN Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 LZCIEN Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 25 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 MCLKEN Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 15 1 read-write 0 Master clock Disabled #0 1 Master clock Enabled #1 MONO Monaural Data 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format #1 MUTE Transmit Mute Enable Bit 3 1 read-write 0 Transmit data is shifted from buffer #0 1 Transmit channel zero #1 ORDER Stereo Data Order in FIFO 7 1 read-write 0 Left channel data at high byte #0 1 Left channel data at low byte #1 RXEN Receive Enable Bit 2 1 read-write 0 Data receive Disabled #0 1 Data receive Enabled #1 RXLCH Receive Left Channel Enable Bit 23 1 read-write 0 Receive right channel data in Mono mode #0 1 Receive left channel data in Mono mode #1 RZCEN Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RZCIEN Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 24 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 SLAVE Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from the M0564 series to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXEN Transmit Enable Bit 1 1 read-write 0 Data transmit Disabled #0 1 Data transmit Enabled #1 WDWIDTH Word Width 4 2 read-write 0 data size is 8-bit #00 1 data size is 16-bit #01 2 data size is 24-bit #10 3 data size is 32-bit #11 SPIx_I2SSTS SPIx_I2SSTS I2S Status Register 0x68 -1 read-write n 0x0 0x0 I2SENSTS I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 15 1 read-only 0 SPI/I2S control logic Disabled #0 1 SPI/I2S control logic Enabled #1 LZCIF Left Channel Zero Cross Interrupt Flag 21 1 read-write 0 No zero cross event occurred on left channel #0 1 Zero cross event occurred on left channel #1 RIGHT Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel. 4 1 read-only 0 Left channel #0 1 Right channel #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 3 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 RZCIF Right Channel Zero Cross Interrupt Flag 20 1 read-write 0 No zero cross event occurred on right channel #0 1 Zero cross event occurred on right channel #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 3 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 19 1 read-write SPIx_PDMACTL SPIx_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPIx_RX SPIx_RX SPI Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register. 0 32 read-only SPIx_SSCTL SPIx_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state #0 1 set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS). 2 1 read-write 0 The slave selection signal SPIx_SS is active low #0 1 The slave selection signal SPIx_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPIx_STATUS SPIx_STATUS SPI Status Register 0x14 -1 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 No FIFO is overrun #0 1 Receive FIFO is overrun #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurs #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurs #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 SPI controller Disabled #0 1 SPI controller Enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt was cleared or not occurred #0 1 Slave select active interrupt event occurred #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt was cleared or not occurred #0 1 Slave select inactive interrupt event occurred #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote1: This bit will be cleared by writing 1 to it.\nNote2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPIx_TX SPIx_TX SPI Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x114 0x4 registers n 0x18 0x8 registers n 0x24 0x8 registers n 0x30 0x2C registers n 0x80 0xC registers n 0x90 0x4 registers n 0xC0 0x4 registers n BODCTL SYS_BODCTL Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by RC10K clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit. Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 2 read-write 0 Brown-Out Detector threshold voltage is 2.2V #00 1 Brown-Out Detector threshold voltage is 2.7V #01 2 Brown-Out Detector threshold voltage is 3.7V #10 3 Brown-Out Detector threshold voltage is 4.5V #11 LVRDGSEL LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 VDETDGSEL Voltage Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 25 3 read-write 0 VDET output is sampled by VDET clock #000 1 16 system clock (HCLK) #001 2 32 system clock (HCLK) #010 3 64 system clock (HCLK) #011 4 128 system clock (HCLK) #100 5 256 system clock (HCLK) #101 6 512 system clock (HCLK) #110 7 1024 system clock (HCLK) #111 VDETEN Voltage Detector Enable Bit\nNote1: This function is still active in whole chip power-down mode.\nNote2: This function need use LIRC or LXT as VDET clock source, which is selected in VDETCKSEL (CLK_BODCLK[0]).\nNote2: The input pin for VDET detect voltage is selectabe by VDETPINSEL (SYS_BODCTL[17]). 16 1 read-write 0 VDET detect external input voltage function Disabled #0 1 VDET detect external input voltage function Enabled #1 VDETIEN Voltage Detector Interrupt Enable Bit 18 1 read-write 0 VDET interrupt Disabled #0 1 VDET interrupt Enabled #1 VDETIF Voltage Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'. 19 1 read-write 0 VDET does not detect any voltage draft at external pin down through or up through the voltage of Bandgap #0 1 When VDET detects the external pin is dropped down through the voltage of Bandgap or the external pin is raised up through the voltage of Bandgap, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 VDETOUT Voltage Detector Output Status\nIt means the detected voltage is lower than Bandgap. If the VDETEN is 0, VDET function disabled, this bit always responds 0. 24 1 read-write 0 VDET output status is 0 #0 1 VDET output status is 1 #1 VDETPINSEL Voltage Detector External Input Voltage Pin Selection\nNote1: If VDET_P0 is selected, multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0]).\nNote2: If VDET_P1 is selected, multi-function pin must be selected correctly in PB1MFP (SYS_GPB_MFPL[7:4]). 17 1 read-write 0 The input voltage is from VDET_P0 (PB.0) #0 1 The input voltage is from VDET_P1 (PB.1) #1 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 PA10MFP PA.10 Multi-function Pin Selection 8 4 read-write PA11MFP PA.11 Multi-function Pin Selection 12 4 read-write PA12MFP PA.12 Multi-function Pin Selection 16 4 read-write PA13MFP PA.13 Multi-function Pin Selection 20 4 read-write PA14MFP PA.14 Multi-function Pin Selection 24 4 read-write PA15MFP PA.15 Multi-function Pin Selection 28 4 read-write PA8MFP PA.8 Multi-function Pin Selection 0 4 read-write PA9MFP PA.9 Multi-function Pin Selection 4 4 read-write GPA_MFPL SYS_GPA_MFPL GPIOA Low Byte Multiple Function Control Register 0x30 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write PA4MFP PA.4 Multi-function Pin Selection 16 4 read-write PA5MFP PA.5 Multi-function Pin Selection 20 4 read-write PA6MFP PA.6 Multi-function Pin Selection 24 4 read-write PA7MFP PA.7 Multi-function Pin Selection 28 4 read-write GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB10MFP PB.10 Multi-function Pin Selection 8 4 read-write PB11MFP PB.11 Multi-function Pin Selection 12 4 read-write PB12MFP PB.12 Multi-function Pin Selection 16 4 read-write PB13MFP PB.13 Multi-function Pin Selection 20 4 read-write PB14MFP PB.14 Multi-function Pin Selection 24 4 read-write PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write PB9MFP PB.9 Multi-function Pin Selection 4 4 read-write GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 PC10MFP PC10 Multi-function Pin Selection 8 4 read-write PC11MFP PC11 Multi-function Pin Selection 12 4 read-write PC12MFP PC12 Multi-function Pin Selection 16 4 read-write PC13MFP PC13 Multi-function Pin Selection 20 4 read-write PC14MFP PC14 Multi-function Pin Selection 24 4 read-write PC15MFP PC15 Multi-function Pin Selection 28 4 read-write PC8MFP PC8 Multi-function Pin Selection 0 4 read-write PC9MFP PC9 Multi-function Pin Selection 4 4 read-write GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write PC6MFP PC.6 Multi-function Pin Selection 24 4 read-write PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD10MFP PD.10 Multi-function Pin Selection 8 4 read-write PD11MFP PD.11 Multi-function Pin Selection 12 4 read-write PD12MFP PD.12 Multi-function Pin Selection 16 4 read-write PD13MFP PD.13 Multi-function Pin Selection 20 4 read-write PD14MFP PD.14 Multi-function Pin Selection 24 4 read-write PD15MFP PD.15 Multi-function Pin Selection 28 4 read-write PD8MFP PD.8 Multi-function Pin Selection 0 4 read-write PD9MFP PD.9 Multi-function Pin Selection 4 4 read-write GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 4 read-write PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD4MFP PD.4 Multi-function Pin Selection 16 4 read-write PD5MFP PD.5 Multi-function Pin Selection 20 4 read-write PD6MFP PD.6 Multi-function Pin Selection 24 4 read-write PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write GPE_MFPH SYS_GPE_MFPH GPIOE High Byte Multiple Function Control Register 0x54 read-write n 0x0 0x0 PE10MFP PE.10 Multi-function Pin Selection 8 4 read-write PE11MFP PE.11 Multi-function Pin Selection 12 4 read-write PE12MFP PE.12 Multi-function Pin Selection 16 4 read-write PE13MFP PE.13 Multi-function Pin Selection 20 4 read-write PE8MFP PE.8 Multi-function Pin Selection 0 4 read-write PE9MFP PE.9 Multi-function Pin Selection 4 4 read-write GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 -1 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write PE1MFP PE.1 Multi-function Pin Selection 4 4 read-write PE2MFP PE.2 Multi-function Pin Selection 8 4 read-write PE3MFP PE.3 Multi-function Pin Selection 12 4 read-write PE4MFP PE.4 Multi-function Pin Selection 16 4 read-write PE5MFP PE.5 Multi-function Pin Selection 20 4 read-write PE6MFP PE.6 Multi-function Pin Selection 24 4 read-write PE7MFP PE.7 Multi-function Pin Selection 28 4 read-write GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit. 12 4 read-write 0 PF.3 pin is configured as GPIO pins 0 1 PF.3 pin is configured as external 4~24 MHz external high speed crystal oscillator (HXT) pins 1 PF4MFP PF.4 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit. 16 4 read-write 0 PF.4 pin is configured as GPIO pins 0 1 PF.4 pin is configured as external 4~24 MHz external high speed crystal oscillator (HXT) pins 1 PF5MFP PF.5 Multi-function Pin Selection 20 4 read-write PF6MFP PF.6 Multi-function Pin Selection 24 4 read-write PF7MFP PF.7 Multi-function Pin Selection 28 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 -1 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 CRCRST CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 CRC calculation controller normal operation #0 1 CRC calculation controller reset #1 EBIRST EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 EBI controller normal operation #0 1 EBI controller reset #1 HDIVRST HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the HDIV controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 HDIV controller normal operation #0 1 HDIV controller reset #1 PDMARST PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC read-write n 0x0 0x0 ACMP01RST ACMP01 Controller Reset 22 1 read-write 0 ACMP01 controller normal operation #0 1 ACMP01 controller reset #1 ADCRST ADC Controller Reset 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 PWM0RST PWM0 Controller Reset 20 1 read-write 0 PWM0 controller normal operation #0 1 PWM0 controller reset #1 PWM1RST PWM1 Controller Reset 21 1 read-write 0 PWM1 controller normal operation #0 1 PWM1 controller reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1RST SPI1 Controller Reset 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 UART2RST UART2 Controller Reset 18 1 read-write 0 UART2 controller normal operation #0 1 UART2 controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 read-write n 0x0 0x0 SC0RST SC0 Controller Reset 0 1 read-write 0 SC0 controller normal operation #0 1 SC0 controller reset #1 SC1RST SC1 Controller Reset 1 1 read-write 0 SC1 controller normal operation #0 1 SC1 controller reset #1 USCI0RST USCI0 Controller Reset 8 1 read-write 0 USCI0 controller normal operation #0 1 USCI0 controller reset #1 USCI1RST USCI1 Controller Reset 9 1 read-write 0 USCI1 controller normal operation #0 1 USCI1 controller reset #1 USCI2RST USCI2 Controller Reset 10 1 read-write 0 USCI2 controller normal operation #0 1 USCI2 controller reset #1 IRCTCTL0 SYS_IRCTCTL0 HIRC0 Trim Control Register 0x80 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 0 (HIRC0) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL0[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC0 auto trim function #00 1 Enable HIRC0 auto trim function and trim HIRC to 22.1184 MHz #01 2 Reserved. #10 3 Reserved. #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz, LXT).\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) #0 1 Reserved. #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL0[1:0]) will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTCTL1 SYS_IRCTCTL1 HIRC1 Trim Control Register 0x90 -1 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is keep going if clock is inaccuracy #0 1 The trim operation is stopped if clock is inaccuracy #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 1 (HIRC 1) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 0 2 read-write 0 Disable HIRC1 auto trim function #00 1 Reserved. #01 2 Enable HIRC1 auto trim function and trim HIRC to 48 MHz #10 3 Reserved. #11 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 clocks of reference clock #00 1 Trim value calculation is based on average difference in 8 clocks of reference clock #01 2 Trim value calculation is based on average difference in 16 clocks of reference clock #10 3 Trim value calculation is based on average difference in 32 clocks of reference clock #11 REFCKSEL Reference Clock Selection 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) #0 1 Reserved. #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0x84 read-write n 0x0 0x0 CLKEIEN HIRC0 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC0 clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS0[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2 1 read-write 0 Disable CLKERRIF(SYS_IRCTSTS0[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTSTS0[2]) status to trigger an interrupt to CPU #1 CLKEIEN1 HIRC1 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC1 clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 10 1 read-write 0 Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN HIRC0 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL0[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS0[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRCTSTS0[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTSTS0[1]) status to trigger an interrupt to CPU #1 TFAILIEN1 HIRC1 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. 9 1 read-write 0 Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0x88 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator 0 (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL0[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL0[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN0[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accuracy #0 1 Clock frequency is inaccuracy #1 CLKERRIF1 HIRC1 Clock Error Interrupt Status\nWhen 48 MHz internal high speed RC oscillator 1 (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL1[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL1[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN1[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0. 10 1 read-write 0 HIRC1 Clock frequency is accuracy #0 1 HIRC1 Clock frequency is inaccuracy #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal high-speed RC oscillator 0 frequency doesn't lock at 22.1184 MHz yet #0 1 The internal high-speed RC oscillator 0 frequency locked at 22.1184 MHz #1 FREQLOCK1 HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 8 1 read-write 0 The internal high-speed RC oscillator 1 frequency doesn't lock at 48 MHz yet #0 1 The internal high-speed RC oscillator 1 frequency locked at 48 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL0[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN0[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 TFAILIF1 HIRC1 Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN1[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. Write 1 to clear this to 0. 9 1 read-write 0 HIRC1 trim value update limitation count does not reach #0 1 HIRC1 trim value update limitation count reached and frequency still not locked #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C read-write n 0x0 0x0 VBATUGEN VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 1 1 read-write 0 VBAT unity gain buffer function Disabled (default) #0 1 VBAT unity gain buffer function Enabled #1 VTEMPEN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 MODCTL SYS_MODCTL Modulation Control Register 0xC0 read-write n 0x0 0x0 MODEN Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM channel output and UART1_TXD. 0 1 read-write 0 Modulation Function Disabled #0 1 Modulation Function Enabled #1 MODH Modulation at Data High\nSelect modulation pulse(PWM) at UART1_TXD high or low 1 1 read-write 0 Modulation pulse at UART1_TXD low #0 1 Modulation pulse at UART1_TXD high #1 MODPWMSEL PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART1_TXD.\nNote: This bit is valid while MODEN (SYS_MODCTL[0]) is set to 1. 4 3 read-write 0 PWM0 channel 0 modulate with UART1_TXD #000 1 PWM0 channel 1 modulate with UART1_TXD #001 2 PWM0 channel 2 modulate with UART1_TXD #010 3 PWM0 channel 3 modulete with UART1_TXD #011 PDID SYS_PDID Part Device Identification Number Register 0x0 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-on Reset Controller Register 0x24 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 read-write n 0x0 0x0 REGLCTL Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 1 7 write-only REGLCTL0 Register Lock Control Disable Index (Read Only)\nThe Protected registers are:\nSYS_IPRST0: address 0x5000_0008\nSYS_BODCTL: address 0x5000_0018\nSYS_PORCTL: address 0x5000_0024\nSYS_VREFCTL: address 0x5000_0028\nCLK_PWRCTL[13]: address 0x5000_0200 (HIRC48 Enable Bit)\nCLK_PWRCTL[12]: address 0x5000_0200 (HXT Crystal Type Select Bit)\nCLK_PWRCTL[11:10]: address 0x5000_0200 (HXT Gain Control Bit)\nCLK_PWRCTL[7]: address 0x5000_0200 (System Power-down Enable)\nCLK_PWRCTL[5]: address 0x5000_0200 (Power-down Mode Wake-up Interrupt Enable Bit)\nCLK_PWRCTL[4]: address 0x5000_0200 (Enable the Wake-up Delay Counter)\nCLK_PWRCTL[3]: address 0x5000_0200 (LIRC Enable Bit)\nCLK_PWRCTL[2]: address 0x5000_0200 (HIRC Enable Bit)\nCLK_PWRCTL[1]: address 0x5000_0200 (LXT Enable Bit)\nCLK_PWRCTL[0]: address 0x5000_0200 (HXT Enable Bit)\nCLK_APBCLK0 [0]: address 0x5000_0208 (bit[0] is watchdog clock enable)\nCLK_CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLK_CLKSEL1 [1:0]: address 0x5000_0214 (for watchdog clock source select)\nCLK_CLKDSTS: address 0x5000_0274\nFMC_ISPCTL: address 0x5000_C000 (Flash ISP Control register)\nFMC_ISPTRG: address 0x5000_C010 (ISP Trigger Control register)\nFMC_ISPSTS: address 0x5000_C040\nWDT_CTL: address 0x4000_4000\nFMC_FTCTL: address 0x5000_C018\nPWM0_CTL: address 0x4004_0000 \nPWM1_CTL: address 0x4014_0000\nPWM0_DTCTL0_1: address 0x4004_0070\nPWM1_DTCTL0_1: address 0x4014_0070\nPWM0_DTCTL2_3: address 0x4004_0074\nPWM1_DTCTL2_3: address 0x4014_0074\nPWM0_DTCTL4_5: address 0x4004_0078\nPWM1_DTCTL4_5: address 0x4014_0078\nPWM0_BRKCTL0_1: address 0x4004_00C8\nPWM1_BRKCTL0_1: address 0x4014_00C8\nPWM0_BRKCTL2_3: address 0x4004_00CC\nPWM1_BRKCTL2_3: address 0x4014_00CC\nPWM0_BRKCTL4_5: address 0x4004_00D0\nPWM1_BRKCTL4_5: address 0x4014_00D0\nPWM0_INTEN1: address 0x4004_00E4\nPWM1_INTEN1: address 0x4014_00E4\nPWM0_INTSTS1: address 0x4004_00EC\nPWM1_INTSTS1: address 0x4014_00EC\nTIMER0_PWMCTL: address 0x4001_0040\nTIMER1_PWMCTL: address 0x4001_0140\nTIMER2_PWMCTL: address 0x4011_0040\nTIMER3_PWMCTL: address 0x4011_0140\nTIMER0_PWMDTCTL: address 0x4001_0058\nTIMER1_PWMDTCTL: address 0x4001_0158\nTIMER2_PWMDTCTL: address 0x4011_0058\nTIMER3_PWMDTCTL: address 0x4011_0158\nTIMER0_PWMBRKCTL: address 0x4001_0070\nTIMER1_PWMBRKCTL: address 0x4001_0170\nTIMER2_PWMBRKCTL: address 0x4011_0070\nTIMER3_PWMBRKCTL: address 0x4011_0170\nTIMER0_PWMSWBRK: address 0x4001_007C\nTIMER1_PWMSWBRK: address 0x4001_017C\nTIMER2_PWMSWBRK: address 0x4011_007C\nTIMER3_PWMSWBRK: address 0x4011_017C\nTIMER0_PWMINTEN1: address 0x4001_0084\nTIMER1_PWMINTEN1: address 0x4001_0184\nTIMER2_PWMINTEN1: address 0x4011_0084\nTIMER3_PWMINTEN1: address 0x4011_0184\nTIMER0_PWMINTSTS1: address 0x4001_008C\nTIMER1_PWMINTSTS1: address 0x4001_018C\nTIMER2_PWMINTSTS1: address 0x4011_008C\nTIMER3_PWMINTSTS1: address 0x4011_018 0 1 read-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF CPU Lockup Reset Flag\nThe CPU lockup reset flag is set by hardware If Cortex-M0 lockup happened.\nNote: This bit can be cleared by software writing '1'. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M0 lockup happened and chip is reset #1 CPURF CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: This bit can be cleared by software writing '1'. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 Core and FMC are reset by software setting CPURST to 1 #1 LVRF LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 MCURF MCU Reset Flag\nThe MCU reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 PINRF nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 WDTRF WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: This bit can be cleared by software writing '1'.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 TSOFFSET SYS_TSOFFSET Temperature Sensor Offset Register 0x114 read-only n 0x0 0x0 VTEMP Temperature Sensor Offset Value \nThis field reflects temperature sensor output voltage offset at 25oC from flash. 0 12 read-only VREFCTL SYS_VREFCTL VREF Control Register 0x28 read-write n 0x0 0x0 VREFCTL Int_VREF Control Bits (Write Protect)\nNote: These bit are write protected. Refer to the SYS_REGLCTL register. 0 5 read-write 0 From VREF pin #00000 3 VREF is internal 2.56V #00011 7 VREF is internal 2.048V #00111 11 VREF is internal 3.072V #01011 15 VREF is internal 4.096V #01111 16 VREF is from AVDD #10000 TMR01 TIMER Register Map TIMER 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x58 registers n 0x19C 0xC registers n 0x40 0x68 registers n TIMER0_ALTCTL TIMER0_ALTCTL Timer0 Alternative Control Register 0x20 read-write n 0x0 0x0 FUNCSEL Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 0 1 read-write 0 Timer controller is used as timer function #0 1 Timer controller is used as PWM function #1 TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Comparator Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC read-write n 0x0 0x0 CNT Timer Data Register\nRead operation:\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation:\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER0_CTL TIMER0_CTL Timer0 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from Tx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal. User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source #1 CNTEN Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not. 30 1 read-write 0 Stop/Suspend counting #0 1 Start counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If the updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode Disabled #0 1 The behavior selection in periodic mode Enabled #1 PSC Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 read-write n 0x0 0x0 ACMPSSEL ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 1 read-write 0 Capture Function source is from internal ACMP0 output signal #0 1 Capture Function source is from internal ACMP1 output signal #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on Tx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on Tx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer. #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on Tx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on Tx_EXT (x= 0~3) pin #111 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function. 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from Tx (x= 0~3) pin #0 1 Reserved. #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER0_PWMADCTS TIMER0_PWMADCTS Timer0 PWM ADC Trigger Source Select Register 0x90 read-write n 0x0 0x0 TRGEN PWM Counter Event Trigger ADC Conversion Enable Bit 7 1 read-write 0 PWM counter event trigger ADC conversion Disabled #0 1 PWM counter event trigger ADC conversion Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger ADC Conversion 0 3 read-write 0 Trigger ADC conversion at zero point (ZIF) #000 1 Trigger ADC conversion at period point (PIF) #001 2 Trigger ADC conversion at zero or period point (ZIF or PIF) #010 3 Trigger ADC conversion at compare up count point (CMPUIF) #011 4 Trigger ADC conversion at compare down count point (CMPDIF) #100 TIMER0_PWMBNF TIMER0_PWMBNF Timer0 PWM Brake Pin Noise Filter Register 0x68 read-write n 0x0 0x0 BKPINSRC Brake Pin Source Select 16 2 read-write 0 Brake pin source comes from TM_BRAKE0 #00 1 Brake pin source comes from TM_BRAKE1 #01 2 Brake pin source comes from TM_BRAKE2 #10 3 Brake pin source comes from TM_BRAKE3 #11 BRKFCNT Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time. 4 3 read-write BRKNFEN Brake Pin Noise Filter Enable Bit 0 1 read-write 0 Pin noise filter detect of TM_BRAKEx Disabled #0 1 Pin noise filter detect of TM_BRAKEx Enabled #1 BRKNFSEL Brake Pin Noise Filter Clock Selection 1 3 read-write 0 Noise filter clock is PCLKx #000 1 Noise filter clock is PCLKx/2 #001 2 Noise filter clock is PCLKx/4 #010 3 Noise filter clock is PCLKx/8 #011 4 Noise filter clock is PCLKx/16 #100 5 Noise filter clock is PCLKx/32 #101 6 Noise filter clock is PCLKx/64 #110 7 Noise filter clock is PCLKx/128 #111 BRKPINV Brake Pin Detection Control Bit 7 1 read-write 0 Brake pin event will be detected if TM_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if TM_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 TIMER0_PWMBRKCTL TIMER0_PWMBRKCTL Timer0 PWM Brake Control Register 0x70 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 TIMERx_PWM brake event will not affect PWMx_CH0 output #00 1 PWMx_CH0 output tri-state when TIMERx_PWM brake event happened #01 2 PWMx_CH0 output low level when TIMERx_PWM brake event happened #10 3 PWMx_CH0 output high level when TIMERx_PWM brake event happened #11 BRKAODD PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 TIMERx_PWM brake event will not affect PWMx_CH1 output #00 1 PWMx_CH1 output tri-state when TIMERx_PWM brake event happened #01 2 PWMx_CH1 output low level when TIMERx_PWM brake event happened #10 3 PWMx_CH1 output high level when TIMERx_PWM brake event happened #11 BRKPEEN Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 TM_BRAKEx pin event as edge-detect brake source Disabled #0 1 TM_BRAKEx pin event as edge-detect brake source Enabled #1 BRKPLEN Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 TM_BRAKEx pin event as level-detect brake source Disabled #0 1 TM_BRAKEx pin event as level-detect brake source Enabled #1 CPO0EBEN Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Internal ACMP0_O signal as edge-detect brake source Disabled #0 1 Internal ACMP0_O signal as edge-detect brake source Enabled #1 CPO0LBEN Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Internal ACMP0_O signal as level-detect brake source Disabled #0 1 Internal ACMP0_O signal as level-detect brake source Enabled #1 CPO1EBEN Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Internal ACMP1_O signal as edge-detect brake source Disabled #0 1 Internal ACMP1_O signal as edge-detect brake source Enabled #1 CPO1LBEN Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Internal ACMP1_O signal as level-detect brake source Disabled #0 1 Internal ACMP1_O signal as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System fail condition as edge-detect brake source Disabled #0 1 System fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System fail condition as level-detect brake source Disabled #0 1 System fail condition as level-detect brake source Enabled #1 TIMER0_PWMCLKPSC TIMER0_PWMCLKPSC Timer0 PWM Counter Clock Pre-scale Register 0x48 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 12 read-write TIMER0_PWMCLKSRC TIMER0_PWMCLKSRC Timer0 PWM Counter Clock Source Register 0x44 read-write n 0x0 0x0 CLKSRC PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 0 3 read-write 0 TMRx_CLK #000 1 Internal TIMER0 time-out or capture event #001 2 Internal TIMER1 time-out or capture event #010 3 Internal TIMER2 time-out or capture event #011 4 Internal TIMER3 time-out or capture event #100 TIMER0_PWMCMPBUF TIMER0_PWMCMPBUF Timer0 PWM Comparator Buffer Register 0xA4 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register. 0 16 read-only TIMER0_PWMCMPDAT TIMER0_PWMCMPDAT Timer0 PWM Comparator Register 0x54 read-write n 0x0 0x0 CMP PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 0 16 read-write TIMER0_PWMCNT TIMER0_PWMCNT Timer0 PWM Counter Register 0x5C read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only DIRF PWM Counter Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is active in down counting #0 1 Counter is active in up counting #1 TIMER0_PWMCNTCLR TIMER0_PWMCNTCLR Timer0 PWM Clear Counter Register 0x4C read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type #1 TIMER0_PWMCTL TIMER0_PWMCTL Timer0 PWM Control Register 0x40 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE PWM Counter Behavior Type 1 2 read-write 0 Up count type #00 1 Down count type #01 2 Up-down count type #10 3 Reserved. #11 CTRLD Center Re-load\nIn up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 8 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN Immediately Load Enable Bit\nNote: If IMMLDEN is enabled, CTRLD will be invalid. 9 1 read-write 0 PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period #0 1 PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP #1 OUTMODE PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel. 16 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 TIMER0_PWMDTCTL TIMER0_PWMDTCTL Timer0 PWM Dead-time Control Register 0x58 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from TMRx_PWMCLK without counter clock prescale #0 1 Dead-time clock source from TMRx_PWMCLK with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 TIMER0_PWMFAILBRK TIMER0_PWMFAILBRK Timer0 PWM System Fail Brake Control Register 0x6C read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by core lockup event Disabled #0 1 Brake Function triggered by core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 TIMER0_PWMINTEN0 TIMER0_PWMINTEN0 Timer0 PWM Interrupt Enable Register 0 0x80 read-write n 0x0 0x0 CMPDIEN PWM Compare Down Count Interrupt Enable Bit 3 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit\nNote: In up-down count type, period point means the center point of current PWM period. 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN PWM Zero Point Interrupt Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 TIMER0_PWMINTEN1 TIMER0_PWMINTEN1 Timer0 PWM Interrupt Enable Register 1 0x84 read-write n 0x0 0x0 BRKEIEN PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM edge-detect brake interrupt Disabled #0 1 PWM edge-detect brake interrupt Enabled #1 BRKLIEN PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM level-detect brake interrupt Disabled #0 1 PWM level-detect brake interrupt Enabled #1 TIMER0_PWMINTSTS0 TIMER0_PWMINTSTS0 Timer0 PWM Interrupt Status Register 0 0x88 read-write n 0x0 0x0 CMPDIF PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write CMPUIF PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type, PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write ZIF PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write TIMER0_PWMINTSTS1 TIMER0_PWMINTSTS1 Timer0 PWM Interrupt Status Register 1 0x8C read-write n 0x0 0x0 BRKEIF0 Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWMx_CH0 edge-detect brake event did not happen #0 1 PWMx_CH0 edge-detect brake event happened #1 BRKEIF1 Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWMx_CH1 edge-detect brake event did not happen #0 1 PWMx_CH1 edge-detect brake event happened #1 BRKESTS0 Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 16 1 read-only 0 PWMx_CH0 edge-detect brake state is released #0 1 PWMx_CH0 at edge-detect brake state #1 BRKESTS1 Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 17 1 read-only 0 PWMx_CH1 edge-detect brake state is released #0 1 PWMx_CH1 at edge-detect brake state #1 BRKLIF0 Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWMx_CH0 level-detect brake event did not happen #0 1 PWMx_CH0 level-detect brake event happened #1 BRKLIF1 Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWMx_CH1 level-detect brake event did not happen #0 1 PWMx_CH1 level-detect brake event happened #1 BRKLSTS0 Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 24 1 read-only 0 PWMx_CH0 level-detect brake state is released #0 1 PWMx_CH0 at level-detect brake state #1 BRKLSTS1 Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 25 1 read-only 0 PWMx_CH1 level-detect brake state is released #0 1 PWMx_CH1 at level-detect brake state #1 TIMER0_PWMMSK TIMER0_PWMMSK Timer0 PWM Output Mask Data Control Register 0x64 read-write n 0x0 0x0 MSKDAT0 PWMx_CH0 Output Mask Data Control Bit 0 1 read-write 0 Output logic Low to PWMx_CH0 #0 1 Output logic High to PWMx_CH0 #1 MSKDAT1 PWMx_CH1 Output Mask Data Control Bit 1 1 read-write 0 Output logic Low to PWMx_CH1 #0 1 Output logic High to PWMx_CH1 #1 TIMER0_PWMMSKEN TIMER0_PWMMSKEN Timer0 PWM Output Mask Enable Register 0x60 read-write n 0x0 0x0 MSKEN0 PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 0 1 read-write 0 PWMx_CH0 output signal is non-masked #0 1 PWMx_CH0 output signal is masked and output MSKDAT0 data #1 MSKEN1 PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 1 1 read-write 0 PWMx_CH1 output signal is non-masked #0 1 PWMx_CH1 output signal is masked and output MSKDAT1 data #1 TIMER0_PWMPBUF TIMER0_PWMPBUF Timer0 PWM Period Buffer Register 0xA0 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register. 0 16 read-only TIMER0_PWMPERIOD TIMER0_PWMPERIOD Timer0 PWM Period Register 0x50 read-write n 0x0 0x0 PERIOD PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\nIn up and down count type:\nNote: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 0 16 read-write TIMER0_PWMPOEN TIMER0_PWMPOEN Timer0 PWM Pin Output Enable Register 0x78 read-write n 0x0 0x0 POEN0 PWMx_CH0 Output Pin Enable Bit 0 1 read-write 0 PWMx_CH0 pin at tri-state mode #0 1 PWMx_CH0 pin in output mode #1 POEN1 PWMx_CH1 Output Pin Enable Bit 1 1 read-write 0 PWMx_CH1 pin at tri-state mode #0 1 PWMx_CH1 pin in output mode #1 TIMER0_PWMPOLCTL TIMER0_PWMPOLCTL Timer0 PWM Pin Output Polar Control Register 0x74 read-write n 0x0 0x0 PINV0 PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin. 0 1 read-write 0 PWMx_CH0 output pin polar inverse Disabled #0 1 PWMx_CH0 output pin polar inverse Enabled #1 PINV1 PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin. 1 1 read-write 0 PWMx_CH1 output pin polar inverse Disabled #0 1 PWMx_CH1 output pin polar inverse Enabled #1 TIMER0_PWMSCTL TIMER0_PWMSCTL Timer0 PWM Synchronous Control Register 0x94 read-write n 0x0 0x0 SYNCMODE PWM Synchronous Mode Enable Select 0 2 read-write 0 PWM synchronous function Disabled #00 1 PWM synchronous counter start function Enabled #01 2 Reserved. #10 3 PWM synchronous counter clear function Enabled #11 SYNCSRC PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8], TIME1_PWMSCTL[8], TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8] and TIME1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be set 1. 8 1 read-write 0 Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN #0 1 Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN #1 TIMER0_PWMSTATUS TIMER0_PWMSTATUS Timer0 PWM Status Register 0x9C read-write n 0x0 0x0 ADCTRGF Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger ADC start conversion has not occurred #0 1 PWM counter event trigger ADC start conversion has occurred #1 CNTMAXF PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 PWM counter value never reached its maximum value 0xFFFF #0 1 PWM counter value has reached its maximum value #1 TIMER0_PWMSTRG TIMER0_PWMSTRG Timer0 PWM Synchronous Trigger Register 0x98 write-only n 0x0 0x0 STRGEN PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\nNote: This bit is only available in TIMER0 and TIMER2. 0 1 write-only TIMER0_PWMSWBRK TIMER0_PWMSWBRK Timer0 PWM Software Trigger Brake Control Register 0x7C write-only n 0x0 0x0 BRKETRG Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKLTRG Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 write-only TIMER0_TRGCTL TIMER0_TRGCTL Timer0 Trigger Control Register 0x1C read-write n 0x0 0x0 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered ADC conversion. 2 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source. 1 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger PWM, PDMA, and ADC #0 1 Capture interrupt signal is used to internal trigger PWM, PDMA, and ADC #1 TIMER1_ALTCTL TIMER1_ALTCTL Timer1 Alternative Control Register 0x120 read-write n 0x0 0x0 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x110 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Comparator Register 0x104 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x10C read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control Register 0x100 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x118 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x114 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x108 read-write n 0x0 0x0 TIMER1_PWMADCTS TIMER1_PWMADCTS Timer1 PWM ADC Trigger Source Select Register 0x190 read-write n 0x0 0x0 TIMER1_PWMBNF TIMER1_PWMBNF Timer1 PWM Brake Pin Noise Filter Register 0x168 read-write n 0x0 0x0 TIMER1_PWMBRKCTL TIMER1_PWMBRKCTL Timer1 PWM Brake Control Register 0x170 read-write n 0x0 0x0 TIMER1_PWMCLKPSC TIMER1_PWMCLKPSC Timer1 PWM Counter Clock Pre-scale Register 0x148 read-write n 0x0 0x0 TIMER1_PWMCLKSRC TIMER1_PWMCLKSRC Timer1 PWM Counter Clock Source Register 0x144 read-write n 0x0 0x0 TIMER1_PWMCMPBUF TIMER1_PWMCMPBUF Timer1 PWM Comparator Buffer Register 0x1A4 read-write n 0x0 0x0 TIMER1_PWMCMPDAT TIMER1_PWMCMPDAT Timer1 PWM Comparator Register 0x154 read-write n 0x0 0x0 TIMER1_PWMCNT TIMER1_PWMCNT Timer1 PWM Counter Register 0x15C read-write n 0x0 0x0 TIMER1_PWMCNTCLR TIMER1_PWMCNTCLR Timer1 PWM Clear Counter Register 0x14C read-write n 0x0 0x0 TIMER1_PWMCTL TIMER1_PWMCTL Timer1 PWM Control Register 0x140 read-write n 0x0 0x0 TIMER1_PWMDTCTL TIMER1_PWMDTCTL Timer1 PWM Dead-time Control Register 0x158 read-write n 0x0 0x0 TIMER1_PWMFAILBRK TIMER1_PWMFAILBRK Timer1 PWM System Fail Brake Control Register 0x16C read-write n 0x0 0x0 TIMER1_PWMINTEN0 TIMER1_PWMINTEN0 Timer1 PWM Interrupt Enable Register 0 0x180 read-write n 0x0 0x0 TIMER1_PWMINTEN1 TIMER1_PWMINTEN1 Timer1 PWM Interrupt Enable Register 1 0x184 read-write n 0x0 0x0 TIMER1_PWMINTSTS0 TIMER1_PWMINTSTS0 Timer1 PWM Interrupt Status Register 0 0x188 read-write n 0x0 0x0 TIMER1_PWMINTSTS1 TIMER1_PWMINTSTS1 Timer1 PWM Interrupt Status Register 1 0x18C read-write n 0x0 0x0 TIMER1_PWMMSK TIMER1_PWMMSK Timer1 PWM Output Mask Data Control Register 0x164 read-write n 0x0 0x0 TIMER1_PWMMSKEN TIMER1_PWMMSKEN Timer1 PWM Output Mask Enable Register 0x160 read-write n 0x0 0x0 TIMER1_PWMPBUF TIMER1_PWMPBUF Timer1 PWM Period Buffer Register 0x1A0 read-write n 0x0 0x0 TIMER1_PWMPERIOD TIMER1_PWMPERIOD Timer1 PWM Period Register 0x150 read-write n 0x0 0x0 TIMER1_PWMPOEN TIMER1_PWMPOEN Timer1 PWM Pin Output Enable Register 0x178 read-write n 0x0 0x0 TIMER1_PWMPOLCTL TIMER1_PWMPOLCTL Timer1 PWM Pin Output Polar Control Register 0x174 read-write n 0x0 0x0 TIMER1_PWMSCTL TIMER1_PWMSCTL Timer1 PWM Synchronous Control Register 0x194 read-write n 0x0 0x0 TIMER1_PWMSTATUS TIMER1_PWMSTATUS Timer1 PWM Status Register 0x19C read-write n 0x0 0x0 TIMER1_PWMSWBRK TIMER1_PWMSWBRK Timer1 PWM Software Trigger Brake Control Register 0x17C read-write n 0x0 0x0 TIMER1_TRGCTL TIMER1_TRGCTL Timer1 Trigger Control Register 0x11C read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x140 0x58 registers n 0x19C 0xC registers n 0x40 0x68 registers n TIMER2_ALTCTL TIMER2_ALTCTL Timer2 Alternative Control Register 0x20 read-write n 0x0 0x0 FUNCSEL Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. 0 1 read-write 0 Timer controller is used as timer function #0 1 Timer controller is used as PWM function #1 TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Comparator Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC read-write n 0x0 0x0 CNT Timer Data Register\nRead operation:\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation:\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 0 24 read-write RSTACT Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically. 31 1 read-only 0 Reset operation is done #0 1 Reset operation triggered by writing TIMERx_CNT is in progress #1 TIMER2_CTL TIMER2_CTL Timer2 Control Register 0x0 -1 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAPSRC Capture Pin Source Selection 22 1 read-write 0 Capture Function source is from Tx_EXT (x= 0~3) pin #0 1 Capture Function source is from internal ACMP output signal. User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source #1 CNTEN Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not. 30 1 read-write 0 Stop/Suspend counting #0 1 Start counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer time-out interrupt Disabled #0 1 Timer time-out interrupt Enabled #1 INTRGEN Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PERIOSEL Periodic Mode Behavior Selection Enable Bit If the updated CMPDAT value CNT, CNT will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode Disabled #0 1 The behavior selection in periodic mode Enabled #1 PSC Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 0 8 read-write TGLPINSEL Toggle-output Pin Select 21 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 read-write n 0x0 0x0 ACMPSSEL ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. 8 1 read-write 0 Capture Function source is from internal ACMP0 output signal #0 1 Capture Function source is from internal ACMP1 output signal #1 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. 12 3 read-write 0 Capture event occurred when detect falling edge transfer on Tx_EXT (x= 0~3) pin #000 1 Capture event occurred when detect rising edge transfer on Tx_EXT (x= 0~3) pin #001 2 Capture event occurred when detect both falling and rising edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer #010 3 Capture event occurred when detect both rising and falling edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer #011 6 First capture event occurred at falling edge, follows capture events are at rising edge transfer on Tx_EXT (x= 0~3) pin #110 7 First capture event occurred at rising edge, follows capture events are at falling edge transfer on Tx_EXT (x= 0~3) pin #111 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function. 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A falling edge of external counting pin will be counted #0 1 A rising edge of external counting pin will be counted #1 ECNTSSEL Event Counter Source Selection to Trigger Event Counter Function 16 1 read-write 0 Event Counter input source is from Tx (x= 0~3) pin #0 1 Reserved. #1 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER2_PWMADCTS TIMER2_PWMADCTS Timer2 PWM ADC Trigger Source Select Register 0x90 read-write n 0x0 0x0 TRGEN PWM Counter Event Trigger ADC Conversion Enable Bit 7 1 read-write 0 PWM counter event trigger ADC conversion Disabled #0 1 PWM counter event trigger ADC conversion Enabled #1 TRGSEL PWM Counter Event Source Select to Trigger ADC Conversion 0 3 read-write 0 Trigger ADC conversion at zero point (ZIF) #000 1 Trigger ADC conversion at period point (PIF) #001 2 Trigger ADC conversion at zero or period point (ZIF or PIF) #010 3 Trigger ADC conversion at compare up count point (CMPUIF) #011 4 Trigger ADC conversion at compare down count point (CMPDIF) #100 TIMER2_PWMBNF TIMER2_PWMBNF Timer2 PWM Brake Pin Noise Filter Register 0x68 read-write n 0x0 0x0 BKPINSRC Brake Pin Source Select 16 2 read-write 0 Brake pin source comes from TM_BRAKE0 #00 1 Brake pin source comes from TM_BRAKE1 #01 2 Brake pin source comes from TM_BRAKE2 #10 3 Brake pin source comes from TM_BRAKE3 #11 BRKFCNT Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time. 4 3 read-write BRKNFEN Brake Pin Noise Filter Enable Bit 0 1 read-write 0 Pin noise filter detect of TM_BRAKEx Disabled #0 1 Pin noise filter detect of TM_BRAKEx Enabled #1 BRKNFSEL Brake Pin Noise Filter Clock Selection 1 3 read-write 0 Noise filter clock is PCLKx #000 1 Noise filter clock is PCLKx/2 #001 2 Noise filter clock is PCLKx/4 #010 3 Noise filter clock is PCLKx/8 #011 4 Noise filter clock is PCLKx/16 #100 5 Noise filter clock is PCLKx/32 #101 6 Noise filter clock is PCLKx/64 #110 7 Noise filter clock is PCLKx/128 #111 BRKPINV Brake Pin Detection Control Bit 7 1 read-write 0 Brake pin event will be detected if TM_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect #0 1 Brake pin event will be detected if TM_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect #1 TIMER2_PWMBRKCTL TIMER2_PWMBRKCTL Timer2 PWM Brake Control Register 0x70 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 TIMERx_PWM brake event will not affect PWMx_CH0 output #00 1 PWMx_CH0 output tri-state when TIMERx_PWM brake event happened #01 2 PWMx_CH0 output low level when TIMERx_PWM brake event happened #10 3 PWMx_CH0 output high level when TIMERx_PWM brake event happened #11 BRKAODD PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 TIMERx_PWM brake event will not affect PWMx_CH1 output #00 1 PWMx_CH1 output tri-state when TIMERx_PWM brake event happened #01 2 PWMx_CH1 output low level when TIMERx_PWM brake event happened #10 3 PWMx_CH1 output high level when TIMERx_PWM brake event happened #11 BRKPEEN Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 TM_BRAKEx pin event as edge-detect brake source Disabled #0 1 TM_BRAKEx pin event as edge-detect brake source Enabled #1 BRKPLEN Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 TM_BRAKEx pin event as level-detect brake source Disabled #0 1 TM_BRAKEx pin event as level-detect brake source Enabled #1 CPO0EBEN Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Internal ACMP0_O signal as edge-detect brake source Disabled #0 1 Internal ACMP0_O signal as edge-detect brake source Enabled #1 CPO0LBEN Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Internal ACMP0_O signal as level-detect brake source Disabled #0 1 Internal ACMP0_O signal as level-detect brake source Enabled #1 CPO1EBEN Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Internal ACMP1_O signal as edge-detect brake source Disabled #0 1 Internal ACMP1_O signal as edge-detect brake source Enabled #1 CPO1LBEN Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Internal ACMP1_O signal as level-detect brake source Disabled #0 1 Internal ACMP1_O signal as level-detect brake source Enabled #1 SYSEBEN Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System fail condition as edge-detect brake source Disabled #0 1 System fail condition as edge-detect brake source Enabled #1 SYSLBEN Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System fail condition as level-detect brake source Disabled #0 1 System fail condition as level-detect brake source Enabled #1 TIMER2_PWMCLKPSC TIMER2_PWMCLKPSC Timer2 PWM Counter Clock Pre-scale Register 0x48 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source. 0 12 read-write TIMER2_PWMCLKSRC TIMER2_PWMCLKSRC Timer2 PWM Counter Clock Source Register 0x44 read-write n 0x0 0x0 CLKSRC PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. 0 3 read-write 0 TMRx_CLK #000 1 Internal TIMER0 time-out or capture event #001 2 Internal TIMER1 time-out or capture event #010 3 Internal TIMER2 time-out or capture event #011 4 Internal TIMER3 time-out or capture event #100 TIMER2_PWMCMPBUF TIMER2_PWMCMPBUF Timer2 PWM Comparator Buffer Register 0xA4 read-only n 0x0 0x0 CMPBUF PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register. 0 16 read-only TIMER2_PWMCMPDAT TIMER2_PWMCMPDAT Timer2 PWM Comparator Register 0x54 read-write n 0x0 0x0 CMP PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. 0 16 read-write TIMER2_PWMCNT TIMER2_PWMCNT Timer2 PWM Counter Register 0x5C read-only n 0x0 0x0 CNT PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter. 0 16 read-only DIRF PWM Counter Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is active in down counting #0 1 Counter is active in up counting #1 TIMER2_PWMCNTCLR TIMER2_PWMCNTCLR Timer2 PWM Clear Counter Register 0x4C read-write n 0x0 0x0 CNTCLR Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type #1 TIMER2_PWMCTL TIMER2_PWMCTL Timer2 PWM Control Register 0x40 read-write n 0x0 0x0 CNTEN PWM Counter Enable Bit 0 1 read-write 0 PWM counter and clock prescale Stop Running #0 1 PWM counter and clock prescale Start Running #1 CNTMODE PWM Counter Mode 3 1 read-write 0 Auto-reload mode #0 1 One-shot mode #1 CNTTYPE PWM Counter Behavior Type 1 2 read-write 0 Up count type #00 1 Down count type #01 2 Up-down count type #10 3 Reserved. #11 CTRLD Center Re-load\nIn up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. 8 1 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement Disabled #1 IMMLDEN Immediately Load Enable Bit\nNote: If IMMLDEN is enabled, CTRLD will be invalid. 9 1 read-write 0 PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period #0 1 PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP #1 OUTMODE PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel. 16 1 read-write 0 PWM independent mode #0 1 PWM complementary mode #1 TIMER2_PWMDTCTL TIMER2_PWMDTCTL Timer2 PWM Dead-time Control Register 0x58 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 24 1 read-write 0 Dead-time clock source from TMRx_PWMCLK without counter clock prescale #0 1 Dead-time clock source from TMRx_PWMCLK with counter clock prescale #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion Disabled on the pin pair #0 1 Dead-time insertion Enabled on the pin pair #1 TIMER2_PWMFAILBRK TIMER2_PWMFAILBRK Timer2 PWM System Fail Brake Control Register 0x6C read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function Enable Bit 1 1 read-write 0 Brake Function triggered by BOD event Disabled #0 1 Brake Function triggered by BOD event Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function Enable Bit 3 1 read-write 0 Brake Function triggered by core lockup event Disabled #0 1 Brake Function triggered by core lockup event Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function Enable Bit 0 1 read-write 0 Brake Function triggered by clock fail detection Disabled #0 1 Brake Function triggered by clock fail detection Enabled #1 TIMER2_PWMINTEN0 TIMER2_PWMINTEN0 Timer2 PWM Interrupt Enable Register 0 0x80 read-write n 0x0 0x0 CMPDIEN PWM Compare Down Count Interrupt Enable Bit 3 1 read-write 0 Compare down count interrupt Disabled #0 1 Compare down count interrupt Enabled #1 CMPUIEN PWM Compare Up Count Interrupt Enable Bit 2 1 read-write 0 Compare up count interrupt Disabled #0 1 Compare up count interrupt Enabled #1 PIEN PWM Period Point Interrupt Enable Bit\nNote: In up-down count type, period point means the center point of current PWM period. 1 1 read-write 0 Period point interrupt Disabled #0 1 Period point interrupt Enabled #1 ZIEN PWM Zero Point Interrupt Enable Bit 0 1 read-write 0 Zero point interrupt Disabled #0 1 Zero point interrupt Enabled #1 TIMER2_PWMINTEN1 TIMER2_PWMINTEN1 Timer2 PWM Interrupt Enable Register 1 0x84 read-write n 0x0 0x0 BRKEIEN PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM edge-detect brake interrupt Disabled #0 1 PWM edge-detect brake interrupt Enabled #1 BRKLIEN PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM level-detect brake interrupt Disabled #0 1 PWM level-detect brake interrupt Enabled #1 TIMER2_PWMINTSTS0 TIMER2_PWMINTSTS0 Timer2 PWM Interrupt Status Register 0 0x88 read-write n 0x0 0x0 CMPDIF PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write CMPUIF PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is cleared by writing 1 to it. 2 1 read-write PIF PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type, PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it. 1 1 read-write ZIF PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write TIMER2_PWMINTSTS1 TIMER2_PWMINTSTS1 Timer2 PWM Interrupt Status Register 1 0x8C read-write n 0x0 0x0 BRKEIF0 Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWMx_CH0 edge-detect brake event did not happen #0 1 PWMx_CH0 edge-detect brake event happened #1 BRKEIF1 Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWMx_CH1 edge-detect brake event did not happen #0 1 PWMx_CH1 edge-detect brake event happened #1 BRKESTS0 Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. 16 1 read-only 0 PWMx_CH0 edge-detect brake state is released #0 1 PWMx_CH0 at edge-detect brake state #1 BRKESTS1 Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. 17 1 read-only 0 PWMx_CH1 edge-detect brake state is released #0 1 PWMx_CH1 at edge-detect brake state #1 BRKLIF0 Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWMx_CH0 level-detect brake event did not happen #0 1 PWMx_CH0 level-detect brake event happened #1 BRKLIF1 Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWMx_CH1 level-detect brake event did not happen #0 1 PWMx_CH1 level-detect brake event happened #1 BRKLSTS0 Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 24 1 read-only 0 PWMx_CH0 level-detect brake state is released #0 1 PWMx_CH0 at level-detect brake state #1 BRKLSTS1 Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. 25 1 read-only 0 PWMx_CH1 level-detect brake state is released #0 1 PWMx_CH1 at level-detect brake state #1 TIMER2_PWMMSK TIMER2_PWMMSK Timer2 PWM Output Mask Data Control Register 0x64 read-write n 0x0 0x0 MSKDAT0 PWMx_CH0 Output Mask Data Control Bit 0 1 read-write 0 Output logic Low to PWMx_CH0 #0 1 Output logic High to PWMx_CH0 #1 MSKDAT1 PWMx_CH1 Output Mask Data Control Bit 1 1 read-write 0 Output logic Low to PWMx_CH1 #0 1 Output logic High to PWMx_CH1 #1 TIMER2_PWMMSKEN TIMER2_PWMMSKEN Timer2 PWM Output Mask Enable Register 0x60 read-write n 0x0 0x0 MSKEN0 PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. 0 1 read-write 0 PWMx_CH0 output signal is non-masked #0 1 PWMx_CH0 output signal is masked and output MSKDAT0 data #1 MSKEN1 PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. 1 1 read-write 0 PWMx_CH1 output signal is non-masked #0 1 PWMx_CH1 output signal is masked and output MSKDAT1 data #1 TIMER2_PWMPBUF TIMER2_PWMPBUF Timer2 PWM Period Buffer Register 0xA0 read-only n 0x0 0x0 PBUF PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register. 0 16 read-only TIMER2_PWMPERIOD TIMER2_PWMPERIOD Timer2 PWM Period Register 0x50 read-write n 0x0 0x0 PERIOD PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\nIn up and down count type:\nNote: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. 0 16 read-write TIMER2_PWMPOEN TIMER2_PWMPOEN Timer2 PWM Pin Output Enable Register 0x78 read-write n 0x0 0x0 POEN0 PWMx_CH0 Output Pin Enable Bit 0 1 read-write 0 PWMx_CH0 pin at tri-state mode #0 1 PWMx_CH0 pin in output mode #1 POEN1 PWMx_CH1 Output Pin Enable Bit 1 1 read-write 0 PWMx_CH1 pin at tri-state mode #0 1 PWMx_CH1 pin in output mode #1 TIMER2_PWMPOLCTL TIMER2_PWMPOLCTL Timer2 PWM Pin Output Polar Control Register 0x74 read-write n 0x0 0x0 PINV0 PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin. 0 1 read-write 0 PWMx_CH0 output pin polar inverse Disabled #0 1 PWMx_CH0 output pin polar inverse Enabled #1 PINV1 PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin. 1 1 read-write 0 PWMx_CH1 output pin polar inverse Disabled #0 1 PWMx_CH1 output pin polar inverse Enabled #1 TIMER2_PWMSCTL TIMER2_PWMSCTL Timer2 PWM Synchronous Control Register 0x94 read-write n 0x0 0x0 SYNCMODE PWM Synchronous Mode Enable Select 0 2 read-write 0 PWM synchronous function Disabled #00 1 PWM synchronous counter start function Enabled #01 2 Reserved. #10 3 PWM synchronous counter clear function Enabled #11 SYNCSRC PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8], TIME1_PWMSCTL[8], TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8] and TIME1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be set 1. 8 1 read-write 0 Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN #0 1 Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN #1 TIMER2_PWMSTATUS TIMER2_PWMSTATUS Timer2 PWM Status Register 0x9C read-write n 0x0 0x0 ADCTRGF Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it. 16 1 read-write 0 PWM counter event trigger ADC start conversion has not occurred #0 1 PWM counter event trigger ADC start conversion has occurred #1 CNTMAXF PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 PWM counter value never reached its maximum value 0xFFFF #0 1 PWM counter value has reached its maximum value #1 TIMER2_PWMSTRG TIMER2_PWMSTRG Timer2 PWM Synchronous Trigger Register 0x98 write-only n 0x0 0x0 STRGEN PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\nNote: This bit is only available in TIMER0 and TIMER2. 0 1 write-only TIMER2_PWMSWBRK TIMER2_PWMSWBRK Timer2 PWM Software Trigger Brake Control Register 0x7C write-only n 0x0 0x0 BRKETRG Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 write-only BRKLTRG Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 write-only TIMER2_TRGCTL TIMER2_TRGCTL Timer2 Trigger Control Register 0x1C read-write n 0x0 0x0 TRGADC Trigger ADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered ADC conversion. 2 1 read-write 0 Timer interrupt trigger ADC Disabled #0 1 Timer interrupt trigger ADC Enabled #1 TRGPDMA Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. 4 1 read-write 0 Timer interrupt trigger PDMA Disabled #0 1 Timer interrupt trigger PDMA Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source. 1 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. 0 1 read-write 0 Time-out interrupt signal is used to internal trigger PWM, PDMA, and ADC #0 1 Capture interrupt signal is used to internal trigger PWM, PDMA, and ADC #1 TIMER3_ALTCTL TIMER3_ALTCTL Timer3 Alternative Control Register 0x120 read-write n 0x0 0x0 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x110 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Comparator Register 0x104 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x10C read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control Register 0x100 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x118 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x114 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x108 read-write n 0x0 0x0 TIMER3_PWMADCTS TIMER3_PWMADCTS Timer3 PWM ADC Trigger Source Select Register 0x190 read-write n 0x0 0x0 TIMER3_PWMBNF TIMER3_PWMBNF Timer3 PWM Brake Pin Noise Filter Register 0x168 read-write n 0x0 0x0 TIMER3_PWMBRKCTL TIMER3_PWMBRKCTL Timer3 PWM Brake Control Register 0x170 read-write n 0x0 0x0 TIMER3_PWMCLKPSC TIMER3_PWMCLKPSC Timer3 PWM Counter Clock Pre-scale Register 0x148 read-write n 0x0 0x0 TIMER3_PWMCLKSRC TIMER3_PWMCLKSRC Timer3 PWM Counter Clock Source Register 0x144 read-write n 0x0 0x0 TIMER3_PWMCMPBUF TIMER3_PWMCMPBUF Timer3 PWM Comparator Buffer Register 0x1A4 read-write n 0x0 0x0 TIMER3_PWMCMPDAT TIMER3_PWMCMPDAT Timer3 PWM Comparator Register 0x154 read-write n 0x0 0x0 TIMER3_PWMCNT TIMER3_PWMCNT Timer3 PWM Counter Register 0x15C read-write n 0x0 0x0 TIMER3_PWMCNTCLR TIMER3_PWMCNTCLR Timer3 PWM Clear Counter Register 0x14C read-write n 0x0 0x0 TIMER3_PWMCTL TIMER3_PWMCTL Timer3 PWM Control Register 0x140 read-write n 0x0 0x0 TIMER3_PWMDTCTL TIMER3_PWMDTCTL Timer3 PWM Dead-time Control Register 0x158 read-write n 0x0 0x0 TIMER3_PWMFAILBRK TIMER3_PWMFAILBRK Timer3 PWM System Fail Brake Control Register 0x16C read-write n 0x0 0x0 TIMER3_PWMINTEN0 TIMER3_PWMINTEN0 Timer3 PWM Interrupt Enable Register 0 0x180 read-write n 0x0 0x0 TIMER3_PWMINTEN1 TIMER3_PWMINTEN1 Timer3 PWM Interrupt Enable Register 1 0x184 read-write n 0x0 0x0 TIMER3_PWMINTSTS0 TIMER3_PWMINTSTS0 Timer3 PWM Interrupt Status Register 0 0x188 read-write n 0x0 0x0 TIMER3_PWMINTSTS1 TIMER3_PWMINTSTS1 Timer3 PWM Interrupt Status Register 1 0x18C read-write n 0x0 0x0 TIMER3_PWMMSK TIMER3_PWMMSK Timer3 PWM Output Mask Data Control Register 0x164 read-write n 0x0 0x0 TIMER3_PWMMSKEN TIMER3_PWMMSKEN Timer3 PWM Output Mask Enable Register 0x160 read-write n 0x0 0x0 TIMER3_PWMPBUF TIMER3_PWMPBUF Timer3 PWM Period Buffer Register 0x1A0 read-write n 0x0 0x0 TIMER3_PWMPERIOD TIMER3_PWMPERIOD Timer3 PWM Period Register 0x150 read-write n 0x0 0x0 TIMER3_PWMPOEN TIMER3_PWMPOEN Timer3 PWM Pin Output Enable Register 0x178 read-write n 0x0 0x0 TIMER3_PWMPOLCTL TIMER3_PWMPOLCTL Timer3 PWM Pin Output Polar Control Register 0x174 read-write n 0x0 0x0 TIMER3_PWMSCTL TIMER3_PWMSCTL Timer3 PWM Synchronous Control Register 0x194 read-write n 0x0 0x0 TIMER3_PWMSTATUS TIMER3_PWMSTATUS Timer3 PWM Status Register 0x19C read-write n 0x0 0x0 TIMER3_PWMSWBRK TIMER3_PWMSWBRK Timer3 PWM Software Trigger Brake Control Register 0x17C read-write n 0x0 0x0 TIMER3_TRGCTL TIMER3_TRGCTL Timer3 Trigger Control Register 0x11C read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.2244. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.2244.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. \nNote: The detail description is shown in Table 6.2244. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.2244. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Imcoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-only 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)). 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register (Only for UART0 and UART1) 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register (Only for UART0 and UART1) 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATEN Incoming Data Wake-up Enable Bit 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up #1 UART1 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.2244. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.2244.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. \nNote: The detail description is shown in Table 6.2244. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.2244. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Imcoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-only 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)). 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register (Only for UART0 and UART1) 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register (Only for UART0 and UART1) 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATEN Incoming Data Wake-up Enable Bit 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up #1 UART2 UART Register Map UART 0x0 0x0 0x4C registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C -1 read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only 0 No auto-baud rate interrupt flag is generated #0 1 Auto-baud rate interrupt flag is generated #1 ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write BRKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1. 0 4 read-write LINRXEN LIN RX Enable Bit 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LINTXEN LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break mode Disabled #0 1 LIN TX Break mode Enabled #1 RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divider Register 0x24 -1 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.223. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.223.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. \nNote: The detail description is shown in Table 6.223. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.223. 24 4 read-write UART_BRCOMP UART_BRCOMP UART Baud Rate Compensation Register 0x3C read-write n 0x0 0x0 BRCOMP Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. 0 9 read-write BRCOMPDEC Baud Rate Compensation Decrease 31 1 read-write 0 Positive (increase one module clock) compensation for each compensated bit #0 1 Negative (decrease one module clock) compensation for each compensated bit #1 UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO. 0 8 read-write PARITY Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. 8 1 read-write UART_DWKCOMP UART_DWKCOMP UART Imcoming Data Wake-up Compensation Register 0x48 read-write n 0x0 0x0 STCOMP Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set. 0 16 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXIDLE RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle. 29 1 read-only 0 RX is busy #0 1 RX is idle. (Default) #1 RXOVIF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only TXRXACT TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set. 31 1 read-only 0 TX and RX are inactive #0 1 TX and RX are active. (Default) #1 UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 LIN function #01 2 IrDA function #10 3 RS-485 function #11 TXRXDIS TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. 3 1 read-write 0 TX and RX Enabled #0 1 TX and RX Disabled #1 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 LINIEN LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus interrupt Disabled #0 1 LIN bus interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. 15 1 read-write 0 RX PDMA Disabled #0 1 RX PDMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empty interrupt Enabled #1 TOCNTEN Receive Buffer Time-out Counter Enable Bit 11 1 read-write 0 Receive Buffer Time-out counter Disabled #0 1 Receive Buffer Time-out counter Enabled #1 TXENDIEN Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). 22 1 read-write 0 Transmitter empty interrupt Disabled #0 1 Transmitter empty interrupt Enabled #1 TXPDMAEN TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service. 14 1 read-write 0 TX PDMA Disabled #0 1 TX PDMA Enabled #1 WKIEN Wake-up Interrupt Enable Bit 6 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 ABRINT Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. 31 1 read-only 0 No Auto-baud Rate interrupt is generated #0 1 The Auto-baud Rate interrupt is generated #1 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 HWBUFEIF PDMA Mode Buffer Error Interrupt Flag (Read Only) This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated in PDMA mode #0 1 Buffer error interrupt flag is generated in PDMA mode #1 HWBUFEINT PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in PDMA mode #0 1 Buffer error interrupt is generated in PDMA mode #1 HWMODIF PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). 19 1 read-only 0 No Modem interrupt flag is generated in PDMA mode #0 1 Modem interrupt flag is generated in PDMA mode #1 HWMODINT PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in PDMA mode #0 1 Modem interrupt is generated in PDMA mode #1 HWRLSIF PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated in PDMA mode #0 1 RLS interrupt flag is generated in PDMA mode #1 HWRLSINT PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in PDMA mode #0 1 RLS interrupt is generated in PDMA mode #1 HWTOIF PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No RX time-out interrupt flag is generated in PDMA mode #0 1 RX time-out interrupt flag is generated in PDMA mode #1 HWTOINT PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No RX time-out interrupt is generated in PDMA mode #0 1 RX time-out interrupt is generated in PDMA mode #1 LINIF LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). 7 1 read-write 0 None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #0 1 At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated #1 LININT LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. 15 1 read-only 0 No LIN Bus interrupt is generated #0 1 The LIN Bus interrupt is generated #1 MODEMIF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No RX time-out interrupt flag is generated #0 1 RX time-out interrupt flag is generated #1 RXTOINT RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No RX time-out interrupt is generated #0 1 RX time-out interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TXENDIF Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 22 1 read-only 0 No transmitter empty interrupt flag is generated #0 1 Transmitter empty interrupt flag is generated #1 TXENDINT Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. 30 1 read-only 0 No Transmitter Empty interrupt is generated #0 1 Transmitter Empty interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 6 1 read-only 0 No UART wake-up interrupt flag is generated #0 1 UART wake-up interrupt flag is generated #1 WKINT UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. 14 1 read-only 0 No UART wake-up interrupt is generated #0 1 UART wake-up interrupt is generated #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode, the BAUDM1 (UART_BAUD [29]) register must be disabled, the baud equation must be Clock / (16 * (BRD + 2)). 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINCTL UART_LINCTL UART LIN Control Register (Only for UART0 and UART1) 0x34 -1 read-write n 0x0 0x0 BITERREN Bit Error Detect Enable Bit 12 1 read-write 0 Bit error detection function Disabled #0 1 Bit error detection function Enabled #1 BRKDETEN LIN Break Detection Enable Bit 10 1 read-write 0 LIN break detection Disabled #0 1 LIN break detection Enabled #1 BRKFL LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1. 16 4 read-write BSL LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field. 20 2 read-write 0 The LIN break/sync delimiter length is 1-bit time #00 1 The LIN break/sync delimiter length is 2-bit time #01 2 The LIN break/sync delimiter length is 3-bit time #10 3 The LIN break/sync delimiter length is 4-bit time #11 HSEL LIN Header Select 22 2 read-write 0 The LIN header includes 'break field' #00 1 The LIN header includes 'break field' and 'sync field' #01 2 The LIN header includes 'break field', 'sync field' and 'frame ID field' #10 3 Reserved. #11 IDPEN LIN ID Parity Enable Bit 9 1 read-write 0 LIN frame ID parity Disabled #0 1 LIN frame ID parity Enabled #1 LINRXOFF LIN Receiver Disable Bit 11 1 read-write 0 LIN receiver Enabled #0 1 LIN receiver Disabled #1 MUTE LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode). 4 1 read-write 0 LIN mute mode Disabled #0 1 LIN mute mode Enabled #1 PID LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode. 24 8 read-write SENDH LIN TX Send Header Enable Bit The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. 8 1 read-write 0 Send LIN TX header Disabled #0 1 Send LIN TX header Enabled #1 SLVAREN LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 2 1 read-write 0 LIN automatic resynchronization Disabled #0 1 LIN automatic resynchronization Enabled #1 SLVDUEN LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.22.5.10 (Slave mode with automatic resynchronization). 3 1 read-write 0 UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time) #0 1 UART_BAUD is updated at the next received character. User must set the bit before checksum reception #1 SLVEN LIN Slave Mode Enable Bit 0 1 read-write 0 LIN slave mode Disabled #0 1 LIN slave mode Enabled #1 SLVHDEN LIN Slave Header Detection Enable Bit 1 1 read-write 0 LIN slave header detection Disabled #0 1 LIN slave header detection Enabled #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 Parity bit generated Disabled #0 1 Parity bit generated Enabled #1 PSS Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the parity bit is transmitted and checked automatically. If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). 7 1 read-write 0 Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically #0 1 Parity bit generated and checked by software #1 RXDINV RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 9 1 read-write 0 Received data signal inverted Disabled #0 1 Received data signal inverted Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 TXDINV TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. 8 1 read-write 0 Transmitted data signal inverted Disabled #0 1 Transmitted data signal inverted Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_LINSTS UART_LINSTS UART LIN Status Register (Only for UART0 and UART1) 0x38 read-write n 0x0 0x0 BITEF Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. 9 1 read-write 0 Bit error not detected #0 1 Bit error detected #1 BRKDETF LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. 8 1 read-write 0 LIN break not detected #0 1 LIN break detected #1 SLVHDETF LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. 0 1 read-write 0 LIN header not detected #0 1 LIN header detected (break + sync + frame ID) #1 SLVHEF LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. 1 1 read-write 0 LIN header error not detected #0 1 LIN header error detected #1 SLVIDPEF LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct. 2 1 read-write 0 No active #0 1 Receipted frame ID parity is not correct #1 SLVSYNCF LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. 3 1 read-write 0 The current character is not at LIN sync state #0 1 The current character is at LIN sync state #1 UART_MODEM UART_MODEM UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 9 1 read-write 0 nRTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it. 0 1 read-write 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART_WKCTL UART_WKCTL UART Wake-up Control Register 0x40 read-write n 0x0 0x0 WKCTSEN nCTS Wake-up Enable Bit 0 1 read-write 0 nCTS Wake-up system function Disabled #0 1 nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATEN Incoming Data Wake-up Enable Bit 1 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 WKRFRTEN Received Data FIFO Reached Threshold Wake-up Enable Bit 2 1 read-write 0 Received Data FIFO reached threshold wake-up system function Disabled #0 1 Received Data FIFO reached threshold wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode #1 WKRS485EN RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1. 3 1 read-write 0 RS-485 Address Match (AAD mode) wake-up system function Disabled #0 1 RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode #1 WKTOUTEN Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. 4 1 read-write 0 Received Data FIFO reached threshold time-out wake-up system function Disabled #0 1 Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode #1 UART_WKSTS UART_WKSTS UART Wake-up Status Register 0x44 read-write n 0x0 0x0 CTSWKF nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 0 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKF Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 1 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Incoming Data wake-up #1 RFRTWKF Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 2 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up #1 RS485WKF RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 3 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up #1 TOUTWKF Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it. 4 1 read-write 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up #1 UI2C0 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: When I2C operating in 7-bit address mode, only use DEVADDR[6:0] 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 Monitor mode Disabled #0 1 Monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN Start Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a start condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN Stop Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a stop condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nIt is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 ERRARBLO Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag\nIt is cleared by software writing 1 into this bit\nNote: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: This bit is cleared by software writing 1 to it. 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote1: In I2C protocol, only use RXDAT[7:0].. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode. 6 6 read-write STCTL Setup Time Configure Control\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 8-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UI2C1 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: When I2C operating in 7-bit address mode, only use DEVADDR[6:0] 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function Disabled #0 1 Address match 10 bit function Enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 Monitor mode Disabled #0 1 Monitor mode Enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol Disabled #0 1 I2C Protocol Enabled #1 PTRG I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt Disabled #0 1 The acknowledge interrupt Enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt Disabled #0 1 The arbitration lost interrupt Enabled #1 ERRIEN Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt Disabled #0 1 The error interrupt Enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt Disabled #0 1 The non - acknowledge interrupt Enabled #1 STARIEN Start Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a start condition is detected. 1 1 read-write 0 The start condition interrupt Disabled #0 1 The start condition interrupt Enabled #1 STORIEN Stop Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a stop condition is detected. 2 1 read-write 0 The stop condition interrupt Disabled #0 1 The stop condition interrupt Enabled #1 TOIEN Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt Disabled #0 1 The time-out interrupt Enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nIt is cleared by software writing 1 into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 ERRARBLO Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag\nIt is cleared by software writing 1 into this bit\nNote: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: This bit is cleared by software writing 1 to it. 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote1: In I2C protocol, only use RXDAT[7:0].. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode. 6 6 read-write STCTL Setup Time Configure Control\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 8-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UI2C2 UI2C Register Map UI2C 0x0 0x0 0x4 registers n 0x2C 0xC registers n 0x44 0x24 registers n 0x8 0x4 registers n 0x88 0x8 registers n UI2C_ADDRMSK0 UI2C_ADDRMSK0 USCI Device Address Mask Register 0 0x4C read-write n 0x0 0x0 ADDRMSK USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 0 10 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 UI2C_ADDRMSK1 UI2C_ADDRMSK1 USCI Device Address Mask Register 1 0x50 read-write n 0x0 0x0 UI2C_ADMAT UI2C_ADMAT I2C Slave Match Address Register 0x88 read-write n 0x0 0x0 ADMAT0 USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 0 1 read-write ADMAT1 USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit. 1 1 read-write UI2C_BRGEN UI2C_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 UI2C_CTL UI2C_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UI2C_DEVADDR0 UI2C_DEVADDR0 USCI Device Address Register 0 0x44 read-write n 0x0 0x0 DEVADDR Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: When I2C operating in 7-bit address mode, only use DEVADDR[6:0] 0 10 read-write UI2C_DEVADDR1 UI2C_DEVADDR1 USCI Device Address Register 1 0x48 read-write n 0x0 0x0 UI2C_LINECTL UI2C_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In I2C protocol, the length must be configured as 8 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UI2C_PROTCTL UI2C_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 AA Assert Acknowledge Control 1 1 read-write ADDR10EN Address 10-bit Function Enable Bit 4 1 read-write 0 Address match 10 bit function is disabled #0 1 Address match 10 bit function is enabled #1 GCFUNC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 MONEN Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 9 1 read-write 0 The monitor mode is disabled #0 1 The monitor mode is enabled #1 PROTEN I2C Protocol Enable Bit 31 1 read-write 0 I2C Protocol disable #0 1 I2C Protocol enable #1 PTRG I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 5 1 read-write 0 I2C's stretch disabled and the I2C protocol function will go ahead #0 1 I2C's stretch active #1 SCLOUTEN SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 8 1 read-write 0 SCL output will be forced high due to open drain mechanism #0 1 I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt #1 STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 3 1 read-write STO I2C STOP Control 2 1 read-write TOCNT Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 16 10 read-write UI2C_PROTIEN UI2C_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ACKIEN Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 6 1 read-write 0 The acknowledge interrupt is disabled #0 1 The acknowledge interrupt is enabled #1 ARBLOIEN Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 4 1 read-write 0 The arbitration lost interrupt is disabled #0 1 The arbitration lost interrupt is enabled #1 ERRIEN Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 5 1 read-write 0 The error interrupt is disabled #0 1 The error interrupt is enabled #1 NACKIEN Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 3 1 read-write 0 The non - acknowledge interrupt is disabled #0 1 The non - acknowledge interrupt is enabled #1 STARIEN Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected. 1 1 read-write 0 The start condition interrupt is disabled #0 1 The start condition interrupt is enabled #1 STORIEN Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected. 2 1 read-write 0 The stop condition interrupt is disabled #0 1 The stop condition interrupt is enabled #1 TOIEN Time-out Interrupt Enable Control\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event. 0 1 read-write 0 The time-out interrupt is disabled #0 1 The time-out interrupt is enabled #1 UI2C_PROTSTS UI2C_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ACKIF Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit 13 1 read-write 0 An acknowledge has not been received #0 1 An acknowledge has been received #1 ARBLOIF Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit 11 1 read-write 0 An arbitration has not been lost #0 1 An arbitration has been lost #1 BUSHANG Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 18 1 read-write 0 The bus is normal status for transmission #0 1 The bus is hang-up status for transmission #1 ERRARBLO Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 19 1 read-write 0 The bus is normal status for transmission #0 1 The bus is error arbitration lost status for transmission #1 ERRIF Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode. 12 1 read-write 0 An I2C error has not been detected #0 1 An I2C error has been detected #1 NACKIF Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit 10 1 read-write 0 A non - acknowledge has not been received #0 1 A non - acknowledge has been received #1 ONBUSY On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 6 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 SLAREAD Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 15 1 read-write 0 A slave read request has not been detected #0 1 A slave read request has been detected #1 SLASEL Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware. 14 1 read-write 0 The device is not selected as slave #0 1 The device is selected as slave #1 STARIF Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nIt is cleared by software writing one into this bit 8 1 read-write 0 A start condition has not yet been detected #0 1 A start condition has been detected #1 STORIF Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit 9 1 read-write 0 A stop condition has not yet been detected #0 1 A stop condition has been detected #1 TOIF Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit 5 1 read-write 0 A time-out interrupt status has not occurred #0 1 A time-out interrupt status has occurred #1 WKAKDONE Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set. 16 1 read-write 0 The ACK bit cycle of address match frame isn't done #0 1 The ACK bit cycle of address match frame is done in power-down #1 WRSTSWK Read/Write Status Bit in Address Wakeup Frame 17 1 read-write 0 Write command be record on the address match wakeup frame #0 1 Read command be record on the address match wakeup frame #1 UI2C_RXDAT UI2C_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol, only use RXDAT[7:0].. 0 16 read-only UI2C_TMCTL UI2C_TMCTL I2C Timing Configure Control Register 0x8C read-write n 0x0 0x0 HTCTL Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode. 6 6 read-write STCTL Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 0 6 read-write UI2C_TXDAT UI2C_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UI2C_WKCTL UI2C_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UI2C_WKSTS UI2C_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI0 USPI Register Map USPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: I2C function, the minimum value of CLKDIV is 8. 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-only 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under-run event occurs #0 1 The output data level is 1 if TX under-run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 4 1 read-write 0 Receive end event does not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. 6 1 read-write 0 Slave bit count error event does not occur #0 1 Slave bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: This bit is cleared by software writing 1 to it. 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI1 USPI Register Map USPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: I2C function, the minimum value of CLKDIV is 8. 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter Disabled #0 1 Time measurement counter Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-only 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under-run event occurs #0 1 The output data level is 1 if TX under-run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 4 1 read-write 0 Receive end event does not occur #0 1 Receive end event occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 3 1 read-write 0 Receive start event did not occur #0 1 Receive start event occurred #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. 6 1 read-write 0 Slave bit count error event does not occur #0 1 Slave bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: This bit is cleared by software writing 1 to it. 5 1 read-write 0 Slave time-out event did not occur #0 1 Slave time-out event occurred #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 2 1 read-write 0 Transmit end event did not occur #0 1 Transmit end event occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it. 1 1 read-write 0 Transmit start event did not occur #0 1 Transmit start event occurred #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write USPI2 USPI Register Map USPI 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n USPI_BRGEN USPI_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: I2C function, the minimum value of CLKDIV is 8. 16 10 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fDIV_CLK #00 1 fPROT_CLK #01 2 fSCLK #10 3 fREF_CLK #11 TMCNTEN Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Time measurement counter is Disabled #0 1 Time measurement counter is Enabled #1 TMCNTSRC Time Measurement Counter Clock Source Selection 5 1 read-write 0 Time measurement counter with fPROT_CLK #0 1 Time measurement counter with fDIV_CLK #1 USPI_BUFCTL USPI_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Interrupt Enable Control 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote: It is cleared automatically after one PCLK cycle. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 TXUDRIEN Slave Transmit Under-run Interrupt Enable Bit 6 1 read-write 0 Transmit under-run interrupt Disabled #0 1 Transmit under-run interrupt Enabled #1 USPI_BUFSTS USPI_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun event has not been detected #0 1 A receive buffer overrun event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty and available for the next transmission datum #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 TXUDRIF Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit 11 1 read-only 0 A transmit buffer under-run event has not been detected #0 1 A transmit buffer under-run event has been detected #1 USPI_CLKIN USPI_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_CTL USPI_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 USPI_CTLIN0 USPI_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_DATIN0 USPI_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, we suggest this bit should be set as 0. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol, we suggest this bit should be set as 0. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 USPI_INTEN USPI_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 USPI_LINECTL USPI_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. 5 1 read-write 0 Data output level is not inverted #0 1 Data output level is inverted #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0]. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 USPI_PROTCTL USPI_PROTCTL USCI Protocol Control Register 0x5C -1 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only) 3 1 read-write 0 Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit #0 1 Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished #1 PROTEN SPI Protocol Enable Bit 31 1 read-write 0 SPI Protocol Disabled #0 1 SPI Protocol Enabled #1 SCLKMODE Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge. 6 2 read-write SLAVE Slave Mode Selection 0 1 read-write 0 Master mode #0 1 Slave mode #1 SLV3WIRE Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. 1 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVTOCNT Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. 16 10 read-write SS Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high. 2 1 read-write SUSPITV Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle\nExample: 8 4 read-write TSMSEL Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. 12 3 read-write TXUDRPOL Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. 28 1 read-write 0 The output data level is 0 if TX under-run event occurs #0 1 The output data level is 1 if TX under-run event occurs #1 USPI_PROTIEN USPI_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Control\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs. 3 1 read-write 0 The Slave mode bit count error interrupt Disabled #0 1 The Slave mode bit count error interrupt Enabled #1 SLVTOIEN Slave Time-out Interrupt Enable Control\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. 2 1 read-write 0 The Slave time-out interrupt Disabled #0 1 The Slave time-out interrupt Enabled #1 SSACTIEN Slave Select Active Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active. 1 1 read-write 0 Slave select active interrupt generation Disabled #0 1 Slave select active interrupt generation Enabled #1 SSINAIEN Slave Select Inactive Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. 0 1 read-write 0 Slave select inactive interrupt generation Disabled #0 1 Slave select inactive interrupt generation Enabled #1 USPI_PROTSTS USPI_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 17 1 read-only 0 SPI is in idle state #0 1 SPI is in busy state #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 4 1 read-write 0 Receive end event does not occur #0 1 Receive end event occurs #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 3 1 read-write 0 Receive start event does not occur #0 1 Receive start event occurs #1 SLVBEIF Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit. 6 1 read-write 0 Slave bit count error event does not occur #0 1 Slave bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit 5 1 read-write 0 Slave time-out event does not occur #0 1 Slave time-out event occurs #1 SLVUDR Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. 18 1 read-only 0 Slave transmit under-run event does not occur #0 1 Slave transmit under-run event occurs #1 SSACTIF Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high. 9 1 read-write 0 The slave select signal has not changed to active #0 1 The slave select signal has changed to active #1 SSINAIF Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high. 8 1 read-write 0 The slave select signal has not changed to inactive #0 1 The slave select signal has changed to inactive #1 SSLINE Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus. 16 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 2 1 read-write 0 Transmit end event does not occur #0 1 Transmit end event occurs #1 TXSTIF Transmit Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit 1 1 read-write 0 Transmit start event does not occur #0 1 Transmit start event occurs #1 USPI_RXDAT USPI_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer. 0 16 read-only USPI_TXDAT USPI_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 PORTDIR Port Direction Control 16 1 write-only 0 The data pin is configured as output mode #0 1 The data pin is configured as input mode #1 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. 0 16 write-only USPI_WKCTL USPI_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKADDREN Wake-up Address Match Enable Bit 1 1 read-write 0 The chip is woken up according data toggle #0 1 The chip is woken up according address match #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 USPI_WKSTS USPI_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART0 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter Disabled #0 1 Timing measurement counter Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART will reassert nRTS signal.\nNote1: This bit is used for nRTS auto direction control for RS485.\nNote2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detail information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote1: This bit is set at the same time of ABRDETIF.\nNote2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit is used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit is used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.\nNote2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART1 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter Disabled #0 1 Timing measurement counter Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Bit 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt Disabled #0 1 The receive end interrupt Enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt Disabled #0 1 The receive start interrupt Enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt Disabled #0 1 The transmit finish interrupt Enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt Disabled #0 1 The transmit start interrupt Enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART will reassert nRTS signal.\nNote1: This bit is used for nRTS auto direction control for RS485.\nNote2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detail information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote1: This bit is set at the same time of ABRDETIF.\nNote2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit is used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit is used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.\nNote2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write UUART2 UUART Register Map UUART 0x0 0x0 0xC registers n 0x10 0x4 registers n 0x20 0x4 registers n 0x28 0x18 registers n 0x54 0x14 registers n UUART_BRGEN UUART_BRGEN USCI Baud Rate Generator Register 0x8 -1 read-write n 0x0 0x0 CLKDIV Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. 16 10 read-write DSCNT Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. 10 5 read-write PDSCNT Pre-divider for Sample Counter 8 2 read-write PTCLKSEL Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). 1 1 read-write 0 Reference clock fREF_CLK #0 1 fREF_CLK2 (its frequency is half of fREF_CLK) #1 RCLKSEL Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). 0 1 read-write 0 Peripheral device clock fPCLK #0 1 Reserved. #1 SPCLKSEL Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 2 2 read-write 0 fSAMP_CLK = fDIV_CLK #00 1 fSAMP_CLK = fPROT_CLK #01 2 fSAMP_CLK = fSCLK #10 3 fSAMP_CLK = fREF_CLK #11 TMCNTEN Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter. 4 1 read-write 0 Timing measurement counter is Disabled #0 1 Timing measurement counter is Enabled #1 TMCNTSRC Timing Measurement Counter Clock Source Selection 5 1 read-write 0 Timing measurement counter with fPROT_CLK #0 1 Timing measurement counter with fDIV_CLK #1 UUART_BUFCTL UUART_BUFCTL USCI Transmit/Receive Buffer Control Register 0x38 read-write n 0x0 0x0 RXCLR Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle. 15 1 read-write 0 No effect #0 1 The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 RXOVIEN Receive Buffer Overrun Error Interrupt Enable Control 14 1 read-write 0 Receive overrun interrupt Disabled #0 1 Receive overrun interrupt Enabled #1 RXRST Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. 17 1 read-write 0 No effect #0 1 Reset the receive-related counters, state machine, and the content of receive shift register and data buffer #1 TXCLR Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle. 7 1 read-write 0 No effect #0 1 The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic #1 TXRST Transmit Reset\nNote: It is cleared automatically after one PCLK cycle. 16 1 read-write 0 No effect #0 1 Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer #1 UUART_BUFSTS UUART_BUFSTS USCI Transmit/Receive Buffer Status Register 0x3C -1 read-only n 0x0 0x0 RXEMPTY Receive Buffer Empty Indicator 0 1 read-only 0 Receive buffer is not empty #0 1 Receive buffer is empty #1 RXFULL Receive Buffer Full Indicator 1 1 read-only 0 Receive buffer is not full #0 1 Receive buffer is full #1 RXOVIF Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit. 3 1 read-only 0 A receive buffer overrun error event has not been detected #0 1 A receive buffer overrun error event has been detected #1 TXEMPTY Transmit Buffer Empty Indicator 8 1 read-only 0 Transmit buffer is not empty #0 1 Transmit buffer is empty #1 TXFULL Transmit Buffer Full Indicator 9 1 read-only 0 Transmit buffer is not full #0 1 Transmit buffer is full #1 UUART_CLKIN UUART_CLKIN USCI Input Clock Signal Configuration Register 0x28 read-write n 0x0 0x0 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_CTL UUART_CTL USCI Control Register 0x0 read-write n 0x0 0x0 FUNMODE Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved. 0 3 read-write 0 The USCI is disabled. All protocol related state machines are set to idle state #000 1 The SPI protocol is selected #001 2 The UART protocol is selected #010 4 The I2C protocol is selected #100 UUART_CTLIN0 UUART_CTLIN0 USCI Input Control Signal Configuration Register 0 0x20 read-write n 0x0 0x0 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_DATIN0 UUART_DATIN0 USCI Input Data Signal Configuration Register 0 0x10 read-write n 0x0 0x0 EDGEDET Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10. 3 2 read-write 0 The trigger event activation is disabled #00 1 A rising edge activates the trigger event of input data signal #01 2 A falling edge activates the trigger event of input data signal #10 3 Both edges activate the trigger event of input data signal #11 ININV Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal. 2 1 read-write 0 The un-synchronized input signal will not be inverted #0 1 The un-synchronized input signal will be inverted #1 SYNCSEL Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. 0 1 read-write 0 The un-synchronized signal can be taken as input for the data shift unit #0 1 The synchronized signal can be taken as input for the data shift unit #1 UUART_INTEN UUART_INTEN USCI Interrupt Enable Register 0x4 read-write n 0x0 0x0 RXENDIEN Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event. 4 1 read-write 0 The receive end interrupt is disabled #0 1 The receive end interrupt is enabled #1 RXSTIEN Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event. 3 1 read-write 0 The receive start interrupt is disabled #0 1 The receive start interrupt is enabled #1 TXENDIEN Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event. 2 1 read-write 0 The transmit finish interrupt is disabled #0 1 The transmit finish interrupt is enabled #1 TXSTIEN Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event. 1 1 read-write 0 The transmit start interrupt is disabled #0 1 The transmit start interrupt is enabled #1 UUART_LINECTL UUART_LINECTL USCI Line Control Register 0x2C read-write n 0x0 0x0 CTLOINV Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal. 7 1 read-write 0 No effect #0 1 The control signal will be inverted before its output #1 DATOINV Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. 5 1 read-write 0 The value of USCIx_DAT1 is equal to the data shift register #0 1 The value of USCIx_DAT1 is the inversion of data shift register #1 DWIDTH Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits. 8 4 read-write LSB LSB First Transmission Selection 0 1 read-write 0 The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, the bit 0 of data buffer, will be transmitted/received first #1 UUART_PROTCTL UUART_PROTCTL USCI Protocol Control Register 0x5C read-write n 0x0 0x0 ABREN Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). 6 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 BCEN Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 29 1 read-write 0 Transmit Break Control Disabled #0 1 Transmit Break Control Enabled #1 BRDETITV Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV. 16 9 read-write CTSAUTOEN nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). 4 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 CTSWKEN nCTS Wake-up Mode Enable Bit 10 1 read-write 0 nCTS wake-up mode Disabled #0 1 nCTS wake-up mode Enabled #1 DATWKEN Data Wake-up Mode Enable Bit 9 1 read-write 0 Data wake-up mode Disabled #0 1 Data wake-up mode Enabled #1 EVENPARITY Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set. 2 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 PARITYEN Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame. 1 1 read-write 0 The parity bit Disabled #0 1 The parity bit Enabled #1 PROTEN UART Protocol Enable Bit 31 1 read-write 0 UART Protocol Disabled #0 1 UART Protocol Enabled #1 RTSAUDIREN nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART will reassert nRTS signal.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set. 5 1 read-write 0 nRTS auto direction control Disabled #0 1 nRTS auto direction control Enabled #1 RTSAUTOEN nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set. 3 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 STICKEN Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detail information. 26 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 STOPB Stop Bits\nThis bit defines the number of stop bits in an UART frame. 0 1 read-write 0 The number of stop bits is 1 #0 1 The number of stop bits is 2 #1 WAKECNT Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. 11 4 read-write UUART_PROTIEN UUART_PROTIEN USCI Protocol Interrupt Enable Register 0x60 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 1 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. 2 1 read-write 0 Receive line status interrupt Disabled #0 1 Receive line status interrupt Enabled #1 UUART_PROTSTS UUART_PROTSTS USCI Protocol Status Register 0x64 read-write n 0x0 0x0 ABERRSTS Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. 11 1 read-write 0 Auto-baud rate detect counter is not overrun #0 1 Auto-baud rate detect counter is overrun #1 ABRDETIF Auto-baud Rate Interrupt Flag This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. Note: This bit can be cleared by writing '1' to it. 9 1 read-write 0 Auto-baud rate detect function is not done #0 1 One Bit auto-baud rate detect function is done #1 BREAK Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 7 1 read-write 0 No Break is generated #0 1 Break is generated in the receiver bus #1 CTSLV nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input. 17 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 CTSSYNCLV nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal. 16 1 read-only 0 The internal synchronized nCTS is low #0 1 The internal synchronized nCTS is high #1 FRMERR Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 6 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PARITYERR Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. 5 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RXBUSY RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver. 10 1 read-only 0 The receiver is Idle #0 1 The receiver is BUSY #1 RXENDIF Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit. 4 1 read-write 0 A receive finish interrupt status has not occurred #0 1 A receive finish interrupt status has occurred #1 RXSTIF Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit. 3 1 read-write 0 A receive start interrupt status has not occurred #0 1 A receive start interrupt status has occurred #1 TXENDIF Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit. 2 1 read-write 0 A transmit end interrupt status has not occurred #0 1 A transmit end interrupt status has occurred #1 TXSTIF Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer. 1 1 read-write 0 A transmit start interrupt status has not occurred #0 1 A transmit start interrupt status has occurred #1 UUART_RXDAT UUART_RXDAT USCI Receive Data Register 0x34 read-only n 0x0 0x0 RXDAT Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). 0 16 read-only UUART_TXDAT UUART_TXDAT USCI Transmit Data Register 0x30 write-only n 0x0 0x0 TXDAT Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. 0 16 write-only UUART_WKCTL UUART_WKCTL USCI Wake-up Control Register 0x54 read-write n 0x0 0x0 PDBOPT Power Down Blocking Option 2 1 read-write 0 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately #0 1 If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately #1 WKEN Wake-up Enable Bit 0 1 read-write 0 Wake-up function Disabled #0 1 Wake-up function Enabled #1 UUART_WKSTS UUART_WKSTS USCI Wake-up Status Register 0x58 read-write n 0x0 0x0 WKF Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write WDT WDT Register Map WDT 0x0 0x0 0xC registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Period Selection (Write Protect)\nWhen WDT time-out event happened, user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred. User can select a suitable setting of RSTDSEL for application program.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset system event occurred. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 -1 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt event did not occur #0 1 WDT time-out interrupt event occurred #1 INTEN WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTEN WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset system function Disabled #0 1 WDT time-out reset system function Enabled #1 RSTF WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset system event or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset system event did not occur #0 1 WDT time-out reset system event has been occurred #1 SYNC WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. 30 1 read-only 0 Set WDTEN bit is completed #0 1 Set WDTEN bit is synchronizing and not become active yet. #1 TOUTSEL WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period after WDT starts counting.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enabe/disable command is completed or not.\nNote3: If CWDTEN[2:0] (combined with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 Set WDT counter stop, and internal up counter value will be reset also #0 1 Set WDT counter start #1 WKEN WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken-up while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC (10 kHz) or LXT (32 kHz). 4 1 read-write 0 Trigger wake-up event function Disabled if WDT time-out interrupt signal generated #0 1 Trigger wake-up event function Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the WDT time-out event has triggered chip wake-up or not.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode when WDT time-out interrupt signal is generated #1 RSTCNT WDT_RSTCNT WDT Reset Counter Register 0x8 write-only n 0x0 0x0 RSTCNT WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 0 32 write-only WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC -1 read-only n 0x0 0x0 CNTDAT WWDT Counter Value\nCNTDAT will be updated continuously. 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 -1 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Value\nSet this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT. If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT, WWDT reset system event will be generated immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Bit\nThe WWDT down counter will keep counting no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counter counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Bit\nIf this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. 1 1 read-write 0 WWDT counter compare match interrupt disabled #0 1 WWDT counter compare match interrupt enabled #1 PSCSEL WWDT Counter Prescale Period Selection 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Bit\nSet this bit to start WWDT counter counting. 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register\nWriting only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT (WWDT_CTL[21:16]). If user writes 0x00005AA5 in WWDT_RLDCNT register when current CNTDAT is larger than CMPDAT, WWDT reset system event will be generated immediately.\nNote2: Executing WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT CNTDAT matches the CMPDAT #1 WWDTRF WWDT Timer-out Reset System Flag\nIf this bit is set to 1, it indicates that system has been reset by WWDT counter time-out reset system event.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset system event did not occur #0 1 WWDT time-out reset system event occurred #1