nuvoTon
M251_v1
2024.04.28
M251_v1 SVD file
8
32
ACMP01
ACMP Register Map
ACMP
0x0
0x0
0x10
registers
n
ACMP_CTL0
ACMP_CTL0
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit
0
1
read-write
0
Comparator 0 Disabled
#0
1
Comparator 0 Enabled
#1
ACMPIE
Comparator Interrupt Enable Bit
1
1
read-write
0
Comparator 0 interrupt Disabled
#0
1
Comparator 0 interrupt Enabled. If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well
#1
ACMPOINV
Comparator Output Inverse
3
1
read-write
0
Comparator 0 output inverse Disabled
#0
1
Comparator 0 output inverse Enabled
#1
FILTSEL
Comparator Output Filter Count Selection
13
3
read-write
0
Filter function is Disabled
#000
1
ACMP0 output is sampled 1 consecutive PCLK
#001
2
ACMP0 output is sampled 2 consecutive PCLKs
#010
3
ACMP0 output is sampled 4 consecutive PCLKs
#011
4
ACMP0 output is sampled 8 consecutive PCLKs
#100
5
ACMP0 output is sampled 16 consecutive PCLKs
#101
6
ACMP0 output is sampled 32 consecutive PCLKs
#110
7
ACMP0 output is sampled 64 consecutive PCLKs
#111
HYSSEL
Hysteresis Mode Selection
24
2
read-write
0
Hysteresis is 0mV
#00
1
Hysteresis is 10mV
#01
2
Hysteresis is 20mV
#10
3
Hysteresis is 30mV
#11
INTPOL
Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected.
8
2
read-write
0
Rising edge or falling edge
#00
1
Rising edge
#01
2
Falling edge
#10
3
Reserved.
#11
MODESEL
Propagation Delay Mode Selection
28
2
read-write
0
Max propagation delay is 4.5uS, operation current is 1.2uA
#00
1
Max propagation delay is 2uS, operation current is 3uA
#01
2
Max propagation delay is 600nS, operation current is 10uA
#10
3
Max propagation delay is 200nS, operation current is 75uA
#11
NEGSEL
Comparator Negative Input Selection
4
2
read-write
0
ACMP0_N pin
#00
1
Internal comparator reference voltage (CRV)
#01
2
Band-gap voltage
#10
3
DAC output
#11
OUTSEL
Comparator Output Select
12
1
read-write
0
Comparator 0 output to ACMP0_O pin is unfiltered comparator output
#0
1
Comparator 0 output to ACMP0_O pin is from filter output
#1
POSSEL
Comparator Positive Input Selection
6
2
read-write
0
Input from ACMP0_P0
#00
1
Input from ACMP0_P1
#01
2
Input from ACMP0_P2
#10
3
Input from ACMP0_P3
#11
WCMPSEL
Window Compare Mode Selection
18
1
read-write
0
Window Compare Mode Disabled
#0
1
Window Compare Mode is Selected
#1
WKEN
Power-down Wake-up Enable Bit
16
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
WLATEN
Window Latch Mode Enable Bit
17
1
read-write
0
Window Latch Mode Disabled
#0
1
Window Latch Mode Enabled
#1
ACMP_CTL1
ACMP_CTL1
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMPEN
Comparator Enable Bit
0
1
read-write
0
Comparator 1 Disabled
#0
1
Comparator 1 Enabled
#1
ACMPIE
Comparator Interrupt Enable Bit
1
1
read-write
0
Comparator 1 interrupt Disabled
#0
1
Comparator 1 interrupt Enabled. If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well
#1
ACMPOINV
Comparator Output Inverse Control
3
1
read-write
0
Comparator 1 output inverse Disabled
#0
1
Comparator 1 output inverse Enabled
#1
FILTSEL
Comparator Output Filter Count Selection
13
3
read-write
0
Filter function is Disabled
#000
1
ACMP1 output is sampled 1 consecutive PCLK
#001
2
ACMP1 output is sampled 2 consecutive PCLKs
#010
3
ACMP1 output is sampled 4 consecutive PCLKs
#011
4
ACMP1 output is sampled 8 consecutive PCLKs
#100
5
ACMP1 output is sampled 16 consecutive PCLKs
#101
6
ACMP1 output is sampled 32 consecutive PCLKs
#110
7
ACMP1 output is sampled 64 consecutive PCLKs
#111
HYSSEL
Hysteresis Mode Selection
24
2
read-write
0
Hysteresis is 0mV
#00
1
Hysteresis is 10mV
#01
2
Hysteresis is 20mV
#10
3
Hysteresis is 30mV
#11
INTPOL
Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected.
8
2
read-write
0
Rising edge or falling edge
#00
1
Rising edge
#01
2
Falling edge
#10
3
Reserved.
#11
MODESEL
Propagation Delay Mode Selection
28
2
read-write
0
Max propagation delay is 4.5uS, operation current is 1.2uA
#00
1
Max propagation delay is 2uS, operation current is 3uA
#01
2
Max propagation delay is 600nS, operation current is 10uA
#10
3
Max propagation delay is 200nS, operation current is 75uA
#11
NEGSEL
Comparator Negative Input Selection
4
2
read-write
0
ACMP1_N pin
#00
1
Internal comparator reference voltage (CRV)
#01
2
Band-gap voltage
#10
3
DAC output
#11
OUTSEL
Comparator Output Select
12
1
read-write
0
Comparator 1 output to ACMP1_O pin is unfiltered comparator output
#0
1
Comparator 1 output to ACMP1_O pin is from filter output
#1
POSSEL
Comparator Positive Input Selection
6
2
read-write
0
Input from ACMP1_P0
#00
1
Input from ACMP1_P1
#01
2
Input from ACMP1_P2
#10
3
Input from ACMP1_P3
#11
WCMPSEL
Window Compare Mode Selection
18
1
read-write
0
Window Compare Mode Disabled
#0
1
Window Compare Mode is Selected
#1
WKEN
Power-down Wake-up Enable Bit
16
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
WLATEN
Window Latch Mode Enable Bit
17
1
read-write
0
Window Latch Mode Disabled
#0
1
Window Latch Mode Enabled
#1
ACMP_STATUS
ACMP_STATUS
Analog Comparator Status Register
0x8
read-write
n
0x0
0x0
ACMPIF0
Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.\nNote: Write 1 to clear this bit to 0.
0
1
read-write
ACMPIF1
Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
ACMPO0
Comparator 0 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
4
1
read-write
ACMPO1
Comparator 1 Output\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
5
1
read-write
ACMPS0
Comparator 0 Status \nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
12
1
read-write
ACMPS1
Comparator 1 Status\nSynchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
13
1
read-write
ACMPWO
Comparator Window Output\nThis bit shows the output status of window compare mode
16
1
read-write
0
The positive input voltage is outside the window
#0
1
The positive input voltage is in the window
#1
WKIF0
Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0.
8
1
read-write
0
No power-down wake-up occurred
#0
1
Power-down wake-up occurred
#1
WKIF1
Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No power-down wake-up occurred
#0
1
Power-down wake-up occurred
#1
ACMP_VREF
ACMP_VREF
Analog Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVCTL
Comparator Reference Voltage Setting
0
4
read-write
CRVSSEL
CRV Source Voltage Selection
6
1
read-write
0
AVDD is selected as CRV source voltage
#0
1
The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage
#1
BPWM0
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is down counting
#0
1
Counter is up counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0\nNote: It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLD0
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_EADCTS0
BPWM_EADCTS0
BPWM Trigger EADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 0 Trigger EADC function Disabled
#0
1
BPWM Channel 0 Trigger EADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 1 Trigger EADC function Disabled
#0
1
BPWM Channel 1 Trigger EADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger EADC Enable Bit
23
1
read-write
0
BPWM Channel 2 Trigger EADC function Disabled
#0
1
BPWM Channel 2 Trigger EADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger EADC Enable Bit
31
1
read-write
0
BPWM Channel 3 Trigger EADC function Disabled
#0
1
BPWM Channel 3 Trigger EADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger EADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger EADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger EADC Source Select\nOthers reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger EADC Source Select\nOthers reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
BPWM_EADCTS1
BPWM_EADCTS1
BPWM Trigger EADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 4 Trigger EADC function Disabled
#0
1
BPWM Channel 4 Trigger EADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 5 Trigger EADC function Disabled
#0
1
BPWM Channel 5 Trigger EADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger EADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger EADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
read-write
n
0x0
0x0
PERIOD
BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: \nIn this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Synchronous start source come from BPWM0
#10
3
Synchronous start source come from BPWM1
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
read-write
n
0x0
0x0
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value.Note: This bit can be cleared by software write 1
#1
EADCTRG0
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
16
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG1
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
17
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG2
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
18
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG3
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
19
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG4
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
20
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG5
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
21
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL1
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL2
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL3
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL4
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL5
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
BPWM1
BPWM Register Map
BPWM
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x20
0x8
registers
n
0x200
0x3C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x31C
0x18
registers
n
0x50
0x18
registers
n
0x90
0x4
registers
n
0xB0
0x10
registers
n
0xD4
0x8
registers
n
0xE0
0x4
registers
n
0xE8
0x4
registers
n
0xF8
0x8
registers
n
BPWM_CAPCTL
BPWM_CAPCTL
BPWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
BPWM_CAPIEN
BPWM_CAPIEN
BPWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIENn
BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
8
6
read-write
0
Capture falling edge latch interrupt Disabled
0
1
Capture falling edge latch interrupt Enabled
1
CAPRIENn
BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
6
read-write
0
Capture rising edge latch interrupt Disabled
0
1
Capture rising edge latch interrupt Enabled
1
BPWM_CAPIF
BPWM_CAPIF
BPWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CAPFIF0
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF1
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF2
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF3
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF4
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPFIF5
BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CAPRIF0
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF1
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF2
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF3
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF4
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CAPRIF5
BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
BPWM_CAPINEN
BPWM_CAPINEN
BPWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#0
1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
#1
BPWM_CAPSTS
BPWM_CAPSTS
BPWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFIFOV0
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
8
1
read-only
CFIFOV1
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
9
1
read-only
CFIFOV2
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
10
1
read-only
CFIFOV3
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
11
1
read-only
CFIFOV4
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
12
1
read-only
CFIFOV5
Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
13
1
read-only
CRIFOV0
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
0
1
read-only
CRIFOV1
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
1
1
read-only
CRIFOV2
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
2
1
read-only
CRIFOV3
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
3
1
read-only
CRIFOV4
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
4
1
read-only
CRIFOV5
Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
5
1
read-only
BPWM_CLKPSC
BPWM_CLKPSC
BPWM Clock Prescale Register
0x14
read-write
n
0x0
0x0
CLKPSC
BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
0
12
read-write
BPWM_CLKSRC
BPWM_CLKSRC
BPWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
BPWM_CH01 External Clock Source Select
0
3
read-write
0
BPWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
BPWM_CMPBUF0
BPWM_CMPBUF0
BPWM CMPDAT 0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
BPWM Comparator Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
BPWM_CMPBUF1
BPWM_CMPBUF1
BPWM CMPDAT 1 Buffer
0x320
read-write
n
0x0
0x0
BPWM_CMPBUF2
BPWM_CMPBUF2
BPWM CMPDAT 2 Buffer
0x324
read-write
n
0x0
0x0
BPWM_CMPBUF3
BPWM_CMPBUF3
BPWM CMPDAT 3 Buffer
0x328
read-write
n
0x0
0x0
BPWM_CMPBUF4
BPWM_CMPBUF4
BPWM CMPDAT 4 Buffer
0x32C
read-write
n
0x0
0x0
BPWM_CMPBUF5
BPWM_CMPBUF5
BPWM CMPDAT 5 Buffer
0x330
read-write
n
0x0
0x0
BPWM_CMPDAT0
BPWM_CMPDAT0
BPWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMPDAT
BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
0
16
read-write
BPWM_CMPDAT1
BPWM_CMPDAT1
BPWM Comparator Register 1
0x54
read-write
n
0x0
0x0
BPWM_CMPDAT2
BPWM_CMPDAT2
BPWM Comparator Register 2
0x58
read-write
n
0x0
0x0
BPWM_CMPDAT3
BPWM_CMPDAT3
BPWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
BPWM_CMPDAT4
BPWM_CMPDAT4
BPWM Comparator Register 4
0x60
read-write
n
0x0
0x0
BPWM_CMPDAT5
BPWM_CMPDAT5
BPWM Comparator Register 5
0x64
read-write
n
0x0
0x0
BPWM_CNT
BPWM_CNT
BPWM Counter Register
0x90
read-only
n
0x0
0x0
CNT
BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter.
0
16
read-only
DIRF
BPWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is down counting
#0
1
Counter is up counting
#1
BPWM_CNTCLR
BPWM_CNTCLR
BPWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear BPWM Counter Control Bit 0\nNote: It is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit BPWM counter to 0000H
#1
BPWM_CNTEN
BPWM_CNTEN
BPWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
BPWM Counter 0 Enable Bit
0
1
read-write
0
BPWM Counter and clock prescaler stop running
#0
1
BPWM Counter and clock prescaler start running
#1
BPWM_CTL0
BPWM_CTL0
BPWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLD0
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
CTRLD1
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
1
1
read-write
CTRLD2
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
2
1
read-write
CTRLD3
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
3
1
read-write
CTRLD4
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
4
1
read-write
CTRLD5
Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
5
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects BPWM output
#0
1
ICE debug mode acknowledgement Disabled
#1
IMMLDEN0
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN1
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
17
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN2
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
18
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN3
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
19
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN4
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
20
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
IMMLDEN5
Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
21
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
BPWM_CTL1
BPWM_CTL1
BPWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.
0
2
read-write
0
Up counter type (supports in capture mode)
#00
1
Down count type (supports in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
BPWM_EADCTS0
BPWM_EADCTS0
BPWM Trigger EADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
BPWM_CH0 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 0 Trigger EADC function Disabled
#0
1
BPWM Channel 0 Trigger EADC function Enabled
#1
TRGEN1
BPWM_CH1 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 1 Trigger EADC function Disabled
#0
1
BPWM Channel 1 Trigger EADC function Enabled
#1
TRGEN2
BPWM_CH2 Trigger EADC Enable Bit
23
1
read-write
0
BPWM Channel 2 Trigger EADC function Disabled
#0
1
BPWM Channel 2 Trigger EADC function Enabled
#1
TRGEN3
BPWM_CH3 Trigger EADC Enable Bit
31
1
read-write
0
BPWM Channel 3 Trigger EADC function Disabled
#0
1
BPWM Channel 3 Trigger EADC function Enabled
#1
TRGSEL0
BPWM_CH0 Trigger EADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
BPWM_CH1 Trigger EADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH0 zero point
#0000
1
BPWM_CH0 period point
#0001
2
BPWM_CH0 zero or period point
#0010
3
BPWM_CH0 up-count CMPDAT point
#0011
4
BPWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH1 up-count CMPDAT point
#1000
9
BPWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
BPWM_CH2 Trigger EADC Source Select\nOthers reserved
16
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
BPWM_CH3 Trigger EADC Source Select\nOthers reserved.
24
4
read-write
0
BPWM_CH2 zero point
#0000
1
BPWM_CH2 period point
#0001
2
BPWM_CH2 zero or period point
#0010
3
BPWM_CH2 up-count CMPDAT point
#0011
4
BPWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH3 up-count CMPDAT point
#1000
9
BPWM_CH3 down-count CMPDAT point
#1001
BPWM_EADCTS1
BPWM_EADCTS1
BPWM Trigger EADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
BPWM_CH4 Trigger EADC Enable Bit
7
1
read-write
0
BPWM Channel 4 Trigger EADC function Disabled
#0
1
BPWM Channel 4 Trigger EADC function Enabled
#1
TRGEN5
BPWM_CH5 Trigger EADC Enable Bit
15
1
read-write
0
BPWM Channel 5 Trigger EADC function Disabled
#0
1
BPWM Channel 5 Trigger EADC function Enabled
#1
TRGSEL4
BPWM_CH4 Trigger EADC Source Select\nOthers reserved
0
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
BPWM_CH5 Trigger EADC Source Select\nOthers reserved
8
4
read-write
0
BPWM_CH4 zero point
#0000
1
BPWM_CH4 period point
#0001
2
BPWM_CH4 zero or period point
#0010
3
BPWM_CH4 up-count CMPDAT point
#0011
4
BPWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
BPWM_CH5 up-count CMPDAT point
#1000
9
BPWM_CH5 down-count CMPDAT point
#1001
BPWM_FCAPDAT0
BPWM_FCAPDAT0
BPWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_FCAPDAT1
BPWM_FCAPDAT1
BPWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
BPWM_FCAPDAT2
BPWM_FCAPDAT2
BPWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
BPWM_FCAPDAT3
BPWM_FCAPDAT3
BPWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
BPWM_FCAPDAT4
BPWM_FCAPDAT4
BPWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
BPWM_FCAPDAT5
BPWM_FCAPDAT5
BPWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
BPWM_INTEN
BPWM_INTEN
BPWM Interrupt Enable Register
0xE0
read-write
n
0x0
0x0
CMPDIEN0
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
BPWM Zero Point Interrupt 0 Enable Bit
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
BPWM_INTSTS
BPWM_INTSTS
BPWM Interrupt Flag Register
0xE8
read-write
n
0x0
0x0
CMPDIF0
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
24
1
read-write
CMPDIF1
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
25
1
read-write
CMPDIF2
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
26
1
read-write
CMPDIF3
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
27
1
read-write
CMPDIF4
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
28
1
read-write
CMPDIF5
BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
29
1
read-write
CMPUIF0
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
16
1
read-write
CMPUIF1
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
17
1
read-write
CMPUIF2
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
18
1
read-write
CMPUIF3
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
19
1
read-write
CMPUIF4
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
20
1
read-write
CMPUIF5
BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
21
1
read-write
PIF0
BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0.
8
1
read-write
ZIF0
BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0.
0
1
read-write
BPWM_MSK
BPWM_MSK
BPWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT1
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT2
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT3
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT4
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
MSKDAT5
BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
Output logic low to BPWMn
#0
1
Output logic high to BPWMn
#1
BPWM_MSKEN
BPWM_MSKEN
BPWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
0
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN1
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
1
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN2
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
2
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN3
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
3
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN4
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
4
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
MSKEN5
BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
5
1
read-write
0
BPWM output signal is non-masked
#0
1
BPWM output signal is masked and output MSKDATn data
#1
BPWM_PBUF
BPWM_PBUF
BPWM PERIOD Buffer
0x304
read-only
n
0x0
0x0
PBUF
BPWM Period Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
BPWM_PERIOD
BPWM_PERIOD
BPWM Period Register
0x30
read-write
n
0x0
0x0
PERIOD
BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: \nIn this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
BPWM_POEN
BPWM_POEN
BPWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN1
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN2
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN3
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN4
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
POEN5
BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM pin at tri-state
#0
1
BPWM pin in output mode
#1
BPWM_POLCTL
BPWM_POLCTL
BPWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
0
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV1
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
1
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV2
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
2
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV3
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
3
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV4
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
4
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
PINV5
BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
5
1
read-write
0
BPWM output pin polar inverse Disabled
#0
1
BPWM output pin polar inverse Enabled
#1
BPWM_RCAPDAT0
BPWM_RCAPDAT0
BPWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register.
0
16
read-only
BPWM_RCAPDAT1
BPWM_RCAPDAT1
BPWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
BPWM_RCAPDAT2
BPWM_RCAPDAT2
BPWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
BPWM_RCAPDAT3
BPWM_RCAPDAT3
BPWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
BPWM_RCAPDAT4
BPWM_RCAPDAT4
BPWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
BPWM_RCAPDAT5
BPWM_RCAPDAT5
BPWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
BPWM_SSCTL
BPWM_SSCTL
BPWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
BPWM synchronous start function Disabled
#0
1
BPWM synchronous start function Enabled
#1
SSRC
BPWM Synchronous Start Source Select
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Synchronous start source come from BPWM0
#10
3
Synchronous start source come from BPWM1
#11
BPWM_SSTRG
BPWM_SSTRG
BPWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
0
1
write-only
BPWM_STATUS
BPWM_STATUS
BPWM Status Register
0x120
read-write
n
0x0
0x0
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Status
0
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value.Note: This bit can be cleared by software write 1
#1
EADCTRG0
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
16
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG1
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
17
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG2
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
18
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG3
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
19
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG4
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
20
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
EADCTRG5
EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
21
1
read-write
0
No EADC start of conversion trigger event has occurred
#0
1
An EADC start of conversion trigger event has occurred
#1
BPWM_WGCTL0
BPWM_WGCTL0
BPWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL1
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL2
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL3
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL4
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
PRDPCTL5
BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
BPWM period (center) point output Low
#01
2
BPWM period (center) point output High
#10
3
BPWM period (center) point output Toggle
#11
ZPCTL0
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
0
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL1
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
2
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL2
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
4
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL3
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
6
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL4
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
8
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
ZPCTL5
BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
10
2
read-write
0
Do nothing
#00
1
BPWM zero point output Low
#01
2
BPWM zero point output High
#10
3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
#11
BPWM_WGCTL1
BPWM_WGCTL1
BPWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
16
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL1
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
18
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL2
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
20
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL3
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
22
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL4
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
24
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPDCTL5
BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
26
2
read-write
0
Do nothing
#00
1
BPWM compare down point output Low
#01
2
BPWM compare down point output High
#10
3
BPWM compare down point output Toggle
#11
CMPUCTL0
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
0
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL1
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
2
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL2
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
4
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL3
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
6
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL4
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
8
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CMPUCTL5
BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
10
2
read-write
0
Do nothing
#00
1
BPWM compare up point output Low
#01
2
BPWM compare up point output High
#10
3
BPWM compare up point output Toggle
#11
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
0x30
0x8
registers
n
0x40
0x4
registers
n
0x50
0x4
registers
n
0x60
0x4
registers
n
0x70
0x10
registers
n
0x90
0x8
registers
n
0xB4
0x4
registers
n
AHBCLK
CLK_AHBCLK
AHB Devices Clock Enable Control Register
0x4
read-write
n
0x0
0x0
CRCCKEN
CRC Generator Controller Clock Enable Bit
7
1
read-write
0
CRC peripheral clock Disabled
#0
1
CRC peripheral clock Enabled
#1
CRYPTCKEN
Cryptographic Accelerator Clock Enable Bit
12
1
read-write
0
Cryptographic Accelerator clock Disabled
#0
1
Cryptographic Accelerator clock Enabled
#1
EBICKEN
EBI Controller Clock Enable Bit
3
1
read-write
0
EBI peripheral clock Disabled
#0
1
EBI peripheral clock Enabled
#1
FMCIDLE
Flash Memory Controller Clock Enable Bit in IDLE Mode
15
1
read-write
0
FMC clock Disabled when chip is under IDLE mode,in this case, PDMA can not access FMC memory
#0
1
FMC clock Enabled when chip is under IDLE mode,PDMA can access FMC memory
#1
ISPCKEN
Flash ISP Controller Clock Enable Bit
2
1
read-write
0
Flash ISP peripheral clock Disabled
#0
1
Flash ISP peripheral clock Enabled
#1
PDMACKEN
PDMA Controller Clock Enable Bit
1
1
read-write
0
PDMA peripheral clock Disabled
#0
1
PDMA peripheral clock Enabled
#1
APBCLK0
CLK_APBCLK0
APB Devices Clock Enable Control Register 0
0x8
read-write
n
0x0
0x0
ACMP01CKEN
Analog Comparator 0/1 Clock Enable Bit
7
1
read-write
0
Analog comparator 0/1 clock Disabled
#0
1
Analog comparator 0/1 clock Enabled
#1
CLKOCKEN
CLKO Clock Enable Bit
6
1
read-write
0
CLKO clock Disabled
#0
1
CLKO clock Enabled
#1
EADCCKEN
Enhanced Analog-digital-converter (EADC) Clock Enable Bit
28
1
read-write
0
EADC clock Disabled
#0
1
EADC clock Enabled
#1
I2C0CKEN
I2C0 Clock Enable Bit
8
1
read-write
0
I2C0 clock Disabled
#0
1
I2C0 clock Enabled
#1
I2C1CKEN
I2C1 Clock Enable Bit
9
1
read-write
0
I2C1 clock Disabled
#0
1
I2C1 clock Enabled
#1
QSPI0CKEN
QSPI0 Clock Enable Bit
12
1
read-write
0
QSPI0 clock Disabled
#0
1
QSPI0 clock Enabled
#1
RTCCKEN
Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 38.4 kHz internal low speed RC oscillator (LIRC).
1
1
read-write
0
RTC clock Disabled
#0
1
RTC clock Enabled
#1
SPI0CKEN
SPI0 Clock Enable Bit
13
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
TMR0CKEN
Timer0 Clock Enable Bit
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1CKEN
Timer1 Clock Enable Bit
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2CKEN
Timer2 Clock Enable Bit
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3CKEN
Timer3 Clock Enable Bit
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0CKEN
UART0 Clock Enable Bit
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1CKEN
UART1 Clock Enable Bit
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
UART2CKEN
UART2 Clock Enable Bit
18
1
read-write
0
UART2 clock Disabled
#0
1
UART2 clock Enabled
#1
USBDCKEN
USB Device Clock Enable Bit
27
1
read-write
0
USB Device clock Disabled
#0
1
USB Device clock Enabled
#1
WDTCKEN
Watchdog Timer Clock Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is forced to 1 when CONFIG0[3] or CONFIG0[4] or CONFIG0[31] is 0.\nNote3: Reset by power on reset or watch dog reset or software chip reset.
0
1
read-write
0
Watchdog timer clock Disabled
#0
1
Watchdog timer clock Enabled
#1
APBCLK1
CLK_APBCLK1
APB Devices Clock Enable Control Register 1
0xC
read-write
n
0x0
0x0
BPWM0CKEN
BPWM0 Clock Enable Bit
18
1
read-write
0
BPWM0 clock Disabled
#0
1
BPWM0 clock Enabled
#1
BPWM1CKEN
BPWM1 Clock Enable Bit
19
1
read-write
0
BPWM1 clock Disabled
#0
1
BPWM1 clock Enabled
#1
DACCKEN
DAC Clock Enable Bit
12
1
read-write
0
DAC clock Disabled
#0
1
DAC clock Enabled
#1
OPACKEN
OP Amplifier (OPA) Clock Enable Bit
30
1
read-write
0
OPA clock Disabled
#0
1
OPA clock Enabled
#1
PSIOCKEN
PSIO Clock Enable Bit
31
1
read-write
0
PSIO clock Disabled
#0
1
PSIO clock Enabled
#1
PWM0CKEN
PWM0 Clock Enable Bit
16
1
read-write
0
PWM0 clock Disabled
#0
1
PWM0 clock Enabled
#1
PWM1CKEN
PWM1 Clock Enable Bit
17
1
read-write
0
PWM1 clock Disabled
#0
1
PWM1 clock Enabled
#1
SC0CKEN
SC0 Clock Enable Bit
0
1
read-write
0
SC0 clock Disabled
#0
1
SC0 clock Enabled
#1
USCI0CKEN
USCI0 Clock Enable Bit
8
1
read-write
0
USCI0 clock Disabled
#0
1
USCI0 clock Enabled
#1
USCI1CKEN
USCI1 Clock Enable Bit
9
1
read-write
0
USCI1 clock Disabled
#0
1
USCI1 clock Enabled
#1
USCI2CKEN
USCI2 Clock Enable Bit
10
1
read-write
0
USCI1 clock Disabled
#0
1
USCI1 clock Enabled
#1
CDLOWB
CLK_CDLOWB
Clock Frequency Range Detector Lower Boundary Register
0x7C
read-write
n
0x0
0x0
LOWERBD
HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.\nNote :The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
0
10
read-write
CDUPB
CLK_CDUPB
Clock Frequency Range Detector Upper Boundary Register
0x78
read-write
n
0x0
0x0
UPERBD
HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.\nNote :Frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
0
10
read-write
CLKDCTL
CLK_CLKDCTL
Clock Fail Detector Control Register
0x70
read-write
n
0x0
0x0
HXTFDEN
HXT Clock Fail Detector Enable Bit
4
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled
#1
HXTFIEN
HXT Clock Fail Interrupt Enable Bit
5
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled
#1
HXTFQDEN
HXT Clock Frequency Range Detector Enable Bit
16
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled
#1
HXTFQIEN
HXT Clock Frequency Range Detector Interrupt Enable Bit
17
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
#1
LXTFDEN
LXT Clock Fail Detector Enable Bit
12
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled
#1
LXTFIEN
LXT Clock Fail Interrupt Enable Bit
13
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled
#1
CLKDIV0
CLK_CLKDIV0
Clock Divider Number Register 0
0x20
read-write
n
0x0
0x0
EADCDIV
EADC Clock Divide Number From EADC Clock Source
16
8
read-write
HCLKDIV
HCLK Clock Divide Number From HCLK Clock Source
0
4
read-write
UART0DIV
UART0 Clock Divide Number From UART0 Clock Source
8
4
read-write
UART1DIV
UART1 Clock Divide Number From UART1 Clock Source
12
4
read-write
USBDIV
USB Clock Divide Number From PLL Clock
4
4
read-write
CLKDIV1
CLK_CLKDIV1
Clock Divider Number Register 1
0x24
read-write
n
0x0
0x0
PSIODIV
PSIO Clock Divide Number From PSIO Clock Source
24
8
read-write
SC0DIV
SC0 Clock Divide Number From SC0 Clock Source
0
8
read-write
CLKDIV4
CLK_CLKDIV4
Clock Divider Number Register 4
0x30
read-write
n
0x0
0x0
UART2DIV
UART2 Clock Divide Number From UART2 Clock Source
0
4
read-write
CLKDSTS
CLK_CLKDSTS
Clock Fail Detector Status Register
0x74
read-write
n
0x0
0x0
HXTFIF
HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
0
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock is normal
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock stops
#1
HXTFQIF
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
8
1
read-write
0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal
#1
LXTFIF
LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
1
1
read-write
0
32.768 kHz external low speed crystal oscillator (LXT) clock is normal
#0
1
32.768 kHz external low speed crystal oscillator (LXT) stops
#1
CLKOCTL
CLK_CLKOCTL
Clock Output Control Register
0x60
read-write
n
0x0
0x0
CLK1HZEN
Clock Output 1Hz Enable Bit
6
1
read-write
0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#0
1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
#1
CLKOEN
Clock Output Enable Bit
4
1
read-write
0
Clock Output function Disabled
#0
1
Clock Output function Enabled
#1
DIV1EN
Clock Output Divide One Enable Bit
5
1
read-write
0
Clock Output will output clock with source frequency divided by FREQSEL
#0
1
Clock Output will output clock with source frequency
#1
FREQSEL
Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
0
4
read-write
CLKSEL0
CLK_CLKSEL0
Clock Source Select Control Register 0
0x10
read-write
n
0x0
0x0
HCLKSEL
HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by power on reset.
0
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from PLL
#010
3
Clock source from LIRC
#011
5
Clock source from MIRC
#101
7
Clock source from HIRC
#111
STCLKSEL
Cortex-M23 SysTick Clock Source Selection (Write Protect)\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
3
3
read-write
0
Clock source from HXT
#000
1
Clock source from LXT
#001
2
Clock source from HXT/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC/2
#111
USBDSEL
USB Device Clock Source Selection (Write Protect)\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
8
1
read-write
0
Clock source from HIRC
#0
1
Clock source from PLL Divided
#1
CLKSEL1
CLK_CLKSEL1
Clock Source Select Control Register 1
0x14
read-write
n
0x0
0x0
CLKOSEL
Clock Divider Clock Source Selection
4
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from HCLK
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#100
5
Clock source from 4 MHz internal medium speed RC oscillator (MIRC)
#101
6
Clock source from PLL
#110
7
Clock source from USB SOF
#111
TMR0SEL
TIMER0 Clock Source Selection
8
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T0 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR1SEL
TIMER1 Clock Source Selection
12
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK0
#010
3
Clock source from external clock T1 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR2SEL
TIMER2 Clock Source Selection
16
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T2 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
TMR3SEL
TIMER3 Clock Source Selection
20
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from external clock T3 pin
#011
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
UART0SEL
UART0 Clock Source Selection
24
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
UART1SEL
UART1 Clock Source Selection
28
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK1
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register. \nNote2: This bit is forced to 11 when CONFIG0[31] or CONFIG0[4] or CONFIG0[3] is 0.
0
2
read-write
0
Reserved.
#00
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#01
2
Clock source from HCLK/2048
#10
3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#11
WWDTSEL
Window Watchdog Timer Clock Source Selection (Write Protect)
2
2
read-write
2
Clock source from HCLK/2048
#10
3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#11
CLKSEL2
CLK_CLKSEL2
Clock Source Select Control Register 2
0x18
read-write
n
0x0
0x0
BPWM0SEL
BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL.
8
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK0
#1
BPWM1SEL
BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL.
9
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK1
#1
PSIOSEL
PSIO Clock Source Selection
28
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#001
2
Clock source from PCLK1
#010
3
Clock source from PLL
#011
4
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#100
7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#111
PWM0SEL
PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL.
0
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK0
#1
PWM1SEL
PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL.
1
1
read-write
0
Clock source from PLL
#0
1
Clock source from PCLK1
#1
QSPI0SEL
QSPI0 Clock Source Selection
2
2
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK0
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
SPI0SEL
SPI0 Clock Source Selection
4
2
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK1
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
CLKSEL3
CLK_CLKSEL3
Clock Source Select Control Register 3
0x1C
read-write
n
0x0
0x0
SC0SEL
SC0 Clock Source Selection
0
2
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#00
1
Clock source from PLL
#01
2
Clock source from PCLK0
#10
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#11
UART2SEL
UART2 Clock Source Selection
24
3
read-write
0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#000
1
Clock source from PLL
#001
2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010
3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#011
4
Clock source from PCLK0
#100
5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101
HXTFSEL
CLK_HXTFSEL
HXT Filter Select Control Register
0xB4
read-write
n
0x0
0x0
HXTFSEL
HXT Filter Select \nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit should not be changed during HXT running.
0
1
read-write
0
HXT frequency is greater than 12 MHz
#0
1
HXT frequency is less than or equal to 12 MHz
#1
PCLKDIV
CLK_PCLKDIV
APB Clock Divider Register
0x34
read-write
n
0x0
0x0
APB0DIV
APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved.
0
3
read-write
APB1DIV
APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved.
4
3
read-write
PLLCTL
CLK_PLLCTL
PLL Control Register
0x40
read-write
n
0x0
0x0
BP
PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as PLL input clock FIN
#1
FBDIV
PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
6
read-write
INDIV
PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
9
4
read-write
OE
PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
18
1
read-write
0
PLL FOUT Enabled
#0
1
PLL FOUT is fixed low
#1
OUTDIV
PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
14
2
read-write
PD
Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in Power-down mode (default)
#1
PLLSRC
PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: MIRC and HIRC have to be both on when source switch between them
19
2
read-write
0
PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT)
#00
1
PLL source clock from 12 MHz internal high-speed oscillator (HIRC/4)
#01
2
PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT)
#10
3
PLL source clock from 4 MHz internal high-speed oscillator (MIRC)
#11
PLL_CLF_EN
1: PLL Clock Filter On\n0 : OFF
24
1
read-write
STBSEL
PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
PLL stable time is 1200 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#0
1
PLL stable time is 3200 PLL source clock (suitable for source clock is larger than 12 MHz)
#1
PMUCTL
CLK_PMUCTL
Power Manager Control Register
0x90
read-write
n
0x0
0x0
PDMSEL
Power-down Mode Selection (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThese bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
3
read-write
0
Power-down mode is selected. (PD)
#000
2
fast wake up
#010
6
Deep Power-down mode is selected (DPD)
#110
RTCWKEN
RTC Wake-up Enable (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
23
1
read-write
0
RTC wake-up disable at Deep Power-down mode or Standby Power-down mode
#0
1
RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode
#1
WKPINDBEN
Wake-up Pin De-bounce Enable Bit (Write Protect)\nThe WKPINDBEN bit is used to enable the de-bounce function for wake-up pin. If the input signal pulse width cannot be sampled by continuous eight de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 38 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered.
22
1
read-write
0
Deep power-down wake-up pin De-bounce function disable
#0
1
Deep power-down wake-up pin De-bounce function enable
#1
WKPINEN0
Wake-up Pin Enable 0 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PC.0 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
16
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKPINEN1
Wake-up Pin Enable 1 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.0 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
24
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKPINEN2
Wake-up Pin Enable 2 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.2 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
26
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKPINEN3
Wake-up Pin Enable 3 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.12 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
28
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKPINEN4
Wake-up Pin Enable 4 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PF.6 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
30
2
read-write
0
Wake-up pin disable at Deep Power-down mode
#00
1
Wake-up pin rising edge enabled at Deep Power-down mode
#01
2
Wake-up pin falling edge enabled at Deep Power-down mode
#10
3
Wake-up pin both edge enabled at Deep Power-down mode
#11
WKTMREN
Wake-up Timer Enable (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register
8
1
read-write
0
Wake-up timer disable at DPD mode
#0
1
Wake-up timer enabled at DPD mode
#1
WKTMRIS
Wake-up Timer Time-out Interval Select (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThese bits control wake-up timer time-out interval when chip at DPD mode.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
9
3
read-write
0
Time-out interval is 128 LIRC clocks (~3.368 ms)
#000
1
Time-out interval is 256 LIRC clocks (~6.736 ms)
#001
2
Time-out interval is 512 LIRC clocks (~13.47 ms)
#010
3
Time-out interval is 1024 LIRC clocks (~26.95 ms)
#011
4
Time-out interval is 4096 LIRC clocks (~107.79 ms)
#100
5
Time-out interval is 8192 LIRC clocks (~215.58 ms)
#101
6
Time-out interval is 16384 LIRC clocks (~431.16 ms)
#110
7
Time-out interval is 32768 LIRC clocks (~862.32 ms)
#111
PMUSTS
CLK_PMUSTS
Power Manager Status Register
0x94
read-write
n
0x0
0x0
CLRWK
Clear Wake-up Flag\nNote: Reset by powr on reset.
31
1
read-write
0
Not cleared
#0
1
Clear all wake-up flag
#1
LVRWK
LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode was requested with a LVR happened. This flag is cleared when DPD mode is entered.
12
1
read-only
PINWK0
Pin Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). This flag is cleared when DPD mode is entered.
0
1
read-only
PINWK1
Pin Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.0). This flag is cleared when DPD mode is entered.
3
1
read-only
PINWK2
Pin Wake-up 2 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.2). This flag is cleared when DPD mode is entered.
4
1
read-only
PINWK3
Pin Wake-up 3 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.12). This flag is cleared when DPD mode is entered.
5
1
read-only
PINWK4
Pin Wake-up 4 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPF.6). This flag is cleared when DPD mode is entered.
6
1
read-only
RTCWK
RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) was requested with a RTC alarm, tick time or tamper happened. This flag is cleared when DPD mode is entered.
2
1
read-only
TMRWK
Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by wakeup timer time-out. This flag is cleared when DPD mode is entered.
1
1
read-only
PWRCTL
CLK_PWRCTL
System Power-down Control Register
0x0
read-write
n
0x0
0x0
HIRCEN
HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) Enabled
#1
HXTEN
HXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by powr on reset.
0
1
read-write
0
4~32 MHz external high speed crystal (HXT) Disabled
#0
1
4~32 MHz external high speed crystal (HXT) Enabled
#1
HXTGAIN
HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by power on reset.
20
3
read-write
0
HXT frequency 1~4 MHz
#000
1
HXT frequency 4~8 MHz
#001
3
HXT frequency 12~ 16 MHz
#011
4
HXT frequency 16~24 MHz
#100
5
HXT frequency 24~32 Mhz
#101
LIRCEN
LIRC Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC will also be forced on when 1. Power down and ~(CONFIG0[3] CONFIG0[4] ~CONFIG0[31] CONFIG0[30]) 2. Not power down and ~(CONFIG0[3] CONFIG0[4] CONFIG0[31])
3
1
read-write
0
38.4 kHz internal low speed RC oscillator (LIRC) Disabled
#0
1
38.4 kHz internal low speed RC oscillator (LIRC) Enabled
#1
LXTEN
LXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by RTC powr on reset.
1
1
read-write
0
32.768 kHz external low speed crystal (LXT) Disabled
#0
1
32.768 kHz external low speed crystal (LXT) Enabled
#1
MIRCEN
MIRC Enable Bit (Write Protect)
19
1
read-write
0
4 MHz internal high speed RC oscillator (MIRC) Disabled
#0
1
4 MHz internal high speed RC oscillator (MIRC) Enabled
#1
PDEN
System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled, chip enters Power-down mode immediately after the PDEN bit set. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT ,MIRC and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL, HCLK, PCLK0 and PCLK1 clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Chip operating normally or chip in idle mode because of WFI command
#0
1
Chip enters Power-down mode instant or wait CPU sleep command WFI
#1
PDWKDLY
Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~32 MHz external high speed crystal oscillator (HXT),\nThe delayed clock cycle is 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC)\nThe delayed clock cycle is 32 clock cycles when chip works at 4 MHz internal median speed RC oscillator (MIRC)\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
PDWKIEN
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
Power-down mode wake-up interrupt Disabled
#0
1
Power-down mode wake-up interrupt Enabled
#1
PDWKIF
Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
6
1
read-write
STATUS
CLK_STATUS
Clock Status Monitor Register
0x50
read-only
n
0x0
0x0
CLKSFAIL
Clock Switching Fail Flag \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
7
1
read-only
0
Clock switching success
#0
1
Clock switching failure
#1
HIRCSTB
HIRC Clock Source Stable Flag (Read Only)
4
1
read-only
0
48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#0
1
48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
#1
HXTSTB
HXT Clock Source Stable Flag (Read Only)
0
1
read-only
0
4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#0
1
4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
#1
LIRCSTB
LIRC Clock Source Stable Flag (Read Only)
3
1
read-only
0
38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#0
1
38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
#1
LXTSTB
LXT Clock Source Stable Flag (Read Only)
1
1
read-only
0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#0
1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
#1
MIRCSTB
MIRC Clock Source Stable Flag (Read Only)
6
1
read-only
0
4 MHz internal mid speed RC oscillator (MIRC) clock is not stable or disabled
#0
1
4 MHz internal mid speed RC oscillator (MIRC) clock is stable and enabled
#1
PLLSTB
Internal PLL Clock Source Stable Flag (Read Only)
2
1
read-only
0
Internal PLL clock is not stable or disabled
#0
1
Internal PLL clock is stable and enabled
#1
CRC
CRC Register Map
CRC
0x0
0x0
0x10
registers
n
CHECKSUM
CRC_CHECKSUM
CRC Checksum Register
0xC
read-only
n
0x0
0x0
CHECKSUM
CRC Checksum Results\nThis field indicates the CRC checksum result.
0
32
read-only
CTL
CRC_CTL
CRC Control Register
0x0
read-write
n
0x0
0x0
CHKSFMT
Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
27
1
read-write
0
1's complement for CRC checksum Disabled
#0
1
1's complement for CRC checksum Enabled
#1
CHKSINIT
Checksum Initialization\nNote: This bit will be cleared automatically.
1
1
read-write
0
No effect
#0
1
Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value
#1
CHKSREV
Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
25
1
read-write
0
Bit order reverse for CRC checksum Disabled
#0
1
Bit order reverse for CRC checksum Enabled
#1
CRCEN
CRC Channel Enable Bit
0
1
read-write
0
No effect
#0
1
CRC operation Enabled
#1
CRCMODE
CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.
30
2
read-write
0
CRC-CCITT Polynomial mode
#00
1
CRC-8 Polynomial mode
#01
2
CRC-16 Polynomial mode
#10
3
CRC-32 Polynomial mode
#11
DATFMT
Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register.
26
1
read-write
0
1's complement for CRC writes data in Disabled
#0
1
1's complement for CRC writes data in Enabled
#1
DATLEN
CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
28
2
read-write
0
Data length is 8-bit mode
#00
1
Data length is 16-bit mode.\nData length is 32-bit mode
#01
DATREV
Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
24
1
read-write
0
Bit order reversed for CRC write data in Disabled
#0
1
Bit order reversed for CRC write data in Enabled (per byte)
#1
DAT
CRC_DAT
CRC Write Data Register
0x4
read-write
n
0x0
0x0
DATA
CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
0
32
read-write
SEED
CRC_SEED
CRC Seed Register
0x8
read-write
n
0x0
0x0
SEED
CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
0
32
read-write
CRYPTO
CRYPTO Register Map
CRYPTO
0x0
0x0
0x30
registers
n
0x100
0x4C
registers
n
0x50
0x10
registers
n
AES_CNT
CRYPTO_AES_CNT
AES Byte Count Register
0x148
read-write
n
0x0
0x0
CNT
AES Byte Count\nThe CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AESn_CNT can be read and written. Writing to CRYPTO_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
0
32
read-write
AES_CTL
CRYPTO_AES_CTL
AES Control Register
0x100
read-write
n
0x0
0x0
DMACSCAD
AES Engine DMA with Cascade Mode
6
1
read-write
0
DMA cascade function Disabled
#0
1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
#1
DMAEN
AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
7
1
read-write
0
AES DMA engine Disabled
#0
1
AES_DMA engine Enabled
#1
DMALAST
AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
5
1
read-write
ENCRYPTO
AES Encryption/Decryption
16
1
read-write
0
AES engine executes decryption operation
#0
1
AES engine executes encryption operation
#1
INSWAP
AES Engine Input Data Swap
23
1
read-write
0
Keep the original order
#0
1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
KEYPRT
Protect Key\nRead as a flag to reflect KEYPRT.
31
1
read-write
0
No effect
#0
1
Protect the content of the AES key from reading. The return value for reading CRYPTO_AES_KEYx is not the content of the registers CRYPTO_AES_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
#1
KEYSZ
AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
2
2
read-write
KEYUNPRT
Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
26
5
read-write
OPMODE
AES Engine Operation Modes
8
8
read-write
0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x00
2
CFB (Cipher Feedback Mode)
0x02
3
OFB (Output Feedback Mode)
0x03
4
CTR (Counter Mode)
0x04
16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x10
17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x11
18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
0x12
OUTSWAP
AES Engine Output Data Swap
22
1
read-write
0
Keep the original order
#0
1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
#1
START
AES Engine Start\nNote: This bit is always 0 when it's read back.
0
1
read-write
0
No effect
#0
1
Start AES engine. BUSY flag will be set
#1
STOP
AES Engine Stop\nNote: This bit is always 0 when it's read back.
1
1
read-write
0
No effect
#0
1
Stop AES engine
#1
AES_DADDR
CRYPTO_AES_DADDR
AES DMA Destination Address Register
0x144
read-write
n
0x0
0x0
DADDR
AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AES_DADDR before triggering START. \nThe value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
0
32
read-write
AES_DATIN
CRYPTO_AES_DATIN
AES Engine Data Input Port Register
0x108
read-write
n
0x0
0x0
DATIN
AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0.
0
32
read-write
AES_DATOUT
CRYPTO_AES_DATOUT
AES Engine Data Output Port Register
0x10C
read-only
n
0x0
0x0
DATOUT
AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0.
0
32
read-only
AES_FDBCK0
CRYPTO_AES_FDBCK0
AES Engine Output Feedback Data After Cryptographic Operation
0x50
read-only
n
0x0
0x0
FDBCK
AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting.
0
32
read-only
AES_FDBCK1
CRYPTO_AES_FDBCK1
AES Engine Output Feedback Data After Cryptographic Operation
0x54
read-write
n
0x0
0x0
AES_FDBCK2
CRYPTO_AES_FDBCK2
AES Engine Output Feedback Data After Cryptographic Operation
0x58
read-write
n
0x0
0x0
AES_FDBCK3
CRYPTO_AES_FDBCK3
AES Engine Output Feedback Data After Cryptographic Operation
0x5C
read-write
n
0x0
0x0
AES_IV0
CRYPTO_AES_IV0
AES Initial Vector Word 0 Register
0x130
read-write
n
0x0
0x0
IV
AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
0
32
read-write
AES_IV1
CRYPTO_AES_IV1
AES Initial Vector Word 1 Register
0x134
read-write
n
0x0
0x0
AES_IV2
CRYPTO_AES_IV2
AES Initial Vector Word 2 Register
0x138
read-write
n
0x0
0x0
AES_IV3
CRYPTO_AES_IV3
AES Initial Vector Word 3 Register
0x13C
read-write
n
0x0
0x0
AES_KEY0
CRYPTO_AES_KEY0
AES Key Word 0 Register
0x110
read-write
n
0x0
0x0
KEY
CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\n{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. \n{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. \n{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation.
0
32
read-write
AES_KEY1
CRYPTO_AES_KEY1
AES Key Word 1 Register
0x114
read-write
n
0x0
0x0
AES_KEY2
CRYPTO_AES_KEY2
AES Key Word 2 Register
0x118
read-write
n
0x0
0x0
AES_KEY3
CRYPTO_AES_KEY3
AES Key Word 3 Register
0x11C
read-write
n
0x0
0x0
AES_KEY4
CRYPTO_AES_KEY4
AES Key Word 4 Register
0x120
read-write
n
0x0
0x0
AES_KEY5
CRYPTO_AES_KEY5
AES Key Word 5 Register
0x124
read-write
n
0x0
0x0
AES_KEY6
CRYPTO_AES_KEY6
AES Key Word 6 Register
0x128
read-write
n
0x0
0x0
AES_KEY7
CRYPTO_AES_KEY7
AES Key Word 7 Register
0x12C
read-write
n
0x0
0x0
AES_SADDR
CRYPTO_AES_SADDR
AES DMA Source Address Register
0x140
read-write
n
0x0
0x0
SADDR
AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AES_SADDR before triggering START.\nThe value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
0
32
read-write
AES_STS
CRYPTO_AES_STS
AES Engine Flag
0x104
read-only
n
0x0
0x0
BUSERR
AES DMA Access Bus Error Flag
20
1
read-only
0
No error
#0
1
Bus error will stop DMA operation and AES engine
#1
BUSY
AES Engine Busy
0
1
read-only
0
The AES engine is idle or finished
#0
1
The AES engine is under processing
#1
CNTERR
CRYPTO_ AES_CNT Setting Error
12
1
read-only
0
No error in CRYPTO_AES_CNT setting
#0
1
CRYPTO_AES_CNT is 0 if DMAEN (CRYPTO_AES_CTL[7]) is enabled
#1
INBUFEMPTY
AES Input Buffer Empty
8
1
read-only
0
There are some data in input buffer waiting for the AES engine to process
#0
1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
#1
INBUFERR
AES Input Buffer Error Flag
10
1
read-only
0
No error
#0
1
Error happens during feeding data to the AES engine
#1
INBUFFULL
AES Input Buffer Full Flag
9
1
read-only
0
AES input buffer is not full. Software can feed the data into the AES engine
#0
1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
#1
OUTBUFEMPTY
AES Out Buffer Empty
16
1
read-only
0
AES output buffer is not empty. There are some valid data kept in output buffer
#0
1
AES output buffer is empty. Software cannot get data from CRYPTO_AES_DATOUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
#1
OUTBUFERR
AES Out Buffer Error Flag
18
1
read-only
0
No error
#0
1
Error happens during getting the result from AES engine
#1
OUTBUFFULL
AES Out Buffer Full Flag
17
1
read-only
0
AES output buffer is not full
#0
1
AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT. Otherwise, the AES engine will be pending since the output buffer is full
#1
INTEN
CRYPTO_INTEN
Crypto Interrupt Enable Control Register
0x0
read-write
n
0x0
0x0
AESEIEN
AES Error Flag Enable Bit
1
1
read-write
0
AES error interrupt flag Disabled
#0
1
AES error interrupt flag Enabled
#1
AESIEN
AES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
0
1
read-write
0
AES interrupt Disabled
#0
1
AES interrupt Enabled
#1
PRNGIEN
PRNG Interrupt Enable Bit
16
1
read-write
0
PRNG interrupt Disabled
#0
1
PRNG interrupt Enabled
#1
INTSTS
CRYPTO_INTSTS
Crypto Interrupt Flag
0x4
read-write
n
0x0
0x0
AESEIF
AES Error Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
1
1
read-write
0
No AES error
#0
1
AES encryption/decryption error interrupt
#1
AESIF
AES Finish Interrupt Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
0
1
read-write
0
No AES interrupt
#0
1
AES encryption/decryption done interrupt
#1
PRNGIF
PRNG Finish Interrupt Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
16
1
read-write
0
No PRNG interrupt
#0
1
PRNG key generation done interrupt
#1
PRNG_CTL
CRYPTO_PRNG_CTL
PRNG Control Register
0x8
read-write
n
0x0
0x0
BUSY
PRNG Busy (Read Only)
8
1
read-only
0
PRNG engine is idle
#0
1
Indicate that the PRNG engine is generating CRYPTO_PRNG_KEYx
#1
KEYSZ
PRNG Generate Key Size
2
2
read-write
0
64 bits
#00
1
128 bits
#01
2
192 bits
#10
3
256 bits
#11
SEEDRLD
Reload New Seed for PRNG Engine
1
1
read-write
0
Generating key based on the current seed
#0
1
Reload new seed
#1
START
Start PRNG Engine
0
1
read-write
0
Stop PRNG engine
#0
1
Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated
#1
PRNG_KEY0
CRYPTO_PRNG_KEY0
PRNG Generated Key0
0x10
read-only
n
0x0
0x0
KEY
Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
0
32
read-only
PRNG_KEY1
CRYPTO_PRNG_KEY1
PRNG Generated Key1
0x14
read-write
n
0x0
0x0
PRNG_KEY2
CRYPTO_PRNG_KEY2
PRNG Generated Key2
0x18
read-write
n
0x0
0x0
PRNG_KEY3
CRYPTO_PRNG_KEY3
PRNG Generated Key3
0x1C
read-write
n
0x0
0x0
PRNG_KEY4
CRYPTO_PRNG_KEY4
PRNG Generated Key4
0x20
read-write
n
0x0
0x0
PRNG_KEY5
CRYPTO_PRNG_KEY5
PRNG Generated Key5
0x24
read-write
n
0x0
0x0
PRNG_KEY6
CRYPTO_PRNG_KEY6
PRNG Generated Key6
0x28
read-write
n
0x0
0x0
PRNG_KEY7
CRYPTO_PRNG_KEY7
PRNG Generated Key7
0x2C
read-write
n
0x0
0x0
PRNG_SEED
CRYPTO_PRNG_SEED
Seed for PRNG
0xC
write-only
n
0x0
0x0
SEED
Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.
0
32
write-only
DAC
DAC Register Map
DAC
0x0
0x0
0x18
registers
n
DAC0_CTL
DAC0_CTL
DAC0 Control Register
0x0
read-write
n
0x0
0x0
BWSEL
DAC Data Bit-width Selection
14
2
read-write
0
data is 12 bits
#00
1
data is 8 bits
#01
BYPASS
Bypass Buffer Mode
8
1
read-write
0
Output voltage buffer Enabled
#0
1
Output voltage buffer Disabled
#1
DACEN
DAC Enable Bit
0
1
read-write
0
DAC Disabled
#0
1
DAC Enabled
#1
DACIEN
DAC Interrupt Enable Bit
1
1
read-write
0
DAC interrupt Disabled
#0
1
DAC interrupt Enabled
#1
DMAEN
DMA Mode Enable Bit
2
1
read-write
0
DMA mode Disabled
#0
1
DMA mode Enabled
#1
DMAURIEN
DMA Under-run Interrupt Enable Bit
3
1
read-write
0
DMA interrupt Disabled
#0
1
DMA under-run interrupt Enabled
#1
ETRGSEL
External Pin Trigger Selection
12
2
read-write
0
Low level trigger
#00
1
High level trigger
#01
2
Falling edge trigger
#10
3
Rising edge trigger
#11
LALIGN
DAC Data Left-aligned Enabled Bit\nNote: Only for 12 bit mode.
10
1
read-write
0
Right alignment
#0
1
Left alignment
#1
TRGEN
Trigger Mode Enable Bit
4
1
read-write
0
DAC event trigger mode Disabled
#0
1
DAC event trigger mode Enabled
#1
TRGSEL
Trigger Source Selection
5
3
read-write
0
Software trigger
#000
1
External pin DAC0_ST trigger
#001
2
Timer 0 trigger
#010
3
Timer 1 trigger
#011
4
Timer 2 trigger
#100
5
Timer 3 trigger
#101
DAC0_DAT
DAC0_DAT
DAC0 Data Holding Register
0x8
read-write
n
0x0
0x0
DACDAT
DAC 12-bit Holding Data\nThe unused bits (DAC0_DAT[3:0] in left-alignment mode and DAC0_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12 bit left alignment: user has to load data into DAC0_DAT[15:4] bits.\n12 bit right alignment: user has to load data into DAC0_DAT[11:0] bits.\nDAC 8-bit Holding Data\nThe unused bits DAC0_DAT[15:8] are ignored by DAC controller hardware.\nNote: Conversion data and DAC output data is 12-bit.
0
16
read-write
DAC0_DATOUT
DAC0_DATOUT
DAC0 Data Output Register
0xC
read-only
n
0x0
0x0
DATOUT
DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly.
0
12
read-only
DAC0_STATUS
DAC0_STATUS
DAC0 Status Register
0x10
read-write
n
0x0
0x0
BUSY
DAC Busy Flag (Read Only)
8
1
read-only
0
DAC is ready for next conversion
#0
1
DAC is busy in conversion
#1
DMAUDR
DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit.
1
1
read-write
0
No DMA under-run error condition occurred
#0
1
DMA under-run error condition occurred
#1
FINISH
DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0.
0
1
read-write
0
DAC is in conversion state
#0
1
DAC conversion finish
#1
DAC0_SWTRG
DAC0_SWTRG
DAC0 Software Trigger Control Register
0x4
read-write
n
0x0
0x0
SWTRG
Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; reading this bit will always get 0.
0
1
read-write
0
Software trigger Disabled
#0
1
Software trigger Enabled
#1
DAC0_TCTL
DAC0_TCTL
DAC0 Timing Control Register
0x14
read-write
n
0x0
0x0
SETTLET
DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example, DAC controller clock speed is 50 MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x32.
0
10
read-write
EADC
EADC Register Map
EADC
0x0
0x0
0x60
registers
n
0x110
0x4
registers
n
0x130
0x4
registers
n
0x140
0x40
registers
n
0x208
0x4
registers
n
0x80
0x4C
registers
n
0xD0
0x30
registers
n
CMP0
EADC_CMP0
ADC Result Compare Register 0
0xE0
read-write
n
0x0
0x0
CMPCOND
Compare Condition
2
1
read-write
0
Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#1
CMPDAT
Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
16
12
read-write
CMPMCNT
Compare Match Count
8
4
read-write
CMPSPL
Compare Sample Module Selection
3
5
read-write
0
Sample Module 0 conversion result EADC_DAT0 is selected to be compared
#00000
1
Sample Module 1 conversion result EADC_DAT1 is selected to be compared
#00001
2
Sample Module 2 conversion result EADC_DAT2 is selected to be compared
#00010
3
Sample Module 3 conversion result EADC_DAT3 is selected to be compared
#00011
4
Sample Module 4 conversion result EADC_DAT4 is selected to be compared
#00100
5
Sample Module 5 conversion result EADC_DAT5 is selected to be compared
#00101
6
Sample Module 6 conversion result EADC_DAT6 is selected to be compared
#00110
7
Sample Module 7 conversion result EADC_DAT7 is selected to be compared
#00111
8
Sample Module 8 conversion result EADC_DAT8 is selected to be compared
#01000
9
Sample Module 9 conversion result EADC_DAT9 is selected to be compared
#01001
10
Sample Module 10 conversion result EADC_DAT10 is selected to be compared
#01010
11
Sample Module 11 conversion result EADC_DAT11 is selected to be compared
#01011
12
Sample Module 12 conversion result EADC_DAT12 is selected to be compared
#01100
13
Sample Module 13 conversion result EADC_DAT13 is selected to be compared
#01101
14
Sample Module 14 conversion result EADC_DAT14 is selected to be compared
#01110
15
Sample Module 15 conversion result EADC_DAT15 is selected to be compared
#01111
16
Sample Module 16 conversion result EADC_DAT16 is selected to be compared
#10000
17
Sample Module 17 conversion result EADC_DAT17 is selected to be compared
#10001
18
Sample Module 18 conversion result EADC_DAT18 is selected to be compared
#10010
CMPWEN
Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
15
1
read-write
0
EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
#0
1
EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched
#1
EADCMPEN
ADC Result Compare Enable Bit
0
1
read-write
0
Compare Disabled
#0
1
Compare Enabled
#1
EADCMPIE
ADC Result Compare Interrupt Enable Bit
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMP1
EADC_CMP1
ADC Result Compare Register 1
0xE4
read-write
n
0x0
0x0
CMP2
EADC_CMP2
ADC Result Compare Register 2
0xE8
read-write
n
0x0
0x0
CMP3
EADC_CMP3
ADC Result Compare Register 3
0xEC
read-write
n
0x0
0x0
CTL
EADC_CTL
ADC Control Register
0x50
read-write
n
0x0
0x0
EADCEN
ADC Converter Enable Bit\nNote: Before starting ADC conversion function, this bit should be set to 1. Clear it to 0 to disable ADC converter analog circuit power consumption.
0
1
read-write
0
Disabled EADC
#0
1
Enabled EADC
#1
EADCIEN0
Specific Sample Module ADC ADINT0 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion. If EADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
2
1
read-write
0
Specific sample module ADC ADINT0 interrupt function Disabled
#0
1
Specific sample module ADC ADINT0 interrupt function Enabled
#1
EADCIEN1
Specific Sample Module ADC ADINT1 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion. If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
3
1
read-write
0
Specific sample module ADC ADINT1 interrupt function Disabled
#0
1
Specific sample module ADC ADINT1 interrupt function Enabled
#1
EADCIEN2
Specific Sample Module ADC ADINT2 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion. If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
4
1
read-write
0
Specific sample module ADC ADINT2 interrupt function Disabled
#0
1
Specific sample module ADC ADINT2 interrupt function Enabled
#1
EADCIEN3
Specific Sample Module ADC ADINT3 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion. If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
5
1
read-write
0
Specific sample module ADC ADINT3 interrupt function Disabled
#0
1
Specific sample module ADC ADINT3 interrupt function Enabled
#1
EADCRST
EADC ADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset. When EADC reset end, the EADCRST bit is automatically cleared to 0.
1
1
read-write
0
No effect
#0
1
Cause EADC control circuits reset to initial state, but not change the EADC registers value
#1
CURDAT
EADC_CURDAT
EADC PDMA Current Transfer Data Register
0x4C
read-only
n
0x0
0x0
CURDAT
EADC PDMA Current Transfer Data (Read Only)\nNote: After PDMA reads this register, the VAILD of the shadow EADC_DAT register will be automatically cleared.
0
19
read-only
DAT0
EADC_DAT0
ADC Data Register 0 for Sample Module 0
0x0
read-only
n
0x0
0x0
OV
Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read.
16
1
read-only
0
Data in RESULT[11:0] is recent conversion result
#0
1
Data in RESULT[11:0] is overwrite
#1
RESULT
ADC Conversion Result\nThis field contains 12 bits conversion result.
0
16
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
17
1
read-only
0
Data in RESULT[11:0] bits is not valid
#0
1
Data in RESULT[11:0] bits is valid
#1
DAT1
EADC_DAT1
ADC Data Register 1 for Sample Module 1
0x4
read-write
n
0x0
0x0
DAT10
EADC_DAT10
ADC Data Register 10 for Sample Module 10
0x28
read-write
n
0x0
0x0
DAT11
EADC_DAT11
ADC Data Register 11 for Sample Module 11
0x2C
read-write
n
0x0
0x0
DAT12
EADC_DAT12
ADC Data Register 12 for Sample Module 12
0x30
read-write
n
0x0
0x0
DAT13
EADC_DAT13
ADC Data Register 13 for Sample Module 13
0x34
read-write
n
0x0
0x0
DAT14
EADC_DAT14
ADC Data Register 14 for Sample Module 14
0x38
read-write
n
0x0
0x0
DAT15
EADC_DAT15
ADC Data Register 15 for Sample Module 15
0x3C
read-write
n
0x0
0x0
DAT16
EADC_DAT16
ADC Data Register 16 for Sample Module 16
0x40
read-write
n
0x0
0x0
DAT17
EADC_DAT17
ADC Data Register 17 for Sample Module 17
0x44
read-write
n
0x0
0x0
DAT18
EADC_DAT18
ADC Data Register 18 for Sample Module 18
0x48
read-write
n
0x0
0x0
DAT2
EADC_DAT2
ADC Data Register 2 for Sample Module 2
0x8
read-write
n
0x0
0x0
DAT3
EADC_DAT3
ADC Data Register 3 for Sample Module 3
0xC
read-write
n
0x0
0x0
DAT4
EADC_DAT4
ADC Data Register 4 for Sample Module 4
0x10
read-write
n
0x0
0x0
DAT5
EADC_DAT5
ADC Data Register 5 for Sample Module 5
0x14
read-write
n
0x0
0x0
DAT6
EADC_DAT6
ADC Data Register 6 for Sample Module 6
0x18
read-write
n
0x0
0x0
DAT7
EADC_DAT7
ADC Data Register 7 for Sample Module 7
0x1C
read-write
n
0x0
0x0
DAT8
EADC_DAT8
ADC Data Register 8 for Sample Module 8
0x20
read-write
n
0x0
0x0
DAT9
EADC_DAT9
ADC Data Register 9 for Sample Module 9
0x24
read-write
n
0x0
0x0
INTSRC0
EADC_INTSRC0
EADC Interrupt 0 Source Enable Control Register.
0xD0
read-write
n
0x0
0x0
SPLIE0
Sample Module 0 Interrupt Enable Bit
0
1
read-write
0
Sample Module 0 interrupt Disabled
#0
1
Sample Module 0 interrupt Enabled
#1
SPLIE1
Sample Module 1 Interrupt Enable Bit
1
1
read-write
0
Sample Module 1 interrupt Disabled
#0
1
Sample Module 1 interrupt Enabled
#1
SPLIE10
Sample Module 10 Interrupt Enable Bit
10
1
read-write
0
Sample Module 10 interrupt Disabled
#0
1
Sample Module 10 interrupt Enabled
#1
SPLIE11
Sample Module 11 Interrupt Enable Bit
11
1
read-write
0
Sample Module 11 interrupt Disabled
#0
1
Sample Module 11 interrupt Enabled
#1
SPLIE12
Sample Module 12 Interrupt Enable Bit
12
1
read-write
0
Sample Module 12 interrupt Disabled
#0
1
Sample Module 12 interrupt Enabled
#1
SPLIE13
Sample Module 13 Interrupt Enable Bit
13
1
read-write
0
Sample Module 13 interrupt Disabled
#0
1
Sample Module 13 interrupt Enabled
#1
SPLIE14
Sample Module 14 Interrupt Enable Bit
14
1
read-write
0
Sample Module 14 interrupt Disabled
#0
1
Sample Module 14 interrupt Enabled
#1
SPLIE15
Sample Module 15 Interrupt Enable Bit
15
1
read-write
0
Sample Module 15 interrupt Disabled
#0
1
Sample Module 15 interrupt Enabled
#1
SPLIE16
Sample Module 16 Interrupt Enable Bit
16
1
read-write
0
Sample Module 16 interrupt Disabled
#0
1
Sample Module 16 interrupt Enabled
#1
SPLIE17
Sample Module 17 Interrupt Enable Bit
17
1
read-write
0
Sample Module 17 interrupt Disabled
#0
1
Sample Module 17 interrupt Enabled
#1
SPLIE18
Sample Module 18 Interrupt Enable Bit
18
1
read-write
0
Sample Module 18 interrupt Disabled
#0
1
Sample Module 18 interrupt Enabled
#1
SPLIE2
Sample Module 2 Interrupt Enable Bit
2
1
read-write
0
Sample Module 2 interrupt Disabled
#0
1
Sample Module 2 interrupt Enabled
#1
SPLIE3
Sample Module 3 Interrupt Enable Bit
3
1
read-write
0
Sample Module 3 interrupt Disabled
#0
1
Sample Module 3 interrupt Enabled
#1
SPLIE4
Sample Module 4 Interrupt Enable Bit
4
1
read-write
0
Sample Module 4 interrupt Disabled
#0
1
Sample Module 4 interrupt Enabled
#1
SPLIE5
Sample Module 5 Interrupt Enable Bit
5
1
read-write
0
Sample Module 5 interrupt Disabled
#0
1
Sample Module 5 interrupt Enabled
#1
SPLIE6
Sample Module 6 Interrupt Enable Bit
6
1
read-write
0
Sample Module 6 interrupt Disabled
#0
1
Sample Module 6 interrupt Enabled
#1
SPLIE7
Sample Module 7 Interrupt Enable Bit
7
1
read-write
0
Sample Module 7 interrupt Disabled
#0
1
Sample Module 7 interrupt Enabled
#1
SPLIE8
Sample Module 8 Interrupt Enable Bit
8
1
read-write
0
Sample Module 8 interrupt Disabled
#0
1
Sample Module 8 interrupt Enabled
#1
SPLIE9
Sample Module 9 Interrupt Enable Bit
9
1
read-write
0
Sample Module 9 interrupt Disabled
#0
1
Sample Module 9 interrupt Enabled
#1
INTSRC1
EADC_INTSRC1
EADC Interrupt 1 Source Enable Control Register.
0xD4
read-write
n
0x0
0x0
INTSRC2
EADC_INTSRC2
EADC Interrupt 2 Source Enable Control Register.
0xD8
read-write
n
0x0
0x0
INTSRC3
EADC_INTSRC3
EADC Interrupt 3 Source Enable Control Register.
0xDC
read-write
n
0x0
0x0
M0CTL1
EADC_M0CTL1
ADC Sample Module0 Control Register 1
0x140
read-write
n
0x0
0x0
ACU
Number of Accumulated Conversion Results Selection
4
4
read-write
0
1 conversion result will be accumulated
#0000
1
2 conversion result will be accumulated
#0001
2
4 conversion result will be accumulated
#0010
3
8 conversion result will be accumulated
#0011
4
16 conversion result will be accumulated
#0100
5
32 conversion result will be accumulated
#0101
6
64 conversion result will be accumulated
#0110
7
128 conversion result will be accumulated
#0111
8
256 conversion result will be accumulated
#1000
ALIGN
Alignment Selection
0
1
read-write
0
The conversion result will be right aligned in data register
#0
1
The conversion result will be left aligned in data register
#1
AVG
Average Mode Selection
1
1
read-write
0
Conversion results will be stored in data register without averaging
#0
1
Conversion results in data register will be averaged
#1
M10CTL1
EADC_M10CTL1
ADC Sample Module10 Control Register 1
0x168
read-write
n
0x0
0x0
M11CTL1
EADC_M11CTL1
ADC Sample Module11 Control Register 1
0x16C
read-write
n
0x0
0x0
M12CTL1
EADC_M12CTL1
ADC Sample Module12 Control Register 1
0x170
read-write
n
0x0
0x0
M13CTL1
EADC_M13CTL1
ADC Sample Module13 Control Register 1
0x174
read-write
n
0x0
0x0
M14CTL1
EADC_M14CTL1
ADC Sample Module14 Control Register 1
0x178
read-write
n
0x0
0x0
M15CTL1
EADC_M15CTL1
ADC Sample Module15 Control Register 1
0x17C
read-write
n
0x0
0x0
M1CTL1
EADC_M1CTL1
ADC Sample Module1 Control Register 1
0x144
read-write
n
0x0
0x0
M2CTL1
EADC_M2CTL1
ADC Sample Module2 Control Register 1
0x148
read-write
n
0x0
0x0
M3CTL1
EADC_M3CTL1
ADC Sample Module3 Control Register 1
0x14C
read-write
n
0x0
0x0
M4CTL1
EADC_M4CTL1
ADC Sample Module4 Control Register 1
0x150
read-write
n
0x0
0x0
M5CTL1
EADC_M5CTL1
ADC Sample Module5 Control Register 1
0x154
read-write
n
0x0
0x0
M6CTL1
EADC_M6CTL1
ADC Sample Module6 Control Register 1
0x158
read-write
n
0x0
0x0
M7CTL1
EADC_M7CTL1
ADC Sample Module7 Control Register 1
0x15C
read-write
n
0x0
0x0
M8CTL1
EADC_M8CTL1
ADC Sample Module8 Control Register 1
0x160
read-write
n
0x0
0x0
M9CTL1
EADC_M9CTL1
ADC Sample Module9 Control Register 1
0x164
read-write
n
0x0
0x0
OFFSETCAL
EADC_OFFSETCAL
ADC Result Offset Cancellation Register
0x208
read-write
n
0x0
0x0
OFFSETCANCEL
ADC Offset Cancellation Trim Bits\nWhen CALEN(EADC_CTL[8]) is set to 1, the offset cancellation trim bits will compensate ADC result offset. When this bit is set to 0, the offset cancellation trim bits have no effect to ADC result.\nNote1:These 5 bits trim value wouln't latched into EADC_OFFSETCAL automatically when Flash initalization. User must read DCR2 by ISP command first, then write the value to OFFSETCANCEL. \nNote2: OFFSETCANCEL is signed format. OFFSETCANCEL will sign extension to 12 bit by hardware to perform signed addition with EADC conversion result if CALEN is enabled.
0
5
read-write
OVSTS
EADC_OVSTS
ADC Sample Module Start of Conversion Overrun Flag Register
0x5C
read-write
n
0x0
0x0
SPOVF
ADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it.
0
19
read-write
0
No sample module event overrun
0
1
Indicates a new sample module event is generated while an old one event is pending
1
PDMACTL
EADC_PDMACTL
ADC PDMA Control Register
0x130
read-write
n
0x0
0x0
PDMATEN
PDMA Transfer Enable Bit\nWhen EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
0
19
read-write
0
PDMA data transfer Disabled
0
1
PDMA data transfer Enabled
1
PENDSTS
EADC_PENDSTS
ADC Start of Conversion Pending Flag Register
0x58
read-write
n
0x0
0x0
STPF
ADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation:
0
19
read-write
0
There is no pending conversion for sample module
0
1
Sample module EADC start of conversion is pending.\nClear pending flag and stop conversion for corresponding sample module
1
PWRCTL
EADC_PWRCTL
EADC Power Management Control Register
0x110
read-write
n
0x0
0x0
AUTOFF
Auto Off Mode
5
1
read-write
0
Auto off function Disabled
#0
1
Auto off function Enabled. When AUTOFF is set to 1, EADC will be powered off automatically to save power
#1
AUTOPDTHT
Auto Power Down Threshold Time
20
4
read-write
7
8 EADC clock for power down threshold time
#0111
8
16 EADC clock for power down threshold time
#1000
9
32 EADC clock for power down threshold time
#1001
10
64 EADC clock for power down threshold time
#1010
11
128 EADC clock for power down threshold time
#1011
12
256 EADC clock for power down threshold time
#1100
READY
EADC Start-up Completely and Ready for Conversion (Read Only)
0
1
read-only
0
Power-on sequence is still in progress
#0
1
EADC is ready for conversion
#1
STUPT
EADC Start-up Time\nSet this bit fields to adjust start-up time. The minimum start-up time of EADC is 10us.
8
12
read-write
SCTL0
EADC_SCTL0
ADC Sample Module 0 Control Register
0x80
read-write
n
0x0
0x0
CHSEL
ADC Sample Module Channel Selection\n Note: When internal EADC channel16, 17 or 18 is selected, EADC_CH15 is useless.
0
4
read-write
EXTFEN
ADC External Trigger Falling Edge Enable Bit
5
1
read-write
0
Falling edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Falling edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTREN
ADC External Trigger Rising Edge Enable Bit
4
1
read-write
0
Rising edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Rising edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTSMPT
EADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. EXTSMPT can be set from 0~8'd251.
24
8
read-write
INTPOS
Interrupt Flag Position Select
22
1
read-write
0
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion
#0
1
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion
#1
TRGDLYCNT
ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1, trigger delay time is actullay the same as TRGDLYCNT is set to 2 for hardware operation.
8
8
read-write
TRGDLYDIV
ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:
6
2
read-write
0
EADC_CLK/1
#00
1
EADC_CLK/2
#01
2
EADC_CLK/4
#10
3
EADC_CLK/16
#11
TRGSEL
ADC Sample Module Start of Conversion Trigger Source Selection
16
5
read-write
SCTL1
EADC_SCTL1
ADC Sample Module 1 Control Register
0x84
read-write
n
0x0
0x0
SCTL10
EADC_SCTL10
ADC Sample Module 10 Control Register
0xA8
read-write
n
0x0
0x0
SCTL11
EADC_SCTL11
ADC Sample Module 11 Control Register
0xAC
read-write
n
0x0
0x0
SCTL12
EADC_SCTL12
ADC Sample Module 12 Control Register
0xB0
read-write
n
0x0
0x0
SCTL13
EADC_SCTL13
ADC Sample Module 13 Control Register
0xB4
read-write
n
0x0
0x0
SCTL14
EADC_SCTL14
ADC Sample Module 14 Control Register
0xB8
read-write
n
0x0
0x0
SCTL15
EADC_SCTL15
ADC Sample Module 15 Control Register
0xBC
read-write
n
0x0
0x0
SCTL16
EADC_SCTL16
ADC Sample Module 16 Control Register
0xC0
read-write
n
0x0
0x0
EXTSMPT
EADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time. EXTSMPT can be set from 0~8'd255.\nThe range of start delay time is from 0~255 EADC clock.
24
8
read-write
SCTL17
EADC_SCTL17
ADC Sample Module 17 Control Register
0xC4
read-write
n
0x0
0x0
SCTL18
EADC_SCTL18
ADC Sample Module 18 Control Register
0xC8
read-write
n
0x0
0x0
SCTL2
EADC_SCTL2
ADC Sample Module 2 Control Register
0x88
read-write
n
0x0
0x0
SCTL3
EADC_SCTL3
ADC Sample Module 3 Control Register
0x8C
read-write
n
0x0
0x0
SCTL4
EADC_SCTL4
ADC Sample Module 4 Control Register
0x90
read-write
n
0x0
0x0
CHSEL
ADC Sample Module Channel Selection\nNote: when internal EADC channel16, 17 or 18 is selected, EADC_CH15 is useless.
0
4
read-write
EXTFEN
ADC External Trigger Falling Edge Enable Bit
5
1
read-write
0
Falling edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Falling edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTREN
ADC External Trigger Rising Edge Enable Bit
4
1
read-write
0
Rising edge Disabled when ADC selects EADC0_ST as trigger source
#0
1
Rising edge Enabled when ADC selects EADC0_ST as trigger source
#1
EXTSMPT
EADC Sampling Time Extend\nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend ADC sampling time after trigger source is coming to get enough sampling time.EXTSMPT can be set from 0~8'd251.
24
8
read-write
INTPOS
Interrupt Flag Position Select
22
1
read-write
0
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion
#0
1
Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion
#1
TRGDLYCNT
ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1, Trigger delay time is actullay the same as TRGDLYCNT is set to 2 for hardware operation.
8
8
read-write
TRGDLYDIV
ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:
6
2
read-write
0
EADC_CLK/1
#00
1
EADC_CLK/2
#01
2
EADC_CLK/4
#10
3
EADC_CLK/16
#11
TRGSEL
ADC Sample Module Start of Conversion Trigger Source Selection
16
5
read-write
SCTL5
EADC_SCTL5
ADC Sample Module 5 Control Register
0x94
read-write
n
0x0
0x0
SCTL6
EADC_SCTL6
ADC Sample Module 6 Control Register
0x98
read-write
n
0x0
0x0
SCTL7
EADC_SCTL7
ADC Sample Module 7 Control Register
0x9C
read-write
n
0x0
0x0
SCTL8
EADC_SCTL8
ADC Sample Module 8 Control Register
0xA0
read-write
n
0x0
0x0
SCTL9
EADC_SCTL9
ADC Sample Module 9 Control Register
0xA4
read-write
n
0x0
0x0
STATUS0
EADC_STATUS0
ADC Status Register 0
0xF0
read-only
n
0x0
0x0
OV
EADC_DAT0~15 Overrun Flag
16
16
read-only
VALID
EADC_DAT0~15 Data Valid Flag
0
16
read-only
STATUS1
EADC_STATUS1
ADC Status Register 1
0xF4
read-only
n
0x0
0x0
OV
EADC_DAT16~18 Overrun Flag
16
3
read-only
VALID
EADC_DAT16~18 Data Valid Flag
0
3
read-only
STATUS2
EADC_STATUS2
ADC Status Register 2
0xF8
read-write
n
0x0
0x0
ADIF0
ADC ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed
0
1
read-write
0
No ADINT0 interrupt pulse received
#0
1
ADINT0 interrupt pulse has been received
#1
ADIF1
ADC ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed
1
1
read-write
0
No ADINT1 interrupt pulse received
#0
1
ADINT1 interrupt pulse has been received
#1
ADIF2
ADC ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it. \nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed
2
1
read-write
0
No ADINT2 interrupt pulse received
#0
1
ADINT2 interrupt pulse has been received
#1
ADIF3
ADC ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed
3
1
read-write
0
No ADINT3 interrupt pulse received
#0
1
ADINT3 interrupt pulse has been received
#1
ADOVIF
All ADC Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
24
1
read-write
0
None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#0
1
Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#1
ADOVIF0
ADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
ADINT0 interrupt flag is not overwritten to 1
#0
1
ADINT0 interrupt flag is overwritten to 1
#1
ADOVIF1
ADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
9
1
read-write
0
ADINT1 interrupt flag is not overwritten to 1
#0
1
ADINT1 interrupt flag is overwritten to 1
#1
ADOVIF2
ADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
10
1
read-write
0
ADINT2 interrupt flag is not overwritten to 1
#0
1
ADINT2 interrupt flag is overwritten to 1
#1
ADOVIF3
ADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
11
1
read-write
0
ADINT3 interrupt flag is not overwritten to 1
#0
1
ADINT3 interrupt flag is overwritten to 1
#1
AOV
All Sample Module ADC Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVn Flag is equal to 1.
27
1
read-write
0
None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1
#0
1
Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1
#1
AVALID
All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1.
26
1
read-write
0
None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
#0
1
Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
#1
BUSY
ADC Conveter Busy/Idle Status (Read Only)\nNote: Once a trigger source is coming, this bit must wait 2 EADC_CLK synchronization then the BUSY status will be high. The status will be high to low when the current conversion is finished.
23
1
read-only
0
EADC is in idle state
#0
1
EADC is busy for sample or conversion
#1
CHANNEL
Current Conversion Channel (Read Only)
16
5
read-only
EADCMPF0
EADC Compare 0 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
4
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP0 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP0 register setting
#1
EADCMPF1
EADC Compare 1 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
5
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP1 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP1 register setting
#1
EADCMPF2
EADC Compare 2 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
6
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP2 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP2 register setting
#1
EADCMPF3
EADC Compare 3 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
7
1
read-write
0
Conversion result in EADC_DAT does not meet EADC_CMP3 register setting
#0
1
Conversion result in EADC_DAT meets EADC_CMP3 register setting
#1
EADCMPO0
EADC Compare 0 Output Status\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
12
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT0 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT0 setting
#1
EADCMPO1
EADC Compare 1 Output Status\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
13
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT1 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT1 setting
#1
EADCMPO2
EADC Compare 2 Output Status\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
14
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT2 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT2 setting
#1
EADCMPO3
EADC Compare 3 Output Status\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.
15
1
read-write
0
Conversion result in EADC_DAT is less than CMPDAT3 setting
#0
1
Conversion result in EADC_DAT is greater than or equal to CMPDAT3 setting
#1
STOVF
All ADC Sample Module Start of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1.
25
1
read-write
0
None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
#0
1
Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
#1
STATUS3
EADC_STATUS3
ADC Status Register 3
0xFC
read-only
n
0x0
0x0
CURSPL
EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle, the bit filed will be set to 0x1F.
0
5
read-only
SWTRG
EADC_SWTRG
ADC Sample Module Software Start Register
0x54
write-only
n
0x0
0x0
SWTRG
ADC Sample Module 0~18 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
0
19
write-only
0
No effect
0
1
Cause an EADC conversion when the priority is given to sample module
1
EBI
EBI Register Map
EBI
0x0
0x0
0x8
registers
n
0x10
0x8
registers
n
0x20
0x8
registers
n
CTL0
EBI_CTL0
External Bus Interface Bank0 Control Register
0x0
read-write
n
0x0
0x0
CACCESS
Continuous Data Access Mode\nWhen con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
4
1
read-write
0
Continuous data access mode Disabled
#0
1
Continuous data access mode Enabled
#1
CSPOLINV
Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS).
2
1
read-write
0
Chip select pin (EBI_nCS) is active low
#0
1
Chip select pin (EBI_nCS) is active high
#1
DW16
EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit.
1
1
read-write
0
EBI data width is 8-bit
#0
1
EBI data width is 16-bit
#1
EN
EBI Enable Bit\nThis bit is the functional enable bit for EBI.
0
1
read-write
0
EBI function Disabled
#0
1
EBI function Enabled
#1
MCLKDIV
External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
8
3
read-write
0
HCLK/1
#000
1
HCLK/2
#001
2
HCLK/4
#010
3
HCLK/8
#011
4
HCLK/16
#100
5
HCLK/32
#101
6
HCLK/64
#110
7
HCLK/128
#111
TALE
Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register
16
3
read-write
WBUFEN
EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register
24
1
read-write
0
EBI write buffer Disabled
#0
1
EBI write buffer Enabled
#1
CTL1
EBI_CTL1
External Bus Interface Bank1 Control Register
0x10
read-write
n
0x0
0x0
CTL2
EBI_CTL2
External Bus Interface Bank2 Control Register
0x20
read-write
n
0x0
0x0
TCTL0
EBI_TCTL0
External Bus Interface Bank0 Timing Control Register
0x4
read-write
n
0x0
0x0
R2R
Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
24
4
read-write
RAHDOFF
Access Hold Time Disable Control When Read
22
1
read-write
0
Data Access Hold Time (tAHD) during EBI reading Enabled
#0
1
Data Access Hold Time (tAHD) during EBI reading Disabled
#1
TACC
EBI Data Access Time\nTACC defines data access time (tACC).
3
5
read-write
TAHD
EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD).
8
3
read-write
W2X
Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
12
4
read-write
WAHDOFF
Access Hold Time Disable Control When Write
23
1
read-write
0
Data Access Hold Time (tAHD) during EBI writing Enabled
#0
1
Data Access Hold Time (tAHD) during EBI writing Disabled
#1
TCTL1
EBI_TCTL1
External Bus Interface Bank1 Timing Control Register
0x14
read-write
n
0x0
0x0
TCTL2
EBI_TCTL2
External Bus Interface Bank2 Timing Control Register
0x24
read-write
n
0x0
0x0
FMC
FMC Register Map
FMC
0x0
0x0
0x14
registers
n
0x18
0x4
registers
n
0x40
0x4
registers
n
0x4C
0x4
registers
n
0x80
0x10
registers
n
0xC0
0x8
registers
n
0xD0
0x8
registers
n
0xE0
0x4
registers
n
CYCCTL
FMC_CYCCTL
Flash Access Cycle Control Register
0x4C
read-write
n
0x0
0x0
CYCLE
Flash Access Cycle Control (Write Protect) \n The optimized HCLK working frequency range is 33~50 MHz\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
4
read-write
1
CPU access with zero wait cycle if cache hit or cache is disabled; Flash access cycle is 1;
#0001
2
CPU access with one wait cycles if cache miss; Flash access cycle is 2;
#0010
3
CPU access with two wait cycles if cahce miss; Flash access cycle is 3;
#0011
FTCTL
FMC_FTCTL
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
CACHEINV
Flash Cache Invalidation (Write Protect)\nNote1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.\nNote2: This bit is write-protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
Flash Cache Invalidation finished (default)
#0
1
Flash Cache Invalidation
#1
ISPADDR
FMC_ISPADDR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADDR
ISP Address\nThe NuMicro M23 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
0
32
read-write
ISPCMD
FMC_ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
CMD
ISP Command\nISP command table is shown below:\nThe other commands are invalid.
0
7
read-write
0
FLASH Read
0x00
4
Read Unique ID
0x04
8
Read Flash All-One Result
0x08
11
Read Company ID
0x0b
12
Read Device ID
0x0c
13
Read Checksum
0x0d
33
FLASH 32-bit Program
0x21
34
FLASH Page Erase
0x22
38
FLASH Mass Erase
0x26
39
FLASH Multi-Word Program
0x27
40
Run Flash All-One Verification
0x28
45
Run Checksum Calculation
0x2d
46
Vector Remap
0x2e
ISPCTL
FMC_ISPCTL
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
APROM cannot be updated when the chip runs in APROM
#0
1
APROM can be updated when the chip runs in APROM
#1
BS
Boot Select (Write Protect)\n/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset or system reset is happened\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Booting from APROM
#0
1
Booting from LDROM
#1
CFGUEN
CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
CONFIG cannot be updated
#0
1
CONFIG can be updated
#1
ISPEN
ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(9) The wrong setting of page erase ISP CMD in XOM\n(10) Violate XOM setting one time protection \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
LDUEN
LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated
#1
ISPDAT
FMC_ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPSTS
FMC_ISPSTS
ISP Status Register
0x40
read-write
n
0x0
0x0
ALLONE
Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit also can be clear by writing 1
7
1
read-write
0
Flash bits are not all 1 after 'Run Flash All-One Verification' complete
#0
1
All of Flash bits are 1 after 'Run Flash All-One Verification' complete
#1
CBS
Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset or system reset is happened.
1
2
read-only
0
LDROM with IAP mode
#00
1
LDROM without IAP mode
#01
2
APROM with IAP mode
#10
3
APROM without IAP mode
#11
ISPBUSY
ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP operation is finished
#0
1
ISP is progressed
#1
ISPFF
ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(9) The wrong setting of page erase ISP CMD in XOM\n(10) Violate XOM setting one time protection \nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
6
1
read-write
PGFF
Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
5
1
read-only
0
Flash Program is success
#0
1
Flash Program is fail. Program data is different with data in the Flash memory
#1
VECMAP
Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}.\nVECMAP [18:12] should be 0.
9
21
read-only
ISPTRG
FMC_ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
ISP operation is finished
#0
1
ISP is progressed
#1
MPADDR
FMC_MPADDR
ISP Multi-program Address Register
0xC4
read-only
n
0x0
0x0
MPADDR
ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
0
32
read-only
MPDAT0
FMC_MPDAT0
ISP Data0 Register
0x80
read-write
n
0x0
0x0
ISPDAT0
ISP Data 0\nThis register is the first 32-bit data for 32-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
0
32
read-write
MPDAT1
FMC_MPDAT1
ISP Data1 Register
0x84
read-write
n
0x0
0x0
ISPDAT1
ISP Data 1\nThis register is the second 32-bit data for multi-word programming.
0
32
read-write
MPDAT2
FMC_MPDAT2
ISP Data2 Register
0x88
read-write
n
0x0
0x0
ISPDAT2
ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
0
32
read-write
MPDAT3
FMC_MPDAT3
ISP Data3 Register
0x8C
read-write
n
0x0
0x0
ISPDAT3
ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
0
32
read-write
MPSTS
FMC_MPSTS
ISP Multi-program Status Register
0xC0
read-only
n
0x0
0x0
D0
ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
4
1
read-only
0
FMC_MPDAT0 register is empty, or program to Flash complete
#0
1
FMC_MPDAT0 register has been written, and not program to Flash complete
#1
D1
ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
5
1
read-only
0
FMC_MPDAT1 register is empty, or program to Flash complete
#0
1
FMC_MPDAT1 register has been written, and not program to Flash complete
#1
D2
ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
6
1
read-only
0
FMC_MPDAT2 register is empty, or program to Flash complete
#0
1
FMC_MPDAT2 register has been written, and not program to Flash complete
#1
D3
ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
7
1
read-only
0
FMC_MPDAT3 register is empty, or program to Flash complete
#0
1
FMC_MPDAT3 register has been written, and not program to Flash complete
#1
ISPFF
ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands.
2
1
read-only
MPBUSY
ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0
1
read-only
0
ISP Multi-Word program operation is finished
#0
1
ISP Multi-Word program operation is progressed
#1
PPGO
ISP Multi-program Status (Read Only)
1
1
read-only
0
ISP multi-word program operation is not active
#0
1
ISP multi-word program operation is in progress
#1
XOMR0STS0
FMC_XOMR0STS0
XOM Region 0 Status Register 0
0xD0
read-only
n
0x0
0x0
BASE
XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0.
0
24
read-only
XOMR0STS1
FMC_XOMR0STS1
XOM Region 0 Status Register 1
0xD4
read-only
n
0x0
0x0
SIZE
XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0.
0
9
read-only
XOMSTS
FMC_XOMSTS
XOM Status Register
0xE0
read-only
n
0x0
0x0
XOMPEF
XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
4
1
read-only
0
Success
#0
1
Fail
#1
XOMR0ON
XOM Region 0 On\nXOM Region 0 active status.
0
1
read-only
0
No active
#0
1
XOM region 0 is active
#1
GPIO
GPIO Register Map
GPIO
0x0
0x0
0x2C
registers
n
0x100
0x2C
registers
n
0x130
0x4
registers
n
0x140
0x2C
registers
n
0x170
0x4
registers
n
0x30
0x4
registers
n
0x40
0x2C
registers
n
0x440
0x4
registers
n
0x70
0x4
registers
n
0x80
0x2C
registers
n
0x800
0xB4
registers
n
0x8B8
0x40
registers
n
0x8FC
0x64
registers
n
0xB0
0x4
registers
n
0xC0
0x2C
registers
n
0xF0
0x4
registers
n
DBCTL
GPIO_DBCTL
Interrupt De-bounce Control Register
0x440
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection
0
4
read-write
0
Sample interrupt input once per 1 clocks
#0000
1
Sample interrupt input once per 2 clocks
#0001
2
Sample interrupt input once per 4 clocks
#0010
3
Sample interrupt input once per 8 clocks
#0011
4
Sample interrupt input once per 16 clocks
#0100
5
Sample interrupt input once per 32 clocks
#0101
6
Sample interrupt input once per 64 clocks
#0110
7
Sample interrupt input once per 128 clocks
#0111
8
Sample interrupt input once per 256 clocks
#1000
9
Sample interrupt input once per 2*256 clocks
#1001
10
Sample interrupt input once per 4*256 clocks
#1010
11
Sample interrupt input once per 8*256 clocks
#1011
12
Sample interrupt input once per 16*256 clocks
#1100
13
Sample interrupt input once per 32*256 clocks
#1101
14
Sample interrupt input once per 64*256 clocks
#1110
15
Sample interrupt input once per 128*256 clocks
#1111
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC)
#1
ICLKONx
Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. Each bit control each GPIO group.
16
6
read-write
0
Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1
0
1
All I/O pins edge detection circuit is always active after reset
1
PA0_PDIO
PA0_PDIO
GPIO PA.n Pin Data Input/Output Register
0x800
read-write
n
0x0
0x0
PDIO
GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).\nNote1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Corresponding GPIO pin set to low
#0
1
Corresponding GPIO pin set to high
#1
PA10_PDIO
PA10_PDIO
GPIO PA.n Pin Data Input/Output Register
0x828
read-write
n
0x0
0x0
PA11_PDIO
PA11_PDIO
GPIO PA.n Pin Data Input/Output Register
0x82C
read-write
n
0x0
0x0
PA12_PDIO
PA12_PDIO
GPIO PA.n Pin Data Input/Output Register
0x830
read-write
n
0x0
0x0
PA13_PDIO
PA13_PDIO
GPIO PA.n Pin Data Input/Output Register
0x834
read-write
n
0x0
0x0
PA14_PDIO
PA14_PDIO
GPIO PA.n Pin Data Input/Output Register
0x838
read-write
n
0x0
0x0
PA15_PDIO
PA15_PDIO
GPIO PA.n Pin Data Input/Output Register
0x83C
read-write
n
0x0
0x0
PA1_PDIO
PA1_PDIO
GPIO PA.n Pin Data Input/Output Register
0x804
read-write
n
0x0
0x0
PA2_PDIO
PA2_PDIO
GPIO PA.n Pin Data Input/Output Register
0x808
read-write
n
0x0
0x0
PA3_PDIO
PA3_PDIO
GPIO PA.n Pin Data Input/Output Register
0x80C
read-write
n
0x0
0x0
PA4_PDIO
PA4_PDIO
GPIO PA.n Pin Data Input/Output Register
0x810
read-write
n
0x0
0x0
PA5_PDIO
PA5_PDIO
GPIO PA.n Pin Data Input/Output Register
0x814
read-write
n
0x0
0x0
PA6_PDIO
PA6_PDIO
GPIO PA.n Pin Data Input/Output Register
0x818
read-write
n
0x0
0x0
PA7_PDIO
PA7_PDIO
GPIO PA.n Pin Data Input/Output Register
0x81C
read-write
n
0x0
0x0
PA8_PDIO
PA8_PDIO
GPIO PA.n Pin Data Input/Output Register
0x820
read-write
n
0x0
0x0
PA9_PDIO
PA9_PDIO
GPIO PA.n Pin Data Input/Output Register
0x824
read-write
n
0x0
0x0
PA_DATMSK
PA_DATMSK
PA Data Output Write Mask
0xC
read-write
n
0x0
0x0
DATMSK0
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK1
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK10
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK11
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK12
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK13
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK14
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK15
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK2
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK3
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK4
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK5
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK6
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK7
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK8
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
DATMSK9
Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Corresponding DOUT (Px_DOUT[n]) bit can be updated
#0
1
Corresponding DOUT (Px_DOUT[n]) bit protected
#1
PA_DBEN
PA_DBEN
PA De-bounce Enable Control Register
0x14
read-write
n
0x0
0x0
DBEN0
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN1
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN10
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN11
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN12
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN13
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN14
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN15
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN2
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN3
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN4
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN5
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN6
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN7
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN8
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
DBEN9
Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Px.n de-bounce function Disabled
#0
1
Px.n de-bounce function Enabled
#1
PA_DINOFF
PA_DINOFF
PA Digital Input Path Disable Control
0x4
read-write
n
0x0
0x0
DINOFF0
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
16
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF1
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
17
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF10
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
26
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF11
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
27
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF12
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
28
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF13
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
29
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF14
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
30
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF15
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
31
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF2
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
18
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF3
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
19
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF4
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
20
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF5
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
21
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF6
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
22
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF7
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
23
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF8
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
24
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
DINOFF9
Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
25
1
read-write
0
Px.n digital input path Enabled
#0
1
Px.n digital input path Disabled (digital input tied to low)
#1
PA_DOUT
PA_DOUT
PA Data Output Value
0x8
read-write
n
0x0
0x0
DOUT0
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT10
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT11
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT12
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT13
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT14
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT15
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT8
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT9
Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode
#1
PA_INTEN
PA_INTEN
PA Interrupt Enable Control Register
0x1C
read-write
n
0x0
0x0
FLIEN0
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN1
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN10
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN11
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN12
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN13
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN14
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN15
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN2
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN3
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN4
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN5
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN6
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN7
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN8
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
FLIEN9
Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Px.n level low or high to low interrupt Disabled
#0
1
Px.n level low or high to low interrupt Enabled
#1
RHIEN0
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
16
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN1
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
17
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN10
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
26
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN11
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
27
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN12
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
28
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN13
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
29
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN14
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
30
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN15
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
31
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN2
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
18
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN3
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
19
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN4
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
20
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN5
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
21
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN6
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
22
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN7
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
23
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN8
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
24
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
RHIEN9
Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
25
1
read-write
0
Px.n level high or low to high interrupt Disabled
#0
1
Px.n level high or low to high interrupt Enabled
#1
PA_INTSRC
PA_INTSRC
PA Interrupt Source Flag
0x20
read-write
n
0x0
0x0
INTSRC0
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC1
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC10
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC11
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC12
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC13
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC14
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC15
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC2
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC3
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC4
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC5
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC6
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC7
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC8
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
INTSRC9
Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
No action.\nNo interrupt at Px.n
#0
1
Clear the corresponding pending interrupt.\nPx.n generates an interrupt
#1
PA_INTTYPE
PA_INTTYPE
PA Interrupt Trigger Type Control
0x18
read-write
n
0x0
0x0
TYPE0
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE1
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE10
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE11
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE12
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE13
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE14
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE15
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE2
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE3
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE4
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE5
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE6
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE7
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE8
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
TYPE9
Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
PA_MODE
PA_MODE
PA I/O Mode Control
0x0
read-write
n
0x0
0x0
MODE0
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE1
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE10
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
20
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE11
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
22
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE12
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
24
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE13
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
26
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE14
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
28
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE15
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
30
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE2
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE3
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE4
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE5
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE6
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE7
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE8
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
16
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
MODE9
Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
18
2
read-write
0
Px.n is in Input mode
#00
1
Px.n is in Push-pull Output mode
#01
2
Px.n is in Open-drain Output mode
#10
3
Px.n is in Quasi-bidirectional mode
#11
PA_PIN
PA_PIN
PA Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN1
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN10
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN11
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN12
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN13
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN14
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN15
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN2
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN3
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN4
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN5
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN6
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN7
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN8
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PIN9
Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-only
0
The corresponding pin status is low
#0
1
The corresponding pin status is high
#1
PA_PUSEL
PA_PUSEL
PA Pull-up and Pull-down Selection Register
0x30
read-write
n
0x0
0x0
PUSEL0
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL1
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL10
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
20
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL11
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
22
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL12
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
24
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL13
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
26
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL14
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
28
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL15
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
30
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL2
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL3
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL4
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL5
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL6
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL7
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL8
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
16
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PUSEL9
Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
18
2
read-write
0
Px.n pull-up and pull-down disable
#00
1
Px.n pull-up enable
#01
2
Px.n pull-down enable
#10
3
Px.n pull-up and pull- down disable
#11
PA_SLEWCTL
PA_SLEWCTL
PA High Slew Rate Control Register
0x28
read-write
n
0x0
0x0
HSREN0
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
0
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN1
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
2
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN10
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
20
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN11
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
22
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN12
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
24
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN13
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
26
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN14
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
28
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN15
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
30
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN2
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
4
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN3
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
6
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN4
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
8
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN5
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
10
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN6
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
12
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN7
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
14
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN8
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
16
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
HSREN9
Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
18
2
read-write
0
Px.n output with normal slew rate mode
#00
1
Px.n output with high slew rate mode
#01
2
Reserved.
#10
3
Reserved.
#11
PA_SMTEN
PA_SMTEN
PA Input Schmitt Trigger Enable Register
0x24
read-write
n
0x0
0x0
SMTEN0
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
0
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN1
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
1
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN10
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
10
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN11
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
11
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN12
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
12
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN13
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
13
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN14
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
14
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN15
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
15
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN2
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
2
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN3
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
3
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN4
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
4
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN5
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
5
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN6
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
6
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN7
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
7
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN8
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
8
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
SMTEN9
Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
9
1
read-write
0
Px.n input schmitt trigger function Disabled
#0
1
Px.n input schmitt trigger function Enabled
#1
PB0_PDIO
PB0_PDIO
GPIO PB.n Pin Data Input/Output Register
0x840
read-write
n
0x0
0x0
PB10_PDIO
PB10_PDIO
GPIO PB.n Pin Data Input/Output Register
0x868
read-write
n
0x0
0x0
PB11_PDIO
PB11_PDIO
GPIO PB.n Pin Data Input/Output Register
0x86C
read-write
n
0x0
0x0
PB12_PDIO
PB12_PDIO
GPIO PB.n Pin Data Input/Output Register
0x870
read-write
n
0x0
0x0
PB13_PDIO
PB13_PDIO
GPIO PB.n Pin Data Input/Output Register
0x874
read-write
n
0x0
0x0
PB14_PDIO
PB14_PDIO
GPIO PB.n Pin Data Input/Output Register
0x878
read-write
n
0x0
0x0
PB15_PDIO
PB15_PDIO
GPIO PB.n Pin Data Input/Output Register
0x87C
read-write
n
0x0
0x0
PB1_PDIO
PB1_PDIO
GPIO PB.n Pin Data Input/Output Register
0x844
read-write
n
0x0
0x0
PB2_PDIO
PB2_PDIO
GPIO PB.n Pin Data Input/Output Register
0x848
read-write
n
0x0
0x0
PB3_PDIO
PB3_PDIO
GPIO PB.n Pin Data Input/Output Register
0x84C
read-write
n
0x0
0x0
PB4_PDIO
PB4_PDIO
GPIO PB.n Pin Data Input/Output Register
0x850
read-write
n
0x0
0x0
PB5_PDIO
PB5_PDIO
GPIO PB.n Pin Data Input/Output Register
0x854
read-write
n
0x0
0x0
PB6_PDIO
PB6_PDIO
GPIO PB.n Pin Data Input/Output Register
0x858
read-write
n
0x0
0x0
PB7_PDIO
PB7_PDIO
GPIO PB.n Pin Data Input/Output Register
0x85C
read-write
n
0x0
0x0
PB8_PDIO
PB8_PDIO
GPIO PB.n Pin Data Input/Output Register
0x860
read-write
n
0x0
0x0
PB9_PDIO
PB9_PDIO
GPIO PB.n Pin Data Input/Output Register
0x864
read-write
n
0x0
0x0
PB_DATMSK
PB_DATMSK
PB Data Output Write Mask
0x4C
read-write
n
0x0
0x0
PB_DBEN
PB_DBEN
PB De-bounce Enable Control Register
0x54
read-write
n
0x0
0x0
PB_DINOFF
PB_DINOFF
PB Digital Input Path Disable Control
0x44
read-write
n
0x0
0x0
PB_DOUT
PB_DOUT
PB Data Output Value
0x48
read-write
n
0x0
0x0
PB_INTEN
PB_INTEN
PB Interrupt Enable Control Register
0x5C
read-write
n
0x0
0x0
PB_INTSRC
PB_INTSRC
PB Interrupt Source Flag
0x60
read-write
n
0x0
0x0
PB_INTTYPE
PB_INTTYPE
PB Interrupt Trigger Type Control
0x58
read-write
n
0x0
0x0
PB_MODE
PB_MODE
PB I/O Mode Control
0x40
read-write
n
0x0
0x0
PB_PIN
PB_PIN
PB Pin Value
0x50
read-write
n
0x0
0x0
PB_PUSEL
PB_PUSEL
PB Pull-up and Pull-down Selection Register
0x70
read-write
n
0x0
0x0
PB_SLEWCTL
PB_SLEWCTL
PB High Slew Rate Control Register
0x68
read-write
n
0x0
0x0
PB_SMTEN
PB_SMTEN
PB Input Schmitt Trigger Enable Register
0x64
read-write
n
0x0
0x0
PC0_PDIO
PC0_PDIO
GPIO PC.n Pin Data Input/Output Register
0x880
read-write
n
0x0
0x0
PC10_PDIO
PC10_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A8
read-write
n
0x0
0x0
PC11_PDIO
PC11_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8AC
read-write
n
0x0
0x0
PC12_PDIO
PC12_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B0
read-write
n
0x0
0x0
PC14_PDIO
PC14_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8B8
read-write
n
0x0
0x0
PC15_PDIO
PC15_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8BC
read-write
n
0x0
0x0
PC1_PDIO
PC1_PDIO
GPIO PC.n Pin Data Input/Output Register
0x884
read-write
n
0x0
0x0
PC2_PDIO
PC2_PDIO
GPIO PC.n Pin Data Input/Output Register
0x888
read-write
n
0x0
0x0
PC3_PDIO
PC3_PDIO
GPIO PC.n Pin Data Input/Output Register
0x88C
read-write
n
0x0
0x0
PC4_PDIO
PC4_PDIO
GPIO PC.n Pin Data Input/Output Register
0x890
read-write
n
0x0
0x0
PC5_PDIO
PC5_PDIO
GPIO PC.n Pin Data Input/Output Register
0x894
read-write
n
0x0
0x0
PC6_PDIO
PC6_PDIO
GPIO PC.n Pin Data Input/Output Register
0x898
read-write
n
0x0
0x0
PC7_PDIO
PC7_PDIO
GPIO PC.n Pin Data Input/Output Register
0x89C
read-write
n
0x0
0x0
PC8_PDIO
PC8_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A0
read-write
n
0x0
0x0
PC9_PDIO
PC9_PDIO
GPIO PC.n Pin Data Input/Output Register
0x8A4
read-write
n
0x0
0x0
PC_DATMSK
PC_DATMSK
PC Data Output Write Mask
0x8C
read-write
n
0x0
0x0
PC_DBEN
PC_DBEN
PC De-bounce Enable Control Register
0x94
read-write
n
0x0
0x0
PC_DINOFF
PC_DINOFF
PC Digital Input Path Disable Control
0x84
read-write
n
0x0
0x0
PC_DOUT
PC_DOUT
PC Data Output Value
0x88
read-write
n
0x0
0x0
PC_INTEN
PC_INTEN
PC Interrupt Enable Control Register
0x9C
read-write
n
0x0
0x0
PC_INTSRC
PC_INTSRC
PC Interrupt Source Flag
0xA0
read-write
n
0x0
0x0
PC_INTTYPE
PC_INTTYPE
PC Interrupt Trigger Type Control
0x98
read-write
n
0x0
0x0
PC_MODE
PC_MODE
PC I/O Mode Control
0x80
read-write
n
0x0
0x0
PC_PIN
PC_PIN
PC Pin Value
0x90
read-write
n
0x0
0x0
PC_PUSEL
PC_PUSEL
PC Pull-up and Pull-down Selection Register
0xB0
read-write
n
0x0
0x0
PC_SLEWCTL
PC_SLEWCTL
PC High Slew Rate Control Register
0xA8
read-write
n
0x0
0x0
PC_SMTEN
PC_SMTEN
PC Input Schmitt Trigger Enable Register
0xA4
read-write
n
0x0
0x0
PD0_PDIO
PD0_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C0
read-write
n
0x0
0x0
PD10_PDIO
PD10_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E8
read-write
n
0x0
0x0
PD11_PDIO
PD11_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8EC
read-write
n
0x0
0x0
PD12_PDIO
PD12_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F0
read-write
n
0x0
0x0
PD13_PDIO
PD13_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8F4
read-write
n
0x0
0x0
PD15_PDIO
PD15_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8FC
read-write
n
0x0
0x0
PD1_PDIO
PD1_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C4
read-write
n
0x0
0x0
PD2_PDIO
PD2_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8C8
read-write
n
0x0
0x0
PD3_PDIO
PD3_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8CC
read-write
n
0x0
0x0
PD4_PDIO
PD4_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D0
read-write
n
0x0
0x0
PD5_PDIO
PD5_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D4
read-write
n
0x0
0x0
PD6_PDIO
PD6_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8D8
read-write
n
0x0
0x0
PD7_PDIO
PD7_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8DC
read-write
n
0x0
0x0
PD8_PDIO
PD8_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E0
read-write
n
0x0
0x0
PD9_PDIO
PD9_PDIO
GPIO PD.n Pin Data Input/Output Register
0x8E4
read-write
n
0x0
0x0
PD_DATMSK
PD_DATMSK
PD Data Output Write Mask
0xCC
read-write
n
0x0
0x0
PD_DBEN
PD_DBEN
PD De-bounce Enable Control Register
0xD4
read-write
n
0x0
0x0
PD_DINOFF
PD_DINOFF
PD Digital Input Path Disable Control
0xC4
read-write
n
0x0
0x0
PD_DOUT
PD_DOUT
PD Data Output Value
0xC8
read-write
n
0x0
0x0
PD_INTEN
PD_INTEN
PD Interrupt Enable Control Register
0xDC
read-write
n
0x0
0x0
PD_INTSRC
PD_INTSRC
PD Interrupt Source Flag
0xE0
read-write
n
0x0
0x0
PD_INTTYPE
PD_INTTYPE
PD Interrupt Trigger Type Control
0xD8
read-write
n
0x0
0x0
PD_MODE
PD_MODE
PD I/O Mode Control
0xC0
read-write
n
0x0
0x0
PD_PIN
PD_PIN
PD Pin Value
0xD0
read-write
n
0x0
0x0
PD_PUSEL
PD_PUSEL
PD Pull-up and Pull-down Selection Register
0xF0
read-write
n
0x0
0x0
PD_SLEWCTL
PD_SLEWCTL
PD High Slew Rate Control Register
0xE8
read-write
n
0x0
0x0
PD_SMTEN
PD_SMTEN
PD Input Schmitt Trigger Enable Register
0xE4
read-write
n
0x0
0x0
PE0_PDIO
PE0_PDIO
GPIO PE.n Pin Data Input/Output Register
0x900
read-write
n
0x0
0x0
PE10_PDIO
PE10_PDIO
GPIO PE.n Pin Data Input/Output Register
0x928
read-write
n
0x0
0x0
PE11_PDIO
PE11_PDIO
GPIO PE.n Pin Data Input/Output Register
0x92C
read-write
n
0x0
0x0
PE12_PDIO
PE12_PDIO
GPIO PE.n Pin Data Input/Output Register
0x930
read-write
n
0x0
0x0
PE13_PDIO
PE13_PDIO
GPIO PE.n Pin Data Input/Output Register
0x934
read-write
n
0x0
0x0
PE14_PDIO
PE14_PDIO
GPIO PE.n Pin Data Input/Output Register
0x938
read-write
n
0x0
0x0
PE15_PDIO
PE15_PDIO
GPIO PE.n Pin Data Input/Output Register
0x93C
read-write
n
0x0
0x0
PE1_PDIO
PE1_PDIO
GPIO PE.n Pin Data Input/Output Register
0x904
read-write
n
0x0
0x0
PE2_PDIO
PE2_PDIO
GPIO PE.n Pin Data Input/Output Register
0x908
read-write
n
0x0
0x0
PE3_PDIO
PE3_PDIO
GPIO PE.n Pin Data Input/Output Register
0x90C
read-write
n
0x0
0x0
PE4_PDIO
PE4_PDIO
GPIO PE.n Pin Data Input/Output Register
0x910
read-write
n
0x0
0x0
PE5_PDIO
PE5_PDIO
GPIO PE.n Pin Data Input/Output Register
0x914
read-write
n
0x0
0x0
PE6_PDIO
PE6_PDIO
GPIO PE.n Pin Data Input/Output Register
0x918
read-write
n
0x0
0x0
PE7_PDIO
PE7_PDIO
GPIO PE.n Pin Data Input/Output Register
0x91C
read-write
n
0x0
0x0
PE8_PDIO
PE8_PDIO
GPIO PE.n Pin Data Input/Output Register
0x920
read-write
n
0x0
0x0
PE9_PDIO
PE9_PDIO
GPIO PE.n Pin Data Input/Output Register
0x924
read-write
n
0x0
0x0
PE_DATMSK
PE_DATMSK
PE Data Output Write Mask
0x10C
read-write
n
0x0
0x0
PE_DBEN
PE_DBEN
PE De-bounce Enable Control Register
0x114
read-write
n
0x0
0x0
PE_DINOFF
PE_DINOFF
PE Digital Input Path Disable Control
0x104
read-write
n
0x0
0x0
PE_DOUT
PE_DOUT
PE Data Output Value
0x108
read-write
n
0x0
0x0
PE_INTEN
PE_INTEN
PE Interrupt Enable Control Register
0x11C
read-write
n
0x0
0x0
PE_INTSRC
PE_INTSRC
PE Interrupt Source Flag
0x120
read-write
n
0x0
0x0
PE_INTTYPE
PE_INTTYPE
PE Interrupt Trigger Type Control
0x118
read-write
n
0x0
0x0
PE_MODE
PE_MODE
PE I/O Mode Control
0x100
read-write
n
0x0
0x0
PE_PIN
PE_PIN
PE Pin Value
0x110
read-write
n
0x0
0x0
PE_PUSEL
PE_PUSEL
PE Pull-up and Pull-down Selection Register
0x130
read-write
n
0x0
0x0
PE_SLEWCTL
PE_SLEWCTL
PE High Slew Rate Control Register
0x128
read-write
n
0x0
0x0
PE_SMTEN
PE_SMTEN
PE Input Schmitt Trigger Enable Register
0x124
read-write
n
0x0
0x0
PF0_PDIO
PF0_PDIO
GPIO PF.n Pin Data Input/Output Register
0x940
read-write
n
0x0
0x0
PF1_PDIO
PF1_PDIO
GPIO PF.n Pin Data Input/Output Register
0x944
read-write
n
0x0
0x0
PF2_PDIO
PF2_PDIO
GPIO PF.n Pin Data Input/Output Register
0x948
read-write
n
0x0
0x0
PF3_PDIO
PF3_PDIO
GPIO PF.n Pin Data Input/Output Register
0x94C
read-write
n
0x0
0x0
PF4_PDIO
PF4_PDIO
GPIO PF.n Pin Data Input/Output Register
0x950
read-write
n
0x0
0x0
PF5_PDIO
PF5_PDIO
GPIO PF.n Pin Data Input/Output Register
0x954
read-write
n
0x0
0x0
PF6_PDIO
PF6_PDIO
GPIO PF.n Pin Data Input/Output Register
0x958
read-write
n
0x0
0x0
PF7_PDIO
PF7_PDIO
GPIO PF.n Pin Data Input/Output Register
0x95C
read-write
n
0x0
0x0
PF_DATMSK
PF_DATMSK
PF Data Output Write Mask
0x14C
read-write
n
0x0
0x0
PF_DBEN
PF_DBEN
PF De-bounce Enable Control Register
0x154
read-write
n
0x0
0x0
PF_DINOFF
PF_DINOFF
PF Digital Input Path Disable Control
0x144
read-write
n
0x0
0x0
PF_DOUT
PF_DOUT
PF Data Output Value
0x148
read-write
n
0x0
0x0
PF_INTEN
PF_INTEN
PF Interrupt Enable Control Register
0x15C
read-write
n
0x0
0x0
PF_INTSRC
PF_INTSRC
PF Interrupt Source Flag
0x160
read-write
n
0x0
0x0
PF_INTTYPE
PF_INTTYPE
PF Interrupt Trigger Type Control
0x158
read-write
n
0x0
0x0
PF_MODE
PF_MODE
PF I/O Mode Control
0x140
read-write
n
0x0
0x0
PF_PIN
PF_PIN
PF Pin Value
0x150
read-write
n
0x0
0x0
PF_PUSEL
PF_PUSEL
PF Pull-up and Pull-down Selection Register
0x170
read-write
n
0x0
0x0
PF_SLEWCTL
PF_SLEWCTL
PF High Slew Rate Control Register
0x168
read-write
n
0x0
0x0
PF_SMTEN
PF_SMTEN
PF Input Schmitt Trigger Enable Register
0x164
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
#0
1
Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
PECCLR
PEC Clear at Repeat \nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat START' function Disabled
#0
1
PEC calculation is cleared by 'Repeat START' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit\nNote: When I2C enters Power-down mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
TIDLE
Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOUT is used to calculate the clock low period in bus active
#0
1
BUSTOUT is used to calculate the IDLE period in bus Idle
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
read-write
n
0x0
0x0
ALERT
SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.\nNo SMBALERT event
#0
1
SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status \nIn bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCLK and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception \nNote: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in BIDLE=0) or high more than BUSTO (in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled
#0
1
SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK.\nFor Slave, it calculates the period from START to STOP.
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high.)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x30
registers
n
I2C_ADDR0
I2C_ADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
ADDR
I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used.
1
10
read-write
GC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
I2C_ADDR1
I2C_ADDR1
I2C Slave Address Register1
0x18
read-write
n
0x0
0x0
I2C_ADDR2
I2C_ADDR2
I2C Slave Address Register2
0x1C
read-write
n
0x0
0x0
I2C_ADDR3
I2C_ADDR3
I2C Slave Address Register3
0x20
read-write
n
0x0
0x0
I2C_ADDRMSK0
I2C_ADDRMSK0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
ADDRMSK
I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
1
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2C_ADDRMSK1
I2C_ADDRMSK1
I2C Slave Address Mask Register1
0x28
read-write
n
0x0
0x0
I2C_ADDRMSK2
I2C_ADDRMSK2
I2C Slave Address Mask Register2
0x2C
read-write
n
0x0
0x0
I2C_ADDRMSK3
I2C_ADDRMSK3
I2C Slave Address Mask Register3
0x30
read-write
n
0x0
0x0
I2C_BUSCTL
I2C_BUSCTL
I2C Bus Management Control Register
0x50
read-write
n
0x0
0x0
ACKM9SI
Acknowledge Manual Enable Extra SI Interrupt
11
1
read-write
0
There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#0
1
There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1
#1
ACKMEN
Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0
1
read-write
0
Slave byte control Disabled
#0
1
Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse
#1
ALERTEN
Bus Management Alert Enable Bit
4
1
read-write
0
Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported
#0
1
Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported
#1
BCDIEN
Packet Error Checking Byte Count Done Interrupt Enable Bit
12
1
read-write
0
Byte count done interrupt Disabled
#0
1
Byte count done interrupt Enabled
#1
BMDEN
Bus Management Device Default Address Enable Bit
2
1
read-write
0
Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
#0
1
Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed
#1
BMHEN
Bus Management Host Enable Bit
3
1
read-write
0
Host function Disabled
#0
1
Host function Enabled
#1
BUSEN
BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
7
1
read-write
0
The system management function Disabled
#0
1
The system management function Enabled
#1
PECCLR
PEC Clear at Repeat \nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation.
10
1
read-write
0
PEC calculation is cleared by 'Repeat START' function Disabled
#0
1
PEC calculation is cleared by 'Repeat START' function Enabled
#1
PECDIEN
Packet Error Checking Byte Transfer Done Interrupt Enable Bit
13
1
read-write
0
PEC transfer done interrupt Disabled
#0
1
PEC transfer done interrupt Enabled
#1
PECEN
Packet Error Checking Calculation Enable Bit\nNote: When I2C enters Power-down mode, the bit should be enabled after wake-up if needed PEC calculation.
1
1
read-write
0
Packet Error Checking Calculation Disabled
#0
1
Packet Error Checking Calculation Enabled
#1
PECTXEN
Packet Error Checking Byte Transmission/Reception
8
1
read-write
0
No PEC transfer
#0
1
PEC transmission is requested
#1
SCTLOEN
Suspend or Control Pin Output Enable Bit
6
1
read-write
0
The SUSCON pin in input
#0
1
The output enable is active on the SUSCON pin
#1
SCTLOSTS
Suspend/Control Data Output Status
5
1
read-write
0
The output of SUSCON pin is low
#0
1
The output of SUSCON pin is high
#1
TIDLE
Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
9
1
read-write
0
BUSTOUT is used to calculate the clock low period in bus active
#0
1
BUSTOUT is used to calculate the IDLE period in bus Idle
#1
I2C_BUSSTS
I2C_BUSSTS
I2C Bus Management Status Register
0x58
read-write
n
0x0
0x0
ALERT
SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
3
1
read-write
0
SMBALERT pin state is low.\nNo SMBALERT event
#0
1
SMBALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1
#1
BCDONE
Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
1
1
read-write
0
Byte count transmission/ receive is not finished when the PECEN is set
#0
1
Byte count transmission/ receive is finished when the PECEN is set
#1
BUSTO
Bus Time-out Status \nIn bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit.
5
1
read-write
0
There is no any time-out or external clock time-out
#0
1
A time-out or external clock time-out occurred
#1
BUSY
Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
0
1
read-only
0
Bus is IDLE (both SCLK and SDA High)
#0
1
Bus is busy
#1
CLKTO
Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit.
6
1
read-write
0
Cumulative clock low is no any time-out
#0
1
Cumulative clock low time-out occurred
#1
PECDONE
PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
7
1
read-write
0
PEC transmission/ receive is not finished when the PECEN is set
#0
1
PEC transmission/ receive is finished when the PECEN is set
#1
PECERR
PEC Error in Reception \nNote: Software can write 1 to clear this bit.
2
1
read-write
0
PEC value equal the received PEC data packet
#0
1
PEC value doesn't match the receive PEC data packet
#1
SCTLDIN
Bus Suspend or Control Signal Input Status (Read Only)
4
1
read-only
0
The input status of SUSCON pin is 0
#0
1
The input status of SUSCON pin is 1
#1
I2C_BUSTCTL
I2C_BUSTCTL
I2C Bus Management Timer Control Register
0x54
read-write
n
0x0
0x0
BUSTOEN
Bus Time Out Enable Bit
0
1
read-write
0
Bus clock low time-out detection Disabled
#0
1
Bus clock low time-out detection Enabled (bus clock is low for more than BUSTO (I2C_BUSTOUT[7:0]) (in BIDLE=0) or high more than BUSTO (in BIDLE =1)
#1
BUSTOIEN
Time-out Interrupt Enable Bit
2
1
read-write
0
SCLK low time-out interrupt Disabled.\nBus IDLE time-out interrupt Disabled
#0
1
SCLK low time-out interrupt Enabled.\nBus IDLE time-out interrupt Enabled
#1
CLKTOEN
Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK.\nFor Slave, it calculates the period from START to STOP.
1
1
read-write
0
Cumulative clock low time-out detection Disabled
#0
1
Cumulative clock low time-out detection Enabled
#1
CLKTOIEN
Extended Clock Time Out Interrupt Enable Bit
3
1
read-write
0
Clock time out interrupt Disabled
#0
1
Clock time out interrupt Enabled
#1
TORSTEN
Time Out Reset Enable Bit
4
1
read-write
0
I2C state machine reset Disabled
#0
1
I2C state machine reset Enabled. (The clock and data bus will be released to high.)
#1
I2C_BUSTOUT
I2C_BUSTOUT
I2C Bus Management Timer Register
0x64
read-write
n
0x0
0x0
BUSTO
Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
0
8
read-write
I2C_CLKDIV
I2C_CLKDIV
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
DIVIDER
I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
0
10
read-write
I2C_CLKTOUT
I2C_CLKTOUT
I2C Bus Management Clock Low Timer Register
0x68
read-write
n
0x0
0x0
CLKTO
Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
0
8
read-write
I2C_CTL0
I2C_CTL0
I2C Control Register 0
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
2
1
read-write
I2CEN
I2C Controller Enable Bit
6
1
read-write
0
I2C controller Disabled
#0
1
I2C controller Enabled
#1
INTEN
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
3
1
read-write
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
4
1
read-write
I2C_CTL1
I2C_CTL1
I2C Control Register 1
0x44
read-write
n
0x0
0x0
ADDR10EN
Address 10-bit Function Enable Bit
9
1
read-write
0
Address match 10-bit function Disabled
#0
1
Address match 10-bit function Enabled
#1
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the I2C request to PDMA
#1
PDMASTR
PDMA Stretch Bit
8
1
read-write
0
I2C send STOP automatically after PDMA transfer done. (only master TX)
#0
1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
#1
RXPDMAEN
PDMA Receive Channel Available
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
I2C_DAT
I2C_DAT
I2C Data Register
0x8
read-write
n
0x0
0x0
DAT
I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
0
8
read-write
I2C_PKTCRC
I2C_PKTCRC
I2C Packet Error Checking Byte Value Register
0x60
read-only
n
0x0
0x0
PECCRC
Packet Error Checking Byte Value
0
8
read-only
I2C_PKTSIZE
I2C_PKTSIZE
I2C Packet Error Checking Byte Number Register
0x5C
read-write
n
0x0
0x0
PLDSIZE
Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame.
0
9
read-write
I2C_STATUS0
I2C_STATUS0
I2C Status Register 0
0xC
read-only
n
0x0
0x0
STATUS
I2C Status
0
8
read-only
I2C_STATUS1
I2C_STATUS1
I2C Status Register 1
0x48
read-write
n
0x0
0x0
ADMAT0
I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
ADMAT2
I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
2
1
read-write
ADMAT3
I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
3
1
read-write
ONBUSY
On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
8
1
read-only
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
I2C_TMCTL
I2C_TMCTL
I2C Timing Configure Control Register
0x4C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
16
9
read-write
STCTL
Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
0
9
read-write
I2C_TOCTL
I2C_TOCTL
I2C Time-out Control Register
0x14
read-write
n
0x0
0x0
TOCDIV4
Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times.
1
1
read-write
0
Time-out period is extend 4 times Disabled
#0
1
Time-out period is extend 4 times Enabled
#1
TOCEN
Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
TOIF
Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
0
1
read-write
I2C_WKCTL
I2C_WKCTL
I2C Wake-up Control Register
0x3C
read-write
n
0x0
0x0
NHDBUSEN
I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
7
1
read-write
0
I2C hold bus after wake-up
#0
1
I2C don't hold bus after wake-up
#1
WKEN
I2C Wake-up Enable Bit
0
1
read-write
0
I2C wake-up function Disabled
#0
1
I2C wake-up function Enabled
#1
I2C_WKSTS
I2C_WKSTS
I2C Wake-up Status Register
0x40
read-write
n
0x0
0x0
WKAKDONE
Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
1
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WKIF
I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WRSTSWK
Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
2
1
read-only
0
Write command be record on the address match wakeup frame
#0
1
Read command be record on the address match wakeup frame
#1
NMI
NMI Register Map
NMI
0x0
0x0
0x8
registers
n
NMIEN
NMIEN
NMI Source Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BODOUT
BOD NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
BOD NMI source Disabled
#0
1
BOD NMI source Enabled
#1
CLKFAIL
Clock Fail Detected NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
Clock fail detected interrupt NMI source Disabled
#0
1
Clock fail detected interrupt NMI source Enabled
#1
EINT0
External Interrupt From PA.0, PD.2 or PE.4 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
8
1
read-write
0
External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled
#0
1
External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled
#1
EINT1
External Interrupt From PB.0, PD.3 or PE.5 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
9
1
read-write
0
External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled
#0
1
External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled
#1
EINT2
External Interrupt From PC.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
10
1
read-write
0
External interrupt from PC.0 pin NMI source Disabled
#0
1
External interrupt from PC.0 pin NMI source Enabled
#1
EINT3
External Interrupt From PD.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
11
1
read-write
0
External interrupt from PD.0 pin NMI source Disabled
#0
1
External interrupt from PD.0 pin NMI source Enabled
#1
EINT4
External Interrupt From PE.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
External interrupt from PE.0 pin NMI source Disabled
#0
1
External interrupt from PE.0 pin NMI source Enabled
#1
EINT5
External Interrupt From PF.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
13
1
read-write
0
External interrupt from PF.0 pin NMI source Disabled
#0
1
External interrupt from PF.0 pin NMI source Enabled
#1
IRC_INT
IRC TRIM NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
IRC TRIM NMI source Disabled
#0
1
IRC TRIM NMI source Enabled
#1
PWRWU_INT
Power-down Mode Wake-up NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
Power-down mode wake-up NMI source Disabled
#0
1
Power-down mode wake-up NMI source Enabled
#1
RTC_INT
RTC NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
RTC NMI source Disabled
#0
1
RTC NMI source Enabled
#1
TAMPER_INT
TAMPER_INT NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Backup register tamper detected interrupt.NMI source Disabled
#0
1
Backup register tamper detected interrupt.NMI source Enabled
#1
UART0_INT
UART0 NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
14
1
read-write
0
UART0 NMI source Disabled
#0
1
UART0 NMI source Enabled
#1
UART1_INT
UART1 NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
15
1
read-write
0
UART1 NMI source Disabled
#0
1
UART1 NMI source Enabled
#1
NMISTS
NMISTS
NMI Source Interrupt Status Register
0x4
read-only
n
0x0
0x0
BODOUT
BOD Interrupt Flag (Read Only)
0
1
read-only
0
BOD interrupt is deasserted
#0
1
BOD interrupt is asserted
#1
CLKFAIL
Clock Fail Detected Interrupt Flag (Read Only)
4
1
read-only
0
Clock fail detected interrupt is deasserted
#0
1
Clock fail detected interrupt is asserted
#1
EINT0
External Interrupt From PA.0, PD.2 or PE.4 Pin Interrupt Flag (Read Only)
8
1
read-only
0
External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted
#0
1
External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted
#1
EINT1
External Interrupt From PB.0, PD.3 or PE.5 Pin Interrupt Flag (Read Only)
9
1
read-only
0
External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted
#0
1
External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted
#1
EINT2
External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
10
1
read-only
0
External Interrupt from PC.0 interrupt is deasserted
#0
1
External Interrupt from PC.0 interrupt is asserted
#1
EINT3
External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
11
1
read-only
0
External Interrupt from PD.0 interrupt is deasserted
#0
1
External Interrupt from PD.0 interrupt is asserted
#1
EINT4
External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
12
1
read-only
0
External Interrupt from PE.0 interrupt is deasserted
#0
1
External Interrupt from PE.0 interrupt is asserted
#1
EINT5
External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
13
1
read-only
0
External Interrupt from PF.0 interrupt is deasserted
#0
1
External Interrupt from PF.0 interrupt is asserted
#1
IRC_INT
IRC TRIM Interrupt Flag (Read Only)
1
1
read-only
0
HIRC TRIM interrupt is deasserted
#0
1
HIRC TRIM interrupt is asserted
#1
PWRWU_INT
Power-down Mode Wake-up Interrupt Flag (Read Only)
2
1
read-only
0
Power-down mode wake-up interrupt is deasserted
#0
1
Power-down mode wake-up interrupt is asserted
#1
RTC_INT
RTC Interrupt Flag (Read Only)
6
1
read-only
0
RTC interrupt is deasserted
#0
1
RTC interrupt is asserted
#1
TAMPER_INT
TAMPER_INT Interrupt Flag (Read Only)
7
1
read-only
0
Backup register tamper detected interrupt is deasserted
#0
1
Backup register tamper detected interrupt is asserted
#1
UART0_INT
UART0 Interrupt Flag (Read Only)
14
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
UART1_INT
UART1 Interrupt Flag (Read Only)
15
1
read-only
0
UART1 interrupt is deasserted
#0
1
UART1 interrupt is asserted
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x8
registers
n
0x100
0x8
registers
n
0x180
0x8
registers
n
0x200
0x8
registers
n
0x80
0x8
registers
n
IABR0
NVIC_IABR0
IRQ0 ~ IRQ31 Active Bit Register
0x200
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
IABR1
NVIC_IABR1
IRQ32 ~ IRQ63 Active Bit Register
0x204
read-write
n
0x0
0x0
ACTIVE
Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
0
32
read-write
0
interrupt not active
0
1
interrupt active
1
ICER0
NVIC_ICER0
IRQ0 ~ IRQ31 Clear-enable Control Register
0x80
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
ICER1
NVIC_ICER1
IRQ32 ~ IRQ63 Clear-enable Control Register
0x84
read-write
n
0x0
0x0
CALENA
Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
ICPR0
NVIC_ICPR0
IRQ0 ~ IRQ31 Clear-pending Control Register
0x180
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Removes pending state an interrupt.\nInterrupt is pending
1
ICPR1
NVIC_ICPR1
IRQ32 ~ IRQ63 Clear-pending Control Register
0x184
read-write
n
0x0
0x0
CALPEND
Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Removes pending state an interrupt.\nInterrupt is pending
1
ISER0
NVIC_ISER0
IRQ0 ~ IRQ31 Set-enable Control Register
0x0
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
ISER1
NVIC_ISER1
IRQ32 ~ IRQ63 Set-enable Control Register
0x4
read-write
n
0x0
0x0
SETENA
Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
ISPR0
NVIC_ISPR0
IRQ0 ~ IRQ31 Set-pending Control Register
0x100
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Changes interrupt state to pending.\nInterrupt is pending
1
ISPR1
NVIC_ISPR1
IRQ32 ~ IRQ63 Set-pending Control Register
0x104
read-write
n
0x0
0x0
SETPEND
Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
0
32
read-write
0
No effect.\nInterrupt is not pending
0
1
Changes interrupt state to pending.\nInterrupt is pending
1
OPA
OPA Register Map
OPA
0x0
0x0
0x10
registers
n
CALCTL
OPA_CALCTL
OP Amplifier Calibration Control Register
0x8
read-write
n
0x0
0x0
CALRVS0
OPA0 Calibration Reference Voltage Selection
16
1
read-write
0
VREF is
#0
1
VREF from high vcm to low vcm
#1
CALTRG0
OP Amplifier 0 Calibration Trigger Bit\nNote: Before this bit is enabled, OPEN0 should be set in advance.
0
1
read-write
0
OP amplifier 0 calibration is stopped; hardware auto clear
#0
1
OP amplifier 0 calibration is started
#1
CALST
OPA_CALST
OP Amplifier Calibration Status Register
0xC
read-only
n
0x0
0x0
CALNS0
OP Amplifier 0 Calibration Result Status for NMOS
1
1
read-only
0
Pass
#0
1
Fail
#1
CALPS0
OP Amplifier 0 Calibration Result Status for PMOS
2
1
read-only
0
Pass
#0
1
Fail
#1
DONE0
OP Amplifier 0 Calibration Done Status
0
1
read-only
0
Calibrating
#0
1
Calibration Done
#1
CTL
OPA_CTL
OP Amplifier Control Register
0x0
read-write
n
0x0
0x0
OPDOEN0
OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
4
1
read-write
0
Disable OP amplifier0 schmitt trigger non-invert buffer
#0
1
Enable OP amplifier0 schmitt trigger non-invert buffer
#1
OPDOIEN0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
8
1
read-write
0
OP Amplifier 0 digital output interrupt function Disabled
#0
1
OP Amplifier 0 digital output interrupt function Enabled
#1
OPEN0
OP Amplifier 0 Enable Bit\nNote: OP Amplifier 0 output needs wait stable 20 s after OPEN0 is set.
0
1
read-write
0
OP amplifier0 Disabled
#0
1
OP amplifier0 Enabled
#1
STATUS
OPA_STATUS
OP Amplifier Status Register
0x4
read-write
n
0x0
0x0
OPDO0
OP Amplifier 0 Digital Output
0
1
read-write
OPDOIF0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
4
1
read-write
PDMA
PDMA Register Map
PDMA
0x0
0x0
0x2C
registers
n
0x100
0x20
registers
n
0x400
0x44
registers
n
0x460
0x8
registers
n
0x480
0x8
registers
n
0x500
0x30
registers
n
ABTSTS
PDMA_ABTSTS
PDMA Channel Read/Write Target Abort Flag Register
0x420
read-write
n
0x0
0x0
ABTIF0
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
0
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF1
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
1
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF2
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
2
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF3
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
3
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF4
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
4
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF5
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
5
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF6
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
6
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ABTIF7
PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
7
1
read-write
0
No AHB bus ERROR response received when channel n transfer
#0
1
AHB bus ERROR response received when channel n transfer
#1
ALIGN
PDMA_ALIGN
PDMA Transfer Alignment Status Register
0x428
read-write
n
0x0
0x0
ALIGN0
Transfer Alignment Flag
0
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN1
Transfer Alignment Flag
1
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN2
Transfer Alignment Flag
2
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN3
Transfer Alignment Flag
3
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN4
Transfer Alignment Flag
4
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN5
Transfer Alignment Flag
5
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN6
Transfer Alignment Flag
6
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ALIGN7
Transfer Alignment Flag
7
1
read-write
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
ASOCR0
PDMA_ASOCR0
Address Stride Offset Register of PDMA Channel 0
0x504
read-write
n
0x0
0x0
DASOL
VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row.
16
16
read-write
SASOL
VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row.
0
16
read-write
ASOCR1
PDMA_ASOCR1
Address Stride Offset Register of PDMA Channel 1
0x50C
read-write
n
0x0
0x0
ASOCR2
PDMA_ASOCR2
Address Stride Offset Register of PDMA Channel 2
0x514
read-write
n
0x0
0x0
ASOCR3
PDMA_ASOCR3
Address Stride Offset Register of PDMA Channel 3
0x51C
read-write
n
0x0
0x0
ASOCR4
PDMA_ASOCR4
Address Stride Offset Register of PDMA Channel 4
0x524
read-write
n
0x0
0x0
ASOCR5
PDMA_ASOCR5
Address Stride Offset Register of PDMA Channel 5
0x52C
read-write
n
0x0
0x0
CHCTL
PDMA_CHCTL
PDMA Channel Control Register
0x400
read-write
n
0x0
0x0
CHEN0
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
0
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN1
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
1
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN2
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
2
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN3
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
3
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN4
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
4
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN5
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
5
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN6
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
6
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHEN7
PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
7
1
read-write
0
PDMA channel [n] Disabled
#0
1
PDMA channel [n] Enabled
#1
CHRST
PDMA_CHRST
PDMA Channel Reset Register
0x460
read-write
n
0x0
0x0
CHnRST
Channel n Reset
0
16
read-write
0
corresponding channel n is not reset
0
1
corresponding channel n is reset
1
CURSCAT0
PDMA_CURSCAT0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x100
read-only
n
0x0
0x0
CURADDR
PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address.
0
32
read-only
CURSCAT1
PDMA_CURSCAT1
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x104
read-write
n
0x0
0x0
CURSCAT2
PDMA_CURSCAT2
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x108
read-write
n
0x0
0x0
CURSCAT3
PDMA_CURSCAT3
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x10C
read-write
n
0x0
0x0
CURSCAT4
PDMA_CURSCAT4
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x110
read-write
n
0x0
0x0
CURSCAT5
PDMA_CURSCAT5
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x114
read-write
n
0x0
0x0
CURSCAT6
PDMA_CURSCAT6
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x118
read-write
n
0x0
0x0
CURSCAT7
PDMA_CURSCAT7
Current Scatter-gather Descriptor Table Address of PDMA Channel n
0x11C
read-write
n
0x0
0x0
DSCT0_CTL
PDMA_DSCT0_CTL
Descriptor Table Control Register of PDMA Channel n
0x0
read-write
n
0x0
0x0
BURSIZE
Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type.
4
3
read-write
0
128 Transfers
#000
1
64 Transfers
#001
2
32 Transfers
#010
3
16 Transfers
#011
4
8 Transfers
#100
5
4 Transfers
#101
6
2 Transfers
#110
7
1 Transfers
#111
DAINC
Destination Address Increment\nThis field is used to set the destination address increment size.
10
2
read-write
3
No increment (fixed address)
#11
OPMODE
PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete.
0
2
read-write
0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#00
1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted
#01
2
Scatter-gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute
#10
3
Reserved.
#11
SAINC
Source Address Increment\nThis field is used to set the source address increment size.
8
2
read-write
3
No increment (fixed address)
#11
STRIDEEN
Stride Mode Enable Bit
15
1
read-write
0
Stride transfer mode Disabled
#0
1
Stride transfer mode Enabled
#1
TBINTDIS
Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function only for Scatter-gather mode.
7
1
read-write
0
Table interrupt Enabled
#0
1
Table interrupt Disabled
#1
TXCNT
Transfer Count\nThe TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA finish each transfer data, this field will be decreased immediately.
16
16
read-write
TXTYPE
Transfer Type
2
1
read-write
0
Burst transfer type
#0
1
Single transfer type
#1
TXWIDTH
Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
12
2
read-write
0
One byte (8 bit) is transferred for every operation
#00
1
One half-word (16 bit) is transferred for every operation
#01
2
One word (32-bit) is transferred for every operation
#10
3
Reserved.
#11
DSCT0_DA
PDMA_DSCT0_DA
Destination Address Register of PDMA Channel n
0x8
read-write
n
0x0
0x0
DA
PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller.
0
32
read-write
DSCT0_NEXT
PDMA_DSCT0_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0xC
read-write
n
0x0
0x0
EXENEXT
PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field.
16
16
read-write
NEXT
PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in Scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.\nNote1: The descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
0
16
read-write
DSCT0_SA
PDMA_DSCT0_SA
Source Address Register of PDMA Channel n
0x4
read-write
n
0x0
0x0
SA
PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller.
0
32
read-write
DSCT1_CTL
PDMA_DSCT1_CTL
Descriptor Table Control Register of PDMA Channel n
0x10
read-write
n
0x0
0x0
DSCT1_DA
PDMA_DSCT1_DA
Destination Address Register of PDMA Channel n
0x18
read-write
n
0x0
0x0
DSCT1_NEXT
PDMA_DSCT1_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x1C
read-write
n
0x0
0x0
DSCT1_SA
PDMA_DSCT1_SA
Source Address Register of PDMA Channel n
0x14
read-write
n
0x0
0x0
DSCT2_CTL
PDMA_DSCT2_CTL
Descriptor Table Control Register of PDMA Channel n
0x20
read-write
n
0x0
0x0
DSCT2_DA
PDMA_DSCT2_DA
Destination Address Register of PDMA Channel n
0x28
read-write
n
0x0
0x0
DSCT2_NEXT
PDMA_DSCT2_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x2C
read-write
n
0x0
0x0
DSCT2_SA
PDMA_DSCT2_SA
Source Address Register of PDMA Channel n
0x24
read-write
n
0x0
0x0
DSCT3_CTL
PDMA_DSCT3_CTL
Descriptor Table Control Register of PDMA Channel n
0x30
read-write
n
0x0
0x0
DSCT3_DA
PDMA_DSCT3_DA
Destination Address Register of PDMA Channel n
0x38
read-write
n
0x0
0x0
DSCT3_NEXT
PDMA_DSCT3_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x3C
read-write
n
0x0
0x0
DSCT3_SA
PDMA_DSCT3_SA
Source Address Register of PDMA Channel n
0x34
read-write
n
0x0
0x0
DSCT4_CTL
PDMA_DSCT4_CTL
Descriptor Table Control Register of PDMA Channel n
0x40
read-write
n
0x0
0x0
DSCT4_DA
PDMA_DSCT4_DA
Destination Address Register of PDMA Channel n
0x48
read-write
n
0x0
0x0
DSCT4_NEXT
PDMA_DSCT4_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x4C
read-write
n
0x0
0x0
DSCT4_SA
PDMA_DSCT4_SA
Source Address Register of PDMA Channel n
0x44
read-write
n
0x0
0x0
DSCT5_CTL
PDMA_DSCT5_CTL
Descriptor Table Control Register of PDMA Channel n
0x50
read-write
n
0x0
0x0
DSCT5_DA
PDMA_DSCT5_DA
Destination Address Register of PDMA Channel n
0x58
read-write
n
0x0
0x0
DSCT5_NEXT
PDMA_DSCT5_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x5C
read-write
n
0x0
0x0
DSCT5_SA
PDMA_DSCT5_SA
Source Address Register of PDMA Channel n
0x54
read-write
n
0x0
0x0
DSCT6_CTL
PDMA_DSCT6_CTL
Descriptor Table Control Register of PDMA Channel n
0x60
read-write
n
0x0
0x0
DSCT6_DA
PDMA_DSCT6_DA
Destination Address Register of PDMA Channel n
0x68
read-write
n
0x0
0x0
DSCT6_NEXT
PDMA_DSCT6_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x6C
read-write
n
0x0
0x0
DSCT6_SA
PDMA_DSCT6_SA
Source Address Register of PDMA Channel n
0x64
read-write
n
0x0
0x0
DSCT7_CTL
PDMA_DSCT7_CTL
Descriptor Table Control Register of PDMA Channel n
0x70
read-write
n
0x0
0x0
DSCT7_DA
PDMA_DSCT7_DA
Destination Address Register of PDMA Channel n
0x78
read-write
n
0x0
0x0
DSCT7_NEXT
PDMA_DSCT7_NEXT
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
0x7C
read-write
n
0x0
0x0
DSCT7_SA
PDMA_DSCT7_SA
Source Address Register of PDMA Channel n
0x74
read-write
n
0x0
0x0
INTEN
PDMA_INTEN
PDMA Interrupt Enable Register
0x418
read-write
n
0x0
0x0
INTEN0
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
0
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN1
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
1
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN2
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
2
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN3
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
3
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN4
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
4
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN5
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
5
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN6
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
6
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTEN7
PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
7
1
read-write
0
PDMA channel n interrupt Disabled
#0
1
PDMA channel n interrupt Enabled
#1
INTSTS
PDMA_INTSTS
PDMA Interrupt Status Register
0x41C
read-write
n
0x0
0x0
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
0
1
read-only
0
No AHB bus ERROR response received
#0
1
AHB bus ERROR response received
#1
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
2
1
read-only
0
PDMA channel source address and destination address both follow transfer width setting
#0
1
PDMA channel source address or destination address is not follow transfer width setting
#1
REQTOF0
Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear this bit.
8
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
REQTOF1
Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear this bit.
9
1
read-write
0
No request time-out
#0
1
Peripheral request time-out
#1
TDIF
Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
1
1
read-only
0
Not finished yet
#0
1
PDMA channel has finished transmission
#1
PAUSE
PDMA_PAUSE
PDMA Transfer Pause Control Register
0x404
write-only
n
0x0
0x0
PAUSE0
PDMA Channel n Transfer Pause Control (Write Only)
0
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE1
PDMA Channel n Transfer Pause Control (Write Only)
1
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE2
PDMA Channel n Transfer Pause Control (Write Only)
2
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE3
PDMA Channel n Transfer Pause Control (Write Only)
3
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE4
PDMA Channel n Transfer Pause Control (Write Only)
4
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE5
PDMA Channel n Transfer Pause Control (Write Only)
5
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE6
PDMA Channel n Transfer Pause Control (Write Only)
6
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PAUSE7
PDMA Channel n Transfer Pause Control (Write Only)
7
1
write-only
0
No effect
#0
1
Pause PDMA channel n transfer
#1
PRICLR
PDMA_PRICLR
PDMA Fixed Priority Clear Register
0x414
write-only
n
0x0
0x0
FPRICLR0
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
0
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR1
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
1
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR2
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
2
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR3
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
3
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR4
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
4
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR5
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
5
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR6
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
6
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
FPRICLR7
PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
7
1
write-only
0
No effect
#0
1
Clear PDMA channel [n] fixed priority setting
#1
PRISET
PDMA_PRISET
PDMA Fixed Priority Setting Register
0x410
read-write
n
0x0
0x0
FPRISET0
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
0
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET1
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
1
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET2
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
2
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET3
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
3
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET4
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
4
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET5
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
5
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET6
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
6
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
FPRISET7
PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
7
1
read-write
0
No effect.\nCorresponding PDMA channel is round-robin priority
#0
1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
#1
REQSEL0_3
PDMA_REQSEL0_3
PDMA Request Source Select Register 0
0x480
read-write
n
0x0
0x0
REQSRC0
Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
0
7
read-write
0
Disable PDMA peripheral request
0
1
Reserved.
1
10
Reserved.
10
11
Reserved.
11
12
Reserved.
12
13
Reserved.
13
14
Reserved.
14
15
Reserved.
15
16
Channel connects to USCI0_TX
16
17
Channel connects to USCI0_RX
17
18
Channel connects to USCI1_TX
18
19
Channel connects to USCI1_RX
19
2
Reserved.
2
20
Channel connects to SPI0_TX
20
21
Channel connects to SPI0_RX
21
22
Channel connects to SPI1_TX
22
23
Channel connects to SPI1_RX
23
24
Reserved.
24
25
Reserved.
25
26
Reserved.
26
27
Reserved.
27
28
Reserved.
28
29
Reserved.
29
3
Reserved.
3
30
Reserved.
30
31
Reserved.
31
32
Channel connects to PWM0_P1_RX
32
33
Channel connects to PWM0_P2_RX
33
34
Channel connects to PWM0_P3_RX
34
35
Channel connects to PWM1_P1_RX
35
36
Channel connects to PWM1_P2_RX
36
37
Channel connects to PWM1_P3_RX
37
38
Channel connects to I2C0_TX
38
39
Channel connects to I2C0_RX
39
4
Channel connects to UART0_TX
4
40
Channel connects to I2C1_TX
40
41
Channel connects to I2C1_RX
41
42
Reserved.
42
43
Reserved.
43
44
Reserved.
44
45
Reserved.
45
46
Channel connects to TMR0
46
47
Channel connects to TMR1
47
48
Channel connects to TMR2
48
49
Channel connects to TMR3
49
5
Channel connects to UART0_RX
5
50
Channel connects to ADC_RX
50
52
Reserved.
52
53
Reserved.
53
54
Reserved.
54
55
Reserved.
55
56
Reserved.
56
57
Reserved.
57
58
Reserved.
58
59
Reserved.
59
6
Channel connects to UART1_TX
6
60
Reserved.
60
61
Reserved.
61
62
Reserved.
62
63
Reserved.
63
64
Reserved.
64
65
Reserved.
65
7
Channel connects to UART1_RX
7
8
Channel connects to UART2_TX
8
9
Channel connects to UART2_RX
9
REQSRC1
Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
7
read-write
REQSRC2
Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
7
read-write
REQSRC3
Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
7
read-write
REQSEL4_7
PDMA_REQSEL4_7
PDMA Request Source Select Register 1
0x484
read-write
n
0x0
0x0
REQSRC4
Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
0
7
read-write
REQSRC5
Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
8
7
read-write
REQSRC6
Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
16
7
read-write
REQSRC7
Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
24
7
read-write
SCATBA
PDMA_SCATBA
PDMA Scatter-gather Descriptor Table Base Address Register
0x43C
read-write
n
0x0
0x0
SCATBA
PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode.
16
16
read-write
SPI
PDMA_SPI
PDMA with SPI Performance Improvement Register
0x464
read-write
n
0x0
0x0
STCR0
PDMA_STCR0
Stride Transfer Count Register of PDMA Channel 0
0x500
read-write
n
0x0
0x0
STC
PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row.
0
16
read-write
STCR1
PDMA_STCR1
Stride Transfer Count Register of PDMA Channel 1
0x508
read-write
n
0x0
0x0
STCR2
PDMA_STCR2
Stride Transfer Count Register of PDMA Channel 2
0x510
read-write
n
0x0
0x0
STCR3
PDMA_STCR3
Stride Transfer Count Register of PDMA Channel 3
0x518
read-write
n
0x0
0x0
STCR4
PDMA_STCR4
Stride Transfer Count Register of PDMA Channel 4
0x520
read-write
n
0x0
0x0
STCR5
PDMA_STCR5
Stride Transfer Count Register of PDMA Channel 5
0x528
read-write
n
0x0
0x0
SWREQ
PDMA_SWREQ
PDMA Software Request Register
0x408
write-only
n
0x0
0x0
SWREQ0
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
0
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ1
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
1
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ2
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
2
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ3
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
3
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ4
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
4
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ5
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
5
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ6
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
6
1
write-only
0
No effect
#0
1
Generate a software request
#1
SWREQ7
PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
7
1
write-only
0
No effect
#0
1
Generate a software request
#1
TACTSTS
PDMA_TACTSTS
PDMA Transfer Active Flag Register
0x42C
read-only
n
0x0
0x0
TXACTF0
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
0
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF1
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
1
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF2
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
2
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF3
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
3
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF4
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
4
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF5
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
5
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF6
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
6
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TXACTF7
Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
7
1
read-only
0
PDMA channel is not finished
#0
1
PDMA channel is active
#1
TDSTS
PDMA_TDSTS
PDMA Channel Transfer Done Flag Register
0x424
read-write
n
0x0
0x0
TDIF0
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
0
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF1
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
1
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF2
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
2
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF3
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
3
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF4
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
4
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF5
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
5
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF6
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
6
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TDIF7
Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
7
1
read-write
0
PDMA channel transfer has not finished
#0
1
PDMA channel has finished transmission
#1
TOC0_1
PDMA_TOC0_1
PDMA Time-out Counter Ch1 and Ch0 Register
0x440
read-write
n
0x0
0x0
TOC0
Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC0[2:0]) clock.
0
16
read-write
TOC1
Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC0[6:4]) clock. The example of time-out period can refer TOC0 bit description.
16
16
read-write
TOUTEN
PDMA_TOUTEN
PDMA Time-out Enable Register
0x434
read-write
n
0x0
0x0
TOUTEN0
PDMA Time-out Enable Bits
0
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTEN1
PDMA Time-out Enable Bits
1
1
read-write
0
PDMA Channel n time-out function Disabled
#0
1
PDMA Channel n time-out function Enabled
#1
TOUTIEN
PDMA_TOUTIEN
PDMA Time-out Interrupt Enable Register
0x438
read-write
n
0x0
0x0
TOUTIEN0
PDMA Time-out Interrupt Enable Bits
0
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTIEN1
PDMA Time-out Interrupt Enable Bits
1
1
read-write
0
PDMA Channel n time-out interrupt Disabled
#0
1
PDMA Channel n time-out interrupt Enabled
#1
TOUTPSC
PDMA_TOUTPSC
PDMA Time-out Prescaler Register
0x430
read-write
n
0x0
0x0
TOUTPSC0
PDMA Channel 0 Time-out Clock Source Prescaler Bits
0
3
read-write
0
PDMA channel 0 time-out clock source is HCLK/28
#000
1
PDMA channel 0 time-out clock source is HCLK/29
#001
2
PDMA channel 0 time-out clock source is HCLK/210
#010
3
PDMA channel 0 time-out clock source is HCLK/211
#011
4
PDMA channel 0 time-out clock source is HCLK/212
#100
5
PDMA channel 0 time-out clock source is HCLK/213
#101
6
PDMA channel 0 time-out clock source is HCLK/214
#110
7
PDMA channel 0 time-out clock source is HCLK/215
#111
TOUTPSC1
PDMA Channel 1 Time-out Clock Source Prescaler Bits
4
3
read-write
0
PDMA channel 1 time-out clock source is HCLK/28
#000
1
PDMA channel 1 time-out clock source is HCLK/29
#001
2
PDMA channel 1 time-out clock source is HCLK/210
#010
3
PDMA channel 1 time-out clock source is HCLK/211
#011
4
PDMA channel 1 time-out clock source is HCLK/212
#100
5
PDMA channel 1 time-out clock source is HCLK/213
#101
6
PDMA channel 1 time-out clock source is HCLK/214
#110
7
PDMA channel 1 time-out clock source is HCLK/215
#111
TRGSTS
PDMA_TRGSTS
PDMA Channel Request Status Register
0x40C
read-only
n
0x0
0x0
REQSTS0
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
0
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS1
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
1
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS2
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
2
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS3
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
3
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS4
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
4
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS5
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
5
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS6
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
6
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
REQSTS7
PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
7
1
read-only
0
PDMA Channel n has no request
#0
1
PDMA Channel n has a request
#1
PSIO
PSIO Register Map
PSIO
0x0
0x0
0x5C
registers
n
0x100
0x1C
registers
n
0x120
0x1C
registers
n
0x60
0x1C
registers
n
0x80
0x1C
registers
n
0xA0
0x1C
registers
n
0xC0
0x1C
registers
n
0xE0
0x1C
registers
n
INTCTL
PSIO_INTCTL
PSIO Interrupt Control Register
0x0
read-write
n
0x0
0x0
CONI0SCS
Configurable Interrupt 0 Slot Controller Selection \nSelect Slot controller for INT0
8
2
read-write
0
Slot controller 0
#00
1
Slot controller 1
#01
2
Slot controller 2
#10
3
Slot controller 3
#11
CONI0SS
Configurable Interrupt 0 Slot Selection \n0000: NO USE\n0001: SLOT0\n0010: SLOT1\n0011: SLOT2\n0100: SLOT3\n0101: SLOT4\n0110: SLOT5\n0111: SLOT6\n1000: SLOT7\n1001 - 1111:Reserved
0
3
read-write
CONI1SCS
Configurable Interrupt 1 Slot Controller Selection \nSelect Slot controller for INT1
12
2
read-write
0
Slot controller 0
#00
1
Slot controller 1
#01
2
Slot controller 2
#10
3
Slot controller 3
#11
CONI1SS
Configurable Interrupt 1 Slot Selection \n0000: NO USE\n0001: SLOT0\n0010: SLOT1\n0011: SLOT2\n0100: SLOT3\n0101: SLOT4\n0110: SLOT5\n0111: SLOT6\n1000: SLOT7\n1001 - 1111:Reserved
4
3
read-write
INTEN
PSIO_INTEN
PSIO Interrupt Enable Register
0x4
read-write
n
0x0
0x0
CON0IE
Configurable Interrupt 0 Enable Bit\nThis field is used to enable selective interrupt 0.
0
1
read-write
0
Selective interrupt 0 Disabled
#0
1
Selective interrupt 0 Enabled
#1
CON1IE
Configurable Interrupt 1 Enable Bit\nThis field is used to enable selective interrupt 1.
1
1
read-write
0
Selective interrupt 1 Disabled
#0
1
Selective interrupt 1 Enabled
#1
MISMATIE
Mismatch Interrupt Enable Bit\nThis field is used to enable mismatch interrupt.
2
1
read-write
0
Mismatch interrupt Disabled
#0
1
Mismatch interrupt Enabled
#1
SC0IE
Slot Controller 0 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 0 finish interrupt.\nNote: This bit can be cleared by writing 1.
4
1
read-write
0
Slot controller 0 finish interrupt Disabled
#0
1
Slot controller 0 finish interrupt Enabled
#1
SC1IE
Slot Controller 1 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 1 finish interrupt.\nNote: This bit can be cleared by writing 1.
5
1
read-write
0
Slot controller 1 finish interrupt Disabled
#0
1
Slot controller 1 finish interrupt Enabled
#1
SC2IE
Slot Controller 2 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 2 finish interrupt.\nNote: This bit can be cleared by writing 1.
6
1
read-write
0
Slot controller 2 finish interrupt Disabled
#0
1
Slot controller 2 finish interrupt Enabled
#1
SC3IE
Slot Controller 3 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 3 finish interrupt.\nNote: This bit can be cleared by writing 1.
7
1
read-write
0
Slot controller 3 finish interrupt Disabled
#0
1
Slot controller 3 finish interrupt Enabled
#1
TERRIE
Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt.
3
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
INTSTS
PSIO_INTSTS
PSIO Interrupt Status Register
0x8
read-write
n
0x0
0x0
CON0IF
Configurable Interrupt 0 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1.
0
1
read-write
0
Condition in PSIO_INTCTL is not triggered
#0
1
Condition in PSIO_INTCTL is triggered
#1
CON1IF
Configurable Interrupt 1 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1.
1
1
read-write
0
Condition in PSIO_INTCTL is not triggered
#0
1
Condition in PSIO_INTCTL is triggered
#1
MISMATIF
Mismatch Interrupt Flag\nThis flag shows the amounts of data are not the same in each pins with PDMA enabled. \nIf this situation happens, all slot controllers stop counting.\nNote1: This flag is only effective on the pin with PDMA enabled.\nNote2: This bit can be cleared by writing 1.
2
1
read-write
0
Each pin with PDMA enabled receive or transfer data in the same rate
#0
1
Each pin with PDMA enabled receive or transfer data in different rate
#1
SC0IF
Slot Controller 0 Counting Done Interrupt Status Flag\nThis field is used for slot controller 0 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
4
1
read-write
0
Slot controller 0 done interrupt did not occur
#0
1
Slot controller 0 done interrupt occurred
#1
SC1IF
Slot Controller 1 Counting Done Interrupt Status Flag\nThis field is used for slot controller 1 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
5
1
read-write
0
Slot controller 1 done interrupt did not occur
#0
1
Slot controller 1 done interrupt occurred
#1
SC2IF
Slot Controller 2 Counting Done Interrupt Status Flag\nThis field is used for slot controller 2 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
6
1
read-write
0
Slot controller 2 done interrupt did not occur
#0
1
Slot controller 2 done interrupt occurred
#1
SC3IF
Slot Controller 3 Counting Done Interrupt Status Flag\nThis field is used for slot controller 3 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
7
1
read-write
0
Slot controller 3 done interrupt did not occur
#0
1
Slot controller 3 done interrupt occurred
#1
TERRIF
Transfer Error Interrupt Status Flag \nThis field is used for transfer error interrupt status flag. The transfer error states is at PSIO_DATCTL register which includes receive buffer overflow error INOVER (PSIOn_DATCTL[14]), transmit buffer shortage error OUTUFER (PSIOn_DATCTL[6])\nNote1: This field is the status flag of INOVER or OUTUFER.\nNote2: This bit can only be cleared by writing 1 to coordinate transfer error.
3
1
read-write
0
Transfer error interrupt did not occur
#0
1
Transfer error interrupt occurred
#1
ISSTS
PSIO_ISSTS
PSIO Input Status State Register
0x10
read-write
n
0x0
0x0
INSTSOV0
Input Status Overflow 0\nNote: This overflow bit can be write 1 clear..
1
1
read-write
0
The pin 0 input Status does not overflow
#0
1
The pin 0 input Status occur overflow
#1
INSTSOV1
Input Status Overflow 1\nNote: This overflow bit can be write 1 clear..
3
1
read-write
0
The pin 1 input Status does not overflow
#0
1
The pin 1 input Status occur overflow
#1
INSTSOV2
Input Status Overflow 2\nNote: This overflow bit can be write 1 clear..
5
1
read-write
0
The pin 2 input Status does not overflow
#0
1
The pin 2 input Status occur overflow
#1
INSTSOV3
Input Status Overflow 3\nNote: This overflow bit can be write 1 clear..
7
1
read-write
0
The pin 3 input Status does not overflow
#0
1
The pin 3 input Status occur overflow
#1
INSTSOV4
Input Status Overflow 4\nNote: This overflow bit can be write 1 clear..
9
1
read-write
0
The pin 4 input Status does not overflow
#0
1
The pin 4 input Status occur overflow
#1
INSTSOV5
Input Status Overflow 5\nNote: This overflow bit can be write 1 clear..
11
1
read-write
0
The pin 5 input Status does not overflow
#0
1
The pin 5 input Status occur overflow
#1
INSTSOV6
Input Status Overflow 6\nNote: This overflow bit can be write 1 clear..
13
1
read-write
0
The pin 6 input Status does not overflow
#0
1
The pin 6 input Status occur overflow
#1
INSTSOV7
Input Status Overflow 7\nNote: This overflow bit can be write 1 clear..
15
1
read-write
0
The pin7 input Status does not overflow
#0
1
The pin7 input Status occur overflow
#1
VALID0
Input Status Valid 0\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
0
1
read-write
0
The pin 0 input Status is not ready
#0
1
The pin 0 input Status is ready
#1
VALID1
Input Status Valid 1\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
2
1
read-write
0
The pin 1 input Status is not ready
#0
1
The pin 1 input Status is ready
#1
VALID2
Input Status Valid 2\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
4
1
read-write
0
The pin 2 input Status is not ready
#0
1
The pin 2 input Status is ready
#1
VALID3
Input Status Valid 3\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
6
1
read-write
0
The pin 3 input Status is not ready
#0
1
The pin 3 input Status is ready
#1
VALID4
Input Status Valid 4\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
8
1
read-write
0
The pin 4 input Status is not ready
#0
1
The pin 4 input Status is ready
#1
VALID5
Input Status Valid 5\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
10
1
read-write
0
The pin 5 input Status is not ready
#0
1
The pin 5 input Status is ready
#1
VALID6
Input Status Valid 6\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
12
1
read-write
0
The pin 6 input Status is not ready
#0
1
The pin 6 input Status is ready
#1
VALID7
Input Status Valid 7\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
14
1
read-write
0
The pin7 input Status is not ready
#0
1
The pin7 input Status is ready
#1
PDMACTL
PSIO_PDMACTL
PSIO PDMA Control Register
0x14
read-write
n
0x0
0x0
INNUM
PDMA Input Current Number (Read Only)\nThis register shows the current pin number of input register read by PDMA.
24
4
read-only
0
PDMA IDLE
#0000
1
pin 0
#0001
2
pin 1
#0010
3
pin 2
#0011
4
pin 3
#0100
5
pin 4
#0101
6
pin 5
#0110
7
pin 6
#0111
8
pin 7
#1000
9
PDMA WAIT
#1001
INSCSEL
PDMA Input Data Slot Controller Selection\n00: slot controller 0.\n01: slot controller 1.\n10: slot controller 2.\n11: slot controller 3.
28
2
read-write
IPIN0EN
Input PDMA Pin0 Enable Bit
8
1
read-write
0
Pin0 input PDMA function Disabled
#0
1
Pin0 input PDMA function Enabled
#1
IPIN1EN
Input PDMA Pin1 Enable Bit
9
1
read-write
0
Pin1 input PDMA function Disabled
#0
1
Pin1 input PDMA function Enabled
#1
IPIN2EN
Input PDMA Pin2 Enable Bit
10
1
read-write
0
Pin2 input PDMA function Disabled
#0
1
Pin2 input PDMA function Enabled
#1
IPIN3EN
Input PDMA Pin3 Enable Bit
11
1
read-write
0
Pin3 input PDMA function Disabled
#0
1
Pin3 input PDMA function Enabled
#1
IPIN4EN
Input PDMA Pin4 Enable Bit
12
1
read-write
0
Pin4 input PDMA function Disabled
#0
1
Pin4 input PDMA function Enabled
#1
IPIN5EN
Input PDMA Pin5 Enable Bit
13
1
read-write
0
Pin5 input PDMA function Disabled
#0
1
Pin5 input PDMA function Enabled
#1
IPIN6EN
Input PDMA Pin6 Enable Bit
14
1
read-write
0
Pin6 input PDMA function Disabled
#0
1
Pin6 input PDMA function Enabled
#1
IPIN7EN
Input PDMA Pin7 Enable Bit
15
1
read-write
0
Pin7 input PDMA function Disabled
#0
1
Pin7 input PDMA function Enabled
#1
OPIN0EN
Output PDMA Pin0 Enable Bit
0
1
read-write
0
Pin0 output PDMA function Disabled
#0
1
Pin0 output PDMA function Enabled
#1
OPIN1EN
Output PDMA Pin1 Enable Bit
1
1
read-write
0
Pin1 output PDMA function Disabled
#0
1
Pin1 output PDMA function Enabled
#1
OPIN2EN
Output PDMA Pin2 Enable Bit
2
1
read-write
0
Pin2 output PDMA function Disabled
#0
1
Pin2 output PDMA function Enabled
#1
OPIN3EN
Output PDMA Pin3 Enable Bit
3
1
read-write
0
Pin3 output PDMA function Disabled
#0
1
Pin3 output PDMA function Enabled
#1
OPIN4EN
Output PDMA Pin4 Enable Bit
4
1
read-write
0
Pin4 output PDMA function Disabled
#0
1
Pin4 output PDMA function Enabled
#1
OPIN5EN
Output PDMA Pin5 Enable Bit
5
1
read-write
0
Pin5 output PDMA function Disabled
#0
1
Pin5 output PDMA function Enabled
#1
OPIN6EN
Output PDMA Pin6 Enable Bit
6
1
read-write
0
Pin6 output PDMA function Disabled
#0
1
Pin6 output PDMA function Enabled
#1
OPIN7EN
Output PDMA Pin7 Enable Bit
7
1
read-write
0
Pin7 output PDMA function Disabled
#0
1
Pin7 output PDMA function Enabled
#1
OUTNUM
PDMA Output Current Number (Read Only)\nThis register shows the current pin number of output register write by PDMA.
16
4
read-only
0
PDMA IDLE
#0000
1
pin 0
#0001
2
pin 1
#0010
3
pin 2
#0011
4
pin 3
#0100
5
pin 4
#0101
6
pin 5
#0110
7
pin 6
#0111
8
pin 7
#1000
9
PDMA WAIT
#1001
OUTSCSEL
PDMA Output Data Slot Controller Selection\n00: slot controller 0.\n01: slot controller 1.\n10: slot controller 2.\n11: slot controller 3.
20
2
read-write
PIDAT
PSIO_PIDAT
PSIO PDMA Input Data Register
0x1C
read-write
n
0x0
0x0
PDMAIN
PDMA Input Data\nThis register is used for PSIO with PDMA single mode, and set PDMA with fixed address.\nWhen PSIO in PDMA mode, setting PDMA to read data from this register.\nThe data in this register will be updated from corresponding PSIOn_INDATA register in order, when Input Data Full Flag is 1 and PDMA mode enable.
0
32
read-write
PODAT
PSIO_PODAT
PSIO PDMA Output Data Register
0x18
write-only
n
0x0
0x0
PDMAOUT
PDMA Output Data\nThis register is used for PSIO with PDMA single mode, and set PDMA with fixed address.\nWhen PSIO in PDMA mode, setting PDMA to write data to this register.\nThe data in this register will be placed to corresponding PSIOn_OUTDATA register in order, when Output Data Empty Flag is 1 and PDMA mode enabled.
0
32
write-only
PSIO0_CPCTL0
PSIO0_CPCTL0
PSIOn Check Point Control 0 Register
0x54
read-write
n
0x0
0x0
CKPT0
Check Point 0\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
0
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT1
Check Point 1\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
4
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT2
Check Point 2\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
8
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT3
Check Point 3\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered
12
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT4
Check Point 4\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
16
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT5
Check Point 5\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
20
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT6
Check Point 6\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
24
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT6
1000
CKPT7
Check Point 7\nThis field is used to link check point and slot controller slot.\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
28
3
read-write
0
No use
0000
1
SLOT0
0001
10
SLOT1
0010
11
SLOT2
0011
100
SLOT3
0100
101
SLOT4
0101
110
SLOT5
0110
111
SLOT6
0111
1000
SLOT7
1000
PSIO0_CPCTL1
PSIO0_CPCTL1
PSIOn Check Point Control1 Register
0x58
read-write
n
0x0
0x0
CKPT0ACT
Check Point 0 Action\nSelect output data source at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
0
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT1ACT
Check Point 1 Action\nSelect output data source at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
4
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT2ACT
Check Point 2 Action\nSelect output data source at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
8
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT3ACT
Check Point 3 Action\nSelect output data source at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
12
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT4ACT
Check Point 4 Action\nSelect output data source at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
16
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT5ACT
Check Point 5 Action\nSelect output data source at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
20
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
CKPT6ACT
Check Point 6 Action\nSelect output data source at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
24
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Iinput status record and update
#110
CKPT7ACT
Check Point 7 Action\nSelect output data source at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
28
3
read-write
0
Output level low
#000
1
Output level high
#001
2
Output from data buffer
#010
3
Output toggle
#011
4
Input data buffer
#100
5
Input status
#101
6
Input status record and update
#110
PSIO0_DATCTL
PSIO0_DATCTL
PSIOn Data Control Register
0x44
read-write
n
0x0
0x0
INDATWD
Input Data Width\nIndicate the data width of INPUT DATA register.
8
5
read-write
INDEPTH
Input Data Depth\nRepresent the data depth of the input buffer, when data width is larger than 16-bit, this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit , \nNote1: The data depth is impacted when the full flag and input over flow flag is set to 1.\nNote2: There is no difference of data depth no matter using software program data or PDMA program data.
28
2
read-write
0
INDEPTH[0], the data depth is 1.\nINDEPTH, the data depth is 1
0
1
INDEPTH[0], the data depth is 2.\nINDEPTH, the data depth is 2
1
2
INDEPTH, the data depth is 3
2
3
INDEPTH, the data depth is 4
3
ORDER
Order\nThe order of output data and input data\nData transfer start form
16
1
read-write
0
LSB
#0
1
MSB
#1
OUTDATWD
Output Data Width\nIndicate the data width of OUTPUT DATA register.
0
5
read-write
OUTDEPTH
Output Data Depth\nRepresent the data depth of the output buffer, when data width is larger than 16-bit, this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit , \nNote1: data depth impact when the output empty flag and output under flow flag will be set to 1.\nNote2: There is no difference of data depth no matter using software program data or PDMA program data.
24
2
read-write
0
OUTDEPTH [0], the data depth is 1.\nOUTDEPTH, the data depth is 1
0
1
OUTDEPTH [0], the data depth is 2.\nOUTDEPTH, the data depth is 2
1
2
OUTDEPTH, the data depth is 3
2
3
OUTDEPTH, the data depth is 4
3
PSIO0_GENCTL
PSIO0_GENCTL
PSIOn General Control Register
0x40
read-write
n
0x0
0x0
INITIAL
Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote1: Only when IO_MODE is not input mode, this register is effective.\nNote2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is high.
2
2
read-write
0
Low level
#00
1
High level
#01
2
Last output
#10
3
Toggle
#11
INTERVAL
Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote1: Only when IO_MODE is not input mode, then this register is effective.\nNote2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is low.
4
2
read-write
0
Low level
#00
1
High level
#01
2
Last output
#10
3
Toggle
#11
IOMODE
IO Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote1: When slot controller stops counting, it will switch to the current I/O mode setting.\nNote2: When PSIO uses quasi mode or open drain mode to trigger slot controller, the initial or interval state needs to be set output high level, or the pin will not be triggered.
0
2
read-write
0
Input mode
#00
1
Output mode
#01
2
Open-drain
#10
3
Quasi-bidirectional Mode
#11
MODESW0
Mode Switch0 Point\nMode at the switch0 point.
16
2
read-write
0
Input mode
#00
1
Output mode
#01
2
Open-drain
#10
3
Quasi-bidirectional Mode
#11
MODESW1
Mode Switch1 Point\nMode at the switch1 point
18
2
read-write
0
Input mode
#00
1
Output mode
#01
2
Open-drain mode
#10
3
Quasi-bidirectional Mode
#11
PINEN
Pin Enable Bit
26
1
read-write
0
Pin Disabled
#0
1
Pin Enabled
#1
SCSEL
Slot Controller Selection\nSelect slot controller for check point.
24
2
read-write
0
SLOT CONTROLLER0
#00
1
SLOT CONTROLLER1
#01
2
SLOT CONTROLLER2
#10
3
SLOT CONTROLLER3
#11
SW0CP
Switch0 Check Point\nOthers: reserved
8
4
read-write
0
No use
#0000
1
CHECK POINT0
#0001
2
CHECK POINT1
#0010
3
CHECK POINT 2
#0011
4
CHECK POINT 3
#0100
5
CHECK POINT 4
#0101
6
CHECK POINT 5
#0110
7
CHECK POINT 6
#0111
8
CHECK POINT 7
#1000
SW1CP
Switch1 Check Point\nOthers: reserved
12
4
read-write
0
No use
#0000
1
CHECK POINT0
#0001
2
CHECK POINT1
#0010
3
CHECK POINT 2
#0011
4
CHECK POINT 3
#0100
5
CHECK POINT 4
#0101
6
CHECK POINT 5
#0110
7
CHECK POINT 6
#0111
8
CHECK POINT 7
#1000
PSIO0_INDAT
PSIO0_INDAT
PSIOn Input Data Register
0x4C
read-only
n
0x0
0x0
INDAT
Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, PSIO sample input data when the slot controller count to 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9.
0
32
read-only
PSIO0_INSTS
PSIO0_INSTS
PSIOn Input Status Register
0x48
read-only
n
0x0
0x0
INSTS
Input Status\nStatus input buffer\n(read clear)\nNote: When the valid bit is set, the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update.
0
8
read-only
PSIO0_OUTDAT
PSIO0_OUTDAT
PSIOn Output Data Register
0x50
write-only
n
0x0
0x0
OUTDAT
Output Data Buffer\nThis field is used to configure output data.
0
32
write-only
PSIO1_CPCTL0
PSIO1_CPCTL0
PSIOn Check Point Control 0 Register
0x74
read-write
n
0x0
0x0
PSIO1_CPCTL1
PSIO1_CPCTL1
PSIOn Check Point Control1 Register
0x78
read-write
n
0x0
0x0
PSIO1_DATCTL
PSIO1_DATCTL
PSIOn Data Control Register
0x64
read-write
n
0x0
0x0
PSIO1_GENCTL
PSIO1_GENCTL
PSIOn General Control Register
0x60
read-write
n
0x0
0x0
PSIO1_INDAT
PSIO1_INDAT
PSIOn Input Data Register
0x6C
read-write
n
0x0
0x0
PSIO1_INSTS
PSIO1_INSTS
PSIOn Input Status Register
0x68
read-write
n
0x0
0x0
PSIO1_OUTDAT
PSIO1_OUTDAT
PSIOn Output Data Register
0x70
read-write
n
0x0
0x0
PSIO2_CPCTL0
PSIO2_CPCTL0
PSIOn Check Point Control 0 Register
0x94
read-write
n
0x0
0x0
PSIO2_CPCTL1
PSIO2_CPCTL1
PSIOn Check Point Control1 Register
0x98
read-write
n
0x0
0x0
PSIO2_DATCTL
PSIO2_DATCTL
PSIOn Data Control Register
0x84
read-write
n
0x0
0x0
PSIO2_GENCTL
PSIO2_GENCTL
PSIOn General Control Register
0x80
read-write
n
0x0
0x0
PSIO2_INDAT
PSIO2_INDAT
PSIOn Input Data Register
0x8C
read-write
n
0x0
0x0
PSIO2_INSTS
PSIO2_INSTS
PSIOn Input Status Register
0x88
read-write
n
0x0
0x0
PSIO2_OUTDAT
PSIO2_OUTDAT
PSIOn Output Data Register
0x90
read-write
n
0x0
0x0
PSIO3_CPCTL0
PSIO3_CPCTL0
PSIOn Check Point Control 0 Register
0xB4
read-write
n
0x0
0x0
PSIO3_CPCTL1
PSIO3_CPCTL1
PSIOn Check Point Control1 Register
0xB8
read-write
n
0x0
0x0
PSIO3_DATCTL
PSIO3_DATCTL
PSIOn Data Control Register
0xA4
read-write
n
0x0
0x0
PSIO3_GENCTL
PSIO3_GENCTL
PSIOn General Control Register
0xA0
read-write
n
0x0
0x0
PSIO3_INDAT
PSIO3_INDAT
PSIOn Input Data Register
0xAC
read-write
n
0x0
0x0
PSIO3_INSTS
PSIO3_INSTS
PSIOn Input Status Register
0xA8
read-write
n
0x0
0x0
PSIO3_OUTDAT
PSIO3_OUTDAT
PSIOn Output Data Register
0xB0
read-write
n
0x0
0x0
PSIO4_CPCTL0
PSIO4_CPCTL0
PSIOn Check Point Control 0 Register
0xD4
read-write
n
0x0
0x0
PSIO4_CPCTL1
PSIO4_CPCTL1
PSIOn Check Point Control1 Register
0xD8
read-write
n
0x0
0x0
PSIO4_DATCTL
PSIO4_DATCTL
PSIOn Data Control Register
0xC4
read-write
n
0x0
0x0
PSIO4_GENCTL
PSIO4_GENCTL
PSIOn General Control Register
0xC0
read-write
n
0x0
0x0
PSIO4_INDAT
PSIO4_INDAT
PSIOn Input Data Register
0xCC
read-write
n
0x0
0x0
PSIO4_INSTS
PSIO4_INSTS
PSIOn Input Status Register
0xC8
read-write
n
0x0
0x0
PSIO4_OUTDAT
PSIO4_OUTDAT
PSIOn Output Data Register
0xD0
read-write
n
0x0
0x0
PSIO5_CPCTL0
PSIO5_CPCTL0
PSIOn Check Point Control 0 Register
0xF4
read-write
n
0x0
0x0
PSIO5_CPCTL1
PSIO5_CPCTL1
PSIOn Check Point Control1 Register
0xF8
read-write
n
0x0
0x0
PSIO5_DATCTL
PSIO5_DATCTL
PSIOn Data Control Register
0xE4
read-write
n
0x0
0x0
PSIO5_GENCTL
PSIO5_GENCTL
PSIOn General Control Register
0xE0
read-write
n
0x0
0x0
PSIO5_INDAT
PSIO5_INDAT
PSIOn Input Data Register
0xEC
read-write
n
0x0
0x0
PSIO5_INSTS
PSIO5_INSTS
PSIOn Input Status Register
0xE8
read-write
n
0x0
0x0
PSIO5_OUTDAT
PSIO5_OUTDAT
PSIOn Output Data Register
0xF0
read-write
n
0x0
0x0
PSIO6_CPCTL0
PSIO6_CPCTL0
PSIOn Check Point Control 0 Register
0x114
read-write
n
0x0
0x0
PSIO6_CPCTL1
PSIO6_CPCTL1
PSIOn Check Point Control1 Register
0x118
read-write
n
0x0
0x0
PSIO6_DATCTL
PSIO6_DATCTL
PSIOn Data Control Register
0x104
read-write
n
0x0
0x0
PSIO6_GENCTL
PSIO6_GENCTL
PSIOn General Control Register
0x100
read-write
n
0x0
0x0
PSIO6_INDAT
PSIO6_INDAT
PSIOn Input Data Register
0x10C
read-write
n
0x0
0x0
PSIO6_INSTS
PSIO6_INSTS
PSIOn Input Status Register
0x108
read-write
n
0x0
0x0
PSIO6_OUTDAT
PSIO6_OUTDAT
PSIOn Output Data Register
0x110
read-write
n
0x0
0x0
PSIO7_CPCTL0
PSIO7_CPCTL0
PSIOn Check Point Control 0 Register
0x134
read-write
n
0x0
0x0
PSIO7_CPCTL1
PSIO7_CPCTL1
PSIOn Check Point Control1 Register
0x138
read-write
n
0x0
0x0
PSIO7_DATCTL
PSIO7_DATCTL
PSIOn Data Control Register
0x124
read-write
n
0x0
0x0
PSIO7_GENCTL
PSIO7_GENCTL
PSIOn General Control Register
0x120
read-write
n
0x0
0x0
PSIO7_INDAT
PSIO7_INDAT
PSIOn Input Data Register
0x12C
read-write
n
0x0
0x0
PSIO7_INSTS
PSIO7_INSTS
PSIOn Input Status Register
0x128
read-write
n
0x0
0x0
PSIO7_OUTDAT
PSIO7_OUTDAT
PSIOn Output Data Register
0x130
read-write
n
0x0
0x0
SC0CTL
PSIO_SC0CTL
PSIO Slot Controller n Control Register
0x20
read-write
n
0x0
0x0
BUSY
PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller start to count automatically and it will be cleared to 0 automatically when slot controller stop counting, too.
24
1
read-write
0
PSIO_SCn is not busy
#0
1
PSIO_SCn is busy
#1
ENDSLOT
End Slot Period\nThe end slot of the repeat period
4
4
read-write
0
No use
#0000
1
SLOT0
#0001
2
SLOT1
#0010
3
SLOT2
#0011
4
SLOT3
#0100
5
SLOT4
#0101
6
SLOT5
#0110
7
SLOT6
#0111
8
SLOT7
#1000
IDLE
PSIO_SCn Idle Flag\nNote1: This bit will be cleared to 0 when slot controller start to count automatically. \nNote2: This bit will be set to 1 when configuring it 1 by software. \nNote3: This bit is set to distinguish INTERVAL_OUTPUT(PSIOn_GENCTL[5:4]) and INITIAL_OUTPUT(PSIOn_GENCTL[3:2]).
25
1
read-write
0
PSIO_SCn is not IDLE
#0
1
PSIO_SCn is IDLE
#1
INISLOT
Initial Slot Period\nThe initial slot of the repeat period
0
4
read-write
0
No use
#0000
1
SLOT0
#0001
2
SLOT1
#0010
3
SLOT2
#0011
4
SLOT3
#0100
5
SLOT4
#0101
6
SLOT5
#0110
7
SLOT6
#0111
8
SLOT7
#1000
REPEAT
Whole Repeat Mode\nSlot controller repeats counting forever. It can stop by clear START bit.\nNote1: If this bit is enabled with PDMA mode, slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote2: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished.
17
1
read-write
0
Repeat mode Disabled
#0
1
Repeat mode Enabled
#1
SPLCNT
Slot Period Loop Count\n000000 ~ 111110: loop count\nNote1: If setting this register 111111 with PDMA mode and OUTPUT mode, it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote2: If setting this register 111111 with PDMA mode and INPUT mode, it will stop automatically when pdma is finished.\nNote3: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished.
8
6
read-write
0
slot period loop count function is disable
#000000
1
repeat selection loop once, which means total go through selected repeat slots 2 times
#000001
63
loop until stop PSIO slot controller
#111111
START
PSIO_SCn Start\nNote: this bit is always read as 0.
16
1
read-write
0
No use
#0
1
Start PSIO_SCn to count and active related PSIO_PIN
#1
STOP
PSIO_SCn Stop\nNote: This bit is always read as 0.
18
1
read-write
0
No use
#0
1
Stop PSIO_SCn
#1
TRIGSRC
PSIO_SCn Trigger Source\nNote1: PSIO slot controller pin can only be triggered by related pins set from PSIOn_GENCTL[25:24] SC_SEL.\nNote2: Configuring rising or falling signal trigger PSIO, the signal needs to hold for at least two PSIO_CLK for de-bounce or PSIO will not be triggered.
14
2
read-write
0
Trigger by software
00
1
Trigger PSIO_SCn when related PSIO_PIN occurred falling edge
01
2
Trigger PSIO_SCn when related PSIO_PIN occurred rising edge
02
3
Trigger PSIO_SCn when related PSIO_PIN occurred rising edge or falling edge
03
SC0SLOT
PSIO_SC0SLOT
PSIO Slot Controller n Slot Register
0x24
read-write
n
0x0
0x0
SLOT0
PSIO Slot Controller Slot0 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
0
4
read-write
SLOT1
PSIO Slot Controller Slot1 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
4
4
read-write
SLOT2
PSIO Slot Controller Slot2 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
8
4
read-write
SLOT3
PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
12
4
read-write
SLOT4
PSIO Slot Controller Slot4 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
16
4
read-write
SLOT5
PSIO Slot Controller Slot5 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
20
4
read-write
SLOT6
PSIO Slot Controller Slot6 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
24
4
read-write
SLOT7
PSIO Slot Controller Slot7 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
28
4
read-write
SC1CTL
PSIO_SC1CTL
PSIO Slot Controller n Control Register
0x28
read-write
n
0x0
0x0
SC1SLOT
PSIO_SC1SLOT
PSIO Slot Controller n Slot Register
0x2C
read-write
n
0x0
0x0
SC2CTL
PSIO_SC2CTL
PSIO Slot Controller n Control Register
0x30
read-write
n
0x0
0x0
SC2SLOT
PSIO_SC2SLOT
PSIO Slot Controller n Slot Register
0x34
read-write
n
0x0
0x0
SC3CTL
PSIO_SC3CTL
PSIO Slot Controller n Control Register
0x38
read-write
n
0x0
0x0
SC3SLOT
PSIO_SC3SLOT
PSIO Slot Controller n Slot Register
0x3C
read-write
n
0x0
0x0
TRANSTS
PSIO_TRANSTS
PSIO Transfer Status Register
0xC
read-write
n
0x0
0x0
INFULL0
Input Data Full Flag0 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
0
1
read-only
0
The pin0 input data is empty
#0
1
The pin0 input data is full
#1
INFULL1
Input Data Full Flag1 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
4
1
read-only
0
The pin1 input data is empty
#0
1
The pin1 input data is full
#1
INFULL2
Input Data Full Flag2 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
8
1
read-only
0
The pin2 input data is empty
#0
1
The pin2 input data is full
#1
INFULL3
Input Data Full Flag3 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
12
1
read-only
0
The pin3 input data is empty
#0
1
The pin3 input data is full
#1
INFULL4
Input Data Full Flag4 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
16
1
read-only
0
The pin4 input data is empty
#0
1
The pin4 input data is full
#1
INFULL5
Input Data Full Flag5 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
20
1
read-only
0
The pin5 input data is empty
#0
1
The pin5 input data is full
#1
INFULL6
Input Data Full Flag6 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
24
1
read-only
0
The pin6 input data is empty
#0
1
The pin6 input data is full
#1
INFULL7
Input Data Full Flag7 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
28
1
read-only
0
The pin7 input data is empty
#0
1
The pin7 input data is full
#1
INOVER0
Input Data Overflow Flag0\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
1
1
read-write
0
The pin0 input data does not occur overflow
#0
1
The pin0 input data occurs overflow
#1
INOVER1
Input Data Overflow Flag1\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
5
1
read-write
0
The pin1 input data does not occur overflow
#0
1
The pin1 input data occurs overflow
#1
INOVER2
Input Data Overflow Flag2\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
9
1
read-write
0
The pin2 input data does not occur overflow
#0
1
The pin2 input data occurs overflow
#1
INOVER3
Input Data Overflow Flag3\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
13
1
read-write
0
The pin3 input data does not occur overflow
#0
1
The pin3 input data occurs overflow
#1
INOVER4
Input Data Overflow Flag4\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
17
1
read-write
0
The pin4 input data does not occur overflow
#0
1
The pin4 input data occurs overflow
#1
INOVER5
Input Data Overflow Flag5\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
21
1
read-write
0
The pin5 input data does not occur overflow
#0
1
The pin5 input data occurs overflow
#1
INOVER6
Input Data Overflow Flag6\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
25
1
read-write
0
The pin6 input data does not occur overflow
#0
1
The pin6 input data occurs overflow
#1
INOVER7
Input Data Overflow Flag7\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
29
1
read-write
0
The pin7 input data does not occur overflow
#0
1
The pin7 input data occurs overflow
#1
OUTEPY0
Output Data Empty Flag0 (Read Only)
2
1
read-only
0
The pin0 output data is full
#0
1
The pin0 output data is empty
#1
OUTEPY1
Output Data Empty Flag1
6
1
read-write
0
The pin1 output data is full
#0
1
The pin1 output data is empty
#1
OUTEPY2
Output Data Empty Flag2 (Read Only)
10
1
read-only
0
The pin2 output data is full
#0
1
The pin2 output data is empty
#1
OUTEPY3
Output Data Empty Flag3 (Read Only)
14
1
read-only
0
The pin3 output data is full
#0
1
The pin3 output data is empty
#1
OUTEPY4
Output Data Empty Flag4 (Read Only)
18
1
read-only
0
The pin4 output data is full
#0
1
The pin4 output data is empty
#1
OUTEPY5
Output Data Empty Flag5 (Read Only)
22
1
read-only
0
The pin5 output data is full
#0
1
The pin5 output data is empty
#1
OUTEPY6
Output Data Empty Flag6 (Read Only)
26
1
read-only
0
The pin6 output data is full
#0
1
The pin6 output data is empty
#1
OUTEPY7
Output Data Empty Flag7 (Read Only)
30
1
read-only
0
The pin7 output data is full
#0
1
The pin7 output data is empty
#1
OUTUF0
Output Data Underflow Flag0\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
3
1
read-write
0
The pin0 output data is not overflow
#0
1
The pin0 output data is overflow
#1
OUTUF1
Output Data Underflow Flag1\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled
7
1
read-write
0
The pin1 output data is not overflow
#0
1
The pin1 output data is overflow
#1
OUTUF2
Output Data Underflow Flag2\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
11
1
read-write
0
The pin3 output data is not overflow
#0
1
The pin3 output data is overflow
#1
OUTUF3
Output Data Underflow Flag3\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
15
1
read-write
0
The pin3 output data is not overflow
#0
1
The pin3 output data is overflow
#1
OUTUF4
Output Data Underflow Flag4\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
19
1
read-write
0
The pin4 output data is not overflow
#0
1
The pin4 output data is overflow
#1
OUTUF5
Output Data Underflow Flag5\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin is enabled.
23
1
read-write
0
The pin5 output data is not overflow
#0
1
The pin5 output data is overflow
#1
OUTUF6
Output Data Underflow Flag6\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
27
1
read-write
0
The pin6 output data is not overflow
#0
1
The pin6 output data is overflow
#1
OUTUF7
Output Data Underflow Flag7\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
31
1
read-write
0
The pin7 output data is not overflow
#0
1
The pin7 output data is overflow
#1
PWM0
PWM Register Map
PWM
0x0
0x0
0x8
registers
n
0x10
0x18
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x200
0x4C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x30C
0x4
registers
n
0x314
0x4
registers
n
0x31C
0x18
registers
n
0x38
0x4
registers
n
0x40
0x4
registers
n
0x50
0x18
registers
n
0x70
0xC
registers
n
0x90
0x4
registers
n
0x98
0x4
registers
n
0xA0
0x4
registers
n
0xB0
0x40
registers
n
0xF8
0x8
registers
n
PWM_ADCTS0
PWM_ADCTS0
PWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
PWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH0 Trigger ADC function Disabled
#0
1
PWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
PWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH1 Trigger ADC function Disabled
#0
1
PWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
PWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
PWM_CH2 Trigger ADC function Disabled
#0
1
PWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
PWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
PWM_CH3 Trigger ADC function Disabled
#0
1
PWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
PWM_CH0 Trigger ADC Source Select
0
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
PWM_CH1 Trigger ADC Source Select
8
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
PWM_CH2 Trigger ADC Source Select
16
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
PWM_CH3 Trigger ADC Source Select
24
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
PWM_ADCTS1
PWM_ADCTS1
PWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
PWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH4 Trigger ADC function Disabled
#0
1
PWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
PWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH5 Trigger ADC function Disabled
#0
1
PWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
PWM_CH4 Trigger ADC Source Select
0
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
PWM_CH5 Trigger ADC Source Select
8
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
PWM_BNF
PWM_BNF
PWM Brake Noise Filter Register
0xC0
read-write
n
0x0
0x0
BK0SRC
Brake 0 Pin Source Select\nFor PWM0 setting:
16
1
read-write
0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#0
1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
#1
BK1SRC
Brake 1 Pin Source Select\nFor PWM0 setting:
24
1
read-write
0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#0
1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
#1
BRK0NFCNT
Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
4
3
read-write
BRK0NFEN
PWM Brake 0 Noise Filter Enable Bit
0
1
read-write
0
Noise filter of PWM Brake 0 Disabled
#0
1
Noise filter of PWM Brake 0 Enabled
#1
BRK0NFSEL
Brake 0 Edge Detector Filter Clock Selection
1
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK0PINV
Brake 0 Pin Inverse
7
1
read-write
0
The state of pin PWMx_BRAKE0 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector
#1
BRK1FCNT
Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
12
3
read-write
BRK1FEN
PWM Brake 1 Noise Filter Enable Bit
8
1
read-write
0
Noise filter of PWM Brake 1 Disabled
#0
1
Noise filter of PWM Brake 1 Enabled
#1
BRK1NFSEL
Brake 1 Edge Detector Filter Clock Selection
9
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK1PINV
Brake 1 Pin Inverse
15
1
read-write
0
The state of pin PWMx_BRAKE1 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector
#1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM Brake Edge Detect Control Register 0/1
0xC8
read-write
n
0x0
0x0
BRKAEVEN
PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
16
2
read-write
0
PWM even channel level-detect brake function not affect channel output
#00
1
PWM even channel output tri-state when level-detect brake happened
#01
2
PWM even channel output low level when level-detect brake happened
#10
3
PWM even channel output high level when level-detect brake happened
#11
BRKAODD
PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
18
2
read-write
0
PWM odd channel level-detect brake function not affect channel output
#00
1
PWM odd channel output tri-state when level-detect brake happened
#01
2
PWM odd channel output low level when level-detect brake happened
#10
3
PWM odd channel output high level when level-detect brake happened
#11
BRKP0EEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
BKP0 pin as edge-detect brake source Disabled
#0
1
BKP0 pin as edge-detect brake source Enabled
#1
BRKP0LEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE0 pin as level-detect brake source Enabled
#1
BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
BKP1 pin as edge-detect brake source Disabled
#0
1
BKP1 pin as edge-detect brake source Enabled
#1
BRKP1LEN
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE1 pin as level-detect brake source Enabled
#1
CPO0EBEN
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
ACMP0_O as edge-detect brake source Disabled
#0
1
ACMP0_O as edge-detect brake source Enabled
#1
CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
ACMP0_O as level-detect brake source Disabled
#0
1
ACMP0_O as level-detect brake source Enabled
#1
CPO1EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
ACMP1_O as edge-detect brake source Disabled
#0
1
ACMP1_O as edge-detect brake source Enabled
#1
CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
ACMP1_O as level-detect brake source Disabled
#0
1
ACMP1_O as level-detect brake source Enabled
#1
SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
7
1
read-write
0
System Fail condition as edge-detect brake source Disabled
#0
1
System Fail condition as edge-detect brake source Enabled
#1
SYSLBEN
Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
15
1
read-write
0
System Fail condition as level-detect brake source Disabled
#0
1
System Fail condition as level-detect brake source Enabled
#1
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM Brake Edge Detect Control Register 2/3
0xCC
read-write
n
0x0
0x0
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM Brake Edge Detect Control Register 4/5
0xD0
read-write
n
0x0
0x0
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
PWM_CAPIEN
PWM_CAPIEN
PWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIEN0
PWM Capture Falling Latch Interrupt Enable Bits
8
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN1
PWM Capture Falling Latch Interrupt Enable Bits
9
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN2
PWM Capture Falling Latch Interrupt Enable Bits
10
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN3
PWM Capture Falling Latch Interrupt Enable Bits
11
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN4
PWM Capture Falling Latch Interrupt Enable Bits
12
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN5
PWM Capture Falling Latch Interrupt Enable Bits
13
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPRIEN0
PWM Capture Rising Latch Interrupt Enable Bits
0
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN1
PWM Capture Rising Latch Interrupt Enable Bits
1
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN2
PWM Capture Rising Latch Interrupt Enable Bits
2
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN3
PWM Capture Rising Latch Interrupt Enable Bits
3
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN4
PWM Capture Rising Latch Interrupt Enable Bits
4
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN5
PWM Capture Rising Latch Interrupt Enable Bits
5
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
PWM_CAPIF
PWM_CAPIF
PWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CFLIF0
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF1
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF2
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF4
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF5
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIF0
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF1
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF2
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF4
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF5
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
1
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
2
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
3
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
4
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
5
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFLIFOV0
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
8
1
read-only
CFLIFOV1
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
9
1
read-only
CFLIFOV2
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
10
1
read-only
CFLIFOV3
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
11
1
read-only
CFLIFOV4
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
12
1
read-only
CFLIFOV5
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
13
1
read-only
CRLIFOV0
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
0
1
read-only
CRLIFOV1
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
1
1
read-only
CRLIFOV2
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
2
1
read-only
CRLIFOV3
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
3
1
read-only
CRLIFOV4
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
4
1
read-only
CRLIFOV5
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
5
1
read-only
PWM_CLKPSC0_1
PWM_CLKPSC0_1
PWM Clock Prescale Register 0/1
0x14
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
0
12
read-write
PWM_CLKPSC2_3
PWM_CLKPSC2_3
PWM Clock Prescale Register 2/3
0x18
read-write
n
0x0
0x0
PWM_CLKPSC4_5
PWM_CLKPSC4_5
PWM Clock Prescale Register 4/5
0x1C
read-write
n
0x0
0x0
PWM_CLKSRC
PWM_CLKSRC
PWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
PWM_CH01 External Clock Source Select
0
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC2
PWM_CH23 External Clock Source Select
8
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC4
PWM_CH45 External Clock Source Select
16
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
PWM_CMPBUF0
PWM_CMPBUF0
PWM CMPDAT0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
PWM_CMPBUF1
PWM_CMPBUF1
PWM CMPDAT1 Buffer
0x320
read-write
n
0x0
0x0
PWM_CMPBUF2
PWM_CMPBUF2
PWM CMPDAT2 Buffer
0x324
read-write
n
0x0
0x0
PWM_CMPBUF3
PWM_CMPBUF3
PWM CMPDAT3 Buffer
0x328
read-write
n
0x0
0x0
PWM_CMPBUF4
PWM_CMPBUF4
PWM CMPDAT4 Buffer
0x32C
read-write
n
0x0
0x0
PWM_CMPBUF5
PWM_CMPBUF5
PWM CMPDAT5 Buffer
0x330
read-write
n
0x0
0x0
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x54
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x58
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x60
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x64
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Counter Register 0
0x90
read-only
n
0x0
0x0
CNT
PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
PWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is counting down
#0
1
Counter is counting up
#1
PWM_CNT2
PWM_CNT2
PWM Counter Register 2
0x98
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Counter Register 4
0xA0
read-write
n
0x0
0x0
PWM_CNTCLR
PWM_CNTCLR
PWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR2
Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.
2
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR4
Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.
4
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
PWM Counter Enable Bit 0
0
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN2
PWM Counter Enable Bit 2
2
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN4
PWM Counter Enable Bit 4
4
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
PWM_CTL0
PWM_CTL0
PWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLDn
Center Load Enable Bits\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disable
#0
1
ICE debug mode counter halt Enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDENn
Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
PWM_CTL1
PWM_CTL1
PWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0
0
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE2
PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2
4
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE4
PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4
8
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
OUTMODEn
PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
24
3
read-write
0
PWM independent mode
0
1
PWM complementary mode
1
PWM_DTCTL0_1
PWM_DTCTL0_1
PWM Dead-time Control Register 0/1
0x70
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
24
1
read-write
0
Dead-time clock source from PWM_CLK
#0
1
Dead-time clock source from prescaler output
#1
DTCNT
Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
PWM_DTCTL2_3
PWM_DTCTL2_3
PWM Dead-time Control Register 2/3
0x74
read-write
n
0x0
0x0
PWM_DTCTL4_5
PWM_DTCTL4_5
PWM Dead-time Control Register 4/5
0x78
read-write
n
0x0
0x0
PWM_FAILBRK
PWM_FAILBRK
PWM System Fail Brake Control Register
0xC4
read-write
n
0x0
0x0
BODBRKEN
Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
1
1
read-write
0
Brake Function triggered by BOD Disabled
#0
1
Brake Function triggered by BOD Enabled
#1
CORBRKEN
Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
3
1
read-write
0
Brake Function triggered by Core lockup detection Disabled
#0
1
Brake Function triggered by Core lockup detection Enabled
#1
CSSBRKEN
Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
0
1
read-write
0
Brake Function triggered by CSS detection Disabled
#0
1
Brake Function triggered by CSS detection Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
PWM_INTEN0
PWM_INTEN0
PWM Interrupt Enable Register 0
0xE0
read-write
n
0x0
0x0
CMPDIEN0
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type, period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN2
PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type, period point means center point.
10
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN4
PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type, period point means center point.
12
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN2
PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
2
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN4
PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
4
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
PWM_INTEN1
PWM_INTEN1
PWM Interrupt Enable Register 1
0xE4
read-write
n
0x0
0x0
BRKEIEN0_1
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
Edge-detect Brake interrupt for channel0/1 Disabled
#0
1
Edge-detect Brake interrupt for channel0/1 Enabled
#1
BRKEIEN2_3
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
Edge-detect Brake interrupt for channel2/3 Disabled
#0
1
Edge-detect Brake interrupt for channel2/3 Enabled
#1
BRKEIEN4_5
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
Edge-detect Brake interrupt for channel4/5 Disabled
#0
1
Edge-detect Brake interrupt for channel4/5 Enabled
#1
BRKLIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
Level-detect Brake interrupt for channel0/1 Disabled
#0
1
Level-detect Brake interrupt for channel0/1 Enabled
#1
BRKLIEN2_3
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
Level-detect Brake interrupt for channel2/3 Disabled
#0
1
Level-detect Brake interrupt for channel2/3 Enabled
#1
BRKLIEN4_5
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
Level-detect Brake interrupt for channel4/5 Disabled
#0
1
Level-detect Brake interrupt for channel4/5 Enabled
#1
PWM_INTSTS0
PWM_INTSTS0
PWM Interrupt Flag Register 0
0xE8
read-write
n
0x0
0x0
CMPDIF0
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
24
1
read-write
CMPDIF1
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
25
1
read-write
CMPDIF2
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
26
1
read-write
CMPDIF3
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
27
1
read-write
CMPDIF4
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
28
1
read-write
CMPDIF5
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
29
1
read-write
CMPUIFn
PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
16
6
read-write
PIF0
PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1.
8
1
read-write
PIF2
PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1.
10
1
read-write
PIF4
PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1.
12
1
read-write
ZIF0
PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
ZIF2
PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
2
1
read-write
ZIF4
PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
4
1
read-write
PWM_INTSTS1
PWM_INTSTS1
PWM Interrupt Flag Register 1
0xEC
read-write
n
0x0
0x0
BRKEIF0
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF1
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF2
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF3
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
3
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF4
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF5
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKESTS0
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
16
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS1
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
17
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS2
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
18
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS3
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
19
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS4
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
20
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS5
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
21
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLIF0
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF1
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF2
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF3
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
11
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF4
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF5
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLSTS0
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
24
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS1
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
25
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS2
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
26
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS3
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
27
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS4
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
28
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS5
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
29
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
PWM_MSK
PWM_MSK
PWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
0
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT1
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
1
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT2
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
2
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT3
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
3
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT4
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
4
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT5
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
5
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
PWM_MSKEN
PWM_MSKEN
PWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
0
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN1
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
1
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN2
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
2
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN3
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
3
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN4
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
4
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN5
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
5
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
PWM_PBUF0
PWM_PBUF0
PWM PERIOD0 Buffer
0x304
read-only
n
0x0
0x0
PBUF
PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
PWM_PBUF2
PWM_PBUF2
PWM PERIOD2 Buffer
0x30C
read-write
n
0x0
0x0
PWM_PBUF4
PWM_PBUF4
PWM PERIOD4 Buffer
0x314
read-write
n
0x0
0x0
PWM_PDMACAP0_1
PWM_PDMACAP0_1
PWM Capture Channel 01 PDMA Register
0x240
read-only
n
0x0
0x0
CAPBUF
PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
0
16
read-only
PWM_PDMACAP2_3
PWM_PDMACAP2_3
PWM Capture Channel 23 PDMA Register
0x244
read-write
n
0x0
0x0
PWM_PDMACAP4_5
PWM_PDMACAP4_5
PWM Capture Channel 45 PDMA Register
0x248
read-write
n
0x0
0x0
PWM_PDMACTL
PWM_PDMACTL
PWM PDMA Control Register
0x23C
read-write
n
0x0
0x0
CAPMOD0_1
Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
1
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT0/1
#01
2
PWM_FCAPDAT0/1
#10
3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
#11
CAPMOD2_3
Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
9
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT2/3
#01
2
PWM_FCAPDAT2/3
#10
3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
#11
CAPMOD4_5
Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
17
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT4/5
#01
2
PWM_FCAPDAT4/5
#10
3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
#11
CAPORD0_1
Capture Channel 0/1 Rising/Falling Order
3
1
read-write
0
PWM_FCAPDAT0/1 is the first captured data to memory
#0
1
PWM_RCAPDAT0/1 is the first captured data to memory
#1
CAPORD2_3
Capture Channel 2/3 Rising/Falling Order
11
1
read-write
0
PWM_FCAPDAT2/3 is the first captured data to memory
#0
1
PWM_RCAPDAT2/3 is the first captured data to memory
#1
CAPORD4_5
Capture Channel 4/5 Rising/Falling Order
19
1
read-write
0
PWM_FCAPDAT4/5 is the first captured data to memory
#0
1
PWM_RCAPDAT4/5 is the first captured data to memory
#1
CHEN0_1
Channel 0/1 PDMA Enable Bit
0
1
read-write
0
Channel 0/1 PDMA function Disabled
#0
1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
#1
CHEN2_3
Channel 2/3 PDMA Enable Bit
8
1
read-write
0
Channel 2/3 PDMA function Disabled
#0
1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
#1
CHEN4_5
Channel 4/5 PDMA Enable Bit
16
1
read-write
0
Channel 4/5 PDMA function Disabled
#0
1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
#1
CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer
4
1
read-write
0
Channel0
#0
1
Channel1
#1
CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer
12
1
read-write
0
Channel2
#0
1
Channel3
#1
CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer
20
1
read-write
0
Channel4
#0
1
Channel5
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x30
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x38
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x40
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
PWM Pin Output Enable Bits
0
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN1
PWM Pin Output Enable Bits
1
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN2
PWM Pin Output Enable Bits
2
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN3
PWM Pin Output Enable Bits
3
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN4
PWM Pin Output Enable Bits
4
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN5
PWM Pin Output Enable Bits
5
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
PWM_POLCTL
PWM_POLCTL
PWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
0
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV1
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
1
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV2
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
2
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV3
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
3
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV4
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
4
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV5
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
5
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
PWM_SSCTL
PWM_SSCTL
PWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN2
PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
2
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN4
PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
4
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSRC
PWM Synchronous Start Source Select Bits
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Reserved.
#10
3
Reserved.
#11
PWM_SSTRG
PWM_SSTRG
PWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
0
1
write-only
PWM_STATUS
PWM_STATUS
PWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
16
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG1
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
17
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG2
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
18
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG3
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
19
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG4
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
20
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG5
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
21
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
0
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX2
Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
2
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX4
Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
4
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value
#1
PWM_SWBRK
PWM_SWBRK
PWM Software Brake Control Register
0xDC
write-only
n
0x0
0x0
BRKETRG0
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
write-only
BRKETRG2
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
write-only
BRKETRG4
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
write-only
BRKLTRG0
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
write-only
BRKLTRG2
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
write-only
BRKLTRG4
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
write-only
PWM_WGCTL0
PWM_WGCTL0
PWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL1
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL2
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL3
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL4
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL5
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
ZPCTL0
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL1
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL2
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL3
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL4
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL5
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
PWM_WGCTL1
PWM_WGCTL1
PWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
16
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL1
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
18
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL2
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
20
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL3
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
22
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL4
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
24
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL5
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
26
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPUCTL0
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
0
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL1
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
2
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL2
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
4
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL3
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
6
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL4
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
8
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL5
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
10
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
PWM1
PWM Register Map
PWM
0x0
0x0
0x8
registers
n
0x10
0x18
registers
n
0x110
0x8
registers
n
0x120
0x4
registers
n
0x200
0x4C
registers
n
0x250
0x8
registers
n
0x30
0x4
registers
n
0x304
0x4
registers
n
0x30C
0x4
registers
n
0x314
0x4
registers
n
0x31C
0x18
registers
n
0x38
0x4
registers
n
0x40
0x4
registers
n
0x50
0x18
registers
n
0x70
0xC
registers
n
0x90
0x4
registers
n
0x98
0x4
registers
n
0xA0
0x4
registers
n
0xB0
0x40
registers
n
0xF8
0x8
registers
n
PWM_ADCTS0
PWM_ADCTS0
PWM Trigger ADC Source Select Register 0
0xF8
read-write
n
0x0
0x0
TRGEN0
PWM_CH0 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH0 Trigger ADC function Disabled
#0
1
PWM_CH0 Trigger ADC function Enabled
#1
TRGEN1
PWM_CH1 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH1 Trigger ADC function Disabled
#0
1
PWM_CH1 Trigger ADC function Enabled
#1
TRGEN2
PWM_CH2 Trigger ADC Enable Bit
23
1
read-write
0
PWM_CH2 Trigger ADC function Disabled
#0
1
PWM_CH2 Trigger ADC function Enabled
#1
TRGEN3
PWM_CH3 Trigger ADC Enable Bit
31
1
read-write
0
PWM_CH3 Trigger ADC function Disabled
#0
1
PWM_CH3 Trigger ADC function Enabled
#1
TRGSEL0
PWM_CH0 Trigger ADC Source Select
0
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL1
PWM_CH1 Trigger ADC Source Select
8
4
read-write
0
PWM_CH0 zero point
#0000
1
PWM_CH0 period point
#0001
2
PWM_CH0 zero or period point
#0010
3
PWM_CH0 up-count CMPDAT point
#0011
4
PWM_CH0 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH1 up-count CMPDAT point
#1000
9
PWM_CH1 down-count CMPDAT point
#1001
TRGSEL2
PWM_CH2 Trigger ADC Source Select
16
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
TRGSEL3
PWM_CH3 Trigger ADC Source Select
24
4
read-write
0
PWM_CH2 zero point
#0000
1
PWM_CH2 period point
#0001
2
PWM_CH2 zero or period point
#0010
3
PWM_CH2 up-count CMPDAT point
#0011
4
PWM_CH2 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH3 up-count CMPDAT point
#1000
9
PWM_CH3 down-count CMPDAT point
#1001
PWM_ADCTS1
PWM_ADCTS1
PWM Trigger ADC Source Select Register 1
0xFC
read-write
n
0x0
0x0
TRGEN4
PWM_CH4 Trigger ADC Enable Bit
7
1
read-write
0
PWM_CH4 Trigger ADC function Disabled
#0
1
PWM_CH4 Trigger ADC function Enabled
#1
TRGEN5
PWM_CH5 Trigger ADC Enable Bit
15
1
read-write
0
PWM_CH5 Trigger ADC function Disabled
#0
1
PWM_CH5 Trigger ADC function Enabled
#1
TRGSEL4
PWM_CH4 Trigger ADC Source Select
0
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
TRGSEL5
PWM_CH5 Trigger ADC Source Select
8
4
read-write
0
PWM_CH4 zero point
#0000
1
PWM_CH4 period point
#0001
2
PWM_CH4 zero or period point
#0010
3
PWM_CH4 up-count CMPDAT point
#0011
4
PWM_CH4 down-count CMPDAT point
#0100
5
Reserved.
#0101
6
Reserved.
#0110
7
Reserved.
#0111
8
PWM_CH5 up-count CMPDAT point
#1000
9
PWM_CH5 down-count CMPDAT point
#1001
PWM_BNF
PWM_BNF
PWM Brake Noise Filter Register
0xC0
read-write
n
0x0
0x0
BK0SRC
Brake 0 Pin Source Select\nFor PWM0 setting:
16
1
read-write
0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#0
1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
#1
BK1SRC
Brake 1 Pin Source Select\nFor PWM0 setting:
24
1
read-write
0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#0
1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
#1
BRK0NFCNT
Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
4
3
read-write
BRK0NFEN
PWM Brake 0 Noise Filter Enable Bit
0
1
read-write
0
Noise filter of PWM Brake 0 Disabled
#0
1
Noise filter of PWM Brake 0 Enabled
#1
BRK0NFSEL
Brake 0 Edge Detector Filter Clock Selection
1
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK0PINV
Brake 0 Pin Inverse
7
1
read-write
0
The state of pin PWMx_BRAKE0 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector
#1
BRK1FCNT
Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
12
3
read-write
BRK1FEN
PWM Brake 1 Noise Filter Enable Bit
8
1
read-write
0
Noise filter of PWM Brake 1 Disabled
#0
1
Noise filter of PWM Brake 1 Enabled
#1
BRK1NFSEL
Brake 1 Edge Detector Filter Clock Selection
9
3
read-write
0
Filter clock = HCLK
#000
1
Filter clock = HCLK/2
#001
2
Filter clock = HCLK/4
#010
3
Filter clock = HCLK/8
#011
4
Filter clock = HCLK/16
#100
5
Filter clock = HCLK/32
#101
6
Filter clock = HCLK/64
#110
7
Filter clock = HCLK/128
#111
BRK1PINV
Brake 1 Pin Inverse
15
1
read-write
0
The state of pin PWMx_BRAKE1 is passed to the negative edge detector
#0
1
The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector
#1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM Brake Edge Detect Control Register 0/1
0xC8
read-write
n
0x0
0x0
BRKAEVEN
PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
16
2
read-write
0
PWM even channel level-detect brake function not affect channel output
#00
1
PWM even channel output tri-state when level-detect brake happened
#01
2
PWM even channel output low level when level-detect brake happened
#10
3
PWM even channel output high level when level-detect brake happened
#11
BRKAODD
PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
18
2
read-write
0
PWM odd channel level-detect brake function not affect channel output
#00
1
PWM odd channel output tri-state when level-detect brake happened
#01
2
PWM odd channel output low level when level-detect brake happened
#10
3
PWM odd channel output high level when level-detect brake happened
#11
BRKP0EEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
BKP0 pin as edge-detect brake source Disabled
#0
1
BKP0 pin as edge-detect brake source Enabled
#1
BRKP0LEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE0 pin as level-detect brake source Enabled
#1
BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
BKP1 pin as edge-detect brake source Disabled
#0
1
BKP1 pin as edge-detect brake source Enabled
#1
BRKP1LEN
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#0
1
PWMx_BRAKE1 pin as level-detect brake source Enabled
#1
CPO0EBEN
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
ACMP0_O as edge-detect brake source Disabled
#0
1
ACMP0_O as edge-detect brake source Enabled
#1
CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
ACMP0_O as level-detect brake source Disabled
#0
1
ACMP0_O as level-detect brake source Enabled
#1
CPO1EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
ACMP1_O as edge-detect brake source Disabled
#0
1
ACMP1_O as edge-detect brake source Enabled
#1
CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
ACMP1_O as level-detect brake source Disabled
#0
1
ACMP1_O as level-detect brake source Enabled
#1
SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
7
1
read-write
0
System Fail condition as edge-detect brake source Disabled
#0
1
System Fail condition as edge-detect brake source Enabled
#1
SYSLBEN
Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
15
1
read-write
0
System Fail condition as level-detect brake source Disabled
#0
1
System Fail condition as level-detect brake source Enabled
#1
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM Brake Edge Detect Control Register 2/3
0xCC
read-write
n
0x0
0x0
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM Brake Edge Detect Control Register 4/5
0xD0
read-write
n
0x0
0x0
PWM_CAPCTL
PWM_CAPCTL
PWM Capture Control Register
0x204
read-write
n
0x0
0x0
CAPEN0
Capture Function Enable Bits
0
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN1
Capture Function Enable Bits
1
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN2
Capture Function Enable Bits
2
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN3
Capture Function Enable Bits
3
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN4
Capture Function Enable Bits
4
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPEN5
Capture Function Enable Bits
5
1
read-write
0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#0
1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
#1
CAPINV0
Capture Inverter Enable Bits
8
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV1
Capture Inverter Enable Bits
9
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV2
Capture Inverter Enable Bits
10
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV3
Capture Inverter Enable Bits
11
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV4
Capture Inverter Enable Bits
12
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
CAPINV5
Capture Inverter Enable Bits
13
1
read-write
0
Capture source inverter Disabled
#0
1
Capture source inverter Enabled. Reverse the input signal from GPIO
#1
FCRLDEN0
Falling Capture Reload Enable Bits
24
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN1
Falling Capture Reload Enable Bits
25
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN2
Falling Capture Reload Enable Bits
26
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN3
Falling Capture Reload Enable Bits
27
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN4
Falling Capture Reload Enable Bits
28
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
FCRLDEN5
Falling Capture Reload Enable Bits
29
1
read-write
0
Falling capture reload counter Disabled
#0
1
Falling capture reload counter Enabled
#1
RCRLDEN0
Rising Capture Reload Enable Bits
16
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN1
Rising Capture Reload Enable Bits
17
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN2
Rising Capture Reload Enable Bits
18
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN3
Rising Capture Reload Enable Bits
19
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN4
Rising Capture Reload Enable Bits
20
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
RCRLDEN5
Rising Capture Reload Enable Bits
21
1
read-write
0
Rising capture reload counter Disabled
#0
1
Rising capture reload counter Enabled
#1
PWM_CAPIEN
PWM_CAPIEN
PWM Capture Interrupt Enable Register
0x250
read-write
n
0x0
0x0
CAPFIEN0
PWM Capture Falling Latch Interrupt Enable Bits
8
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN1
PWM Capture Falling Latch Interrupt Enable Bits
9
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN2
PWM Capture Falling Latch Interrupt Enable Bits
10
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN3
PWM Capture Falling Latch Interrupt Enable Bits
11
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN4
PWM Capture Falling Latch Interrupt Enable Bits
12
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPFIEN5
PWM Capture Falling Latch Interrupt Enable Bits
13
1
read-write
0
Capture falling edge latch interrupt Disabled
#0
1
Capture falling edge latch interrupt Enabled
#1
CAPRIEN0
PWM Capture Rising Latch Interrupt Enable Bits
0
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN1
PWM Capture Rising Latch Interrupt Enable Bits
1
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN2
PWM Capture Rising Latch Interrupt Enable Bits
2
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN3
PWM Capture Rising Latch Interrupt Enable Bits
3
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN4
PWM Capture Rising Latch Interrupt Enable Bits
4
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
CAPRIEN5
PWM Capture Rising Latch Interrupt Enable Bits
5
1
read-write
0
Capture rising edge latch interrupt Disabled
#0
1
Capture rising edge latch interrupt Enabled
#1
PWM_CAPIF
PWM_CAPIF
PWM Capture Interrupt Flag Register
0x254
read-write
n
0x0
0x0
CFLIF0
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
8
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF1
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
9
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF2
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
10
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF3
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
11
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF4
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
12
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CFLIF5
PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
13
1
read-write
0
No capture falling latch condition happened
#0
1
Capture falling latch condition happened, this flag will be set to high
#1
CRLIF0
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
0
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF1
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
1
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF2
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
2
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF3
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
3
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF4
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
4
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
CRLIF5
PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
5
1
read-write
0
No capture rising latch condition happened
#0
1
Capture rising latch condition happened, this flag will be set to high
#1
PWM_CAPINEN
PWM_CAPINEN
PWM Capture Input Enable Register
0x200
read-write
n
0x0
0x0
CAPINEN0
Capture Input Enable Bits
0
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN1
Capture Input Enable Bits
1
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN2
Capture Input Enable Bits
2
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN3
Capture Input Enable Bits
3
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN4
Capture Input Enable Bits
4
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
CAPINEN5
Capture Input Enable Bits
5
1
read-write
0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#0
1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
#1
PWM_CAPSTS
PWM_CAPSTS
PWM Capture Status Register
0x208
read-only
n
0x0
0x0
CFLIFOV0
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
8
1
read-only
CFLIFOV1
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
9
1
read-only
CFLIFOV2
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
10
1
read-only
CFLIFOV3
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
11
1
read-only
CFLIFOV4
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
12
1
read-only
CFLIFOV5
Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
13
1
read-only
CRLIFOV0
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
0
1
read-only
CRLIFOV1
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
1
1
read-only
CRLIFOV2
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
2
1
read-only
CRLIFOV3
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
3
1
read-only
CRLIFOV4
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
4
1
read-only
CRLIFOV5
Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
5
1
read-only
PWM_CLKPSC0_1
PWM_CLKPSC0_1
PWM Clock Prescale Register 0/1
0x14
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
0
12
read-write
PWM_CLKPSC2_3
PWM_CLKPSC2_3
PWM Clock Prescale Register 2/3
0x18
read-write
n
0x0
0x0
PWM_CLKPSC4_5
PWM_CLKPSC4_5
PWM Clock Prescale Register 4/5
0x1C
read-write
n
0x0
0x0
PWM_CLKSRC
PWM_CLKSRC
PWM Clock Source Register
0x10
read-write
n
0x0
0x0
ECLKSRC0
PWM_CH01 External Clock Source Select
0
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC2
PWM_CH23 External Clock Source Select
8
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
ECLKSRC4
PWM_CH45 External Clock Source Select
16
3
read-write
0
PWMx_CLK, x denotes 0 or 1
#000
1
TIMER0 overflow
#001
2
TIMER1 overflow
#010
3
TIMER2 overflow
#011
4
TIMER3 overflow
#100
PWM_CMPBUF0
PWM_CMPBUF0
PWM CMPDAT0 Buffer
0x31C
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
0
16
read-only
PWM_CMPBUF1
PWM_CMPBUF1
PWM CMPDAT1 Buffer
0x320
read-write
n
0x0
0x0
PWM_CMPBUF2
PWM_CMPBUF2
PWM CMPDAT2 Buffer
0x324
read-write
n
0x0
0x0
PWM_CMPBUF3
PWM_CMPBUF3
PWM CMPDAT3 Buffer
0x328
read-write
n
0x0
0x0
PWM_CMPBUF4
PWM_CMPBUF4
PWM CMPDAT4 Buffer
0x32C
read-write
n
0x0
0x0
PWM_CMPBUF5
PWM_CMPBUF5
PWM CMPDAT5 Buffer
0x330
read-write
n
0x0
0x0
PWM_CMPDAT0
PWM_CMPDAT0
PWM Comparator Register 0
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
0
16
read-write
PWM_CMPDAT1
PWM_CMPDAT1
PWM Comparator Register 1
0x54
read-write
n
0x0
0x0
PWM_CMPDAT2
PWM_CMPDAT2
PWM Comparator Register 2
0x58
read-write
n
0x0
0x0
PWM_CMPDAT3
PWM_CMPDAT3
PWM Comparator Register 3
0x5C
read-write
n
0x0
0x0
PWM_CMPDAT4
PWM_CMPDAT4
PWM Comparator Register 4
0x60
read-write
n
0x0
0x0
PWM_CMPDAT5
PWM_CMPDAT5
PWM Comparator Register 5
0x64
read-write
n
0x0
0x0
PWM_CNT0
PWM_CNT0
PWM Counter Register 0
0x90
read-only
n
0x0
0x0
CNT
PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
0
16
read-only
DIRF
PWM Direction Indicator Flag (Read Only)
16
1
read-only
0
Counter is counting down
#0
1
Counter is counting up
#1
PWM_CNT2
PWM_CNT2
PWM Counter Register 2
0x98
read-write
n
0x0
0x0
PWM_CNT4
PWM_CNT4
PWM Counter Register 4
0xA0
read-write
n
0x0
0x0
PWM_CNTCLR
PWM_CNTCLR
PWM Clear Counter Register
0x24
read-write
n
0x0
0x0
CNTCLR0
Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR2
Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.
2
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
CNTCLR4
Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.
4
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0000H
#1
PWM_CNTEN
PWM_CNTEN
PWM Counter Enable Register
0x20
read-write
n
0x0
0x0
CNTEN0
PWM Counter Enable Bit 0
0
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN2
PWM Counter Enable Bit 2
2
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
CNTEN4
PWM Counter Enable Bit 4
4
1
read-write
0
PWM Counter and clock prescaler Stop Running
#0
1
PWM Counter and clock prescaler Start Running
#1
PWM_CTL0
PWM_CTL0
PWM Control Register 0
0x0
read-write
n
0x0
0x0
CTRLDn
Center Load Enable Bits\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
0
1
read-write
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
30
1
read-write
0
ICE debug mode counter halt Disable
#0
1
ICE debug mode counter halt Enable
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
IMMLDENn
Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
16
1
read-write
0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#0
1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
#1
PWM_CTL1
PWM_CTL1
PWM Control Register 1
0x4
read-write
n
0x0
0x0
CNTTYPE0
PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0
0
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE2
PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2
4
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
CNTTYPE4
PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4
8
2
read-write
0
Up counter type (supported in capture mode)
#00
1
Down count type (supported in capture mode)
#01
2
Up-down counter type
#10
3
Reserved.
#11
OUTMODEn
PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
24
3
read-write
0
PWM independent mode
0
1
PWM complementary mode
1
PWM_DTCTL0_1
PWM_DTCTL0_1
PWM Dead-time Control Register 0/1
0x70
read-write
n
0x0
0x0
DTCKSEL
Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
24
1
read-write
0
Dead-time clock source from PWM_CLK
#0
1
Dead-time clock source from prescaler output
#1
DTCNT
Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
12
read-write
DTEN
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair
#0
1
Dead-time insertion Enabled on the pin pair
#1
PWM_DTCTL2_3
PWM_DTCTL2_3
PWM Dead-time Control Register 2/3
0x74
read-write
n
0x0
0x0
PWM_DTCTL4_5
PWM_DTCTL4_5
PWM Dead-time Control Register 4/5
0x78
read-write
n
0x0
0x0
PWM_FAILBRK
PWM_FAILBRK
PWM System Fail Brake Control Register
0xC4
read-write
n
0x0
0x0
BODBRKEN
Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
1
1
read-write
0
Brake Function triggered by BOD Disabled
#0
1
Brake Function triggered by BOD Enabled
#1
CORBRKEN
Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
3
1
read-write
0
Brake Function triggered by Core lockup detection Disabled
#0
1
Brake Function triggered by Core lockup detection Enabled
#1
CSSBRKEN
Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
0
1
read-write
0
Brake Function triggered by CSS detection Disabled
#0
1
Brake Function triggered by CSS detection Enabled
#1
PWM_FCAPDAT0
PWM_FCAPDAT0
PWM Falling Capture Data Register 0
0x210
read-only
n
0x0
0x0
FCAPDAT
PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_FCAPDAT1
PWM_FCAPDAT1
PWM Falling Capture Data Register 1
0x218
read-write
n
0x0
0x0
PWM_FCAPDAT2
PWM_FCAPDAT2
PWM Falling Capture Data Register 2
0x220
read-write
n
0x0
0x0
PWM_FCAPDAT3
PWM_FCAPDAT3
PWM Falling Capture Data Register 3
0x228
read-write
n
0x0
0x0
PWM_FCAPDAT4
PWM_FCAPDAT4
PWM Falling Capture Data Register 4
0x230
read-write
n
0x0
0x0
PWM_FCAPDAT5
PWM_FCAPDAT5
PWM Falling Capture Data Register 5
0x238
read-write
n
0x0
0x0
PWM_INTEN0
PWM_INTEN0
PWM Interrupt Enable Register 0
0xE0
read-write
n
0x0
0x0
CMPDIEN0
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
24
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN1
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
25
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN2
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
26
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN3
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
27
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN4
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
28
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPDIEN5
PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
29
1
read-write
0
Compare down count interrupt Disabled
#0
1
Compare down count interrupt Enabled
#1
CMPUIEN0
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
16
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN1
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
17
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN2
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
18
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN3
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
19
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN4
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
20
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
CMPUIEN5
PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
21
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN0
PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type, period point means center point.
8
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN2
PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type, period point means center point.
10
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
PIEN4
PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type, period point means center point.
12
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
ZIEN0
PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
0
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN2
PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
2
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
ZIEN4
PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
4
1
read-write
0
Zero point interrupt Disabled
#0
1
Zero point interrupt Enabled
#1
PWM_INTEN1
PWM_INTEN1
PWM Interrupt Enable Register 1
0xE4
read-write
n
0x0
0x0
BRKEIEN0_1
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
Edge-detect Brake interrupt for channel0/1 Disabled
#0
1
Edge-detect Brake interrupt for channel0/1 Enabled
#1
BRKEIEN2_3
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
Edge-detect Brake interrupt for channel2/3 Disabled
#0
1
Edge-detect Brake interrupt for channel2/3 Enabled
#1
BRKEIEN4_5
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
Edge-detect Brake interrupt for channel4/5 Disabled
#0
1
Edge-detect Brake interrupt for channel4/5 Enabled
#1
BRKLIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
Level-detect Brake interrupt for channel0/1 Disabled
#0
1
Level-detect Brake interrupt for channel0/1 Enabled
#1
BRKLIEN2_3
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
Level-detect Brake interrupt for channel2/3 Disabled
#0
1
Level-detect Brake interrupt for channel2/3 Enabled
#1
BRKLIEN4_5
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
Level-detect Brake interrupt for channel4/5 Disabled
#0
1
Level-detect Brake interrupt for channel4/5 Enabled
#1
PWM_INTSTS0
PWM_INTSTS0
PWM Interrupt Flag Register 0
0xE8
read-write
n
0x0
0x0
CMPDIF0
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
24
1
read-write
CMPDIF1
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
25
1
read-write
CMPDIF2
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
26
1
read-write
CMPDIF3
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
27
1
read-write
CMPDIF4
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
28
1
read-write
CMPDIF5
PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
29
1
read-write
CMPUIFn
PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
16
6
read-write
PIF0
PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1.
8
1
read-write
PIF2
PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1.
10
1
read-write
PIF4
PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1.
12
1
read-write
ZIF0
PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
0
1
read-write
ZIF2
PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
2
1
read-write
ZIF4
PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
4
1
read-write
PWM_INTSTS1
PWM_INTSTS1
PWM Interrupt Flag Register 1
0xEC
read-write
n
0x0
0x0
BRKEIF0
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF1
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF2
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF3
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
3
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF4
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
4
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKEIF5
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
5
1
read-write
0
PWM channel n edge-detect brake event do not happened
#0
1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKESTS0
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
16
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS1
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
17
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS2
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
18
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS3
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
19
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS4
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
20
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKESTS5
PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
21
1
read-only
0
PWM channel n edge-detect brake state is released
#0
1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLIF0
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF1
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF2
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF3
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
11
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF4
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
12
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLIF5
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
13
1
read-write
0
PWM channel n level-detect brake event do not happened
#0
1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
#1
BRKLSTS0
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
24
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS1
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
25
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS2
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
26
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS3
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
27
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS4
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
28
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
BRKLSTS5
PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
29
1
read-only
0
PWM channel n level-detect brake state is released
#0
1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
#1
PWM_MSK
PWM_MSK
PWM Mask Data Register
0xBC
read-write
n
0x0
0x0
MSKDAT0
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
0
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT1
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
1
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT2
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
2
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT3
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
3
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT4
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
4
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
MSKDAT5
PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
5
1
read-write
0
Output logic low to PWM channel n
#0
1
Output logic high to PWM channel n
#1
PWM_MSKEN
PWM_MSKEN
PWM Mask Enable Register
0xB8
read-write
n
0x0
0x0
MSKEN0
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
0
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN1
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
1
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN2
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
2
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN3
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
3
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN4
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
4
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
MSKEN5
PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
5
1
read-write
0
PWM output signal is non-masked
#0
1
PWM output signal is masked and output MSKDATn data
#1
PWM_PBUF0
PWM_PBUF0
PWM PERIOD0 Buffer
0x304
read-only
n
0x0
0x0
PBUF
PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
0
16
read-only
PWM_PBUF2
PWM_PBUF2
PWM PERIOD2 Buffer
0x30C
read-write
n
0x0
0x0
PWM_PBUF4
PWM_PBUF4
PWM PERIOD4 Buffer
0x314
read-write
n
0x0
0x0
PWM_PDMACAP0_1
PWM_PDMACAP0_1
PWM Capture Channel 01 PDMA Register
0x240
read-only
n
0x0
0x0
CAPBUF
PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
0
16
read-only
PWM_PDMACAP2_3
PWM_PDMACAP2_3
PWM Capture Channel 23 PDMA Register
0x244
read-write
n
0x0
0x0
PWM_PDMACAP4_5
PWM_PDMACAP4_5
PWM Capture Channel 45 PDMA Register
0x248
read-write
n
0x0
0x0
PWM_PDMACTL
PWM_PDMACTL
PWM PDMA Control Register
0x23C
read-write
n
0x0
0x0
CAPMOD0_1
Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
1
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT0/1
#01
2
PWM_FCAPDAT0/1
#10
3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
#11
CAPMOD2_3
Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
9
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT2/3
#01
2
PWM_FCAPDAT2/3
#10
3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
#11
CAPMOD4_5
Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
17
2
read-write
0
Reserved.
#00
1
PWM_RCAPDAT4/5
#01
2
PWM_FCAPDAT4/5
#10
3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
#11
CAPORD0_1
Capture Channel 0/1 Rising/Falling Order
3
1
read-write
0
PWM_FCAPDAT0/1 is the first captured data to memory
#0
1
PWM_RCAPDAT0/1 is the first captured data to memory
#1
CAPORD2_3
Capture Channel 2/3 Rising/Falling Order
11
1
read-write
0
PWM_FCAPDAT2/3 is the first captured data to memory
#0
1
PWM_RCAPDAT2/3 is the first captured data to memory
#1
CAPORD4_5
Capture Channel 4/5 Rising/Falling Order
19
1
read-write
0
PWM_FCAPDAT4/5 is the first captured data to memory
#0
1
PWM_RCAPDAT4/5 is the first captured data to memory
#1
CHEN0_1
Channel 0/1 PDMA Enable Bit
0
1
read-write
0
Channel 0/1 PDMA function Disabled
#0
1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
#1
CHEN2_3
Channel 2/3 PDMA Enable Bit
8
1
read-write
0
Channel 2/3 PDMA function Disabled
#0
1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
#1
CHEN4_5
Channel 4/5 PDMA Enable Bit
16
1
read-write
0
Channel 4/5 PDMA function Disabled
#0
1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
#1
CHSEL0_1
Select Channel 0/1 to Do PDMA Transfer
4
1
read-write
0
Channel0
#0
1
Channel1
#1
CHSEL2_3
Select Channel 2/3 to Do PDMA Transfer
12
1
read-write
0
Channel2
#0
1
Channel3
#1
CHSEL4_5
Select Channel 4/5 to Do PDMA Transfer
20
1
read-write
0
Channel4
#0
1
Channel5
#1
PWM_PERIOD0
PWM_PERIOD0
PWM Period Register 0
0x30
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
0
16
read-write
PWM_PERIOD2
PWM_PERIOD2
PWM Period Register 2
0x38
read-write
n
0x0
0x0
PWM_PERIOD4
PWM_PERIOD4
PWM Period Register 4
0x40
read-write
n
0x0
0x0
PWM_POEN
PWM_POEN
PWM Output Enable Register
0xD8
read-write
n
0x0
0x0
POEN0
PWM Pin Output Enable Bits
0
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN1
PWM Pin Output Enable Bits
1
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN2
PWM Pin Output Enable Bits
2
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN3
PWM Pin Output Enable Bits
3
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN4
PWM Pin Output Enable Bits
4
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
POEN5
PWM Pin Output Enable Bits
5
1
read-write
0
PWM pin at tri-state
#0
1
PWM pin in output mode
#1
PWM_POLCTL
PWM_POLCTL
PWM Pin Polar Inverse Register
0xD4
read-write
n
0x0
0x0
PINV0
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
0
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV1
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
1
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV2
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
2
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV3
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
3
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV4
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
4
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PINV5
PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
5
1
read-write
0
PWM output polar inverse Disabled
#0
1
PWM output polar inverse Enabled
#1
PWM_RCAPDAT0
PWM_RCAPDAT0
PWM Rising Capture Data Register 0
0x20C
read-only
n
0x0
0x0
RCAPDAT
PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
0
16
read-only
PWM_RCAPDAT1
PWM_RCAPDAT1
PWM Rising Capture Data Register 1
0x214
read-write
n
0x0
0x0
PWM_RCAPDAT2
PWM_RCAPDAT2
PWM Rising Capture Data Register 2
0x21C
read-write
n
0x0
0x0
PWM_RCAPDAT3
PWM_RCAPDAT3
PWM Rising Capture Data Register 3
0x224
read-write
n
0x0
0x0
PWM_RCAPDAT4
PWM_RCAPDAT4
PWM Rising Capture Data Register 4
0x22C
read-write
n
0x0
0x0
PWM_RCAPDAT5
PWM_RCAPDAT5
PWM Rising Capture Data Register 5
0x234
read-write
n
0x0
0x0
PWM_SSCTL
PWM_SSCTL
PWM Synchronous Start Control Register
0x110
read-write
n
0x0
0x0
SSEN0
PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
0
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN2
PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
2
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSEN4
PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
4
1
read-write
0
PWM synchronous start function Disabled
#0
1
PWM synchronous start function Enabled
#1
SSRC
PWM Synchronous Start Source Select Bits
8
2
read-write
0
Synchronous start source come from PWM0
#00
1
Synchronous start source come from PWM1
#01
2
Reserved.
#10
3
Reserved.
#11
PWM_SSTRG
PWM_SSTRG
PWM Synchronous Start Trigger Register
0x114
write-only
n
0x0
0x0
CNTSEN
PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
0
1
write-only
PWM_STATUS
PWM_STATUS
PWM Status Register
0x120
read-write
n
0x0
0x0
ADCTRG0
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
16
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG1
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
17
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG2
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
18
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG3
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
19
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG4
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
20
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
ADCTRG5
ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
21
1
read-write
0
Indicates no ADC start of conversion trigger event has occurred
#0
1
An ADC start of conversion trigger event has occurred
#1
CNTMAX0
Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
0
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX2
Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
2
1
read-write
0
indicates the time-base counter never reached its maximum value 0xFFFF
#0
1
indicates the time-base counter reached its maximum value
#1
CNTMAX4
Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
4
1
read-write
0
The time-base counter never reached its maximum value 0xFFFF
#0
1
The time-base counter reached its maximum value
#1
PWM_SWBRK
PWM_SWBRK
PWM Software Brake Control Register
0xDC
write-only
n
0x0
0x0
BRKETRG0
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
0
1
write-only
BRKETRG2
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
1
1
write-only
BRKETRG4
PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
2
1
write-only
BRKLTRG0
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
8
1
write-only
BRKLTRG2
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
9
1
write-only
BRKLTRG4
PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
10
1
write-only
PWM_WGCTL0
PWM_WGCTL0
PWM Generation Register 0
0xB0
read-write
n
0x0
0x0
PRDPCTL0
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
16
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL1
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
18
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL2
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
20
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL3
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
22
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL4
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
24
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
PRDPCTL5
PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
26
2
read-write
0
Do nothing
#00
1
PWM period (center) point output Low
#01
2
PWM period (center) point output High
#10
3
PWM period (center) point output Toggle
#11
ZPCTL0
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
0
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL1
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
2
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL2
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
4
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL3
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
6
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL4
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
8
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
ZPCTL5
PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
10
2
read-write
0
Do nothing
#00
1
PWM zero point output Low
#01
2
PWM zero point output High
#10
3
PWM zero point output Toggle
#11
PWM_WGCTL1
PWM_WGCTL1
PWM Generation Register 1
0xB4
read-write
n
0x0
0x0
CMPDCTL0
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
16
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL1
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
18
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL2
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
20
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL3
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
22
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL4
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
24
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPDCTL5
PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
26
2
read-write
0
Do nothing
#00
1
PWM compare down point output Low
#01
2
PWM compare down point output High
#10
3
PWM compare down point output Toggle
#11
CMPUCTL0
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
0
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL1
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
2
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL2
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
4
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL3
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
6
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL4
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
8
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
CMPUCTL5
PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
10
2
read-write
0
Do nothing
#00
1
PWM compare up point output Low
#01
2
PWM compare up point output High
#10
3
PWM compare up point output Toggle
#11
QSPIx
QSPI Register Map
QSPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
CLKDIV
QSPIx_CLKDIV
QSPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote: The time interval must be larger than or equal 8 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
0
9
read-write
CTL
QSPIx_CTL
QSPI Control Register
0x0
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
QSPI bus clock is idle low
#0
1
QSPI bus clock is idle high
#1
DATDIR
Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
QSPI data is input direction
#0
1
QSPI data is output direction
#1
DUALIOEN
Dual I/O Mode Enable Bit
21
1
read-write
0
Dual I/O mode Disabled
#0
1
Dual I/O mode Enabled
#1
DWIDTH
Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
8
5
read-write
HALFDPX
QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer. The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
QSPI operates in full-duplex transfer
#0
1
QSPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the QSPIx TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPIx_RX)
#1
QUADIOEN
Quad I/O Mode Enable Bit
22
1
read-write
0
Quad I/O mode Disabled
#0
1
Quad I/O mode Enabled
#1
REORDER
Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of QSPI bus clock
#0
1
Received data input signal is latched on the falling edge of QSPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
QSPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of QSPICLK clock cycle\nExample:
4
4
read-write
TWOBIT
2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
16
1
read-write
0
2-bit Transfer mode Disabled
#0
1
2-bit Transfer mode Enabled
#1
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of QSPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of QSPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
QSPI unit transfer interrupt Disabled
#0
1
QSPI unit transfer interrupt Enabled
#1
FIFOCTL
QSPIx_FIFOCTL
QSPI FIFO Control Register
0x10
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The QSPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The QSPI data out is keep 1 if there is TX underflow event in Slave mode
#1
PDMACTL
QSPIx_PDMACTL
QSPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
QSPIx_RX
QSPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from QSPI data input pin. If the RXEMPTY (QSPIx_STATUS[8) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SSCTL
QSPIx_SSCTL
QSPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLV3WIRE
Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPIx_CLK, QSPIx_MISO and QSPIx_MOSI pins.
4
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVTOCNT
Slave Mode Time-out Period\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
16
16
read-write
SLVTOIEN
Slave Mode Time-out Interrupt Enable Bit
5
1
read-write
0
Slave mode time-out interrupt Disabled
#0
1
Slave mode time-out interrupt Enabled
#1
SLVTORST
Slave Mode Time-out Reset Control
6
1
read-write
0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#0
1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,
0
1
read-write
0
set the QSPIx_SS line to inactive state.\nKeep the QSPIx_SS line at inactive state
#0
1
set the QSPIx_SS line to active state.\nQSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS).
2
1
read-write
0
The slave selection signal QSPIx_SS is active low
#0
1
The slave selection signal QSPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
QSPIx_STATUS
QSPI Status Register
0x14
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
QSPI controller is in idle state
#0
1
QSPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPIx_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
5
1
read-write
0
Slave time-out is not active
#0
1
Slave time-out is active
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock. In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
15
1
read-only
0
QSPI controller Disabled
#0
1
QSPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
QSPI controller has finished one unit transfer
#1
TX
QSPIx_TX
QSPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]).\nIf DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the QSPI controller will perform a 32-bit transfer.\nNote: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
RTC
RTC Register Map
RTC
0x0
0x0
0x4
registers
n
0x100
0x8
registers
n
0x110
0x4
registers
n
0x120
0x4
registers
n
0x130
0x8
registers
n
0x8
0x4C
registers
n
CAL
RTC_CAL
RTC Calendar Loading Register
0x10
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit (0~9)
0
4
read-write
MON
1-Month Calendar Digit (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit (0~9)
16
4
read-write
CALM
RTC_CALM
RTC Calendar Alarm Register
0x20
read-write
n
0x0
0x0
DAY
1-Day Calendar Digit of Alarm Setting (0~9)
0
4
read-write
MON
1-Month Calendar Digit of Alarm Setting (0~9)
8
4
read-write
TENDAY
10-Day Calendar Digit of Alarm Setting (0~3)
4
2
read-write
TENMON
10-Month Calendar Digit of Alarm Setting (0~1)
12
1
read-write
TENYEAR
10-Year Calendar Digit of Alarm Setting (0~9)
20
4
read-write
YEAR
1-Year Calendar Digit of Alarm Setting (0~9)
16
4
read-write
CAMSK
RTC_CAMSK
RTC Calendar Alarm Mask Register
0x38
read-write
n
0x0
0x0
MDAY
Mask 1-Day Calendar Digit of Alarm Setting (0~9)
0
1
read-write
MMON
Mask 1-Month Calendar Digit of Alarm Setting (0~9)
2
1
read-write
MTENDAY
Mask 10-Day Calendar Digit of Alarm Setting (0~3)
1
1
read-write
MTENMON
Mask 10-Month Calendar Digit of Alarm Setting (0~1)
3
1
read-write
MTENYEAR
Mask 10-Year Calendar Digit of Alarm Setting (0~9)
5
1
read-write
MYEAR
Mask 1-Year Calendar Digit of Alarm Setting (0~9)
4
1
read-write
CLKFMT
RTC_CLKFMT
RTC Time Scale Selection Register
0x14
read-write
n
0x0
0x0
_24HEN
24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
0
1
read-write
0
12-hour time scale with AM and PM indication selected
#0
1
24-hour time scale selected
#1
DSTCTL
RTC_DSTCTL
RTC Daylight Saving Time Control Register
0x110
read-write
n
0x0
0x0
ADDHR
Add 1 Hour
0
1
read-write
0
No effect
#0
1
Indicates RTC hour digit has been added one hour for summer time change
#1
DSBAK
Daylight Saving Back
2
1
read-write
0
Daylight Saving Change is not performed
#0
1
Daylight Saving Change is performed
#1
SUBHR
Subtract 1 Hour
1
1
read-write
0
No effect
#0
1
Indicates RTC hour digit has been subtracted one hour for winter time change
#1
FREQADJ
RTC_FREQADJ
RTC Frequency Compensation Register
0x8
read-write
n
0x0
0x0
FRACTION
Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number.
0
6
read-write
INTEGER
Integer Part
8
5
read-write
0
Integer part of detected value is 32752
#00000
1
Integer part of detected value is 32753
#00001
2
Integer part of detected value is 32754
#00010
3
Integer part of detected value is 32755
#00011
4
Integer part of detected value is 32756
#00100
5
Integer part of detected value is 32757
#00101
6
Integer part of detected value is 32758
#00110
7
Integer part of detected value is 32759
#00111
8
Integer part of detected value is 32760
#01000
9
Integer part of detected value is 32761
#01001
10
Integer part of detected value is 32762
#01010
11
Integer part of detected value is 32763
#01011
12
Integer part of detected value is 32764
#01100
13
Integer part of detected value is 32765
#01101
14
Integer part of detected value is 32766
#01110
15
Integer part of detected value is 32767
#01111
16
Integer part of detected value is 32768
#10000
17
Integer part of detected value is 32769
#10001
18
Integer part of detected value is 32770
#10010
19
Integer part of detected value is 32771
#10011
20
Integer part of detected value is 32772
#10100
21
Integer part of detected value is 32773
#10101
22
Integer part of detected value is 32774
#10110
23
Integer part of detected value is 32775
#10111
24
Integer part of detected value is 32776
#11000
25
Integer part of detected value is 32777
#11001
26
Integer part of detected value is 32778
#11010
27
Integer part of detected value is 32779
#11011
28
Integer part of detected value is 32780
#11100
29
Integer part of detected value is 32781
#11101
30
Integer part of detected value is 32782
#11110
31
Integer part of detected value is 32783
#11111
GPIOCTL0
RTC_GPIOCTL0
RTC GPIO Control 0 Register
0x104
read-write
n
0x0
0x0
CTLSEL0
IO Pin State Backup Selection (Only for VBAT Domain)\nWhen low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function. User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.\nNote1: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
3
1
read-write
0
PF.4 pin I/O function is controlled by GPIO module
#0
1
PF.4 pin I/O function is controlled by VBAT power domain
#1
CTLSEL1
IO Pin State Backup Selection (Only for VBAT Domain)\nWhen low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function. User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.\nNote1: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
11
1
read-write
0
PF.5 pin I/O function is controlled by GPIO module
#0
1
PF.5 pin I/O function is controlled by VBAT power domain
#1
CTLSEL2
IO Pin State Backup Selection (Only for VBAT Domain)When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function. User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.\nNote1: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
19
1
read-write
0
PF.6 pin I/O function is controlled by GPIO module
#0
1
PF.6 pin I/O function is controlled by VBAT power domain
#1
DOUT0
IO Output Data (Only for VBAT Domain)
2
1
read-write
0
PF.4 output low
#0
1
PF.4 output high
#1
DOUT1
IO Output Data (Only for VBAT Domain)
10
1
read-write
0
PF.5 output low
#0
1
PF.5 output high
#1
DOUT2
IO Output Data (Only for VBAT Domain)
18
1
read-write
0
PF.6 output low
#0
1
PF.6 output high
#1
OPMODE0
IO Operation Mode (Only for VBAT Domain)
0
2
read-write
0
PF.4 is input only mode
#00
1
PF.4 is output push pull mode
#01
2
PF.4 is open drain mode
#10
3
PF.4 is quasi-bidirectional mode
#11
OPMODE1
IO Operation Mode (Only for VBAT Domain)
8
2
read-write
0
PF.5 is input only mode
#00
1
PF.5 is output push pull mode
#01
2
PF.5 is open drain mode
#10
3
PF.5 is quasi-bidirectional mode
#11
OPMODE2
IO Operation Mode (Only for VBAT Domain)
16
2
read-write
0
PF.6 is input only mode
#00
1
PF.6 is output push pull mode
#01
2
PF.6 is open drain mode
#10
3
PF.6 is quasi-bidirectional mode
#11
PUSEL0
IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE0 set as input tri-state and open-drain mode.
4
2
read-write
0
PF.4 pull-up and pull-down disabled
#00
1
PF.4 pull-up enabled
#01
2
PF.4 pull-down enabled
#10
3
PF.4 pull-up and pull-down disabled
#11
PUSEL1
IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.5 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE1 set as input tri-state and open-drain mode.
12
2
read-write
0
PF.5 pull-up and pull-down disabled
#00
1
PF.5 pull-up enabled
#01
2
PF.5 pull-down enabled
#10
3
PF.5 pull-up and pull-down disabled
#11
PUSEL2
IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.6 I/O pull-up or pull-down.\nThe independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode and PF6 as tamper pin.
20
2
read-write
0
PF.6 pull-up and pull-down disabled
#00
1
PF.6 pull-up enabled
#01
2
PF.6 pull-down enabled
#10
3
PF.6 pull-up and pull-down disabled.Note: Basically, the pull-up control and pull-down control has following behavior limitation
#11
SMTEN0
Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
6
1
read-write
0
PF.4 input schmitt trigger function Disabled
#0
1
PF.4 input schmitt trigger function Enabled
#1
SMTEN1
Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
14
1
read-write
0
PF.5 input schmitt trigger function Disabled
#0
1
PF.5 input schmitt trigger function Enabled
#1
SMTEN2
Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
22
1
read-write
0
PF.6 input schmitt trigger function Disabled
#0
1
PF.6 input schmitt trigger function Enabled
#1
INIT
RTC_INIT
RTC Initiation Register
0x0
read-write
n
0x0
0x0
INIT
RTC Initiation (Write Only)\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
1
31
write-only
INIT_ACTIVE
RTC Active Status (Read Only)
0
1
read-only
0
RTC is at reset state
#0
1
RTC is at normal active state
#1
INTEN
RTC_INTEN
RTC Interrupt Enable Register
0x28
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
0
1
read-write
0
RTC Alarm interrupt Disabled
#0
1
RTC Alarm interrupt Enabled
#1
TAMP0IEN
Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
8
1
read-write
0
Tamper 0 interrupt Disabled
#0
1
Tamper 0 interrupt Enabled
#1
TICKIEN
Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
1
1
read-write
0
RTC Time Tick interrupt Disabled
#0
1
RTC Time Tick interrupt Enabled
#1
INTSTS
RTC_INTSTS
RTC Interrupt Status Register
0x2C
read-write
n
0x0
0x0
ALMIF
RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit.
0
1
read-write
0
Alarm condition is not matched
#0
1
Alarm condition is matched
#1
TAMP0IF
Tamper 0 Interrupt Flag\nNote: Write 1 to clear this bit.
8
1
read-write
0
No Tamper 0 interrupt flag is generated
#0
1
Tamper 0 interrupt flag is generated
#1
TICKIF
RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit.
1
1
read-write
0
Tick condition did not occur
#0
1
Tick condition occurred
#1
LEAPYEAR
RTC_LEAPYEAR
RTC Leap Year Indicator Register
0x24
read-only
n
0x0
0x0
LEAPYEAR
Leap Year Indication (Read Only)
0
1
read-only
0
This year is not a leap year
#0
1
This year is leap year
#1
LXTCTL
RTC_LXTCTL
RTC 32.768 KHz Oscillator Control Register
0x100
read-write
n
0x0
0x0
C32KS
Clock 32K Source Selection:
7
1
read-write
0
Internal 32K clock is from 32K crystal
#0
1
Internal 32K clock is from LIRC32K
#1
GAIN
Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.\nNote: Please refer to the M251 Datasheet for detailed information about LXT electrical characteristics.
1
3
read-write
0
L0 mode
#000
1
L1 mode
#001
2
L2 mode
#010
3
L3 mode
#011
4
L4 mode. (Only for VBAT domain)
#100
5
L5 mode. (Only for VBAT domain)
#101
6
L6 mode. (Only for VBAT domain)
#110
7
L7 mode. (Only for VBAT domain)
#111
RTCLVDPD
RTC Low Voltage Detector Power Down (Only for VBAT Domain)
13
1
read-write
0
RTC Low Voltage Detector active.
#0
1
RTC Low Voltage Detector enter power down
#1
RTCPORPD
RTC Power on Reset Power Down (Only for VBAT Domain)\nNote: This bit only can be set to 1.
14
1
read-write
0
RTC POR active 1sec after first power up
#0
1
RTC POR enter power down
#1
SPR0
RTC_SPR0
RTC Spare Register 0
0x40
read-write
n
0x0
0x0
SPARE
Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.
0
32
read-write
SPR1
RTC_SPR1
RTC Spare Register 1
0x44
read-write
n
0x0
0x0
SPR2
RTC_SPR2
RTC Spare Register 2
0x48
read-write
n
0x0
0x0
SPR3
RTC_SPR3
RTC Spare Register 3
0x4C
read-write
n
0x0
0x0
SPR4
RTC_SPR4
RTC Spare Register 4
0x50
read-write
n
0x0
0x0
SPRCTL
RTC_SPRCTL
RTC Spare Functional Control Register
0x3C
read-write
n
0x0
0x0
SPRCLRM
Spare Register Clear Mask Bit
0
1
read-write
0
Spare register will be clear after TAMPER occurs
#0
1
Spare register will not be clear after TAMPER occurs
#1
SPRCSTS
SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[8] is not equal to 0.
5
1
read-write
0
Spare register content is not cleared
#0
1
Spare register content is cleared
#1
SPRRWEN
Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed.
2
1
read-write
0
Spare register Disabled
#0
1
Spare register Enabled
#1
TALM
RTC_TALM
RTC Time Alarm Register
0x1C
read-write
n
0x0
0x0
HR
1-Hour Time Digit of Alarm Setting (0~9)
16
4
read-write
MIN
1-Min Time Digit of Alarm Setting (0~9)
8
4
read-write
SEC
1-Sec Time Digit of Alarm Setting (0~9)
0
4
read-write
TENHR
10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit of Alarm Setting (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit of Alarm Setting (0~5)
4
3
read-write
TAMPCAL
RTC_TAMPCAL
RTC Tamper Calendar Register
0x134
read-only
n
0x0
0x0
DAY
1-Day Calendar Digit of TAMPER Calendar (0~9)
0
4
read-only
MON
1-Month Calendar Digit of TAMPER Calendar (0~9)
8
4
read-only
TENDAY
10-Day Calendar Digit of TAMPER Calendar (0~3)
4
2
read-only
TENMON
10-Month Calendar Digit of TAMPER Calendar (0~1)
12
1
read-only
TENYEAR
10-Year Calendar Digit of TAMPER Calendar (0~9)
20
4
read-only
YEAR
1-Year Calendar Digit of TAMPER Calendar (0~9)
16
4
read-only
TAMPCTL
RTC_TAMPCTL
RTC Tamper Pin Control Register
0x120
read-write
n
0x0
0x0
TAMP0DBEN
Tamper 0 De-bounce Enable Bit\nNote: In normal condition (25 ), it can deglitch 1~2 ns noise.
10
1
read-write
0
Tamper 0 de-bounce Disabled
#0
1
Tamper 0 de-bounce Enabled., tamper detection pin will sync 1 RTC clock
#1
TAMP0EN
Tamper0 Detect Enable Bit\nNote: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
8
1
read-write
0
Tamper 0 detect Disabled
#0
1
Tamper 0 detect Enabled
#1
TAMP0LV
Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
9
1
read-write
0
Detect Rising detection, will trigger tamper status when RTC_TAMPCTL[11] = 1
#0
1
Detect Falling detection, will trigger tamper status when RTC_TAMPCTL[11] = 1
#1
TAMP0TYPE
Tamper 0 DetectType
11
1
read-write
0
Tamper as edge detector
#0
1
Tamper as Level detector
#1
TAMPTIME
RTC_TAMPTIME
RTC Tamper Time Register
0x130
read-only
n
0x0
0x0
HR
1-Hour Time Digit of TAMPER Time (0~9)
16
4
read-only
MIN
1-Min Time Digit of TAMPER Time (0~9)
8
4
read-only
SEC
1-Sec Time Digit of TAMPER Time (0~9)
0
4
read-only
TENHR
10-Hour Time Digit of TAMPER Time (0~2) \nNote: 24-hour time scale only.
20
2
read-only
TENMIN
10-Min Time Digit of TAMPER Time (0~5)
12
3
read-only
TENSEC
10-Sec Time Digit of TAMPER Time (0~5)
4
3
read-only
TAMSK
RTC_TAMSK
RTC Time Alarm Mask Register
0x34
read-write
n
0x0
0x0
MHR
Mask 1-Hour Time Digit of Alarm Setting (0~9)
4
1
read-write
MMIN
Mask 1-Min Time Digit of Alarm Setting (0~9)
2
1
read-write
MSEC
Mask 1-Sec Time Digit of Alarm Setting (0~9)
0
1
read-write
MTENHR
Mask 10-Hour Time Digit of Alarm Setting (0~2)
5
1
read-write
MTENMIN
Mask 10-Min Time Digit of Alarm Setting (0~5)
3
1
read-write
MTENSEC
Mask 10-Sec Time Digit of Alarm Setting (0~5)
1
1
read-write
TICK
RTC_TICK
RTC Time Tick Register
0x30
read-write
n
0x0
0x0
TICK
Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
0
3
read-write
0
Time tick is 1 second
#000
1
Time tick is 1/2 second
#001
2
Time tick is 1/4 second
#010
3
Time tick is 1/8 second
#011
4
Time tick is 1/16 second
#100
5
Time tick is 1/32 second
#101
6
Time tick is 1/64 second
#110
7
Time tick is 1/128 second
#111
TIME
RTC_TIME
RTC Time Loading Register
0xC
read-write
n
0x0
0x0
HR
1-Hour Time Digit (0~9)
16
4
read-write
MIN
1-Min Time Digit (0~9)
8
4
read-write
SEC
1-Sec Time Digit (0~9)
0
4
read-write
TENHR
10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
20
2
read-write
TENMIN
10-Min Time Digit (0~5)
12
3
read-write
TENSEC
10-Sec Time Digit (0~5)
4
3
read-write
WEEKDAY
RTC_WEEKDAY
RTC Day of the Week Register
0x18
read-write
n
0x0
0x0
WEEKDAY
Day of the Week Register
0
3
read-write
0
Sunday
#000
1
Monday
#001
2
Tuesday
#010
3
Wednesday
#011
4
Thursday
#100
5
Friday
#101
6
Saturday
#110
7
Reserved.
#111
SC0
SC Register Map
SC
0x0
0x0
0x38
registers
n
0x4C
0x4
registers
n
SC_ACTCTL
SC_ACTCTL
SC Activation Control Register
0x4C
read-write
n
0x0
0x0
T1EXT
T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3.
0
5
read-write
SC_ALTCTL
SC_ALTCTL
SC Alternate Control Register
0x8
read-write
n
0x0
0x0
ACTEN
Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the activation sequence, RX is disabled automatically and can not receive data. After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
3
1
read-write
0
No effect
#0
1
Activation sequence generator Enabled
#1
ACTSTS0
Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
13
1
read-only
0
Timer0 is not active
#0
1
Timer0 is active
#1
ACTSTS1
Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
14
1
read-only
0
Timer1 is not active
#0
1
Timer1 is active
#1
ACTSTS2
Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
15
1
read-only
0
Timer2 is not active
#0
1
Timer2 is active
#1
ADACEN
Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
11
1
read-write
0
Auto deactivation Disabled
#0
1
Auto deactivation Enabled
#1
CNTEN0
Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
5
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN1
Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
6
1
read-write
0
Stops counting
#0
1
Start counting
#1
CNTEN2
Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
7
1
read-write
0
Stops counting
#0
1
Start counting
#1
DACTEN
Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
2
1
read-write
0
No effect
#0
1
Deactivation sequence generator Enabled
#1
INITSEL
Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Error! Reference source not found..\nWarm-reset: refer to Warm-Reset Sequence in Error! Reference source not found..\nDeactivation: refer to Deactivation Sequence in Error! Reference source not found..\nNote: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
8
2
read-write
RXBGTEN
Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function.
12
1
read-write
0
Receiver block guard time function Disabled
#0
1
Receiver block guard time function Enabled
#1
RXRST
Rx Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
1
1
read-write
0
No effect
#0
1
Reset the Rx internal state machine and pointers
#1
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
31
1
read-only
0
Synchronizing is completion, user can write new data to SCn_ALTCTL register
#0
1
Last value is synchronizing
#1
TXRST
TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
0
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
WARSTEN
Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the warm reset sequence, RX is disabled automatically and can not receive data. After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
4
1
read-write
0
No effect
#0
1
Warm reset sequence generator Enabled
#1
SC_CTL
SC_CTL
SC Control Register
0x4
read-write
n
0x0
0x0
AUTOCEN
Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nNote1: If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\nNote2: If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
3
1
read-write
0
Auto-convention Disabled
#0
1
Auto-convention Enabled
#1
BGT
Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
8
5
read-write
CDDBSEL
Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved.
24
2
read-write
0
De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks
#00
CDLV
Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled.
26
1
read-write
0
When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected
#0
1
When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected
#1
CONSEL
Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
4
2
read-write
0
Direct convention
#00
1
Reserved.
#01
2
Reserved.
#10
3
Inverse convention
#11
NSB
Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
15
1
read-write
0
The stop bit length is 2 ETU
#0
1
The stop bit length is 1 ETU
#1
RXOFF
RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
1
1
read-write
0
The receiver Enabled
#0
1
The receiver Disabled
#1
RXRTY
RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value.
16
3
read-write
RXRTYEN
RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit.
19
1
read-write
0
RX error retry function Disabled
#0
1
RX error retry function Enabled
#1
RXTRGLV
Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
6
2
read-write
0
Rx Buffer Trigger Level with 01 bytes
#00
1
Rx Buffer Trigger Level with 02 bytes
#01
2
Rx Buffer Trigger Level with 03 bytes
#10
3
Reserved.
#11
SCEN
SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, \nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
0
1
read-write
0
SC will force all transition to IDLE state
#0
1
SC controller is enabled and all function can work correctly
#1
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
30
1
read-only
0
Synchronizing is completion, user can write new data to RXRTY and TXRTY
#0
1
Last value is synchronizing
#1
TMRSEL
Timer Channel Selection \nOther configurations are reserved
13
2
read-write
0
All internal timer function Disabled
#00
3
Internal 24 bit timer and two 8 bit timers Enabled. User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]
#11
TXOFF
TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function.
2
1
read-write
0
The transceiver Enabled
#0
1
The transceiver Disabled
#1
TXRTY
TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value.
20
3
read-write
TXRTYEN
TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.
23
1
read-write
0
TX error retry function Disabled
#0
1
TX error retry function Enabled
#1
SC_DAT
SC_DAT
SC Receive/Transmit Holding Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
0
8
read-write
SC_EGT
SC_EGT
SC Extra Guard Time Register
0xC
read-write
n
0x0
0x0
EGT
Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base.
0
8
read-write
SC_ETUCTL
SC_ETUCTL
SC Element Time Unit Control Register
0x14
read-write
n
0x0
0x0
ETURDIV
ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field, but this field must be greater than 0x04.
0
12
read-write
SC_INTEN
SC_INTEN
SC Interrupt Enable Control Register
0x18
read-write
n
0x0
0x0
ACERRIEN
Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt.
10
1
read-write
0
Auto-convention error interrupt Disabled
#0
1
Auto-convention error interrupt Enabled
#1
BGTIEN
Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time.
6
1
read-write
0
Block guard time interrupt Disabled
#0
1
Block guard time interrupt Enabled
#1
CDIEN
Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13]).
7
1
read-write
0
Card detect interrupt Disabled
#0
1
Card detect interrupt Enabled
#1
INITIEN
Initial End Interrupt Enable Bit
8
1
read-write
0
Initial end interrupt Disabled
#0
1
Initial end interrupt Enabled
#1
RDAIEN
Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
0
1
read-write
0
Receive data reach trigger level interrupt Disabled
#0
1
Receive data reach trigger level interrupt Enabled
#1
RXTOIEN
Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt.
9
1
read-write
0
Receiver buffer time-out interrupt Disabled
#0
1
Receiver buffer time-out interrupt Enabled
#1
TBEIEN
Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt.
1
1
read-write
0
Transmit buffer empty interrupt Disabled
#0
1
Transmit buffer empty interrupt Enabled
#1
TERRIEN
Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
2
1
read-write
0
Transfer error interrupt Disabled
#0
1
Transfer error interrupt Enabled
#1
TMR0IEN
Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function.
3
1
read-write
0
Timer0 interrupt Disabled
#0
1
Timer0 interrupt Enabled
#1
TMR1IEN
Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function.
4
1
read-write
0
Timer1 interrupt Disabled
#0
1
Timer1 interrupt Enabled
#1
TMR2IEN
Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function.
5
1
read-write
0
Timer2 interrupt Disabled
#0
1
Timer2 interrupt Enabled
#1
SC_INTSTS
SC_INTSTS
SC Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ACERRIF
Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it.
10
1
read-write
0
Received TS at ATR state is 0x3B or 0x3F
#0
1
Received TS at ATR state is neither 0x3B nor 0x3F
#1
BGTIF
Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by writing 1 to it.
6
1
read-write
0
Block guard time interrupt did not occur
#0
1
Block guard time interrupt occurred
#1
CDIF
Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
7
1
read-only
0
Card detect event did not occur
#0
1
Card detect event occurred
#1
INITIF
Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
8
1
read-write
0
Initial sequence is not complete
#0
1
Initial sequence is completed
#1
RDAIF
Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
0
1
read-only
0
Number of receive buffer is less than RXTRGLV setting
#0
1
Number of receive buffer data equals the RXTRGLV setting
#1
RXTOIF
Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
9
1
read-only
0
Receive buffer time-out interrupt did not occur
#0
1
Receive buffer time-out interrupt occurred
#1
TBEIF
Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
1
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TERRIF
Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it.
2
1
read-write
0
Transfer error interrupt did not occur
#0
1
Transfer error interrupt occurred
#1
TMR0IF
Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
3
1
read-write
0
Timer0 interrupt did not occur
#0
1
Timer0 interrupt occurred
#1
TMR1IF
Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
4
1
read-write
0
Timer1 interrupt did not occur
#0
1
Timer1 interrupt occurred
#1
TMR2IF
Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
5
1
read-write
0
Timer2 interrupt did not occur
#0
1
Timer2 interrupt occurred
#1
SC_PINCTL
SC_PINCTL
SC Pin Control State Register
0x24
read-write
n
0x0
0x0
CLKKEEP
SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
6
1
read-write
0
SC clock generation Disabled
#0
1
SC clock always keeps free running
#1
DATASTS
SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA.
16
1
read-only
0
The SCn_DATA pin status is low
#0
1
The SCn_DATA pin status is high
#1
PWREN
SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. \nRead this field to get SCn_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
0
1
read-write
0
SCn_PWR signal status is low
#0
1
SCn_PWR signal status is high
#1
PWRINV
SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, \nNote: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
11
1
read-write
0
SCn_PWR pin is 0
00
1
SCn_PWR pin is 1
01
10
SCn_PWR pin is 1
10
11
SCn_PWR pin is 0
11
PWRSTS
SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR.
17
1
read-only
0
SCn_PWR pin to low
#0
1
SCn_PWR pin to high
#1
RSTEN
SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
1
1
read-write
0
Drive SCn_RST pin to low.\nSCn_RST signal status is low
#0
1
Drive SCn_RST pin to high.\nSCn_RST signal status is high
#1
RSTSTS
SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST.
18
1
read-only
0
SCn_RST pin is low
#0
1
SCn_RST pin is high
#1
SCDATA
SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes.
9
1
read-write
0
Drive SCn_DATA pin to low.\nSCn_DATA signal status is low
#0
1
Drive SCn_DATA pin to high.\nSCn_DATA signal status is high
#1
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
30
1
read-only
0
Synchronizing is completion, user can write new data to SCn_PINCTL register
#0
1
Last value is synchronizing
#1
SC_RXTOUT
SC_RXTOUT
SC Receive Buffer Time-out Counter Register
0x10
read-write
n
0x0
0x0
RFTM
SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function.
0
9
read-write
SC_STATUS
SC_STATUS
SC Transfer Status Register
0x20
read-write
n
0x0
0x0
BEF
Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits').\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
6
1
read-write
0
Receiver break error flag did not occur
#0
1
Receiver break error flag occurred
#1
CDPINSTS
Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD.
13
1
read-only
0
The SCn_CD pin state at low
#0
1
The SCn_CD pin state at high
#1
CINSERT
Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set.
12
1
read-write
0
No effect
#0
1
Card insert
#1
CREMOVE
Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set.
11
1
read-write
0
No effect
#0
1
Card removed
#1
FEF
Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
5
1
read-write
0
Receiver frame error flag did not occur
#0
1
Receiver frame error flag occurred
#1
PEF
Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
4
1
read-write
0
Receiver parity error flag did not occur
#0
1
Receiver parity error flag occurred
#1
RXACT
Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status.
23
1
read-only
0
This bit is cleared automatically when Rx transfer is finished
#0
1
This bit is set by hardware when Rx transfer is in active
#1
RXEMPTY
Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not.
1
1
read-only
0
Rx buffer is not empty
#0
1
Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU
#1
RXFULL
Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not.
2
1
read-only
0
Rx buffer count is less than 4
#0
1
Rx buffer count equals to 4
#1
RXOV
Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it.
0
1
read-write
0
Rx buffer is not overflow
#0
1
Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes)
#1
RXOVERR
Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
22
1
read-write
0
Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1
#0
1
Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1
#1
RXPOINT
Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
16
3
read-only
RXRERR
Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
21
1
read-write
0
No Rx retry transfer
#0
1
Rx has any error and retries transfer
#1
TXACT
Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status.
31
1
read-only
0
This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed
#0
1
Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted
#1
TXEMPTY
Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
9
1
read-only
0
Tx buffer is not empty
#0
1
Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register
#1
TXFULL
Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not.
10
1
read-only
0
Tx buffer count is less than 4
#0
1
Tx buffer count equals to 4
#1
TXOV
Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it.
8
1
read-write
0
Tx buffer is not overflow
#0
1
Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0])
#1
TXOVERR
Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it.
30
1
read-write
0
Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1
#0
1
Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1
#1
TXPOINT
Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT, TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
24
3
read-only
TXRERR
Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU.
29
1
read-write
0
No Tx retry transfer
#0
1
Tx has any error and retries transfer
#1
SC_TMRCTL0
SC_TMRCTL0
SC Internal Timer0 Control Register
0x28
read-write
n
0x0
0x0
CNT
Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base.
0
24
read-write
OPMODE
Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Error! Reference source not found. for programming Timer0.
24
4
read-write
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
31
1
read-only
0
Synchronizing is completion, user can write new data to SCn_TMRCTL0 register
#0
1
Last value is synchronizing
#1
SC_TMRCTL1
SC_TMRCTL1
SC Internal Timer1 Control Register
0x2C
read-write
n
0x0
0x0
CNT
Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base.
0
8
read-write
OPMODE
Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Error! Reference source not found. for programming Timer1.
24
4
read-write
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
31
1
read-only
0
Synchronizing is completion, user can write new data to SCn_TMRCTL1 register
#0
1
Last value is synchronizing
#1
SC_TMRCTL2
SC_TMRCTL2
SC Internal Timer2 Control Register
0x30
read-write
n
0x0
0x0
CNT
Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base.
0
8
read-write
OPMODE
Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Error! Reference source not found. for programming Timer2.
24
4
read-write
SYNC
SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
31
1
read-only
0
Synchronizing is completion, user can write new data to SCn_TMRCTL2 register
#0
1
Last value is synchronizing
#1
SC_UARTCTL
SC_UARTCTL
SC UART Mode Control Register
0x34
read-write
n
0x0
0x0
OPE
Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0.
7
1
read-write
0
Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode
#0
1
Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode
#1
PBOFF
Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode, this field must be 0 (default setting is with parity bit).
6
1
read-write
0
Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data
#0
1
Parity bit is not generated (transmitting data) or checked (receiving data) during transfer
#1
UARTEN
UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
0
1
read-write
0
Smart Card mode
#0
1
UART mode
#1
WLS
Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode, this WLS must be 00.
4
2
read-write
0
Word length is 8 bits
#00
1
Word length is 7 bits
#01
2
Word length is 6 bits
#10
3
Word length is 5 bits
#11
SCS
SYST_SCR Register Map
SYST_SCR
0x0
0x10
0xC
registers
n
0xD04
0x14
registers
n
0xD1C
0xC
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness (Read Only)
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
PRIS
Priority Secure Exceptions Bit
14
1
read-write
0
Priority ranges of Secure and Non-secure exceptions are identical.1 = Non-secure exceptions are de-prioritized
#0
SYSRESETREQ
System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence.
2
1
read-write
SYSRESETREQS
System Reset Request Secure Only Bit
3
1
read-write
0
SYSRESETREQ functionality is available to both security states.1 = SYSRESETREQ functionality is available to secure state only
#0
VECTCLRACTIVE
Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.\nNote: This bit reads as zero.
1
1
read-write
VECTORKEY
Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
16
16
read-write
CCR
CCR
Configuration and Control Register
0xD14
read-write
n
0x0
0x0
ICSR
ICSR
Interrupt Control and State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDCLR
NMI Bit-pending Bit\nNote: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
30
1
read-write
0
No effect
#0
1
Clear pending status
#1
NMIPENDSET
NMI Set-pending Bit\nWrite Operation:\nNote: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
31
1
read-write
0
No effect.\nNMI exception is not pending
#0
1
Changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time.
25
1
read-write
0
No effect
#0
1
Removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite Operation:
26
1
read-write
0
No effect.\nSysTick exception is not pending
#0
1
Changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time.
27
1
read-write
0
No effect
#0
1
Removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception is not pending
#0
1
Changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Number of the Current Active Exception (Read Only)
0
8
read-only
0
Thread mode
0
VECTPENDING
Number of the Highest Pended Exception (Read Only)
12
8
read-only
0
no pending exceptions
0
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
#1
SHCSR
SHCSR
System Handler Control and State Register
0xD24
read-write
n
0x0
0x0
HARDFAULTPENDED
HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state of\nthe HardFault exception corresponding to the selected Security state.\nThis bit is banked between Security states.\nThe possible values of this bit are:
21
1
read-write
0
HardFault exception not pending for the selected Security state
#0
1
HardFault exception pending for the selected Security state
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority.
30
2
read-write
SYST_CTRL
SYST_CTRL
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
CLKSRC
System Tick Clock Source Selection
2
1
read-write
0
Clock source is the (optional) external reference clock
#0
1
Core clock used for SysTick
#1
COUNTFLAG
System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
System Tick Counter Enabled
0
1
read-write
0
Counter Disabled
#0
1
Counter will operate in a multi-shot manner
#1
TICKINT
System Tick Interrupt Enabled
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
#1
SYST_LOAD
SYST_LOAD
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SYST_VAL
SYST_VAL
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
0
24
read-write
VTOR
VTOR
Vector Table Offset Register
0xD08
read-write
n
0x0
0x0
TBLOFF
Table Offset Bits\nThe vector table address for the selected Security state.
9
23
read-write
SPIx
SPI Register Map
SPI
0x0
0x0
0x18
registers
n
0x20
0x4
registers
n
0x30
0x4
registers
n
0x60
0xC
registers
n
CLKDIV
SPIx_CLKDIV
SPI Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.\nNote1: Not supported in I2S mode.\nNote2: The time interval must be larger than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
0
9
read-write
CTL
SPIx_CTL
SPI Control Register
0x0
read-write
n
0x0
0x0
CLKPOL
Clock Polarity
3
1
read-write
0
SPI bus clock is idle low
#0
1
SPI bus clock is idle high
#1
DATDIR
Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
20
1
read-write
0
SPI data is input direction
#0
1
SPI data is output direction
#1
DWIDTH
Data Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\nNote: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode. Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
8
5
read-write
HALFDPX
SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
14
1
read-write
0
SPI operates in full-duplex transfer
#0
1
SPI operates in half-duplex transfer
#1
LSB
Send LSB First
13
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
19
1
read-write
0
Byte Reorder function Disabled
#0
1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
#1
RXNEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI bus clock
#0
1
Received data input signal is latched on the falling edge of SPI bus clock
#1
RXONLY
Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode. In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
15
1
read-write
0
Receive-only mode Disabled
#0
1
Receive-only mode Enabled
#1
SLAVE
Slave Mode Control
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SPIEN
SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
0
1
read-write
0
Transfer control Disabled
#0
1
Transfer control Enabled
#1
SUSPITV
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of SPICLK clock cycle\nExample:
4
4
read-write
TXNEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI bus clock
#1
UNITIEN
Unit Transfer Interrupt Enable Bit
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
FIFOCTL
SPIx_FIFOCTL
SPI FIFO Control Register
0x10
read-write
n
0x0
0x0
RXFBCLR
Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared.
8
1
read-write
0
No effect
#0
1
Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
RXOVIEN
Receive FIFO Overrun Interrupt Enable Bit
5
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RXRST
Receive Reset
0
1
read-write
0
No effect
#0
1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
RXTH
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
24
3
read-write
RXTHIEN
Receive FIFO Threshold Interrupt Enable Bit
2
1
read-write
0
RX FIFO threshold interrupt Disabled
#0
1
RX FIFO threshold interrupt Enabled
#1
RXTOIEN
Slave Receive Time-out Interrupt Enable Bit
4
1
read-write
0
Receive time-out interrupt Disabled
#0
1
Receive time-out interrupt Enabled
#1
TXFBCLR
Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared.
9
1
read-write
0
No effect
#0
1
Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1
#1
TXRST
Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
1
1
read-write
0
No effect
#0
1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not
#1
TXTH
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
28
3
read-write
TXTHIEN
Transmit FIFO Threshold Interrupt Enable Bit
3
1
read-write
0
TX FIFO threshold interrupt Disabled
#0
1
TX FIFO threshold interrupt Enabled
#1
TXUFIEN
TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1. This bit is used to enable the TX underflow interrupt.
7
1
read-write
0
Slave TX underflow interrupt Disabled
#0
1
Slave TX underflow interrupt Enabled
#1
TXUFPOL
TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.\nNote 2: This bit should be set as 0 in I2S mode.\nNote 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward. Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
6
1
read-write
0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#0
1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
#1
I2SCLK
SPIx_I2SCLK
I2S Clock Divider Control Register
0x64
read-write
n
0x0
0x0
BCLKDIV
Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The clock frequency of bit clock , fBCLK, is determined by the following expression:\n\nwhere \n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.\nIn I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .\nThe peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.\nNote: The time interval must be larger than or equal 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
8
10
read-write
MCLKDIV
Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The frequency of master clock, fMCLK, is determined by the following expressions:\nwhere\n is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. In general, the master clock rate is 256 times sampling clock rate.
0
7
read-write
I2SCTL
SPIx_I2SCTL
I2S Control Register
0x60
read-write
n
0x0
0x0
FORMAT
Data Format Selection
28
2
read-write
0
I2S data format
#00
1
MSB justified data format
#01
2
PCM mode A
#10
3
PCM mode B
#11
I2SEN
I2S Controller Enable Bit\nNote 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode.\nNote 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
0
1
read-write
0
I2S mode Disabled
#0
1
I2S mode Enabled
#1
LZCEN
Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
17
1
read-write
0
Left channel zero cross detection Disabled
#0
1
Left channel zero cross detection Enabled
#1
LZCIEN
Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
25
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
MCLKEN
Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
15
1
read-write
0
Master clock Disabled
#0
1
Master clock Enabled
#1
MONO
Monaural Data
6
1
read-write
0
Data is stereo format
#0
1
Data is monaural format
#1
MUTE
Transmit Mute Enable Bit
3
1
read-write
0
Transmit data is shifted from buffer
#0
1
Transmit channel zero
#1
ORDER
Stereo Data Order in FIFO
7
1
read-write
0
Left channel data at high byte
#0
1
Left channel data at low byte
#1
RXEN
Receive Enable Bit
2
1
read-write
0
Data receive Disabled
#0
1
Data receive Enabled
#1
RXLCH
Receive Left Channel Enable Bit
23
1
read-write
0
Receive right channel data in Mono mode
#0
1
Receive left channel data in Mono mode
#1
RZCEN
Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit operation.
16
1
read-write
0
Right channel zero cross detection Disabled
#0
1
Right channel zero cross detection Enabled
#1
RZCIEN
Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
24
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
SLAVE
Slave Mode\nI2S can operate as master or slave. For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
8
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLVERRIEN
Bit Clock Loss Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit clock loss event occurs.
31
1
read-write
0
Interrupt Disabled
#0
1
Interrupt Enabled
#1
TXEN
Transmit Enable Bit
1
1
read-write
0
Data transmit Disabled
#0
1
Data transmit Enabled
#1
WDWIDTH
Word Width
4
2
read-write
0
data size is 8-bit
#00
1
data size is 16-bit
#01
2
data size is 24-bit
#10
3
data size is 32-bit
#11
I2SSTS
SPIx_I2SSTS
I2S Status Register
0x68
read-write
n
0x0
0x0
I2SENSTS
I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
15
1
read-only
0
The SPI/I2S control logic is disabled
#0
1
The SPI/I2S control logic is enabled
#1
LZCIF
Left Channel Zero Cross Interrupt Flag
21
1
read-write
0
No zero cross event occurred on left channel
#0
1
Zero cross event occurred on left channel
#1
RIGHT
Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel.
4
1
read-only
0
Left channel
#0
1
Right channel
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
3
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
RZCIF
Right Channel Zero Cross Interrupt Flag
20
1
read-write
0
No zero cross event occurred on right channel
#0
1
Zero cross event occurred on right channel
#1
SLVERRIF
Bit Clock Loss Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it.
22
1
read-write
0
No bit clock loss event occurred
#0
1
Bit clock loss event occurred
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
3
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
19
1
read-write
PDMACTL
SPIx_PDMACTL
SPI PDMA Control Register
0xC
read-write
n
0x0
0x0
PDMARST
PDMA Reset
2
1
read-write
0
No effect
#0
1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
#1
RXPDMAEN
Receive PDMA Enable Bit
1
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
0
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
RX
SPIx_RX
SPI Data Receive Register
0x30
read-only
n
0x0
0x0
RX
Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
0
32
read-only
SSCTL
SPIx_SSCTL
SPI Slave Select Control Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)
3
1
read-write
0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0])
#0
1
Automatic slave selection function Enabled
#1
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit
8
1
read-write
0
Slave mode bit count error interrupt Disabled
#0
1
Slave mode bit count error interrupt Enabled
#1
SLVURIEN
Slave Mode TX Under Run Interrupt Enable Bit
9
1
read-write
0
Slave mode TX under run interrupt Disabled
#0
1
Slave mode TX under run interrupt Enabled
#1
SS
Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,
0
1
read-write
0
set the SPIx_SS line to inactive state.\nKeep the SPIx_SS line at inactive state
#0
1
set the SPIx_SS line to active state.\nSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2])
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit
12
1
read-write
0
Slave select active interrupt Disabled
#0
1
Slave select active interrupt Enabled
#1
SSACTPOL
Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS).
2
1
read-write
0
The slave selection signal SPIx_SS is active low
#0
1
The slave selection signal SPIx_SS is active high
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit
13
1
read-write
0
Slave select inactive interrupt Disabled
#0
1
Slave select inactive interrupt Enabled
#1
STATUS
SPIx_STATUS
SPI Status Register
0x14
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
0
1
read-only
0
SPI controller is in idle state
#0
1
SPI controller is in busy state
#1
RXCNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
24
4
read-only
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
8
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
9
1
read-only
0
Receive FIFO buffer is not full
#0
1
Receive FIFO buffer is full
#1
RXOVIF
Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
11
1
read-write
0
No FIFO is overrun
#0
1
Receive FIFO is overrun
#1
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
10
1
read-only
0
The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
#1
RXTOIF
Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
12
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
6
1
read-write
0
No Slave mode bit count error event
#0
1
Slave mode bit count error event occurred
#1
SLVURIF
Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
7
1
read-write
0
No Slave TX under run event
#0
1
Slave TX under run event occurred
#1
SPIENSTS
SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
15
1
read-only
0
SPI controller Disabled
#0
1
SPI controller Enabled
#1
SSACTIF
Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
2
1
read-write
0
Slave select active interrupt was cleared or not occurred
#0
1
Slave select active interrupt event occurred
#1
SSINAIF
Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
3
1
read-write
0
Slave select inactive interrupt was cleared or not occurred
#0
1
Slave select inactive interrupt event occurred
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
4
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXCNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
16
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TXFULL
Transmit FIFO Buffer Full Indicator (Read Only)
17
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TXRXRST
TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
23
1
read-only
0
The reset function of TXRST or RXRST is done
#0
1
Doing the reset function of TXRST or RXRST
#1
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
18
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
#1
TXUFIF
TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
19
1
read-write
0
No effect
#0
1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
#1
UNITIF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
1
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
TX
SPIx_TX
SPI Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.\nIn SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nIn I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]. If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section\nNote: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
0
32
write-only
SYS
SYS Register Map
SYS
0x0
0x0
0x14
registers
n
0x100
0x10
registers
n
0x144
0x8
registers
n
0x18
0x8
registers
n
0x188
0x4
registers
n
0x1EC
0x4
registers
n
0x1F8
0x8
registers
n
0x24
0x8
registers
n
0x30
0x30
registers
n
0x80
0x18
registers
n
0xC0
0x4
registers
n
0xD0
0x8
registers
n
0xF0
0xC
registers
n
BODCTL
SYS_BODCTL
Brown-out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BODDGSEL
Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
8
3
read-write
0
BOD output is sampled by LIRC
#000
1
4 system clock (HCLK)
#001
2
8 system clock (HCLK)
#010
3
16 system clock (HCLK)
#011
4
32 system clock (HCLK)
#100
5
64 system clock (HCLK)
#101
6
128 system clock (HCLK)
#110
7
256 system clock (HCLK)
#111
BODEN
Brown-out Detector Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BODIF
Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
#1
BODLPM
Brown-out Detector Low Power Mode (Write Protect)
Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note 2: For BOD low power mode to be active, LVREN must be set to 1
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
5
1
read-write
0
BOD operate in normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BODOUT
Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0000.
6
1
read-write
0
Brown-out Detector output status is 0
#0
1
Brown-out Detector output status is 1
#1
BODRSTEN
Brown-out Reset Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 3: Reset by power on reset.
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: Reset by power on reset.
16
3
read-write
0
Reserved.
#000
1
Brown-Out Detector threshold voltage is 1.8V
#001
2
Brown-Out Detector threshold voltage is 2.0V
#010
3
Brown-Out Detector threshold voltage is 2.4V
#011
4
Brown-Out Detector threshold voltage is 2.7V
#100
5
Brown-Out Detector threshold voltage is 3.0V
#101
6
Brown-Out Detector threshold voltage is 3.7V
#110
7
Brown-Out Detector threshold voltage is 4.4V
#111
LVRDGSEL
LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote: The MIRC enabled automatically when LVRDGSEL is not 000 and LVREN is 1.
12
3
read-write
0
Without de-glitch function
#000
1
4 MIRC clock (4 MHz), 1 us
#001
2
8 MIRC clock (4 MHz), 2 us
#010
3
16 MIRC clock (4 MHz), 4 us
#011
4
32 MIRC clock (4 MHz), 8 us
#100
5
64 MIRC clock (4 MHz), 16 us
#101
6
128 MIRC clock (4 MHz), 32 us
#110
7
256 MIRC clock (4 MHz), 64 us
#111
LVREN
Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note 1: After enabling the bit, the LVR function will be active with 3ms delay for LVR output stable (default).
Note 2: For BOD low power mode to be active, this bit must be set to 1.
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled
#1
GPA_MFOS
SYS_GPA_MFOS
GPIOA Multiple Function Output Select Register
0x80
read-write
n
0x0
0x0
MFOS0
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
0
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS1
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
1
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS10
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
10
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS11
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
11
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS12
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
12
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS13
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
13
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS14
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
14
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS15
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
15
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS2
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
2
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS3
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
3
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS4
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
4
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS5
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
5
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS6
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
6
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS7
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
7
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS8
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
8
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
MFOS9
GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
9
1
read-write
0
Multiple funtion pin output mode type is Push-pull mode
#0
1
Multiple funtion pin output mode type is Open-drain mode
#1
GPA_MFPH
SYS_GPA_MFPH
GPIOA High Byte Multiple Function Control Register
0x34
read-write
n
0x0
0x0
PA10MFP
PA.10 Multi-function Pin Selection
8
4
read-write
PA11MFP
PA.11 Multi-function Pin Selection
12
4
read-write
PA12MFP
PA.12 Multi-function Pin Selection
16
4
read-write
PA13MFP
PA.13 Multi-function Pin Selection
20
4
read-write
PA14MFP
PA.14 Multi-function Pin Selection
24
4
read-write
PA15MFP
PA.15 Multi-function Pin Selection
28
4
read-write
PA8MFP
PA.8 Multi-function Pin Selection
0
4
read-write
PA9MFP
PA.9 Multi-function Pin Selection
4
4
read-write
GPA_MFPL
SYS_GPA_MFPL
GPIOA Low Byte Multiple Function Control Register
0x30
read-write
n
0x0
0x0
PA0MFP
PA.0 Multi-function Pin Selection
0
4
read-write
PA1MFP
PA.1 Multi-function Pin Selection
4
4
read-write
PA2MFP
PA.2 Multi-function Pin Selection
8
4
read-write
PA3MFP
PA.3 Multi-function Pin Selection
12
4
read-write
PA4MFP
PA.4 Multi-function Pin Selection
16
4
read-write
PA5MFP
PA.5 Multi-function Pin Selection
20
4
read-write
PA6MFP
PA.6 Multi-function Pin Selection
24
4
read-write
PA7MFP
PA.7 Multi-function Pin Selection
28
4
read-write
GPB_MFOS
SYS_GPB_MFOS
GPIOB Multiple Function Output Select Register
0x84
read-write
n
0x0
0x0
GPB_MFPH
SYS_GPB_MFPH
GPIOB High Byte Multiple Function Control Register
0x3C
read-write
n
0x0
0x0
PB10MFP
PB.10 Multi-function Pin Selection
8
4
read-write
PB11MFP
PB.11 Multi-function Pin Selection
12
4
read-write
PB12MFP
PB.12 Multi-function Pin Selection
16
4
read-write
PB13MFP
PB.13 Multi-function Pin Selection
20
4
read-write
PB14MFP
PB.14 Multi-function Pin Selection
24
4
read-write
PB15MFP
PB.15 Multi-function Pin Selection
28
4
read-write
PB8MFP
PB.8 Multi-function Pin Selection
0
4
read-write
PB9MFP
PB.9 Multi-function Pin Selection
4
4
read-write
GPB_MFPL
SYS_GPB_MFPL
GPIOB Low Byte Multiple Function Control Register
0x38
read-write
n
0x0
0x0
PB0MFP
PB.0 Multi-function Pin Selection
0
4
read-write
PB1MFP
PB.1 Multi-function Pin Selection
4
4
read-write
PB2MFP
PB.2 Multi-function Pin Selection
8
4
read-write
PB3MFP
PB.3 Multi-function Pin Selection
12
4
read-write
PB4MFP
PB.4 Multi-function Pin Selection
16
4
read-write
PB5MFP
PB.5 Multi-function Pin Selection
20
4
read-write
PB6MFP
PB.6 Multi-function Pin Selection
24
4
read-write
PB7MFP
PB.7 Multi-function Pin Selection
28
4
read-write
GPC_MFOS
SYS_GPC_MFOS
GPIOC Multiple Function Output Select Register
0x88
read-write
n
0x0
0x0
GPC_MFPH
SYS_GPC_MFPH
GPIOC High Byte Multiple Function Control Register
0x44
read-write
n
0x0
0x0
PC10MFP
PC.10 Multi-function Pin Selection
8
4
read-write
PC11MFP
PC.11 Multi-function Pin Selection
12
4
read-write
PC12MFP
PC.12 Multi-function Pin Selection
16
4
read-write
PC13MFP
PC.13 Multi-function Pin Selection
20
4
read-write
PC14MFP
PC.14 Multi-function Pin Selection
24
4
read-write
PC15MFP
PC.15 Multi-function Pin Selection
28
4
read-write
PC8MFP
PC.8 Multi-function Pin Selection
0
4
read-write
PC9MFP
PC.9 Multi-function Pin Selection
4
4
read-write
GPC_MFPL
SYS_GPC_MFPL
GPIOC Low Byte Multiple Function Control Register
0x40
read-write
n
0x0
0x0
PC0MFP
PC.0 Multi-function Pin Selection
0
4
read-write
PC1MFP
PC.1 Multi-function Pin Selection
4
4
read-write
PC2MFP
PC.2 Multi-function Pin Selection
8
4
read-write
PC3MFP
PC.3 Multi-function Pin Selection
12
4
read-write
PC4MFP
PC.4 Multi-function Pin Selection
16
4
read-write
PC5MFP
PC.5 Multi-function Pin Selection
20
4
read-write
PC6MFP
PC.6 Multi-function Pin Selection
24
4
read-write
PC7MFP
PC.7 Multi-function Pin Selection
28
4
read-write
GPD_MFOS
SYS_GPD_MFOS
GPIOD Multiple Function Output Select Register
0x8C
read-write
n
0x0
0x0
GPD_MFPH
SYS_GPD_MFPH
GPIOD High Byte Multiple Function Control Register
0x4C
read-write
n
0x0
0x0
PD10MFP
PD.10 Multi-function Pin Selection
8
4
read-write
PD11MFP
PD.11 Multi-function Pin Selection
12
4
read-write
PD12MFP
PD.12 Multi-function Pin Selection
16
4
read-write
PD13MFP
PD.13 Multi-function Pin Selection
20
4
read-write
PD14MFP
PD.14 Multi-function Pin Selection
24
4
read-write
PD15MFP
PD.15 Multi-function Pin Selection
28
4
read-write
PD8MFP
PD.8 Multi-function Pin Selection
0
4
read-write
PD9MFP
PD.9 Multi-function Pin Selection
4
4
read-write
GPD_MFPL
SYS_GPD_MFPL
GPIOD Low Byte Multiple Function Control Register
0x48
read-write
n
0x0
0x0
PD0MFP
PD.0 Multi-function Pin Selection
0
4
read-write
PD1MFP
PD.1 Multi-function Pin Selection
4
4
read-write
PD2MFP
PD.2 Multi-function Pin Selection
8
4
read-write
PD3MFP
PD.3 Multi-function Pin Selection
12
4
read-write
PD4MFP
PD.4 Multi-function Pin Selection
16
4
read-write
PD5MFP
PD.5 Multi-function Pin Selection
20
4
read-write
PD6MFP
PD.6 Multi-function Pin Selection
24
4
read-write
PD7MFP
PD.7 Multi-function Pin Selection
28
4
read-write
GPE_MFOS
SYS_GPE_MFOS
GPIOE Multiple Function Output Select Register
0x90
read-write
n
0x0
0x0
GPE_MFPH
SYS_GPE_MFPH
GPIOE High Byte Multiple Function Control Register
0x54
read-write
n
0x0
0x0
PE10MFP
PE.10 Multi-function Pin Selection
8
4
read-write
PE11MFP
PE.11 Multi-function Pin Selection
12
4
read-write
PE12MFP
PE.12 Multi-function Pin Selection
16
4
read-write
PE13MFP
PE.13 Multi-function Pin Selection
20
4
read-write
PE14_MFP
PE.14 Multi-function Pin Selection
24
4
read-write
PE15_MFP
PE.15 Multi-function Pin Selection
28
4
read-write
PE8MFP
PE.8 Multi-function Pin Selection
0
4
read-write
PE9MFP
PE.9 Multi-function Pin Selection
4
4
read-write
GPE_MFPL
SYS_GPE_MFPL
GPIOE Low Byte Multiple Function Control Register
0x50
read-write
n
0x0
0x0
PE0MFP
PE.0 Multi-function Pin Selection
0
4
read-write
PE1MFP
PE.1 Multi-function Pin Selection
4
4
read-write
PE2MFP
PE.2 Multi-function Pin Selection
8
4
read-write
PE3MFP
PE.3 Multi-function Pin Selection
12
4
read-write
PE4MFP
PE.4 Multi-function Pin Selection
16
4
read-write
PE5MFP
PE.5 Multi-function Pin Selection
20
4
read-write
PE6MFP
PE.6 Multi-function Pin Selection
24
4
read-write
PE7MFP
PE.7 Multi-function Pin Selection
28
4
read-write
GPF_MFOS
SYS_GPF_MFOS
GPIOF Multiple Function Output Select Register
0x94
read-write
n
0x0
0x0
GPF_MFPH
SYS_GPF_MFPH
GPIOF High Byte Multiple Function Control Register
0x5C
read-write
n
0x0
0x0
PF10MFP
PF.10 Multi-function Pin Selection
8
4
read-write
PF11MFP
PF.11 Multi-function Pin Selection
12
4
read-write
PF12MFP
PF.12 Multi-function Pin Selection
16
4
read-write
PF13MFP
PF.13 Multi-function Pin Selection
20
4
read-write
PF14MFP
PF.14 Multi-function Pin Selection
24
4
read-write
PF15MFP
PF.15 Multi-function Pin Selection
28
4
read-write
PF8MFP
PF.8 Multi-function Pin Selection
0
4
read-write
PF9MFP
PF.9 Multi-function Pin Selection
4
4
read-write
GPF_MFPL
SYS_GPF_MFPL
GPIOF Low Byte Multiple Function Control Register
0x58
-1
read-write
n
0x0
0x0
PF0MFP
PF.0 Multi-function Pin Selection
0
4
read-write
PF1MFP
PF.1 Multi-function Pin Selection
4
4
read-write
PF2MFP
PF.2 Multi-function Pin Selection
8
4
read-write
PF3MFP
PF.3 Multi-function Pin Selection
12
4
read-write
PF4MFP
PF.4 Multi-function Pin Selection
16
4
read-write
PF5MFP
PF.5 Multi-function Pin Selection
20
4
read-write
PF6MFP
PF.6 Multi-function Pin Selection
24
4
read-write
PF7MFP
PF.7 Multi-function Pin Selection
28
4
read-write
HIRCTCTL
SYS_HIRCTCTL
HIRC Test Mode Control Register
0x188
read-write
n
0x0
0x0
HIRCTRIMCTL
SYS_HIRCTRIMCTL
HIRC Trim Control Register
0xF0
-1
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection\nFill the boundary range from 0x1 to 0x1F, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation keeps going if clock is inaccurate
#0
1
The trim operation stops if clock is inaccurate
#1
FREQSEL
Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#01
2
Reserved.
#10
3
Reserved.
#11
LOOPSEL
Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Trim value calculation is based on average difference in 4 clocks of reference clock
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
HIRC trim reference clock is from LXT (32.768 kHz)
#0
1
HIRC trim reference clock is from internal USB synchronous mode
#1
RETRYCNT
Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
HIRCTRIMIEN
SYS_HIRCTRIMIEN
HIRC Trim Interrupt Enable Register
0xF4
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
2
1
read-write
0
Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1
TFALIEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
1
1
read-write
0
Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1
HIRCTRIMSTS
SYS_HIRCTRIMSTS
HIRC Trim Interrupt Status Register
0xF8
read-write
n
0x0
0x0
CLKERIF
Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_HIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote: Reset by power on reset.
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote: Reset by power on reset.
0
1
read-write
0
The internal high-speed oscillator frequency doesn't lock at 48 MHz
#0
1
The internal high-speed oscillator frequency locked at 48 MHz
#1
OVBDIF
Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
3
1
read-write
0
Over boundary coundition did not occur
#0
1
Over boundary coundition occurred
#1
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_HIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote: Reset by power on reset.
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and HIRC frequency still not locked
#1
IPRST0
SYS_IPRST0
Peripheral Reset Control Register 0
0x8
read-write
n
0x0
0x0
CHIPRST
Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.
For the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset
0
1
read-write
0
Chip normal operation
#0
1
Chip one-shot reset
#1
CPURST
Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
Processor core normal operation
#0
1
Processor core one-shot reset
#1
CRCRST
CRC Calculation Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
CRC calculation controller normal operation
#0
1
CRC calculation controller reset
#1
CRYPTRST
CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
12
1
read-write
0
CRYPTO controller normal operation
#0
1
CRYPTO controller reset
#1
EBIRST
EBI Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
3
1
read-write
0
EBI controller normal operation
#0
1
EBI controller reset
#1
PDMARST
PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
PDMA controller normal operation
#0
1
PDMA controller reset
#1
IPRST1
SYS_IPRST1
Peripheral Reset Control Register 1
0xC
read-write
n
0x0
0x0
ACMP01RST
Analog Comparator 0/1 Controller Reset
7
1
read-write
0
Analog Comparator 0/1 controller normal operation
#0
1
Analog Comparator 0/1 controller reset
#1
EADCRST
EADC Controller Reset
28
1
read-write
0
EADC controller normal operation
#0
1
EADC controller reset
#1
GPIORST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C0RST
I2C0 Controller Reset
8
1
read-write
0
I2C0 controller normal operation
#0
1
I2C0 controller reset
#1
I2C1RST
I2C1 Controller Reset
9
1
read-write
0
I2C1 controller normal operation
#0
1
I2C1 controller reset
#1
QSPI0RST
QSPI0 Controller Reset
12
1
read-write
0
QSPI0 controller normal operation
#0
1
QSPI0 controller reset
#1
SPI0RST
SPI0 Controller Reset
13
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
TMR0RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
UART2RST
UART2 Controller Reset
18
1
read-write
0
UART2 controller normal operation
#0
1
UART2 controller reset
#1
USBDRST
USBD Controller Reset
27
1
read-write
0
USBD controller normal operation
#0
1
USBD controller reset
#1
IPRST2
SYS_IPRST2
Peripheral Reset Control Register 2
0x10
read-write
n
0x0
0x0
BPWM0RST
BPWM0 Controller Reset
18
1
read-write
0
BPWM0 controller normal operation
#0
1
BPWM0 controller reset
#1
BPWM1RST
BPWM1 Controller Reset
19
1
read-write
0
BPWM1 controller normal operation
#0
1
BPWM1 controller reset
#1
DACRST
DAC Controller Reset
12
1
read-write
0
DAC controller normal operation
#0
1
DAC controller reset
#1
OPARST
OP Amplifier (OPA) Controller Reset
30
1
read-write
0
OPA controller normal operation
#0
1
OPA controller reset
#1
PSIORST
PSIORST
31
1
read-write
PWM0RST
PWM0 Controller Reset
16
1
read-write
0
PWM0 controller normal operation
#0
1
PWM0 controller reset
#1
PWM1RST
PWM1 Controller Reset
17
1
read-write
0
PWM1 controller normal operation
#0
1
PWM1 controller reset
#1
SC0RST
SC0 Controller Reset
0
1
read-write
0
SC0 controller normal operation
#0
1
SC0 controller reset
#1
SLCDRST
SLCD Controller Reset
14
1
read-write
0
Segment LCD controller normal operation
#0
1
Segment LCD controller reset
#1
TKRST
Touch Key Controller Reset
15
1
read-write
0
Touch Key controller normal operation
#0
1
Touch Key controller reset
#1
USCI0RST
USCI0 Controller Reset
8
1
read-write
0
USCI0 controller normal operation
#0
1
USCI0 controller reset
#1
USCI1RST
USCI1 Controller Reset
9
1
read-write
0
USCI1 controller normal operation
#0
1
USCI1 controller reset
#1
USCI2RST
USCI2 Controller Reset
10
1
read-write
0
USCI2 controller normal operation
#0
1
USCI2 controller reset
#1
IVSCTL
SYS_IVSCTL
Internal Voltage Source Control Register
0x1C
read-write
n
0x0
0x0
VBATUGEN
VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
1
1
read-write
0
VBAT unity gain buffer function Disabled (default)
#0
1
VBAT unity gain buffer function Enabled
#1
VTEMPEN
Temperature Sensor Enable Bit
This bit is used to enable/disable temperature sensor function.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
MIRCTRIMCTL
SYS_MIRCTRIMCTL
MIRC Trim Control Register
0x104
read-write
n
0x0
0x0
BOUNDARY
Boundary Selection\nFill the boundary range from 0x1 to 0x1F, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled
16
5
read-write
BOUNDEN
Boundary Enable Bit
9
1
read-write
0
Boundary function Disabled
#0
1
Boundary function Enabled
#1
CESTOPEN
Clock Error Stop Enable Bit
8
1
read-write
0
The trim operation keeps going if clock is inaccurate
#0
1
The trim operation stops if clock is inaccurate
#1
FREQSEL
Trim Frequency Selection\nThis field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
0
2
read-write
0
Disable HIRC auto trim function
#00
1
Reserved.
#01
2
Enable HIRC auto trim function and trim MIRC to 4.032 MHz
#10
LOOPSEL
Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
4
2
read-write
0
Reserved.
#00
1
Trim value calculation is based on average difference in 8 clocks of reference clock
#01
2
Trim value calculation is based on average difference in 16 clocks of reference clock
#10
3
Trim value calculation is based on average difference in 32 clocks of reference clock
#11
REFCKSEL
Reference Clock Selection
10
1
read-write
0
MIRC trim reference clock is from LXT (32.768 kHz)
#0
1
MIRC trim reference clock is from internal USB synchronous mode
#1
RETRYCNT
Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
6
2
read-write
0
Trim retry count limitation is 64 loops
#00
1
Trim retry count limitation is 128 loops
#01
2
Trim retry count limitation is 256 loops
#10
3
Trim retry count limitation is 512 loops
#11
MIRCTRIMIEN
SYS_MIRCTRIMIEN
MIRC Trim Interrupt Enable Register
0x108
read-write
n
0x0
0x0
CLKEIEN
Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_MIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
2
1
read-write
0
Disable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#0
1
Enable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1
TFALIEN
Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRTRIMCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_ MIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached.
1
1
read-write
0
Disable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#0
1
Enable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1
MIRCTRIMSTS
SYS_MIRCTRIMSTS
MIRC Trim Interrupt Status Register
0x10C
read-write
n
0x0
0x0
CLKERIF
Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_MIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote: Reset by power on reset.
2
1
read-write
0
Clock frequency is accuracy
#0
1
Clock frequency is inaccuracy
#1
FREQLOCK
MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote: Reset by power on reset.
0
1
read-write
0
The internal medium-speed oscillator frequency isn't locked
#0
1
The internal medium-speed oscillator frequency locked
#1
OVBDIF
Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
3
1
read-write
0
Over boundary coundition did not occur
#0
1
Over boundary coundition occurred
#1
TFAILIF
Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_MIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote: Reset by power on reset.
1
1
read-write
0
Trim value update limitation count does not reach
#0
1
Trim value update limitation count reached and MIRC frequency still not locked
#1
MODCTL
SYS_MODCTL
Modulation Control Register
0xC0
read-write
n
0x0
0x0
MODEN
Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT1) or UART0(UART0_TXD) output.
0
1
read-write
0
Modulation Function Disabled
#0
1
Modulation Function Enabled
#1
MODH
Modulation at Data High\nSelect modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT1
1
1
read-write
0
Modulation pulse at UART0_TXD low or USCI0_DAT1 low
#0
1
Modulation pulse at UART0_TXD high or USCI0_DAT1 high
#1
MODPWMSEL
PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT1.\n0000: PWM0 Channel 0 modulate with UART0_TXD.\n0001: PWM0 Channel 1 modulate with UART0_TXD.\n0010: PWM0 Channel 2 modulate with UART0_TXD.\n0011: PWM0 Channel 3 modulete with UART0_TXD.\n0100: PWM0 Channel 4 modulete with UART0_TXD.\n0101: PWM0 Channel 5 modulete with UART0_TXD.\n0110: Reserved.\n0111: Reserved.\n1000: PWM0 Channel 0 modulate with USCI0_DAT1.\n1001: PWM0 Channel 1 modulate with USCI0_DAT1.\n1010: PWM0 Channel 2 modulate with USCI0_DAT1.\n1011: PWM0 Channel 3 modulete with USCI0_DAT1.\n1100: PWM0 Channel 4 modulete with USCI0_DAT1.\n1101: PWM0 Channel 5 modulete with USCI0_DAT1.\n1110: Reserved.\n1111: Reserved.\nNote: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
4
4
read-write
PDID
SYS_PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
0
32
read-only
PLCTL
SYS_PLCTL
Power Level Control Register
0x1F8
read-write
n
0x0
0x0
PLSEL
Power Level Select(Write Protect)\nNote : When at PL2, HCLK has to be lower than 4Mhz
0
2
read-write
0
Set to power level 0 (PL0)
#00
1
Reserved.
#01
2
Set to power level 2 (PL2) [Internal note: this mode is MLDO low power mode]
#10
3
Reserved.
#11
PLSTS
SYS_PLSTS
Power Level Status Register
0x1FC
read-write
n
0x0
0x0
CURPL
Current Power Level (Read Only)\nThis bit field reflect the current power level.
8
2
read-only
0
Current power level is PL0
#00
1
Reserved.
#01
2
Current power level is PL2. [Internal note: this mode is MLDO low power mode]
#10
PLCBUSY
Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
0
1
read-only
0
Power level change is completed
#0
1
Power level change is ongoing
#1
PORCTL0
SYS_PORCTL0
Power-On-reset Controller Register 0
0x24
read-write
n
0x0
0x0
PORMASK
Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
PORCTL1
SYS_PORCTL1
Power-On-reset Controller Register 1
0x1EC
read-write
n
0x0
0x0
POROFF
Power-on Reset Enable Bit (Write Protect)\nAfter powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
16
read-write
REGLCTL
SYS_REGLCTL
Register Lock Control Register
0x100
read-write
n
0x0
0x0
REGLCTL
Register Lock Control Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Lock Control Disable Index
The Protected registers are:
NMIEN address 0x4000_0300
FMC_ISPCTL address 0x4000_C000 (Flash ISP Control register)
FMC_ISPTRG address 0x4000_C010 (ISP Trigger Control register)
FMC_ISPSTS address 0x4000_C040
WDT_CTL address 0x4004_0000
FMC_FTCTL address 0x4000_5018
FMC_ICPCMD address 0x4000_501C
EADC_TEST address 0x4004_3200
AHBMCTL address 0x4000_0400
SYS_IPRST0 address 0x4000_0008
SYS_BODCTL address 0x4000_0018
SYS_PORCTL0 address 0x4000_0024
SYS_SRAM_BISTCTL address 0x4000_00D0
SYS_PORCTL1 address 0x4000_1EC
CLK_PWRCTL address 0x4000_0200
CLK_APBCLK0[0] address 0x4000_0208
CLK_CLKSEL0 address 0x4000_0110
CLK_CLKSEL1[3:0] address 0x4000_0214
CLK_PLLCTL address 0x4000_0240
CLK_PMUCTL address 0x4000_0290
CLK_HXTFSEL address 0x4000_02B4
PWM_CTL0 address 0x4005_8000
PWM_CTL0 address 0x4005_9000
PWM_DTCTL0_1 address 0x4005_8070
PWM_DTCTL0_1 address 0x4005_9070
PWM_DTCTL2_3 address 0x4005_8074
PWM_DTCTL2_3 address 0x4005_9074
PWM_DTCTL4_5 address 0x4005_8078
PWM_DTCTL4_5 address 0x4005_9078
PWM_BRKCTL0_1 address 0x4005_80C8
PWM_BRKCTL0_1 address 0x4005_90C8
PWM_BRKCTL2_3 address0x4005_80CC
PWM_BRKCTL2_3 address0x4005_90CC
PWM_BRKCTL4_5 address0x4005_80D0
PWM_BRKCTL4_5 address0x4005_90D0
PWM_INTEN1 address0x4005_80E4
PWM_INTEN1 address0x4005_90E4
PWM_INTSTS1 address0x4005_80EC
PWM_INTSTS1 address0x4005_90EC
PWM_SELFTEST address0x4005_8300
PWM_SELFTEST address0x4005_930
0
8
read-write
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
0
1
Write-protection Disabled for writing protected registers
1
RSTSTS
SYS_RSTSTS
System Reset Status Register
0x4
-1
read-write
n
0x0
0x0
BODRF
BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
CPULKRF
CPU Lockup Reset Flag
Note: Write 1 to clear this bit to 0.
Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
8
1
read-write
0
No reset from CPU lockup happened
#0
1
The Cortex-M23lockup happened and chip is reset
#1
CPURF
CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M23 Core and FMC are reset by software setting CPURST to 1
#1
LVRF
LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
LVR controller had issued the reset signal to reset the system
#1
PINRF
NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
1
1
read-write
0
No reset from nRESET pin
#0
1
Pin nRESET had issued the reset signal to reset the system
#1
PMURF
PMU Reset Flag, \nThe PMU reset flag is set by any reset signal when MCU is in power down state.\nNote: Write 1 to clear this bit to 0.
6
1
read-write
0
No reset in power down state
#0
1
Any reset signal happens in power down state
#1
PORF
POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIPRST
#0
1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
#1
SYSRF
System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the CortexM23Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M23
#0
1
The Cortex- M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23core
#1
VBATLVRF
VBAT LVR Reset Flag\nThe VBAT LVR reset flag is set by the 'Reset Signal' from the VBAT Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
9
1
read-write
0
No reset from VBAT LVR
#0
1
VBAT LVR controller had issued the reset signal to reset the system
#1
WDTRF
WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note 1: Write 1 to clear this bit to 0.
Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
2
1
read-write
0
No reset from watchdog timer or window watchdog timer
#0
1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
#1
RTCLVRIEN
SYS_RTCLVRIEN
RTC LVR Interrupt Control Register
0x144
read-write
n
0x0
0x0
IE
RTC LVR Interrupt Enable Bit (Write Protect)
0
1
read-write
0
RTC LVR Interrupt Disabled (default)
#0
1
RTC LVR Interrupt Enabled
#1
RTCLVRSTS
SYS_RTCLVRSTS
RTC LVR Interrupt Status Register
0x148
read-write
n
0x0
0x0
IF
RTC LVR Interrupt Flag\nWhen a positive edge of RTCLVR is detected, this bit will be set to 1 and will be cleared when a 1 is set to this bit\nThis bit is write protected
0
1
read-write
RTCLVR
RTCLVR value (read only)
8
1
read-only
SRAM_BISTCTL
SYS_SRAM_BISTCTL
System SRAM BIST Test Control Register
0xD0
read-write
n
0x0
0x0
FMCBIST
FMC CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
2
1
read-write
0
System CACHE BIST Disabled
#0
1
System CACHE BIST Enabled
#1
PDMABIST
PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
7
1
read-write
0
System PDMA BIST Disabled
#0
1
Sstem PDMA BIST Enabled
#1
SRBIST
SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
0
1
read-write
0
System SRAM BIST Disabled
#0
1
System SRAM BIST Enabled
#1
USBBIST
USB BIST Enable Bit (Write Protect) \nThis bit enables BIST test for USB RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
4
1
read-write
0
System USB BIST Disabled
#0
1
System USB BIST Enabled
#1
SRAM_BISTSTS
SYS_SRAM_BISTSTS
System SRAM BIST Test Status Register
0xD4
read-only
n
0x0
0x0
CR0BEND
CACHE 0 SRAM BIST Test Finish
17
1
read-only
0
System CACHE RAM BIST is active
#0
1
System CACHE RAM BIST test finished
#1
CR0BISTEF
CACHE0 SRAM BIST Fail Flag
1
1
read-only
0
System CACHE RAM BIST test pass
#0
1
System CACHE RAM BIST test failed
#1
CR1BEND
CACHE 1 SRAM BIST Test Finish
18
1
read-only
0
System CACHE RAM BIST is active
#0
1
System CACHE RAM BIST test finished
#1
CR1BISTEF
CACHE1 SRAM BIST Fail Flag
2
1
read-only
0
System CACHE RAM BIST test pass
#0
1
System CACHE RAM BIST test failed
#1
PDMABISTF
PDMA SRAM BIST Failed Flag
7
1
read-only
0
PDMA SRAM BIST pass
#0
1
PDMA SRAM BIST failed
#1
PDMAEND
PDMA SRAM BIST Test Finish
23
1
read-only
0
PDMA SRAM BIST is active
#0
1
PDMA SRAM BIST test finished
#1
SRBEND
SRAM BIST Test Finish
16
1
read-only
0
System SRAM BIST active
#0
1
system SRAM BIST finished
#1
SRBISTEF
System SRAM BIST Fail Flag
0
1
read-only
0
System SRAM BIST test pass
#0
1
System SRAM BIST test failed
#1
USBBEF
USB SRAM BIST Fail Flag
4
1
read-only
0
USB SRAM BIST test pass
#0
1
USB SRAM BIST test failed
#1
USBBEND
USB SRAM BIST Test Finish
20
1
read-only
0
USB SRAM BIST is active
#0
1
USB SRAM BIST test finished
#1
VREFCTL
SYS_VREFCTL
VREF Control Register
0x28
read-write
n
0x0
0x0
IVREN
Internal Voltage Reference Module Enable Bit (Write Protect)
Note: INT_VREF is only supported while package includes VREF pin with external capacitor.
3
1
read-write
0
Internal voltage reference module Disabled
#0
1
Internal voltage reference module Enabled
#1
IVRS
Internal Voltage Reference Scale (Write Protect)
0
3
read-write
0
Internal voltage reference(INT_VREF) set to 1.536V
0
1
Internal voltage reference(INT_VREF) set to 2.048V
1
2
Internal voltage reference(INT_VREF) set to 2.56V
2
3
Internal voltage reference(INT_VREF) set to 3.072V
3
4
Internal voltage reference(INT_VREF) set to 4.096V
4
PRELOAD
Preload Enable Bit\nNote: This bit is used to speed up charging external capacitor of VREF.If INT_VREF voltage is stable, this bit has to be disabled.
10
1
read-write
0
Preload Disabled (default)
#0
1
Preload Enabled
#1
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x20
registers
n
0x100
0x20
registers
n
0x140
0x38
registers
n
0x40
0x38
registers
n
TIMER0_CAP
TIMER0_CAP
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER0_CMP
TIMER0_CMP
Timer0 Comparator Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER0_CNT
TIMER0_CNT
Timer0 Data Register
0xC
read-write
n
0x0
0x0
CNT
Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation.\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER0_CTL
TIMER0_CTL
Timer0 Control Register
0x0
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
22
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal , internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT)
#1
CNTEN
Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
FUNCSEL
Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
15
1
read-write
0
Timer controller is used as timer function
#0
1
Timer controller is used as PWM function
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ineffective and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER0_EINTSTS
TIMER0_EINTSTS
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred
#1
TIMER0_EXTCTL
TIMER0_EXTCTL
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPDIVSCL
Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
28
4
read-write
0
Capture source/1
#0000
1
Capture source/2
#0001
2
Capture source/4
#0010
3
Capture source/8
#0011
4
Capture source/16
#0100
5
Capture source/32
#0101
6
Capture source/64
#0110
7
Capture source/128
#0111
8
Capture source/256
#1000
CAPEDGE
Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Event Counter input source is from USB internal SOF output signal
#1
INTERCAPSEL
Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
2
Capture Function source is from HXT
#010
3
Capture Function source is from LXT
#011
4
Capture Function source is from HIRC
#100
5
Capture Function source is from LIRC
#101
6
Capture Function source is from MIRC
#110
7
Reserved.
#111
TIMER0_INTSTS
TIMER0_INTSTS
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER0_PWMCLKPSC
TIMER0_PWMCLKPSC
Timer0 PWM Counter Clock Pre-scale Register
0x44
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
0
8
read-write
TIMER0_PWMCMPBUF
TIMER0_PWMCMPBUF
Timer0 PWM Comparator Buffer Register
0x74
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register.
0
16
read-only
TIMER0_PWMCMPDAT
TIMER0_PWMCMPDAT
Timer0 PWM Comparator Register
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start convert.
0
16
read-write
TIMER0_PWMCNT
TIMER0_PWMCNT
Timer0 PWM Counter Register
0x54
read-only
n
0x0
0x0
CNT
PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter.
0
16
read-only
TIMER0_PWMCNTCLR
TIMER0_PWMCNTCLR
Timer0 PWM Clear Counter Register
0x48
read-write
n
0x0
0x0
CNTCLR
Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0x0000 in up count type
#1
TIMER0_PWMCTL
TIMER0_PWMCTL
Timer0 PWM Control Register
0x40
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit
0
1
read-write
0
PWM counter and clock prescale Stop Running
#0
1
PWM counter and clock prescale Start Running
#1
CNTMODE
PWM Counter Mode
3
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
PWMINTWKEN
PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not.
12
1
read-write
0
PWM interrupt wake-up Disabled
#0
1
PWM interrupt wake-up Enabled
#1
TIMER0_PWMINTEN0
TIMER0_PWMINTEN0
Timer0 PWM Interrupt Enable Register 0
0x60
read-write
n
0x0
0x0
CMPUIEN
PWM Compare Up Count Interrupt Enable Bit
2
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN
PWM Period Point Interrupt Enable Bit
1
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
TIMER0_PWMINTSTS0
TIMER0_PWMINTSTS0
Timer0 PWM Interrupt Status Register 0
0x64
read-write
n
0x0
0x0
CMPUIF
PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. Note2: This bit is cleared by writing 1 to it.
2
1
read-write
PIF
PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
TIMER0_PWMPBUF
TIMER0_PWMPBUF
Timer0 PWM Period Buffer Register
0x70
read-only
n
0x0
0x0
PBUF
PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register.
0
16
read-only
TIMER0_PWMPERIOD
TIMER0_PWMPERIOD
Timer0 PWM Period Register
0x4C
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn up count type:
0
16
read-write
TIMER0_PWMPOCTL
TIMER0_PWMPOCTL
Timer0 PWM Pin Output Control Register
0x5C
read-write
n
0x0
0x0
POEN
PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
0
1
read-write
0
PWMx_OUT pin at tri-state mode
#0
1
PWMx_OUT pin in output mode
#1
POSEL
PWM Output Pin Select
8
1
read-write
0
PWMx_OUT pin is TMx
#0
1
PWMx_OUT pin is TMx_EXT
#1
TIMER0_PWMPOLCTL
TIMER0_PWMPOLCTL
Timer0 PWM Pin Output Polar Control Register
0x58
read-write
n
0x0
0x0
PINV
PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
0
1
read-write
0
PWMx_OUT pin polar inverse Disabled
#0
1
PWMx_OUT polar inverse Enabled
#1
TIMER0_PWMSTATUS
TIMER0_PWMSTATUS
Timer0 PWM Status Register
0x6C
read-write
n
0x0
0x0
CNTMAXF
PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
The PWM counter value never reached its maximum value 0xFFFF
#0
1
The PWM counter value has reached its maximum value
#1
DACTRGF
Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
17
1
read-write
0
PWM counter event trigger DAC start conversion has not occurred
#0
1
PWM counter event trigger DAC start conversion has occurred
#1
EADCTRGF
Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
16
1
read-write
0
PWM counter event trigger EADC start conversion is not occurred
#0
1
PWM counter event trigger EADC start conversion has occurred
#1
PDMATRGF
Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
18
1
read-write
0
PWM counter event trigger PDMA start conversion has not occurred
#0
1
PWM counter event trigger PDMA start conversion has occurred
#1
PWMINTWKF
PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
PWM interrupt wake-up has not occurred
#0
1
PWM interrupt wake-up has occurred
#1
TIMER0_PWMTRGCTL
TIMER0_PWMTRGCTL
Timer0 PWM Trigger Control Register
0x68
read-write
n
0x0
0x0
PWMTRGDAC
PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
8
1
read-write
0
PWM trigger DAC Disabled
#0
1
PWM trigger DAC Enabled
#1
PWMTRGEADC
PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
7
1
read-write
0
PWM counter event trigger EADC conversion Disabled
#0
1
PWM counter event trigger EADC conversion Enabled
#1
PWMTRGPDMA
PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
9
1
read-write
0
PWM trigger PDMA Disabled
#0
1
PWM trigger PDMA Enabled
#1
TRGSEL
PWM Counter Event Source Select to Trigger Conversion
0
2
read-write
0
Trigger conversion at period point (PIF)
#00
1
Trigger conversion at compare up count point (CMPUIF)
#01
2
Trigger conversion at period or compare up count point (PIF or CMPUIF)
#10
3
Reserved.
#11
TIMER0_TRGCTL
TIMER0_TRGCTL
Timer0 Trigger Control Register
0x1C
read-write
n
0x0
0x0
TRGDAC
Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
3
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGEADC
Trigger EADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
2
1
read-write
0
Timer interrupt trigger EADC Disabled
#0
1
Timer interrupt trigger EADC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM/BPWM counter clock source.
1
1
read-write
0
Timer interrupt trigger PWM/BPWM Disabled
#0
1
Timer interrupt trigger PWM/BPWM Enabled
#1
TRGSSEL
Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC
#0
1
Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC
#1
TIMER1_CAP
TIMER1_CAP
Timer1 Capture Data Register
0x110
read-write
n
0x0
0x0
TIMER1_CMP
TIMER1_CMP
Timer1 Comparator Register
0x104
read-write
n
0x0
0x0
TIMER1_CNT
TIMER1_CNT
Timer1 Data Register
0x10C
read-write
n
0x0
0x0
TIMER1_CTL
TIMER1_CTL
Timer1 Control Register
0x100
read-write
n
0x0
0x0
TIMER1_EINTSTS
TIMER1_EINTSTS
Timer1 External Interrupt Status Register
0x118
read-write
n
0x0
0x0
TIMER1_EXTCTL
TIMER1_EXTCTL
Timer1 External Control Register
0x114
read-write
n
0x0
0x0
TIMER1_INTSTS
TIMER1_INTSTS
Timer1 Interrupt Status Register
0x108
read-write
n
0x0
0x0
TIMER1_PWMCLKPSC
TIMER1_PWMCLKPSC
Timer1 PWM Counter Clock Pre-scale Register
0x144
read-write
n
0x0
0x0
TIMER1_PWMCMPBUF
TIMER1_PWMCMPBUF
Timer1 PWM Comparator Buffer Register
0x174
read-write
n
0x0
0x0
TIMER1_PWMCMPDAT
TIMER1_PWMCMPDAT
Timer1 PWM Comparator Register
0x150
read-write
n
0x0
0x0
TIMER1_PWMCNT
TIMER1_PWMCNT
Timer1 PWM Counter Register
0x154
read-write
n
0x0
0x0
TIMER1_PWMCNTCLR
TIMER1_PWMCNTCLR
Timer1 PWM Clear Counter Register
0x148
read-write
n
0x0
0x0
TIMER1_PWMCTL
TIMER1_PWMCTL
Timer1 PWM Control Register
0x140
read-write
n
0x0
0x0
TIMER1_PWMINTEN0
TIMER1_PWMINTEN0
Timer1 PWM Interrupt Enable Register 0
0x160
read-write
n
0x0
0x0
TIMER1_PWMINTSTS0
TIMER1_PWMINTSTS0
Timer1 PWM Interrupt Status Register 0
0x164
read-write
n
0x0
0x0
TIMER1_PWMPBUF
TIMER1_PWMPBUF
Timer1 PWM Period Buffer Register
0x170
read-write
n
0x0
0x0
TIMER1_PWMPERIOD
TIMER1_PWMPERIOD
Timer1 PWM Period Register
0x14C
read-write
n
0x0
0x0
TIMER1_PWMPOCTL
TIMER1_PWMPOCTL
Timer1 PWM Pin Output Control Register
0x15C
read-write
n
0x0
0x0
TIMER1_PWMPOLCTL
TIMER1_PWMPOLCTL
Timer1 PWM Pin Output Polar Control Register
0x158
read-write
n
0x0
0x0
TIMER1_PWMSTATUS
TIMER1_PWMSTATUS
Timer1 PWM Status Register
0x16C
read-write
n
0x0
0x0
TIMER1_PWMTRGCTL
TIMER1_PWMTRGCTL
Timer1 PWM Trigger Control Register
0x168
read-write
n
0x0
0x0
TIMER1_TRGCTL
TIMER1_TRGCTL
Timer1 Trigger Control Register
0x11C
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x20
registers
n
0x100
0x20
registers
n
0x140
0x38
registers
n
0x40
0x38
registers
n
TIMER2_CAP
TIMER2_CAP
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
CAPDAT
Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
0
24
read-only
TIMER2_CMP
TIMER2_CMP
Timer2 Comparator Register
0x4
read-write
n
0x0
0x0
CMPDAT
Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
0
24
read-write
TIMER2_CNT
TIMER2_CNT
Timer2 Data Register
0xC
read-write
n
0x0
0x0
CNT
Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation.\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
0
24
read-write
RSTACT
Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
31
1
read-only
0
Reset operation is done
#0
1
Reset operation triggered by writing TIMERx_CNT is in progress
#1
TIMER2_CTL
TIMER2_CTL
Timer2 Control Register
0x0
read-write
n
0x0
0x0
ACTSTS
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CAPSRC
Capture Pin Source Selection
22
1
read-write
0
Capture Function source is from TMx_EXT (x= 0~3) pin
#0
1
Capture Function source is from internal ACMP output signal , internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT)
#1
CNTEN
Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
EXTCNTEN
Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
24
1
read-write
0
Event counter mode Disabled
#0
1
Event counter mode Enabled
#1
FUNCSEL
Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
15
1
read-write
0
Timer controller is used as timer function
#0
1
Timer controller is used as PWM function
#1
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer time-out interrupt Disabled
#0
1
Timer time-out interrupt Enabled
#1
INTRGEN
Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ineffective and the read back value is always 0.
19
1
read-write
0
Inter-Timer Trigger Capture mode Disabled
#0
1
Inter-Timer Trigger Capture mode Enabled
#1
OPMODE
Timer Counting Mode Select
27
2
read-write
0
The timer controller is operated in One-shot mode
#00
1
The timer controller is operated in Periodic mode
#01
2
The timer controller is operated in Toggle-output mode
#10
3
The timer controller is operated in Continuous Counting mode
#11
PERIOSEL
Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT, CNT will be reset to default value.
20
1
read-write
0
The behavior selection in periodic mode is Disabled
#0
1
The behavior selection in periodic mode is Enabled
#1
PSC
Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
0
8
read-write
TGLPINSEL
Toggle-output Pin Select
21
1
read-write
0
Toggle mode output to TMx (Timer Event Counter Pin)
#0
1
Toggle mode output to TMx_EXT (Timer External Capture Pin)
#1
WKEN
Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
23
1
read-write
0
Wake-up function Disabled if timer interrupt signal generated
#0
1
Wake-up function Enabled if timer interrupt signal generated
#1
TIMER2_EINTSTS
TIMER2_EINTSTS
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
CAPIF
Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
0
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred
#1
TIMER2_EXTCTL
TIMER2_EXTCTL
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
CAPDBEN
Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
6
1
read-write
0
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#0
1
TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
#1
CAPDIVSCL
Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
28
4
read-write
0
Capture source/1
#0000
1
Capture source/2
#0001
2
Capture source/4
#0010
3
Capture source/8
#0011
4
Capture source/16
#0100
5
Capture source/32
#0101
6
Capture source/64
#0110
7
Capture source/128
#0111
8
Capture source/256
#1000
CAPEDGE
Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
12
3
read-write
0
Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin
#000
1
Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin
#001
2
Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#010
3
Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer
#011
6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin
#110
7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin
#111
CAPEN
Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source.
3
1
read-write
0
Capture source Disabled
#0
1
Capture source Enabled
#1
CAPFUNCS
Capture Function Selection
4
1
read-write
0
External Capture Mode Enabled
#0
1
External Reset Mode Enabled
#1
CAPIEN
Timer External Capture Interrupt Enable Bit
5
1
read-write
0
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled
#0
1
TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled
#1
CNTDBEN
Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx (x= 0~3) pin de-bounce Disabled
#0
1
TMx (x= 0~3) pin de-bounce Enabled
#1
CNTPHASE
Timer External Count Phase
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
ECNTSSEL
Event Counter Source Selection to Trigger Event Counter Function
16
1
read-write
0
Event Counter input source is from TMx (x= 0~3) pin
#0
1
Event Counter input source is from USB internal SOF output signal
#1
INTERCAPSEL
Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
8
3
read-write
0
Capture Function source is from internal ACMP0 output signal
#000
1
Capture Function source is from internal ACMP1 output signal
#001
2
Capture Function source is from HXT
#010
3
Capture Function source is from LXT
#011
4
Capture Function source is from HIRC
#100
5
Capture Function source is from LIRC
#101
6
Capture Function source is from MIRC
#110
7
Reserved.
#111
TIMER2_INTSTS
TIMER2_INTSTS
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
CNT value matches the CMPDAT value
#1
TWKF
Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
#1
TIMER2_PWMCLKPSC
TIMER2_PWMCLKPSC
Timer2 PWM Counter Clock Pre-scale Register
0x44
read-write
n
0x0
0x0
CLKPSC
PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
0
8
read-write
TIMER2_PWMCMPBUF
TIMER2_PWMCMPBUF
Timer2 PWM Comparator Buffer Register
0x74
read-only
n
0x0
0x0
CMPBUF
PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register.
0
16
read-only
TIMER2_PWMCMPDAT
TIMER2_PWMCMPDAT
Timer2 PWM Comparator Register
0x50
read-write
n
0x0
0x0
CMP
PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start convert.
0
16
read-write
TIMER2_PWMCNT
TIMER2_PWMCNT
Timer2 PWM Counter Register
0x54
read-only
n
0x0
0x0
CNT
PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter.
0
16
read-only
TIMER2_PWMCNTCLR
TIMER2_PWMCNTCLR
Timer2 PWM Clear Counter Register
0x48
read-write
n
0x0
0x0
CNTCLR
Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Clear 16-bit PWM counter to 0x0000 in up count type
#1
TIMER2_PWMCTL
TIMER2_PWMCTL
Timer2 PWM Control Register
0x40
read-write
n
0x0
0x0
CNTEN
PWM Counter Enable Bit
0
1
read-write
0
PWM counter and clock prescale Stop Running
#0
1
PWM counter and clock prescale Start Running
#1
CNTMODE
PWM Counter Mode
3
1
read-write
0
Auto-reload mode
#0
1
One-shot mode
#1
DBGHALT
ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
30
1
read-write
0
ICE debug mode counter halt Disabled
#0
1
ICE debug mode counter halt Enabled
#1
DBGTRIOFF
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
31
1
read-write
0
ICE debug mode acknowledgement effects PWM output
#0
1
ICE debug mode acknowledgement disabled
#1
PWMINTWKEN
PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not.
12
1
read-write
0
PWM interrupt wake-up Disabled
#0
1
PWM interrupt wake-up Enabled
#1
TIMER2_PWMINTEN0
TIMER2_PWMINTEN0
Timer2 PWM Interrupt Enable Register 0
0x60
read-write
n
0x0
0x0
CMPUIEN
PWM Compare Up Count Interrupt Enable Bit
2
1
read-write
0
Compare up count interrupt Disabled
#0
1
Compare up count interrupt Enabled
#1
PIEN
PWM Period Point Interrupt Enable Bit
1
1
read-write
0
Period point interrupt Disabled
#0
1
Period point interrupt Enabled
#1
TIMER2_PWMINTSTS0
TIMER2_PWMINTSTS0
Timer2 PWM Interrupt Status Register 0
0x64
read-write
n
0x0
0x0
CMPUIF
PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. Note2: This bit is cleared by writing 1 to it.
2
1
read-write
PIF
PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
TIMER2_PWMPBUF
TIMER2_PWMPBUF
Timer2 PWM Period Buffer Register
0x70
read-only
n
0x0
0x0
PBUF
PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register.
0
16
read-only
TIMER2_PWMPERIOD
TIMER2_PWMPERIOD
Timer2 PWM Period Register
0x4C
read-write
n
0x0
0x0
PERIOD
PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn up count type:
0
16
read-write
TIMER2_PWMPOCTL
TIMER2_PWMPOCTL
Timer2 PWM Pin Output Control Register
0x5C
read-write
n
0x0
0x0
POEN
PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
0
1
read-write
0
PWMx_OUT pin at tri-state mode
#0
1
PWMx_OUT pin in output mode
#1
POSEL
PWM Output Pin Select
8
1
read-write
0
PWMx_OUT pin is TMx
#0
1
PWMx_OUT pin is TMx_EXT
#1
TIMER2_PWMPOLCTL
TIMER2_PWMPOLCTL
Timer2 PWM Pin Output Polar Control Register
0x58
read-write
n
0x0
0x0
PINV
PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
0
1
read-write
0
PWMx_OUT pin polar inverse Disabled
#0
1
PWMx_OUT polar inverse Enabled
#1
TIMER2_PWMSTATUS
TIMER2_PWMSTATUS
Timer2 PWM Status Register
0x6C
read-write
n
0x0
0x0
CNTMAXF
PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
The PWM counter value never reached its maximum value 0xFFFF
#0
1
The PWM counter value has reached its maximum value
#1
DACTRGF
Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
17
1
read-write
0
PWM counter event trigger DAC start conversion has not occurred
#0
1
PWM counter event trigger DAC start conversion has occurred
#1
EADCTRGF
Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
16
1
read-write
0
PWM counter event trigger EADC start conversion is not occurred
#0
1
PWM counter event trigger EADC start conversion has occurred
#1
PDMATRGF
Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
18
1
read-write
0
PWM counter event trigger PDMA start conversion has not occurred
#0
1
PWM counter event trigger PDMA start conversion has occurred
#1
PWMINTWKF
PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it.
8
1
read-write
0
PWM interrupt wake-up has not occurred
#0
1
PWM interrupt wake-up has occurred
#1
TIMER2_PWMTRGCTL
TIMER2_PWMTRGCTL
Timer2 PWM Trigger Control Register
0x68
read-write
n
0x0
0x0
PWMTRGDAC
PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
8
1
read-write
0
PWM trigger DAC Disabled
#0
1
PWM trigger DAC Enabled
#1
PWMTRGEADC
PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
7
1
read-write
0
PWM counter event trigger EADC conversion Disabled
#0
1
PWM counter event trigger EADC conversion Enabled
#1
PWMTRGPDMA
PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
9
1
read-write
0
PWM trigger PDMA Disabled
#0
1
PWM trigger PDMA Enabled
#1
TRGSEL
PWM Counter Event Source Select to Trigger Conversion
0
2
read-write
0
Trigger conversion at period point (PIF)
#00
1
Trigger conversion at compare up count point (CMPUIF)
#01
2
Trigger conversion at period or compare up count point (PIF or CMPUIF)
#10
3
Reserved.
#11
TIMER2_TRGCTL
TIMER2_TRGCTL
Timer2 Trigger Control Register
0x1C
read-write
n
0x0
0x0
TRGDAC
Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
3
1
read-write
0
Timer interrupt trigger DAC Disabled
#0
1
Timer interrupt trigger DAC Enabled
#1
TRGEADC
Trigger EADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
2
1
read-write
0
Timer interrupt trigger EADC Disabled
#0
1
Timer interrupt trigger EADC Enabled
#1
TRGPDMA
Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
4
1
read-write
0
Timer interrupt trigger PDMA Disabled
#0
1
Timer interrupt trigger PDMA Enabled
#1
TRGPWM
Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM/BPWM counter clock source.
1
1
read-write
0
Timer interrupt trigger PWM/BPWM Disabled
#0
1
Timer interrupt trigger PWM/BPWM Enabled
#1
TRGSSEL
Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
0
1
read-write
0
Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC
#0
1
Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC
#1
TIMER3_CAP
TIMER3_CAP
Timer3 Capture Data Register
0x110
read-write
n
0x0
0x0
TIMER3_CMP
TIMER3_CMP
Timer3 Comparator Register
0x104
read-write
n
0x0
0x0
TIMER3_CNT
TIMER3_CNT
Timer3 Data Register
0x10C
read-write
n
0x0
0x0
TIMER3_CTL
TIMER3_CTL
Timer3 Control Register
0x100
read-write
n
0x0
0x0
TIMER3_EINTSTS
TIMER3_EINTSTS
Timer3 External Interrupt Status Register
0x118
read-write
n
0x0
0x0
TIMER3_EXTCTL
TIMER3_EXTCTL
Timer3 External Control Register
0x114
read-write
n
0x0
0x0
TIMER3_INTSTS
TIMER3_INTSTS
Timer3 Interrupt Status Register
0x108
read-write
n
0x0
0x0
TIMER3_PWMCLKPSC
TIMER3_PWMCLKPSC
Timer3 PWM Counter Clock Pre-scale Register
0x144
read-write
n
0x0
0x0
TIMER3_PWMCMPBUF
TIMER3_PWMCMPBUF
Timer3 PWM Comparator Buffer Register
0x174
read-write
n
0x0
0x0
TIMER3_PWMCMPDAT
TIMER3_PWMCMPDAT
Timer3 PWM Comparator Register
0x150
read-write
n
0x0
0x0
TIMER3_PWMCNT
TIMER3_PWMCNT
Timer3 PWM Counter Register
0x154
read-write
n
0x0
0x0
TIMER3_PWMCNTCLR
TIMER3_PWMCNTCLR
Timer3 PWM Clear Counter Register
0x148
read-write
n
0x0
0x0
TIMER3_PWMCTL
TIMER3_PWMCTL
Timer3 PWM Control Register
0x140
read-write
n
0x0
0x0
TIMER3_PWMINTEN0
TIMER3_PWMINTEN0
Timer3 PWM Interrupt Enable Register 0
0x160
read-write
n
0x0
0x0
TIMER3_PWMINTSTS0
TIMER3_PWMINTSTS0
Timer3 PWM Interrupt Status Register 0
0x164
read-write
n
0x0
0x0
TIMER3_PWMPBUF
TIMER3_PWMPBUF
Timer3 PWM Period Buffer Register
0x170
read-write
n
0x0
0x0
TIMER3_PWMPERIOD
TIMER3_PWMPERIOD
Timer3 PWM Period Register
0x14C
read-write
n
0x0
0x0
TIMER3_PWMPOCTL
TIMER3_PWMPOCTL
Timer3 PWM Pin Output Control Register
0x15C
read-write
n
0x0
0x0
TIMER3_PWMPOLCTL
TIMER3_PWMPOLCTL
Timer3 PWM Pin Output Polar Control Register
0x158
read-write
n
0x0
0x0
TIMER3_PWMSTATUS
TIMER3_PWMSTATUS
Timer3 PWM Status Register
0x16C
read-write
n
0x0
0x0
TIMER3_PWMTRGCTL
TIMER3_PWMTRGCTL
Timer3 PWM Trigger Control Register
0x168
read-write
n
0x0
0x0
TIMER3_TRGCTL
TIMER3_TRGCTL
Timer3 Trigger Control Register
0x11C
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x4C
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Error! Reference source not found..
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Error! Reference source not found..
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the PARITY bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
1
LIN function
#001
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
LINIF
LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
7
1
read-write
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated.
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINCTL
UART_LINCTL
UART LIN Control Register
0x34
read-write
n
0x0
0x0
BITERREN
Bit Error Detect Enable Bit
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection function Enabled
#1
BRKDETEN
LIN Break Detection Enable Bit
10
1
read-write
0
LIN break detection Disabled
#0
1
LIN break detection Enabled
#1
BRKFL
LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.
16
4
read-write
BSL
LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1-bit time
#00
1
The LIN break/sync delimiter length is 2-bit time
#01
2
The LIN break/sync delimiter length is 3-bit time
#10
3
The LIN break/sync delimiter length is 4-bit time
#11
HSEL
LIN Header Select
22
2
read-write
0
The LIN header includes 'break field'
#00
1
The LIN header includes 'break field' and 'sync field'
#01
2
The LIN header includes 'break field', 'sync field' and 'frame ID field'
#10
3
Reserved.
#11
IDPEN
LIN ID Parity Enable Bit
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LINRXOFF
LIN Receiver Disable Bit
11
1
read-write
0
LIN receiver Enabled
#0
1
LIN receiver Disabled
#1
MUTE
LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in Error! Reference source not found. (LIN slave mode).
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
PID
LIN PID Bits\nIf the parity generated by hardware, user fill ID0~ID5 (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
SENDH
LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).\nNote2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
SLVAREN
LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in Error! Reference source not found. (Slave mode with automatic resynchronization).
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
SLVDUEN
LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in Error! Reference source not found. (Slave mode with automatic resynchronization).
3
1
read-write
0
UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time)
#0
1
UART_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
SLVEN
LIN Slave Mode Enable Bit
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
SLVHDEN
LIN Slave Header Detection Enable Bit
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_LINSTS
UART_LINSTS
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BITEF
Bit Error Detect Status Flag \nAt TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
9
1
read-write
0
Bit error not detected
#0
1
Bit error detected
#1
BRKDETF
LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
8
1
read-write
0
LIN break not detected
#0
1
LIN break detected
#1
SLVHDETF
LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not.
0
1
read-write
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
SLVHEF
LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', 'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'.
1
1
read-write
0
LIN header error not detected
#0
1
LIN header error detected
#1
SLVIDPEF
LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.
2
1
read-write
0
No active
#0
1
Receipted frame ID parity is not correct
#1
SLVSYNCF
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit can be cleared by writing 1 to it.\nNote3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Error! Reference source not found. and Error! Reference source not found. for UART function mode.\nNote2: Refer to Error! Reference source not found. and Error! Reference source not found. for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART1
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Error! Reference source not found..
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Error! Reference source not found..
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the PARITY bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
1
LIN function
#001
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
LINIF
LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
7
1
read-write
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Error! Reference source not found. and Error! Reference source not found. for UART function mode.\nNote2: Refer to Error! Reference source not found. and Error! Reference source not found. for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UART2
UART Register Map
UART
0x0
0x0
0x30
registers
n
0x3C
0x10
registers
n
UART_ALTCTL
UART_ALTCTL
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ABRDBITS
Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit.
19
2
read-write
0
1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01
#00
1
2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02
#01
2
4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08
#10
3
8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80
#11
ABRDEN
Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished.
18
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
ABRIF
Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
17
1
read-only
0
No auto-baud rate interrupt flag is generated
#0
1
Auto-baud rate interrupt flag is generated
#1
ADDRDEN
RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
ADDRMV
Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
BRKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.
0
4
read-write
LINRXEN
LIN RX Enable Bit
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LINTXEN
LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485AUD
RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation function (AUD) Disabled
#0
1
RS-485 Auto Direction Operation function (AUD) Enabled
#1
RS485NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UART_BAUD
UART_BAUD
UART Baud Rate Divider Register
0x24
read-write
n
0x0
0x0
BAUDM0
BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..
28
1
read-write
BAUDM1
BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Error! Reference source not found..\nNote: In IrDA mode must be operated in mode 0.
29
1
read-write
BRD
Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Error! Reference source not found..
0
16
read-write
EDIVM1
Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Error! Reference source not found..
24
4
read-write
UART_BRCOMP
UART_BRCOMP
UART Baud Rate Compensation Register
0x3C
read-write
n
0x0
0x0
BRCOMP
Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not. \nBRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the PARITY bit.
0
9
read-write
BRCOMPDEC
Baud Rate Compensation Decrease
31
1
read-write
0
Positive (increase one module clock) compensation for each compensated bit
#0
1
Negative (decrease one module clock) compensation for each compensated bit
#1
UART_DAT
UART_DAT
UART Receive/Transmit Buffer Register
0x0
read-write
n
0x0
0x0
DAT
Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.\nRead Operation:\nBy reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
0
8
read-write
PARITY
PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit, the PARITY bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.\nRead Operation:\nIf PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit.\nNote: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
8
1
read-write
UART_DWKCOMP
UART_DWKCOMP
UART Incoming Data Wake-up Compensation Register
0x48
read-write
n
0x0
0x0
STCOMP
START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
0
16
read-write
UART_FIFO
UART_FIFO
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
4
4
read-write
0
RX FIFO Interrupt Trigger Level is 1 byte
#0000
1
RX FIFO Interrupt Trigger Level is 4 bytes
#0001
2
RX FIFO Interrupt Trigger Level is 8 bytes
#0010
3
RX FIFO Interrupt Trigger Level is 14 bytes
#0011
RTSTRGLV
nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control.
16
4
read-write
0
nRTS Trigger Level is 1 byte
#0000
1
nRTS Trigger Level is 4 bytes
#0001
2
nRTS Trigger Level is 8 bytes
#0010
3
nRTS Trigger Level is 14 bytes
#0011
RXOFF
Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
RXRST
RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
TXRST
TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UART_FIFOSTS
UART_FIFOSTS
UART FIFO Status Register
0x18
read-write
n
0x0
0x0
ABRDIF
Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Auto-baud rate detect function is not finished
#0
1
Auto-baud rate detect function is finished
#1
ABRDTOIF
Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Auto-baud rate counter is underflow
#0
1
Auto-baud rate counter is overflow
#1
ADDRDETF
RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Receiver detects a data that is not an address bit (bit 9 ='0')
#0
1
Receiver detects a data that is an address bit (bit 9 ='1')
#1
BIF
Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' to it.
6
1
read-write
0
No Break interrupt is generated
#0
1
Break interrupt is generated
#1
FEF
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to it.
5
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PEF
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it.
4
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXEMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
0
RX FIFO is not empty
#0
1
RX FIFO is empty
#1
RXFULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
15
1
read-only
0
RX FIFO is not full
#0
1
RX FIFO is full
#1
RXIDLE
RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle.
29
1
read-only
0
RX is busy
#0
1
RX is idle. (Default)
#1
RXOVIF
RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
RX FIFO is not overflow
#0
1
RX FIFO is overflow
#1
RXPTR
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
8
6
read-only
TXEMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UART_DAT (TX FIFO not empty).
22
1
read-only
0
TX FIFO is not empty
#0
1
TX FIFO is empty
#1
TXEMPTYF
Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
0
TX FIFO is not empty or the STOP bit of the last byte has been not transmitted
#0
1
TX FIFO is empty and the STOP bit of the last byte has been transmitted
#1
TXFULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
23
1
read-only
0
TX FIFO is not full
#0
1
TX FIFO is full
#1
TXOVIF
TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
24
1
read-write
0
TX FIFO is not overflow
#0
1
TX FIFO is overflow
#1
TXPTR
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
16
6
read-only
TXRXACT
TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. The UART controller can not transmit or receive data at this moment. Otherwise this bit is set.
31
1
read-only
0
TX and RX are inactive
#0
1
TX and RX are active. (Default)
#1
UART_FUNCSEL
UART_FUNCSEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUNCSEL
Function Select
0
3
read-write
0
UART function
#000
1
LIN function
#001
2
IrDA function
#010
3
RS-485 function
#011
4
UART Single-wire function
#100
TXRXDIS
TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set. The TX and RX compelet current task before disable TX and RX. When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
3
1
read-write
0
TX and RX Enabled
#0
1
TX and RX Disabled
#1
UART_INTEN
UART_INTEN
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
18
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
ATOCTSEN
nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
ATORTSEN
nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
BUFERRIEN
Buffer Error Interrupt Enable Bit
5
1
read-write
0
Buffer error interrupt Disabled
#0
1
Buffer error interrupt Enabled
#1
LINIEN
LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode.
8
1
read-write
0
LIN bus interrupt Disabled
#0
1
LIN bus interrupt Enabled
#1
MODEMIEN
Modem Status Interrupt Enable Bit
3
1
read-write
0
Modem status interrupt Disabled
#0
1
Modem status interrupt Enabled
#1
RDAIEN
Receive Data Available Interrupt Enable Bit
0
1
read-write
0
Receive data available interrupt Disabled
#0
1
Receive data available interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit
2
1
read-write
0
Receive Line Status interrupt Disabled
#0
1
Receive Line Status interrupt Enabled
#1
RXPDMAEN
RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
15
1
read-write
0
RX PDMA Disabled
#0
1
RX PDMA Enabled
#1
RXTOIEN
RX Time-out Interrupt Enable Bit
4
1
read-write
0
RX time-out interrupt Disabled
#0
1
RX time-out interrupt Enabled
#1
SWBEIEN
Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
16
1
read-write
0
Single-wire Bit Error Detect Inerrupt Disabled
#0
1
Single-wire Bit Error Detect Inerrupt Enabled
#1
THREIEN
Transmit Holding Register Empty Interrupt Enable Bit
1
1
read-write
0
Transmit holding register empty interrupt Disabled
#0
1
Transmit holding register empty interrupt Enabled
#1
TOCNTEN
Receive Buffer Time-out Counter Enable Bit
11
1
read-write
0
Receive Buffer Time-out counter Disabled
#0
1
Receive Buffer Time-out counter Enabled
#1
TXENDIEN
Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
22
1
read-write
0
Transmitter empty interrupt Disabled
#0
1
Transmitter empty interrupt Enabled
#1
TXPDMAEN
TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue.
14
1
read-write
0
TX PDMA Disabled
#0
1
TX PDMA Enabled
#1
WKIEN
Wake-up Interrupt Enable Bit
6
1
read-write
0
Wake-up Interrupt Disabled
#0
1
Wake-up Interrupt Enabled
#1
UART_INTSTS
UART_INTSTS
UART Interrupt Status Register
0x1C
read-write
n
0x0
0x0
ABRINT
Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
31
1
read-only
0
No Auto-baud Rate interrupt is generated
#0
1
The Auto-baud Rate interrupt is generated
#1
BUFERRIF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
5
1
read-only
0
No buffer error interrupt flag is generated
#0
1
Buffer error interrupt flag is generated
#1
BUFERRINT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
HWBUFEIF
PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
21
1
read-only
0
No buffer error interrupt flag is generated in PDMA mode
#0
1
Buffer error interrupt flag is generated in PDMA mode
#1
HWBUFEINT
PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
29
1
read-only
0
No buffer error interrupt is generated in PDMA mode
#0
1
Buffer error interrupt is generated in PDMA mode
#1
HWMODIF
PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
19
1
read-only
0
No Modem interrupt flag is generated in PDMA mode
#0
1
Modem interrupt flag is generated in PDMA mode
#1
HWMODINT
PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
27
1
read-only
0
No Modem interrupt is generated in PDMA mode
#0
1
Modem interrupt is generated in PDMA mode
#1
HWRLSIF
PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
18
1
read-only
0
No RLS interrupt flag is generated in PDMA mode
#0
1
RLS interrupt flag is generated in PDMA mode
#1
HWRLSINT
PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
26
1
read-only
0
No RLS interrupt is generated in PDMA mode
#0
1
RLS interrupt is generated in PDMA mode
#1
HWTOIF
PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
20
1
read-only
0
No RX time-out interrupt flag is generated in PDMA mode
#0
1
RX time-out interrupt flag is generated in PDMA mode
#1
HWTOINT
PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
28
1
read-only
0
No RX time-out interrupt is generated in PDMA mode
#0
1
RX time-out interrupt is generated in PDMA mode
#1
LINIF
LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]).
7
1
read-write
0
None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#0
1
At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated
#1
LININT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEMIF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
3
1
read-only
0
No Modem interrupt flag is generated
#0
1
Modem interrupt flag is generated
#1
MODEMINT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDAIF
Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
0
1
read-write
0
No RDA interrupt flag is generated
#0
1
RDA interrupt flag is generated
#1
RDAINT
Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLSIF
Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
2
1
read-only
0
No RLS interrupt flag is generated
#0
1
RLS interrupt flag is generated
#1
RLSINT
Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
RXTOIF
RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
4
1
read-only
0
No RX time-out interrupt flag is generated
#0
1
RX time-out interrupt flag is generated
#1
RXTOINT
RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
12
1
read-only
0
No RX time-out interrupt is generated
#0
1
RX time-out interrupt is generated
#1
SWBEIF
Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.\nNote2: This bit can be cleared by writing '1' to it.
16
1
read-write
0
No single-wire bit error detection interrupt flag is generated
#0
1
Single-wire bit error detection interrupt flag is generated
#1
SWBEINT
Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
24
1
read-only
0
No Single-wire Bit Error Detection Interrupt generated
#0
1
Single-wire Bit Error Detection Interrupt generated
#1
THREIF
Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
1
1
read-write
0
No THRE interrupt flag is generated
#0
1
THRE interrupt flag is generated
#1
THREINT
Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TXENDIF
Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
22
1
read-write
0
No transmitter empty interrupt flag is generated
#0
1
Transmitter empty interrupt flag is generated
#1
TXENDINT
Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
30
1
read-only
0
No Transmitter Empty interrupt is generated
#0
1
Transmitter Empty interrupt is generated
#1
WKIF
UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
6
1
read-only
0
No UART wake-up interrupt flag is generated
#0
1
UART wake-up interrupt flag is generated
#1
WKINT
UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
14
1
read-only
0
No UART wake-up interrupt is generated
#0
1
UART wake-up interrupt is generated
#1
UART_IRDA
UART_IRDA
UART IrDA Control Register
0x28
read-write
n
0x0
0x0
RXINV
IrDA Inverse Receive Input Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
6
1
read-write
0
None inverse receiving input signal
#0
1
Inverse receiving input signal. (Default)
#1
TXEN
IrDA Receiver/Transmitter Selection Enable Bit
1
1
read-write
0
IrDA Transmitter Disabled and Receiver Enabled. (Default)
#0
1
IrDA Transmitter Enabled and Receiver Disabled
#1
TXINV
IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
5
1
read-write
0
None inverse transmitting signal. (Default)
#0
1
Inverse transmitting output signal
#1
UART_LINE
UART_LINE
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nNote: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
6
1
read-write
0
Break Control Disabled
#0
1
Break Control Enabled
#1
EPE
Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP Bit'
2
1
read-write
0
One 'STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data.
3
1
read-write
0
PARITY bit generated Disabled
#0
1
PARITY bit generated Enabled
#1
PSS
PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0, the PARITY bit is transmitted and checked automatically. If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]).
7
1
read-write
0
PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically
#0
1
PARITY bit generated and checked by software
#1
RXDINV
RX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
9
1
read-write
0
Received data signal inverted Disabled
#0
1
Received data signal inverted Enabled
#1
SPE
Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1.
5
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
TXDINV
TX Data Inverted\nNote1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.\nNote2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
8
1
read-write
0
Transmitted data signal inverted Disabled
#0
1
Transmitted data signal inverted Enabled
#1
WLS
Word Length Selection\nThis field sets UART word length.
0
2
read-write
0
5 bits
#00
1
6 bits
#01
2
7 bits
#10
3
8 bits
#11
UART_MODEM
UART_MODEM
UART Modem Control Register
0x10
read-write
n
0x0
0x0
RTS
nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.\nNote3: Single-wire mode is support this feature.
1
1
read-write
0
nRTS signal is active
#0
1
nRTS signal is inactive
#1
RTSACTLV
nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Error! Reference source not found. and Error! Reference source not found. for UART function mode.\nNote2: Refer to Error! Reference source not found. and Error! Reference source not found. for RS-485 function mode.\nNote3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
9
1
read-write
0
nRTS pin output is high level active
#0
1
nRTS pin output is low level active. (Default)
#1
RTSSTS
nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
13
1
read-only
0
nRTS pin output is low level voltage logic state
#0
1
nRTS pin output is high level voltage logic state
#1
UART_MODEMSTS
UART_MODEMSTS
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTSACTLV
nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
8
1
read-write
0
nCTS pin input is high level active
#0
1
nCTS pin input is low level active. (Default)
#1
CTSDETF
Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it.
0
1
read-write
0
nCTS input has not change state
#0
1
nCTS input has change state
#1
CTSSTS
nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
4
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
UART_TOUT
UART_TOUT
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit. The unit is bit time.
8
8
read-write
TOIC
Time-out Interrupt Comparator
0
8
read-write
UART_WKCTL
UART_WKCTL
UART Wake-up Control Register
0x40
read-write
n
0x0
0x0
WKCTSEN
nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode.
0
1
read-write
0
nCTS Wake-up system function Disabled
#0
1
nCTS Wake-up system function Enabled
#1
WKDATEN
Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
1
1
read-write
0
Incoming data wake-up system function Disabled
#0
1
Incoming data wake-up system function Enabled
#1
WKRFRTEN
Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode.
2
1
read-write
0
Received Data FIFO reached threshold wake-up system function Disabled
#0
1
Received Data FIFO reached threshold wake-up system function Enabled
#1
WKRS485EN
RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in Power-down mode, RS-485 Address Match will wake up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
3
1
read-write
0
RS-485 Address Match (AAD mode) wake-up system function Disabled
#0
1
RS-485 Address Match (AAD mode) wake-up system function Enabled
#1
WKTOUTEN
Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
4
1
read-write
0
Received Data FIFO reached threshold time-out wake-up system function Disabled
#0
1
Received Data FIFO reached threshold time-out wake-up system function Enabled
#1
UART_WKSTS
UART_WKSTS
UART Wake-up Status Register
0x44
read-write
n
0x0
0x0
CTSWKF
nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
0
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by nCTS wake-up
#1
DATWKF
Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
1
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Incoming Data wake-up
#1
RFRTWKF
Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
2
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up
#1
RS485WKF
RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
3
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up
#1
TOUTWKF
Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it.
4
1
read-write
0
Chip stays in power-down state
#0
1
Chip wake-up from power-down state by Received Data FIFO reached threshold time-out
#1
UI2C0
UI2CI2C Register Map
UI2CI2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software sets 10'h000, the address can not be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.
16
9
read-write
STCTL
Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UI2C1
UI2CI2C Register Map
UI2CI2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software sets 10'h000, the address can not be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.
16
9
read-write
STCTL
Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UI2C2
UI2CI2C Register Map
UI2CI2C
0x0
0x0
0x4
registers
n
0x2C
0xC
registers
n
0x44
0x24
registers
n
0x8
0x4
registers
n
0x88
0x8
registers
n
UI2C_ADDRMSK0
UI2C_ADDRMSK0
USCI Device Address Mask Register 0
0x4C
read-write
n
0x0
0x0
ADDRMSK
USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
0
10
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
UI2C_ADDRMSK1
UI2C_ADDRMSK1
USCI Device Address Mask Register 1
0x50
read-write
n
0x0
0x0
UI2C_ADMAT
UI2C_ADMAT
I2C Slave Match Address Register
0x88
read-write
n
0x0
0x0
ADMAT0
USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
0
1
read-write
ADMAT1
USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
1
1
read-write
UI2C_BRGEN
UI2C_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK = fDIV_CLK
#00
1
fSAMP_CLK = fPROT_CLK
#01
2
fSAMP_CLK = fSCLK
#10
3
fSAMP_CLK = fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter is Disabled
#0
1
Time measurement counter is Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
UI2C_CTL
UI2C_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UI2C_DEVADDR0
UI2C_DEVADDR0
USCI Device Address Register 0
0x44
read-write
n
0x0
0x0
DEVADDR
Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software sets 10'h000, the address can not be used.
0
10
read-write
UI2C_DEVADDR1
UI2C_DEVADDR1
USCI Device Address Register 1
0x48
read-write
n
0x0
0x0
UI2C_LINECTL
UI2C_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UI2C_PROTCTL
UI2C_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AA
Assert Acknowledge Control
1
1
read-write
ADDR10EN
Address 10-bit Function Enable Bit
4
1
read-write
0
Address match 10 bit function Disabled
#0
1
Address match 10 bit function Enabled
#1
GCFUNC
General Call Function
0
1
read-write
0
General Call Function Disabled
#0
1
General Call Function Enabled
#1
MONEN
Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
9
1
read-write
0
The monitor mode Disabled
#0
1
The monitor mode Enabled
#1
PROTEN
I2C Protocol Enable Bit
31
1
read-write
0
I2C Protocol Disabled
#0
1
I2C Protocol Enabled
#1
PTRG
I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
5
1
write-only
0
I2C's stretch disabled and the I2C protocol function will go ahead
#0
1
I2C's stretch active
#1
SCLOUTEN
SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
8
1
read-write
0
SCL output will be forced high due to open drain mechanism
#0
1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
#1
STA
I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
3
1
read-write
STO
I2C STOP Control
2
1
read-write
TOCNT
Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
16
10
read-write
UI2C_PROTIEN
UI2C_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ACKIEN
Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
6
1
read-write
0
The acknowledge interrupt Disabled
#0
1
The acknowledge interrupt Enabled
#1
ARBLOIEN
Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
4
1
read-write
0
The arbitration lost interrupt Disabled
#0
1
The arbitration lost interrupt Enabled
#1
ERRIEN
Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
5
1
read-write
0
The error interrupt Disabled
#0
1
The error interrupt Enabled
#1
NACKIEN
Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
3
1
read-write
0
The non - acknowledge interrupt Disabled
#0
1
The non - acknowledge interrupt Enabled
#1
STARIEN
START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
1
1
read-write
0
The start condition interrupt Disabled
#0
1
The start condition interrupt Enabled
#1
STORIEN
STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
2
1
read-write
0
The stop condition interrupt Disabled
#0
1
The stop condition interrupt Enabled
#1
TOIEN
Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
0
1
read-write
0
The time-out interrupt Disabled
#0
1
The time-out interrupt Enabled
#1
UI2C_PROTSTS
UI2C_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ACKIF
Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
13
1
read-write
0
An acknowledge has not been received
#0
1
An acknowledge has been received
#1
ARBLOIF
Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
11
1
read-write
0
An arbitration has not been lost
#0
1
An arbitration has been lost
#1
BUSHANG
Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
18
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is hang-up status for transmission
#1
ERRARBLO
Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
19
1
read-write
0
The bus is normal status for transmission
#0
1
The bus is error arbitration lost status for transmission
#1
ERRIF
Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
12
1
read-write
0
An I2C error has not been detected
#0
1
An I2C error has been detected
#1
NACKIF
Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
10
1
read-write
0
A non - acknowledge has not been received
#0
1
A non - acknowledge has been received
#1
ONBUSY
On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
6
1
read-write
0
The bus is IDLE (both SCLK and SDA High)
#0
1
The bus is busy
#1
SLAREAD
Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
15
1
read-write
0
A slave R/W bit is 1 has not been detected
#0
1
A slave R/W bit is 1 has been detected
#1
SLASEL
Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
14
1
read-write
0
The device is not selected as slave
#0
1
The device is selected as slave
#1
STARIF
Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit.
8
1
read-write
0
A start condition has not yet been detected
#0
1
A start condition has been detected
#1
STORIF
Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.
9
1
read-write
0
A stop condition has not yet been detected
#0
1
A stop condition has been detected
#1
TOIF
Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
5
1
read-write
0
A time-out interrupt status has not occurred
#0
1
A time-out interrupt status has occurred
#1
WKAKDONE
Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
16
1
read-write
0
The ACK bit cycle of address match frame isn't done
#0
1
The ACK bit cycle of address match frame is done in power-down
#1
WRSTSWK
Read/Write Status Bit in Address Wake-up Frame
17
1
read-write
0
Write command is recorded on the address match wake-up frame
#0
1
Read command is recorded on the address match wake-up frame
#1
UI2C_RXDAT
UI2C_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
0
16
read-only
UI2C_TMCTL
UI2C_TMCTL
I2C Timing Configure Control Register
0x8C
read-write
n
0x0
0x0
HTCTL
Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.
16
9
read-write
STCTL
Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
0
9
read-write
UI2C_TXDAT
UI2C_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UI2C_WKCTL
UI2C_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
WKADDREN
Wake-up Address Match Enable Bit
1
1
read-write
0
The chip is woken up according to data toggle
#0
1
The chip is woken up according to address match
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UI2C_WKSTS
UI2C_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USBD
USBD Register Map
USBD
0x0
0x0
0x1C
registers
n
0x20
0x8
registers
n
0x500
0xC0
registers
n
0x88
0xC
registers
n
ATTR
USBD_ATTR
USB Device Bus Status and Attribution Register
0x10
read-write
n
0x0
0x0
BYTEM
CPU Access USB SRAM Size Mode Selection
10
1
read-write
0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#0
1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
#1
DPPUEN
Pull-up Resistor on USB_DP Enable Bit
8
1
read-write
0
Pull-up resistor in USB_D+ bus Disabled
#0
1
Pull-up resistor in USB_D+ bus Active
#1
L1RESUME
LPM L1 Resume (Read Only)
13
1
read-only
0
Bus no LPM L1 state resume
#0
1
LPM L1 state resume from LPM L1 state suspend
#1
L1SUSPEND
LPM L1 Suspend (Read Only)
12
1
read-only
0
Bus no L1 state suspend
#0
1
This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged
#1
LPMACK
LPM Token Acknowledge Enable Bit
11
1
read-write
0
the valid LPM Token will be NYET
#0
1
the valid LPM Token will be ACK
#1
PHYEN
PHY Transceiver Function Enable Bit
4
1
read-write
0
PHY transceiver function Disabled
#0
1
PHY transceiver function Enabled
#1
PWRDN
Power-down PHY Transceiver, Low Active
9
1
read-write
0
Power-down related circuit of PHY transceiver
#0
1
Turn-on related circuit of PHY transceiver
#1
RESUME
Resume Status (Read Only)
2
1
read-only
0
No bus resume
#0
1
Resume from suspend
#1
RWAKEUP
Remote Wake-up
5
1
read-write
0
Release the USB bus from K state
#0
1
Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up
#1
SUSPEND
Suspend Status (Read Only)
1
1
read-only
0
Bus no suspend
#0
1
Bus idle more than 3ms, either cable is plugged out or host is sleeping
#1
TOUT
Time-out Status (Read Only)
3
1
read-only
0
No time-out
#0
1
No Bus response more than 18 bits time(
#1
USBEN
USB Controller Enable Bit
7
1
read-write
0
USB Controller Disabled
#0
1
USB Controller Enabled
#1
USBRST
USB Reset Status (Read Only)
0
1
read-only
0
Bus no reset
#0
1
Bus reset when SE0 (single-ended 0) more than 2.5us
#1
BUFSEG0
USBD_BUFSEG0
Endpoint 0 Buffer Segmentation Register
0x500
read-write
n
0x0
0x0
BUFSEG
Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSBD_SRAM address + { BUFSEG, 3'b000}\nRefer to the section Error! Reference source not found. for the endpoint SRAM structure and its description.
3
6
read-write
BUFSEG1
USBD_BUFSEG1
Endpoint 1 Buffer Segmentation Register
0x510
read-write
n
0x0
0x0
BUFSEG10
USBD_BUFSEG10
Endpoint 10 Buffer Segmentation Register
0x5A0
read-write
n
0x0
0x0
BUFSEG11
USBD_BUFSEG11
Endpoint 11 Buffer Segmentation Register
0x5B0
read-write
n
0x0
0x0
BUFSEG2
USBD_BUFSEG2
Endpoint 2 Buffer Segmentation Register
0x520
read-write
n
0x0
0x0
BUFSEG3
USBD_BUFSEG3
Endpoint 3 Buffer Segmentation Register
0x530
read-write
n
0x0
0x0
BUFSEG4
USBD_BUFSEG4
Endpoint 4 Buffer Segmentation Register
0x540
read-write
n
0x0
0x0
BUFSEG5
USBD_BUFSEG5
Endpoint 5 Buffer Segmentation Register
0x550
read-write
n
0x0
0x0
BUFSEG6
USBD_BUFSEG6
Endpoint 6 Buffer Segmentation Register
0x560
read-write
n
0x0
0x0
BUFSEG7
USBD_BUFSEG7
Endpoint 7 Buffer Segmentation Register
0x570
read-write
n
0x0
0x0
BUFSEG8
USBD_BUFSEG8
Endpoint 8 Buffer Segmentation Register
0x580
read-write
n
0x0
0x0
BUFSEG9
USBD_BUFSEG9
Endpoint 9 Buffer Segmentation Register
0x590
read-write
n
0x0
0x0
CFG0
USBD_CFG0
Endpoint 0 Configuration Register
0x508
read-write
n
0x0
0x0
CSTALL
Clear STALL Response
9
1
read-write
0
Disable the device to clear the STALL handshake in setup stage
#0
1
Clear the device to response STALL handshake in setup stage
#1
DSQSYNC
Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit.
7
1
read-write
0
DATA0 PID
#0
1
DATA1 PID
#1
EPNUM
Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint.
0
4
read-write
ISOCH
Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.
4
1
read-write
0
No Isochronous endpoint
#0
1
Isochronous endpoint
#1
STATE
Endpoint State
5
2
read-write
0
Endpoint is Disabled
#00
1
Out endpoint
#01
2
IN endpoint
#10
3
Undefined
#11
CFG1
USBD_CFG1
Endpoint 1 Configuration Register
0x518
read-write
n
0x0
0x0
CFG10
USBD_CFG10
Endpoint 10 Configuration Register
0x5A8
read-write
n
0x0
0x0
CFG11
USBD_CFG11
Endpoint 11 Configuration Register
0x5B8
read-write
n
0x0
0x0
CFG2
USBD_CFG2
Endpoint 2 Configuration Register
0x528
read-write
n
0x0
0x0
CFG3
USBD_CFG3
Endpoint 3 Configuration Register
0x538
read-write
n
0x0
0x0
CFG4
USBD_CFG4
Endpoint 4 Configuration Register
0x548
read-write
n
0x0
0x0
CFG5
USBD_CFG5
Endpoint 5 Configuration Register
0x558
read-write
n
0x0
0x0
CFG6
USBD_CFG6
Endpoint 6 Configuration Register
0x568
read-write
n
0x0
0x0
CFG7
USBD_CFG7
Endpoint 7 Configuration Register
0x578
read-write
n
0x0
0x0
CFG8
USBD_CFG8
Endpoint 8 Configuration Register
0x588
read-write
n
0x0
0x0
CFG9
USBD_CFG9
Endpoint 9 Configuration Register
0x598
read-write
n
0x0
0x0
CFGP0
USBD_CFGP0
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
0x50C
read-write
n
0x0
0x0
CLRRDY
Clear Ready\nWhen the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\nFor IN token, write '1' to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and is always 0 when it is read back.
0
1
read-write
SSTALL
Set STALL
1
1
read-write
0
Disable the device to response STALL
#0
1
Set the device to respond STALL automatically
#1
CFGP1
USBD_CFGP1
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
0x51C
read-write
n
0x0
0x0
CFGP10
USBD_CFGP10
Endpoint 10 Set Stall and Clear In/Out Ready Control Register
0x5AC
read-write
n
0x0
0x0
CFGP11
USBD_CFGP11
Endpoint 11 Set Stall and Clear In/Out Ready Control Register
0x5BC
read-write
n
0x0
0x0
CFGP2
USBD_CFGP2
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
0x52C
read-write
n
0x0
0x0
CFGP3
USBD_CFGP3
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
0x53C
read-write
n
0x0
0x0
CFGP4
USBD_CFGP4
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
0x54C
read-write
n
0x0
0x0
CFGP5
USBD_CFGP5
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
0x55C
read-write
n
0x0
0x0
CFGP6
USBD_CFGP6
Endpoint 6 Set Stall and Clear In/Out Ready Control Register
0x56C
read-write
n
0x0
0x0
CFGP7
USBD_CFGP7
Endpoint 7 Set Stall and Clear In/Out Ready Control Register
0x57C
read-write
n
0x0
0x0
CFGP8
USBD_CFGP8
Endpoint 8 Set Stall and Clear In/Out Ready Control Register
0x58C
read-write
n
0x0
0x0
CFGP9
USBD_CFGP9
Endpoint 9 Set Stall and Clear In/Out Ready Control Register
0x59C
read-write
n
0x0
0x0
EPSTS
USBD_EPSTS
USB Device Endpoint Status Register
0xC
read-only
n
0x0
0x0
OV
Overrun\nIt indicates that the received data is over the maximum payload number or not.
7
1
read-only
0
No overrun
#0
1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes
#1
EPSTS0
USBD_EPSTS0
USB Device Endpoint Status Register 0
0x20
read-only
n
0x0
0x0
EPSTS5
Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint
20
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS6
Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint
24
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS7
Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint
28
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS1
USBD_EPSTS1
USB Device Endpoint Status Register 1
0x24
read-only
n
0x0
0x0
EPSTS10
Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint
8
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS11
Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint
12
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS8
Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint
0
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
EPSTS9
Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint
4
4
read-only
0
In ACK
#0000
1
In NAK
#0001
2
Out Packet Data0 ACK
#0010
3
Setup ACK
#0011
6
Out Packet Data1 ACK
#0110
7
Isochronous transfer end
#0111
FADDR
USBD_FADDR
USB Device Function Address Register
0x8
read-write
n
0x0
0x0
FADDR
USB Device Function Address
0
7
read-write
FN
USBD_FN
USB Frame Number Register
0x8C
read-only
n
0x0
0x0
FN
Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet.
0
11
read-only
INTEN
USBD_INTEN
USB Device Interrupt Enable Register
0x0
read-write
n
0x0
0x0
BUSIEN
Bus Event Interrupt Enable Bit
0
1
read-write
0
BUS event interrupt Disabled
#0
1
BUS event interrupt Enabled
#1
INNAKEN
Active NAK Function and Its Status in IN Token
15
1
read-write
0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1 register, so that the USB interrupt event will not be asserted
#0
1
IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
#1
NEVWKIEN
USB No-event-wake-up Interrupt Enable Bit
3
1
read-write
0
No-event-wake-up Interrupt Disabled
#0
1
No-event-wake-up Interrupt Enabled
#1
SOFIEN
Start of Frame Interrupt Enable Bit
4
1
read-write
0
SOF Interrupt Disabled
#0
1
SOF Interrupt Enabled
#1
USBIEN
USB Event Interrupt Enable Bit
1
1
read-write
0
USB event interrupt Disabled
#0
1
USB event interrupt Enabled
#1
VBDETIEN
VBUS Detection Interrupt Enable Bit
2
1
read-write
0
VBUS detection Interrupt Disabled
#0
1
VBUS detection Interrupt Enabled
#1
WKEN
Wake-up Function Enable Bit\nIf waked up by any change by VBUS state, VBDETIEN must be enabled. If waked up by receiving resume signal, BUSIEN must be enabled.
8
1
read-write
0
USB wake-up function Disabled
#0
1
USB wake-up function Enabled
#1
INTSTS
USBD_INTSTS
USB Device Interrupt Event Status Register
0x4
read-write
n
0x0
0x0
BUSIF
BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.
0
1
read-write
0
No BUS event occurred
#0
1
Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]
#1
EPEVT0
Endpoint 0's USB Event Status
16
1
read-write
0
No event occurred in endpoint 0
#0
1
USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
#1
EPEVT1
Endpoint 1's USB Event Status
17
1
read-write
0
No event occurred in endpoint 1
#0
1
USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
#1
EPEVT10
Endpoint 10's USB Event Status
26
1
read-write
0
No event occurred in endpoint 10
#0
1
USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]
#1
EPEVT11
Endpoint 11's USB Event Status
27
1
read-write
0
No event occurred in endpoint 11
#0
1
USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]
#1
EPEVT2
Endpoint 2's USB Event Status
18
1
read-write
0
No event occurred in endpoint 2
#0
1
USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
#1
EPEVT3
Endpoint 3's USB Event Status
19
1
read-write
0
No event occurred in endpoint 3
#0
1
USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
#1
EPEVT4
Endpoint 4's USB Event Status
20
1
read-write
0
No event occurred in endpoint 4
#0
1
USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
#1
EPEVT5
Endpoint 5's USB Event Status
21
1
read-write
0
No event occurred in endpoint 5
#0
1
USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
#1
EPEVT6
Endpoint 6's USB Event Status
22
1
read-write
0
No event occurred in endpoint 6
#0
1
USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
#1
EPEVT7
Endpoint 7's USB Event Status
23
1
read-write
0
No event occurred in endpoint 7
#0
1
USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
#1
EPEVT8
Endpoint 8's USB Event Status
24
1
read-write
0
No event occurred in endpoint 8
#0
1
USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]
#1
EPEVT9
Endpoint 9's USB Event Status
25
1
read-write
0
No event occurred in endpoint 9
#0
1
USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]
#1
NEVWKIF
No-event-wake-up Interrupt Status
3
1
read-write
0
NEVWK event does not occur
#0
1
No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]
#1
SETUP
Setup Event Status
31
1
read-write
0
No Setup event
#0
1
Setup event occurred, cleared by write 1 to USBD_INTSTS[31]
#1
SOFIF
Start of Frame Interrupt Status
4
1
read-write
0
SOF event does not occur
#0
1
SOF event occurred, cleared by write 1 to USBD_INTSTS[4]
#1
USBIF
USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
1
1
read-write
0
No USB event occurred
#0
1
USB event occurred, check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31])
#1
VBDETIF
VBUS Detection Interrupt Status
2
1
read-write
0
There is not attached/detached event in the USB
#0
1
There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]
#1
LPMATTR
USBD_LPMATTR
USB LPM Attribution Register
0x88
read-only
n
0x0
0x0
LPMBESL
LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token
4
4
read-only
LPMLINKSTS
LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token
0
4
read-only
LPMRWAKUP
LPM Remote Wake-up\nThis bit contains the bRemoteWake value received with last ACK LPM Token
8
1
read-only
MXPLD0
USBD_MXPLD0
Endpoint 0 Maximal Payload Register
0x504
read-write
n
0x0
0x0
MXPLD
Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length receiving from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
0
9
read-write
MXPLD1
USBD_MXPLD1
Endpoint 1 Maximal Payload Register
0x514
read-write
n
0x0
0x0
MXPLD10
USBD_MXPLD10
Endpoint 10 Maximal Payload Register
0x5A4
read-write
n
0x0
0x0
MXPLD11
USBD_MXPLD11
Endpoint 11 Maximal Payload Register
0x5B4
read-write
n
0x0
0x0
MXPLD2
USBD_MXPLD2
Endpoint 2 Maximal Payload Register
0x524
read-write
n
0x0
0x0
MXPLD3
USBD_MXPLD3
Endpoint 3 Maximal Payload Register
0x534
read-write
n
0x0
0x0
MXPLD4
USBD_MXPLD4
Endpoint 4 Maximal Payload Register
0x544
read-write
n
0x0
0x0
MXPLD5
USBD_MXPLD5
Endpoint 5 Maximal Payload Register
0x554
read-write
n
0x0
0x0
MXPLD6
USBD_MXPLD6
Endpoint 6 Maximal Payload Register
0x564
read-write
n
0x0
0x0
MXPLD7
USBD_MXPLD7
Endpoint 7 Maximal Payload Register
0x574
read-write
n
0x0
0x0
MXPLD8
USBD_MXPLD8
Endpoint 8 Maximal Payload Register
0x584
read-write
n
0x0
0x0
MXPLD9
USBD_MXPLD9
Endpoint 9 Maximal Payload Register
0x594
read-write
n
0x0
0x0
SE0
USBD_SE0
USB Device Drive SE0 Control Register
0x90
read-write
n
0x0
0x0
SE0
Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0
1
read-write
0
Normal operation
#0
1
Force USB PHY transceiver to drive SE0
#1
STBUFSEG
USBD_STBUFSEG
SETUP Token Buffer Segmentation Register
0x18
read-write
n
0x0
0x0
STBUFSEG
SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG, 3'b000} \nNote: It is used for SETUP token only.
3
6
read-write
VBUSDET
USBD_VBUSDET
USB Device VBUS Detection Register
0x14
read-only
n
0x0
0x0
VBUSDET
Device VBUS Detection
0
1
read-only
0
Controller is not attached to the USB host
#0
1
Controller is attached to the USB host
#1
USPI0
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under-run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
0
MODE0. The idle state of SPI clock is low level. Data is transmitted with falling edge and received with rising edge
#00
1
MODE1. The idle state of SPI clock is low level. Data is transmitted with rising edge and received with falling edge
#01
2
MODE2. The idle state of SPI clock is high level. Data is transmitted with rising edge and received with falling edge
#10
3
MODE3. The idle state of SPI clock is high level. Data is transmitted with falling edge and received with rising edge
#11
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of SPI_CLK clock cycle\nExample:
8
4
read-write
TSMSEL
Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
0
TSMSEL: Full-duplex SPI
#000
4
TSMSEL: Half-duplex SPI
#100
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data level is 0 if TX under run event occurs
#0
1
The output data level is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under-run event does not occur
#0
1
Slave transmit under-run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USPI1
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under-run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
0
MODE0. The idle state of SPI clock is low level. Data is transmitted with falling edge and received with rising edge
#00
1
MODE1. The idle state of SPI clock is low level. Data is transmitted with rising edge and received with falling edge
#01
2
MODE2. The idle state of SPI clock is high level. Data is transmitted with rising edge and received with falling edge
#10
3
MODE3. The idle state of SPI clock is high level. Data is transmitted with falling edge and received with rising edge
#11
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of SPI_CLK clock cycle\nExample:
8
4
read-write
TSMSEL
Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
0
TSMSEL: Full-duplex SPI
#000
4
TSMSEL: Half-duplex SPI
#100
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data level is 0 if TX under run event occurs
#0
1
The output data level is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under-run event does not occur
#0
1
Slave transmit under-run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
USPI2
USCISPI Register Map
USCISPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
USPI_BRGEN
USPI_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider
16
10
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fDIV_CLK
#00
1
fPROT_CLK
#01
2
fSCLK
#10
3
fREF_CLK
#11
TMCNTEN
Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Time measurement counter Disabled
#0
1
Time measurement counter Enabled
#1
TMCNTSRC
Time Measurement Counter Clock Source Selection
5
1
read-write
0
Time measurement counter with fPROT_CLK
#0
1
Time measurement counter with fDIV_CLK
#1
USPI_BUFCTL
USPI_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared. Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
TXUDRIEN
Slave Transmit Under-run Interrupt Enable Bit
6
1
read-write
0
Transmit under-run interrupt Disabled
#0
1
Transmit under-run interrupt Enabled
#1
USPI_BUFSTS
USPI_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
3
1
read-only
0
A receive buffer overrun event has not been detected
#0
1
A receive buffer overrun event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty and available for the next transmission datum
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
TXUDRIF
Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
11
1
read-only
0
A transmit buffer under-run event has not been detected
#0
1
A transmit buffer under-run event has been detected
#1
USPI_CLKIN
USPI_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_CTL
USPI_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
USPI_CTLIN0
USPI_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_DATIN0
USPI_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
USPI_INTEN
USPI_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
USPI_LINECTL
USPI_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
5
1
read-write
0
Data output values of USCIx_DAT0/1 pins are not inverted
#0
1
Data output values of USCIx_DAT0/1 pins are inverted
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
USPI_PDMACTL
USPI_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
USPI_PROTCTL
USPI_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit
#0
1
Slave select signal will be generated automatically. The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
PROTEN
SPI Protocol Enable Bit
31
1
read-write
0
SPI Protocol Disabled
#0
1
SPI Protocol Enabled
#1
SCLKMODE
Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
6
2
read-write
0
MODE0. The idle state of SPI clock is low level. Data is transmitted with falling edge and received with rising edge
#00
1
MODE1. The idle state of SPI clock is low level. Data is transmitted with rising edge and received with falling edge
#01
2
MODE2. The idle state of SPI clock is high level. Data is transmitted with rising edge and received with falling edge
#10
3
MODE3. The idle state of SPI clock is high level. Data is transmitted with falling edge and received with rising edge
#11
SLAVE
Slave Mode Selection
0
1
read-write
0
Master mode
#0
1
Slave mode
#1
SLV3WIRE
Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
1
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLVTOCNT
Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
16
10
read-write
SS
Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
2
1
read-write
SUSPITV
Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of SPI_CLK clock cycle\nExample:
8
4
read-write
TSMSEL
Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
12
3
read-write
0
TSMSEL: Full-duplex SPI
#000
4
TSMSEL: Half-duplex SPI
#100
TXUDRPOL
Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring.
28
1
read-write
0
The output data level is 0 if TX under run event occurs
#0
1
The output data level is 1 if TX under run event occurs
#1
USPI_PROTIEN
USPI_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
SLVBEIEN
Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
3
1
read-write
0
The Slave mode bit count error interrupt Disabled
#0
1
The Slave mode bit count error interrupt Enabled
#1
SLVTOIEN
Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
2
1
read-write
0
The Slave time-out interrupt Disabled
#0
1
The Slave time-out interrupt Enabled
#1
SSACTIEN
Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
1
1
read-write
0
Slave select active interrupt generation Disabled
#0
1
Slave select active interrupt generation Enabled
#1
SSINAIEN
Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
0
1
read-write
0
Slave select inactive interrupt generation Disabled
#0
1
Slave select inactive interrupt generation Enabled
#1
USPI_PROTSTS
USPI_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
BUSY
Busy Status (Read Only)
17
1
read-only
0
SPI is in idle state
#0
1
SPI is in busy state
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
4
1
read-write
0
Receive end event did not occur
#0
1
Receive end event occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
3
1
read-write
0
Receive start event did not occur
#0
1
Receive start event occurred
#1
SLVBEIF
Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
6
1
read-write
0
Slave bit count error event did not occur
#0
1
Slave bit count error event occurred
#1
SLVTOIF
Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
5
1
read-write
0
Slave time-out event did not occur
#0
1
Slave time-out event occurred
#1
SLVUDR
Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
18
1
read-only
0
Slave transmit under-run event does not occur
#0
1
Slave transmit under-run event occurs
#1
SSACTIF
Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
9
1
read-write
0
The slave select signal has not changed to active
#0
1
The slave select signal has changed to active
#1
SSINAIF
Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
8
1
read-write
0
The slave select signal has not changed to inactive
#0
1
The slave select signal has changed to inactive
#1
SSLINE
Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
16
1
read-only
0
The slave select line status is 0
#0
1
The slave select line status is 1
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
2
1
read-write
0
Transmit end event did not occur
#0
1
Transmit end event occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
1
1
read-write
0
Transmit start event did not occur
#0
1
Transmit start event occurred
#1
USPI_RXDAT
USPI_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.
0
16
read-only
USPI_TXDAT
USPI_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
PORTDIR
Port Direction Control
16
1
write-only
0
The data pin is configured as output mode
#0
1
The data pin is configured as input mode
#1
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
0
16
write-only
USPI_WKCTL
USPI_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
USPI_WKSTS
USPI_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UUART0
UUARTUART Register Map
UUARTUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK is selected to fDIV_CLK
#00
1
fSAMP_CLK is selected to fPROT_CLK
#01
2
fSAMP_CLK is selected to fSCLK
#10
3
fSAMP_CLK is selected to fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit.
3
1
read-only
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
5
1
read-write
0
The value of USCIx_DAT1 is equal to the data shift register
#0
1
The value of USCIx_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
EVENPARITY
Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame.
1
1
read-write
0
The PARITY bit Disabled
#0
1
The PARITY bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
STOP Bits\nThis bit defines the number of STOP bits in an UART frame.
0
1
read-write
0
The number of STOP bits is 1
#0
1
The number of STOP bits is 2
#1
WAKECNT
Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is woken up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.\nNote: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UUART1
UUARTUART Register Map
UUARTUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK is selected to fDIV_CLK
#00
1
fSAMP_CLK is selected to fPROT_CLK
#01
2
fSAMP_CLK is selected to fSCLK
#10
3
fSAMP_CLK is selected to fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit.
3
1
read-only
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
5
1
read-write
0
The value of USCIx_DAT1 is equal to the data shift register
#0
1
The value of USCIx_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
EVENPARITY
Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame.
1
1
read-write
0
The PARITY bit Disabled
#0
1
The PARITY bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
STOP Bits\nThis bit defines the number of STOP bits in an UART frame.
0
1
read-write
0
The number of STOP bits is 1
#0
1
The number of STOP bits is 2
#1
WAKECNT
Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is woken up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.\nNote: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
UUART2
UUARTUART Register Map
UUARTUART
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x28
0x1C
registers
n
0x54
0x14
registers
n
UUART_BRGEN
UUART_BRGEN
USCI Baud Rate Generator Register
0x8
read-write
n
0x0
0x0
CLKDIV
Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
16
10
read-write
DSCNT
Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
10
5
read-write
PDSCNT
Pre-divider for Sample Counter
8
2
read-write
PTCLKSEL
Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
1
1
read-write
0
Reference clock fREF_CLK
#0
1
fREF_CLK2 (its frequency is half of fREF_CLK)
#1
RCLKSEL
Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
0
1
read-write
0
Peripheral device clock fPCLK
#0
1
Reserved.
#1
SPCLKSEL
Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
2
2
read-write
0
fSAMP_CLK is selected to fDIV_CLK
#00
1
fSAMP_CLK is selected to fPROT_CLK
#01
2
fSAMP_CLK is selected to fSCLK
#10
3
fSAMP_CLK is selected to fREF_CLK
#11
TMCNTEN
Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
4
1
read-write
0
Timing measurement counter is Disabled
#0
1
Timing measurement counter is Enabled
#1
TMCNTSRC
Timing Measurement Counter Clock Source Selection
5
1
read-write
0
Timing measurement counter with fPROT_CLK
#0
1
Timing measurement counter with fDIV_CLK
#1
UUART_BUFCTL
UUART_BUFCTL
USCI Transmit/Receive Buffer Control Register
0x38
read-write
n
0x0
0x0
RXCLR
Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
15
1
read-write
0
No effect
#0
1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
RXOVIEN
Receive Buffer Overrun Error Interrupt Enable Bit
14
1
read-write
0
Receive overrun interrupt Disabled
#0
1
Receive overrun interrupt Enabled
#1
RXRST
Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
17
1
read-write
0
No effect
#0
1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
#1
TXCLR
Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
7
1
read-write
0
No effect
#0
1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
#1
TXRST
Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
16
1
read-write
0
No effect
#0
1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
#1
UUART_BUFSTS
UUART_BUFSTS
USCI Transmit/Receive Buffer Status Register
0x3C
read-only
n
0x0
0x0
RXEMPTY
Receive Buffer Empty Indicator
0
1
read-only
0
Receive buffer is not empty
#0
1
Receive buffer is empty
#1
RXFULL
Receive Buffer Full Indicator
1
1
read-only
0
Receive buffer is not full
#0
1
Receive buffer is full
#1
RXOVIF
Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit.
3
1
read-only
0
A receive buffer overrun error event has not been detected
#0
1
A receive buffer overrun error event has been detected
#1
TXEMPTY
Transmit Buffer Empty Indicator
8
1
read-only
0
Transmit buffer is not empty
#0
1
Transmit buffer is empty
#1
TXFULL
Transmit Buffer Full Indicator
9
1
read-only
0
Transmit buffer is not full
#0
1
Transmit buffer is full
#1
UUART_CLKIN
UUART_CLKIN
USCI Input Clock Signal Configuration Register
0x28
read-write
n
0x0
0x0
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_CTL
UUART_CTL
USCI Control Register
0x0
read-write
n
0x0
0x0
FUNMODE
Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
0
3
read-write
0
The USCI is disabled. All protocol related state machines are set to idle state
#000
1
The SPI protocol is selected
#001
2
The UART protocol is selected
#010
4
The I2C protocol is selected
#100
UUART_CTLIN0
UUART_CTLIN0
USCI Input Control Signal Configuration Register 0
0x20
read-write
n
0x0
0x0
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_DATIN0
UUART_DATIN0
USCI Input Data Signal Configuration Register 0
0x10
read-write
n
0x0
0x0
EDGEDET
Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 10.
3
2
read-write
0
The trigger event activation is disabled
#00
1
A rising edge activates the trigger event of input data signal
#01
2
A falling edge activates the trigger event of input data signal
#10
3
Both edges activate the trigger event of input data signal
#11
ININV
Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
2
1
read-write
0
The un-synchronized input signal will not be inverted
#0
1
The un-synchronized input signal will be inverted
#1
SYNCSEL
Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
0
1
read-write
0
The un-synchronized signal can be taken as input for the data shift unit
#0
1
The synchronized signal can be taken as input for the data shift unit
#1
UUART_INTEN
UUART_INTEN
USCI Interrupt Enable Register
0x4
read-write
n
0x0
0x0
RXENDIEN
Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
4
1
read-write
0
The receive end interrupt Disabled
#0
1
The receive end interrupt Enabled
#1
RXSTIEN
Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
3
1
read-write
0
The receive start interrupt Disabled
#0
1
The receive start interrupt Enabled
#1
TXENDIEN
Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
2
1
read-write
0
The transmit finish interrupt Disabled
#0
1
The transmit finish interrupt Enabled
#1
TXSTIEN
Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
1
1
read-write
0
The transmit start interrupt Disabled
#0
1
The transmit start interrupt Enabled
#1
UUART_LINECTL
UUART_LINECTL
USCI Line Control Register
0x2C
read-write
n
0x0
0x0
CTLOINV
Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
7
1
read-write
0
No effect
#0
1
The control signal will be inverted before its output
#1
DATOINV
Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
5
1
read-write
0
The value of USCIx_DAT1 is equal to the data shift register
#0
1
The value of USCIx_DAT1 is the inversion of data shift register
#1
DWIDTH
Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In UART protocol, the length can be configured as 6~13 bits.
8
4
read-write
LSB
LSB First Transmission Selection
0
1
read-write
0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#0
1
The LSB, the bit 0 of data buffer, will be transmitted/received first
#1
UUART_PDMACTL
UUART_PDMACTL
USCI PDMA Control Register
0x40
read-write
n
0x0
0x0
PDMAEN
PDMA Mode Enable Bit
3
1
read-write
0
PDMA function Disabled
#0
1
PDMA function Enabled
#1
PDMARST
PDMA Reset
0
1
read-write
0
No effect
#0
1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
#1
RXPDMAEN
PDMA Receive Channel Available
2
1
read-write
0
Receive PDMA function Disabled
#0
1
Receive PDMA function Enabled
#1
TXPDMAEN
PDMA Transmit Channel Available
1
1
read-write
0
Transmit PDMA function Disabled
#0
1
Transmit PDMA function Enabled
#1
UUART_PROTCTL
UUART_PROTCTL
USCI Protocol Control Register
0x5C
read-write
n
0x0
0x0
ABREN
Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
6
1
read-write
0
Auto-baud rate detect function Disabled
#0
1
Auto-baud rate detect function Enabled
#1
BCEN
Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
29
1
read-write
0
Transmit Break Control Disabled
#0
1
Transmit Break Control Enabled
#1
BRDETITV
Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
16
9
read-write
CTSAUTOEN
nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
4
1
read-write
0
nCTS auto-flow control Disabled
#0
1
nCTS auto-flow control Enabled
#1
CTSWKEN
nCTS Wake-up Mode Enable Bit
10
1
read-write
0
nCTS wake-up mode Disabled
#0
1
nCTS wake-up mode Enabled
#1
DATWKEN
Data Wake-up Mode Enable Bit
9
1
read-write
0
Data wake-up mode Disabled
#0
1
Data wake-up mode Enabled
#1
EVENPARITY
Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
2
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
PARITYEN
Parity Enable Bit\nThis bit defines the PARITY bit is enabled in an UART frame.
1
1
read-write
0
The PARITY bit Disabled
#0
1
The PARITY bit Enabled
#1
PROTEN
UART Protocol Enable Bit
31
1
read-write
0
UART Protocol Disabled
#0
1
UART Protocol Enabled
#1
RTSAUDIREN
nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
5
1
read-write
0
nRTS auto direction control Disabled
#0
1
nRTS auto direction control Enabled
#1
RTSAUTOEN
nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
3
1
read-write
0
nRTS auto-flow control Disabled
#0
1
nRTS auto-flow control Enabled
#1
STICKEN
Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
26
1
read-write
0
Stick parity Disabled
#0
1
Stick parity Enabled
#1
STOPB
STOP Bits\nThis bit defines the number of STOP bits in an UART frame.
0
1
read-write
0
The number of STOP bits is 1
#0
1
The number of STOP bits is 2
#1
WAKECNT
Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (START bit) when the device is woken up from Power-down mode.
11
4
read-write
UUART_PROTIEN
UUART_PROTIEN
USCI Protocol Interrupt Enable Register
0x60
read-write
n
0x0
0x0
ABRIEN
Auto-baud Rate Interrupt Enable Bit
1
1
read-write
0
Auto-baud rate interrupt Disabled
#0
1
Auto-baud rate interrupt Enabled
#1
RLSIEN
Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
2
1
read-write
0
Receive line status interrupt Disabled
#0
1
Receive line status interrupt Enabled
#1
UUART_PROTSTS
UUART_PROTSTS
USCI Protocol Status Register
0x64
read-write
n
0x0
0x0
ABERRSTS
Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
11
1
read-write
0
Auto-baud rate detect counter is not overrun
#0
1
Auto-baud rate detect counter is overrun
#1
ABRDETIF
Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.\nNote: This bit can be cleared by writing '1' to it.
9
1
read-write
0
Auto-baud rate detect function is not done
#0
1
One Bit auto-baud rate detect function is done
#1
BREAK
Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
7
1
read-write
0
No Break is generated
#0
1
Break is generated in the receiver bus
#1
CTSLV
nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
17
1
read-only
0
nCTS pin input is low level voltage logic state
#0
1
nCTS pin input is high level voltage logic state
#1
CTSSYNCLV
nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
16
1
read-only
0
The internal synchronized nCTS is low
#0
1
The internal synchronized nCTS is high
#1
FRMERR
Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
6
1
read-write
0
No framing error is generated
#0
1
Framing error is generated
#1
PARITYERR
Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
5
1
read-write
0
No parity error is generated
#0
1
Parity error is generated
#1
RXBUSY
RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
10
1
read-only
0
The receiver is Idle
#0
1
The receiver is BUSY
#1
RXENDIF
Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
4
1
read-write
0
A receive finish interrupt status has not occurred
#0
1
A receive finish interrupt status has occurred
#1
RXSTIF
Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
3
1
read-write
0
A receive start interrupt status has not occurred
#0
1
A receive start interrupt status has occurred
#1
TXENDIF
Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
2
1
read-write
0
A transmit end interrupt status has not occurred
#0
1
A transmit end interrupt status has occurred
#1
TXSTIF
Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
1
1
read-write
0
A transmit start interrupt status has not occurred
#0
1
A transmit start interrupt status has occurred
#1
UUART_RXDAT
UUART_RXDAT
USCI Receive Data Register
0x34
read-only
n
0x0
0x0
RXDAT
Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
0
16
read-only
UUART_TXDAT
UUART_TXDAT
USCI Transmit Data Register
0x30
write-only
n
0x0
0x0
TXDAT
Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
0
16
write-only
UUART_WKCTL
UUART_WKCTL
USCI Wake-up Control Register
0x54
read-write
n
0x0
0x0
PDBOPT
Power Down Blocking Option
2
1
read-write
0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#0
1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
#1
WKEN
Wake-up Enable Bit
0
1
read-write
0
Wake-up function Disabled
#0
1
Wake-up function Enabled
#1
UUART_WKSTS
UUART_WKSTS
USCI Wake-up Status Register
0x58
read-write
n
0x0
0x0
WKF
Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
0
1
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0xC
registers
n
ALTCTL
WDT_ALTCTL
WDT Alternative Control Register
0x4
read-write
n
0x0
0x0
RSTDSEL
WDT Reset Delay Selection (Write Protect) \nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset happened.
0
2
read-write
0
WDT Reset Delay Period is 1026 * WDT_CLK
#00
1
WDT Reset Delay Period is 130 * WDT_CLK
#01
2
WDT Reset Delay Period is 18 * WDT_CLK
#10
3
WDT Reset Delay Period is 3 * WDT_CLK
#11
CTL
WDT_CTL
WDT Control Register
0x0
read-write
n
0x0
0x0
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
31
1
read-write
0
ICE debug mode acknowledgement affects WDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
IF
WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
3
1
read-write
0
WDT time-out interrupt did not occur
#0
1
WDT time-out interrupt occurred
#1
INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
6
1
read-write
0
WDT time-out interrupt Disabled
#0
1
WDT time-out interrupt Enabled
#1
RSTEN
WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
1
1
read-write
0
WDT time-out reset function Disabled
#0
1
WDT time-out reset function Enabled
#1
RSTF
WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
2
1
read-write
0
WDT time-out reset did not occur
#0
1
WDT time-out reset occurred
#1
SYNC
WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
30
1
read-only
0
Set WDTEN bit is completed
#0
1
Set WDTEN bit is synchronizing and not become active yet
#1
TOUTSEL
WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
8
4
read-write
0
24 * WDT_CLK
#0000
1
26 * WDT_CLK
#0001
2
28 * WDT_CLK
#0010
3
210 * WDT_CLK
#0011
4
212 * WDT_CLK
#0100
5
214 * WDT_CLK
#0101
6
216 * WDT_CLK
#0110
7
218 * WDT_CLK
#0111
8
220 * WDT_CLK
#1000
WDTEN
WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
7
1
read-write
0
WDT Disabled (This action will reset the internal up counter value)
#0
1
WDT Enabled
#1
WKEN
WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WKF
WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is cleared by writing 1 to it.
5
1
read-write
0
WDT does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
RSTCNT
WDT_RSTCNT
WDT Reset Counter Register
0x8
write-only
n
0x0
0x0
RSTCNT
WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
0
32
write-only
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
CNT
WWDT_CNT
WWDT Counter Value Register
0xC
read-only
n
0x0
0x0
CNTDAT
WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
0
6
read-only
CTL
WWDT_CTL
WWDT Control Register
0x4
read-write
n
0x0
0x0
CMPDAT
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
16
6
read-write
ICEDEBUG
ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects WWDT counting
#0
1
ICE debug mode acknowledgement Disabled
#1
INTEN
WWDT Interrupt Enable Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
1
1
read-write
0
WWDT counter compare match interrupt Disabled
#0
1
WWDT counter compare match interrupt Enabled
#1
PSCSEL
WWDT Counter Prescale Period Selection
8
4
read-write
0
Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK
#0000
1
Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK
#0001
2
Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK
#0010
3
Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK
#0011
4
Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK
#0100
5
Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK
#0101
6
Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK
#0110
7
Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK
#0111
8
Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK
#1000
9
Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK
#1001
10
Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK
#1010
11
Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK
#1011
12
Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK
#1100
13
Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK
#1101
14
Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK
#1110
15
Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK
#1111
WWDTEN
WWDT Enable Bit
0
1
read-write
0
WWDT counter is stopped
#0
1
WWDT counter starts counting
#1
RLDCNT
WWDT_RLDCNT
WWDT Reload Counter Register
0x0
write-only
n
0x0
0x0
RLDCNT
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
0
32
write-only
STATUS
WWDT_STATUS
WWDT Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it.
0
1
read-write
0
No effect
#0
1
WWDT counter value matches CMPDAT
#1
WWDTRF
WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
1
1
read-write
0
WWDT time-out reset did not occur
#0
1
WWDT time-out reset occurred
#1