nuvoTon M4521_v1 2024.04.28 M4521_v1 SVD file 8 32 CLK CLK Register Map CLK 0x0 0x0 0x28 registers n 0x40 0x4 registers n 0x50 0x4 registers n 0x60 0x4 registers n 0x70 0x10 registers n AHBCLK CLK_AHBCLK AHB Devices Clock Enable Control Register 0x4 read-write n 0x0 0x0 CRCCKEN CRC Generator Controller Clock Enable Bit 7 1 read-write 0 CRC peripheral clock Disabled #0 1 CRC peripheral clock Enabled #1 EBICKEN EBI Controller Clock Enable Bit 3 1 read-write 0 EBI peripheral clock Disabled #0 1 EBI peripheral clock Enabled #1 FMCIDLE Flash Memory Controller Clock Enable Bit in IDLE Mode 15 1 read-write 0 FMC peripheral clock Disabled when chip operating in IDLE mode #0 1 FMC peripheral clock Enabled when chip operating in IDLE mode #1 ISPCKEN Flash ISP Controller Clock Enable Bit 2 1 read-write 0 Flash ISP peripheral clock Disabled #0 1 Flash ISP peripheral clock Enabled #1 PDMACKEN PDMA Controller Clock Enable Bit 1 1 read-write 0 PDMA peripheral clock Disabled #0 1 PDMA peripheral clock Enabled #1 USBH_EN USB HOST Controller Clock Enable Control 4 1 read-write 0 USB HOST engine clock Disabled #0 1 USB HOST engine clock Enabled #1 APBCLK0 CLK_APBCLK0 APB Devices Clock Enable Control Register 0 0x8 read-write n 0x0 0x0 CLKOCKEN CLKO Clock Enable Bit 6 1 read-write 0 CLKO clock Disabled #0 1 CLKO clock Enabled #1 EADCCKEN Enhanced Analog-digital-converter (EADC) Clock Enable Bit 28 1 read-write 0 EADC clock Disabled #0 1 EADC clock Enabled #1 I2C0CKEN I2C0 Clock Enable Bit 8 1 read-write 0 I2C0 clock Disabled #0 1 I2C0 clock Enabled #1 I2C1CKEN I2C1 Clock Enable Bit 9 1 read-write 0 I2C1 clock Disabled #0 1 I2C1 clock Enabled #1 RTCCKEN Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC). 1 1 read-write 0 RTC APB clock Disabled #0 1 RTC APB clock Enabled #1 SPI0CKEN SPI0 Clock Enable Bit 12 1 read-write 0 SPI0 clock Disabled #0 1 SPI0 clock Enabled #1 SPI1CKEN SPI1 Clock Enable Bit 13 1 read-write 0 SPI1 clock Disabled #0 1 SPI1 clock Enabled #1 TMR0CKEN Timer0 Clock Enable Bit 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1CKEN Timer1 Clock Enable Bit 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2CKEN Timer2 Clock Enable Bit 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3CKEN Timer3 Clock Enable Bit 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0CKEN UART0 Clock Enable Bit 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1CKEN UART1 Clock Enable Bit 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 UART2CKEN UART2 Clock Enable Bit 18 1 read-write 0 UART2 clock Disabled #0 1 UART2 clock Enabled #1 UART3CKEN UART3 Clock Enable Bit 19 1 read-write 0 UART3 clock Disabled #0 1 UART3 clock Enabled #1 USBDCKEN USB Device Clock Enable Bit 27 1 read-write 0 USB Device clock Disabled #0 1 USB Device clock Enabled #1 WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Watchdog timer clock Disabled #0 1 Watchdog timer clock Enabled #1 APBCLK1 CLK_APBCLK1 APB Devices Clock Enable Control Register 1 0xC read-write n 0x0 0x0 PWM0CKEN PWM0 Clock Enable Bit 16 1 read-write 0 PWM0 clock Disabled #0 1 PWM0 clock Enabled #1 PWM1CKEN PWM1 Clock Enable Bit 17 1 read-write 0 PWM1 clock Disabled #0 1 PWM1 clock Enabled #1 SC0CKEN SC0 Clock Enable Bit 0 1 read-write 0 SC0 clock Disabled #0 1 SC0 clock Enabled #1 CDLOWB CLK_CDLOWB Clock Frequency Detector Lower Boundary Register 0x7C read-write n 0x0 0x0 LOWERBD HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CDUPB CLK_CDUPB Clock Frequency Detector Upper Boundary Register 0x78 read-write n 0x0 0x0 UPERBD HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. 0 10 read-write CLKDCTL CLK_CLKDCTL Clock Fail Detector Control Register 0x70 read-write n 0x0 0x0 HXTFDEN HXT Clock Fail Detector Enable Bit 4 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled #1 HXTFIEN HXT Clock Fail Interrupt Enable Bit 5 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled #1 HXTFQDEN HXT Clock Frequency Monitor Enable Bit 16 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled #1 HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit 17 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled #1 LXTFDEN LXT Clock Fail Detector Enable Bit 12 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled #1 LXTFIEN LXT Clock Fail Interrupt Enable Bit 13 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled #1 CLKDIV0 CLK_CLKDIV0 Clock Divider Number Register 0 0x20 read-write n 0x0 0x0 EADCDIV EADC Clock Divide Number From EADC Clock Source 16 8 read-write HCLKDIV HCLK Clock Divide Number From HCLK Clock Source 0 4 read-write UARTDIV UART Clock Divide Number From UART Clock Source 8 4 read-write USBDIV USB Clock Divide Number From PLL Clock 4 4 read-write CLKDIV1 CLK_CLKDIV1 Clock Divider Number Register 1 0x24 read-write n 0x0 0x0 SC0DIV SC0 Clock Divide Number From SC0 Clock Source 0 8 read-write CLKDSTS CLK_CLKDSTS Clock Fail Detector Status Register 0x74 read-write n 0x0 0x0 HXTFIF HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 0 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock stops #1 HXTFQIF HXT Clock Frequency Monitor Interrupt Flag\nNote: Write 1 to clear the bit to 0. 8 1 read-write 0 4~20 MHz external high speed crystal oscillator (HXT) clock is normal #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal #1 LXTFIF LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0. 1 1 read-write 0 32.768 kHz external low speed crystal oscillator (LXT) clock is normal #0 1 32.768 kHz external low speed crystal oscillator (LXT) stops #1 CLKOCTL CLK_CLKOCTL Clock Output Control Register 0x60 read-write n 0x0 0x0 CLK1HZEN Clock Output 1Hz Enable Bit 6 1 read-write 0 1 Hz clock output for 32.768 kHz frequency compensation Disabled #0 1 1 Hz clock output for 32.768 kHz frequency compensation Enabled #1 CLKOEN Clock Output Enable Bit 4 1 read-write 0 Clock Output function Disabled #0 1 Clock Output function Enabled #1 DIV1EN Clock Output Divide One Enable Bit 5 1 read-write 0 Clock Output will output clock with source frequency divided by FREQSEL #0 1 Clock Output will output clock with source frequency #1 FREQSEL Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]. 0 4 read-write CLKSEL0 CLK_CLKSEL0 Clock Source Select Control Register 0 0x10 read-write n 0x0 0x0 HCLKSEL HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from PLL #010 3 Clock source from LIRC #011 7 Clock source from HIRC #111 PCLK0SEL PCLK0 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 APB0 bUS clock source from HCLK #0 1 APB0 bUS clock source from HCLK/2 #1 PCLK1SEL PCLK1 Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 APB1 bUS clock source from HCLK #0 1 APB1 bUS clock source from HCLK/2 #1 STCLKSEL Cortex-M4 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 3 read-write 0 Clock source from HXT #000 1 Clock source from LXT #001 2 Clock source from HXT/2 #010 3 Clock source from HCLK/2 #011 7 Clock source from HIRC/2 #111 USBCKSEL USB Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 USBH and USBD clock source from PLL #0 1 USBH and USBD clock source from HIRC48M #1 CLKSEL1 CLK_CLKSEL1 Clock Source Select Control Register 1 0x14 read-write n 0x0 0x0 CLKOSEL Clock Divider Clock Source Selection 28 2 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 TMR0SEL TIMER0 Clock Source Selection 8 3 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T0 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR1SEL TIMER1 Clock Source Selection 12 3 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK0 #010 3 Clock source from external clock T1 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR2SEL TIMER2 Clock Source Selection 16 3 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T2 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 TMR3SEL TIMER3 Clock Source Selection 20 3 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #000 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #001 2 Clock source from PCLK1 #010 3 Clock source from external clock T3 pin #011 5 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #101 7 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #111 UARTSEL UART Clock Source Selection 24 2 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 WDTSEL Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 2 read-write 0 Reserved. #00 1 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #01 2 Clock source from HCLK/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 WWDTSEL Window Watchdog Timer Clock Source Selection 30 2 read-write 2 Clock source from HCLK/2048 #10 3 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #11 CLKSEL2 CLK_CLKSEL2 Clock Source Select Control Register 2 0x18 read-write n 0x0 0x0 PWM0SEL PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL. 0 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK0 #1 PWM1SEL PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. 1 1 read-write 0 Clock source from PLL #0 1 Clock source from PCLK1 #1 SPI0SEL SPI0 Clock Source Selection 2 2 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 SPI1SEL SPI1 Clock Source Selection 4 2 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK1 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 CLKSEL3 CLK_CLKSEL3 Clock Source Select Control Register 3 0x1C read-write n 0x0 0x0 RTCSEL RTC Clock Source Selection 8 1 read-write 0 Clock source from 32.768 kHz external low speed crystal oscillator (LXT) #0 1 Clock source from 10 kHz internal low speed RC oscillator (LIRC) #1 SC0SEL SC0 Clock Source Selection 0 2 read-write 0 Clock source from 4~20 MHz external high speed crystal oscillator (HXT) #00 1 Clock source from PLL #01 2 Clock source from PCLK0 #10 3 Clock source from 22.1184 MHz internal high speed RC oscillator (HIRC) #11 PLLCTL CLK_PLLCTL PLL Control Register 0x40 read-write n 0x0 0x0 BP PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 17 1 read-write 0 PLL is in normal mode (default) #0 1 PLL clock output is same as PLL input clock FIN #1 FBDIV PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 9 read-write INDIV PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 9 5 read-write OE PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUTDIV PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 14 2 read-write PD Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in Power-down mode (default) #1 PLLSRC PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 19 1 read-write 0 PLL source clock from 4~20 MHz external high-speed crystal oscillator (HXT) #0 1 PLL source clock from 22.1184 MHz internal high-speed oscillator (HIRC) #1 STBSEL PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 23 1 read-write 0 PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz) #0 1 PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz) #1 PWRCTL CLK_PWRCTL System Power-down Control Register 0x0 read-write n 0x0 0x0 HIRC48MEN HIRC48M Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 24 1 read-write 0 48 MHz internal high speed RC oscillator (HIRC48M) Disabled #0 1 48 MHz internal high speed RC oscillator (HIRC48M) Enabled #1 HIRCEN HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled #1 HXTEN HXT Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from HXT, this bit is set to 1 automatically.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 4~20 MHz xxternal high speed crystal (HXT) Disabled #0 1 4~20 MHz external high speed crystal (HXT) Enabled #1 HXTGAIN HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 10 2 read-write 0 HXT frequency is lower than from 8 MHz #00 1 HXT frequency is from 8 MHz to 12 MHz #01 2 HXT frequency is from 12 MHz to 16 MHz #10 3 HXT frequency is higher than 16 MHz #11 HXTSELTYP HXT Crystal Type Select Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 Select INV type #0 1 Select GM type #1 LIRCEN LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 LXTEN LXT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 32.768 kHz external low speed crystal (LXT) Disabled #0 1 32.768 kHz external low speed crystal (LXT) Enabled #1 PDEN System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.\n(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set. (default)\n(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Chip operating normally or chip in idle mode because of WFI command #0 1 Chip enters Power-down mode instant or wait CPU sleep command WFI #1 PDWKDLY Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~20 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PDWKIEN Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 Power-down mode wake-up interrupt Disabled #0 1 Power-down mode wake-up interrupt Enabled #1 PDWKIF Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if the EINT0~5, GPIO, USBD, UART0~3, WDT, BOD, RTC, TMR0~3, I2C0~1 wake-up occurred.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 6 1 read-write PDWTCPU this Bit Control the Power-down Entry Condition (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 Chip enters Power-down mode when the PDEN bit is set to 1 #0 1 Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU runs WFI instruction #1 STATUS CLK_STATUS Clock Status Monitor Register 0x50 read-only n 0x0 0x0 CLKSFAIL Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0. 7 1 read-only 0 Clock switching success #0 1 Clock switching failure #1 HIRCSTB HIRC Clock Source Stable Flag (Read Only) 4 1 read-only 0 22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) clock is stabe and enabled #1 HXTSTB HXT Clock Source Stable Flag (Read Only) 0 1 read-only 0 4~20 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled #0 1 4~20 MHz external high speed crystal oscillator (HXT) clock is stable and enabled #1 LIRCSTB LIRC Clock Source Stable Flag (Read Only) 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled #1 LXTSTB LXT Clock Source Stable Flag (Read Only) 1 1 read-only 0 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled #0 1 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled #1 PLLSTB Internal PLL Clock Source Stable Flag (Read Only) 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable and enabled #1 CRC CRC Register Map CRC 0x0 0x0 0x10 registers n CHECKSUM CRC_CHECKSUM CRC Checksum Register 0xC read-only n 0x0 0x0 CHECKSUM CRC Checksum Results\nThis field indicates the CRC checksum result. 0 32 read-only CTL CRC_CTL CRC Control Register 0x0 read-write n 0x0 0x0 CHKSFMT Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 27 1 read-write 0 1's complement for CRC checksum Disabled #0 1 1's complement for CRC checksum Enabled #1 CHKSREV Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 25 1 read-write 0 Bit order reverse for CRC checksum Disabled #0 1 Bit order reverse for CRC checksum Enabled #1 CRCEN CRC Channel Enable Bit 0 1 read-write 0 No effect #0 1 CRC operation Enabled #1 CRCMODE CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode. 30 2 read-write 0 CRC-CCITT Polynomial mode #00 1 CRC-8 Polynomial mode #01 2 CRC-16 Polynomial mode #10 3 CRC-32 Polynomial mode #11 CRCRST CRC Engine Reset\nNote1: This bit will be cleared automatically.\nNote2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial vale. 1 1 read-write 0 No effect #0 1 Reset the internal CRC state machine. The others contents of CRC_CTL register will not be cleared #1 DATFMT Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register. 26 1 read-write 0 1's complement for CRC writes data in Disabled #0 1 1's complement for CRC writes data in Enabled #1 DATLEN CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 28 2 read-write 0 Data length is 8-bit mode #00 1 Data length is 16-bit mode.\nData length is 32-bit mode #01 DATREV Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data is 0x55DD33BB. 24 1 read-write 0 Bit order reversed for CRC write data in Disabled #0 1 Bit order reversed for CRC write data in Enabled (per byte) #1 DAT CRC_DAT CRC Write Data Register 0x4 read-write n 0x0 0x0 DATA CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 0 32 read-write SEED CRC_SEED CRC Seed Register 0x8 read-write n 0x0 0x0 SEED CRC Seed Value\nThis field indicates the CRC seed value. 0 32 read-write CURSCAT PDMA Register Map PDMA 0x0 0x0 0x4 registers n PDMA_CURSCATn PDMA_CURSCATn Current Scatter-gather Descriptor Table Address of PDMA Channel n 0x0 read-only n 0x0 0x0 CURADDR PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 0 32 read-only DSCT_CTL PDMA Register Map PDMA 0x0 0x0 0x4 registers n PDMA_DSCTn_CTL PDMA_DSCTn_CTL Descriptor Table Control Register of PDMA Channel n 0x0 read-write n 0x0 0x0 BURSIZE Burst Size\nNote: This field is only useful in burst transfer type. 4 3 read-write 0 128 Transfers #000 1 64 Transfers #001 2 32 Transfers #010 3 16 Transfers #011 4 8 Transfers #100 5 4 Transfers #101 6 2 Transfers #110 7 1 Transfers #111 DAINC Destination Address Increment\nThis field is used to set the destination address increment size. 10 2 read-write 3 No increment (fixed address) #11 OPMODE PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 0 2 read-write 0 Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically #00 1 Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[n] will be asserted #01 2 Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute #10 3 Reserved. #11 SAINC Source Address Increment\nThis field is used to set the source address increment size. 8 2 read-write 3 No increment (fixed address) #11 TBINTDIS Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt. \nNote: If this bit set to '1', the TEMPTYF will not be set. 7 1 read-write 0 Table interrupt Enabled #0 1 Table interrupt Disabled #1 TXCNT Transfer Count\nThe TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA finish each transfer data, this field will be decrease immediately. 16 14 read-write TXTYPE Transfer Type 2 1 read-write 0 Burst transfer type #0 1 Single transfer type #1 TXWIDTH Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 12 2 read-write 0 One byte (8 bit) is transferred for every operation #00 1 One half-word (16 bit) is transferred for every operation #01 2 One word (32-bit) is transferred for every operation #10 3 Reserved. #11 DSCT_DA PDMA Register Map PDMA 0x0 0x0 0x4 registers n PDMA_DSCTn_DA PDMA_DSCTn_DA Destination Address Register of PDMA Channel n 0x0 read-write n 0x0 0x0 DA PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller. 0 32 read-write DSCT_NEXT PDMA Register Map PDMA 0x0 0x0 0x4 registers n PDMA_DSCTn_NEXT PDMA_DSCTn_NEXT First Scatter-gather Descriptor Table Offset Address of PDMA Channel n 0x0 read-write n 0x0 0x0 NEXT PDMA Next Descriptor Table Offset Address Register\nThis field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.\nNote1: The next descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 2 14 read-write DSCT_SA PDMA Register Map PDMA 0x0 0x0 0x4 registers n PDMA_DSCTn_SA PDMA_DSCTn_SA Source Address Register of PDMA Channel n 0x0 read-write n 0x0 0x0 SA PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller. 0 32 read-write EADC EADC Register Map EADC 0x0 0x0 0x60 registers n 0x80 0x4C registers n 0xD0 0x40 registers n CMP0 EADC_CMP0 A/D Result Compare Register 0 0xE0 read-write n 0x0 0x0 ADCMPEN A/D Result Compare Enable Bit 0 1 read-write 0 Compare Disabled #0 1 Compare Enabled #1 ADCMPIE A/D Result Compare Interrupt Enable Bit 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPCOND Compare Condition 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one #1 CMPDAT Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 16 12 read-write CMPMCNT Compare Match Count 8 4 read-write CMPSPL Compare Sample Module Selection 3 5 read-write 0 Sample Module 0 conversion result EADC_DAT0 is selected to be compared #00000 1 Sample Module 1 conversion result EADC_DAT1 is selected to be compared #00001 2 Sample Module 2 conversion result EADC_DAT2 is selected to be compared #00010 3 Sample Module 3 conversion result EADC_DAT3 is selected to be compared #00011 4 Sample Module 4 conversion result EADC_DAT4 is selected to be compared #00100 5 Sample Module 5 conversion result EADC_DAT5 is selected to be compared #00101 6 Sample Module 6 conversion result EADC_DAT6 is selected to be compared #00110 7 Sample Module 7 conversion result EADC_DAT7 is selected to be compared #00111 8 Sample Module 8 conversion result EADC_DAT8 is selected to be compared #01000 9 Sample Module 9 conversion result EADC_DAT9 is selected to be compared #01001 10 Sample Module 10 conversion result EADC_DAT10 is selected to be compared #01010 11 Sample Module 11 conversion result EADC_DAT11 is selected to be compared #01011 12 Sample Module 12 conversion result EADC_DAT12 is selected to be compared #01100 13 Sample Module 13 conversion result EADC_DAT13 is selected to be compared #01101 14 Sample Module 14 conversion result EADC_DAT14 is selected to be compared #01110 15 Sample Module 15 conversion result EADC_DAT15 is selected to be compared #01111 16 Sample Module 16 conversion result EADC_DAT16 is selected to be compared #10000 17 Sample Module 17 conversion result EADC_DAT17 is selected to be compared #10001 18 Sample Module 18 conversion result EADC_DAT18 is selected to be compared #10010 CMPWEN Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 15 1 read-write 0 ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched #0 1 ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched #1 CMP1 EADC_CMP1 A/D Result Compare Register 1 0xE4 read-write n 0x0 0x0 CMP2 EADC_CMP2 A/D Result Compare Register 2 0xE8 read-write n 0x0 0x0 CMP3 EADC_CMP3 A/D Result Compare Register 3 0xEC read-write n 0x0 0x0 CTL EADC_CTL A/D Control Register 0x50 read-write n 0x0 0x0 ADCEN A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 ADC Disabled #0 1 ADC Enabled #1 ADCIEN0 Specific Sample Module A/D ADINT0 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 2 1 read-write 0 Specific sample module A/D ADINT0 interrupt function Disabled #0 1 Specific sample module A/D ADINT0 interrupt function Enabled #1 ADCIEN1 Specific Sample Module A/D ADINT1 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion. If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 3 1 read-write 0 Specific sample module A/D ADINT1 interrupt function Disabled #0 1 Specific sample module A/D ADINT1 interrupt function Enabled #1 ADCIEN2 Specific Sample Module A/D ADINT2 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion. If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 4 1 read-write 0 Specific sample module A/D ADINT2 interrupt function Disabled #0 1 Specific sample module A/D ADINT2 interrupt function Enabled #1 ADCIEN3 Specific Sample Module A/D ADINT3 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion. If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 5 1 read-write 0 Specific sample module A/D ADINT3 interrupt function Disabled #0 1 Specific sample module A/D ADINT3 interrupt function Enabled #1 ADCRST ADC A/D Converter Control Circuits Reset\nNote: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 1 1 read-write 0 No effect #0 1 Cause ADC control circuits reset to initial state, but not change the ADC registers value #1 DIFFEN Differential Analog Input Mode Enable Bit 8 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF ADC Differential Input Mode Output Format\nNote: This bit must be set to 0 in single-end analog input mode. 9 1 read-write 0 A/D conversion result will be filled in RESULT (EADC_DATn[15:0], n= 0 ~18) with unsigned format #0 1 A/D conversion result will be filled in RESULT (EADC_DATn[15:0], n= 0 ~18) with 2'complement format #1 PDMAEN PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. 11 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer Enabled #1 SMPTSEL ADC Internal Sampling Time Selection 16 3 read-write 0 1 ADC clock sampling time #000 1 2 ADC clock sampling time #001 2 3 ADC clock sampling time #010 3 4 ADC clock sampling time #011 4 5 ADC clock sampling time #100 5 6 ADC clock sampling time #101 6 7 ADC clock sampling time #110 7 8 ADC clock sampling time #111 CURDAT EADC_CURDAT EADC PDMA Current Transfer Data Register 0x4C read-only n 0x0 0x0 CURDAT ADC PDMA Current Transfer Data Register\nThis is a read only register.\nNOTE: After PDMA read this register, the VAILD of the shadow EADC_DAT register will be automatically cleared. 0 18 read-only DAT0 EADC_DAT0 A/D Data Register 0 for Sample Module 0 0x0 read-only n 0x0 0x0 OV Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read. 16 1 read-only 0 Data in RESULT[11:0] is recent conversion result #0 1 Data in RESULT[11:0] is overwrite #1 RESULT A/D Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. 0 16 read-only VALID Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 17 1 read-only 0 Data in RESULT[11:0] bits is not valid #0 1 Data in RESULT[11:0] bits is valid #1 DAT1 EADC_DAT1 A/D Data Register 1 for Sample Module 1 0x4 read-write n 0x0 0x0 DAT10 EADC_DAT10 A/D Data Register 10 for Sample Module 10 0x28 read-write n 0x0 0x0 DAT11 EADC_DAT11 A/D Data Register 11 for Sample Module 11 0x2C read-write n 0x0 0x0 DAT12 EADC_DAT12 A/D Data Register 12 for Sample Module 12 0x30 read-write n 0x0 0x0 DAT13 EADC_DAT13 A/D Data Register 13 for Sample Module 13 0x34 read-write n 0x0 0x0 DAT14 EADC_DAT14 A/D Data Register 14 for Sample Module 14 0x38 read-write n 0x0 0x0 DAT15 EADC_DAT15 A/D Data Register 15 for Sample Module 15 0x3C read-write n 0x0 0x0 DAT16 EADC_DAT16 A/D Data Register 16 for Sample Module 16 0x40 read-write n 0x0 0x0 DAT17 EADC_DAT17 A/D Data Register 17 for Sample Module 17 0x44 read-write n 0x0 0x0 DAT18 EADC_DAT18 A/D Data Register 18 for Sample Module 18 0x48 read-write n 0x0 0x0 DAT2 EADC_DAT2 A/D Data Register 2 for Sample Module 2 0x8 read-write n 0x0 0x0 DAT3 EADC_DAT3 A/D Data Register 3 for Sample Module 3 0xC read-write n 0x0 0x0 DAT4 EADC_DAT4 A/D Data Register 4 for Sample Module 4 0x10 read-write n 0x0 0x0 DAT5 EADC_DAT5 A/D Data Register 5 for Sample Module 5 0x14 read-write n 0x0 0x0 DAT6 EADC_DAT6 A/D Data Register 6 for Sample Module 6 0x18 read-write n 0x0 0x0 DAT7 EADC_DAT7 A/D Data Register 7 for Sample Module 7 0x1C read-write n 0x0 0x0 DAT8 EADC_DAT8 A/D Data Register 8 for Sample Module 8 0x20 read-write n 0x0 0x0 DAT9 EADC_DAT9 A/D Data Register 9 for Sample Module 9 0x24 read-write n 0x0 0x0 DDAT0 EADC_DDAT0 A/D Double Data Register 0 for Sample Module 0 0x100 read-only n 0x0 0x0 OV Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read. 16 1 read-only 0 Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result #0 1 Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite #1 RESULT A/D Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. 0 16 read-only VALID Valid Flag 17 1 read-only 0 Double data in RESULT (EADC_DDATn[15:0]) is not valid #0 1 Double data in RESULT (EADC_DDATn[15:0]) is valid #1 DDAT1 EADC_DDAT1 A/D Double Data Register 1 for Sample Module 1 0x104 read-write n 0x0 0x0 DDAT2 EADC_DDAT2 A/D Double Data Register 2 for Sample Module 2 0x108 read-write n 0x0 0x0 DDAT3 EADC_DDAT3 A/D Double Data Register 3 for Sample Module 3 0x10C read-write n 0x0 0x0 INTSRC0 EADC_INTSRC0 ADC Interrupt 0 Source Enable Control Register. 0xD0 read-write n 0x0 0x0 SPLIE0 Sample Module 0 Interrupt Enable Bit 0 1 read-write 0 Sample Module 0 interrupt Disabled #0 1 Sample Module 0 interrupt Enabled #1 SPLIE1 Sample Module 1 Interrupt Enable Bit 1 1 read-write 0 Sample Module 1 interrupt Disabled #0 1 Sample Module 1 interrupt Enabled #1 SPLIE10 Sample Module 10 Interrupt Enable Bit 10 1 read-write 0 Sample Module 10 interrupt Disabled #0 1 Sample Module 10 interrupt Enabled #1 SPLIE11 Sample Module 11 Interrupt Enable Bit 11 1 read-write 0 Sample Module 11 interrupt Disabled #0 1 Sample Module 11 interrupt Enabled #1 SPLIE12 Sample Module 12 Interrupt Enable Bit 12 1 read-write 0 Sample Module 12 interrupt Disabled #0 1 Sample Module 12 interrupt Enabled #1 SPLIE13 Sample Module 13 Interrupt Enable Bit 13 1 read-write 0 Sample Module 13 interrupt Disabled #0 1 Sample Module 13 interrupt Enabled #1 SPLIE14 Sample Module 14 Interrupt Enable Bit 14 1 read-write 0 Sample Module 14 interrupt Disabled #0 1 Sample Module 14 interrupt Enabled #1 SPLIE15 Sample Module 15 Interrupt Enable Bit 15 1 read-write 0 Sample Module 15 interrupt Disabled #0 1 Sample Module 15 interrupt Enabled #1 SPLIE16 Sample Module 16 Interrupt Enable Bit 16 1 read-write 0 Sample Module 16 interrupt Disabled #0 1 Sample Module 16 interrupt Enabled #1 SPLIE17 Sample Module 17 Interrupt Enable Bit 17 1 read-write 0 Sample Module 17 interrupt Disabled #0 1 Sample Module 17 interrupt Enabled #1 SPLIE18 Sample Module 18 Interrupt Enable Bit 18 1 read-write 0 Sample Module 18 interrupt Disabled #0 1 Sample Module 18 interrupt Enabled #1 SPLIE2 Sample Module 2 Interrupt Enable Bit 2 1 read-write 0 Sample Module 2 interrupt Disabled #0 1 Sample Module 2 interrupt Enabled #1 SPLIE3 Sample Module 3 Interrupt Enable Bit 3 1 read-write 0 Sample Module 3 interrupt Disabled #0 1 Sample Module 3 interrupt Enabled #1 SPLIE4 Sample Module 4 Interrupt Enable Bit 4 1 read-write 0 Sample Module 4 interrupt Disabled #0 1 Sample Module 4 interrupt Enabled #1 SPLIE5 Sample Module 5 Interrupt Enable Bit 5 1 read-write 0 Sample Module 5 interrupt Disabled #0 1 Sample Module 5 interrupt Enabled #1 SPLIE6 Sample Module 6 Interrupt Enable Bit 6 1 read-write 0 Sample Module 6 interrupt Disabled #0 1 Sample Module 6 interrupt Enabled #1 SPLIE7 Sample Module 7 Interrupt Enable Bit 7 1 read-write 0 Sample Module 7 interrupt Disabled #0 1 Sample Module 7 interrupt Enabled #1 SPLIE8 Sample Module 8 Interrupt Enable Bit 8 1 read-write 0 Sample Module 8 interrupt Disabled #0 1 Sample Module 8 interrupt Enabled #1 SPLIE9 Sample Module 9 Interrupt Enable Bit 9 1 read-write 0 Sample Module 9 interrupt Disabled #0 1 Sample Module 9 interrupt Enabled #1 INTSRC1 EADC_INTSRC1 ADC Interrupt 1 Source Enable Control Register. 0xD4 read-write n 0x0 0x0 INTSRC2 EADC_INTSRC2 ADC Interrupt 2 Source Enable Control Register. 0xD8 read-write n 0x0 0x0 INTSRC3 EADC_INTSRC3 ADC Interrupt 3 Source Enable Control Register. 0xDC read-write n 0x0 0x0 OVSTS EADC_OVSTS A/D Sample Module Start of Conversion Overrun Flag Register 0x5C read-write n 0x0 0x0 SPOVF A/D SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it. 0 19 read-write 0 No sample module event overrun 0 1 Indicates a new sample module event is generated while an old one event is pending 1 PENDSTS EADC_PENDSTS A/D Start of Conversion Pending Flag Register 0x58 read-write n 0x0 0x0 STPF A/D Sample Module 0~18 Start of Conversion Pending Flag\nRead: 0 19 read-write 0 There is no pending conversion for sample module 0 1 Sample module ADC start of conversion is pending.\nClear pending flag and stop conversion for corresponding sample module 1 SCTL0 EADC_SCTL0 A/D Sample Module 0 Control Register 0x80 read-write n 0x0 0x0 CHSEL A/D Sample Module Channel Selection 0 4 read-write DBMEN Double Buffer Mode Enable Bit 23 1 read-write 0 Sample has one sample result register. (default) #0 1 Sample has two sample result registers #1 EXTFEN A/D External Trigger Falling Edge Enable Bit 5 1 read-write 0 Falling edge Disabled when A/D selects STADC as trigger source #0 1 Falling edge Enabled when A/D selects STADC as trigger source #1 EXTREN A/D External Trigger Rising Edge Enable Bit 4 1 read-write 0 Rising edge Disabled when A/D selects STADC as trigger source #0 1 Rising edge Enabled when A/D selects STADC as trigger source #1 EXTSMPT ADC Sampling Time Extend\nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 22 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion #1 TRGDLYCNT A/D Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency: 6 2 read-write 0 ADC_CLK/1 #00 1 ADC_CLK/2 #01 2 ADC_CLK/4 #10 3 ADC_CLK/16 #11 TRGSEL A/D Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL1 EADC_SCTL1 A/D Sample Module 1 Control Register 0x84 read-write n 0x0 0x0 SCTL10 EADC_SCTL10 A/D Sample Module 10 Control Register 0xA8 read-write n 0x0 0x0 SCTL11 EADC_SCTL11 A/D Sample Module 11 Control Register 0xAC read-write n 0x0 0x0 SCTL12 EADC_SCTL12 A/D Sample Module 12 Control Register 0xB0 read-write n 0x0 0x0 SCTL13 EADC_SCTL13 A/D Sample Module 13 Control Register 0xB4 read-write n 0x0 0x0 SCTL14 EADC_SCTL14 A/D Sample Module 14 Control Register 0xB8 read-write n 0x0 0x0 SCTL15 EADC_SCTL15 A/D Sample Module 15 Control Register 0xBC read-write n 0x0 0x0 SCTL16 EADC_SCTL16 A/D Sample Module 16 Control Register 0xC0 read-write n 0x0 0x0 EXTSMPT ADC Sampling Time Extend\nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write SCTL17 EADC_SCTL17 A/D Sample Module 17 Control Register 0xC4 read-write n 0x0 0x0 SCTL18 EADC_SCTL18 A/D Sample Module 18 Control Register 0xC8 read-write n 0x0 0x0 SCTL2 EADC_SCTL2 A/D Sample Module 2 Control Register 0x88 read-write n 0x0 0x0 SCTL3 EADC_SCTL3 A/D Sample Module 3 Control Register 0x8C read-write n 0x0 0x0 SCTL4 EADC_SCTL4 A/D Sample Module 4 Control Register 0x90 read-write n 0x0 0x0 CHSEL A/D Sample Module Channel Selection 0 4 read-write EXTFEN A/D External Trigger Falling Edge Enable Bit 5 1 read-write 0 Falling edge Disabled when A/D selects STADC as trigger source #0 1 Falling edge Enabled when A/D selects STADC as trigger source #1 EXTREN A/D External Trigger Rising Edge Enable Bit 4 1 read-write 0 Rising edge Disabled when A/D selects STADC as trigger source #0 1 Rising edge Enabled when A/D selects STADC as trigger source #1 EXTSMPT ADC Sampling Time Extend\nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock. 24 8 read-write INTPOS Interrupt Flag Position Select 22 1 read-write 0 Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion #0 1 Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion #1 TRGDLYCNT A/D Sample Module Start of Conversion Trigger Delay Time 8 8 read-write TRGDLYDIV A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency: 6 2 read-write 0 ADC_CLK/1 #00 1 ADC_CLK/2 #01 2 ADC_CLK/4 #10 3 ADC_CLK/16 #11 TRGSEL A/D Sample Module Start of Conversion Trigger Source Selection 16 5 read-write SCTL5 EADC_SCTL5 A/D Sample Module 5 Control Register 0x94 read-write n 0x0 0x0 SCTL6 EADC_SCTL6 A/D Sample Module 6 Control Register 0x98 read-write n 0x0 0x0 SCTL7 EADC_SCTL7 A/D Sample Module 7 Control Register 0x9C read-write n 0x0 0x0 SCTL8 EADC_SCTL8 A/D Sample Module 8 Control Register 0xA0 read-write n 0x0 0x0 SCTL9 EADC_SCTL9 A/D Sample Module 9 Control Register 0xA4 read-write n 0x0 0x0 STATUS0 EADC_STATUS0 A/D Status Register 0 0xF0 read-only n 0x0 0x0 OV EADC_DAT0~15 Overrun Flag 16 16 read-only VALID EADC_DAT0~15 Data Valid Flag 0 16 read-only STATUS1 EADC_STATUS1 A/D Status Register 1 0xF4 read-only n 0x0 0x0 OV EADC_DAT16~18 Overrun Flag 16 3 read-only VALID EADC_DAT16~18 Data Valid Flag 0 3 read-only STATUS2 EADC_STATUS2 A/D Status Register 2 0xF8 read-write n 0x0 0x0 ADCMPF0 ADC Compare 0 Flag\nWhen the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 4 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP0 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP0 register setting #1 ADCMPF1 ADC Compare 1 Flag\nWhen the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP1 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP1 register setting #1 ADCMPF2 ADC Compare 2 Flag\nWhen the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 6 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP2 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP2 register setting #1 ADCMPF3 ADC Compare 3 Flag\nWhen the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it. 7 1 read-write 0 Conversion result in EADC_DAT does not meet EADC_CMP3 register setting #0 1 Conversion result in EADC_DAT meets EADC_CMP3 register setting #1 ADCMPO0 ADC Compare 0 Output Status\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 12 1 read-write 0 Conversion result in EADC_DAT less than CMPDAT0 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT0 setting #1 ADCMPO1 ADC Compare 1 Output Status\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 13 1 read-write 0 Conversion result in EADC_DAT less than CMPDAT1 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT1 setting #1 ADCMPO2 ADC Compare 2 Output Status\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 14 1 read-write 0 Conversion result in EADC_DAT less than CMPDAT2 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT2 setting #1 ADCMPO3 ADC Compare 3 Output Status\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status. 15 1 read-write 0 Conversion result in EADC_DAT less than CMPDAT3 setting #0 1 Conversion result in EADC_DAT great than or equal CMPDAT3 setting #1 ADIF0 A/D ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific sample module has been completed 0 1 read-write 0 No ADINT0 interrupt pulse received #0 1 ADINT0 interrupt pulse has been received #1 ADIF1 A/D ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific sample module has been completed 1 1 read-write 0 No ADINT1 interrupt pulse received #0 1 ADINT1 interrupt pulse has been received #1 ADIF2 A/D ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it. \nNote2:This bit indicates whether an A/D conversion of specific sample module has been completed 2 1 read-write 0 No ADINT2 interrupt pulse received #0 1 ADINT2 interrupt pulse has been received #1 ADIF3 A/D ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific sample module has been completed 3 1 read-write 0 No ADINT3 interrupt pulse received #0 1 ADINT3 interrupt pulse has been received #1 ADOVIF All A/D Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 24 1 read-write 0 None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1 #0 1 Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1 #1 ADOVIF0 A/D ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 8 1 read-write 0 ADINT0 interrupt flag is not overwritten to 1 #0 1 ADINT0 interrupt flag is overwritten to 1 #1 ADOVIF1 A/D ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 9 1 read-write 0 ADINT1 interrupt flag is not overwritten to 1 #0 1 ADINT1 interrupt flag is overwritten to 1 #1 ADOVIF2 A/D ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 10 1 read-write 0 ADINT2 interrupt flag is not overwritten to 1 #0 1 ADINT2 interrupt flag is overwritten to 1 #1 ADOVIF3 A/D ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it. 11 1 read-write 0 ADINT3 interrupt flag is not overwritten to 1 #0 1 ADINT3 interrupt flag is overwritten to 1 #1 AOV for All Sample Module A/D Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVn Flag is equal to 1. 27 1 read-write 0 None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #0 1 Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1 #1 AVALID for All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1. 26 1 read-write 0 None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #0 1 Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1 #1 BUSY Busy/Idle\nNote: This bit is read only. 23 1 read-write 0 EADC is in idle state #0 1 EADC is busy at conversion #1 CHANNEL Current Conversion Channel 16 5 read-write STOVF for All A/D Sample Module Start of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1. 25 1 read-write 0 None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #0 1 Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1 #1 STATUS3 EADC_STATUS3 A/D Status Register 3 0xFC read-only n 0x0 0x0 CURSPL ADC Current Sample Module\nThis register show the current ADC is controlled by which sample module control logic modules.\nIf the ADC is Idle, this bit filed will set to 0x1F.\nThis is a read only register. 0 5 read-only SWTRG EADC_SWTRG A/D Sample Module Software Start Register 0x54 write-only n 0x0 0x0 SWTRG A/D Sample Module 0~18 Software Force to Start ADC Conversion\nNote: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 0 19 write-only 0 No effect 0 1 Cause an ADC conversion when the priority is given to sample module 1 EBI EBI Register Map EBI 0x0 0x0 0x8 registers n 0x10 0x8 registers n CTL0 EBI_CTL0 External Bus Interface Bank0 Control Register 0x0 read-write n 0x0 0x0 CSPOLINV Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS). 2 1 read-write 0 Chip select pin (EBI_nCS) is active low #0 1 Chip select pin (EBI_nCS) is active high #1 DW16 EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit. 1 1 read-write 0 EBI data width is 8-bit #0 1 EBI data width is 16-bit #1 EN EBI Enable Bit\nThis bit is the functional enable bit for EBI. 0 1 read-write 0 EBI function Disabled #0 1 EBI function Enabled #1 MCLKDIV External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: 8 3 read-write 0 HCLK/1 #000 1 HCLK/2 #001 2 HCLK/4 #010 3 HCLK/8 #011 4 HCLK/16 #100 5 HCLK/32 #101 6 Reserved. #110 7 Reserved. #111 TALE Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register 16 3 read-write WBUFEN EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register 24 1 read-write 0 EBI write buffer Disabled #0 1 EBI write buffer Enabled #1 CTL1 EBI_CTL1 External Bus Interface Bank1 Control Register 0x10 read-write n 0x0 0x0 TCTL0 EBI_TCTL0 External Bus Interface Bank0 Timing Control Register 0x4 read-write n 0x0 0x0 R2R Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS returns to idle state. 24 4 read-write RAHDOFF Access Hold Time Disable Control When Read 22 1 read-write 0 The Data Access Hold Time (tAHD) during EBI reading Enabled #0 1 The Data Access Hold Time (tAHD) during EBI reading Disabled #1 TACC EBI Data Access Time\nTACC define data access time (tACC). 3 5 read-write TAHD EBI Data Access Hold Time\nTAHD define data access hold time (tAHD). 8 3 read-write W2X Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. 12 4 read-write WAHDOFF Access Hold Time Disable Control When Write 23 1 read-write 0 The Data Access Hold Time (tAHD) during EBI writing Enabled #0 1 The Data Access Hold Time (tAHD) during EBI writing Disabled #1 TCTL1 EBI_TCTL1 External Bus Interface Bank1 Timing Control Register 0x14 read-write n 0x0 0x0 FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n 0x80 0x10 registers n 0xC0 0x8 registers n DFBA FMC_DFBA Data Flash Base Address 0x14 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 0 32 read-only FTCTL FMC_FTCTL Flash Access Time Control Register 0x18 read-write n 0x0 0x0 FOM Frequency Optimization Mode (Write Protect)\nThe M4521 series support adjustable Flash access timing to optimize the Flash access cycles in different working frequency.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 3 read-write 1 Frequency 12MHz #001 2 Frequency 36MHz #010 4 Frequency 60MHz #100 ISPADDR FMC_ISPADDR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADDR ISP Address\nThe M4521 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 KB alignment is necessary for checksum calculation. 0 32 read-write ISPCMD FMC_ISPCMD ISP CMD Register 0xC read-write n 0x0 0x0 CMD ISP CMD\nISP command table is shown below:\nThe other commands are invalid. 0 7 read-write 0 FLASH 32-bit Read 0x00 4 Read Unique ID 0x04 11 Read Company ID 0x0b 13 Read Checksum 0x0d 33 FLASH 32-bit Program 0x21 34 FLASH Page Erase 0x22 39 FLASH Multi-Word Program 0x27 45 Run Checksum Calculation 0x2d 46 Vector Remap 0x2e 64 FLASH 64-bit Read 0x40 97 FLASH 64-bit Program 0x61 ISPCTL FMC_ISPCTL ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 APROM cannot be updated when the chip runs in APROM #0 1 APROM can be updated when the chip runs in APROM #1 BS Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Booting from APROM #0 1 Booting from LDROM #1 CFGUEN CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 CONFIG cannot be updated #0 1 CONFIG can be updated #1 ISPEN ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write LDUEN LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated #1 ISPDAT FMC_ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTS FMC_ISPSTS ISP Status Register 0x40 read-write n 0x0 0x0 CBS Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 1 2 read-only 0 LDROM with IAP mode #00 1 LDROM without IAP mode #01 2 APROM with IAP mode #10 3 APROM without IAP mode #11 ISPBUSY ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP operation is finished #0 1 ISP is progressed #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write PGFF Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation 5 1 read-only 0 Flash Program is success #0 1 Flash Program is fail. Program data is different with data in the Flash memory #1 VECMAP Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} 9 15 read-only ISPTRG FMC_ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 ISP operation is finished #0 1 ISP is progressed #1 MPADDR FMC_MPADDR ISP Multi-program Address Register 0xC4 read-only n 0x0 0x0 MPADDR ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete. 0 32 read-only MPDAT0 FMC_MPDAT0 ISP Data0 Register 0x80 read-write n 0x0 0x0 ISPDAT0 ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data. 0 32 read-write MPDAT1 FMC_MPDAT1 ISP Data1 Register 0x84 read-write n 0x0 0x0 ISPDAT1 ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming. 0 32 read-write MPDAT2 FMC_MPDAT2 ISP Data2 Register 0x88 read-write n 0x0 0x0 ISPDAT2 ISP Data 2\nThis register is the third 32-bit data for multi-word programming. 0 32 read-write MPDAT3 FMC_MPDAT3 ISP Data3 Register 0x8C read-write n 0x0 0x0 ISPDAT3 ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming. 0 32 read-write MPSTS FMC_MPSTS ISP Multi-program Status Register 0xC0 read-only n 0x0 0x0 D0 ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete. 4 1 read-only 0 FMC_MPDAT0 register is empty, or program to Flash complete #0 1 FMC_MPDAT0 register has been written, and not program to Flash complete #1 D1 ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete. 5 1 read-only 0 FMC_MPDAT1 register is empty, or program to Flash complete #0 1 FMC_MPDAT1 register has been written, and not program to Flash complete #1 D2 ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete. 6 1 read-only 0 FMC_MPDAT2 register is empty, or program to Flash complete #0 1 FMC_MPDAT2 register has been written, and not program to Flash complete #1 D3 ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete. 7 1 read-only 0 FMC_MPDAT3 register is empty, or program to Flash complete #0 1 FMC_MPDAT3 register has been written, and not program to Flash complete #1 ISPFF ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands 2 1 read-only MPBUSY ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]). 0 1 read-only 0 ISP Multi-Word program operation is finished #0 1 ISP Multi-Word program operation is progressed #1 PPGO ISP Multi-program Status (Read Only) 1 1 read-only 0 ISP multi-word program operation is not active #0 1 ISP multi-word program operation is in progress #1 GPIO GPIO Register Map GPIO 0x0 0x0 0x2C registers n 0x100 0x30 registers n 0x140 0x2C registers n 0x40 0x2C registers n 0x440 0x4 registers n 0x80 0x2C registers n 0x800 0x10 registers n 0x840 0x60 registers n 0x8C0 0x78 registers n 0x940 0x20 registers n 0xC0 0x2C registers n DBCTL GPIO_DBCTL Interrupt De-bounce Control Register 0x440 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC) #1 ICLKON Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 PA0_PDIO PA0_PDIO GPIO PA.n Pin Data Input/Output Register 0x800 read-write n 0x0 0x0 PDIO GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).\nNote1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]). 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 PA1_PDIO PA1_PDIO GPIO PA.n Pin Data Input/Output Register 0x804 read-write n 0x0 0x0 PA2_PDIO PA2_PDIO GPIO PA.n Pin Data Input/Output Register 0x808 read-write n 0x0 0x0 PA3_PDIO PA3_PDIO GPIO PA.n Pin Data Input/Output Register 0x80C read-write n 0x0 0x0 PA_DATMSK PA_DATMSK PA Data Output Write Mask 0xC read-write n 0x0 0x0 DATMSK0 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 0 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK1 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 1 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK10 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 10 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK11 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 11 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK12 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 12 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK13 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 13 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK14 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 14 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK15 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 15 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK2 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 2 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK3 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 3 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK4 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 4 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK5 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 5 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK6 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 6 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK7 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 7 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK8 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 8 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 DATMSK9 Port A-f Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. 9 1 read-write 0 Corresponding DOUT (Px_DOUT[n]) bit can be updated #0 1 Corresponding DOUT (Px_DOUT[n]) bit protected #1 PA_DBEN PA_DBEN PA De-bounce Enable Control Register 0x14 read-write n 0x0 0x0 DBEN0 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 0 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN1 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 1 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN10 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 10 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN11 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 11 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN12 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 12 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN13 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 13 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN14 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 14 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN15 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 15 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN2 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 2 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN3 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 3 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN4 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 4 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN5 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 5 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN6 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 6 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN7 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 7 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN8 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 8 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 DBEN9 Port A-f Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 9 1 read-write 0 Px.n de-bounce function Disabled #0 1 Px.n de-bounce function Enabled #1 PA_DINOFF PA_DINOFF PA Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 DINOFF0 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 16 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF1 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 17 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF10 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 26 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF11 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 27 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF12 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 28 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF13 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 29 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF14 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 30 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF15 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 31 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF2 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 18 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF3 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 19 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF4 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 20 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF5 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 21 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF6 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 22 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF7 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 23 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF8 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 24 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 DINOFF9 Port A-f Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. 25 1 read-write 0 Px.n digital input path Enabled #0 1 Px.n digital input path Disabled (digital input tied to low) #1 PA_DOUT PA_DOUT PA Data Output Value 0x8 read-write n 0x0 0x0 DOUT0 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 0 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT1 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 1 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT10 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 10 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT11 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 11 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT12 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 12 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT13 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 13 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT14 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 14 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT15 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 15 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT2 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 2 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT3 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 3 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT4 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 4 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT5 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 5 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT6 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 6 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT7 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 7 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT8 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 8 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 DOUT9 Port A-f Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. 9 1 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode #0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode #1 PA_INTEN PA_INTEN PA Interrupt Enable Control Register 0x1C read-write n 0x0 0x0 FLIEN0 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 0 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN1 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 1 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN10 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 10 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN11 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 11 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN12 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 12 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN13 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 13 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN14 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 14 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN15 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 15 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN2 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 2 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN3 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 3 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN4 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 4 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN5 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 5 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN6 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 6 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN7 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 7 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN8 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 8 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 FLIEN9 Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. 9 1 read-write 0 Px.n level low or high to low interrupt Disabled #0 1 Px.n level low or high to low interrupt Enabled #1 RHIEN0 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 16 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN1 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 17 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN10 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 26 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN11 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 27 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN12 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 28 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN13 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 29 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN14 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 30 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN15 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 31 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN2 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 18 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN3 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 19 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN4 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 20 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN5 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 21 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN6 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 22 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN7 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 23 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN8 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 24 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 RHIEN9 Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. 25 1 read-write 0 Px.n level high or low to high interrupt Disabled #0 1 Px.n level high or low to high interrupt Enabled #1 PA_INTSRC PA_INTSRC PA Interrupt Source Flag 0x20 read-write n 0x0 0x0 INTSRC0 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 0 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC1 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 1 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC10 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 10 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC11 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 11 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC12 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 12 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC13 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 13 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC14 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 14 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC15 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 15 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC2 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 2 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC3 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 3 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC4 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 4 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC5 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 5 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC6 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 6 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC7 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 7 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC8 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 8 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 INTSRC9 Port A-f Pin[N] Interrupt Source Flag\nWrite Operation : 9 1 read-write 0 No action.\nNo interrupt at Px.n #0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt #1 PA_INTTYPE PA_INTTYPE PA Interrupt Trigger Type Control 0x18 read-write n 0x0 0x0 TYPE0 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE1 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE10 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE11 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE12 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE13 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE14 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE15 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE2 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE3 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE4 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE5 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE6 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE7 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE8 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 TYPE9 Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 PA_MODE PA_MODE PA I/O Mode Control 0x0 read-write n 0x0 0x0 MODE0 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 0 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE1 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 2 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE10 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 20 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE11 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 22 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE12 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 24 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE13 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 26 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE14 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 28 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE15 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 30 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE2 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 4 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE3 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 6 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE4 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 8 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE5 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 10 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE6 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 12 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE7 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 14 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE8 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 16 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 MODE9 Port A-f I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. 18 2 read-write 0 Px.n is in Input mode #00 1 Px.n is in Push-pull Output mode #01 2 Px.n is in Open-drain Output mode #10 3 Px.n is in Quasi-bidirectional mode #11 PA_PIN PA_PIN PA Pin Value 0x10 read-only n 0x0 0x0 PIN0 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 0 1 read-only PIN1 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 1 1 read-only PIN10 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 10 1 read-only PIN11 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 11 1 read-only PIN12 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 12 1 read-only PIN13 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 13 1 read-only PIN14 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 14 1 read-only PIN15 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 15 1 read-only PIN2 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 2 1 read-only PIN3 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 3 1 read-only PIN4 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 4 1 read-only PIN5 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 5 1 read-only PIN6 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 6 1 read-only PIN7 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 7 1 read-only PIN8 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 8 1 read-only PIN9 Port A-f Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. 9 1 read-only PA_SLEWCTL PA_SLEWCTL PA High Slew Rate Control Register 0x28 read-write n 0x0 0x0 HSREN0 Port A-f Pin[N] High Slew Rate Control 0 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN1 Port A-f Pin[N] High Slew Rate Control 1 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN10 Port A-f Pin[N] High Slew Rate Control 10 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN11 Port A-f Pin[N] High Slew Rate Control 11 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN12 Port A-f Pin[N] High Slew Rate Control 12 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN13 Port A-f Pin[N] High Slew Rate Control 13 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN14 Port A-f Pin[N] High Slew Rate Control 14 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN15 Port A-f Pin[N] High Slew Rate Control 15 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN2 Port A-f Pin[N] High Slew Rate Control 2 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN3 Port A-f Pin[N] High Slew Rate Control 3 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN4 Port A-f Pin[N] High Slew Rate Control 4 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN5 Port A-f Pin[N] High Slew Rate Control 5 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN6 Port A-f Pin[N] High Slew Rate Control 6 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN7 Port A-f Pin[N] High Slew Rate Control 7 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN8 Port A-f Pin[N] High Slew Rate Control 8 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 HSREN9 Port A-f Pin[N] High Slew Rate Control 9 1 read-write 0 Px.n output with basic slew rate #0 1 Px.n output with higher slew rate #1 PA_SMTEN PA_SMTEN PA Input Schmitt Trigger Enable Register 0x24 read-write n 0x0 0x0 SMTEN0 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 0 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN1 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 1 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN10 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 10 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN11 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 11 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN12 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 12 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN13 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 13 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN14 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 14 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN15 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 15 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN2 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 2 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN3 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 3 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN4 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 4 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN5 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 5 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN6 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 6 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN7 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 7 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN8 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 8 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 SMTEN9 Port A-f Pin[N] Input Schmitt Trigger Enable Bit 9 1 read-write 0 Px.n input schmitt trigger function Disabled #0 1 Px.n input schmitt trigger function Enabled #1 PB0_PDIO PB0_PDIO GPIO PB.n Pin Data Input/Output Register 0x840 read-write n 0x0 0x0 PB10_PDIO PB10_PDIO GPIO PB.n Pin Data Input/Output Register 0x868 read-write n 0x0 0x0 PB11_PDIO PB11_PDIO GPIO PB.n Pin Data Input/Output Register 0x86C read-write n 0x0 0x0 PB12_PDIO PB12_PDIO GPIO PB.n Pin Data Input/Output Register 0x870 read-write n 0x0 0x0 PB13_PDIO PB13_PDIO GPIO PB.n Pin Data Input/Output Register 0x874 read-write n 0x0 0x0 PB14_PDIO PB14_PDIO GPIO PB.n Pin Data Input/Output Register 0x878 read-write n 0x0 0x0 PB15_PDIO PB15_PDIO GPIO PB.n Pin Data Input/Output Register 0x87C read-write n 0x0 0x0 PB1_PDIO PB1_PDIO GPIO PB.n Pin Data Input/Output Register 0x844 read-write n 0x0 0x0 PB2_PDIO PB2_PDIO GPIO PB.n Pin Data Input/Output Register 0x848 read-write n 0x0 0x0 PB3_PDIO PB3_PDIO GPIO PB.n Pin Data Input/Output Register 0x84C read-write n 0x0 0x0 PB4_PDIO PB4_PDIO GPIO PB.n Pin Data Input/Output Register 0x850 read-write n 0x0 0x0 PB5_PDIO PB5_PDIO GPIO PB.n Pin Data Input/Output Register 0x854 read-write n 0x0 0x0 PB6_PDIO PB6_PDIO GPIO PB.n Pin Data Input/Output Register 0x858 read-write n 0x0 0x0 PB7_PDIO PB7_PDIO GPIO PB.n Pin Data Input/Output Register 0x85C read-write n 0x0 0x0 PB8_PDIO PB8_PDIO GPIO PB.n Pin Data Input/Output Register 0x860 read-write n 0x0 0x0 PB9_PDIO PB9_PDIO GPIO PB.n Pin Data Input/Output Register 0x864 read-write n 0x0 0x0 PB_DATMSK PB_DATMSK PB Data Output Write Mask 0x4C read-write n 0x0 0x0 PB_DBEN PB_DBEN PB De-bounce Enable Control Register 0x54 read-write n 0x0 0x0 PB_DINOFF PB_DINOFF PB Digital Input Path Disable Control 0x44 read-write n 0x0 0x0 PB_DOUT PB_DOUT PB Data Output Value 0x48 read-write n 0x0 0x0 PB_INTEN PB_INTEN PB Interrupt Enable Control Register 0x5C read-write n 0x0 0x0 PB_INTSRC PB_INTSRC PB Interrupt Source Flag 0x60 read-write n 0x0 0x0 PB_INTTYPE PB_INTTYPE PB Interrupt Trigger Type Control 0x58 read-write n 0x0 0x0 PB_MODE PB_MODE PB I/O Mode Control 0x40 read-write n 0x0 0x0 PB_PIN PB_PIN PB Pin Value 0x50 read-write n 0x0 0x0 PB_SLEWCTL PB_SLEWCTL PB High Slew Rate Control Register 0x68 read-write n 0x0 0x0 PB_SMTEN PB_SMTEN PB Input Schmitt Trigger Enable Register 0x64 read-write n 0x0 0x0 PC0_PDIO PC0_PDIO GPIO PC.n Pin Data Input/Output Register 0x880 read-write n 0x0 0x0 PC1_PDIO PC1_PDIO GPIO PC.n Pin Data Input/Output Register 0x884 read-write n 0x0 0x0 PC2_PDIO PC2_PDIO GPIO PC.n Pin Data Input/Output Register 0x888 read-write n 0x0 0x0 PC3_PDIO PC3_PDIO GPIO PC.n Pin Data Input/Output Register 0x88C read-write n 0x0 0x0 PC4_PDIO PC4_PDIO GPIO PC.n Pin Data Input/Output Register 0x890 read-write n 0x0 0x0 PC5_PDIO PC5_PDIO GPIO PC.n Pin Data Input/Output Register 0x894 read-write n 0x0 0x0 PC6_PDIO PC6_PDIO GPIO PC.n Pin Data Input/Output Register 0x898 read-write n 0x0 0x0 PC7_PDIO PC7_PDIO GPIO PC.n Pin Data Input/Output Register 0x89C read-write n 0x0 0x0 PC_DATMSK PC_DATMSK PC Data Output Write Mask 0x8C read-write n 0x0 0x0 PC_DBEN PC_DBEN PC De-bounce Enable Control Register 0x94 read-write n 0x0 0x0 PC_DINOFF PC_DINOFF PC Digital Input Path Disable Control 0x84 read-write n 0x0 0x0 PC_DOUT PC_DOUT PC Data Output Value 0x88 read-write n 0x0 0x0 PC_INTEN PC_INTEN PC Interrupt Enable Control Register 0x9C read-write n 0x0 0x0 PC_INTSRC PC_INTSRC PC Interrupt Source Flag 0xA0 read-write n 0x0 0x0 PC_INTTYPE PC_INTTYPE PC Interrupt Trigger Type Control 0x98 read-write n 0x0 0x0 PC_MODE PC_MODE PC I/O Mode Control 0x80 read-write n 0x0 0x0 PC_PIN PC_PIN PC Pin Value 0x90 read-write n 0x0 0x0 PC_SLEWCTL PC_SLEWCTL PC High Slew Rate Control Register 0xA8 read-write n 0x0 0x0 PC_SMTEN PC_SMTEN PC Input Schmitt Trigger Enable Register 0xA4 read-write n 0x0 0x0 PD0_PDIO PD0_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C0 read-write n 0x0 0x0 PD10_PDIO PD10_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E8 read-write n 0x0 0x0 PD11_PDIO PD11_PDIO GPIO PD.n Pin Data Input/Output Register 0x8EC read-write n 0x0 0x0 PD12_PDIO PD12_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F0 read-write n 0x0 0x0 PD13_PDIO PD13_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F4 read-write n 0x0 0x0 PD14_PDIO PD14_PDIO GPIO PD.n Pin Data Input/Output Register 0x8F8 read-write n 0x0 0x0 PD15_PDIO PD15_PDIO GPIO PD.n Pin Data Input/Output Register 0x8FC read-write n 0x0 0x0 PD1_PDIO PD1_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C4 read-write n 0x0 0x0 PD2_PDIO PD2_PDIO GPIO PD.n Pin Data Input/Output Register 0x8C8 read-write n 0x0 0x0 PD3_PDIO PD3_PDIO GPIO PD.n Pin Data Input/Output Register 0x8CC read-write n 0x0 0x0 PD4_PDIO PD4_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D0 read-write n 0x0 0x0 PD5_PDIO PD5_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D4 read-write n 0x0 0x0 PD6_PDIO PD6_PDIO GPIO PD.n Pin Data Input/Output Register 0x8D8 read-write n 0x0 0x0 PD7_PDIO PD7_PDIO GPIO PD.n Pin Data Input/Output Register 0x8DC read-write n 0x0 0x0 PD8_PDIO PD8_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E0 read-write n 0x0 0x0 PD9_PDIO PD9_PDIO GPIO PD.n Pin Data Input/Output Register 0x8E4 read-write n 0x0 0x0 PD_DATMSK PD_DATMSK PD Data Output Write Mask 0xCC read-write n 0x0 0x0 PD_DBEN PD_DBEN PD De-bounce Enable Control Register 0xD4 read-write n 0x0 0x0 PD_DINOFF PD_DINOFF PD Digital Input Path Disable Control 0xC4 read-write n 0x0 0x0 PD_DOUT PD_DOUT PD Data Output Value 0xC8 read-write n 0x0 0x0 PD_INTEN PD_INTEN PD Interrupt Enable Control Register 0xDC read-write n 0x0 0x0 PD_INTSRC PD_INTSRC PD Interrupt Source Flag 0xE0 read-write n 0x0 0x0 PD_INTTYPE PD_INTTYPE PD Interrupt Trigger Type Control 0xD8 read-write n 0x0 0x0 PD_MODE PD_MODE PD I/O Mode Control 0xC0 read-write n 0x0 0x0 PD_PIN PD_PIN PD Pin Value 0xD0 read-write n 0x0 0x0 PD_SLEWCTL PD_SLEWCTL PD High Slew Rate Control Register 0xE8 read-write n 0x0 0x0 PD_SMTEN PD_SMTEN PD Input Schmitt Trigger Enable Register 0xE4 read-write n 0x0 0x0 PE0_PDIO PE0_PDIO GPIO PE.n Pin Data Input/Output Register 0x900 read-write n 0x0 0x0 PE10_PDIO PE10_PDIO GPIO PE.n Pin Data Input/Output Register 0x928 read-write n 0x0 0x0 PE11_PDIO PE11_PDIO GPIO PE.n Pin Data Input/Output Register 0x92C read-write n 0x0 0x0 PE12_PDIO PE12_PDIO GPIO PE.n Pin Data Input/Output Register 0x930 read-write n 0x0 0x0 PE13_PDIO PE13_PDIO GPIO PE.n Pin Data Input/Output Register 0x934 read-write n 0x0 0x0 PE1_PDIO PE1_PDIO GPIO PE.n Pin Data Input/Output Register 0x904 read-write n 0x0 0x0 PE2_PDIO PE2_PDIO GPIO PE.n Pin Data Input/Output Register 0x908 read-write n 0x0 0x0 PE3_PDIO PE3_PDIO GPIO PE.n Pin Data Input/Output Register 0x90C read-write n 0x0 0x0 PE4_PDIO PE4_PDIO GPIO PE.n Pin Data Input/Output Register 0x910 read-write n 0x0 0x0 PE5_PDIO PE5_PDIO GPIO PE.n Pin Data Input/Output Register 0x914 read-write n 0x0 0x0 PE6_PDIO PE6_PDIO GPIO PE.n Pin Data Input/Output Register 0x918 read-write n 0x0 0x0 PE7_PDIO PE7_PDIO GPIO PE.n Pin Data Input/Output Register 0x91C read-write n 0x0 0x0 PE8_PDIO PE8_PDIO GPIO PE.n Pin Data Input/Output Register 0x920 read-write n 0x0 0x0 PE9_PDIO PE9_PDIO GPIO PE.n Pin Data Input/Output Register 0x924 read-write n 0x0 0x0 PE_DATMSK PE_DATMSK PE Data Output Write Mask 0x10C read-write n 0x0 0x0 PE_DBEN PE_DBEN PE De-bounce Enable Control Register 0x114 read-write n 0x0 0x0 PE_DINOFF PE_DINOFF PE Digital Input Path Disable Control 0x104 read-write n 0x0 0x0 PE_DOUT PE_DOUT PE Data Output Value 0x108 read-write n 0x0 0x0 PE_DRVCTL PE_DRVCTL PE High Drive Strength Control Register 0x12C read-write n 0x0 0x0 HDRVEN10 Port E Pin[N] Driving Strength Control 10 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN11 Port E Pin[N] Driving Strength Control 11 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN12 Port E Pin[N] Driving Strength Control 12 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN13 Port E Pin[N] Driving Strength Control 13 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN8 Port E Pin[N] Driving Strength Control 8 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 HDRVEN9 Port E Pin[N] Driving Strength Control 9 1 read-write 0 Px.n output with basic driving strength #0 1 Px.n output with high driving strength #1 PE_INTEN PE_INTEN PE Interrupt Enable Control Register 0x11C read-write n 0x0 0x0 PE_INTSRC PE_INTSRC PE Interrupt Source Flag 0x120 read-write n 0x0 0x0 PE_INTTYPE PE_INTTYPE PE Interrupt Trigger Type Control 0x118 read-write n 0x0 0x0 PE_MODE PE_MODE PE I/O Mode Control 0x100 read-write n 0x0 0x0 PE_PIN PE_PIN PE Pin Value 0x110 read-write n 0x0 0x0 PE_SLEWCTL PE_SLEWCTL PE High Slew Rate Control Register 0x128 read-write n 0x0 0x0 PE_SMTEN PE_SMTEN PE Input Schmitt Trigger Enable Register 0x124 read-write n 0x0 0x0 PF0_PDIO PF0_PDIO GPIO PF.n Pin Data Input/Output Register 0x940 read-write n 0x0 0x0 PF1_PDIO PF1_PDIO GPIO PF.n Pin Data Input/Output Register 0x944 read-write n 0x0 0x0 PF2_PDIO PF2_PDIO GPIO PF.n Pin Data Input/Output Register 0x948 read-write n 0x0 0x0 PF3_PDIO PF3_PDIO GPIO PF.n Pin Data Input/Output Register 0x94C read-write n 0x0 0x0 PF4_PDIO PF4_PDIO GPIO PF.n Pin Data Input/Output Register 0x950 read-write n 0x0 0x0 PF5_PDIO PF5_PDIO GPIO PF.n Pin Data Input/Output Register 0x954 read-write n 0x0 0x0 PF6_PDIO PF6_PDIO GPIO PF.n Pin Data Input/Output Register 0x958 read-write n 0x0 0x0 PF7_PDIO PF7_PDIO GPIO PF.n Pin Data Input/Output Register 0x95C read-write n 0x0 0x0 PF_DATMSK PF_DATMSK PF Data Output Write Mask 0x14C read-write n 0x0 0x0 PF_DBEN PF_DBEN PF De-bounce Enable Control Register 0x154 read-write n 0x0 0x0 PF_DINOFF PF_DINOFF PF Digital Input Path Disable Control 0x144 read-write n 0x0 0x0 PF_DOUT PF_DOUT PF Data Output Value 0x148 read-write n 0x0 0x0 PF_INTEN PF_INTEN PF Interrupt Enable Control Register 0x15C read-write n 0x0 0x0 PF_INTSRC PF_INTSRC PF Interrupt Source Flag 0x160 read-write n 0x0 0x0 PF_INTTYPE PF_INTTYPE PF Interrupt Trigger Type Control 0x158 read-write n 0x0 0x0 PF_MODE PF_MODE PF I/O Mode Control 0x140 read-write n 0x0 0x0 PF_PIN PF_PIN PF Pin Value 0x150 read-write n 0x0 0x0 PF_SLEWCTL PF_SLEWCTL PF High Slew Rate Control Register 0x168 read-write n 0x0 0x0 PF_SMTEN PF_SMTEN PF Input Schmitt Trigger Enable Register 0x164 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x24 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x44 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled and the SUSCON will be used as CONTROL function #1 BUSEN BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 10 1 read-write 0 The PEC calculation is cleared by 'Repeat Start' function Disabled #0 1 The PEC calculation is cleared by 'Repeat Start' function Enabled #1 PECEN Packet Error Checking Calculation Enable Bit 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception\nThis bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received 8 1 read-write 0 No PEC transfer #0 1 PEC transmission/reception is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current bus state. 9 1 read-write 0 The BUSTOUT is used to calculate the clock low period in bus active #0 1 The BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x4C read-write n 0x0 0x0 ALERT SMBus Alert Status \nNote: The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system. Write 1 to clear this bit. 3 1 read-write 0 SMALERT pin state is low.\nNo SMBALERT event #0 1 SMALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done \nNote: Write 1 to clear this bit. 1 1 read-write 0 Transmission/ receive is not finished when the PECEN is set #0 1 Transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status \nNote: In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 The time-out or external clock time-out occurred #1 BUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 CLKTO Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit. 6 1 read-write 0 The cumulative clock low has no any time-out #0 1 The cumulative clock low time-out occurred #1 PECERR PEC Error in Reception \nNote: Write 1 to clear this bit. 2 1 read-write 0 The PEC value equals the received PEC data packet #0 1 The PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x48 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 The bus clock low time-out detection Disabled #0 1 The bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 The SCLK low time-out interrupt iDisabled.\nThe bus IDLE time-out interrupt Disabled #0 1 The SCLK low time-out interrupt Enabled.\nThe bus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP 1 1 read-write 0 The cumulative clock low time-out detection Disabled #0 1 The cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 The time extended interrupt Disabled #0 1 The time extended interrupt Enabled #1 PECIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 5 1 read-write 0 The byte count done interrupt Disabled #0 1 The byte count done interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x58 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value\nIndicate the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x5C read-write n 0x0 0x0 CLKTO Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C Controller Disabled #0 1 I2C Controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x54 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x50 read-write n 0x0 0x0 PLDSIZE Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 255 Bytes. \nNotice: The byte number counting includes address, command code, and data frame. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0xC read-only n 0x0 0x0 STATUS I2C Status\n2. If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed. 0 8 read-only I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Time-Out Counter Input Clock Divided Disabled #0 1 Time-Out Counter Input Clock Divided Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-Out Counter Disabled #0 1 Time-Out Counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x24 registers n I2C_ADDR0 I2C_ADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 ADDR I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched. 1 7 read-write GC General Call Function 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 I2C_ADDR1 I2C_ADDR1 I2C Slave Address Register1 0x18 read-write n 0x0 0x0 I2C_ADDR2 I2C_ADDR2 I2C Slave Address Register2 0x1C read-write n 0x0 0x0 I2C_ADDR3 I2C_ADDR3 I2C Slave Address Register3 0x20 read-write n 0x0 0x0 I2C_ADDRMSK0 I2C_ADDRMSK0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 ADDRMSK I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 1 7 read-write 0 Mask Disabled (the received corresponding register bit should be exact the same as address register.) 0 1 Mask Enabled (the received corresponding address bit is don't care.) 1 I2C_ADDRMSK1 I2C_ADDRMSK1 I2C Slave Address Mask Register1 0x28 read-write n 0x0 0x0 I2C_ADDRMSK2 I2C_ADDRMSK2 I2C Slave Address Mask Register2 0x2C read-write n 0x0 0x0 I2C_ADDRMSK3 I2C_ADDRMSK3 I2C Slave Address Mask Register3 0x30 read-write n 0x0 0x0 I2C_BUSCTL I2C_BUSCTL I2C Bus Management Control Register 0x44 read-write n 0x0 0x0 ACKM9SI Acknowledge Manual Enable Extra SI Interrupt 11 1 read-write 0 There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #0 1 There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1 #1 ACKMEN Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 0 1 read-write 0 Slave byte control Disabled #0 1 Slave byte control Enabled. The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse #1 ALERTEN Bus Management Alert Enable Bit 4 1 read-write 0 Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin not supported #0 1 Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.\nBM_ALERT pin supported #1 BMDEN Bus Management Device Default Address Enable Bit 2 1 read-write 0 Device default address Disable. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed #0 1 Device default address Enabled. When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed #1 BMHEN Bus Management Host Enable Bit 3 1 read-write 0 Host function Disabled #0 1 Host function Enabled and the SUSCON will be used as CONTROL function #1 BUSEN BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 7 1 read-write 0 The system management function Disabled #0 1 The system management function Enabled #1 PECCLR PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 10 1 read-write 0 The PEC calculation is cleared by 'Repeat Start' function Disabled #0 1 The PEC calculation is cleared by 'Repeat Start' function Enabled #1 PECEN Packet Error Checking Calculation Enable Bit 1 1 read-write 0 Packet Error Checking Calculation Disabled #0 1 Packet Error Checking Calculation Enabled #1 PECTXEN Packet Error Checking Byte Transmission/Reception\nThis bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received 8 1 read-write 0 No PEC transfer #0 1 PEC transmission/reception is requested #1 SCTLOEN Suspend or Control Pin Output Enable Bit 6 1 read-write 0 The SUSCON pin in input #0 1 The output enable is active on the SUSCON pin #1 SCTLOSTS Suspend/Control Data Output Status 5 1 read-write 0 The output of SUSCON pin is low #0 1 The output of SUSCON pin is high #1 TIDLE Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicates the current bus state. 9 1 read-write 0 The BUSTOUT is used to calculate the clock low period in bus active #0 1 The BUSTOUT is used to calculate the IDLE period in bus Idle #1 I2C_BUSSTS I2C_BUSSTS I2C Bus Management Status Register 0x4C read-write n 0x0 0x0 ALERT SMBus Alert Status \nNote: The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system. Write 1 to clear this bit. 3 1 read-write 0 SMALERT pin state is low.\nNo SMBALERT event #0 1 SMALERT pin state is high.\nThere is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1 #1 BCDONE Byte Count Transmission/Receive Done \nNote: Write 1 to clear this bit. 1 1 read-write 0 Transmission/ receive is not finished when the PECEN is set #0 1 Transmission/ receive is finished when the PECEN is set #1 BUSTO Bus Time-out Status \nNote: In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Write 1 to clear this bit. 5 1 read-write 0 There is no any time-out or external clock time-out #0 1 The time-out or external clock time-out occurred #1 BUSY Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected 0 1 read-write 0 The bus is IDLE (both SCLK and SDA High) #0 1 The bus is busy #1 CLKTO Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit. 6 1 read-write 0 The cumulative clock low has no any time-out #0 1 The cumulative clock low time-out occurred #1 PECERR PEC Error in Reception \nNote: Write 1 to clear this bit. 2 1 read-write 0 The PEC value equals the received PEC data packet #0 1 The PEC value doesn't match the receive PEC data packet #1 SCTLDIN Bus Suspend or Control Signal Input Status 4 1 read-write 0 The input status of SUSCON pin is 0 #0 1 The input status of SUSCON pin is 1 #1 I2C_BUSTCTL I2C_BUSTCTL I2C Bus Management Timer Control Register 0x48 read-write n 0x0 0x0 BUSTOEN Bus Time Out Enable Bit 0 1 read-write 0 The bus clock low time-out detection Disabled #0 1 The bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) #1 BUSTOIEN Time-out Interrupt Enable Bit 2 1 read-write 0 The SCLK low time-out interrupt iDisabled.\nThe bus IDLE time-out interrupt Disabled #0 1 The SCLK low time-out interrupt Enabled.\nThe bus IDLE time-out interrupt Enabled #1 CLKTOEN Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP 1 1 read-write 0 The cumulative clock low time-out detection Disabled #0 1 The cumulative clock low time-out detection Enabled #1 CLKTOIEN Extended Clock Time Out Interrupt Enable Bit 3 1 read-write 0 The time extended interrupt Disabled #0 1 The time extended interrupt Enabled #1 PECIEN Packet Error Checking Byte Count Done Interrupt Enable Bit 5 1 read-write 0 The byte count done interrupt Disabled #0 1 The byte count done interrupt Enabled #1 TORSTEN Time Out Reset Enable Bit 4 1 read-write 0 I2C state machine reset Disabled #0 1 I2C state machine reset Enabled. (The clock and data bus will be released to high) #1 I2C_BUSTOUT I2C_BUSTOUT I2C Bus Management Timer Register 0x58 read-write n 0x0 0x0 BUSTO Bus Management Time-out Value\nIndicate the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 0 8 read-write I2C_CLKDIV I2C_CLKDIV I2C Clock Divided Register 0x10 read-write n 0x0 0x0 DIVIDER I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4. 0 8 read-write I2C_CLKTOUT I2C_CLKTOUT I2C Bus Management Clock Low Timer Register 0x5C read-write n 0x0 0x0 CLKTO Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 0 8 read-write I2C_CTL I2C_CTL I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control 2 1 read-write I2CEN I2C Controller Enable Bit 6 1 read-write 0 I2C Controller Disabled #0 1 I2C Controller Enabled #1 INTEN Enable Interrupt 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically. 4 1 read-write I2C_DAT I2C_DAT I2C Data Register 0x8 read-write n 0x0 0x0 DAT I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 0 8 read-write I2C_PKTCRC I2C_PKTCRC I2C Packet Error Checking Byte Value Register 0x54 read-only n 0x0 0x0 PECCRC Packet Error Checking Byte Value 0 8 read-only I2C_PKTSIZE I2C_PKTSIZE I2C Packet Error Checking Byte Number Register 0x50 read-write n 0x0 0x0 PLDSIZE Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 255 Bytes. \nNotice: The byte number counting includes address, command code, and data frame. 0 8 read-write I2C_STATUS I2C_STATUS I2C Status Register 0xC read-only n 0x0 0x0 STATUS I2C Status\n2. If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed. 0 8 read-only I2C_TOCTL I2C_TOCTL I2C Time-out Control Register 0x14 read-write n 0x0 0x0 TOCDIV4 Time-out Counter Input Clock Divided by 4\nWhen Enabled, The time-out period is extend 4 times. 1 1 read-write 0 Time-Out Counter Input Clock Divided Disabled #0 1 Time-Out Counter Input Clock Divided Enabled #1 TOCEN Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-Out Counter Disabled #0 1 Time-Out Counter Enabled #1 TOIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2C_WKCTL I2C_WKCTL I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKEN I2C Wake-up Enable Bit 0 1 read-write 0 I2C wake-up function Disabled #0 1 I2C wake-up function Enabled #1 I2C_WKSTS I2C_WKSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKIF I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write NMI NMI Register Map NMI 0x0 0x0 0x8 registers n NMIEN NMIEN NMI Source Interrupt Enable Register 0x0 read-write n 0x0 0x0 BODOUT BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 BOD NMI source Disabled #0 1 BOD NMI source Enabled #1 CLKFAIL Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 Clock fail detected interrupt NMI source Disabled #0 1 Clock fail detected interrupt NMI source Enabled #1 EINT0 External Interrupt From PA.0, PD.2 or PE.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 1 read-write 0 External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled #0 1 External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled #1 EINT1 External Interrupt From PB.0, PD.3 or PE.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 9 1 read-write 0 External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled #0 1 External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled #1 EINT2 External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 10 1 read-write 0 External interrupt from PC.0 pin NMI source Disabled #0 1 External interrupt from PC.0 pin NMI source Enabled #1 EINT3 External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 11 1 read-write 0 External interrupt from PD.0 pin NMI source Disabled #0 1 External interrupt from PD.0 pin NMI source Enabled #1 EINT4 External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 12 1 read-write 0 External interrupt from PE.0 pin NMI source Disabled #0 1 External interrupt from PE.0 pin NMI source Enabled #1 EINT5 External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 13 1 read-write 0 External interrupt from PF.0 pin NMI source Disabled #0 1 External interrupt from PF.0 pin NMI source Enabled #1 IRC_INT IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 IRC TRIM NMI source Disabled #0 1 IRC TRIM NMI source Enabled #1 PWRWU_INT Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 Power-down mode wake-up NMI source Disabled #0 1 Power-down mode wake-up NMI source Enabled #1 RTC_INT RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 RTC NMI source Disabled #0 1 RTC NMI source Enabled #1 TAMPER_INT TAMPER_INT NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 Backup register tamper detected interrupt.NMI source Disabled #0 1 Backup register tamper detected interrupt.NMI source Enabled #1 UART0_INT UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 14 1 read-write 0 UART0 NMI source Disabled #0 1 UART0 NMI source Enabled #1 UART1_INT UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 15 1 read-write 0 UART1 NMI source Disabled #0 1 UART1 NMI source Enabled #1 NMISTS NMISTS NMI Source Interrupt Status Register 0x4 read-only n 0x0 0x0 BODOUT BOD Interrupt Flag (Read Only) 0 1 read-only 0 BOD interrupt is deasserted #0 1 BOD interrupt is asserted #1 CLKFAIL Clock Fail Detected Interrupt Flag (Read Only) 4 1 read-only 0 Clock fail detected interrupt is deasserted #0 1 Clock fail detected interrupt is asserted #1 EINT0 External Interrupt From PA.0, PD.2 or PE.4 Pin Interrupt Flag (Read Only) 8 1 read-only 0 External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted #0 1 External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted #1 EINT1 External Interrupt From PB.0, PD.3 or PE.5 Pin Interrupt Flag (Read Only) 9 1 read-only 0 External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted #0 1 External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted #1 EINT2 External Interrupt From PC.0 Pin Interrupt Flag (Read Only) 10 1 read-only 0 External Interrupt from PC.0 interrupt is deasserted #0 1 External Interrupt from PC.0 interrupt is asserted #1 EINT3 External Interrupt From PD.0 Pin Interrupt Flag (Read Only) 11 1 read-only 0 External Interrupt from PD.0 interrupt is deasserted #0 1 External Interrupt from PD.0 interrupt is asserted #1 EINT4 External Interrupt From PE.0 Pin Interrupt Flag (Read Only) 12 1 read-only 0 External Interrupt from PE.0 interrupt is deasserted #0 1 External Interrupt from PE.0 interrupt is asserted #1 EINT5 External Interrupt From PF.0 Pin Interrupt Flag (Read Only) 13 1 read-only 0 External Interrupt from PF.0 interrupt is deasserted #0 1 External Interrupt from PF.0 interrupt is asserted #1 IRC_INT IRC TRIM Interrupt Flag (Read Only) 1 1 read-only 0 HIRC TRIM interrupt is deasserted #0 1 HIRC TRIM interrupt is asserted #1 PWRWU_INT Power-down Mode Wake-up Interrupt Flag (Read Only) 2 1 read-only 0 Power-down mode wake-up interrupt is deasserted #0 1 Power-down mode wake-up interrupt is asserted #1 RTC_INT RTC Interrupt Flag (Read Only) 6 1 read-only 0 RTC interrupt is deasserted #0 1 RTC interrupt is asserted #1 TAMPER_INT TAMPER_INT Interrupt Flag (Read Only) 7 1 read-only 0 Backup register tamper detected interrupt is deasserted #0 1 Backup register tamper detected interrupt is asserted #1 UART0_INT UART0 Interrupt Flag (Read Only) 14 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 UART1_INT UART1 Interrupt Flag (Read Only) 15 1 read-only 0 UART1 interrupt is deasserted #0 1 UART1 interrupt is asserted #1 NVIC NVIC Register Map NVIC 0x0 0x0 0x8 registers n 0x100 0x8 registers n 0x180 0x8 registers n 0x200 0x8 registers n 0x300 0x4 registers n 0x33C 0x4 registers n 0x80 0x8 registers n 0xE00 0x4 registers n IABR1 NVIC_IABR1 IRQ0 ~ IRQ63 Active Bit Register 0x200 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 IABR2 NVIC_IABR2 IRQ0 ~ IRQ63 Active Bit Register 0x204 read-write n 0x0 0x0 ACTIVE Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. 0 32 read-write 0 interrupt not active 0 1 interrupt active 1 ICER1 NVIC_ICER1 IRQ0 ~ IRQ63 Clear-enable Control Register 0x80 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICER2 NVIC_ICER2 IRQ0 ~ IRQ63 Clear-enable Control Register 0x84 read-write n 0x0 0x0 CALENA Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Disabled.\nInterrupt Enabled 1 ICPR1 NVIC_ICPR1 IRQ0 ~ IRQ63 Clear-pending Control Register 0x180 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 ICPR2 NVIC_ICPR2 IRQ0 ~ IRQ63 Clear-pending Control Register 0x184 read-write n 0x0 0x0 CALPEND Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Removes pending state an interrupt.\nInterrupt is pending 1 IPR1 NVIC_IPR1 IRQ0 ~ IRQ63 Priority Control Register 0x300 read-write n 0x0 0x0 PRI_4n_0 Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority 4 4 read-write PRI_4n_1 Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority 12 4 read-write PRI_4n_2 Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority 20 4 read-write PRI_4n_3 Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority 28 4 read-write IPR2 NVIC_IPR2 IRQ0 ~ IRQ63 Priority Control Register 0x33C read-write n 0x0 0x0 PRI_4n_0 Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority 4 4 read-write PRI_4n_1 Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority 12 4 read-write PRI_4n_2 Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority 20 4 read-write PRI_4n_3 Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority 28 4 read-write ISER1 NVIC_ISER1 IRQ0 ~ IRQ63 Set-enable Control Register 0x0 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISER2 NVIC_ISER2 IRQ0 ~ IRQ63 Set-enable Control Register 0x4 read-write n 0x0 0x0 SETENA Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt Disabled 0 1 Interrupt Enabled 1 ISPR1 NVIC_ISPR1 IRQ0 ~ IRQ63 Set-pending Control Register 0x100 read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 ISPR2 NVIC_ISPR2 IRQ0 ~ IRQ63 Set-pending Control Register 0x104 read-write n 0x0 0x0 SETPEND Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation: 0 32 read-write 0 No effect.\nInterrupt is not pending 0 1 Changes interrupt state to pending.\nInterrupt is pending 1 STIR STIR Software Trigger Interrupt Registers 0xE00 read-write n 0x0 0x0 INTID Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write PDMA PDMA Register Map PDMA 0x0 0x400 0x30 registers n 0x434 0x1C registers n 0x480 0x8 registers n ABTSTS PDMA_ABTSTS PDMA Channel Read/Write Target Abort Flag Register 0x420 read-write n 0x0 0x0 ABTIFn PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. 0 12 read-write 0 No AHB bus ERROR response received when channel n transfer 0 1 AHB bus ERROR response received when channel n transfer 1 CHCTL PDMA_CHCTL PDMA Channel Control Register 0x400 read-write n 0x0 0x0 CHENn PDMA Channel Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote1: If software stops the corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit. 0 12 read-write 0 PDMA channel [n] Disabled 0 1 PDMA channel [n] Enabled 1 INTEN PDMA_INTEN PDMA Interrupt Enable Register 0x418 read-write n 0x0 0x0 INTENn PDMA Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt. 0 12 read-write 0 PDMA channel n interrupt Disabled 0 1 PDMA channel n interrupt Enabled 1 INTSTS PDMA_INTSTS PDMA Interrupt Status Register 0x41C read-write n 0x0 0x0 ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read-only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 0 1 read-write 0 No AHB bus ERROR response received #0 1 AHB bus ERROR response received #1 REQTOFn Request Time-out Flag for Each Channel [N]\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits. 8 8 read-write 0 No request time-out 0 1 Peripheral request time-out 1 TDIF Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 1 1 read-only 0 Not finished yet #0 1 PDMA channel has finished transmission #1 TEIF Table Empty Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode. User can read TEIF register to indicate which channel finished transfer. 2 1 read-only 0 PDMA channel transfer is not finished #0 1 PDMA channel transfer is finished and the operation is in idle state #1 PRICLR PDMA_PRICLR PDMA Fixed Priority Clear Register 0x414 write-only n 0x0 0x0 FPRICLRn PDMA Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote1: User can read PDMA_PRISET register to know the channel priority. 0 12 write-only 0 No effect 0 1 Clear PDMA channel [n] fixed priority setting 1 PRISET PDMA_PRISET PDMA Fixed Priority Setting Register 0x410 read-write n 0x0 0x0 FPRISETn PDMA Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote1: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 0 12 read-write 0 No effect.\nCorresponding PDMA channel is round-robin priority 0 1 Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority 1 REQSEL0_3 PDMA_REQSEL0_3 PDMA Request Source Select Register 0 0x480 read-write n 0x0 0x0 REQSRC0 Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral can't assign to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory. 0 5 read-write 1 Channel connects to SPI0_TX 1 11 Channel connects to PWM0_P1_RX 11 12 Channel connects to PWM0_P2_RX 12 13 Channel connects to PWM0_P3_RX 13 14 Channel connects to PWM1_P1_RX 14 15 Channel connects to PWM1_P2_RX 15 16 Channel connects to PWM1_P3_RX 16 17 Channel connects to SPI0_RX 17 18 Channel connects to SPI1_RX 18 19 Reserved. 19 2 Channel connects to SPI1_TX 2 20 Channel connects to UART0_RX 20 21 Channel connects to UART1_RX 21 22 Channel connects to UART2_RX 22 23 Channel connects to UART3_RX 23 3 Reserved. 3 31 Disable PDMA 31 4 Channel connects to UART0_TX 4 5 Channel connects to UART1_TX 5 6 Channel connects to UART2_TX 6 7 Channel connects to UART3_TX 7 8 Reserved. 8 9 Channel connects to ADC_RX 9 REQSRC1 Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 5 read-write REQSRC2 Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 5 read-write REQSRC3 Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 5 read-write REQSEL4_7 PDMA_REQSEL4_7 PDMA Request Source Select Register 1 0x484 read-write n 0x0 0x0 REQSRC4 Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 0 5 read-write REQSRC5 Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 8 5 read-write REQSRC6 Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 16 5 read-write REQSRC7 Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0. 24 5 read-write SCATBA PDMA_SCATBA PDMA Scatter-gather Descriptor Table Base Address Register 0x43C read-write n 0x0 0x0 SCATBA PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode. 16 16 read-write SCATSTS PDMA_SCATSTS PDMA Scatter-gather Table Empty Status Register 0x428 read-write n 0x0 0x0 TEMPTYFn Scatter-gather Table Empty Flag Register\nThis bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn (PDMA_SWREQ[11:0]) set to high or channel has finished transmission and the operation mode is Stop mode. User can write 1 to clear these bits. 0 12 read-write 0 PDMA channel scatter-gather table is not empty 0 1 PDMA channel scatter-gather table is empty and PDMA SWREQ has be set 1 STOP PDMA_STOP PDMA Transfer Stop Control Register 0x404 write-only n 0x0 0x0 STOPn PDMA Transfer Stop Control Register (Write Only)\nUser can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).\nBy bit field:\nBy write 0xFFFF_FFFF to PDMA_STOP:\nSetting all PDMA_STOP bit to '1' will generate software reset to reset internal state machine (the DSCT will not be reset). When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'. \nNote1: User can read channel enable bit to know if the on-going transfer is finished. 0 12 write-only 0 No effect 0 1 Stop PDMA transfer[n]. When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag 1 SWREQ PDMA_SWREQ PDMA Software Request Register 0x408 write-only n 0x0 0x0 SWREQn PDMA Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored. 0 12 write-only 0 No effect 0 1 Generate a software request 1 TACTSTS PDMA_TACTSTS PDMA Transfer Active Flag Register 0x42C read-only n 0x0 0x0 TXACTFn Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active. 0 12 read-only 0 PDMA channel is not finished 0 1 PDMA channel is active 1 TDSTS PDMA_TDSTS PDMA Channel Transfer Done Flag Register 0x424 read-write n 0x0 0x0 TDIFn Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 0 12 read-write 0 PDMA channel transfer has not finished 0 1 PDMA channel has finished transmission 1 TOC0_1 PDMA_TOC0_1 PDMA Time-out Counter Ch1 and Ch0 Register 0x440 read-write n 0x0 0x0 TOC0 Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock. 0 16 read-write TOC1 Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock. 16 16 read-write TOC2_3 PDMA_TOC2_3 PDMA Time-out Counter Ch3 and Ch2 Register 0x444 read-write n 0x0 0x0 TOC2 Time-out Period Counter for Channel 2\nThis controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock. 0 16 read-write TOC3 Time-out Period Counter for Channel 3\nThis controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock. 16 16 read-write TOC4_5 PDMA_TOC4_5 PDMA Time-out Counter Ch5 and Ch4 Register 0x448 read-write n 0x0 0x0 TOC4 Time-out Period Counter for Channel 4\nThis controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock. 0 16 read-write TOC5 Time-out Period Counter for Channel 5\nThis controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock. 16 16 read-write TOC6_7 PDMA_TOC6_7 PDMA Time-out Counter Ch7 and Ch6 Register 0x44C read-write n 0x0 0x0 TOC6 Time-out Period Counter for Channel 6\nThis controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock. 0 16 read-write TOC7 Time-out Period Counter for Channel 7\nThis controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock. 16 16 read-write TOUTEN PDMA_TOUTEN PDMA Time-out Enable Register 0x434 read-write n 0x0 0x0 TOUTENn PDMA Time-out Enable Bits 0 8 read-write 0 PDMA Channel n time-out function Disable 0 1 PDMA Channel n time-out function Enable 1 TOUTIEN PDMA_TOUTIEN PDMA Time-out Interrupt Enable Register 0x438 read-write n 0x0 0x0 TOUTIENn PDMA Time-out Interrupt Enable Bits 0 8 read-write 0 PDMA Channel n time-out interrupt Disable 0 1 PDMA Channel n time-out interrupt Enable 1 TRGSTS PDMA_TRGSTS PDMA Channel Request Status Register 0x40C read-only n 0x0 0x0 REQSTSn PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote1: If software stops corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit. 0 12 read-only 0 PDMA Channel n has no request 0 1 PDMA Channel n has a request 1 PWM0 PWM Register Map PWM 0x0 0x0 0x2C registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x30 registers n 0x340 0x10 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x44 registers n 0xF8 0x14 registers n PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nReserved #0 1 Reserved.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0NFEN PWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN PWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEBEN System Fail As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN System Fail As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT1 PWM_CNT1 PWM Counter Register 1 0x94 read-write n 0x0 0x0 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT3 PWM_CNT3 PWM Counter Register 3 0x9C read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNT5 PWM_CNT5 PWM Counter Register 5 0xA4 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLRn Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 No effect 0 1 Clear 16-bit PWM counter to 0000H 1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTENn PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM Counter and clock prescaler Stop Running 0 1 PWM Counter and clock prescaler Start Running 1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each PWM channel are independent #0 1 Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1 #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn Enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 WINLDENn Window Load Enable Bit\nEach bit n controls the corresponding PWM channel n. 8 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success 1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODEn PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 16 6 read-write 0 Auto-reload mode 0 1 One-shot mode 1 CNTTYPEn PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 0 12 read-write 0 Up counter type (supports in capture mode) 00 1 Down count type (supports in capture mode) 01 10 Up-down counter type 10 11 Reserved. 11 OUTMODEn PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) Enable Bit (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion on the pin pair Disabled #0 1 Dead-time insertion on the pin pair Enabled #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4 0x78 read-write n 0x0 0x0 PWM_EADCTS0 PWM_EADCTS0 PWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 PWM_CH0 Trigger EADC Disabled #0 1 PWM_CH0 Trigger EADC Enabled #1 TRGEN1 PWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 PWM_CH1 Trigger EADC Disabled #0 1 PWM_CH1 Trigger EADC Enabled #1 TRGEN2 PWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 PWM_CH2 Trigger EADC Disabled #0 1 PWM_CH2 Trigger EADC Enabled #1 TRGEN3 PWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 PWM_CH3 Trigger EADC Disabled #0 1 PWM_CH3 Trigger EADC Enabled #1 TRGSEL0 PWM_CH0 Trigger EADC Source Select 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL1 PWM_CH1 Trigger EADC Source Select 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL2 PWM_CH2 Trigger EADC Source Select 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL3 PWM_CH3 Trigger EADC Source Select 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 PWM_EADCTS1 PWM_EADCTS1 PWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 PWM_CH4 Trigger EADC Disabled #0 1 PWM_CH4 Trigger EADC Enabled #1 TRGEN5 PWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 PWM_CH5 Trigger EADC Disabled #0 1 PWM_CH5 Trigger EADC Enabled #1 TRGSEL4 PWM_CH4 Trigger EADC Source Select 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL5 PWM_CH5 Trigger EADC Source Select 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_FTCBUF0_1 PWM_FTCBUF0_1 PWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only PWM_FTCBUF2_3 PWM_FTCBUF2_3 PWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 PWM_FTCBUF4_5 PWM_FTCBUF4_5 PWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 PWM_FTCI PWM_FTCI PWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMDn PWM FTCMPDAT Down Indicator 8 3 read-write FTCMUn PWM FTCMPDAT Up Indicator 0 3 read-write PWM_FTCMPDAT0_1 PWM_FTCMPDAT0_1 PWM Free Trigger Compare Register 0 0x100 read-write n 0x0 0x0 FTCMP PWM Free Trigger Compare Register\nFTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_FTCMPDAT2_3 PWM_FTCMPDAT2_3 PWM Free Trigger Compare Register 2 0x104 read-write n 0x0 0x0 PWM_FTCMPDAT4_5 PWM_FTCMPDAT4_5 PWM Free Trigger Compare Register 4 0x108 read-write n 0x0 0x0 PWM_IFA PWM_IFA PWM Interrupt Flag Accumulator Register 0xF0 read-write n 0x0 0x0 IFAEN0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Enable Bit 7 1 read-write 0 PWM_CH0 and PWM_CH1 interrupt flag accumulator Disabled #0 1 PWM_CH0 and PWM_CH1 interrupt flag accumulator Enabled #1 IFAEN2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Enable Bit 15 1 read-write 0 PWM_CH2 and PWM_CH3 interrupt flag accumulator Disabled #0 1 PWM_CH2 and PWM_CH3 interrupt flag accumulator Enabled #1 IFAEN4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit 23 1 read-write 0 PWM_CH4 and PWM_CH5 interrupt flag accumulator Disabled #0 1 PWM_CH4 and PWM_CH5 interrupt flag accumulator Enabled #1 IFCNT0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. \nIFAIF0_1 (PWM_INTSTS0[7]) will be set in every IFCNT0_1+1 times of PWM period. 0 4 read-write IFCNT2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. \nIFAIF2_3 (PWM_INTSTS0[15]) will be set in every IFCNT2_3+1 times of PWM period. 8 4 read-write IFCNT4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. \nIFAIF4_5 (PWM_INTSTS0[23]) will be set in every IFCNT4_5+1 times of PWM period. 16 4 read-write IFSEL0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select 4 3 read-write 0 CNT equal to Zero in channel 0 #000 1 CNT equal to PERIOD in channel 0 #001 2 CNT equal to CMPU in channel 0 #010 3 CNT equal to CMPD in channel 0 #011 4 CNT equal to Zero in channel 1 #100 5 CNT equal to PERIOD in channel 1 #101 6 CNT equal to CMPU in channel 1 #110 7 CNT equal to CMPD in channel 1 #111 IFSEL2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Source Select 12 3 read-write 0 CNT equal to Zero in channel 2 #000 1 CNT equal to PERIOD in channel 2 #001 2 CNT equal to CMPU in channel 2 #010 3 CNT equal to CMPD in channel 2 #011 4 CNT equal to Zero in channel 3 #100 5 CNT equal to PERIOD in channel 3 #101 6 CNT equal to CMPU in channel 3 #110 7 CNT equal to CMPD in channel 3 #111 IFSEL4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Source Select 20 3 read-write 0 CNT equal to Zero in channel 4 #000 1 CNT equal to PERIOD in channel 4 #001 2 CNT equal to CMPU in channel 4 #010 3 CNT equal to CMPD in channel 4 #011 4 CNT equal to Zero in channel 5 #100 5 CNT equal to PERIOD in channel 5 #101 6 CNT equal to CMPU in channel 5 #110 7 CNT equal to CMPD in channel 5 #111 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 IFAIEN0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit 7 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable Bit 15 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable Bit 23 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 PIENn PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 6 read-write 0 Period point interrupt Disabled 0 1 Period point interrupt Enabled 1 ZIENn PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 0 6 read-write 0 Zero point interrupt Disabled 0 1 Zero point interrupt Enabled 1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write IFAIF0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it. 7 1 read-write IFAIF2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it. 15 1 read-write IFAIF4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it. 23 1 read-write PIFn PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PWM_PERIODn; software can write 1 to clear this bit to 0. Each bit n controls the corresponding PWM channel n. 8 6 read-write ZIFn PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches 0; software can write 1 to clear this bit to 0. 0 6 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKESTS1 PWM Channel1 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKESTS2 PWM Channel2 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKESTS3 PWM Channel3 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKESTS4 PWM Channel4 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKESTS5 PWM Channel5 Edge-detect Brake Status 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 BRKLIF0 PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_LOAD PWM_LOAD PWM Load Register 0x28 read-write n 0x0 0x0 LOADn Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 0 6 read-write 0 No effect.\nNo load window is set 0 1 Set load window of window loading mode.\nLoad window is set 1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Bits\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF1 PWM_PBUF1 PWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF3 PWM_PBUF3 PWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PBUF5 PWM_PBUF5 PWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT0/1 #01 2 PWM_FCAPDAT0/1 #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT2/3 #01 2 PWM_FCAPDAT2/3 #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT4/5 #01 2 PWM_FCAPDAT4/5 #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 PWM_FCAPDAT0/1 is the first captured data to memory #0 1 PWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 PWM_FCAPDAT2/3 is the first captured data to memory #0 1 PWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 PWM_FCAPDAT4/5 is the first captured data to memory #0 1 PWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write PWM_PERIOD1 PWM_PERIOD1 PWM Period Register 1 0x34 read-write n 0x0 0x0 PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD3 PWM_PERIOD3 PWM Period Register 3 0x3C read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_PERIOD5 PWM_PERIOD5 PWM Period Register 5 0x44 read-write n 0x0 0x0 PWM_PHS0_1 PWM_PHS0_1 PWM Counter Phase Register 0 0x80 read-write n 0x0 0x0 PHS PWM Synchronous Start Phase Bits\nPHS determines the PWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write PWM_PHS2_3 PWM_PHS2_3 PWM Counter Phase Register 2 0x84 read-write n 0x0 0x0 PWM_PHS4_5 PWM_PHS4_5 PWM Counter Phase Register 4 0x88 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control Bits\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSENn PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM synchronous start function Disabled 0 1 PWM synchronous start function Enabled 1 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable Bit (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.\nNote: This bit only present in PWM0_BA. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGFn EADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit. 16 6 read-write 0 No EADC start of conversion trigger event has occurred 0 1 An EADC start of conversion trigger event has occurred 1 CNTMAXFn Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit. 0 6 read-write 0 The time-base counter never reached its maximum value 0xFFFF 0 1 The time-base counter reached its maximum value 1 SYNCINFn Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 8 3 read-write 0 No SYNC_IN event has occurred 0 1 An SYNC_IN event has occurred, software can write 1 to clear this bit 1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 3 write-only PWM_SWSYNC PWM_SWSYNC PWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNCn Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 0 3 read-write PWM_SYNC PWM_SYNC PWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIRn PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 24 3 read-write 0 Control PWM counter count decrement after synchronizing 0 1 Control PWM counter count increment after synchronizing 1 PHSENn SYNC Phase Enable Bit\nEach bit n controls corresponding PWM channel n. 0 3 read-write 0 PWM counter load PHS value Disabled 0 1 PWM counter load PHS value Enabled 1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the positive edge detector #0 1 The inversed state of pin SYNC is passed to the positive edge detector #1 SINSRCn PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 8 6 read-write 0 Synchronize source from SYNC_IN or SWSYNC 00 1 Counter equal to 0 01 10 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 10 11 SYNC_OUT will not be generated 11 SNFLTEN PWM0_SYNC_IN Noise Filter Enable Bit 16 1 read-write 0 Noise filter of input pin PWM0_SYNC_IN Disabled #0 1 Noise filter of input pin PWM0_SYNC_IN Enabled #1 PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 PWM period (center) point output Low 01 10 PWM period (center) point output High 10 11 PWM period (center) point output Toggle 11 ZPCTLn PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 PWM zero point output Low 01 10 PWM zero point output High 10 11 PWM zero point output Toggle 11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 PWM compare down point output Low 01 10 PWM compare down point output High 10 11 PWM compare down point output Toggle 11 CMPUCTLn PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 PWM compare up point output Low 01 10 PWM compare up point output High 10 11 PWM compare up point output Toggle 11 PWM1 PWM Register Map PWM 0x0 0x0 0x2C registers n 0x110 0x8 registers n 0x120 0x4 registers n 0x200 0x4C registers n 0x250 0x8 registers n 0x30 0x18 registers n 0x304 0x30 registers n 0x340 0x10 registers n 0x50 0x18 registers n 0x70 0xC registers n 0x80 0xC registers n 0x90 0x18 registers n 0xB0 0x44 registers n 0xF8 0x14 registers n PWM_BNF PWM_BNF PWM Brake Noise Filter Register 0xC0 read-write n 0x0 0x0 BK0SRC Brake 0 Pin Source Select\nFor PWM0 setting: 16 1 read-write 0 Brake 0 pin source come from PWM0_BRAKE0.\nReserved #0 1 Reserved.\nBrake 0 pin source come from PWM0_BRAKE0 #1 BK1SRC Brake 1 Pin Source Select\nFor PWM0 setting: 24 1 read-write 0 Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1 #0 1 Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1 #1 BRK0FCNT Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. 4 3 read-write BRK0NFEN PWM Brake 0 Noise Filter Enable Bit 0 1 read-write 0 Noise filter of PWM Brake 0 Disabled #0 1 Noise filter of PWM Brake 0 Enabled #1 BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection 1 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK0PINV Brake 0 Pin Inverse 7 1 read-write 0 The state of pin PWMx_BRAKE0 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector #1 BRK1FCNT Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 12 3 read-write BRK1NFEN PWM Brake 1 Noise Filter Enable Bit 8 1 read-write 0 Noise filter of PWM Brake 1 Disabled #0 1 Noise filter of PWM Brake 1 Enabled #1 BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection 9 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 BRK1PINV Brake 1 Pin Inverse 15 1 read-write 0 The state of pin PWMx_BRAKE1 is passed to the negative edge detector #0 1 The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector #1 PWM_BRKCTL0_1 PWM_BRKCTL0_1 PWM Brake Edge Detect Control Register 0 0xC8 read-write n 0x0 0x0 BRKAEVEN PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 2 read-write 0 PWM even channel level-detect brake function not affect channel output #00 1 PWM even channel output tri-state when level-detect brake happened #01 2 PWM even channel output low level when level-detect brake happened #10 3 PWM even channel output high level when level-detect brake happened #11 BRKAODD PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 18 2 read-write 0 PWM odd channel level-detect brake function not affect channel output #00 1 PWM odd channel output tri-state when level-detect brake happened #01 2 PWM odd channel output low level when level-detect brake happened #10 3 PWM odd channel output high level when level-detect brake happened #11 BRKP0EEN PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 BKP0 pin as edge-detect brake source Disabled #0 1 BKP0 pin as edge-detect brake source Enabled #1 BRKP0LEN BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWMx_BRAKE0 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE0 pin as level-detect brake source Enabled #1 BRKP1EEN PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 BKP1 pin as edge-detect brake source Disabled #0 1 BKP1 pin as edge-detect brake source Enabled #1 BRKP1LEN BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWMx_BRAKE1 pin as level-detect brake source Disabled #0 1 PWMx_BRAKE1 pin as level-detect brake source Enabled #1 SYSEBEN System Fail As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 7 1 read-write 0 System Fail condition as edge-detect brake source Disabled #0 1 System Fail condition as edge-detect brake source Enabled #1 SYSLBEN System Fail As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 15 1 read-write 0 System Fail condition as level-detect brake source Disabled #0 1 System Fail condition as level-detect brake source Enabled #1 PWM_BRKCTL2_3 PWM_BRKCTL2_3 PWM Brake Edge Detect Control Register 2 0xCC read-write n 0x0 0x0 PWM_BRKCTL4_5 PWM_BRKCTL4_5 PWM Brake Edge Detect Control Register 4 0xD0 read-write n 0x0 0x0 PWM_CAPCTL PWM_CAPCTL PWM Capture Control Register 0x204 read-write n 0x0 0x0 CAPENn Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated 0 1 Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) 1 CAPINVn Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n. 8 6 read-write 0 Capture source inverter Disabled 0 1 Capture source inverter Enabled. Reverse the input signal from GPIO 1 FCRLDENn Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 24 6 read-write 0 Falling capture reload counter Disabled 0 1 Falling capture reload counter Enabled 1 RCRLDENn Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n. 16 6 read-write 0 Rising capture reload counter Disabled 0 1 Rising capture reload counter Enabled 1 PWM_CAPIEN PWM_CAPIEN PWM Capture Interrupt Enable Register 0x250 read-write n 0x0 0x0 CAPFIENn PWM Capture Falling Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled. 8 6 read-write 0 Capture falling edge latch interrupt Disabled 0 1 Capture falling edge latch interrupt Enabled 1 CAPRIENn PWM Capture Rising Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled. 0 6 read-write 0 Capture rising edge latch interrupt Disabled 0 1 Capture rising edge latch interrupt Enabled 1 PWM_CAPIF PWM_CAPIF PWM Capture Interrupt Flag Register 0x254 read-write n 0x0 0x0 CFLIFn PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 8 6 read-write 0 No capture falling latch condition happened 0 1 Capture falling latch condition happened, this flag will be set to high 1 CRLIFn PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data. 0 6 read-write 0 No capture rising latch condition happened 0 1 Capture rising latch condition happened, this flag will be set to high 1 PWM_CAPINEN PWM_CAPINEN PWM Capture Input Enable Register 0x200 read-write n 0x0 0x0 CAPINENn Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0 0 1 PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin 1 PWM_CAPSTS PWM_CAPSTS PWM Capture Status Register 0x208 read-only n 0x0 0x0 CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CFLIF. 8 6 read-only CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CRLIF. 0 6 read-only PWM_CLKPSC0_1 PWM_CLKPSC0_1 PWM Clock Pre-scale Register 0 0x14 read-write n 0x0 0x0 CLKPSC PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1). 0 12 read-write PWM_CLKPSC2_3 PWM_CLKPSC2_3 PWM Clock Pre-scale Register 2 0x18 read-write n 0x0 0x0 PWM_CLKPSC4_5 PWM_CLKPSC4_5 PWM Clock Pre-scale Register 4 0x1C read-write n 0x0 0x0 PWM_CLKSRC PWM_CLKSRC PWM Clock Source Register 0x10 read-write n 0x0 0x0 ECLKSRC0 PWM_CH01 External Clock Source Select 0 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC2 PWM_CH23 External Clock Source Select 8 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 ECLKSRC4 PWM_CH45 External Clock Source Select 16 3 read-write 0 PWMx_CLK, x denotes 0 or 1 #000 1 TIMER0 overflow #001 2 TIMER1 overflow #010 3 TIMER2 overflow #011 4 TIMER3 overflow #100 PWM_CMPBUF0 PWM_CMPBUF0 PWM CMPDAT0 Buffer 0x31C read-only n 0x0 0x0 CMPBUF PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register. 0 16 read-only PWM_CMPBUF1 PWM_CMPBUF1 PWM CMPDAT1 Buffer 0x320 read-write n 0x0 0x0 PWM_CMPBUF2 PWM_CMPBUF2 PWM CMPDAT2 Buffer 0x324 read-write n 0x0 0x0 PWM_CMPBUF3 PWM_CMPBUF3 PWM CMPDAT3 Buffer 0x328 read-write n 0x0 0x0 PWM_CMPBUF4 PWM_CMPBUF4 PWM CMPDAT4 Buffer 0x32C read-write n 0x0 0x0 PWM_CMPBUF5 PWM_CMPBUF5 PWM CMPDAT5 Buffer 0x330 read-write n 0x0 0x0 PWM_CMPDAT0 PWM_CMPDAT0 PWM Comparator Register 0 0x50 read-write n 0x0 0x0 CMP PWM Comparator Register\nCMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_CMPDAT1 PWM_CMPDAT1 PWM Comparator Register 1 0x54 read-write n 0x0 0x0 PWM_CMPDAT2 PWM_CMPDAT2 PWM Comparator Register 2 0x58 read-write n 0x0 0x0 PWM_CMPDAT3 PWM_CMPDAT3 PWM Comparator Register 3 0x5C read-write n 0x0 0x0 PWM_CMPDAT4 PWM_CMPDAT4 PWM Comparator Register 4 0x60 read-write n 0x0 0x0 PWM_CMPDAT5 PWM_CMPDAT5 PWM Comparator Register 5 0x64 read-write n 0x0 0x0 PWM_CNT0 PWM_CNT0 PWM Counter Register 0 0x90 read-only n 0x0 0x0 CNT PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter. 0 16 read-only DIRF PWM Direction Indicator Flag (Read Only) 16 1 read-only 0 Counter is Down count #0 1 Counter is UP count #1 PWM_CNT1 PWM_CNT1 PWM Counter Register 1 0x94 read-write n 0x0 0x0 PWM_CNT2 PWM_CNT2 PWM Counter Register 2 0x98 read-write n 0x0 0x0 PWM_CNT3 PWM_CNT3 PWM Counter Register 3 0x9C read-write n 0x0 0x0 PWM_CNT4 PWM_CNT4 PWM Counter Register 4 0xA0 read-write n 0x0 0x0 PWM_CNT5 PWM_CNT5 PWM Counter Register 5 0xA4 read-write n 0x0 0x0 PWM_CNTCLR PWM_CNTCLR PWM Clear Counter Register 0x24 read-write n 0x0 0x0 CNTCLRn Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 No effect 0 1 Clear 16-bit PWM counter to 0000H 1 PWM_CNTEN PWM_CNTEN PWM Counter Enable Register 0x20 read-write n 0x0 0x0 CNTENn PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM Counter and clock prescaler Stop Running 0 1 PWM Counter and clock prescaler Start Running 1 PWM_CTL0 PWM_CTL0 PWM Control Register 0 0x0 read-write n 0x0 0x0 CTRLDn Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period. 0 6 read-write DBGHALT ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 30 1 read-write 0 ICE debug mode counter halt Disabled #0 1 ICE debug mode counter halt Enabled #1 DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects PWM output #0 1 ICE debug mode acknowledgement disabled #1 GROUPEN Group Function Enable Bit 24 1 read-write 0 The output waveform of each PWM channel are independent #0 1 Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1 #1 IMMLDENn Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn Enabled, WINLDENn and CTRLDn will be invalid. 16 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT 1 WINLDENn Window Load Enable Bit\nEach bit n controls the corresponding PWM channel n. 8 6 read-write 0 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit 0 1 PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success 1 PWM_CTL1 PWM_CTL1 PWM Control Register 1 0x4 read-write n 0x0 0x0 CNTMODEn PWM Counter Mode\nEach bit n controls the corresponding PWM channel n. 16 6 read-write 0 Auto-reload mode 0 1 One-shot mode 1 CNTTYPEn PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n. 0 12 read-write 0 Up counter type (supports in capture mode) 00 1 Down count type (supports in capture mode) 01 10 Up-down counter type 10 11 Reserved. 11 OUTMODEn PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode. 24 3 read-write 0 PWM independent mode 0 1 PWM complementary mode 1 PWM_DTCTL0_1 PWM_DTCTL0_1 PWM Dead-time Control Register 0 0x70 read-write n 0x0 0x0 DTCKSEL Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register. 24 1 read-write 0 Dead-time clock source from PWM_CLK #0 1 Dead-time clock source from prescaler output #1 DTCNT Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 12 read-write DTEN Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) Enable Bit (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register. 16 1 read-write 0 Dead-time insertion on the pin pair Disabled #0 1 Dead-time insertion on the pin pair Enabled #1 PWM_DTCTL2_3 PWM_DTCTL2_3 PWM Dead-time Control Register 2 0x74 read-write n 0x0 0x0 PWM_DTCTL4_5 PWM_DTCTL4_5 PWM Dead-time Control Register 4 0x78 read-write n 0x0 0x0 PWM_EADCTS0 PWM_EADCTS0 PWM Trigger EADC Source Select Register 0 0xF8 read-write n 0x0 0x0 TRGEN0 PWM_CH0 Trigger EADC Enable Bit 7 1 read-write 0 PWM_CH0 Trigger EADC Disabled #0 1 PWM_CH0 Trigger EADC Enabled #1 TRGEN1 PWM_CH1 Trigger EADC Enable Bit 15 1 read-write 0 PWM_CH1 Trigger EADC Disabled #0 1 PWM_CH1 Trigger EADC Enabled #1 TRGEN2 PWM_CH2 Trigger EADC Enable Bit 23 1 read-write 0 PWM_CH2 Trigger EADC Disabled #0 1 PWM_CH2 Trigger EADC Enabled #1 TRGEN3 PWM_CH3 Trigger EADC Enable Bit 31 1 read-write 0 PWM_CH3 Trigger EADC Disabled #0 1 PWM_CH3 Trigger EADC Enabled #1 TRGSEL0 PWM_CH0 Trigger EADC Source Select 0 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL1 PWM_CH1 Trigger EADC Source Select 8 4 read-write 0 PWM_CH0 zero point #0000 1 PWM_CH0 period point #0001 2 PWM_CH0 zero or period point #0010 3 PWM_CH0 up-count CMPDAT point #0011 4 PWM_CH0 down-count CMPDAT point #0100 5 PWM_CH1 zero point #0101 6 PWM_CH1 period point #0110 7 PWM_CH1 zero or period point #0111 8 PWM_CH1 up-count CMPDAT point #1000 9 PWM_CH1 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL2 PWM_CH2 Trigger EADC Source Select 16 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL3 PWM_CH3 Trigger EADC Source Select 24 4 read-write 0 PWM_CH2 zero point #0000 1 PWM_CH2 period point #0001 2 PWM_CH2 zero or period point #0010 3 PWM_CH2 up-count CMPDAT point #0011 4 PWM_CH2 down-count CMPDAT point #0100 5 PWM_CH3 zero point #0101 6 PWM_CH3 period point #0110 7 PWM_CH3 zero or period point #0111 8 PWM_CH3 up-count CMPDAT point #1000 9 PWM_CH3 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 PWM_EADCTS1 PWM_EADCTS1 PWM Trigger EADC Source Select Register 1 0xFC read-write n 0x0 0x0 TRGEN4 PWM_CH4 Trigger EADC Enable Bit 7 1 read-write 0 PWM_CH4 Trigger EADC Disabled #0 1 PWM_CH4 Trigger EADC Enabled #1 TRGEN5 PWM_CH5 Trigger EADC Enable Bit 15 1 read-write 0 PWM_CH5 Trigger EADC Disabled #0 1 PWM_CH5 Trigger EADC Enabled #1 TRGSEL4 PWM_CH4 Trigger EADC Source Select 0 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 TRGSEL5 PWM_CH5 Trigger EADC Source Select 8 4 read-write 0 PWM_CH4 zero point #0000 1 PWM_CH4 period point #0001 2 PWM_CH4 zero or period point #0010 3 PWM_CH4 up-count CMPDAT point #0011 4 PWM_CH4 down-count CMPDAT point #0100 5 PWM_CH5 zero point #0101 6 PWM_CH5 period point #0110 7 PWM_CH5 zero or period point #0111 8 PWM_CH5 up-count CMPDAT point #1000 9 PWM_CH5 down-count CMPDAT point #1001 10 PWM_CH0 up-count free CMPDAT point #1010 11 PWM_CH0 down-count free CMPDAT point #1011 12 PWM_CH2 up-count free CMPDAT point #1100 13 PWM_CH2 down-count free CMPDAT point #1101 14 PWM_CH4 up-count free CMPDAT point #1110 15 PWM_CH4 down-count free CMPDAT point #1111 PWM_FAILBRK PWM_FAILBRK PWM System Fail Brake Control Register 0xC4 read-write n 0x0 0x0 BODBRKEN Brown-out Detection Trigger PWM Brake Function 0 Enable Bit 1 1 read-write 0 Brake Function triggered by BOD Disabled #0 1 Brake Function triggered by BOD Enabled #1 CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit 3 1 read-write 0 Brake Function triggered by Core lockup detection Disabled #0 1 Brake Function triggered by Core lockup detection Enabled #1 CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit 0 1 read-write 0 Brake Function triggered by CSS detection Disabled #0 1 Brake Function triggered by CSS detection Enabled #1 PWM_FCAPDAT0 PWM_FCAPDAT0 PWM Falling Capture Data Register 0 0x210 read-only n 0x0 0x0 FCAPDAT PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_FCAPDAT1 PWM_FCAPDAT1 PWM Falling Capture Data Register 1 0x218 read-write n 0x0 0x0 PWM_FCAPDAT2 PWM_FCAPDAT2 PWM Falling Capture Data Register 2 0x220 read-write n 0x0 0x0 PWM_FCAPDAT3 PWM_FCAPDAT3 PWM Falling Capture Data Register 3 0x228 read-write n 0x0 0x0 PWM_FCAPDAT4 PWM_FCAPDAT4 PWM Falling Capture Data Register 4 0x230 read-write n 0x0 0x0 PWM_FCAPDAT5 PWM_FCAPDAT5 PWM Falling Capture Data Register 5 0x238 read-write n 0x0 0x0 PWM_FTCBUF0_1 PWM_FTCBUF0_1 PWM FTCMPDAT0_1 Buffer 0x340 read-only n 0x0 0x0 FTCMPBUF PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register. 0 16 read-only PWM_FTCBUF2_3 PWM_FTCBUF2_3 PWM FTCMPDAT2_3 Buffer 0x344 read-write n 0x0 0x0 PWM_FTCBUF4_5 PWM_FTCBUF4_5 PWM FTCMPDAT4_5 Buffer 0x348 read-write n 0x0 0x0 PWM_FTCI PWM_FTCI PWM FTCMPDAT Indicator Register 0x34C read-write n 0x0 0x0 FTCMDn PWM FTCMPDAT Down Indicator 8 3 read-write FTCMUn PWM FTCMPDAT Up Indicator 0 3 read-write PWM_FTCMPDAT0_1 PWM_FTCMPDAT0_1 PWM Free Trigger Compare Register 0 0x100 read-write n 0x0 0x0 FTCMP PWM Free Trigger Compare Register\nFTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. 0 16 read-write PWM_FTCMPDAT2_3 PWM_FTCMPDAT2_3 PWM Free Trigger Compare Register 2 0x104 read-write n 0x0 0x0 PWM_FTCMPDAT4_5 PWM_FTCMPDAT4_5 PWM Free Trigger Compare Register 4 0x108 read-write n 0x0 0x0 PWM_IFA PWM_IFA PWM Interrupt Flag Accumulator Register 0xF0 read-write n 0x0 0x0 IFAEN0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Enable Bit 7 1 read-write 0 PWM_CH0 and PWM_CH1 interrupt flag accumulator Disabled #0 1 PWM_CH0 and PWM_CH1 interrupt flag accumulator Enabled #1 IFAEN2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Enable Bit 15 1 read-write 0 PWM_CH2 and PWM_CH3 interrupt flag accumulator Disabled #0 1 PWM_CH2 and PWM_CH3 interrupt flag accumulator Enabled #1 IFAEN4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit 23 1 read-write 0 PWM_CH4 and PWM_CH5 interrupt flag accumulator Disabled #0 1 PWM_CH4 and PWM_CH5 interrupt flag accumulator Enabled #1 IFCNT0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. \nIFAIF0_1 (PWM_INTSTS0[7]) will be set in every IFCNT0_1+1 times of PWM period. 0 4 read-write IFCNT2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. \nIFAIF2_3 (PWM_INTSTS0[15]) will be set in every IFCNT2_3+1 times of PWM period. 8 4 read-write IFCNT4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. \nIFAIF4_5 (PWM_INTSTS0[23]) will be set in every IFCNT4_5+1 times of PWM period. 16 4 read-write IFSEL0_1 PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select 4 3 read-write 0 CNT equal to Zero in channel 0 #000 1 CNT equal to PERIOD in channel 0 #001 2 CNT equal to CMPU in channel 0 #010 3 CNT equal to CMPD in channel 0 #011 4 CNT equal to Zero in channel 1 #100 5 CNT equal to PERIOD in channel 1 #101 6 CNT equal to CMPU in channel 1 #110 7 CNT equal to CMPD in channel 1 #111 IFSEL2_3 PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Source Select 12 3 read-write 0 CNT equal to Zero in channel 2 #000 1 CNT equal to PERIOD in channel 2 #001 2 CNT equal to CMPU in channel 2 #010 3 CNT equal to CMPD in channel 2 #011 4 CNT equal to Zero in channel 3 #100 5 CNT equal to PERIOD in channel 3 #101 6 CNT equal to CMPU in channel 3 #110 7 CNT equal to CMPD in channel 3 #111 IFSEL4_5 PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Source Select 20 3 read-write 0 CNT equal to Zero in channel 4 #000 1 CNT equal to PERIOD in channel 4 #001 2 CNT equal to CMPU in channel 4 #010 3 CNT equal to CMPD in channel 4 #011 4 CNT equal to Zero in channel 5 #100 5 CNT equal to PERIOD in channel 5 #101 6 CNT equal to CMPU in channel 5 #110 7 CNT equal to CMPD in channel 5 #111 PWM_INTEN0 PWM_INTEN0 PWM Interrupt Enable Register 0 0xE0 read-write n 0x0 0x0 CMPDIENn PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 24 6 read-write 0 Compare down count interrupt Disabled 0 1 Compare down count interrupt Enabled 1 CMPUIENn PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 16 6 read-write 0 Compare up count interrupt Disabled 0 1 Compare up count interrupt Enabled 1 IFAIEN0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit 7 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable Bit 15 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 IFAIEN4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable Bit 23 1 read-write 0 Interrupt Flag accumulator interrupt Disabled #0 1 Interrupt Flag accumulator interrupt Enabled #1 PIENn PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode. 8 6 read-write 0 Period point interrupt Disabled 0 1 Period point interrupt Enabled 1 ZIENn PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode. 0 6 read-write 0 Zero point interrupt Disabled 0 1 Zero point interrupt Enabled 1 PWM_INTEN1 PWM_INTEN1 PWM Interrupt Enable Register 1 0xE4 read-write n 0x0 0x0 BRKEIEN0_1 PWM Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 Edge-detect Brake interrupt for channel0/1 Disabled #0 1 Edge-detect Brake interrupt for channel0/1 Enabled #1 BRKEIEN2_3 PWM Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 Edge-detect Brake interrupt for channel2/3 Disabled #0 1 Edge-detect Brake interrupt for channel2/3 Enabled #1 BRKEIEN4_5 PWM Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 Edge-detect Brake interrupt for channel4/5 Disabled #0 1 Edge-detect Brake interrupt for channel4/5 Enabled #1 BRKLIEN0_1 PWM Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 Level-detect Brake interrupt for channel0/1 Disabled #0 1 Level-detect Brake interrupt for channel0/1 Enabled #1 BRKLIEN2_3 PWM Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 Level-detect Brake interrupt for channel2/3 Disabled #0 1 Level-detect Brake interrupt for channel2/3 Enabled #1 BRKLIEN4_5 PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 Level-detect Brake interrupt for channel4/5 Disabled #0 1 Level-detect Brake interrupt for channel4/5 Enabled #1 PWM_INTSTS0 PWM_INTSTS0 PWM Interrupt Flag Register 0 0xE8 read-write n 0x0 0x0 CMPDIFn PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 24 6 read-write CMPUIFn PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 16 6 read-write IFAIF0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it. 7 1 read-write IFAIF2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it. 15 1 read-write IFAIF4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it. 23 1 read-write PIFn PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PWM_PERIODn; software can write 1 to clear this bit to 0. Each bit n controls the corresponding PWM channel n. 8 6 read-write ZIFn PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches 0; software can write 1 to clear this bit to 0. 0 6 read-write PWM_INTSTS1 PWM_INTSTS1 PWM Interrupt Flag Register 1 0xEC read-write n 0x0 0x0 BRKEIF0 PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 1 read-write 0 PWM channel0 edge-detect brake event do not happened #0 1 When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF1 PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 1 1 read-write 0 PWM channel1 edge-detect brake event do not happened #0 1 When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF2 PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 2 1 read-write 0 PWM channel2 edge-detect brake event do not happened #0 1 When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF3 PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 3 1 read-write 0 PWM channel3 edge-detect brake event do not happened #0 1 When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF4 PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 4 1 read-write 0 PWM channel4 edge-detect brake event do not happened #0 1 When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKEIF5 PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 5 1 read-write 0 PWM channel5 edge-detect brake event do not happened #0 1 When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKESTS0 PWM Channel0 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 16 1 read-write 0 PWM channel0 edge-detect brake state is released #0 1 When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKESTS1 PWM Channel1 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 17 1 read-write 0 PWM channel1 edge-detect brake state is released #0 1 When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKESTS2 PWM Channel2 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 18 1 read-write 0 PWM channel2 edge-detect brake state is released #0 1 When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKESTS3 PWM Channel3 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 19 1 read-write 0 PWM channel3 edge-detect brake state is released #0 1 When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKESTS4 PWM Channel4 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period. 20 1 read-write 0 PWM channel4 edge-detect brake state is released #0 1 When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKESTS5 PWM Channel5 Edge-detect Brake Status 21 1 read-write 0 PWM channel5 edge-detect brake state is released #0 1 When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 BRKLIF0 PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 1 read-write 0 PWM channel0 level-detect brake event do not happened #0 1 When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF1 PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 9 1 read-write 0 PWM channel1 level-detect brake event do not happened #0 1 When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF2 PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 10 1 read-write 0 PWM channel2 level-detect brake event do not happened #0 1 When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF3 PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 11 1 read-write 0 PWM channel3 level-detect brake event do not happened #0 1 When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF4 PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 12 1 read-write 0 PWM channel4 level-detect brake event do not happened #0 1 When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLIF5 PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register. 13 1 read-write 0 PWM channel5 level-detect brake event do not happened #0 1 When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear #1 BRKLSTS0 PWM Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 24 1 read-only 0 PWM channel0 level-detect brake state is released #0 1 When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state #1 BRKLSTS1 PWM Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 25 1 read-only 0 PWM channel1 level-detect brake state is released #0 1 When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state #1 BRKLSTS2 PWM Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 26 1 read-only 0 PWM channel2 level-detect brake state is released #0 1 When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state #1 BRKLSTS3 PWM Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 27 1 read-only 0 PWM channel3 level-detect brake state is released #0 1 When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state #1 BRKLSTS4 PWM Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 28 1 read-only 0 PWM channel4 level-detect brake state is released #0 1 When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state #1 BRKLSTS5 PWM Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period. 29 1 read-only 0 PWM channel5 level-detect brake state is released #0 1 When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state #1 PWM_LOAD PWM_LOAD PWM Load Register 0x28 read-write n 0x0 0x0 LOADn Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation: 0 6 read-write 0 No effect.\nNo load window is set 0 1 Set load window of window loading mode.\nLoad window is set 1 PWM_MSK PWM_MSK PWM Mask Data Register 0xBC read-write n 0x0 0x0 MSKDATn PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 Output logic low to PWMn 0 1 Output logic high to PWMn 1 PWM_MSKEN PWM_MSKEN PWM Mask Enable Register 0xB8 read-write n 0x0 0x0 MSKENn PWM Mask Enable Bits\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. 0 6 read-write 0 PWM output signal is non-masked 0 1 PWM output signal is masked and output MSKDATn data 1 PWM_PBUF0 PWM_PBUF0 PWM PERIOD0 Buffer 0x304 read-only n 0x0 0x0 PBUF PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register. 0 16 read-only PWM_PBUF1 PWM_PBUF1 PWM PERIOD1 Buffer 0x308 read-write n 0x0 0x0 PWM_PBUF2 PWM_PBUF2 PWM PERIOD2 Buffer 0x30C read-write n 0x0 0x0 PWM_PBUF3 PWM_PBUF3 PWM PERIOD3 Buffer 0x310 read-write n 0x0 0x0 PWM_PBUF4 PWM_PBUF4 PWM PERIOD4 Buffer 0x314 read-write n 0x0 0x0 PWM_PBUF5 PWM_PBUF5 PWM PERIOD5 Buffer 0x318 read-write n 0x0 0x0 PWM_PDMACAP0_1 PWM_PDMACAP0_1 PWM Capture Channel 01 PDMA Register 0x240 read-only n 0x0 0x0 CAPBUF PWM Capture PDMA Register (Read Only)\nThis register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA. 0 16 read-only PWM_PDMACAP2_3 PWM_PDMACAP2_3 PWM Capture Channel 23 PDMA Register 0x244 read-write n 0x0 0x0 PWM_PDMACAP4_5 PWM_PDMACAP4_5 PWM Capture Channel 45 PDMA Register 0x248 read-write n 0x0 0x0 PWM_PDMACTL PWM_PDMACTL PWM PDMA Control Register 0x23C read-write n 0x0 0x0 CAPMOD0_1 Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer 1 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT0/1 #01 2 PWM_FCAPDAT0/1 #10 3 Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 #11 CAPMOD2_3 Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer 9 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT2/3 #01 2 PWM_FCAPDAT2/3 #10 3 Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 #11 CAPMOD4_5 Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer 17 2 read-write 0 Reserved. #00 1 PWM_RCAPDAT4/5 #01 2 PWM_FCAPDAT4/5 #10 3 Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 #11 CAPORD0_1 Capture Channel 0/1 Rising/Falling Order 3 1 read-write 0 PWM_FCAPDAT0/1 is the first captured data to memory #0 1 PWM_RCAPDAT0/1 is the first captured data to memory #1 CAPORD2_3 Capture Channel 2/3 Rising/Falling Order 11 1 read-write 0 PWM_FCAPDAT2/3 is the first captured data to memory #0 1 PWM_RCAPDAT2/3 is the first captured data to memory #1 CAPORD4_5 Capture Channel 4/5 Rising/Falling Order 19 1 read-write 0 PWM_FCAPDAT4/5 is the first captured data to memory #0 1 PWM_RCAPDAT4/5 is the first captured data to memory #1 CHEN0_1 Channel 0/1 PDMA Enable Bit 0 1 read-write 0 Channel 0/1 PDMA function Disabled #0 1 Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory #1 CHEN2_3 Channel 2/3 PDMA Enable Bit 8 1 read-write 0 Channel 2/3 PDMA function Disabled #0 1 Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory #1 CHEN4_5 Channel 4/5 PDMA Enable Bit 16 1 read-write 0 Channel 4/5 PDMA function Disabled #0 1 Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory #1 CHSEL0_1 Select Channel 0/1 to Do PDMA Transfer 4 1 read-write 0 Channel0 #0 1 Channel1 #1 CHSEL2_3 Select Channel 2/3 to Do PDMA Transfer 12 1 read-write 0 Channel2 #0 1 Channel3 #1 CHSEL4_5 Select Channel 4/5 to Do PDMA Transfer 20 1 read-write 0 Channel4 #0 1 Channel5 #1 PWM_PERIOD0 PWM_PERIOD0 PWM Period Register 0 0x30 read-write n 0x0 0x0 PERIOD PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD. 0 16 read-write PWM_PERIOD1 PWM_PERIOD1 PWM Period Register 1 0x34 read-write n 0x0 0x0 PWM_PERIOD2 PWM_PERIOD2 PWM Period Register 2 0x38 read-write n 0x0 0x0 PWM_PERIOD3 PWM_PERIOD3 PWM Period Register 3 0x3C read-write n 0x0 0x0 PWM_PERIOD4 PWM_PERIOD4 PWM Period Register 4 0x40 read-write n 0x0 0x0 PWM_PERIOD5 PWM_PERIOD5 PWM Period Register 5 0x44 read-write n 0x0 0x0 PWM_PHS0_1 PWM_PHS0_1 PWM Counter Phase Register 0 0x80 read-write n 0x0 0x0 PHS PWM Synchronous Start Phase Bits\nPHS determines the PWM synchronous start phase value. These bits only use in synchronous function. 0 16 read-write PWM_PHS2_3 PWM_PHS2_3 PWM Counter Phase Register 2 0x84 read-write n 0x0 0x0 PWM_PHS4_5 PWM_PHS4_5 PWM Counter Phase Register 4 0x88 read-write n 0x0 0x0 PWM_POEN PWM_POEN PWM Output Enable Register 0xD8 read-write n 0x0 0x0 POENn PWM Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM pin at tri-state 0 1 PWM pin in output mode 1 PWM_POLCTL PWM_POLCTL PWM Pin Polar Inverse Register 0xD4 read-write n 0x0 0x0 PINVn PWM PIN Polar Inverse Control Bits\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM output polar inverse Disabled 0 1 PWM output polar inverse Enabled 1 PWM_RCAPDAT0 PWM_RCAPDAT0 PWM Rising Capture Data Register 0 0x20C read-only n 0x0 0x0 RCAPDAT PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register. 0 16 read-only PWM_RCAPDAT1 PWM_RCAPDAT1 PWM Rising Capture Data Register 1 0x214 read-write n 0x0 0x0 PWM_RCAPDAT2 PWM_RCAPDAT2 PWM Rising Capture Data Register 2 0x21C read-write n 0x0 0x0 PWM_RCAPDAT3 PWM_RCAPDAT3 PWM Rising Capture Data Register 3 0x224 read-write n 0x0 0x0 PWM_RCAPDAT4 PWM_RCAPDAT4 PWM Rising Capture Data Register 4 0x22C read-write n 0x0 0x0 PWM_RCAPDAT5 PWM_RCAPDAT5 PWM Rising Capture Data Register 5 0x234 read-write n 0x0 0x0 PWM_SSCTL PWM_SSCTL PWM Synchronous Start Control Register 0x110 read-write n 0x0 0x0 SSENn PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n. 0 6 read-write 0 PWM synchronous start function Disabled 0 1 PWM synchronous start function Enabled 1 PWM_SSTRG PWM_SSTRG PWM Synchronous Start Trigger Register 0x114 write-only n 0x0 0x0 CNTSEN PWM Counter Synchronous Start Enable Bit (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.\nNote: This bit only present in PWM0_BA. 0 1 write-only PWM_STATUS PWM_STATUS PWM Status Register 0x120 read-write n 0x0 0x0 ADCTRGFn EADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit. 16 6 read-write 0 No EADC start of conversion trigger event has occurred 0 1 An EADC start of conversion trigger event has occurred 1 CNTMAXFn Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit. 0 6 read-write 0 The time-base counter never reached its maximum value 0xFFFF 0 1 The time-base counter reached its maximum value 1 SYNCINFn Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n. 8 3 read-write 0 No SYNC_IN event has occurred 0 1 An SYNC_IN event has occurred, software can write 1 to clear this bit 1 PWM_SWBRK PWM_SWBRK PWM Software Brake Control Register 0xDC write-only n 0x0 0x0 BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 0 3 write-only BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register. 8 3 write-only PWM_SWSYNC PWM_SWSYNC PWM Software Control Synchronization Register 0xC read-write n 0x0 0x0 SWSYNCn Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 0 3 read-write PWM_SYNC PWM_SYNC PWM Synchronization Register 0x8 read-write n 0x0 0x0 PHSDIRn PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n. 24 3 read-write 0 Control PWM counter count decrement after synchronizing 0 1 Control PWM counter count increment after synchronizing 1 PHSENn SYNC Phase Enable Bit\nEach bit n controls corresponding PWM channel n. 0 3 read-write 0 PWM counter load PHS value Disabled 0 1 PWM counter load PHS value Enabled 1 SFLTCNT SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector. 20 3 read-write SFLTCSEL SYNC Edge Detector Filter Clock Selection 17 3 read-write 0 Filter clock = HCLK #000 1 Filter clock = HCLK/2 #001 2 Filter clock = HCLK/4 #010 3 Filter clock = HCLK/8 #011 4 Filter clock = HCLK/16 #100 5 Filter clock = HCLK/32 #101 6 Filter clock = HCLK/64 #110 7 Filter clock = HCLK/128 #111 SINPINV SYNC Input Pin Inverse 23 1 read-write 0 The state of pin SYNC is passed to the positive edge detector #0 1 The inversed state of pin SYNC is passed to the positive edge detector #1 SINSRCn PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n. 8 6 read-write 0 Synchronize source from SYNC_IN or SWSYNC 00 1 Counter equal to 0 01 10 Counter equal to PWM_CMPDATm, m denotes 1, 3, 5 10 11 SYNC_OUT will not be generated 11 SNFLTEN PWM0_SYNC_IN Noise Filter Enable Bit 16 1 read-write 0 Noise filter of input pin PWM0_SYNC_IN Disabled #0 1 Noise filter of input pin PWM0_SYNC_IN Enabled #1 PWM_WGCTL0 PWM_WGCTL0 PWM Generation Register 0 0xB0 read-write n 0x0 0x0 PRDPCTLn PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type. 16 12 read-write 0 Do nothing 00 1 PWM period (center) point output Low 01 10 PWM period (center) point output High 10 11 PWM period (center) point output Toggle 11 ZPCTLn PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero. 0 12 read-write 0 Do nothing 00 1 PWM zero point output Low 01 10 PWM zero point output High 10 11 PWM zero point output Toggle 11 PWM_WGCTL1 PWM_WGCTL1 PWM Generation Register 1 0xB4 read-write n 0x0 0x0 CMPDCTLn PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 16 12 read-write 0 Do nothing 00 1 PWM compare down point output Low 01 10 PWM compare down point output High 10 11 PWM compare down point output Toggle 11 CMPUCTLn PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 0 12 read-write 0 Do nothing 00 1 PWM compare up point output Low 01 10 PWM compare up point output High 10 11 PWM compare up point output Toggle 11 RTC RTC Register Map RTC 0x0 0x0 0x80 registers n 0x100 0x10 registers n CAL RTC_CAL RTC Calendar Loading Register 0x10 read-write n 0x0 0x0 DAY 1-Day Calendar Digit (0~9) 0 4 read-write MON 1-Month Calendar Digit (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit (0~3) 4 2 read-write TENMON 10-Month Calendar Digit (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit (0~9) 20 4 read-write YEAR 1-Year Calendar Digit (0~9) 16 4 read-write CALM RTC_CALM RTC Calendar Alarm Register 0x20 read-write n 0x0 0x0 DAY 1-Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write MON 1-Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write TENDAY 10-Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write TENMON 10-Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write YEAR 1-Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CAMSK RTC_CAMSK RTC Calendar Alarm Mask Register 0x38 read-write n 0x0 0x0 MDAY Mask 1-Day Calendar Digit of Alarm Setting (0~9) 0 1 read-write MMON Mask 1-Month Calendar Digit of Alarm Setting (0~9) 2 1 read-write MTENDAY Mask 10-Day Calendar Digit of Alarm Setting (0~3) 1 1 read-write MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1) 3 1 read-write MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9) 5 1 read-write MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9) 4 1 read-write CLKFMT RTC_CLKFMT RTC Time Scale Selection Register 0x14 read-write n 0x0 0x0 _24HEN 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 0 1 read-write 0 12-hour time scale with AM and PM indication selected #0 1 24-hour time scale selected #1 FREQADJ RTC_FREQADJ RTC Frequency Compensation Register 0x8 read-write n 0x0 0x0 FRACTION Fraction Part\nNote: Digit in RTC_FREQADJ must be expressed as hexadecimal number. 0 6 read-write INTEGER Integer Part 8 4 read-write INIT RTC_INIT RTC Initiation Register 0x0 read-write n 0x0 0x0 INIT RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0. 1 31 read-write INIT_ACTIVE RTC Active Status (Read Only) 0 1 read-only 0 RTC is at reset state #0 1 RTC is at normal active state #1 INTEN RTC_INTEN RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable Bit 0 1 read-write 0 RTC Alarm interrupt Disabled #0 1 RTC Alarm interrupt Enabled #1 SNPDIEN Snoop Detection Interrupt Enable Bit 2 1 read-write 0 Snoop detected interrupt Disabled #0 1 Snoop detected interrupt Enabled #1 TICKIEN Time Tick Interrupt Enable Bit 1 1 read-write 0 RTC Time Tick interrupt Disabled #0 1 RTC Time Tick interrupt Enabled #1 INTSTS RTC_INTSTS RTC Interrupt Indicator Register 0x2C read-write n 0x0 0x0 ALMIF RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be woken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit. 0 1 read-write 0 Alarm condition is not matched #0 1 Alarm condition is matched #1 SNPDIF Snoop Detect Interrupt Flag\nWhen tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be woken up from Power-down mode if spare register snooper detect interrupt is enabled.\nNote: Write 1 to clear this bit. 2 1 read-write 0 No snoop event is detected #0 1 Snoop event is detected #1 TICKIF RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be woken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear to clear this bit. 1 1 read-write 0 Tick condition does not occur #0 1 Tick condition occurs #1 LEAPYEAR RTC_LEAPYEAR RTC Leap Year Indicator Register 0x24 read-only n 0x0 0x0 LEAPYEAR Leap Year Indication Register (Read Only) 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 LXTCTL RTC_LXTCTL RTC 32.768 KHz Oscillator Control Register 0x100 read-write n 0x0 0x0 GAIN Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption. 1 3 read-write 0 L0 mode #000 1 L1 mode #001 2 L2 mode #010 3 L3 mode #011 4 L4 mode #100 5 L5 mode #101 6 L6 mode #110 7 L7 mode (Default) #111 LXTEN Backup Domain 32K Oscillator Enable Bit\nNote: This bit controls 32 kHz oscillator on/off. User can set either LXTEN in RTC battery power domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator. If this bit is set 1, X32 kHz oscillator keeps running after system core power is turned off; if this bit is cleared to 0, the oscillator is turned off when system core power is turned off. 0 1 read-write 0 Oscillator Disabled #0 1 Oscillator Enabled #1 LXTICTL RTC_LXTICTL X32KI Pin Control Register 0x108 read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register. 3 1 read-write 0 X32KI (PF.1) pin I/O function is controlled by GPIO module. It becomes floating state when system power is turned off #0 1 X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 X32KI (PF.1) output low #0 1 X32KI (PF.1) output high #1 OPMODE IO Operation Mode 0 2 read-write 0 X32KI (PF.1) is input only mode, without pull-up resistor #00 1 X32KI (PF.1) is output push pull mode #01 2 X32KI (PF.1) is open drain mode #10 3 X32KI (PF.1) is input only mode with internal pull up #11 LXTOCTL RTC_LXTOCTL X32KO Pin Control Register 0x104 read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register. 3 1 read-write 0 X32KO (PF.0) pin I/O function is controlled by GPIO module. It becomes floating when system power is turned off #0 1 X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 X32KO (PF.0) output low #0 1 X32KO (PF.0) output high #1 OPMODE GPF0 Operation Mode 0 2 read-write 0 X32KO (PF.0) is input only mode, without pull-up resistor #00 1 X32KO (PF.0) is output push pull mode #01 2 X32KO (PF.0) is open drain mode #10 3 X32KO (PF.0) is input only mode with internal pull up #11 RWEN RTC_RWEN RTC Access Enable Register 0x4 read-write n 0x0 0x0 RWEN RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock. 0 16 write-only RWENF RTC Register Access Enable Flag (Read Only)\nThis bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock. 16 1 read-only 0 RTC register read/write Disabled #0 1 RTC register read/write Enabled #1 SPR0 RTC_SPR0 RTC Spare Register 0 0x40 read-write n 0x0 0x0 SPARE Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. 0 32 read-write SPR1 RTC_SPR1 RTC Spare Register 1 0x44 read-write n 0x0 0x0 SPR10 RTC_SPR10 RTC Spare Register 10 0x68 read-write n 0x0 0x0 SPR11 RTC_SPR11 RTC Spare Register 11 0x6C read-write n 0x0 0x0 SPR12 RTC_SPR12 RTC Spare Register 12 0x70 read-write n 0x0 0x0 SPR13 RTC_SPR13 RTC Spare Register 13 0x74 read-write n 0x0 0x0 SPR14 RTC_SPR14 RTC Spare Register 14 0x78 read-write n 0x0 0x0 SPR15 RTC_SPR15 RTC Spare Register 15 0x7C read-write n 0x0 0x0 SPR16 RTC_SPR16 RTC Spare Register 16 0x80 read-write n 0x0 0x0 SPR17 RTC_SPR17 RTC Spare Register 17 0x84 read-write n 0x0 0x0 SPR18 RTC_SPR18 RTC Spare Register 18 0x88 read-write n 0x0 0x0 SPR19 RTC_SPR19 RTC Spare Register 19 0x8C read-write n 0x0 0x0 SPR2 RTC_SPR2 RTC Spare Register 2 0x48 read-write n 0x0 0x0 SPR3 RTC_SPR3 RTC Spare Register 3 0x4C read-write n 0x0 0x0 SPR4 RTC_SPR4 RTC Spare Register 4 0x50 read-write n 0x0 0x0 SPR5 RTC_SPR5 RTC Spare Register 5 0x54 read-write n 0x0 0x0 SPR6 RTC_SPR6 RTC Spare Register 6 0x58 read-write n 0x0 0x0 SPR7 RTC_SPR7 RTC Spare Register 7 0x5C read-write n 0x0 0x0 SPR8 RTC_SPR8 RTC Spare Register 8 0x60 read-write n 0x0 0x0 SPR9 RTC_SPR9 RTC Spare Register 9 0x64 read-write n 0x0 0x0 SPRCTL RTC_SPRCTL RTC Spare Functional Control Register 0x3C read-write n 0x0 0x0 SNPDEN Snoop Detection Enable Bit 0 1 read-write 0 TAMPER pin detection Disabled #0 1 TAMPER pin detection Enabled #1 SNPTYPE0 Snoop Detection Level\nThis bit controls TAMPER detect event is high level/rising edge or low level/falling edge. 1 1 read-write 0 Low level/Falling edge detection #0 1 High level/Rising edge detection. #1 SNPTYPE1 Snoop Detection Mode\nThis bit controls TAMPER pin is edge or level detection 3 1 read-write 0 Level detection #0 1 Edge detection #1 SPRCSTS SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.\nWrites 1 to clear this bit. 5 1 read-write 0 Spare register content is not cleared #0 1 Spare register content is cleared #1 SPRRWEN Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. 2 1 read-write 0 Spare register Disabled #0 1 Spare register Enabled #1 SPRRWRDY SPR Register Ready\nThis bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.\nAfter user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.\nNote: This bit is read only and any write to it won't take any effect. 7 1 read-write 0 RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress #0 1 RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed #1 TALM RTC_TALM RTC Time Alarm Register 0x1C read-write n 0x0 0x0 HR 1-Hour Time Digit of Alarm Setting (0~9) 16 4 read-write MIN 1-Min Time Digit of Alarm Setting (0~9) 8 4 read-write SEC 1-Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TENHR 10-hour Time Digit of Alarm Setting (0~2)\nWhen RTC runs as 12-hour time scale mode, the high bit of TENHR (RTC_TIME[21]) means AM/PM indication. 20 2 read-write TENMIN 10-Min Time Digit of Alarm Setting (0~5) 12 3 read-write TENSEC 10-Sec Time Digit of Alarm Setting (0~5) 4 3 read-write TAMPCTL RTC_TAMPCTL TAMPER Pin Control Register 0x10C read-write n 0x0 0x0 CTLSEL IO Pin State Backup Selection\nWhen tamper function is disabled, TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register. 3 1 read-write 0 TAMPER (PF.2) I/O function is controlled by GPIO module. It becomes floating state when system power is turned off #0 1 TAMPER (PF.2) I/O function is controlled by VBAT power domain. PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin state keeps previous state after system power is turned off #1 DOUT IO Output Data 2 1 read-write 0 TAMPER (PF.2) output low #0 1 TAMPER (PF.2) output high #1 OPMODE IO Operation Mode 0 2 read-write 0 TAMPER (PF.2) is input only mode, without pull-up resistor #00 1 TAMPER (PF.2) is output push pull mode #01 2 TAMPER (PF.2) is open drain mode #10 3 TAMPER (PF.2) is input only mode with internal pull up #11 TAMSK RTC_TAMSK RTC Time Alarm Mask Register 0x34 read-write n 0x0 0x0 MHR Mask 1-Hour Time Digit of Alarm Setting (0~9) 4 1 read-write MMIN Mask 1-Min Time Digit of Alarm Setting (0~9) 2 1 read-write MSEC Mask 1-Sec Time Digit of Alarm Setting (0~9) 0 1 read-write MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2) 5 1 read-write MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5) 3 1 read-write MTENSEC Mask 10-Sec Time Digit of Alarm Setting (0~5) 1 1 read-write TICK RTC_TICK RTC Time Tick Register 0x30 read-write n 0x0 0x0 TICK Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. 0 3 read-write 0 Time tick is 1 second #000 1 Time tick is 1/2 second #001 2 Time tick is 1/4 second #010 3 Time tick is 1/8 second #011 4 Time tick is 1/16 second #100 5 Time tick is 1/32 second #101 6 Time tick is 1/64 second #110 7 Time tick is 1/28 second #111 TIME RTC_TIME RTC Time Loading Register 0xC read-write n 0x0 0x0 HR 1-Hour Time Digit (0~9) 16 4 read-write MIN 1-Min Time Digit (0~9) 8 4 read-write SEC 1-Sec Time Digit (0~9) 0 4 read-write TENHR 10-hour Time Digit (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.) 20 2 read-write TENMIN 10-Min Time Digit (0~5) 12 3 read-write TENSEC 10-Sec Time Digit (0~5) 4 3 read-write WEEKDAY RTC_WEEKDAY RTC Day of the Week Register 0x18 read-write n 0x0 0x0 WEEKDAY Day of the Week Register 0 3 read-write 0 Sunday #000 1 Monday #001 2 Tuesday #010 3 Wednesday #011 4 Thursday #100 5 Friday #101 6 Saturday #110 7 Reserved. #111 SC SC Register Map SC 0x0 0x0 0x40 registers n ALTCTL SC_ALTCTL SC Alternate Control Register. 0x8 read-write n 0x0 0x0 ACTEN Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 ACTSTS0 Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0. 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 ACTSTS1 Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1. 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 ACTSTS2 Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2. 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 ADACEN Auto Deactivation When Card Removal\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes, hardware will generate an interrupt INITIF to CPU. 11 1 read-write 0 Auto deactivation Disabled when hardware detected the card removal #0 1 Auto deactivation Enabled when hardware detected the card removal #1 CNTEN0 Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST and RXRST at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN1 Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stops counting #0 1 Start counting #1 CNTEN2 Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.\nNote4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stops counting #0 1 Start counting #1 DACTEN Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INITSEL Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 6.144\nWarm-reset: refer to Warm-Reset Sequence in Figure 6.145\nDeactivation: refer to Deactivation Sequence in Figure 6.146 8 2 read-write RXBGTEN Receiver Block Guard Time Function Enable Bit 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RXRST Rx Software Reset\nWhen RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 TXRST TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARSTEN Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.\nNote3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed. 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 CTL SC_CTL SC Control Register. 0x4 read-write n 0x0 0x0 AUTOCEN Auto Convention Enable Bit 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11 #1 BGT Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1. 8 5 read-write CDDBSEL Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection. 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks #00 1 De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks #01 2 De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks #10 3 De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks #11 CDLV Card Detect Level \nNote: Software must select card detect level before Smart Card engine enabled. 26 1 read-write 0 When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin from low to high, it indicates a card is detected #1 CONSEL Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored. 4 2 read-write 0 Direct convention #00 1 Reserved. #01 2 Reserved. #10 3 Inverse convention #11 DBGOFF ICE Debug Mode Acknowledge Enable Bit 31 1 read-write 0 When DBGACK is high, the internal counter will be held #0 1 No matter DBGACK is high or low, the internal counter will not be held #1 NSB Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 RXOFF RX Transition Disable Control\nNote: If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 RXRTY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value. 16 3 read-write RXRTYEN RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: Software must fill in the RXRTY value before enabling this bit. 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RXTRGLV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated). 6 2 read-write 0 INTR_RDA Trigger Level with 1 Byte #00 1 INTR_RDA Trigger Level with 2 Bytes #01 2 INTR_RDA Trigger Level with 3 Bytes #10 3 Reserved. #11 SCEN SC Engine Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state. 0 1 read-write SYNC SYNC Flag Indicator\nDue to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only. 30 1 read-write 0 synchronizing is completion, user can write new data to RXRTY and TXRTY #0 1 Last value is synchronizing #1 TMRSEL Timer Selection 13 2 read-write 0 All internal timer function Disabled #00 1 Internal 24 bit timer Enabled. Software can configure it by setting SC_TMRCTL0 [23:0]. SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode #01 2 internal 24 bit timer and 8 bit internal timer Enabled. Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0]. SC_TMRCTL2 will be ignored in this mode #10 3 Internal 24 bit timer and two 8 bit timers Enabled. Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0] #11 TXOFF TX Transition Disable Control 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 TXRTY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value. 20 3 read-write TXRTYEN TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred. 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 DAT SC_DAT SC Receiving/Transmit Holding Buffer Register. 0x0 read-write n 0x0 0x0 DAT Receiving/ Transmit Holding Buffer \nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.\n\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data. 0 8 read-write EGT SC_EGT SC Extend Guard Time Register. 0xC read-write n 0x0 0x0 EGT Extended Guard Time\nThis field indicates the extended guard timer value.\nNote: The counter is ETU base and the real extended guard time is EGT. 0 8 read-write ETUCTL SC_ETUCTL SC ETU Control Register. 0x14 read-write n 0x0 0x0 CMPEN Compensation Mode Enable Bit\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV . 15 1 read-write 0 Compensation function Disabled #0 1 Compensation function Enabled #1 ETURDIV ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004. 0 12 read-write INTEN SC_INTEN SC Interrupt Enable Control Register. 0x18 read-write n 0x0 0x0 ACERRIEN Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable. 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGTIEN Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable. 6 1 read-write 0 Block guard time Disabled #0 1 Block guard time Enabled #1 CDIEN Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12]) 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INITIEN Initial End Interrupt Enable Bit 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDAIEN Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable. 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RXTOIF Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable. 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBEIEN Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable. 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERRIEN Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]). 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0IEN Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable. 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1IEN Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt. 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2IEN Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable. 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 INTSTS SC_INTSTS SC Interrupt Status Register. 0x1C read-write n 0x0 0x0 ACERRIF Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 10 1 read-only BGTIF None 6 1 read-only CDIF Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).\nNote: This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])]. So if software wants to clear this bit, software must write 1 to this field. 7 1 read-only INITIF Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only RBTOIF Receiver Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer, 9 1 read-only RDAIF Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically. 0 1 read-only TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically. 1 1 read-only TERRIF Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30]).\nNote: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]). So, if software wants to clear this bit, software must write 1 to each field. 2 1 read-only TMR0IF Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 3 1 read-only TMR1IF Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 4 1 read-only TMR2IF Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 5 1 read-only PINCTL SC_PINCTL SC Pin Control State Register. 0x24 read-write n 0x0 0x0 CLKKEEP SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 DATSTS None 16 1 read-write 0 The SC_DAT pin is low #0 1 The SC_DAT pin is high #1 PWREN SC_PWREN Pin Signal\nSoftware can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 0 1 read-write 0 SC_PWR pin status is low #0 1 SC_PWR pin status is high #1 PWRINV SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.\nNote: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]). 11 1 read-write PWRSTS None 17 1 read-write 0 SC_PWR pin to low #0 1 SC_PWR pin to high #1 RSTSTS SCRST Pin Signals\nThis bit is the pin status of SC_RST\nNote: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes. 18 1 read-write 0 SC_RST pin is low #0 1 SC_RST pin is high #1 SCDOSTS SC Data Pin Output Status \nThis bit is the pin status of SCDATOUT \nNote: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes. 12 1 read-write 0 SCDATOUT pin to low #0 1 SCDATOUT pin to high #1 SCDOUT SC Data Output Pin \nThis bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes. 9 1 read-write 0 Drive SCDATOUT pin to low #0 1 Drive SCDATOUT pin to high #1 SCRST SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST pin status is low #0 1 Drive SC_RST pin to high.\nSC_RST pin status is high #1 SYNC SYNC Flag Indicator\nDue to synchronization, software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only. 30 1 read-write 0 Synchronizing is completion, user can write new data to SC_PINCTL register #0 1 Last value is synchronizing #1 RXTOUT SC_RXTOUT SC Receive Buffer Time-out Register. 0x10 read-write n 0x0 0x0 RFTM SC Receiver FIFO Time-out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling all 0 to this field indicates to disable this function. 0 9 read-write STATUS SC_STATUS SC Status Register. 0x20 read-write n 0x0 0x0 BEF Receiver Break Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). .\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]), hardware will not set this flag. 6 1 read-only CDPINSTS Card Detect Status of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD 13 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CINSERT Card Detect Insert Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only, but it can be cleared by writing '1' to it.\nNote2: The card detect engine will start after SCEN (SC_CTL[0]) set. 12 1 read-only 0 No effect #0 1 Card insert #1 CREMOVE Card Detect Removal Status of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only, but it can be cleared by writing '1' to it.\nNote2: Card detect engine will start after SCEN (SC_CTL[0])set. 11 1 read-only 0 No effect #0 1 Card removed #1 FEF Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]), hardware will not set this flag. 5 1 read-only PEF Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]), hardware will not set this flag. 4 1 read-only RXACT Receiver in Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished. 23 1 read-only RXEMPTY Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data. 1 1 read-only RXFULL Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. 2 1 read-only RXOV RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 0 1 read-only RXOVERR Receiver over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 22 1 read-only RXPOINT Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one. 16 2 read-only RXRERR Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])). 21 1 read-only TXACT Transmit in Active Status Flag (Read Only) 31 1 read-only 0 This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed #0 1 This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted #1 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty). 9 1 read-only TXFULL Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. 10 1 read-only TXOV TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to '1' by hardware. \nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only TXOVERR Transmitter over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 30 1 read-only TXPOINT Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT, TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one. 24 2 read-only TXRERR Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-only TMRCTL0 SC_TMRCTL0 SC Internal Timer Control Register 0. 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values. 0 24 read-write OPMODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer0 24 4 read-write TMRCTL1 SC_TMRCTL1 SC Internal Timer Control Register 1. 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.14.5.4 for programming Timer1 24 4 read-write TMRCTL2 SC_TMRCTL2 SC Internal Timer Control Register 2. 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values. 0 8 read-write OPMODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.14.5.4 for programming Timer2 24 4 read-write TMRDAT0 SC_TMRDAT0 SC Timer Current Data Register A. 0x38 read-only n 0x0 0x0 CNT0 Timer0 Current Data Value (Read Only)\nThis field indicates the current count values of timer0. 0 24 read-only TMRDAT1_2 SC_TMRDAT1_2 SC Timer Current Data Register B. 0x3C read-only n 0x0 0x0 CNT1 Timer1 Current Data Value (Read Only)\nThis field indicates the current count values of timer1. 0 8 read-only CNT2 Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of timer2. 8 8 read-only UARTCTL SC_UARTCTL SC UART Mode Control Register. 0x34 read-write n 0x0 0x0 OPE Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBOFF Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit) 6 1 read-write 0 Parity bit is generated or checked between the 'last data word bit' and 'stop bit' of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UARTEN UART Mode Enable Bit\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 WLS Word Length Selection\nNote: In smart card mode, this WLS must be '00' 4 2 read-write 0 Word length is 8 bits #00 1 Word length is 7 bits #01 2 Word length is 6 bits #10 3 Word length is 5 bits #11 SCS SYST_SCR Register Map SYST_SCR 0x0 0x10 0xC registers n 0xD04 0x4 registers n 0xD0C 0x8 registers n 0xD18 0xC registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C read-write n 0x0 0x0 ENDIANNESS Data Endianness 15 1 read-write 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority, 8 3 read-write SYSRESETREQ System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status. 16 16 read-write ICSR ICSR Interrupt Control and State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, Excluding NMI and Faults (Read Only) 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-only NMIPENDSET NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception is not pending #0 1 Changes NMI exception state to pending.\nNMI exception is pending #1 PENDSTRTC_CAL SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite Operation: 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVRTC_CAL PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending. 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 RETTOBASE Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions 11 1 read-write 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Number of the Current Active Exception 0 6 read-write 0 Thread mode 0 VECTPENDING Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. 12 6 read-write 0 no pending exceptions 0 SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode. 2 1 read-write 0 Sleep #0 1 Deep sleep #1 SLEEPONEXIT Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enters sleep, or deep sleep, on return from an ISR to Thread mode #1 SHPR1 SHPR1 System Handler Priority Register 1 0xD18 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority. 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority. 30 2 read-write SYST_CTRL SYST_CTRL SysTick Control and Status Register 0x10 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection 2 1 read-write 0 Clock source is the (optional) external reference clock #0 1 Core clock used for SysTick #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled 0 1 read-write 0 Counter Disabled #0 1 Counter will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended #1 SYST_LOAD SYST_LOAD SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write SYST_VAL SYST_VAL SysTick Current Value Register 0x18 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DUALIOEN Dual I/O Mode Enable Bit (Only Supported in SPI0) 21 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. 8 5 read-write LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 QDIODIR Quad or Dual I/O Mode Direction Control (Only Supported in SPI0) 20 1 read-write 0 Quad or Dual Input mode #0 1 Quad or Dual Output mode #1 QUADIOEN Quad I/O Mode Enable Bit (Only Supported in SPI0) 22 1 read-write 0 Quad I/O mode Disabled #0 1 Quad I/O mode Enabled #1 REORDER Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample: 4 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit (Only Supported in SPI0)\nNote: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 16 1 read-write 0 2-Bit Transfer mode Disabled #0 1 2-Bit Transfer mode Enabled #1 TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x10 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. In SPI0, RXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[25:24]). 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. In SPI0, TXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[29:28]). 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active. 6 1 read-write 0 The SPI data out is kept 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is kept 1 if there is TX underflow event in Slave mode #1 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX SPI_RX Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register\nThere are 8-/4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register. 0 32 read-only SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLV3WIRE Slave 3-wire Mode Enable Bit (Only Supported in SPI0)\nSlave 3-wire mode is only available in SPI0. In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins. 4 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVTOCNT Slave Mode Time-out Period (Only Supported in SPI0)\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 16 16 read-write SLVTOIEN Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0) 5 1 read-write 0 Slave mode time-out interrupt Disabled #0 1 Slave mode time-out interrupt Enabled #1 SLVTORST Slave Mode Time-out Reset Control (Only Supported in SPI0) 6 1 read-write 0 When Slave mode time-out event occurs, the TX and RX control circuit will not be reset #0 1 When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state #0 1 set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS). 2 1 read-write 0 The slave selection signal SPIn_SS is active low #0 1 The slave selection signal SPIn_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPI_STATUS SPI_STATUS SPI Status Register 0x14 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 Receive FIFO does not over run #0 1 Receive FIFO over run #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (Only Supported in SPI0)\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it. 5 1 read-write 0 Slave time-out is not active #0 1 Slave time-out is active #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurs #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 The SPI controller is disabled #0 1 The SPI controller is enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt be cleared or not occurrs #0 1 Slave select active interrupt event occurrs #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt be cleared or not occurrs #0 1 Slave select inactive interrupt event occurrs #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPI_TX SPI_TX Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x4 registers n 0x30 0x4 registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.\n\nwhere \n is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 0 8 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 read-write n 0x0 0x0 CLKPOL Clock Polarity 3 1 read-write 0 SPI bus clock is idle low #0 1 SPI bus clock is idle high #1 DUALIOEN Dual I/O Mode Enable Bit (Only Supported in SPI0) 21 1 read-write 0 Dual I/O mode Disabled #0 1 Dual I/O mode Enabled #1 DWIDTH Data Width\nThis field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits. 8 5 read-write LSB Send LSB First 13 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first #0 1 The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX) #1 QDIODIR Quad or Dual I/O Mode Direction Control (Only Supported in SPI0) 20 1 read-write 0 Quad or Dual Input mode #0 1 Quad or Dual Output mode #1 QUADIOEN Quad I/O Mode Enable Bit (Only Supported in SPI0) 22 1 read-write 0 Quad I/O mode Disabled #0 1 Quad I/O mode Enabled #1 REORDER Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled. 19 1 read-write 0 Byte Reorder function Disabled #0 1 Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV #1 RXNEG Receive on Negative Edge 1 1 read-write 0 Received data input signal is latched on the rising edge of SPI bus clock #0 1 Received data input signal is latched on the falling edge of SPI bus clock #1 SLAVE Slave Mode Control 18 1 read-write 0 Master mode #0 1 Slave mode #1 SPIEN SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0. 0 1 read-write 0 Transfer control Disabled #0 1 Transfer control Enabled #1 SUSPITV Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample: 4 4 read-write TWOBIT 2-bit Transfer Mode Enable Bit (Only Supported in SPI0)\nNote: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. 16 1 read-write 0 2-Bit Transfer mode Disabled #0 1 2-Bit Transfer mode Enabled #1 TXNEG Transmit on Negative Edge 2 1 read-write 0 Transmitted data output signal is changed on the rising edge of SPI bus clock #0 1 Transmitted data output signal is changed on the falling edge of SPI bus clock #1 UNITIEN Unit Transfer Interrupt Enable Bit 17 1 read-write 0 SPI unit transfer interrupt Disabled #0 1 SPI unit transfer interrupt Enabled #1 SPI_FIFOCTL SPI_FIFOCTL SPI FIFO Control Register 0x10 read-write n 0x0 0x0 RXFBCLR Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared. 8 1 read-write 0 No effect #0 1 Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 RXOVIEN Receive FIFO Overrun Interrupt Enable Bit 5 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RXRST Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. 0 1 read-write 0 No effect #0 1 Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 RXTH Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0. In SPI0, RXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[25:24]). 24 3 read-write RXTHIEN Receive FIFO Threshold Interrupt Enable Bit 2 1 read-write 0 RX FIFO threshold interrupt Disabled #0 1 RX FIFO threshold interrupt Enabled #1 RXTOIEN Slave Receive Time-out Interrupt Enable Bit 4 1 read-write 0 Receive time-out interrupt Disabled #0 1 Receive time-out interrupt Enabled #1 TXFBCLR Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared. 9 1 read-write 0 No effect #0 1 Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1 #1 TXRST Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled. 1 1 read-write 0 No effect #0 1 Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not #1 TXTH Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0. In SPI0, TXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[29:28]). 28 3 read-write TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit 3 1 read-write 0 TX FIFO threshold interrupt Disabled #0 1 TX FIFO threshold interrupt Enabled #1 TXUFIEN TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1. 7 1 read-write 0 Slave TX underflow interrupt Disabled #0 1 Slave TX underflow interrupt Enabled #1 TXUFPOL TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active. 6 1 read-write 0 The SPI data out is kept 0 if there is TX underflow event in Slave mode #0 1 The SPI data out is kept 1 if there is TX underflow event in Slave mode #1 SPI_PDMACTL SPI_PDMACTL SPI PDMA Control Register 0xC read-write n 0x0 0x0 PDMARST PDMA Reset 2 1 read-write 0 No effect #0 1 Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0 #1 RXPDMAEN Receive PDMA Enable Bit 1 1 read-write 0 Receive PDMA function Disabled #0 1 Receive PDMA function Enabled #1 TXPDMAEN Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX SPI_RX Data Receive Register 0x30 read-only n 0x0 0x0 RX Data Receive Register\nThere are 8-/4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register. 0 32 read-only SPI_SSCTL SPI_SSCTL SPI Slave Select Control Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Selection Function Enable Bit (Master Only) 3 1 read-write 0 Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]) #0 1 Automatic slave selection function Enabled #1 SLV3WIRE Slave 3-wire Mode Enable Bit (Only Supported in SPI0)\nSlave 3-wire mode is only available in SPI0. In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins. 4 1 read-write 0 4-wire bi-direction interface #0 1 3-wire bi-direction interface #1 SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit 8 1 read-write 0 Slave mode bit count error interrupt Disabled #0 1 Slave mode bit count error interrupt Enabled #1 SLVTOCNT Slave Mode Time-out Period (Only Supported in SPI0)\nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled. 16 16 read-write SLVTOIEN Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0) 5 1 read-write 0 Slave mode time-out interrupt Disabled #0 1 Slave mode time-out interrupt Enabled #1 SLVTORST Slave Mode Time-out Reset Control (Only Supported in SPI0) 6 1 read-write 0 When Slave mode time-out event occurs, the TX and RX control circuit will not be reset #0 1 When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware #1 SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit 9 1 read-write 0 Slave mode TX under run interrupt Disabled #0 1 Slave mode TX under run interrupt Enabled #1 SS Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0, 0 1 read-write 0 set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state #0 1 set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]) #1 SSACTIEN Slave Select Active Interrupt Enable Bit 12 1 read-write 0 Slave select active interrupt Disabled #0 1 Slave select active interrupt Enabled #1 SSACTPOL Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS). 2 1 read-write 0 The slave selection signal SPIn_SS is active low #0 1 The slave selection signal SPIn_SS is active high #1 SSINAIEN Slave Select Inactive Interrupt Enable Bit 13 1 read-write 0 Slave select inactive interrupt Disabled #0 1 Slave select inactive interrupt Enabled #1 SPI_STATUS SPI_STATUS SPI Status Register 0x14 read-write n 0x0 0x0 BUSY Busy Status (Read Only) 0 1 read-only 0 SPI controller is in idle state #0 1 SPI controller is in busy state #1 RXCNT Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer. 24 4 read-only RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only) 8 1 read-only 0 Receive FIFO buffer is not empty #0 1 Receive FIFO buffer is empty #1 RXFULL Receive FIFO Buffer Full Indicator (Read Only) 9 1 read-only 0 Receive FIFO buffer is not full #0 1 Receive FIFO buffer is full #1 RXOVIF Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 11 1 read-write 0 Receive FIFO does not over run #0 1 Receive FIFO over run #1 RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only) 10 1 read-only 0 The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RXTH #1 RXTOIF Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 12 1 read-write 0 No receive FIFO time-out event #0 1 Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 SLVBEIF Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it. 6 1 read-write 0 No Slave mode bit count error event #0 1 Slave mode bit count error event occurs #1 SLVTOIF Slave Time-out Interrupt Flag (Only Supported in SPI0)\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it. 5 1 read-write 0 Slave time-out is not active #0 1 Slave time-out is active #1 SLVURIF Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it. 7 1 read-write 0 No Slave TX under run event #0 1 Slave TX under run event occurs #1 SPIENSTS SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 15 1 read-only 0 The SPI controller is disabled #0 1 The SPI controller is enabled #1 SSACTIF Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 2 1 read-write 0 Slave select active interrupt be cleared or not occurrs #0 1 Slave select active interrupt event occurrs #1 SSINAIF Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it. 3 1 read-write 0 Slave select inactive interrupt be cleared or not occurrs #0 1 Slave select inactive interrupt event occurrs #1 SSLINE Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 4 1 read-only 0 The slave select line status is 0 #0 1 The slave select line status is 1 #1 TXCNT Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer. 28 4 read-only TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only) 16 1 read-only 0 Transmit FIFO buffer is not empty #0 1 Transmit FIFO buffer is empty #1 TXFULL Transmit FIFO Buffer Full Indicator (Read Only) 17 1 read-only 0 Transmit FIFO buffer is not full #0 1 Transmit FIFO buffer is full #1 TXRXRST TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done. 23 1 read-only 0 The reset function of TXRST or RXRST is done #0 1 Doing the reset function of TXRST or RXRST #1 TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only) 18 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH #1 TXUFIF TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done. 19 1 read-write 0 No effect #0 1 No data in Transmit FIFO and TX shift register when the slave selection signal is active #1 UNITIF Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it. 1 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 SPI_TX SPI_TX Data Transmit Register 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register. 0 32 write-only SYS SYS Register Map SYS 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x130 0xC registers n 0x18 0x8 registers n 0x24 0x38 registers n 0x400 0x4 registers n 0xD0 0x8 registers n 0xF0 0xC registers n AHBMCTL SYS_AHBMCTL AHB Bus Matrix Priority Control Register 0x400 read-write n 0x0 0x0 INTACTEN Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect)\nEnable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Run robin mode #0 1 Cortex-M4 CPU with highest bus priority when interrupt occusr #1 BODCTL SYS_BODCTL Brown-Out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BODDGSEL Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 BOD output is sampled by RC10K clock #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 BODEN Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BODIF Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled #1 BODLPM Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 5 1 read-write 0 BOD operate in normal mode (default) #0 1 BOD Low Power mode Enabled #1 BODOUT Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0. 6 1 read-write 0 Brown-out Detector output status is 0 #0 1 Brown-out Detector output status is 1 #1 BODRSTEN Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .\nNote1: \nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nWhile the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 Brown-out 'INTERRUPT' function Enabled #0 1 Brown-out 'RESET' function Enabled #1 BODVL Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 2 read-write 0 Brown-Out Detector threshold voltage is 2.2V #00 1 Brown-Out Detector threshold voltage is 2.7V #01 2 Brown-Out Detector threshold voltage is 3.7V #10 3 Brown-Out Detector threshold voltage is 4.4V #11 LVRDGSEL LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register. 12 3 read-write 0 Without de-glitch function #000 1 4 system clock (HCLK) #001 2 8 system clock (HCLK) #010 3 16 system clock (HCLK) #011 4 32 system clock (HCLK) #100 5 64 system clock (HCLK) #101 6 128 system clock (HCLK) #110 7 256 system clock (HCLK) #111 LVREN Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote3: LIRC must be enabled before enable LVR. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled #1 GPA_MFPH SYS_GPA_MFPH GPIOA High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 GPA_MFPL SYS_GPA_MFPL GPIOA Low Byte Multiple Function Control Register 0x30 read-write n 0x0 0x0 PA0MFP PA.0 Multi-function Pin Selection 0 4 read-write PA1MFP PA.1 Multi-function Pin Selection 4 4 read-write PA2MFP PA.2 Multi-function Pin Selection 8 4 read-write PA3MFP PA.3 Multi-function Pin Selection 12 4 read-write GPB_MFPH SYS_GPB_MFPH GPIOB High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB11MFP PB.11 Multi-function Pin Selection 12 4 read-write PB12MFP PB.12 Multi-function Pin Selection 16 4 read-write PB15MFP PB.15 Multi-function Pin Selection 28 4 read-write PB8MFP PB.8 Multi-function Pin Selection 0 4 read-write GPB_MFPL SYS_GPB_MFPL GPIOB Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0MFP PB.0 Multi-function Pin Selection 0 4 read-write PB1MFP PB.1 Multi-function Pin Selection 4 4 read-write PB2MFP PB.2 Multi-function Pin Selection 8 4 read-write PB3MFP PB.3 Multi-function Pin Selection 12 4 read-write PB4MFP PB.4 Multi-function Pin Selection 16 4 read-write PB5MFP PB.5 Multi-function Pin Selection 20 4 read-write PB6MFP PB.6 Multi-function Pin Selection 24 4 read-write PB7MFP PB.7 Multi-function Pin Selection 28 4 read-write GPC_MFPH SYS_GPC_MFPH GPIOC High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 GPC_MFPL SYS_GPC_MFPL GPIOC Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0MFP PC.0 Multi-function Pin Selection 0 4 read-write PC1MFP PC.1 Multi-function Pin Selection 4 4 read-write PC2MFP PC.2 Multi-function Pin Selection 8 4 read-write PC3MFP PC.3 Multi-function Pin Selection 12 4 read-write PC4MFP PC.4 Multi-function Pin Selection 16 4 read-write PC5MFP PC.5 Multi-function Pin Selection 20 4 read-write PC6MFP PC.6 Multi-function Pin Selection 24 4 read-write PC7MFP PC.7 Multi-function Pin Selection 28 4 read-write GPD_MFPH SYS_GPD_MFPH GPIOD High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD12MFP PD.12 Multi-function Pin Selection 16 4 read-write PD13MFP PD.13 Multi-function Pin Selection 20 4 read-write PD14MFP PD.14 Multi-function Pin Selection 24 4 read-write PD15MFP PD.15 Multi-function Pin Selection 28 4 read-write PD8MFP PD.8 Multi-function Pin Selection 0 4 read-write PD9MFP PD.9 Multi-function Pin Selection 4 4 read-write GPD_MFPL SYS_GPD_MFPL GPIOD Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD0MFP PD.0 Multi-function Pin Selection 0 4 read-write PD1MFP PD.1 Multi-function Pin Selection 4 4 read-write PD2MFP PD.2 Multi-function Pin Selection 8 4 read-write PD3MFP PD.3 Multi-function Pin Selection 12 4 read-write PD7MFP PD.7 Multi-function Pin Selection 28 4 read-write GPE_MFPH SYS_GPE_MFPH GPIOE High Byte Multiple Function Control Register 0x54 read-write n 0x0 0x0 PE10MFP PE.10 Multi-function Pin Selection 8 4 read-write PE11MFP PE.11 Multi-function Pin Selection 12 4 read-write PE12MFP PE.12 Multi-function Pin Selection 16 4 read-write PE13MFP PE.13 Multi-function Pin Selection 20 4 read-write PE8MFP PE.8 Multi-function Pin Selection 0 4 read-write PE9MFP PE.9 Multi-function Pin Selection 4 4 read-write GPE_MFPL SYS_GPE_MFPL GPIOE Low Byte Multiple Function Control Register 0x50 read-write n 0x0 0x0 PE0MFP PE.0 Multi-function Pin Selection 0 4 read-write GPF_MFPL SYS_GPF_MFPL GPIOF Low Byte Multiple Function Control Register 0x58 read-write n 0x0 0x0 PF0MFP PF.0 Multi-function Pin Selection 0 4 read-write PF1MFP PF.1 Multi-function Pin Selection 4 4 read-write PF2MFP PF.2 Multi-function Pin Selection 8 4 read-write PF3MFP PF.3 Multi-function Pin Selection 12 4 read-write PF4MFP PF.4 Multi-function Pin Selection 16 4 read-write PF5MFP PF.5 Multi-function Pin Selection 20 4 read-write PF6MFP PF.6 Multi-function Pin Selection 24 4 read-write PF7MFP PF.7 Multi-function Pin Selection 28 4 read-write IPRST0 SYS_IPRST0 Peripheral Reset Control Register 0 0x8 read-write n 0x0 0x0 CHIPRST Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPURST Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 Processor core normal operation #0 1 Processor core one-shot reset #1 CRCRST CRC Calculation Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 7 1 read-write 0 CRC calculation controller normal operation #0 1 CRC calculation controller reset #1 EBIRST EBI Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 3 1 read-write 0 EBI controller normal operation #0 1 EBI controller reset #1 PDMARST PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 PDMA controller normal operation #0 1 PDMA controller reset #1 UHCRST UHC Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 UHC controller normal operation #0 1 UHC controller reset #1 IPRST1 SYS_IPRST1 Peripheral Reset Control Register 1 0xC read-write n 0x0 0x0 EADCRST EADC Controller Reset 28 1 read-write 0 EADC controller normal operation #0 1 EADC controller reset #1 GPIORST GPIO Controller Reset 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0RST I2C0 Controller Reset 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1RST I2C1 Controller Reset 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 SPI0RST SPI0 Controller Reset 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1RST SPI1 Controller Reset 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0RST Timer0 Controller Reset 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1RST Timer1 Controller Reset 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2RST Timer2 Controller Reset 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3RST Timer3 Controller Reset 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0RST UART0 Controller Reset 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1RST UART1 Controller Reset 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 UART2RST UART2 Controller Reset 18 1 read-write 0 UART2 controller normal operation #0 1 UART2 controller reset #1 UART3RST UART3 Controller Reset 19 1 read-write 0 UART3 controller normal operation #0 1 UART3 controller reset #1 USBDRST USB Device Controller Reset 27 1 read-write 0 USB device controller normal operation #0 1 USB device controller reset #1 IPRST2 SYS_IPRST2 Peripheral Reset Control Register 2 0x10 read-write n 0x0 0x0 PWM0RST PWM0 Controller Reset 16 1 read-write 0 PWM0 controller normal operation #0 1 PWM0 controller reset #1 PWM1RST PWM1 Controller Reset 17 1 read-write 0 PWM1 controller normal operation #0 1 PWM1 controller reset #1 SC0RST SC0 Controller Reset 0 1 read-write 0 SC0 controller normal operation #0 1 SC0 controller reset #1 IRC48MTIEN SYS_IRC48MTIEN HIRC48M Trim Interrupt Enable Register 0x134 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate. 2 1 read-write 0 Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #1 IRC48MTISTS SYS_IRC48MTISTS HIRC48M Trim Interrupt Status Register 0x138 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate.\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accurate #0 1 Clock frequency is inaccurate #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal high-speed oscillator frequency not locked at 48MHz yet #0 1 The internal high-speed oscillator frequency locked at 48 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 IRC48MTRIMCTL SYS_IRC48MTRIMCTL HIRC48M Trim Control Register 0x130 read-write n 0x0 0x0 BOUNDARY Boundary Selection\nFill in the boundary range from 0x1 to 0x31, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled. 16 5 read-write BOUNDEN Boundary Enable 9 1 read-write 0 Boundary function Disabled #0 1 Boundary function Enabled #1 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is kept going if clock is inaccurate #0 1 The trim operation is stopped if clock is inaccurate #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote: HIRC auto trim cannot work normally at power down mode. These bits must be cleared before entering power down mode. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 48 MHz #01 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 32.768 kHz clock #00 1 Trim value calculation is based on average difference in 8 32.768 kHz clock #01 2 Trim value calculation is based on average difference in 16 32.768 kHz clock #10 3 Trim value calculation is based on average difference in 32 32.768 kHz clock #11 REFCKSEL Reference Clock Selection\nNote1: HIRC trim reference clock is 40 kHz in test mode. \nNote2: HIRC trim reference clock support LXT or HXT or SOF depends on the chip spec. 10 1 read-write 0 HIRC trim reference clock is from LXT (32.768 kHz) or HXT(12 MHz) #0 1 HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet or HXT(12 MHz) #1 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC is locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTCTL SYS_IRCTCTL HIRC Trim Control Register 0xF0 read-write n 0x0 0x0 CESTOPEN Clock Error Stop Enable Bit 8 1 read-write 0 The trim operation is kept going if clock is inaccurate #0 1 The trim operation is stopped if clock is inaccurate #1 FREQSEL Trim Frequency Selection\nThis field indicates the target frequency of 22.1184 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote: HIRC auto trim cannot work normally at power down mode. These bits must be cleared before entering power down mode. 0 2 read-write 0 Disable HIRC auto trim function #00 1 Enable HIRC auto trim function and trim HIRC to 22.1184 MHz #01 LOOPSEL Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock. 4 2 read-write 0 Trim value calculation is based on average difference in 4 32.768 kHz clock #00 1 Trim value calculation is based on average difference in 8 32.768 kHz clock #01 2 Trim value calculation is based on average difference in 16 32.768 kHz clock #10 3 Trim value calculation is based on average difference in 32 32.768 kHz clock #11 RETRYCNT Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 6 2 read-write 0 Trim retry count limitation is 64 loops #00 1 Trim retry count limitation is 128 loops #01 2 Trim retry count limitation is 256 loops #10 3 Trim retry count limitation is 512 loops #11 IRCTIEN SYS_IRCTIEN HIRC Trim Interrupt Enable Register 0xF4 read-write n 0x0 0x0 CLKEIEN Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccurate. 2 1 read-write 0 Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #0 1 Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU #1 TFAILIEN Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 1 1 read-write 0 Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #0 1 Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU #1 IRCTISTS SYS_IRCTISTS HIRC Trim Interrupt Status Register 0xF8 read-write n 0x0 0x0 CLKERRIF Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccurate\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccurate. Write 1 to clear this to 0. 2 1 read-write 0 Clock frequency is accurate #0 1 Clock frequency is inaccurate #1 FREQLOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write 0 The internal high-speed oscillator frequency is not locked at 22.1184 MHz yet #0 1 The internal high-speed oscillator frequency locked at 22.1184 MHz #1 TFAILIF Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 1 1 read-write 0 Trim value update limitation count does not reach #0 1 Trim value update limitation count reached and HIRC frequency still not locked #1 IVSCTL SYS_IVSCTL Internal Voltage Source Control Register 0x1C read-write n 0x0 0x0 VBATUGEN VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result 1 1 read-write 0 VBAT unity gain buffer function Disabled (default) #0 1 VBAT unity gain buffer function Enabled #1 VTEMPEN Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 PDID SYS_PDID Part Device Identification Number Register 0x0 read-only n 0x0 0x0 PDID Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PORCTL SYS_PORCTL Power-On-Reset Controller Register 0x24 -1 read-write n 0x0 0x0 POROFF Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register. 0 16 read-write REGLCTL SYS_REGLCTL Register Lock Control Register 0x100 read-write n 0x0 0x0 REGLCTL Register Lock Control Code Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Register Lock Control Disable Index The Protected registers are: SYS_IPRST0: address 0x4000_0008 SYS_BODCTL: address 0x4000_0018 SYS_PORCTL: address 0x4000_0024 SYS_VREFCTL: address 0x4000_0028 CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power-down wake-up interrupt clear) SYS_SRAM_BISTCTL: address 0x4000_00D0 CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable) CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select) CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select) CLK_CLKDSTS: address 0x4000_0274 NMIEN: address 0x4000_0300 FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register) FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register) FMC_ISPSTS: address 0x4000_C040 WDT_CTL: address 0x4004_0000 FMC_FTCTL: address 0x4000_5018 SYS_AHBMCTL: address 0x40000400 CLK_PLLCTL: address 0x40000240 PWM_CTL0: address 0x4005_8000 PWM_CTL0: address 0x4005_9000 PWM_DTCTL0_1: address 0x4005_8070 PWM_DTCTL0_1: address 0x4005_9070 PWM_DTCTL2_3: address 0x4005_8074 PWM_DTCTL2_3: address 0x4005_9074 PWM_DTCTL4_5: address 0x4005_8078 PWM_DTCTL4_5: address 0x4005_9078 PWM_BRKCTL0_1: address 0x4005_80C8 PWM_BRKCTL0_1: address 0x4005_90C8 PWM_BRKCTL2_3: address0x4005_80CC PWM_BRKCTL2_3: address0x4005_90CC PWM_BRKCTL4_5: address0x4005_80D0 PWM_BRKCTL4_5: address0x4005_90D0 PWM_INTEN1: address0x4005_80E4 PWM_INTEN1: address0x4005_90E4 PWM_INTSTS1: address0x4005_80EC PWM_INTSTS1: address0x4005_90EC 0 8 read-write 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored 0 1 Write-protection Disabled for writing protected registers 1 RSTSTS SYS_RSTSTS System Reset Status Register 0x4 -1 read-write n 0x0 0x0 BODRF BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 CPULKRF The CPULK Reset Flag Is Set by Hardware If Cortex-m4 Lockup Happened\nNote: Write 1 to clear this bit to 0. 8 1 read-write 0 No reset from CPU lockup happened #0 1 The Cortex-M4 lockup happened and chip is reset #1 CPURF CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M4 Core and FMC are reset by software setting CPURST to 1 #1 LVRF LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 LVR controller had issued the reset signal to reset the system #1 PINRF nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from nRESET pin #0 1 Pin nRESET had issued the reset signal to reset the system #1 PORF POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIPRST #0 1 Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system #1 SYSRF System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M4 #0 1 The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core #1 WDTRF WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 2 1 read-write 0 No reset from watchdog timer or window watchdog timer #0 1 The watchdog timer or window watchdog timer had issued the reset signal to reset the system #1 SRAM_BISTCTL SYS_SRAM_BISTCTL System SRAM BIST Test Control Register 0xD0 read-write n 0x0 0x0 CRBIST CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2 1 read-write 0 system CACHE BIST Disabled #0 1 system CACHE BIST Enabled #1 SRBIST0 1st SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 0 1 read-write 0 system SRAM BIST Disabled #0 1 system SRAM BIST Enabled #1 SRBIST1 2nd SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 system SRAM BIST Disabled #0 1 system SRAM BIST Enabled #1 USBBIST USB BIST Enable Bit (Write Protect)\nThis bit enables BIST test for USB RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 4 1 read-write 0 system USB BIST Disabled #0 1 system USB BIST Enabled #1 SRAM_BISTSTS SYS_SRAM_BISTSTS System SRAM BIST Test Status Register 0xD4 read-only n 0x0 0x0 CRBEND CACHE SRAM BIST Test Finish 18 1 read-only 0 System CACHE RAM BIST is active #0 1 System CACHE RAM BIST test finished #1 CRBISTEF CACHE SRAM BIST Fail Flag 2 1 read-only 0 System CACHE RAM BIST test pass #0 1 System CACHE RAM BIST test fail #1 SRBEND0 1st SRAM BIST Test Finish 16 1 read-only 0 1st system SRAM BIST active #0 1 1st system SRAM BIST finished #1 SRBEND1 2nd SRAM BIST Test Finish 17 1 read-only 0 2nd system SRAM BIST is active #0 1 2nd system SRAM BIST finished #1 SRBISTEF0 1st System SRAM BIST Fail Flag 0 1 read-only 0 1st system SRAM BIST test pass #0 1 1st system SRAM BIST test fail #1 SRBISTEF1 2nd System SRAM BIST Fail Flag 1 1 read-only 0 2nd system SRAM BIST test pass #0 1 2nd system SRAM BIST test fail #1 USBBEF USB SRAM BIST Fail Flag 4 1 read-only 0 USB SRAM BIST test pass #0 1 USB SRAM BIST test fail #1 USBBEND USB SRAM BIST Test Finish 20 1 read-only 0 USB SRAM BIST is active #0 1 USB SRAM BIST test finished #1 USBPHYCR SYS_USBPHYCR USB PHY Control Register 0x2C read-write n 0x0 0x0 USB_ROLE USB Role Option (Write Protect)\nThese two bits are used to select the role of USB. 0 2 read-write 0 Standard USB device #00 1 Standard USB host.\nReceived #01 VREFCTL SYS_VREFCTL VREF Control Register 0x28 read-write n 0x0 0x0 VREFCTL VREF Control Bits (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Connecting a 1uF capacitor to AVSS will make internal reference voltage more stable. 0 5 read-write 0 VREF is from external pin #00000 3 VREF is internal 2.56V #00011 7 VREF is internal 2.048V #00111 11 VREF is internal 3.072V #01011 15 VREF is internal 4.096V #01111 TMR01 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER0_CAP TIMER0_CAP Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER0_CMP TIMER0_CMP Timer0 Compare Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER0_CNT TIMER0_CNT Timer0 Data Register 0xC read-only n 0x0 0x0 CNT Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value. 0 24 read-only TIMER0_CTL TIMER0_CTL Timer0 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CNTEN Timer Counting Enable Bit 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter 0 8 read-write RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGEADC Trigger EADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger EADC. 21 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal. 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM and EADC #0 1 Capture interrupt signal is used to trigger PWM and EADC #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER0_EINTSTS TIMER0_EINTSTS Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER0_EXTCTL TIMER0_EXTCTL Timer0 External Control Register 0x14 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect 1 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected #10 3 Reserved. #11 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin. 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TIMER0_INTSTS TIMER0_INTSTS Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER1_CAP TIMER1_CAP Timer1 Capture Data Register 0x30 read-write n 0x0 0x0 TIMER1_CMP TIMER1_CMP Timer1 Compare Register 0x24 read-write n 0x0 0x0 TIMER1_CNT TIMER1_CNT Timer1 Data Register 0x2C read-write n 0x0 0x0 TIMER1_CTL TIMER1_CTL Timer1 Control and Status Register 0x20 read-write n 0x0 0x0 TIMER1_EINTSTS TIMER1_EINTSTS Timer1 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TIMER1_EXTCTL TIMER1_EXTCTL Timer1 External Control Register 0x34 read-write n 0x0 0x0 TIMER1_INTSTS TIMER1_INTSTS Timer1 Interrupt Status Register 0x28 read-write n 0x0 0x0 TMR23 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x20 0x1C registers n TIMER2_CAP TIMER2_CAP Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 CAPDAT Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 0 24 read-only TIMER2_CMP TIMER2_CMP Timer2 Compare Register 0x4 read-write n 0x0 0x0 CMPDAT Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. 0 24 read-write TIMER2_CNT TIMER2_CNT Timer2 Data Register 0xC read-only n 0x0 0x0 CNT Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value. 0 24 read-only TIMER2_CTL TIMER2_CTL Timer2 Control and Status Register 0x0 read-write n 0x0 0x0 ACTSTS Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status. 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CNTEN Timer Counting Enable Bit 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 EXTCNTEN Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. 24 1 read-write 0 Event counter mode Disabled #0 1 Event counter mode Enabled #1 ICEDEBUG ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 OPMODE Timer Counting Mode Select 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PSC Prescale Counter 0 8 read-write RSTCNT Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1. 26 1 read-write 0 No effect #0 1 Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit #1 TGLPINSEL Toggle-output Pin Select 22 1 read-write 0 Toggle mode output to Tx (Timer Event Counter Pin) #0 1 Toggle mode output to Tx_EXT (Timer External Capture Pin) #1 TRGEADC Trigger EADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger EADC. 21 1 read-write 0 Timer interrupt trigger EADC Disabled #0 1 Timer interrupt trigger EADC Enabled #1 TRGPWM Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM. 19 1 read-write 0 Timer interrupt trigger PWM Disabled #0 1 Timer interrupt trigger PWM Enabled #1 TRGSSEL Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal. 18 1 read-write 0 Timer time-out interrupt signal is used to trigger PWM and EADC #0 1 Capture interrupt signal is used to trigger PWM and EADC #1 WKEN Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. 23 1 read-write 0 Wake-up function Disabled if timer interrupt signal generated #0 1 Wake-up function Enabled if timer interrupt signal generated #1 TIMER2_EINTSTS TIMER2_EINTSTS Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 CAPIF Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. 0 1 read-write 0 Tx_EXT (x= 0~3) pin interrupt did not occur #0 1 Tx_EXT (x= 0~3) pin interrupt occurred #1 TIMER2_EXTCTL TIMER2_EXTCTL Timer2 External Control Register 0x14 read-write n 0x0 0x0 CAPDBEN Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit. 6 1 read-write 0 Tx_EXT (x= 0~3) pin de-bounce Disabled #0 1 Tx_EXT (x= 0~3) pin de-bounce Enabled #1 CAPEDGE Timer External Capture Pin Edge Detect 1 2 read-write 0 A Falling edge on Tx_EXT (x= 0~3) pin will be detected #00 1 A Rising edge on Tx_EXT (x= 0~3) pin will be detected #01 2 Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected #10 3 Reserved. #11 CAPEN Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin. 3 1 read-write 0 Tx_EXT (x= 0~3) pin Disabled #0 1 Tx_EXT (x= 0~3) pin Enabled #1 CAPFUNCS Capture Function Selection 4 1 read-write 0 External Capture Mode Enabled #0 1 External Reset Mode Enabled #1 CAPIEN Timer External Capture Interrupt Enable Bit 5 1 read-write 0 Tx_EXT (x= 0~3) pin detection Interrupt Disabled #0 1 Tx_EXT (x= 0~3) pin detection Interrupt Enabled #1 CNTDBEN Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx (x= 0~3) pin de-bounce Disabled #0 1 Tx (x= 0~3) pin de-bounce Enabled #1 CNTPHASE Timer External Count Phase 0 1 read-write 0 A Falling edge of external counting pin will be counted #0 1 A Rising edge of external counting pin will be counted #1 TIMER2_INTSTS TIMER2_INTSTS Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 CNT value matches the CMPDAT value #1 TWKF Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause CPU wake-up #0 1 CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated #1 TIMER3_CAP TIMER3_CAP Timer3 Capture Data Register 0x30 read-write n 0x0 0x0 TIMER3_CMP TIMER3_CMP Timer3 Compare Register 0x24 read-write n 0x0 0x0 TIMER3_CNT TIMER3_CNT Timer3 Data Register 0x2C read-write n 0x0 0x0 TIMER3_CTL TIMER3_CTL Timer3 Control and Status Register 0x20 read-write n 0x0 0x0 TIMER3_EINTSTS TIMER3_EINTSTS Timer3 External Interrupt Status Register 0x38 read-write n 0x0 0x0 TIMER3_EXTCTL TIMER3_EXTCTL Timer3 External Control Register 0x34 read-write n 0x0 0x0 TIMER3_INTSTS TIMER3_INTSTS Timer3 Interrupt Status Register 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.133. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.133.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.133. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.133. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable \nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic '1' when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 Reserved. #01 2 IrDA function #10 3 RS-485 function #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 15 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empt interrupt Enabled #1 TOCNTEN Time-out Counter Enable Bit 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TXPDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 14 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 WKCTSIEN nCTS Wake-up Interrupt Enable Bit 9 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-up Interrupt Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode. #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 HWBUFEIF in DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 HWBUFEINT in DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 HWMODIF in DMA Mode, MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]). 19 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 HWMODINT in DMA Mode, MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 HWRLSIF in DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 HWRLSINT in DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 HWTOIF in DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 HWTOINT in DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 MODEMIF Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated. #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote : Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.\nNote2: Refer to Figure 6.1314 and Figure 6.1315 for RS-485 function mode. 9 1 read-write 0 n RTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.133. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.133.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.133. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.133. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable \nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic '1' when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 Reserved. #01 2 IrDA function #10 3 RS-485 function #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 15 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empt interrupt Enabled #1 TOCNTEN Time-out Counter Enable Bit 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TXPDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 14 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 WKCTSIEN nCTS Wake-up Interrupt Enable Bit 9 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-up Interrupt Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 HWBUFEIF in DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 HWBUFEINT in DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 HWMODIF in DMA Mode, MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]). 19 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 HWMODINT in DMA Mode, MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 HWRLSIF in DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 HWRLSINT in DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 HWTOIF in DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 HWTOINT in DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 MODEMIF Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote : Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.\nNote2: Refer to Figure 6.1314 and Figure 6.1315 for RS-485 function mode. 9 1 read-write 0 n RTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART2 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.133. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.133.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.133. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.133. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable \nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic '1' when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 Reserved. #01 2 IrDA function #10 3 RS-485 function #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 15 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empt interrupt Enabled #1 TOCNTEN Time-out Counter Enable Bit 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TXPDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 14 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 WKCTSIEN nCTS Wake-up Interrupt Enable Bit 9 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-up Interrupt Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 HWBUFEIF in DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 HWBUFEINT in DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 HWMODIF in DMA Mode, MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]). 19 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 HWMODINT in DMA Mode, MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 HWRLSIF in DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 HWRLSINT in DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 HWTOIF in DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 HWTOINT in DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 MODEMIF Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote : Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.\nNote2: Refer to Figure 6.1314 and Figure 6.1315 for RS-485 function mode. 9 1 read-write 0 n RTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write UART3 UART Register Map UART 0x0 0x0 0x30 registers n UART_ALTCTL UART_ALTCTL UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ABRDBITS Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit. 19 2 read-write 0 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01 #00 1 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02 #01 2 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08 #10 3 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80 #11 ABRDEN Auto-baud Rate Detect Enable Bit\nThis bit is cleared automatically after auto-baud detection is finished. 18 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 ABRIF Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). 17 1 read-only ADDRDEN RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode. 15 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled #1 ADDRMV Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled #1 RS485AUD RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation function (AUD) Disabled #0 1 RS-485 Auto Direction Operation function (AUD) Enabled #1 RS485NMM RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BAUDM0 BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in Table 6.133. 28 1 read-write BAUDM1 BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in Table 6.133.\nNote: In IrDA mode must be operated in mode 0. 29 1 read-write BRD Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 6.133. 0 16 read-write EDIVM1 Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 6.133. 24 4 read-write UART_DAT UART_DAT UART Receive/Transmit Buffer Register 0x0 read-write n 0x0 0x0 DAT Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO. 0 8 read-write UART_FIFO UART_FIFO UART FIFO Control Register 0x8 read-write n 0x0 0x0 RFITL RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RTSTRGLV nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control. 16 4 read-write 0 nRTS Trigger Level is 1 byte #0000 1 nRTS Trigger Level is 4 bytes #0001 2 nRTS Trigger Level is 8 bytes #0010 3 nRTS Trigger Level is 14 bytes #0011 RXOFF Receiver Disable \nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RXRST RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TXRST TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UART_FIFOSTS UART_FIFOSTS UART FIFO Status Register 0x18 read-write n 0x0 0x0 ABRDIF Auto-baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic '1' when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing '1' to it. 1 1 read-only 0 Auto-baud rate detect function is not finished #0 1 Auto-baud rate detect function is finished #1 ABRDTOIF Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 2 1 read-only 0 Auto-baud rate counter is underflow #0 1 Auto-baud rate counter is overflow #1 ADDRDETF RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it. 3 1 read-only 0 Receiver detects a data that is not an address bit (bit 9 ='0') #0 1 Receiver detects a data that is an address bit (bit 9 ='1') #1 BIF Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit is read only, but can be cleared by writing '1' to it. 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only, but can be cleared by writing '1' to it. 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only, but can be cleared by writing '1' to it. 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RXEMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RXFULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RXOVIF RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RXPTR RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. 8 6 read-only TXEMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TXEMPTYF Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty or the STOP bit of the last byte has been not transmitted #0 1 TX FIFO is empty and the STOP bit of the last byte has been transmitted #1 TXFULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TXOVIF TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 24 1 read-only 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TXPTR TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. 16 6 read-only UART_FUNCSEL UART_FUNCSEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUNCSEL Function Select 0 2 read-write 0 UART function #00 1 Reserved. #01 2 IrDA function #10 3 RS-485 function #11 UART_INTEN UART_INTEN UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 ABRIEN Auto-baud Rate Interrupt Enable Bit 18 1 read-write 0 Auto-baud rate interrupt Disabled #0 1 Auto-baud rate interrupt Enabled #1 ATOCTSEN nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). 13 1 read-write 0 nCTS auto-flow control Disabled #0 1 nCTS auto-flow control Enabled #1 ATORTSEN nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. 12 1 read-write 0 nRTS auto-flow control Disabled #0 1 nRTS auto-flow control Enabled #1 BUFERRIEN Buffer Error Interrupt Enable Bit 5 1 read-write 0 Buffer error interrupt Disabled #0 1 Buffer error interrupt Enabled #1 MODEMIEN Modem Status Interrupt Enable Bit 3 1 read-write 0 Modem status interrupt Disabled #0 1 Modem status interrupt Enabled #1 RDAIEN Receive Data Available Interrupt Enable Bit 0 1 read-write 0 Receive data available interrupt Disabled #0 1 Receive data available interrupt Enabled #1 RLSIEN Receive Line Status Interrupt Enable Bit 2 1 read-write 0 Receive Line Status interrupt Disabled #0 1 Receive Line Status interrupt Enabled #1 RXPDMAEN RX DMA Enable Bit\nThis bit can enable or disable RX DMA service. 15 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXTOIEN RX Time-out Interrupt Enable Bit 4 1 read-write 0 RX time-out interrupt Disabled #0 1 RX time-out interrupt Enabled #1 THREIEN Transmit Holding Register Empty Interrupt Enable Bit 1 1 read-write 0 Transmit holding register empty interrupt Disabled #0 1 Transmit holding register empt interrupt Enabled #1 TOCNTEN Time-out Counter Enable Bit 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TXPDMAEN TX DMA Enable Bit\nThis bit can enable or disable TX DMA service. 14 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 WKCTSIEN nCTS Wake-up Interrupt Enable Bit 9 1 read-write 0 nCTS wake-up system function Disabled #0 1 Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode #1 WKDATIEN Incoming Data Wake-up Interrupt Enable Bit\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable. 10 1 read-write 0 Incoming data wake-up system function Disabled #0 1 Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode #1 UART_INTSTS UART_INTSTS UART Interrupt Status Register 0x1C read-write n 0x0 0x0 BUFERRIF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUFERRINT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1. 13 1 read-only 0 No buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 CTSWKIF nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 16 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by nCTS wake-up #1 DATWKIF Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it. 17 1 read-only 0 Chip stays in power-down state #0 1 Chip wake-up from power-down state by data wake-up #1 HWBUFEIF in DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. 21 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 HWBUFEINT in DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1. 29 1 read-only 0 No buffer error interrupt is generated in DMA mode #0 1 Buffer error interrupt is generated in DMA mode #1 HWMODIF in DMA Mode, MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]). 19 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 HWMODINT in DMA Mode, MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1. 27 1 read-only 0 No Modem interrupt is generated in DMA mode #0 1 Modem interrupt is generated in DMA mode #1 HWRLSIF in DMA Mode, Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. \nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 18 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 HWRLSINT in DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1. 26 1 read-only 0 No RLS interrupt is generated in DMA mode #0 1 RLS interrupt is generated in DMA mode #1 HWTOIF in DMA Mode, Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 20 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 HWTOINT in DMA Mode, Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1. 28 1 read-only 0 No Tout interrupt is generated in DMA mode #0 1 Tout interrupt is generated in DMA mode #1 MODEMIF Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEMINT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDAIF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDAINT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLSIF Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLSINT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 RXTOIF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 RXTOINT Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. 12 1 read-only 0 No Tout interrupt is generated #0 1 Tout interrupt is generated #1 THREIF Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1. 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 WKIF UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]). 6 1 read-only 0 No DATWKIF and CTSWKIF are generated #0 1 DATWKIF or CTSWKIF #1 UART_IRDA UART_IRDA UART IrDA Control Register 0x28 read-write n 0x0 0x0 RXINV IrDA Inverse Receive Input Signal 6 1 read-write 0 None inverse receiving input signal #0 1 Inverse receiving input signal. (Default) #1 TXEN IrDA Receiver/Transmitter Selection Enable Bit 1 1 read-write 0 IrDA Transmitter Disabled and Receiver Enabled. (Default) #0 1 IrDA Transmitter Enabled and Receiver Disabled #1 TXINV IrDA Inverse Transmitting Output Signal 5 1 read-write 0 None inverse transmitting signal. (Default) #0 1 Inverse transmitting output signal #1 UART_LINE UART_LINE UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic. 6 1 read-write 0 Break Control Disabled #0 1 Break Control Enabled #1 EPE Even Parity Enable Bit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of 'STOP Bit' 2 1 read-write 0 One 'STOP bit' is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data #1 PBE Parity Bit Enable Bit\nNote : Parity bit is generated on each outgoing character and is checked on each incoming data. 3 1 read-write 0 No parity bit generated Disabled #0 1 Parity bit generated Enabled #1 SPE Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 WLS Word Length Selection\nThis field sets UART word length. 0 2 read-write 0 5 bits #00 1 6 bits #01 2 7 bits #10 3 8 bits #11 UART_MODEM UART_MODEM UART Modem Control Register 0x10 read-write n 0x0 0x0 RTS nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 nRTS signal is active #0 1 nRTS signal is inactive #1 RTSACTLV nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.\nNote2: Refer to Figure 6.1314 and Figure 6.1315 for RS-485 function mode. 9 1 read-write 0 n RTS pin output is high level active #0 1 nRTS pin output is low level active. (Default) #1 RTSSTS nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status. 13 1 read-only 0 nRTS pin output is low level voltage logic state #0 1 nRTS pin output is high level voltage logic state #1 UART_MODEMSTS UART_MODEMSTS UART Modem Status Register 0x14 read-write n 0x0 0x0 CTSACTLV nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input. 8 1 read-write 0 nCTS pin input is high level active #0 1 nCTS pin input is low level active. (Default) #1 CTSDETF Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only, but can be cleared by writing '1' to it. 0 1 read-only 0 nCTS input has not change state #0 1 nCTS input has change state #1 CTSSTS nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected. 4 1 read-only 0 nCTS pin input is low level voltage logic state #0 1 nCTS pin input is high level voltage logic state #1 UART_TOUT UART_TOUT UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. 8 8 read-write TOIC Time-out Interrupt Comparator 0 8 read-write USBD USBD Register Map USBD 0x0 0x0 0x1C registers n 0x500 0x80 registers n 0x90 0x4 registers n ATTR USBD_ATTR USB Device Bus Status and Attribution Register 0x10 read-write n 0x0 0x0 BYTEM CPU Access USB SRAM Size Mode Selection 10 1 read-write 0 Word mode: The size of the transfer from CPU to USB SRAM can be Word only #0 1 Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only #1 DPPUEN Pull-up Resistor on USB_DP Enable Bit 8 1 read-write 0 Pull-up resistor in USB_D+ bus Disabled #0 1 Pull-up resistor in USB_D+ bus Active #1 PHYEN PHY Transceiver Function Enable Bit 4 1 read-write 0 PHY transceiver function Disabled #0 1 PHY transceiver function Enabled #1 PWRDN Power-down PHY Transceiver, Low Active 9 1 read-write 0 Power-down related circuits of PHY transceiver #0 1 Turn-on related circuits of PHY transceiver #1 RESUME Resume Status\nNote: This bit is read only. 2 1 read-write 0 No bus resume #0 1 Resume from suspend #1 RWAKEUP Remote Wake-up 5 1 read-write 0 Release the USB bus from K state #0 1 Force USB bus to K (USB_D+ low and USB_D- high) state, used for remote wake-up #1 SUSPEND Suspend Status\nNote: This bit is read only. 1 1 read-write 0 Bus no suspend #0 1 Bus idle more than 3 ms, either cable is plugged off or host is sleeping #1 TOUT Time-out Status\nNote: This bit is read only. 3 1 read-write 0 No time-out #0 1 No Bus response more than 18 bits time #1 USBEN USB Controller Enable Bit 7 1 read-write 0 USB Controller Disabled #0 1 USB Controller Enabled #1 USBRST USB Reset Status\nNote: This bit is read only. 0 1 read-write 0 Bus no reset #0 1 Bus reset when SE0 (single-ended 0) more than 2.5us #1 BUFSEG0 USBD_BUFSEG0 USB Endpoint 0 Buffer Segmentation Register 0x500 read-write n 0x0 0x0 BUFSEG Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG[8:3], 3'b000}\nRefer to the section 6.17.5.7 for the endpoint SRAM structure and its description. 3 6 read-write BUFSEG1 USBD_BUFSEG1 USB Endpoint 1 Buffer Segmentation Register 0x510 read-write n 0x0 0x0 BUFSEG2 USBD_BUFSEG2 USB Endpoint 2 Buffer Segmentation Register 0x520 read-write n 0x0 0x0 BUFSEG3 USBD_BUFSEG3 USB Endpoint 3 Buffer Segmentation Register 0x530 read-write n 0x0 0x0 BUFSEG4 USBD_BUFSEG4 USB Endpoint 4 Buffer Segmentation Register 0x540 read-write n 0x0 0x0 BUFSEG5 USBD_BUFSEG5 USB Endpoint 5 Buffer Segmentation Register 0x550 read-write n 0x0 0x0 BUFSEG6 USBD_BUFSEG6 USB Endpoint 6 Buffer Segmentation Register 0x560 read-write n 0x0 0x0 BUFSEG7 USBD_BUFSEG7 USB Endpoint 7 Buffer Segmentation Register 0x570 read-write n 0x0 0x0 CFG0 USBD_CFG0 USB Endpoint 0 Configuration Register 0x508 read-write n 0x0 0x0 CSTALL Clear STALL Response 9 1 read-write 0 Disable the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQSYNC Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EPNUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshaking. 4 1 read-write 0 No Isochronous endpoint #0 1 Isochronous endpoint #1 STATE Endpoint State 5 2 read-write 0 Endpoint Disabled #00 1 Out endpoint #01 2 IN endpoint #10 3 Undefined #11 CFG1 USBD_CFG1 USB Endpoint 1 Configuration Register 0x518 read-write n 0x0 0x0 CFG2 USBD_CFG2 USB Endpoint 2 Configuration Register 0x528 read-write n 0x0 0x0 CFG3 USBD_CFG3 USB Endpoint 3 Configuration Register 0x538 read-write n 0x0 0x0 CFG4 USBD_CFG4 USB Endpoint 4 Configuration Register 0x548 read-write n 0x0 0x0 CFG5 USBD_CFG5 USB Endpoint 5 Configuration Register 0x558 read-write n 0x0 0x0 CFG6 USBD_CFG6 USB Endpoint 6 Configuration Register 0x568 read-write n 0x0 0x0 CFG7 USBD_CFG7 USB Endpoint 7 Configuration Register 0x578 read-write n 0x0 0x0 CFGP0 USBD_CFGP0 USB Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x50C read-write n 0x0 0x0 CLRRDY Clear Ready\nWhen the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\nFor IN token\nThis bit is write 1 only and is always 0 when it is read back. 0 1 read-write 0 No effect #0 1 Clear the IN token had ready to transmit the data to USB host.\nClear the OUT token had ready to receive the data from USB host #1 SSTALL Set STALL 1 1 read-write 0 Disable the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFGP1 USBD_CFGP1 USB Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x51C read-write n 0x0 0x0 CFGP2 USBD_CFGP2 USB Endpoint 2 Set Stall and Clear In/Out Ready Control Register 0x52C read-write n 0x0 0x0 CFGP3 USBD_CFGP3 USB Endpoint 3 Set Stall and Clear In/Out Ready Control Register 0x53C read-write n 0x0 0x0 CFGP4 USBD_CFGP4 USB Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x54C read-write n 0x0 0x0 CFGP5 USBD_CFGP5 USB Endpoint 5 Set Stall and Clear In/Out Ready Control Register 0x55C read-write n 0x0 0x0 CFGP6 USBD_CFGP6 USB Endpoint 6 Set Stall and Clear In/Out Ready Control Register 0x56C read-write n 0x0 0x0 CFGP7 USBD_CFGP7 USB Endpoint 7 Set Stall and Clear In/Out Ready Control Register 0x57C read-write n 0x0 0x0 EPSTS USBD_EPSTS USB Device Endpoint Status Register 0xC read-only n 0x0 0x0 EPSTS0 Endpoint 0 Status\nThese bits are used to indicate the current status of this endpoint 8 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS1 Endpoint 1 Status\nThese bits are used to indicate the current status of this endpoint 11 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS2 Endpoint 2 Status\nThese bits are used to indicate the current status of this endpoint 14 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS3 Endpoint 3 Status\nThese bits are used to indicate the current status of this endpoint 17 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS4 Endpoint 4 Status\nThese bits are used to indicate the current status of this endpoint 20 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS5 Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint 23 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS6 Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint 26 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 EPSTS7 Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint 29 3 read-only 0 In ACK #000 1 In NAK #001 2 Out Packet Data0 ACK #010 3 Setup ACK #011 6 Out Packet Data1 ACK #110 7 Isochronous transfer end #111 OV Overrun\nIt indicates that the received data is over the maximum payload number or not. 7 1 read-only 0 No overrun #0 1 Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes #1 FADDR USBD_FADDR USB Device Function Address Register 0x8 read-write n 0x0 0x0 FADDR USB Device Function Address 0 7 read-write INTEN USBD_INTEN USB Device Interrupt Enable Register 0x0 read-write n 0x0 0x0 BUSIEN Bus Event Interrupt Enable Bit 0 1 read-write 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 INNAKEN Active NAK Function and Its Status in IN Token 15 1 read-write 0 When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted #0 1 IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token #1 NEVWKIEN USB No-event-wake-up Interrupt Enable Bit 3 1 read-write 0 No-event-wake-up Interrupt Disabled #0 1 No-event-wake-up Interrupt Enabled #1 USBIEN USB Event Interrupt Enable Bit 1 1 read-write 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 VBDETIEN VBUS Detection Interrupt Enable Bit 2 1 read-write 0 VBUS detection Interrupt Disabled #0 1 VBUS detection Interrupt Enabled #1 WKEN Wake-up Function Enable Bit 8 1 read-write 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 INTSTS USBD_INTSTS USB Device Interrupt Event Status Register 0x4 read-write n 0x0 0x0 BUSIF BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus. 0 1 read-write 0 No BUS event occurred #0 1 Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0] #1 EPEVT0 Endpoint 0's USB Event Status 16 1 read-write 0 No event occurred in endpoint 0 #0 1 USB event occurred on Endpoint 0, check USBD_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1] #1 EPEVT1 Endpoint 1's USB Event Status 17 1 read-write 0 No event occurred in endpoint 1 #0 1 USB event occurred on Endpoint 1, check USBD_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1] #1 EPEVT2 Endpoint 2's USB Event Status 18 1 read-write 0 No event occurred in endpoint 2 #0 1 USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1] #1 EPEVT3 Endpoint 3's USB Event Status 19 1 read-write 0 No event occurred in endpoint 3 #0 1 USB event occurred on Endpoint 3, check USBD_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1] #1 EPEVT4 Endpoint 4's USB Event Status 20 1 read-write 0 No event occurred in endpoint 4 #0 1 USB event occurred on Endpoint 4, check USBD_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1] #1 EPEVT5 Endpoint 5's USB Event Status 21 1 read-write 0 No event occurred in endpoint 5 #0 1 USB event occurred on Endpoint 5, check USBD_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1] #1 EPEVT6 Endpoint 6's USB Event Status 22 1 read-write 0 No event occurred in endpoint 6 #0 1 USB event occurred on Endpoint 6, check USBD_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1] #1 EPEVT7 Endpoint 7's USB Event Status 23 1 read-write 0 No event occurred in endpoint 7 #0 1 USB event occurred on Endpoint 7, check USBD_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1] #1 NEVWKIF No-event-wake-up Interrupt Status 3 1 read-write 0 NEVWK event does not occur #0 1 No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3] #1 SETUP Setup Event Status 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by write 1 to USBD_INTSTS[31] #1 USBIF USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN or ISO OUT events in the bus. 1 1 read-write 0 No USB event occurred #0 1 USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31]) #1 VBDETIF VBUS Detection Interrupt Status 2 1 read-write 0 There is not attached/detached event in the USB #0 1 There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2] #1 MXPLD0 USBD_MXPLD0 USB Endpoint 0 Maximal Payload Register 0x504 read-write n 0x0 0x0 MXPLD Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length received from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write MXPLD1 USBD_MXPLD1 USB Endpoint 1 Maximal Payload Register 0x514 read-write n 0x0 0x0 MXPLD2 USBD_MXPLD2 USB Endpoint 2 Maximal Payload Register 0x524 read-write n 0x0 0x0 MXPLD3 USBD_MXPLD3 USB Endpoint 3 Maximal Payload Register 0x534 read-write n 0x0 0x0 MXPLD4 USBD_MXPLD4 USB Endpoint 4 Maximal Payload Register 0x544 read-write n 0x0 0x0 MXPLD5 USBD_MXPLD5 USB Endpoint 5 Maximal Payload Register 0x554 read-write n 0x0 0x0 MXPLD6 USBD_MXPLD6 USB Endpoint 6 Maximal Payload Register 0x564 read-write n 0x0 0x0 MXPLD7 USBD_MXPLD7 USB Endpoint 7 Maximal Payload Register 0x574 read-write n 0x0 0x0 SE0 USBD_SE0 USB Device Drive SE0 Control Register 0x90 read-write n 0x0 0x0 SE0 Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. 0 1 read-write 0 Normal operation #0 1 Force USB PHY transceiver to drive SE0 #1 STBUFSEG USBD_STBUFSEG USB Setup Token Buffer Segmentation Register 0x18 read-write n 0x0 0x0 STBUFSEG SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG, 3'b000} \nNote: It is used for SETUP token only. 3 6 read-write VBUSDET USBD_VBUSDET USB Device VBUS Detection Register 0x14 read-only n 0x0 0x0 VBUSDET Device VBUS Detection 0 1 read-only 0 Controller is not attached to the USB host #0 1 Controller is attached to the USB host #1 USBH USBH Register Map USBH 0x0 0x0 0x58 registers n 0x200 0x8 registers n HCBULKCURRENTED HCBULKCURRENTED Host Controller Bulk Current ED Register 0x2C read-write n 0x0 0x0 BCED Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list. 4 28 read-write HCBULKHEADED HCBULKHEADED Host Controller Bulk Head ED Register 0x28 read-write n 0x0 0x0 BHED Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. 4 28 read-write HCCOMMANDSTATUS HCCOMMANDSTATUS Host Controller CMD Status Register 0x8 read-write n 0x0 0x0 BLF Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. 2 1 read-write 0 No active TD found or Host Controller begins to process the head of the Bulk list #0 1 An active TD added or found on the Bulk list #1 CLF Control List Filled\nSet high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. 1 1 read-write 0 No active TD found or Host Controller begins to process the head of the Control list #0 1 An active TD added or found on the Control list #1 HCR Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller, upon completed of the reset operation.\nThis bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. 0 1 read-write 0 Host Controller is not in software reset state #0 1 Host Controller is in software reset state #1 SOC Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. 16 2 read-write HCCONTROL HCCONTROL Host Controller Control Register 0x4 read-write n 0x0 0x0 BLE Bulk List Enable Bit 5 1 read-write 0 Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Bulk list in the next frame Enabled #1 CBSR Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this\nValue. 0 2 read-write 0 Number of Control EDs over Bulk EDs served is 1:1 #00 1 Number of Control EDs over Bulk EDs served is 2:1 #01 2 Number of Control EDs over Bulk EDs served is 3:1 #10 3 Number of Control EDs over Bulk EDs served is 4:1 #11 CLE Control List Enable Bit 4 1 read-write 0 Processing of the Control list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Control list in the next frame Enabled #1 HCFS Host Controller Functional State\nThis field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are: 6 2 read-write 0 USBRESET #00 1 USBRESUME #01 2 USBOPERATIONAL #10 3 USBSUSPEND #11 IE Isochronous List Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. 3 1 read-write 0 Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too #1 PLE Periodic List Enable Bit\nWhen set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.\nNote: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. 2 1 read-write 0 Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled #0 1 Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled #1 HCCONTROLCURRENTED HCCONTROLCURRENTED Host Controller Control Current ED Register 0x24 read-write n 0x0 0x0 CCED Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list. 4 28 read-write HCCONTROLHEADED HCCONTROLHEADED Host Controller Control Head ED Register 0x20 read-write n 0x0 0x0 CHED Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list. 4 28 read-write HCDONEHEAD HCDONEHEAD Host Controller Done Head Register 0x30 read-write n 0x0 0x0 DH Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. 4 28 read-write HCFMINTERVAL HCFMINTERVAL Host Controller Frame Interval Register 0x34 read-write n 0x0 0x0 FI Frame Interval\nThis field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. 0 14 read-write FIT Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). 31 1 read-write 0 Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]) #0 1 Host Controller Driver loads a new value into FI (HcFmInterval[13:0]) #1 FSMPS FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. 16 15 read-write HCFMNUMBER HCFMNUMBER Host Controller Frame Number Register 0x3C read-only n 0x0 0x0 FN Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.' 0 16 read-only HCFMREMAINING HCFMREMAINING Host Controller Frame Remaining Register 0x38 read-only n 0x0 0x0 FR Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with Frame Interval. In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. 0 14 read-only FRT Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. 31 1 read-only HCHCCA HCHCCA Host Controller Communication Area Register 0x18 read-write n 0x0 0x0 HCCA Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA). 8 24 read-write HCINTERRUPTDISABLE HCINTERRUPTDISABLE Host Controller Interrupt Disable Register 0x14 read-write n 0x0 0x0 FNO Frame Number Overflow Disable Bit\nWrite Operation: 5 1 read-write 0 No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled #0 1 Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Enabled #1 MIE Master Interrupt Disable Bit\nGlobal interrupt disable. Writing '1' to disable all interrupts.\nWrite Operation: 31 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high #1 RD Resume Detected Disable Bit\nWrite Operation: 3 1 read-write 0 No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled #0 1 Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.\nInterrupt generation due to RD (HcInterruptStatus[3]) Enabled #1 RHSC Root Hub Status Change Disable Bit\nWrite Operation: 6 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Enabled #1 SF Start of Frame Disable Bit\nWrite Operation: 2 1 read-write 0 No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled #0 1 Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.\nInterrupt generation due to SF (HcInterruptStatus[2]) Enabled #1 SO Scheduling Overrun Disable Bit\nWrite Operation: 0 1 read-write 0 No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled #0 1 Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.\nInterrupt generation due to SO (HcInterruptStatus[0]) Enabled #1 WDH Write Back Done Head Disable Bit\nWrite Operation: 1 1 read-write 0 No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled #0 1 Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Enabled #1 HCINTERRUPTENABLE HCINTERRUPTENABLE Host Controller Interrupt Enable Register 0x10 read-write n 0x0 0x0 FNO Frame Number Overflow Enable Bit\nWrite Operation: 5 1 read-write 0 No effect.\nInterrupt generation due to FNO (HcInterruptStatus[5]) Disabled #0 1 Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled #1 MIE Master Interrupt Enable Bit\nThis bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.\nWrite Operation: 31 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high #1 RD Resume Detected Enable Bit\nWrite Operation: 3 1 read-write 0 No effect.\nInterrupt generation due to RD (HcInterruptStatus[3]) Disabled #0 1 Interrupt generation due to RD (HcInterruptStatus[3]) Enabled #1 RHSC Root Hub Status Change Enable Bit\nWrite Operation: 6 1 read-write 0 No effect.\nInterrupt generation due to RHSC (HcInterruptStatus[6]) Disabled #0 1 Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled #1 SF Start of Frame Enable Bit\nWrite Operation: 2 1 read-write 0 No effect.\nInterrupt generation due to SF (HcInterruptStatus[2]) Disabled #0 1 Interrupt generation due to SF (HcInterruptStatus[2]) Enabled #1 SO Scheduling Overrun Enable Bit\nWrite Operation: 0 1 read-write 0 No effect.\nInterrupt generation due to SO (HcInterruptStatus[0]) Disabled #0 1 Interrupt generation due to SO (HcInterruptStatus[0]) Enabled #1 WDH Write Back Done Head Enable Bit\nWrite Operation: 1 1 read-write 0 No effect.\nInterrupt generation due to WDH (HcInterruptStatus[1]) Disabled #0 1 Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled #1 HCINTERRUPTSTATUS HCINTERRUPTSTATUS Host Controller Interrupt Status Register 0xC read-write n 0x0 0x0 FNO Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. 5 1 read-write 0 The bit 15 of Frame Number didn't change #0 1 The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1 #1 RD Resume Detected\nSet when Host Controller detects resume signaling on a downstream port. 3 1 read-write 0 No resume signaling detected on a downstream port #0 1 Resume signaling detected on a downstream port #1 RHSC Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed. 6 1 read-write 0 The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change #0 1 The content of HcRhStatus or the content of HcRhPortStatus1 register has changed #1 SF Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time. 2 1 read-write 0 .Not the start of a frame #0 1 .Indicate the start of a frame and Host Controller generates a SOF token #1 SO Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred. 0 1 read-write 0 Schedule Overrun didn't occur #0 1 Schedule Overrun has occurred #1 WDH Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. 1 1 read-write 0 .Host Controller didn't update HccaDoneHead #0 1 .Host Controller has written HcDoneHead to HccaDoneHead #1 HCLSTHRESHOLD HCLSTHRESHOLD Host Controller Low-speed Threshold Register 0x44 read-write n 0x0 0x0 LST Low-speed Threshold 0 12 read-write HCMISCCONTROL HCMISCCONTROL Host Controller Miscellaneous Control Register 0x204 read-write n 0x0 0x0 ABORT AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus. 1 1 read-write 0 No ERROR response received #0 1 ERROR response received #1 DPRT1 Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled, the USB host controller will not recognize any event of USB bus.\nSet this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. 16 1 read-write 0 The connection between USB host controller and transceiver of port 1 Enabled #0 1 The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode #1 OCAL over Current Active Low\nThis bit controls the polarity of over current flag from external power IC. 3 1 read-write 0 Over current flag is high active #0 1 Over current flag is low active #1 HCPERIODCURRENTED HCPERIODCURRENTED Host Controller Period Current ED Register 0x1C read-write n 0x0 0x0 PCED Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. 4 28 read-write HCPERIODICSTART HCPERIODICSTART Host Controller Periodic Start Register 0x40 read-write n 0x0 0x0 PS Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. 0 14 read-write HCPHYCONTROL HCPHYCONTROL Host Controller PHY Control Regsiter 0x200 read-write n 0x0 0x0 STBYEN USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption. 27 1 read-write 0 The USB transceiver would never enter the standby mode #0 1 The USB transceiver will enter standby mode while port is in power off state (port power is inactive) #1 HCREVISION HCREVISION Host Controller Revision Register 0x0 read-only n 0x0 0x0 REV Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification. 0 8 read-only HCRHDESCRIPTORA HCRHDESCRIPTORA Host Controller Root Hub Descriptor A Register 0x48 read-write n 0x0 0x0 NDP Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip. 0 8 read-write NOCP No over Current Protection\nThis bit describes how the over current status for the Root Hub ports reported. 12 1 read-write 0 Over current status is reported #0 1 Over current status is not reported #1 OCPM over Current Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. 11 1 read-write 0 Global Over current #0 1 Individual Over current #1 PSM Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled. 8 1 read-write 0 Global Switching #0 1 Individual Switching #1 HCRHDESCRIPTORB HCRHDESCRIPTORB Host Controller Root Hub Descriptor B Register 0x4C read-write n 0x0 0x0 PPCM Port Power Control Mask\nGlobal power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).\nNote: PPCM[15:2] and PPCM[0] are reserved. 16 16 read-write 0 Port power controlled by global power switching 0 1 Port power controlled by port power switching 1 HCRHPORTSTATUS1 HCRHPORTSTATUS1 Host Controller Root Hub Port Status [1] 0x54 read-write n 0x0 0x0 CCS CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\nWrite Operation: 0 1 read-write 0 No effect.\nNo device connected #0 1 Clear port enable.\nDevice connected #1 CSC Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero. 16 1 read-write 0 No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change) #0 1 Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed) #1 LSDA Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.\nThis bit is also used to clear port power.\nWrite Operation: 9 1 read-write 0 No effect.\nFull Speed device #0 1 Clear PPS (HcRhPortStatus1[8]).\nLow-speed device #1 OCIC Port over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to 0. 19 1 read-write 0 POCI (HcRhPortStatus1[3]) didn't change #0 1 POCI (HcRhPortStatus1[3]) changes #1 PES Port Enable Status\nWrite Operation: 1 1 read-write 0 No effect.\nPort Disabled #0 1 Set port enable.\nPort Enabled #1 PESC Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to 0. 17 1 read-write 0 PES (HcRhPortStatus1[1]) didn't change #0 1 PES (HcRhPortStatus1[1]) changed #1 POCI Port over Current Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.\nThis bit is also used to initiate the selective result sequence for the port.\nWrite Operation: 3 1 read-write 0 No effect.\nNo over current condition #0 1 Clear port suspend.\nOver current condition #1 PPS Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation: 8 1 read-write 0 No effect.\nPort power Diabled #0 1 Port Power Enabled.\nPort power Enabled #1 PRS Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation: 4 1 read-write 0 No effect.\nPort reset signal is not active #0 1 Set port reset.\nPort reset signal is active #1 PRSC Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to 0. 20 1 read-write 0 Port reset is not complete #0 1 Port reset is complete #1 PSS Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation: 2 1 read-write 0 No effect.\nPort is not suspended #0 1 Set port suspend.\nPort is selectively suspended #1 PSSC Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to 0. 18 1 read-write 0 Port resume is not completed #0 1 Port resume completed #1 HCRHSTATUS HCRHSTATUS Host Controller Root Hub Status Register 0x50 read-write n 0x0 0x0 CRWE Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation: 31 1 read-write 0 No effect #0 1 Clear DRWE (HcRhStatus[15]) #1 DRWE Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation: 15 1 read-write 0 No effect.\nConnect Status Change as a remote wake-up event Disabled #0 1 Connect Status Change as a remote wake-up event Enabled #1 LPS Clear Global Power 0 1 read-write 0 No effect #0 1 Clear global power #1 LPSC Set Global Power 16 1 read-write 0 No effect #0 1 Set global power #1 OCI over Current Indicator\nThis bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. 1 1 read-write 0 No over current condition #0 1 Over current condition #1 OCIC over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero. 17 1 read-write 0 OCI (HcRhStatus[1]) didn't change #0 1 OCI (HcRhStatus[1]) change #1 WDT WDT Register Map WDT 0x0 0x0 0x8 registers n ALTCTL WDT_ALTCTL WDT Alternative Control Register 0x4 read-write n 0x0 0x0 RSTDSEL WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 WDT Reset Delay Period is 1026 * WDT_CLK #00 1 WDT Reset Delay Period is 130 * WDT_CLK #01 2 WDT Reset Delay Period is 18 * WDT_CLK #10 3 WDT Reset Delay Period is 3 * WDT_CLK #11 CTL WDT_CTL WDT Control Register 0x0 read-write n 0x0 0x0 ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 31 1 read-write 0 ICE debug mode acknowledgement affects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 IF WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 INTEN WDT Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 RSTCNT Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 RSTEN WDT Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 RSTF WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 TOUTSEL WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 8 3 read-write 0 24 * WDT_CLK #000 1 26 * WDT_CLK #001 2 28 * WDT_CLK #010 3 210 * WDT_CLK #011 4 212 * WDT_CLK #100 5 214 * WDT_CLK #101 6 216 * WDT_CLK #110 7 218 * WDT_CLK #111 WDTEN WDT Enable Control (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. 7 1 read-write 0 WDT Disabled (This action will reset the internal up counter value) #0 1 WDT Enabled #1 WKEN WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WKF WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n CNT WWDT_CNT WWDT Counter Value Register 0xC read-only n 0x0 0x0 CNTDAT WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 0 6 read-only CTL WWDT_CTL WWDT Control Register 0x4 read-write n 0x0 0x0 CMPDAT WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. 16 6 read-write ICEDEBUG ICE Debug Mode Acknowledge Disable Control\nThe WWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 INTEN WWDT Interrupt Enable Control Bit\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 PSCSEL WWDT Counter Prescale Period Selection 8 4 read-write 0 Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK #0000 1 Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK #0001 2 Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK #0010 3 Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK #0011 4 Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK #0100 5 Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK #0101 6 Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK #0110 7 Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK #0111 8 Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK #1000 9 Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK #1001 10 Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK #1010 11 Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK #1011 12 Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK #1100 13 Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK #1101 14 Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK #1110 15 Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK #1111 WWDTEN WWDT Enable Control Bit\nSet this bit to enable WWDT counter counting. 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 RLDCNT WWDT_RLDCNT WWDT Reload Counter Register 0x0 write-only n 0x0 0x0 RLDCNT WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. 0 32 write-only STATUS WWDT_STATUS WWDT Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches CMPDAT #1 WWDTRF WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1