nuvoTon
MINI51AN_v1
2024.05.05
MINI51AN_v1 SVD file
8
32
ADC
ADC Register Map
ADC
0x0
0x0
0x4
registers
n
0x20
0x14
registers
n
0x44
0x4
registers
n
ADCHER
ADCHER
A/D Channel Enable Register
0x24
read-write
n
0x0
0x0
CHEN0
Analog Input Channel 0 Enable\nNote: If software enables more than one channel, the channel with the lowest number will be selected and the other enabled channels will be ignored. That means channel 0 is the highest priority.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN1
Analog Input Channel 1 Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN2
Analog Input Channel 2 Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN3
Analog Input Channel 3 Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN4
Analog Input Channel 4 Enable\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN5
Analog Input Channel 5 Enable\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN6
Analog Input Channel 6 Enable\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
CHEN7
Analog Input Channel 7 Enable\n
7
1
read-write
0
Disabled
#0
1
Enabled
#1
PRESEL
Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
8
1
read-write
0
Analog Input Channel 7
#0
1
Band-gap (VBG) Analog Input
#1
ADCMPR0
ADCMPR0
A/D Compare Register 0
0x28
read-write
n
0x0
0x0
CMPCH
Compare Channel Selection\n
3
3
read-write
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
2
1
read-write
0
Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
16
10
read-write
CMPEN
Compare Enable\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.
0
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CMPIE
Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
CMPMATCNT
Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
8
4
read-write
ADCMPR1
ADCMPR1
A/D Compare Register 1
0x2C
read-write
n
0x0
0x0
ADCR
ADCR
A/D Control Register
0x20
read-write
n
0x0
0x0
ADEN
A/D Converter Enable\nBefore starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADIE
A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
1
1
read-write
0
A/D interrupt function Disabled
#0
1
A/D interrupt function Enabled
#1
ADST
A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically.
11
1
read-write
0
Conversion stopped and A/D converter entered idle state
#0
1
Conversion start
#1
TRGCOND
External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
6
1
read-write
0
Falling edge
#0
1
Raising edge
#1
TRGEN
External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGS
Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
4
2
read-write
0
A/D conversion is started by external STADC pin
#00
3
A/D conversion is started by PWM trigger
#11
ADDR
ADDR
A/D Data Register
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read.
16
1
read-only
0
Data in RSLT[9:0] is recent conversion result
#0
1
Data in RSLT[9:0] overwritten
#1
RSLT
A/D Conversion Result\nThis field contains conversion result of ADC.
0
10
read-only
VALID
Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read.
17
1
read-only
0
Data in RSLT[9:0] bits not valid
#0
1
Data in RSLT[9:0] bits valid
#1
ADSR
ADSR
A/D Status Register
0x30
read-write
n
0x0
0x0
ADF
A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero.
0
1
read-write
BUSY
BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
3
1
read-write
0
A/D converter is in idle state
#0
1
A/D converter is busy at conversion
#1
CHANNEL
Current Conversion Channel\nIt is read only.
4
3
read-write
CMPF0
Compare Flag #0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
1
1
read-write
0
Conversion result in ADDR does not meet the ADCMPR0 setting
#0
1
Conversion result in ADDR meets the ADCMPR0 setting
#1
CMPF1
Compare Flag #1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
2
1
read-write
0
Conversion result in ADDR does not meet the ADCMPR1 setting
#0
1
Conversion result in ADDR meets the ADCMPR1 setting
#1
OVERRUN
Over Run Flag\nIt is a mirror to OVERRUN bit in ADDR.
16
1
read-write
VALID
Data Valid Flag\nIt is a mirror of VALID bit in ADDR.
8
1
read-write
ADTDCR
ADTDCR
A/D Trigger Delay Control Register
0x44
read-write
n
0x0
0x0
PTDT
PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock
0
8
read-write
CLK
CLK Register Map
CLK
0x0
0x0
0x20
registers
n
0x24
0x4
registers
n
AHBCLK
AHBCLK
AHB Device Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
ISP_EN
Flash ISP Controller Clock Enable Control\n
2
1
read-write
0
Flash ISP engine clock Disabled
#0
1
Flash ISP engine clock Enabled
#1
APBCLK
APBCLK
APB Device Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ADC_EN
Analog-Digital-Converter (ADC) Clock Enable Control\n
28
1
read-write
0
Both the ADC's APB and the engine clock Disabled
#0
1
Both the ADC's APB and the engine clock Enabled
#1
CMP_EN
Comparator Clock Enable\n
30
1
read-write
0
Analog Comparator Clock Disabled
#0
1
Analog Comparator Clock Enabled
#1
FDIV_EN
Clock Divider Clock Enable Control\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
I2C_EN
I2C Clock Enable Control\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01_EN
PWM_01 Clock Enable Control\n
20
1
read-write
0
Both the PWM01 APB and the engine clock Disabled
#0
1
Both the PWM01 APB and the engine clock Enabled
#1
PWM23_EN
PWM_23 Clock Enable Control\n
21
1
read-write
0
Both the PWM23 APB and the engine clock Disabled
#0
1
Both the PWM23 APB and the engine clock Enabled
#1
PWM45_EN
PWM_45 Clock Enable Control\n
22
1
read-write
0
Both the PWM45 APB and the engine clock Disabled
#0
1
Both the PWM45 APB and the engine clock Enabled
#1
SPI_EN
SPI Clock Enable Control\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
TMR0_EN
Timer0 Clock Enable Control\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TMR1_EN
Timer1 Clock Enable Control\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
UART_EN
UART Clock Enable Control\n
16
1
read-write
0
Both the UART APB and the engine clock Disabled
#0
1
Both the UART APB and the engine clock Enabled
#1
WDT_EN
Watchdog Clock Enable
This bit is the protected bit programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC Clock Divide Number from ADC Clock Source\n
16
8
read-write
HCLK_N
HCLK Clock Divide Number from HCLK Clock Source\n
0
4
read-write
UART_N
UART Clock Divide Number from UART Clock Source\n
8
4
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
-1
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Selection
Note: Before clock switch the related clock sources (pre-select and new-select) must be turned on.
These bits are protected bit programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.
Note: To set PWRCON[1:0] to select HXT or LXT crystal clock.
0
3
read-write
0
Clock source from HXT or LXT crystal clock
#000
1
Reserved
#001
2
Reserved
#010
3
Clock source from LIRC oscillator clock
#011
7
Clock source from HIRC oscillator clock
#111
STCLK_S
Cortex-M0 CPU SysTick Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
3
3
read-write
0
Clock source from HXT or LXT crystal clock
#000
1
Reserved
#001
2
Clock source from HXT or LXT crystal clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from HIRC oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
ADC_S
ADC Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source from HXT or LXT crystal clock
#00
1
Reserved
#01
2
Clock source from HCLK clock
#10
3
Clock source from HIRC oscillator clock
#11
PWM01_S
PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
28
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Reserved
#11
PWM23_S
PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
30
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Reserved
#11
TMR0_S
TIMER0 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
8
3
read-write
0
Clock source from HXT or LXT crystal clock
#000
1
Clock source from LIRC oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
7
Clock source from HIRC oscillator clock
#111
TMR1_S
TIMER1 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
12
3
read-write
0
Clock source from HXT or LXT crystal clock
#000
1
Clock source from LIRC oscillator clock
#001
2
Clock source from HCLK
#010
3
Clock source from external trigger
#011
7
Clock source from HIRC oscillator clock
#111
UART_S
UART Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
24
2
read-write
0
Clock source from HXT or LXT crystal clock
#00
1
Reserved
#01
2
Clock source from HIRC oscillator clock
#10
3
Reserved
#11
WDT_S
WDT CLK Clock Source Selection\nThese bits are protected bit, programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
0
2
read-write
0
Clock source from HXT or LXT crystal clock
#00
1
Reserved
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from LIRC oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
2
2
read-write
0
Clock source from HXT or LXT crystal clock
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Clock source from HIRC oscillator clock
#11
PWM45_S
PWM4 and PWM5 Clock Source Selection - PWM4 and PWM5 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
4
2
read-write
0
Reserved
#00
1
Reserved
#01
2
Clock source from HCLK
#10
3
Reserved
#11
CLKSTATUS
CLKSTATUS
Clock Status Monitor Register
0xC
-1
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switch Fail Flag\nThis bit will be set when target switch clock source is not stable.\nSoftware can write 1 to clear this bit to zero.
7
1
read-write
0
Clock switch success
#0
1
Clock switch failed
#1
OSC10K_STB
LIRC Clock Source Stable Flag\n
3
1
read-write
0
LIRC clock not stable or not enabled
#0
1
LIRC clock stable
#1
OSC22M_STB
HIRC Clock Source Stable Flag\n
4
1
read-write
0
HIRC clock not stable or not enabled
#0
1
HIRC clock stable
#1
XTL_STB
HXT or LXT Clock Source Stable Flag
0
1
read-write
0
HXT or LXT clock not stable or not enabled
#0
1
HXT or LXT clock stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit\n
4
1
read-write
0
Frequency Divider Disabled
#0
1
Frequency Divider Enabled
#1
FSEL
Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
0
4
read-write
PWRCON
PWRCON
System Power-down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
LIRC Control\n
3
1
read-write
0
LIRC oscillator Disabled
#0
1
LIRC oscillator Enabled
#1
OSC22M_EN
HIRC Control\nNote: The default of OSC22M_EN bit is 1.
2
1
read-write
0
HIRC oscillator Disabled
#0
1
HIRC oscillator Enabled
#1
PD_32K
This bit controls the crystal oscillator active or not in Power-down mode.\n
9
1
read-write
0
No effect to Power-down mode
#0
1
If XTLCLK_EN[1:0] = 10, LXT is still active in Power-down mode
#1
PD_WU_INT_EN
Power-down Mode Wake-up Interrupt Enable (Write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Disabled
#0
1
Enabled. The interrupt will occur when Power-down mode wake up
#1
PD_WU_STS
Power-down Mode Wake-up Interrupt Status
When set by power-down wake-up event , it indicates that resume from Power-down mode.
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred.
Software can write 1 to clear the bit to zero.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) is set to 1.
6
1
read-write
PWR_DOWN_EN
System Power-down Active or Enable Bit\nWhen chip waked up from power-down, this bit is automatically cleared, and user needs to set this bit again for the next power-down.\nIn Power-down mode, the LDO, external crystal and the HIRC will be disabled, and the LIRC enable is not controlled by this bit.\n
7
1
read-write
0
Chip operated in Normal mode or CPU enters into Idle mode
#0
1
Chip entering the Power-down mode instantly or wait CPU Idle command
#1
WU_DLY
Wake-up Delay Counter Enable (Write-protected)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT, 4096 clock cycle for LXT, and 16 clock cycles when chip work at HIRC oscillator.\n
4
1
read-write
0
Clock cycles delay Disabled
#0
1
Clock cycles delay Enabled
#1
XTLCLK_EN
External HXT or LXT Crystal Oscillator Control
The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO.
Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
0
2
read-write
0
XTAL1 and XTAL2 are GPIO, disable both LXT HXT (default)
#00
1
HXT Enabled
#01
2
LXT Enabled
#10
3
XTAL1 is external clock input pin, XTAL2 is GPIO
#11
CMP
CMP Register Map
CMP
0x0
0x0
0x10
registers
n
CMP0CR
CMP0CR
Comparator0 Control Register
0x0
read-write
n
0x0
0x0
CMP0EN
Comparator0 Enable\nComparator output needs to wait 10 us stable time after CMP0EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0IE
Comparator0 Interrupt Enable\nInterrupt is generated if CMP0IE bit is set to 1 after CMP0 conversion finished.
1
1
read-write
0
CMP0 interrupt function Disabled
#0
1
CMP0 interrupt function Enabled
#1
CMP0_FALLING
Comparator0 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer.
9
1
read-write
0
Disable comparator0 trigger PWM/Timer on falling edge
#0
1
Enable comparator0 trigger PWM/Timer on falling edge
#1
CMP0_HYSEN
Comparator0 Hysteresis Enable\n
2
1
read-write
0
CMP0 Hysteresis function Disabled (Default)
#0
1
CMP0 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
#1
CMP0_RISING
Comparator0 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer.
8
1
read-write
0
Disable comparator0 trigger PWM/Timer on rising edge
#0
1
Enable comparator0 trigger PWM/Timer on rising edge
#1
CN0
Comparator0 Negative Input Selection\n
4
1
read-write
0
The comparator reference pin CPN0 is selected as the negative comparator input
#0
1
The internal comparator reference voltage (Vref = 1.25V or from CRV setting value) is selected as the negative comparator input
#1
CPP0SEL
Comparator0 Positive Input Selection\n
29
2
read-write
0
From P1.5
#00
1
From P1.0
#01
2
From P1.2
#10
3
From P1.3
#11
CMP1CR
CMP1CR
Comparator1 Control Register
0x4
read-write
n
0x0
0x0
CMP1EN
Comparator1 Enable\nComparator output needs to wait 10 us stable time after CMP1EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP1IE
Comparator1 Interrupt Enable\nInterrupt is generated if CMP1IE bit is set to 1 after CMP1 conversion finished.
1
1
read-write
0
CMP1 interrupt function Disabled
#0
1
CMP1 interrupt function Enabled
#1
CMP1_FALLING
Comparator1 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer.
9
1
read-write
0
Disable comparator1 trigger PWM/Timer on falling edge
#0
1
Enable comparator1 trigger PWM/Timer on falling edge
#1
CMP1_HYSEN
Comparator1 Hysteresis Enable\n
2
1
read-write
0
CMP0 Hysteresis function Disabled (Default)
#0
1
CMP0 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
#1
CMP1_RISING
Comparator1 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer.
8
1
read-write
0
Disable comparator1 trigger PWM/Timer on rising edge
#0
1
Enable comparator1 trigger PWM/Timer on rising edge
#1
CN1
Comparator1 Negative Input Selection\n
4
1
read-write
0
The comparator reference pin CPN0 is selected as the negative comparator input
#0
1
The internal comparator reference voltage (Vref=1.25V or from CRV setting value) is selected as the negative comparator input
#1
CPP1SEL
Comparator1 Positive Input Selection\n
29
2
read-write
0
From P3.1
#00
1
From P3.2
#01
2
From P3.4
#10
3
From P3.5
#11
CMPRVCR
CMPRVCR
Comparator Reference Voltage Control Register
0xC
read-write
n
0x0
0x0
CRVS
Comparator Reference Voltage Setting\n
0
4
read-write
OUT_SEL
CRV Module Output Selection\n
7
1
read-write
0
Band-gap 1.22 V voltage Selected
#0
1
CRVS setting voltage Selected
#1
CMPSR
CMPSR
Comparator Status Register
0x8
read-write
n
0x0
0x0
CMPF0
Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if CMP0IE set.\nSoftware can write 1 to clear this bit to zero.
0
1
read-write
CMPF1
Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if CMP1IE set.\nSoftware can write 1 to clear this bit to zero.
1
1
read-write
CO0
Comparator0 Output\n
2
1
read-write
CO1
Comparator1 Output\n
3
1
read-write
FMC
FMC Register Map
FMC
0x0
0x0
0x18
registers
n
DFBA
DFBA
Data Flash Start Address
0x14
-1
read-only
n
0x0
0x0
DFBA
Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
0
32
read-only
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address\nThe NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
FOEN_FCEN_FCTRL
ISP Command\n
0
6
read-write
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
BS
Boot Selection
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Enable Config-bits Update by ISP\n
4
1
read-write
0
Disable ISP can update config-bits
#0
1
Enable ISP can update config-bits
#1
ET
Flash Erase Time\n
12
3
read-write
ISPEN
ISP Enable\nISP function enable bit. Set this bit to enable ISP function.\n
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself.\n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination address is illegal, such as over an available range.\nSoftware can write 1 to clear this bit.
6
1
read-write
LDUEN
LDROM Update Enable\n
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when the MCU runs in APROM
#1
PT
Flash Program Time\n
8
3
read-write
SWRST
Software Reset\nWriting 1 to this bit to start software reset.\nIt is cleared by hardware after reset is finished.
7
1
read-write
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
0
32
read-write
ISPTRG
ISPTRG
ISP Trigger Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger
Write 1 to start ISP operation this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0
1
read-write
0
ISP operation finished
#0
1
ISP on going
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x18
0x10
registers
n
0x30
0x18
registers
n
0x80
0xC
registers
n
BODCR
BODCR
Brown-out Detector Control Register
0x18
read-write
n
0x0
0x0
BOD_INTF
Brown-out Detector Interrupt Flag\n
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the VDD is dropped through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_OUT
Brown-out Detector Output State\n
6
1
read-write
0
Brown-out Detector status output is 0, the detected voltage is higher than BOD_VL setting
#0
1
Brown-out Detector status output is 1, the detected voltage is lower than BOD_VL setting
#1
BOD_RSTEN
Brown-out Reset Enable (Initiated and Write-protected bit)\nWhen the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
3
1
read-write
0
Brown-out INTERRUPT function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold, then assert a signal to interrupt the Cortex-M0 CPU
#0
1
Brown-out RESET function Enabled when the Brown-out Detector function is enable and the detected voltage is lower than the threshold then assert a signal to reset the chip
#1
BOD_VL
Brown-out Detector Threshold Voltage Selection (Initiated Write-protected bit)
1
2
read-write
IPRSTC1
IPRSTC1
IP Reset Control Resister 1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One Shot Reset\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reload.\nThis bit is the protected bit, and programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\n
0
1
read-write
0
Normal
#0
1
Reset CHIP
#1
CPU_RST
CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nThis bit is the protected bit, programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\n
1
1
read-write
0
Normal
#0
1
Reset CPU
#1
IPRSTC2
IPRSTC2
IP Reset Control Resister 2
0xC
read-write
n
0x0
0x0
ACMP_RST
ACMP Controller Reset\n
22
1
read-write
0
ACMP block normal operation
#0
1
ACMP block reset
#1
ADC_RST
ADC Controller Reset\n
28
1
read-write
0
ADC block normal operation
#0
1
ADC block reset
#1
GPIO_RST
GPIO (P0~P5) Controller Reset\n
1
1
read-write
0
GPIO normal operation
#0
1
GPIO reset
#1
I2C_RST
I2C Controller Reset\n
8
1
read-write
0
I2C normal operation
#0
1
I2C block reset
#1
PWM_RST
PWM Controller Reset\n
20
1
read-write
0
PWM block normal operation
#0
1
PWM block reset
#1
SPI_RST
SPI Controller Reset\n
12
1
read-write
0
SPI block normal operation
#0
1
SPI block reset
#1
TMR0_RST
Timer0 Controller Reset\n
2
1
read-write
0
Timer0 normal operation
#0
1
Timer0 block reset
#1
TMR1_RST
Timer1 Controller Reset\n
3
1
read-write
0
Timer1 normal operation
#0
1
Timer1 block reset
#1
UART_RST
UART Controller Reset\n
16
1
read-write
0
UART normal operation
#0
1
UART block reset
#1
IRCTRIMCTL
IRCTRIMCTL
HIRC Trim Control Register
0x80
read-write
n
0x0
0x0
TRIM_LOOP
Trim Calculation Loop
This field defines trim value calculation based on the number of LXT clock.
For example, if TRIM_LOOP is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock.
This field also defines how many times the auto trim circuit will try to update the HFIRC trim value before the frequency of HFIRC is locked.
Once the HFIRC is locked, the internal trim value update counter will be reset.
If the trim value update counter reaches this limitation value and frequency of HFIRC is still not locked, the auto trim operation will be disabled and TRIM_SEL will be cleared to 0.
4
2
read-write
0
Trim value calculation is based on average difference in 4 LXT clock and trim retry count limitation is 64
#00
1
Trim value calculation is based on average difference in 8 LXT clock and trim retry count limitation is 128
#01
2
Trim value calculation is based on average difference in 16 LXT clock and trim retry count limitation is 256
#10
3
Trim value calculation is based on average difference in 32 LXT clock and trim retry count limitation is 512
#11
TRIM_SEL
Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1, the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
0
1
read-write
0
HFIRC auto trim function Disabled
#0
1
HFIRC auto trim function Enabled and HFIRC trimmed to 22.1184 MHz
#1
IRCTRIMIEN
IRCTRIMIEN
HIRC Trim Interrupt Enable Register
0x84
read-write
n
0x0
0x0
TRIM_FAIL_IEN
Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HFIRC trim value update limitation count is reached.\n
1
1
read-write
0
TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU
#0
1
TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU
#1
_32K_ERR_IEN
LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
2
1
read-write
0
32K_ERR_INT status Disabled to trigger an interrupt to CPU
#0
1
32K_ERR_INT status Enabled to trigger an interrupt to CPU
#1
IRCTRIMINT
IRCTRIMINT
HIRC Trim Interrupt Status Register
0x88
read-write
n
0x0
0x0
FREQ_LOCK
HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt.
0
1
read-write
TRIM_FAIL_INT
Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HFIRC trim value update limitation count was reached. Software can write 1 to clear this bit to zero.\n
1
1
read-write
0
Trim value update limitation count is not reached
#0
1
Trim value update limitation count is reached and HFIRC frequency is still not locked
#1
_32K_ERR_INT
LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to zero.\n
2
1
read-write
0
LXT clock frequency is accuracy
#0
1
LXT clock frequency is inaccuracy
#1
LDOBPCR
LDOBPCR
LDO Bypass Control Register
0x20
read-write
n
0x0
0x0
LDOCR
LDOCR
LDO Control Register
0x1C
read-write
n
0x0
0x0
P0_MFP
P0_MFP
P0 Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
P0_ALT0
P0.0 Alternate Function Selection\n
8
1
read-write
P0_ALT1
P0.1 Alternate Function Selection\n
9
1
read-write
P0_ALT4
P0.4 Alternate Function Selection\n
12
1
read-write
P0_ALT5
P0.5 Alternate Function Selection\n
13
1
read-write
P0_ALT6
P0.6 Alternate Function Selection\n
14
1
read-write
P0_ALT7
P0.7 Alternate Function Selection\n
15
1
read-write
P0_MFP
P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details.
0
8
read-write
P0_TYPE
P0[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P0[7:0] I/O input Schmitt Trigger function Disabled
0
1
P0[7:0] I/O input Schmitt Trigger function Enabled
1
P1_MFP
P1_MFP
P1 Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
P1_ALT0
P1.0 Alternate Function Selection\n
8
1
read-write
P1_ALT2
P1.2 Alternate Function Selection\n
10
1
read-write
P1_ALT3
P1.3 Alternate Function Selection\n
11
1
read-write
P1_ALT4
P1.4 Alternate Function Selection\n
12
1
read-write
P1_ALT5
P1.5 Alternate Function Selection\n
13
1
read-write
P1_MFP
P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details.
0
8
read-write
P1_TYPE
P1[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P1[7:0] I/O input Schmitt Trigger function Disabled
0
1
P1[7:0] I/O input Schmitt Trigger function Enabled
1
P2_MFP
P2_MFP
P2 Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
P2_ALT2
P2.2 Alternate Function Selection\n
10
1
read-write
P2_ALT3
P2.3 Alternate Function Selection\n
11
1
read-write
P2_ALT4
P2.4 Alternate Function Selection\n
12
1
read-write
P2_ALT5
P2.5 Alternate Function Selection\n
13
1
read-write
P2_ALT6
P2.6 Alternate Function Selection\n
14
1
read-write
P2_MFP
P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details.
0
8
read-write
P2_TYPE
P2[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P2[7:0] I/O input Schmitt Trigger function Disabled
0
1
P2[7:0] I/O input Schmitt Trigger function Enabled
1
P3_MFP
P3_MFP
P3 Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
P32CPP1
P3.2 Alternate Function Selection Extension\n
24
1
read-write
0
P3.2 is set by P3_ALT[2] and P3_MFP[2]
#0
1
P3.2 is set to CPP1 of ACMP1
#1
P3_ALT0
P3.0 Alternate Function Selection\n
8
1
read-write
P3_ALT1
P3.1 Alternate Function Selection\n
9
1
read-write
P3_ALT2
P3.2 Alternate Function Selection\n
10
1
read-write
P3_ALT4
P3.4 Alternate Function Selection\n
12
1
read-write
P3_ALT5
P3.5 Alternate Function Selection\n
13
1
read-write
P3_ALT6
P3.6 Alternate Function Selection\n
14
1
read-write
P3_MFP
P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details.
0
8
read-write
P3_TYPE
P3[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P3[7:0] I/O input Schmitt Trigger function Disabled
0
1
P3[7:0] I/O input Schmitt Trigger function Enabled
1
P4_MFP
P4_MFP
P4 Multiple Function and Input Type Control Register
0x40
-1
read-write
n
0x0
0x0
P4_ALT6
P4.6 Alternate Function Selection\n
14
1
read-write
P4_ALT7
P4.7 Alternate Function Selection\n
15
1
read-write
P4_MFP
P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details.
0
8
read-write
P4_TYPE
P4[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P4[7:0] I/O input Schmitt Trigger function Disabled
0
1
P4[7:0] I/O input Schmitt Trigger function Enabled
1
P5_MFP
P5_MFP
P5 Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
P5_ALT0
P5.0 Alternate Function Selection\n
8
1
read-write
P5_ALT1
P5.1 Alternate Function Selection\n
9
1
read-write
P5_ALT2
P5.2 Alternate Function Selection\n
10
1
read-write
P5_ALT3
P5.3 Alternate Function Selection\n
11
1
read-write
P5_ALT4
P5.4 Alternate Function Selection\n
12
1
read-write
P5_ALT5
P5.5 Alternate Function Selection\n
13
1
read-write
P5_MFP
P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details.
0
8
read-write
P5_TYPE
P5[7:0] Input Schmitt Trigger Function Enable\n
16
8
read-write
0
P5[7:0] I/O input Schmitt Trigger function Disabled
0
1
P5[7:0] I/O input Schmitt Trigger function Enabled
1
PDID
PDID
Part Device Identification Number Register
0x0
read-only
n
0x0
0x0
PDID
Product Device Identification Number
This register reflects the device part number code. Software can read this register to identify which device is used.
For example, the MINI51LBN PDID code is 0x10205100 .
0
32
read-only
PORCR
PORCR
Power-On-Reset Control Register
0x24
read-write
n
0x0
0x0
RegLockAddr
RegLockAddr
Register Lock Key Address Register
0x100
read-write
n
0x0
0x0
RegUnLock
The Protected registers are:\nIPRSTC1 - address 0x5000_0008 (IP reset control register 1)\nBODCR - address 0x5000_0018 (Brown-out detector control register)\nLDOCR - address 0x5000_001C (LDO control register)\nPORCR - address 0x5000_0024 (Power-On-Reset control register)\nPWRCON - address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)\nAPBCLK[0] - address 0x5000_0208 (Watchdog clock enable)\nCLKSEL0 - address 0x5000_0210 (HCLK and CPU STCLK clock source select)\nCLKSEL1[1:0] - address 0x5000_0214 (Watchdog clock source select)\nNMI_SEL[8] - address 0x5000_380 (NMI interrupt source enable)\nISPCON - address 0x5000_C000 (Flash ISP control register)\nWTCR - address 0x4000_4000 (Watchdog Timer control register)
0
1
read-write
0
Protected registers are locked. Any write to the target register is ignored
#0
1
Protected registers are Unlock
#1
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD flag is set by the reset signal from the Brown-out Detected module to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
4
1
read-write
0
No reset from BOD
#0
1
The Brown-out Detected module had issued the reset signal to reset the system
#1
RSTS_CPU
The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with 1 to reset the Cortex-M0 CPU kernel and Flash Memory Controller (FMC).\nSoftware can write 1 to clear this bit to zero.
7
1
read-write
0
No reset from CPU
#0
1
The Cortex-M0 CPU kernel and FMC are reset by setting CPU_RST to 1
#1
RSTS_MCU
The RSTS_MCU flag is set by the reset signal from the Cortex-M0 kernel to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ (AIRCR[2]), Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel
#1
RSTS_POR
The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) set, to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
0
1
read-write
0
No reset from POR
#0
1
The Power-On-Reset (POR) or CHIP_RST=1 had issued the reset signal to reset the system
#1
RSTS_RESET
The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
1
1
read-write
0
No reset from pin /RESET
#0
1
The pin /RESET had issued the reset signal to reset the system
#1
RSTS_WDT
The RSTS_WDT flag is set by the reset signal from the Watchdog module to indicate the previous reset source.
Software can write 1 to clear this bit to zero.
2
1
read-write
0
No reset from Watchdog
#0
1
The Watchdog module had issued the reset signal to reset the system
#1
GP
GP Register Map
GP
0x0
0x0
0x24
registers
n
0x100
0x24
registers
n
0x140
0x24
registers
n
0x180
0x4
registers
n
0x200
0x8
registers
n
0x210
0x14
registers
n
0x228
0x10
registers
n
0x248
0x14
registers
n
0x260
0xC
registers
n
0x270
0xC
registers
n
0x298
0x20
registers
n
0x40
0x24
registers
n
0x80
0x24
registers
n
0xC0
0x24
registers
n
DBNCECON
DBNCECON
Interrupt De-bounce Cycle Control
0x180
-1
read-write
n
0x0
0x0
DBCLKSEL
De-bounce Sampling Cycle Selection\n
0
4
read-write
DBCLKSRC
De-bounce Counter Clock Source Selection\n
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz clock
#1
ICLK_ON
Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled.\n
5
1
read-write
0
The clock Disabled if the P0/1/2/3/4[n] interrupt is disabled
#0
1
Interrupt generated circuit clock always Enabled
#1
P00_DOUT
P00_DOUT
P0.0 Data Output Value
0x200
-1
read-write
n
0x0
0x0
P_DOUT
P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n
0
1
read-write
0
The corresponding GPIO pin set to low.\nCorresponding GPIO pin status is low
#0
1
The corresponding GPIO pin set to high.\nCorresponding GPIO pin status is high
#1
P01_DOUT
P01_DOUT
P0.1 Data Output Value
0x204
read-write
n
0x0
0x0
P04_DOUT
P04_DOUT
P0.4 Data Output Value
0x210
read-write
n
0x0
0x0
P05_DOUT
P05_DOUT
P0.5 Data Output Value
0x214
read-write
n
0x0
0x0
P06_DOUT
P06_DOUT
P0.6 Data Output Value
0x218
read-write
n
0x0
0x0
P07_DOUT
P07_DOUT
P0.7 Data Output Value
0x21C
read-write
n
0x0
0x0
P0_DBEN
P0_DBEN
P0 De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN
Px Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and is ignored for level trigger interrupt.
0
1
read-write
0
The pin[n] de-bounce function disabled
#0
1
The pin[n] de-bounce function enabled
#1
P0_DMASK
P0_DMASK
P0 Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK
Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1, the corresponding DOUTn pin is protected. The write signal is masked, and writing data to the protect pin is ignored.\n
0
1
read-write
0
The corresponding Px_DOUT[n] bit can be updated
#0
1
The corresponding Px_DOUT[n] bit is protected
#1
P0_DOUT
P0_DOUT
P0 Data Output Value
0x8
-1
read-write
n
0x0
0x0
DOUT
Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
0
1
read-write
0
Px pin[n] will drive Low if the corresponding output mode enabling bit is set
#0
1
Px pin[n] will drive High if the corresponding output mode enabling bit is set
#1
P0_IEN
P0_IEN
P0 Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN
Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.
When the IF_EB[n] bit is set to 1:
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state changed from high-to-low will generate the interrupt.
0
1
read-write
0
The Px[n] state low-level or high-to-low change interrupt Disabled
#0
1
The Px[n] state low-level or high-to-low change interrupt Enabled
#1
IR_EN
Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.
When the IR_EN[n] bit is set to 1:
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state changed from low-to-high will generate the interrupt.
16
1
read-write
0
The Px[n] level-high or low-to-high interrupt Disabled
#0
1
The Px[n] level-high or low-to-high interrupt Enabled
#1
P0_IMD
P0_IMD
P0 Interrupt Mode Control
0x18
read-write
n
0x0
0x0
IMD
Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounced. If the interrupt is by level trigger, the input source is sampled by one clock and then generates the interrupt.\n
0
1
read-write
0
Edge trigger interrupt
#0
1
Level trigger interrupt
#1
P0_ISRC
P0_ISRC
P0 Interrupt Trigger Source Indicator
0x20
read-write
n
0x0
0x0
ISRC
Port 0-5 Interrupt Trigger Source Indicator\nRead :\n
0
1
read-write
0
No interrupt at Px[n].\nNo action
#0
1
Indicates Px[n] generate an interrupt.\nClear the corresponding pending interrupt
#1
P0_OFFD
P0_OFFD
P0 Pin OFF Digital Enable
0x4
read-write
n
0x0
0x0
OFFD
OFFD: Px Pin[n] OFF Digital Input Path Enable\n
16
8
read-write
0
I/O digital input path Enabled
0
1
I/O digital input path Disabled (digital input tied to low)
1
P0_PIN
P0_PIN
P0 Pin Value
0x10
read-only
n
0x0
0x0
PIN
Px Pin[n] Value\n
0
1
read-only
P0_PMD
P0_PMD
P0 Pin I/O Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Px Pin[n] I/O Mode Control\n
0
2
read-write
PMD1
Px Pin[n] I/O Mode Control\n
2
2
read-write
PMD2
Px Pin[n] I/O Mode Control\n
4
2
read-write
PMD3
Px Pin[n] I/O Mode Control\n
6
2
read-write
PMD4
Px Pin[n] I/O Mode Control\n
8
2
read-write
PMD5
Px Pin[n] I/O Mode Control\n
10
2
read-write
PMD6
Px Pin[n] I/O Mode Control\n
12
2
read-write
PMD7
Px Pin[n] I/O Mode Control\n
14
2
read-write
P10_DOUT
P10_DOUT
P1.0 Data Output Value
0x220
read-write
n
0x0
0x0
P12_DOUT
P12_DOUT
P1.2 Data Output Value
0x228
read-write
n
0x0
0x0
P13_DOUT
P13_DOUT
P1.3 Data Output Value
0x22C
read-write
n
0x0
0x0
P14_DOUT
P14_DOUT
P1.4 Data Output Value
0x230
read-write
n
0x0
0x0
P15_DOUT
P15_DOUT
P1.5 Data Output Value
0x234
read-write
n
0x0
0x0
P1_DBEN
P1_DBEN
P1 De-bounce Enable
0x54
read-write
n
0x0
0x0
P1_DMASK
P1_DMASK
P1 Data Output Write Mask
0x4C
read-write
n
0x0
0x0
P1_DOUT
P1_DOUT
P1 Data Output Value
0x48
read-write
n
0x0
0x0
P1_IEN
P1_IEN
P1 Interrupt Enable
0x5C
read-write
n
0x0
0x0
P1_IMD
P1_IMD
P1 Interrupt Mode Control
0x58
read-write
n
0x0
0x0
P1_ISRC
P1_ISRC
P1 Interrupt Trigger Source Indicator
0x60
read-write
n
0x0
0x0
P1_OFFD
P1_OFFD
P1 Pin OFF Digital Enable
0x44
read-write
n
0x0
0x0
P1_PIN
P1_PIN
P1 Pin Value
0x50
read-write
n
0x0
0x0
P1_PMD
P1_PMD
P1 Pin I/O Mode Control
0x40
read-write
n
0x0
0x0
P22_DOUT
P22_DOUT
P2.2 Data Output Value
0x248
read-write
n
0x0
0x0
P23_DOUT
P23_DOUT
P2.3 Data Output Value
0x24C
read-write
n
0x0
0x0
P24_DOUT
P24_DOUT
P2.4 Data Output Value
0x250
read-write
n
0x0
0x0
P25_DOUT
P25_DOUT
P2.5 Data Output Value
0x254
read-write
n
0x0
0x0
P26_DOUT
P26_DOUT
P2.6 Data Output Value
0x258
read-write
n
0x0
0x0
P2_DBEN
P2_DBEN
P2 De-bounce Enable
0x94
read-write
n
0x0
0x0
P2_DMASK
P2_DMASK
P2 Data Output Write Mask
0x8C
read-write
n
0x0
0x0
P2_DOUT
P2_DOUT
P2 Data Output Value
0x88
read-write
n
0x0
0x0
P2_IEN
P2_IEN
P2 Interrupt Enable
0x9C
read-write
n
0x0
0x0
P2_IMD
P2_IMD
P2 Interrupt Mode Control
0x98
read-write
n
0x0
0x0
P2_ISRC
P2_ISRC
P2 Interrupt Trigger Source Indicator
0xA0
read-write
n
0x0
0x0
P2_OFFD
P2_OFFD
P2 Pin OFF Digital Enable
0x84
read-write
n
0x0
0x0
P2_PIN
P2_PIN
P2 Pin Value
0x90
read-write
n
0x0
0x0
P2_PMD
P2_PMD
P2 Pin I/O Mode Control
0x80
read-write
n
0x0
0x0
P30_DOUT
P30_DOUT
P3.0 Data Output Value
0x260
read-write
n
0x0
0x0
P31_DOUT
P31_DOUT
P3.1 Data Output Value
0x264
read-write
n
0x0
0x0
P32_DOUT
P32_DOUT
P3.2 Data Output Value
0x268
read-write
n
0x0
0x0
P34_DOUT
P34_DOUT
P3.4 Data Output Value
0x270
read-write
n
0x0
0x0
P35_DOUT
P35_DOUT
P3.5 Data Output Value
0x274
read-write
n
0x0
0x0
P36_DOUT
P36_DOUT
P3.6 Data Output Value
0x278
read-write
n
0x0
0x0
P3_DBEN
P3_DBEN
P3 De-bounce Enable
0xD4
read-write
n
0x0
0x0
P3_DMASK
P3_DMASK
P3 Data Output Write Mask
0xCC
read-write
n
0x0
0x0
P3_DOUT
P3_DOUT
P3 Data Output Value
0xC8
read-write
n
0x0
0x0
P3_IEN
P3_IEN
P3 Interrupt Enable
0xDC
read-write
n
0x0
0x0
P3_IMD
P3_IMD
P3 Interrupt Mode Control
0xD8
read-write
n
0x0
0x0
P3_ISRC
P3_ISRC
P3 Interrupt Trigger Source Indicator
0xE0
read-write
n
0x0
0x0
P3_OFFD
P3_OFFD
P3 Pin OFF Digital Enable
0xC4
read-write
n
0x0
0x0
P3_PIN
P3_PIN
P3 Pin Value
0xD0
read-write
n
0x0
0x0
P3_PMD
P3_PMD
P3 Pin I/O Mode Control
0xC0
read-write
n
0x0
0x0
P46_DOUT
P46_DOUT
P4.6 Data Output Value
0x298
read-write
n
0x0
0x0
P47_DOUT
P47_DOUT
P4.7 Data Output Value
0x29C
read-write
n
0x0
0x0
P4_DBEN
P4_DBEN
P4 De-bounce Enable
0x114
read-write
n
0x0
0x0
P4_DMASK
P4_DMASK
P4 Data Output Write Mask
0x10C
read-write
n
0x0
0x0
P4_DOUT
P4_DOUT
P4 Data Output Value
0x108
read-write
n
0x0
0x0
P4_IEN
P4_IEN
P4 Interrupt Enable
0x11C
read-write
n
0x0
0x0
P4_IMD
P4_IMD
P4 Interrupt Mode Control
0x118
read-write
n
0x0
0x0
P4_ISRC
P4_ISRC
P4 Interrupt Trigger Source Indicator
0x120
read-write
n
0x0
0x0
P4_OFFD
P4_OFFD
P4 Pin OFF Digital Enable
0x104
read-write
n
0x0
0x0
P4_PIN
P4_PIN
P4 Pin Value
0x110
read-write
n
0x0
0x0
P4_PMD
P4_PMD
P4 Pin I/O Mode Control
0x100
read-write
n
0x0
0x0
P50_DOUT
P50_DOUT
P5.0 Data Output Value
0x2A0
read-write
n
0x0
0x0
P51_DOUT
P51_DOUT
P5.1 Data Output Value
0x2A4
read-write
n
0x0
0x0
P52_DOUT
P52_DOUT
P5.2 Data Output Value
0x2A8
read-write
n
0x0
0x0
P53_DOUT
P53_DOUT
P5.3 Data Output Value
0x2AC
read-write
n
0x0
0x0
P54_DOUT
P54_DOUT
P5.4 Data Output Value
0x2B0
read-write
n
0x0
0x0
P55_DOUT
P55_DOUT
P5.5 Data Output Value
0x2B4
read-write
n
0x0
0x0
P5_DBEN
P5_DBEN
P5 De-bounce Enable
0x154
read-write
n
0x0
0x0
P5_DMASK
P5_DMASK
P5 Data Output Write Mask
0x14C
read-write
n
0x0
0x0
P5_DOUT
P5_DOUT
P5 Data Output Value
0x148
read-write
n
0x0
0x0
P5_IEN
P5_IEN
P5 Interrupt Enable
0x15C
read-write
n
0x0
0x0
P5_IMD
P5_IMD
P5 Interrupt Mode Control
0x158
read-write
n
0x0
0x0
P5_ISRC
P5_ISRC
P5 Interrupt Trigger Source Indicator
0x160
read-write
n
0x0
0x0
P5_OFFD
P5_OFFD
P5 Pin OFF Digital Enable
0x144
read-write
n
0x0
0x0
P5_PIN
P5_PIN
P5 Pin Value
0x150
read-write
n
0x0
0x0
P5_PMD
P5_PMD
P5 Pin I/O Mode Control
0x140
read-write
n
0x0
0x0
I2C
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register 0
I2CADRR0
0x4
read-write
n
0x0
0x0
GC
General Call Function\n
0
1
read-write
0
Disable General Call Function
#0
1
Enable General Call Function
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
1
7
read-write
I2CADDR1
I2CADDR1
I2C Slave Address Register 1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
I2C Slave Address Register 2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
I2C Slave Address Register 3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register 0
0x24
read-write
n
0x0
0x0
I2CADMx
I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to 1, the received corresponding address bit is don't-care. If the bit is set to 0, the received corresponding register bit should be exactly the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exactly the same as address register)
0
1
Mask Enabled (the received corresponding address bit is don't care)
1
I2CADM1
I2CADM1
I2C Slave Address Mask Register 1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
I2C Slave Address Mask Register 2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
I2C Slave Address Mask Register 3
0x30
read-write
n
0x0
0x0
I2CADRR0
I2CADRR0
I2C Slave Address Register 0
0x4
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C DATA Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C Clock Divided Register\n
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit\n
2
1
read-write
EI
Enable Interrupt\n
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENSI
I2C Controller Enable Bit\n
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 will enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit
In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CON2
I2CON2
I2C Control Register 2
0x3C
read-write
n
0x0
0x0
NOSTRETCH
NO STRETCH the I2C BUS\n
2
1
read-write
0
The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode
#0
1
The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode
#1
OVER_INTEN
I2C OVER RUN Interrupt Control Bit
Setting OVER_INTEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received fifo.
3
1
read-write
TWOFF_EN
TWO LEVEL FIFO Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
UNDER_INTEN
I2C UNDER RUN Interrupt Control Bit\nSetting UNDER_INTEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted fifo.
4
1
read-write
WAKEUPEN
Wake-Up Enable\nThe system can be wake up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C controller:\n
0
8
read-only
I2CSTATUS2
I2CSTATUS2
I2C Status Register 2
0x40
read-write
n
0x0
0x0
EMPTY
TWO LEVEL FIFO EMPTY\nThis bit is set when RX_POINTER is equal to 0.
2
1
read-write
FULL
TWO LEVEL FIFO FULL\nThis bit is set when TX_POINTER is equal to 2
1
1
read-write
OVERUN
I2C OVER RUN Status Bit
3
1
read-write
UNDERUN
I2C UNDER RUN Status Bit
4
1
read-write
WAKEUP
Wake Up\nThis bit indicates the wake-up function is done.
0
1
read-write
I2CTOC
I2CTOC
I2C Time-out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is prolong 4 times.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
ENTI
Time-out Counter Enabled\nWhen enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TIF
Time-out Flag\n
0
1
read-write
0
Software can clear the flag by writing 1 to this flag when TIF is set
#0
1
Time-out flag is set by hardware. It can interrupt CPU
#1
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (Brown-out) Interrupt Source Identity
0x0
read-only
n
0x0
0x0
INT_SRC
Interrupt Source\nDefine the interrupt sources for interrupt event.
0
3
read-only
IRQ10_SRC
IRQ10_SRC
Reserved
0x28
read-write
n
0x0
0x0
IRQ11_SRC
IRQ11_SRC
Reserved
0x2C
read-write
n
0x0
0x0
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART) Interrupt Source Identity
0x30
read-write
n
0x0
0x0
IRQ13_SRC
IRQ13_SRC
Reserved
0x34
read-write
n
0x0
0x0
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI) Interrupt Source Identity
0x38
read-write
n
0x0
0x0
IRQ15_SRC
IRQ15_SRC
Reserved
0x3C
read-write
n
0x0
0x0
IRQ16_SRC
IRQ16_SRC
IRQ16 (GP5) Interrupt Source Identity
0x40
read-write
n
0x0
0x0
IRQ17_SRC
IRQ17_SRC
IRQ17 (HFIRC Trim) Interrupt Source Identity
0x44
read-write
n
0x0
0x0
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C) Interrupt Source Identity
0x48
read-write
n
0x0
0x0
IRQ19_SRC
IRQ19_SRC
Reserved
0x4C
read-write
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) Interrupt Source Identity
0x4
read-write
n
0x0
0x0
IRQ20_SRC
IRQ20_SRC
Reserved
0x50
read-write
n
0x0
0x0
IRQ21_SRC
IRQ21_SRC
Reserved
0x54
read-write
n
0x0
0x0
IRQ22_SRC
IRQ22_SRC
Reserved
0x58
read-write
n
0x0
0x0
IRQ23_SRC
IRQ23_SRC
Reserved
0x5C
read-write
n
0x0
0x0
IRQ24_SRC
IRQ24_SRC
Reserved
0x60
read-write
n
0x0
0x0
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) Interrupt Source Identity
0x64
read-write
n
0x0
0x0
IRQ26_SRC
IRQ26_SRC
Reserved
0x68
read-write
n
0x0
0x0
IRQ27_SRC
IRQ27_SRC
Reserved
0x6C
read-write
n
0x0
0x0
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) Interrupt Source Identity
0x70
read-write
n
0x0
0x0
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC) Interrupt Source Identity
0x74
read-write
n
0x0
0x0
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) Interrupt Source Identity
0x8
read-write
n
0x0
0x0
IRQ30_SRC
IRQ30_SRC
Reserved
0x78
read-write
n
0x0
0x0
IRQ31_SRC
IRQ31_SRC
Reserved
0x7C
read-write
n
0x0
0x0
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) Interrupt Source Identity
0xC
read-write
n
0x0
0x0
IRQ4_SRC
IRQ4_SRC
IRQ4 (GP0/1) Interrupt Source Identity
0x10
read-write
n
0x0
0x0
IRQ5_SRC
IRQ5_SRC
IRQ5 (GP2/3/4) Interrupt Source Identity
0x14
read-write
n
0x0
0x0
IRQ6_SRC
IRQ6_SRC
IRQ6 (PWM) Interrupt Source Identity
0x18
read-write
n
0x0
0x0
IRQ7_SRC
IRQ7_SRC
IRQ7 (BRAKE) Interrupt Source Identity
0x1C
read-write
n
0x0
0x0
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) Interrupt Source Identity
0x20
read-write
n
0x0
0x0
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) Interrupt Source Identity
0x24
read-write
n
0x0
0x0
MCU_IRQ
MCU_IRQ
MCU IRQ Number Identity Register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, setting MCU_IRQ[n] to 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_bit[n] will clear the interrupt and setting MCU_IRQ[n] 0 has no effect.
0
32
read-write
NMI_CON
NMI_CON
NMI Source Interrupt Select Control Register
0x80
read-write
n
0x0
0x0
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 CPU can be selected from one of the interrupt[31:0].\nThe NMI_SEL[4:0] is used to select the NMI interrupt source.
0
5
read-write
NMI_SEL_EN
NMI Interrupt Source Enable (Write-protected)\nSetting this bit will enable NMI_SEL to generate NMI interrupt source of Cortex-M0.
8
1
read-write
PWM
PWM Register Map
PWM
0x0
0x0
0x3C
registers
n
0x54
0x34
registers
n
CMR0
CMR0
PWM Comparator Register 0
0x24
read-write
n
0x0
0x0
CMRn
PWM Comparator Register\nCMR determines the PWM duty.\nEdge-aligned mode:\nNote: Any write to CMRn will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
PWM Comparator Register 1
0x28
read-write
n
0x0
0x0
CMR2
CMR2
PWM Comparator Register 2
0x2C
read-write
n
0x0
0x0
CMR3
CMR3
PWM Comparator Register 3
0x30
read-write
n
0x0
0x0
CMR4
CMR4
PWM Comparator Register 4
0x34
read-write
n
0x0
0x0
CMR5
CMR5
PWM Comparator Register 5
0x38
read-write
n
0x0
0x0
CNR0
CNR0
PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRn
PWM Counter/Timer Loaded Value\nCNRn determines the PWM period.\nEdge-aligned mode:\nNote: Any write to CNRn will take effect in next PWM cycle.
0
16
read-write
CNR1
CNR1
PWM Counter Register 1
0x10
read-write
n
0x0
0x0
CNR2
CNR2
PWM Counter Register 2
0x14
read-write
n
0x0
0x0
CNR3
CNR3
PWM Counter Register 3
0x18
read-write
n
0x0
0x0
CNR4
CNR4
PWM Counter Register 4
0x1C
read-write
n
0x0
0x0
CNR5
CNR5
PWM Counter Register 5
0x20
read-write
n
0x0
0x0
CSR
CSR
PWM Clock Select Register
0x4
read-write
n
0x0
0x0
CSR0
Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
0
3
read-write
CSR1
Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
4
3
read-write
CSR2
Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
8
3
read-write
CSR3
Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
12
3
read-write
CSR4
Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
16
3
read-write
CSR5
Timer 5 Clock Source Selection\n
20
3
read-write
INTACCUCTL
INTACCUCTL
Period Interrupt Accumulation Control Register
0x84
-1
read-write
n
0x0
0x0
INTACCUEN0
Enable Interrupt Accumulation Function\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PERIODCNT
Interrupt Accumulation Register\nWhen INTACCUEN0 is set, PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero, the PWM0 interrupt will occurred and PERIODCNT will reload itself.
4
4
read-write
PCR
PCR
PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable/Disable Start Run\n
0
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH0INV
PWM-Timer 0 Output Inverter ON/OFF\n
2
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1EN
PWM-Timer 1 Enable/Disable Start Run\n
4
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH1INV
PWM-Timer 1 Output Inverter ON/OFF\nNote: Only even channels (PWM0, PWM2 and PWM4) can be set as inverter bit in independent mode.
6
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 cleared.
7
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH2EN
PWM-Timer 2 Enable/Disable Start Run\n
8
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH2INV
PWM-Timer 2 Output Inverter ON/OFF\n
10
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH2MOD
PWM-Timer 2 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH3EN
PWM-Timer 3 Enable/Disable Start Run\n
12
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH3INV
PWM-Timer 3 Output Inverter ON/OFF\nNote: Only even channels (PWM0, PWM2 and PWM4) can be set as inverter bit in independent mode.
14
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH3MOD
PWM-Timer 3 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 cleared.
15
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH4EN
PWM-Timer 4 Enable/Disable Start Run\n
16
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH4INV
PWM-Timer 4 Output Inverter ON/OFF\n
18
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH4MOD
PWM-Timer 4 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR4 and CMR4 cleared.
19
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH5EN
PWM-Timer 5 Enable/Disable Start Run\n
20
1
read-write
0
Corresponding PWM-timer running Stopped
#0
1
Corresponding PWM-timer start run Enabled
#1
CH5INV
PWM-Timer 5 Output Inverter ON/OFF\nNote: Only even channels (PWM0, PWM2 and PWM4) can be set as inverter bit in independent mode.
22
1
read-write
0
Inverter OFF
#0
1
Inverter ON
#1
CH5MOD
PWM-Timer 5 Auto-reload/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR5 and CMR5 cleared.
23
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CLRPWM
Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
27
1
read-write
0
Do not clear PWM counter
#0
1
16-bit PWM counter cleared to 0x000
#1
DB_MODE
PWM Debug Mode Configuration Bit (Available in DEBUG mode only)\n
1
1
read-write
0
Safe mode: The timer is frozen and PWM outputs are shut down Safe state for the inverter. The timer can still be re-started from where it stops
#0
1
Normal mode: The timer continues to operate normally May be dangerous in some cases since a constant duty cycle is applied to the inverter (no more interrupts serviced)
#1
DZEN01
Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN23
Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
DZEN45
Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 pair for PWM group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
GRP
Group bit\n
30
1
read-write
0
The signals timing of PWM0, PWM2 and PWM4 are independent
#0
1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
#1
PWMMOD
PWM Operating Mode Selection\n
28
2
read-write
PWMTYPE
PWM Aligned Type Selection Bit\n
31
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDZIR
PDZIR
PWM Dead-zone Interval Register
0x64
read-write
n
0x0
0x0
DZI01
Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
0
8
read-write
DZI23
Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
8
8
read-write
DZI45
Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 pair).\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
16
8
read-write
PFBCON
PFBCON
PWM Fault Brake Control Register
0x60
read-write
n
0x0
0x0
BKEN0
Enable BKP0 Pin Trigger Fault Brake Function 0\n
0
1
read-write
0
Disabling BKP0 pin can trigger brake function 0 (EINT0)
#0
1
Enabling a falling at BKP0 pin can trigger brake function 0
#1
BKEN1
Enable BKP1 Pin Trigger Fault Brake Function 1\n
1
1
read-write
0
Disabling BKP1 pin can trigger brake function 1 (EINT1 or CPO0)
#0
1
Enabling a falling at BKP1 pin can trigger brake function 1
#1
BKF
PWM Fault Brake Event Flag (write 1 clear)\nSoftware can write 1 to clear this bit
7
1
read-write
0
PWM output initial state when fault brake conditions asserted
#0
1
PWM output fault brake state when fault brake conditions asserted
#1
CPO0BKEN
BKP1 Fault Brake Function Source Selection\n
2
1
read-write
0
EINT1 as one brake source in BKP1
#0
1
CPO0 as one brake source in BKP1
#1
D6BKO6
D6 Brake Output Select Register\n
30
1
read-write
0
D6 output low when fault brake conditions asserted
#0
1
D6 output high when fault brake conditions asserted
#1
D7BKO7
D7 Brake Output Select Register\n
31
1
read-write
0
D7 output low when fault brake conditions asserted
#0
1
D7 output high when fault brake conditions asserted
#1
PWMBKO0
PWM Channel 0 Brake Output Select Register\n
24
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO1
PWM Channel 1 Brake Output Select Register\n
25
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO2
PWM Channel 2 Brake Output Select Register\n
26
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO3
PWM Channel 3 Brake Output Select Register\n
27
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO4
PWM Channel 4 Brake Output Select Register\n
28
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PWMBKO5
PWM Channel 5 Brake Output Select Register\n
29
1
read-write
0
PWM output low when fault brake conditions asserted
#0
1
PWM output high when fault brake conditions asserted
#1
PHCHG
PHCHG
Phase Changed Register
0x78
read-write
n
0x0
0x0
ACCNT0
Hardware auto clear CE0 when ACMP0 trigger it.\n
14
1
read-write
0
Enabled
#0
1
Disabled
#1
ACCNT1
Hardware auto clear CE1 when ACMP1 trigger it.\n
15
1
read-write
0
Enabled
#0
1
Disabled
#1
CE0
Enable ACPM0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
31
1
read-write
0
Disabled
#0
1
Enabled
#1
CE1
Enable ACPM1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
23
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF0
Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF1
Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: only for PWM0,PWM1,PWM2,PWM3.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF0
Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF1
Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF0
Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application
Note: Only for PWM0, PWM1, PWM2, PWM3.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF1
Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF0
Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF1
Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0SEL
CMP0SEL\nSelect the input source of ACMP0.\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
CMP1SEL
CMP1SEL\nSelect the input source of ACMP1.\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
D0
D0: when PWM0 is zero, channel 0's output waveform is D0.\n
0
1
read-write
0
Output low
#0
1
Output high
#1
D1
D1: when PWM1 is zero, channel 1's output waveform is D1.\n
1
1
read-write
0
Output low
#0
1
Output high
#1
D2
D2: when PWM2 is zero, channel 2's output waveform is D2.\n
2
1
read-write
0
Output low
#0
1
Output high
#1
D3
D3: when PWM3 is zero, channel 3's output waveform is D3.\n
3
1
read-write
0
Output low
#0
1
Output high
#1
D4
D4: when PWM4 is zero, channel 4's output waveform is D4.\n
4
1
read-write
0
Output low
#0
1
Output high
#1
D5
D5: when PWM5 is zero, channel 5's output waveform is D5.\n
5
1
read-write
0
Output low
#0
1
Output high
#1
D6
D6: when MASK6 is 1, channel 6's output waveform is D6.\n
6
1
read-write
0
Output low
#0
1
Output high
#1
D7
D7: when MASK1 is 1, channel 7's output waveform is D7.\n
7
1
read-write
0
Output low
#0
1
Output high
#1
PWM0
PWM channel 0 output enable control.\n
8
1
read-write
0
Output the original channel 0 waveform
#0
1
Output D0 specified in bit 0 of PHCHG register
#1
PWM1
PWM channel 1 output enable control.\n
9
1
read-write
0
Output the original channel 1 waveform
#0
1
Output D1 specified in bit 1 of PHCHG register
#1
PWM2
PWM channel 2 output enable control.\n
10
1
read-write
0
Output the original channel 2 waveform
#0
1
Output D2 specified in bit 2 of PHCHG register
#1
PWM3
PWM channel 3 output enable control.\n
11
1
read-write
0
Output the original channel 3 waveform
#0
1
Output D3 specified in bit 3 of PHCHG register
#1
PWM4
PWM channel 4 output enable control.\n
12
1
read-write
0
Output the original channel 4 waveform
#0
1
Output D4 specified in bit 4 of PHCHG register
#1
PWM5
PWM channel 5 output enable control.\n
13
1
read-write
0
Output the original channel 5 waveform
#0
1
Output D5 specified in bit 5 of PHCHG register
#1
T0
Enable Timer0 trigger PWM function\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
30
1
read-write
0
Disabled
#0
1
Enabled
#1
T1
Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
22
1
read-write
0
Disabled
#0
1
Enabled
#1
PHCHGMASK
PHCHGMASK
Phase Change MASK Register
0x80
read-write
n
0x0
0x0
CMPMASK0
MASK for ACMP0
8
1
read-write
0
The input of ACMP is controlled by CMP0CR
#0
1
The input of ACMP is controlled by CMP0SEL of PHCHG register
#1
CMPMASK1
MASK for ACMP1\n
9
1
read-write
0
The input of ACMP is controlled by CMP1CR
#0
1
The input of ACMP is controlled by CMP1SEL of PHCHG register
#1
MASK6
MASK for D6
6
1
read-write
0
Original GPIO P0.1
#0
1
D6
#1
MASK7
MASK for D7
7
1
read-write
0
Original GPIO P0.0
#0
1
D7
#1
PHCHGNXT
PHCHGNXT
Next Phase Change Register
0x7C
read-write
n
0x0
0x0
ACCNT0
Hardware auto clear CE0 when ACMP0 trigger it.\n
14
1
read-write
0
Enabled
#0
1
Disabled
#1
ACCNT1
Hardware auto clear CE1 when ACMP1 trigger it.\n
15
1
read-write
0
Enabled
#0
1
Disabled
#1
CE0
Enable ACPM0 Trigger Function\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
31
1
read-write
0
Disabled
#0
1
Enabled
#1
CE1
Enable ACPM1 Trigger Function\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
23
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF0
Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CH01TOFF1
Setting this bit will Force PWM0 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: only for PWM0,PWM1,PWM2,PWM3.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF0
Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
CH11TOFF1
Setting this bit will Force PWM1 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF0
Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application
Note: Only for PWM0, PWM1, PWM2, PWM3.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CH21TOFF1
Setting this bit will Force PWM2 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF0
Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP0 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
CH31TOFF1
Setting this bit will Force PWM3 to output low lasting for at most one period cycle as long as ACMP1 trigger it this feature is usually in step motor application.
Note: Only for PWM0, PWM1, PWM2, PWM3.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
CMP0SEL
CMP0SEL\nSelect the input source of ACMP0.\n
28
2
read-write
0
Select P1.5 as the input of ACMP0
#00
1
Select P1.0 as the input of ACMP0
#01
2
Select P1.2 as the input of ACMP0
#10
3
Select P1.3 as the input of ACMP0
#11
CMP1SEL
CMP1SEL\nSelect the input source of ACMP1.\n
20
2
read-write
0
Select P3.1 as the input of ACMP1
#00
1
Select P3.2 as the input of ACMP1
#01
2
Select P3.3 as the input of ACMP1
#10
3
Select P3.4 as the input of ACMP1
#11
D0
D0: when PWM0 is zero, channel 0's output waveform is D0.\n
0
1
read-write
0
Output low
#0
1
Output high
#1
D1
D1: when PWM1 is zero, channel 1's output waveform is D1.\n
1
1
read-write
0
Output low
#0
1
Output high
#1
D2
D2: when PWM2 is zero, channel 2's output waveform is D2.\n
2
1
read-write
0
Output low
#0
1
Output high
#1
D3
D3: when PWM3 is zero, channel 3's output waveform is D3.\n
3
1
read-write
0
Output low
#0
1
Output high
#1
D4
D4: when PWM4 is zero, channel 4's output waveform is D4.\n
4
1
read-write
0
Output low
#0
1
Output high
#1
D5
D5: when PWM5 is zero, channel 5's output waveform is D5.\n
5
1
read-write
0
Output low
#0
1
Output high
#1
D6
D6: when MASK6 is 1, channel 6's output waveform is D6.\n
6
1
read-write
0
Output low
#0
1
Output high
#1
D7
D7: when MASK1 is 1, channel 7's output waveform is D7.\n
7
1
read-write
0
Output low
#0
1
Output high
#1
PWM0
PWM channel 0 output enable control.\n
8
1
read-write
0
Output the original channel 0 waveform
#0
1
Output D0 specified in bit 0 of PHCHG register
#1
PWM1
PWM channel 1 output enable control.\n
9
1
read-write
0
Output the original channel 1 waveform
#0
1
Output D1 specified in bit 1 of PHCHG register
#1
PWM2
PWM channel 2 output enable control.\n
10
1
read-write
0
Output the original channel 2 waveform
#0
1
Output D2 specified in bit 2 of PHCHG register
#1
PWM3
PWM channel 3 output enable control.\n
11
1
read-write
0
Output the original channel 3 waveform
#0
1
Output D3 specified in bit 3 of PHCHG register
#1
PWM4
PWM channel 4 output enable control.\n
12
1
read-write
0
Output the original channel 4 waveform
#0
1
Output D4 specified in bit 4 of PHCHG register
#1
PWM5
PWM channel 5 output enable control.\n
13
1
read-write
0
Output the original channel 5 waveform
#0
1
Output D5 specified in bit 5 of PHCHG register
#1
T0
Enable Timer0 trigger PWM function\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
30
1
read-write
0
Disabled
#0
1
Enabled
#1
T1
Enable Timer1 Trigger PWM Function\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
22
1
read-write
0
Disabled
#0
1
Enabled
#1
PIER
PIER
PWM Interrupt Enable Register
0x54
read-write
n
0x0
0x0
BRKIE
Enable Fault Brake0 and 1 Interrupt\n
16
1
read-write
0
Disabling flags BKF0 and BKF1 to trigger PWM interrupt
#0
1
Enabling flags BKF0 and BKF1 can trigger PWM interrupt
#1
INT_TYPE
PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only.
17
1
read-write
0
PWMPIFn will be set if PWM counter underflows
#0
1
PWMPIFn will be set if PWM counter matches CNRn register
#1
PWMDIE0
PWM Channel 0 Duty Interrupt Enable\n
8
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE1
PWM Channel 1 Duty Interrupt Enable\n
9
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE2
PWM Channel 2 Duty Interrupt Enable\n
10
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE3
PWM Channel 3 Duty Interrupt Enable\n
11
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE4
PWM Channel 4 Duty Interrupt Enable\n
12
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMDIE5
PWM Channel 5 Duty Interrupt Enable\n
13
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE0
PWM Channel 0 Period Interrupt Enable\n
0
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE1
PWM Channel 1 Period Interrupt Enable\n
1
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE2
PWM Channel 2 Period Interrupt Enable\n
2
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE3
PWM Channel 3 Period Interrupt Enable\n
3
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE4
PWM Channel 4 Period Interrupt Enable\n
4
1
read-write
0
Disabled
#0
1
Enabled
#1
PWMPIE5
PWM Channel 5 Period Interrupt Enable\n
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PIIR
PIIR
PWM Interrupt Indication Register
0x58
read-write
n
0x0
0x0
BKF0
PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
16
1
read-write
0
PWM Brake does not recognize a falling signal at BKP0
#0
1
When PWM Brake detects a falling signal at pin BKP0, this flag will be set to high
#1
BKF1
PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
17
1
read-write
0
PWM Brake does not recognize a falling signal at BKP1
#0
1
When PWM Brake detects a falling signal at pin BKP1, this flag will be set to high
#1
PWMDIF0
PWM channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0. Software can write 1 to clear this bit.
8
1
read-write
PWMDIF1
PWM channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1. Software can write 1 to clear this bit.
9
1
read-write
PWMDIF2
PWM channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2. Software can write 1 to clear this bit.
10
1
read-write
PWMDIF3
PWM channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3. Software can write 1 to clear this bit.
11
1
read-write
PWMDIF4
PWM channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4. Software can write 1 to clear this bit.
12
1
read-write
PWMDIF5
PWM channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5. Software can write 1 to clear this bit.
13
1
read-write
PWMPIF0
PWM channel 0 Period Interrupt Flag\nFlag is set by hardware when CNR0 down counter reaches zero. Software can write 1 to clear this bit.
0
1
read-write
PWMPIF1
PWM channel 1 Period Interrupt Flag\nFlag is set by hardware when CNR1 down counter reaches zero. Software can write 1 to clear this bit.
1
1
read-write
PWMPIF2
PWM channel 2 Period Interrupt Flag\nFlag is set by hardware when CNR2 down counter reaches zero. Software can write 1 to clear this bit.
2
1
read-write
PWMPIF3
PWM channel 3 Period Interrupt Flag\nFlag is set by hardware when CNR3 down counter reaches zero. Software can write 1 to clear this bit.
3
1
read-write
PWMPIF4
PWM channel 4 Period Interrupt Flag\nFlag is set by hardware when CNR4 down counter reaches zero. Software can write 1 to clear this bit.
4
1
read-write
PWMPIF5
PWM channel 5 Period Interrupt Flag\nFlag is set by hardware when CNR5 down counter reaches zero. Software can write 1 to clear this bit.
5
1
read-write
PPR
PPR
PWM Pre-scale Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler 0 (PWM Counter 0 1 for group)
Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.
0
8
read-write
CP23
Clock Prescaler 2 (PWM Counter 2 3 for group)
Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.
8
8
read-write
CP45
Clock Prescaler 4 (PWM Counter 4 5 for group)
Clock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.
16
8
read-write
PWMPOE
PWMPOE
PWM Output Enable for Channel 0~5
0x5C
read-write
n
0x0
0x0
PWM0
PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
0
1
read-write
0
PWM channel 0 output to pin Disabled
#0
1
PWM channel 0 output to pin Enabled
#1
PWM1
PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
1
1
read-write
0
PWM channel 1 output to pin Disabled
#0
1
PWM channel 1 output to pin Enabled
#1
PWM2
PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
2
1
read-write
0
PWM channel 2 output to pin Disabled
#0
1
PWM channel 2 output to pin Enabled
#1
PWM3
PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
3
1
read-write
0
PWM channel 3 output to pin Disabled
#0
1
PWM channel 3 output to pin Enabled
#1
PWM4
PWM Channel 4 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
4
1
read-write
0
PWM channel 4 output to pin Disabled
#0
1
PWM channel 4 output to pin Enabled
#1
PWM5
PWM Channel 5 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function.
5
1
read-write
0
PWM channel 5 output to pin Disabled
#0
1
PWM channel 5 output to pin Enabled
#1
TRGCON0
TRGCON0
PWM Trigger Control Register 0
0x68
read-write
n
0x0
0x0
CM0TRGFEN
Enable PWM trigger ADC function while Channel0's counter matching CMR0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CM0TRGREN
Enable PWM trigger ADC function while Channel0's counter matching CMR0 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CM1TRGFEN
Enable PWM trigger ADC function while Channel1's counter matching CMR1 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CM1TRGREN
Enable PWM trigger ADC function while Channel1's counter matching CMR1 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CM2TRGFEN
Enable PWM trigger ADC function while Channel2's counter matching CMR2 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
18
1
read-write
0
Disabled
#0
1
Enabled
#1
CM2TRGREN
Enable PWM trigger ADC function while Channel2's counter matching CMR2 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
16
1
read-write
0
Disabled
#0
1
Enabled
#1
CM3TRGFEN
Enable PWM trigger ADC function while Channel3's counter matching CMR3 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
26
1
read-write
0
Disabled
#0
1
Enabled
#1
CM3TRGREN
Enable PWM trigger ADC function while Channel3's counter matching CMR3 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
24
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT0TRGEN
Enable PWM trigger ADC function while Channel0's counter matching CNR0 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT1TRGEN
Enable PWM trigger ADC function while Channel1's counter matching CNR1 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT2TRGEN
Enable PWM trigger ADC function while Channel2's counter matching CNR2 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
17
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT3TRGEN
Enable PWM trigger ADC function while Channel3's counter matching CNR3 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
25
1
read-write
0
Disabled
#0
1
Enabled
#1
P0TRGEN
Enable PWM trigger ADC function while Channel0's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
P1TRGEN
Enable PWM trigger ADC function while Channel1's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
11
1
read-write
0
Disabled
#0
1
Enabled
#1
P2TRGEN
Enable PWM trigger ADC function while Channel2's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
19
1
read-write
0
Disabled
#0
1
Enabled
#1
P3TRGEN
Enable PWM trigger ADC function while Channel1's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
27
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGCON1
TRGCON1
PWM Trigger Control Register 1
0x6C
read-write
n
0x0
0x0
CM4TRGFEN
Enable PWM trigger ADC function while Channel4's counter matching CMR4 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
2
1
read-write
0
Disabled
#0
1
Enabled
#1
CM4TRGREN
Enable PWM trigger ADC function while Channel4's counter matching CMR4 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
CM5TRGFEN
Enable PWM trigger ADC function while Channel5's counter matching CMR5 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
10
1
read-write
0
Disabled
#0
1
Enabled
#1
CM5TRGREN
Enable PWM trigger ADC function while Channel5's counter matching CMR5 in up-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
8
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT4TRGEN
Enable PWM trigger ADC function while Channel4's counter matching CNR4 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
1
1
read-write
0
Disabled
#0
1
Enabled
#1
CNT5TRGEN
Enable PWM trigger ADC function while Channel5's counter matching CNR5 in down-count direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
9
1
read-write
0
Disabled
#0
1
Enabled
#1
P4TRGEN
Enable PWM trigger ADC function while Channel4's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
3
1
read-write
0
Disabled
#0
1
Enabled
#1
P5TRGEN
Enable PWM trigger ADC function while Channel5's counter matching 0 in down-count direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
11
1
read-write
0
Disabled
#0
1
Enabled
#1
TRGSTS0
TRGSTS0
PWM Trigger Status Register 0
0x70
read-write
n
0x0
0x0
CMR0FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
2
1
read-write
CMR0FLAG_R
ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
0
1
read-write
CMR1FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
10
1
read-write
CMR1FLAG_R
ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
8
1
read-write
CMR2FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
18
1
read-write
CMR2FLAG_R
ADC trigger flag by counting up to CMR \nNote: Software can write 1 to clear this bit.
16
1
read-write
CMR3FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
26
1
read-write
CMR3FLAG_R
ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
24
1
read-write
CNT0FLAG
ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
1
1
read-write
CNT1FLAG
ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
9
1
read-write
CNT2FLAG
ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
17
1
read-write
CNT3FLAG
ADC trigger flag by counting to CNR
Note: Software can write 1 to clear this bit.
25
1
read-write
PERID0FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
3
1
read-write
PERID1FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
11
1
read-write
PERID2FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
19
1
read-write
PERID3FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
27
1
read-write
TRGSTS1
TRGSTS1
PWM Trigger Status Register 1
0x74
read-write
n
0x0
0x0
CMR4FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
2
1
read-write
CMR4FLAG_R
ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
0
1
read-write
CMR5FLAG_F
ADC trigger flag by counting down to CMR\nNote: Software can write 1 to clear this bit.
10
1
read-write
CMR5FLAG_R
ADC trigger flag by counting up to CMR\nNote: Software can write 1 to clear this bit.
8
1
read-write
CNT4FLAG
ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit.
1
1
read-write
CNT5FLAG
ADC trigger flag by counting to CNR\nNote: Software can write 1 to clear this bit.
9
1
read-write
PERID4FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
3
1
read-write
PERID5FLAG
ADC trigger flag by period \nNote: Software can write 1 to clear this bit.
11
1
read-write
SCS
SCS Register Map
SCS
0x0
0x10
0xC
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x200
0x4
registers
n
0x280
0x4
registers
n
0x400
0x20
registers
n
0xD00
0x8
registers
n
0xD0C
0x8
registers
n
0xD1C
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xD0C
-1
read-write
n
0x0
0x0
SYSRESETREQ
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
2
1
read-write
VECTCLRACTIVE
Setting this bit to 1 will clear all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
1
1
read-write
VECTORKEY
When writing this register, this field should be 0x05FA otherwise, the write action will be unpredictable.
16
16
read-write
CPUID
CPUID
CPUID Base Register
0xD00
-1
read-only
n
0x0
0x0
IMPLEMENTER
None
24
8
read-only
PART
Reads as 0xC for ARMv6-M parts.
16
4
read-only
PARTNO
Reads as 0xC20.
4
12
read-only
REVISION
Reads as 0x0.
0
4
read-only
ICSR
ICSR
Interrupt Control State Register
0xD04
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag (Read Only)\nExcluding NMI and Faults.\n
22
1
read-only
0
Interrupt not pending
#0
1
Interrupt pending
#1
ISRPREEMPT
Interrupt Preemption (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
23
1
read-only
NMIPENDSET
NMI Set-pending Bit.\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
No effect.\nNMI exception not pending
#0
1
NMI exception state changed to pending.\nNMI exception pending
#1
PENDSTCLR
SysTick Exception Clear-pending Bit (Write Only)\nWrite:\n
25
1
write-only
0
No effect
#0
1
The pending state removed from the SysTick exception
#1
PENDSTSET
SysTick Exception Set-pending Bit\nWrite:\n
26
1
read-write
0
No effect.\nSysTick exception not pending
#0
1
SysTick exception state changed to pending.\nSysTick exception pending
#1
PENDSVCLR
PendSV Clear-pending Bit (Write Only)\nWrite:\n
27
1
write-only
0
No effect
#0
1
The pending state removed from the PendSV exception
#1
PENDSVSET
PendSV Set-pending Bit\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
No effect.\nPendSV exception not pending
#0
1
PendSV exception state changed to pending.\nPendSV exception pending
#1
VECTACTIVE
Vector Active Indicator (Read Only)\nThis field contains the active exception number:\n
0
9
read-only
0
Thread mode
0
VECTPENDING
Vector Pending Indicator (Read Only)\nThis field indicates the exception number of the highest priority pending enabled exception:\n
12
9
read-only
0
No pending exceptions
0
NVIC_ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-enable Control Register
0x180
read-write
n
0x0
0x0
CLRENA
Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
The associated interrupt Disabled
1
NVIC_ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-pending Control Register
0x280
read-write
n
0x0
0x0
CLRPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
The associated interrupt under software control un-pended. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
NVIC_IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Priority Control Register
0x400
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_1
Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_2
Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_3
Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Priority Control Register
0x404
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_5
Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_6
Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_7
Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Priority Control Register
0x408
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_11
Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
PRI_8
Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_9
Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
NVIC_IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Priority Control Register
0x40C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_13
Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_14
Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_15
Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Priority Control Register
0x410
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_17
Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_18
Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_19
Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Priority Control Register
0x414
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_21
Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_22
Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_23
Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Priority Control Register
0x418
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_25
Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_26
Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_27
Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Priority Control Register
0x41C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority.
6
2
read-write
PRI_29
Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority.
14
2
read-write
PRI_30
Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority.
22
2
read-write
PRI_31
Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority.
30
2
read-write
NVIC_ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-enable Control Register
0x100
read-write
n
0x0
0x0
SETENA
Enable one or more interrupts within a group of 32 bits. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nThe register reads back with the current enable state.
0
32
read-write
0
No effect
0
1
The associated interrupt Enabled
1
NVIC_ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-pending Control Register
0x200
read-write
n
0x0
0x0
SETPEND
The register reads back with the current pending state.
0
32
read-write
0
No effect
0
1
The associated interrupt under software control pended. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47)
1
SCR
SCR
System Control Register
0xD10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Only the enabled interrupts or events can wake up the processor, disabled interrupts are excluded
#0
1
The enabled events and all interrupts, including disabled interrupts, can wake up the processor
#1
SLEEPDEEP
Deep Sleep Mode Enable\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:\n
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-On-exit Enable\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter sleep or deep sleep when returning from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0xD1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes lowest priority.
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0xD20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes lowest priority.
22
2
read-write
PRI_15
Priority of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes lowest priority.
30
2
read-write
SYST_CSR
SYST_CSR
SysTick Control and Status
0x10
read-write
n
0x0
0x0
CLKSRC
None
2
1
read-write
0
Clock source is optional (refer to STCLK_S)
#0
1
Core clock used for SysTick if no external clock provided this bit will read as 1 and ignore writes
#1
COUNTFLAG
Returns 1 if timer counted to 0 since this register was read last time.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
16
1
read-write
ENABLE
None
0
1
read-write
0
The counter Disabled
#0
1
The counter will operate in a multi-shot manner
#1
TICKINT
None
1
1
read-write
0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#0
1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
#1
SYST_CVR
SYST_CVR
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
CURRENT
Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. Software write of any value will clear the register to 0. Bits RAZ is not supported (see SysTick Reload Value Register).
0
24
read-write
SYST_RVR
SYST_RVR
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0.
0
24
read-write
SPI
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity\n
11
1
read-write
0
SPICLK idle low
#0
1
SPICLK idle high
#1
FIFO
FIFO Mode\nNote:\nBefore enabling FIFO mode, the other related settings should be set in advance.\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0.
21
1
read-write
0
Disable FIFO Mode
#0
1
Enable FIFO Mode
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.\nNote:\nAll registers should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Writing 0 to this bit to stop data transfer if SPI is transferring
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
SPI Unit Transfer Interrupt Enable Bit\n
17
1
read-write
0
Disable SPI unit transfer interrupt
#0
1
Enable SPI unit transfer interrupt
#1
IF
SPI Unit Transfer Interrupt Flag\nNote: Software can write 1 to clear this bit.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
LSB
LSB First\n
10
1
read-write
0
The MSB, which bit of SPI_TX0/SPI_RX0 register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI_TX0 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0)
#1
REORDER
Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
19
1
read-write
0
Disable the byte reorder function
#0
1
Enable byte reorder function
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].\n
25
1
read-only
0
Indicates that the receive FIFO buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_NEG
Receive At Negative Edge\n
1
1
read-write
0
The received data input signal latched at the rising edge of SPICLK
#0
1
The received data input signal latched at the falling edge of SPICLK
#1
SLAVE
Slave Mode Enable Bit\n
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].\n
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].\n
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_NEG
Transmit At Negative Edge\n
2
1
read-write
0
The transmitted data output signal changed at the rising edge of SPICLK
#0
1
The transmitted data output signal changed at the falling edge of SPICLK
#1
CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
The clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI.\nNote: In 3-wire mode, the SS_LTRIG, SPI_SSR[4], shall be set as 1.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.\n
11
1
read-write
0
It indicates that the SPI transfer is not active
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared to 0 as transfer done or by writing one to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
10
1
read-write
0
Disable the transfer start interrupt
#0
1
Enable the transaction start interrupt. It is cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider Register (Master Only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0.\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source. It is defined in the CLKSEL1 register.
0
8
read-write
FIFO_CTL
SPI_FIFO_CTL
FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable\n
6
1
read-write
0
Disable Receive FIFO overrun interrupt
#0
1
Enable Receive FIFO overrun interrupt
#1
RX_CLR
Clear Receive FIFO Buffer\n
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
RX_INTEN
Receive Threshold Interrupt Enable\n
2
1
read-write
0
Disable receive threshold interrupt
#0
1
Enable receive threshold interrupt
#1
RX_THRESHOLD
Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
2
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable\n
21
1
read-write
0
Disable time-out interrupt
#0
1
Enable time-out interrupt
#1
TX_CLR
Clear Transmit FIFO Buffer\n
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1
#1
TX_INTEN
Transmit Threshold Interrupt Enable\n
3
1
read-write
0
Disable transmit threshold interrupt
#0
1
Enable transmit threshold interrupt
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
2
read-write
RX0
SPI_RX0
Data Receive Register 0
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register.
0
32
read-only
SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Selection Function Enable Bit (Master Only)\n
3
1
read-write
0
If this bit is cleared, slave select signal is asserted and de-asserted by setting and clearing SSR[0]
#0
1
If this bit is set, SPISS signal are generated automatically. It means that device/slave select signal which is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only.
5
1
read-write
0
The transferred bit length of one transaction does not meet the specified requirement
#0
1
The transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to this field sets the SPISS line to active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to this field will keep the SPISS line at inactive state writing 1 to this field will select the SPISS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISS is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable Bit (Slave only)\n
4
1
read-write
0
The slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
The slave select signal will be level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nIt defines the active status of slave select signal (SPISS).\n
2
1
read-write
0
The slave select signal SPISS is active at low-level/falling-edge
#0
1
The slave select signal SPISS is active at high-level/rising-edge
#1
STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: Software can write 1 to clear this bit.
16
1
read-write
0
It indicates that the transfer does not finish yet
#0
1
It indicates that the SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n
24
1
read-only
0
Indicates that the receive FIFO buffer is not empty
#0
1
Indicates that the receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only) \nIt's a mutual mirror bit of SPI_CNTRL[25].\n
25
1
read-only
0
Indicates that the receive FIFO buffer is not full
#0
1
Indicates that the receive FIFO buffer is full
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)\n
0
1
read-only
0
It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: Software can write 1 to clear this bit.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n
11
1
read-write
0
It indicates that the transfer is not started
#0
1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: Software can write 1 to clear this bit.
20
1
read-write
0
No receive FIFO time-out event
#0
1
It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only) \nIt's a mutual mirror bit of SPI_CNTRL[26].\n
26
1
read-only
0
Indicates that the transmit FIFO buffer is not empty
#0
1
Indicates that the transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27].\n
27
1
read-only
0
Indicates that the transmit FIFO buffer is not full
#0
1
Indicates that the transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (read only)\n
4
1
read-only
0
It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
TX0
SPI_TX0
Data Transmit Register 0
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
0
32
write-only
TMR
TMR Register Map
TMR
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPN (TEXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE (TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.
0
24
read-only
TCAP1
TCAP1
Timer1 Capture Data Register
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nNote1: Never write 0 or 1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
0
24
read-write
TCMPR1
TCMPR1
Timer1 Compare Register
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n
25
1
read-only
0
Timer not active
#0
1
Timer active
#1
CAPS
Capture Trigger Source Selection\n
19
1
read-write
0
Time0/1 capture mode trigger input source is T0EX/T1EX pin
#0
1
Time0/1 capture mode trigger input source is ACMP0/ACMP1 output
#1
CEN
Timer Enable Bit\n
30
1
read-write
0
Counting stopped/suspended
#0
1
Counting started
#1
CRST
Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n
26
1
read-write
0
No effect
#0
1
Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit reset
#1
CTB
Counter Mode Enable Bit\nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n
24
1
read-write
0
Counter mode Disabled
#0
1
Counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nThe TIMER counter will be held while ICE Debug mode acknowledged.
31
1
read-write
0
ICE Debug mode acknowledgement effects TIMER counting
#0
1
ICE Debug mode acknowledgement Disabled
#1
IE
Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode\n
27
2
read-write
PERIOD2
PERIOD2 Enable Bit\n
17
1
read-write
0
In One-shout or Periodic mode, when write new TCMP, timer counter will reset
#0
1
In One-shout or Periodic mode, when write new TCMP
#1
PRESCALE
Pre-Scale Counter\n
0
8
read-write
TDR_EN
Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled
#1
TOUT
Toggle Out Pin Selection\nWhen Timer is set to toggle mode,\n
18
1
read-write
0
Time0/1 toggle output pin is T0/T1 pin
#0
1
Time0/1 toggle output pin is T0EX/T1EX pin
#1
WAKE_EN
Wake-Up Enable\nWhen WAKE_EN is set and the TIF or TEXIF is set, the timer controller will generator a wake-up trigger event to CPU.\n
23
1
read-write
0
Wake-up trigger event Disabled
#0
1
Wake-up trigger event Enabled
#1
TCSR1
TCSR1
Timer1 Control and Status Register
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nThis field indicates the current count value.
0
24
read-only
TDR1
TDR1
Timer1 Data Register
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
CAP_MODE
Capture Mode Selection\n
8
1
read-write
0
Timer counter reset function or free-counting mode of timer capture function
#0
1
Trigger-counting mode of timer capture function
#1
RSTCAPN
Timer External Reset Counter / Capture Mode Selection\n
4
1
read-write
0
TEX transition is used as the timer capture function
#0
1
TEX transition is used as the timer counter reset function
#1
TCDB
Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0~T1 pin is detected with de-bounce circuit.
7
1
read-write
0
De-bounce Disabled
#0
1
De-bounce Enabled
#1
TEXDB
Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TEX pin is detected with de-bounce circuit.
6
1
read-write
0
De-bounce Disabled
#0
1
De-bounce Enabled
#1
TEXEN
Timer External Pin Enable\nThis bit enables the reset/capture function on the TEX pin.\n
3
1
read-write
0
The TEX pin will be ignored
#0
1
The transition detected on the TEX pin will result in capture or reset of timer counter
#1
TEXIEN
Timer External Interrupt Enable Bit\n
5
1
read-write
0
Timer External Interrupt Disabled
#0
1
Timer External Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detection\n
1
2
read-write
TX_PHASE
Timer External Count Phase\nThis bit indicates the external count pin phase.\n
0
1
read-write
0
A falling edge of external count pin will be counted
#0
1
A rising edge of external count pin will be counted
#1
TEXCON1
TEXCON1
Timer1 External Control Register
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag\nThis bit indicates the external interrupt status of the timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting occurred. Software can write 1 to clear this bit.\n
0
1
read-write
TEXISR1
TEXISR1
Timer1 External Interrupt Status Register
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\n
0
1
read-write
TWF
Timer Wake-up Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nSoftware can write 1 to clear this bit.\n
1
1
read-write
0
Timer does not cause CPU wake-up
#0
1
CPU wakes up from sleep or power-down mode by timer time-out
#1
TISR1
TISR1
Timer1 Interrupt Status Register
0x28
read-write
n
0x0
0x0
UART
UART Register Map
UART
0x0
0x0
0x30
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for Auto RS-485 Address Detection mode.
24
8
read-write
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It is unable to be active with RS-485_NMM Operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for any RS-485 Operation mode.
15
1
read-write
0
Address Detection mode Disabled
#0
1
Address Detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD)\nNote: It is able to be active in RS-485_AAD or RS-485_NMM Operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUD) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUD) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It is unable to be active in RS-485_AAD Operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider.
0
16
read-write
DIVIDER_X
Divider X\n
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode, this bit must be disabled.
29
1
read-write
0
The divider X Disabled (the equation of M = 16)
#0
1
The divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X equal 1\nRefer to the table below for more information.
28
1
read-write
0
Divider M = any value (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level\n
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
The RX internal state machine and pointers reset
#1
RTS_TRI_LEV
RTSn Trigger Level (for Auto-flow Control Use)\n
16
4
read-write
RX_DIS
Receiver Disable register\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR[RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
The TX internal state machine and pointers reset
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)
This bit is set to a logic 1 when the received data input(RX) is held in the spacing state (logic 0) for the time longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset when the CPU writes 1 to this bit.
Note: This bit is read only, but software can write 1 to clear it.
6
1
read-only
FEF
Framing Error Flag (Read Only)
This bit is set to logic 1 when the received character does not have a valid stop bit (that is, the stop bit follows the last data bit or parity bit is detected as a logic 0), and is reset when the CPU writes 1 to this bit.
Note: This bit is read only, but software can write 1 to clear it.
5
1
read-only
PEF
Parity Error Flag (Read Only)
This bit is set to logic 1 when the received character does not have a valid parity bit , and is reset when the CPU writes 1 to this bit.
Note: This bit is read only, but software can write 1 to clear it.
4
1
read-only
RS_485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but software can write 1 to clear it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiates RX FIFO empty (or not).\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
This bit is set when RX_POINTER is equal to 16 otherwise, it is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART, this bit will be set.\nNote: This bit is read only, but software can write 1 to clear it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When the UART receives one byte from an external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates whether TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 16, otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but software can write 1 to clear it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable\n
0
2
read-write
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
CTS Auto Flow Control Enable\nNote: When CTSn auto-flow is enabled, the UART will send data to external device when CTSn input assert (UART will not send data to device until CTSn is asserted).
13
1
read-write
0
CTSn auto flow control Disabled
#0
1
CTSn auto flow control Enabled
#1
AUTO_RTS_EN
RTS Auto Flow Control Enable\nNote: When RTSn auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTSn signal.
12
1
read-write
0
RTSn auto flow control Disabled
#0
1
RTSn auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable\n
5
1
read-write
0
INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable\n
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable\n
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable\n
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
RTO_IEN
RX Time-out Interrupt Enable\n
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable\n
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time-out Counter Enable\n
11
1
read-write
0
Time-out counter Disabled
#0
1
Time-out counter Enabled
#1
WAKE_EN
Wake-up CPU Function Enable\n
6
1
read-write
0
UART wake-up CPU function Disabled
#0
1
Wake-up function Enabled when the system is in Deep Sleep mode, an external CTSn change will wake up CPU from Deep Sleep mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX\n
6
1
read-write
0
No inversion
#0
1
RX input signal inversed
#1
INV_TX
INV_TX\n
5
1
read-write
0
No inversion
#0
1
TX output signal inversed
#1
TX_SELECT
TX_SELECT\nNote: When in IrDA mode, the UA_BAUD[DIV_X_EN] register must be disabled (the baud equation must be Clock / 16 * (BRD).
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF ) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator To Interrupt Controller (Read Only)\nAn AND output with inputs of BUF_ERR_IEN and BUF_ERR_IF.
13
1
read-only
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n
11
1
read-only
0
No Modem interrupt generated
#0
1
The Modem interrupt generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER[RDA_IEN] is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n
8
1
read-only
0
No RDA interrupt generated
#0
1
The RDA interrupt generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER[RLS_IEN] is enabled, the RLS interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if RLS_IEN and RLS_IF .are both set to 1.\n
10
1
read-only
0
No RLS interrupt generated
#0
1
The RLS interrupt generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n
9
1
read-only
0
No THRE interrupt generated
#0
1
The THRE interrupt generated
#1
TOUT_IF
Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If UA_IER[TOUT_IEN] is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time-out Interrupt Indicator to Interrupt Controller (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n
12
1
read-only
0
No Tout interrupt generated
#0
1
The Tout interrupt generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nNote: This bit has effect only when bit 3 (parity bit enable) is set.
4
1
read-write
0
Odd number of logic 1 transmitted or checked in the data word and parity bits
#0
1
Even number of logic 1 transmitted or checked in the data word and parity bits
#1
NSB
Number of STOP bit
2
1
read-write
0
One STOP bit is generated in the transmitted data
#0
1
One and a half STOP bit is generated in the transmitted data when 5-bit word length is selected Two STOP bit is generated when 6, 7 and 8bit word length is selected
#1
PBE
Parity Bit Enable\n
3
1
read-write
0
Parity bit not generated (transmit data) or checked (receive data) during transfer
#0
1
Parity bit generated or checked between the last data word bit and stop bit of the serial data
#1
SPE
Stick Parity Enable\n
5
1
read-write
0
Stick parity Disabled
#0
1
When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as cleared. When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as set
#1
WLS
Word Length Selection\n
0
2
read-write
UA_MCR
UA_MCR
UART Modem Control Register
0x10
read-write
n
0x0
0x0
LEV_RTS
RTSn Trigger Level\nThis bit can change the RTSn trigger level.\n
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTSn
RTSn (Request-to-Send) Signal\n
1
1
read-write
RTS_ST
RTSn Pin State (Read Only)\nThis bit is the output pin status of RTSn.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
read-write
n
0x0
0x0
CTS_ST
CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.
4
1
read-only
DCTSF
Detect CTSn State Change Flag (Read Only)\nThis bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when UA_IER[MODEM_IEN].\nNote: This bit is read only, but software can write 1 to clear it.
0
1
read-only
LEV_CTS
CTSn Trigger Level\nThis bit can change the CTSn trigger level.\n
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART sends out an 8-bit data through the TX pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time-out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time-out Interrupt Comparator\n
0
8
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x4
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable (write-protection bit)\nThe Watchdog Timer counter will be held while ICE Debug mode is acknowledged.
31
1
read-write
0
ICE Debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE Debug mode acknowledgement Disabled
#1
WTE
Watchdog Timer Enable\n
7
1
read-write
0
Watchdog Timer Disabled (this action will reset the internal counter)
#0
1
Watchdog Timer Enabled
#1
WTIE
Watchdog Timer Interrupt Enable\n
6
1
read-write
0
Watchdog Timer interrupt Disabled
#0
1
Watchdog Timer interrupt Enabled
#1
WTIF
Watchdog Timer Interrupt Flag\nIf the Watchdog Timer interrupt is Enabled, hardware will set this bit to indicate that the Watchdog Timer interrupt has occurred.\nNote: Software can write 1 to clear this bit.
3
1
read-write
0
Watchdog Timer interrupt does not occur
#0
1
Watchdog Timer interrupt occurs
#1
WTIS
Watchdog Timer Interval Selection\n
8
3
read-write
WTR
Clear Watchdog Timer\nSet this bit will clear the Watchdog Timer.\nNote: This bit will be automatically cleared after a few clock cycles.
0
1
read-write
0
No effect
#0
1
The contents of the Watchdog Timer Reset
#1
WTRE
Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog Timer Reset function.\n
1
1
read-write
0
Watchdog Timer reset function Disabled
#0
1
Watchdog Timer reset function Enabled
#1
WTRF
Watchdog Timer Reset Flag\nWhen the Watchdog Timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog Timer has no effect on this bit.\nNote: Software can write 1 to clear this bit.
2
1
read-write
0
Watchdog Timer reset does not occur
#0
1
Watchdog Timer reset occurs
#1
WTWKE
Watchdog Timer Wake-up Function Enable bit\n
4
1
read-write
0
Watchdog Timer Wake-up CPU function Disabled
#0
1
Wake-up function Enabled so that Watchdog Timer time-out can wake-up CPU from Power-down mode
#1
WTWKF
Watchdog Timer Wake-up Flag\nIf Watchdog Timer causes CPU wakes up from Power-down mode, this bit will be set to high. Software can write 1 to clear this bit.\n
5
1
read-write
0
Watchdog Timer does not cause CPU wake-up
#0
1
CPU wake-up from sleep or Power-down mode by Watchdog time-out
#1