nuvoTon NANO100AN_v1 2024.04.27 NANO100AN_v1 SVD file 8 32 ADC ADC Register Map ADC 0x0 0x0 0x20 registers n 0x28 0x4 registers n 0x30 0x14 registers n 0x54 0x4 registers n 0x60 0x8 registers n ADCDELSEL ADCDELSEL PDMA Counter for Delay Time and PDMA Transfer Count and ADC Start Hold Counter 0x64 -1 read-write n 0x0 0x0 ADCSTHOLDCNT ADC Start Hold Time Counter\nThis ADC start is the start signal from ADC controller to analog ADC, not the ADST in ADCR[11],.\nIn Figure 517, when ADC start signal transition from high to low, the ADC reset signal will transition from low to high, at this moment the ADC hold the input analog single and stop holding when ADC start signal transition from low to high.\nThe interval of the holding time is programmable by setting this register. ADC need ADC start signal to keep low level at least 2 ADC CLOCK in order to get converting result more accurately. Setting this register will change the interval in ADC CLOCK unit 16 8 read-write En2StDelay A/D Delay Time Select Register\nSet this register to adjust the time interval (in PCLK unit )between start signal and enable signal of ADC\nNote: The time interval is En2StDelay+1 PCLK cycle 0 8 read-write TMPDMACNT PDMA Count\nWhen each time out event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and start transfer even though the time out event occur 8 8 read-write ADCHER ADCHER A/D Channel Enable Register 0x34 read-write n 0x0 0x0 CH10SEL Select Channel10 Input\n 11 2 read-write 0 Select VTEMP as channel10 input #00 1 Reserved #01 2 Select AVDD as channel10 input #10 3 Select AVSS as channel10 input #11 CHEN0 Analog Input Channel 0 Enable Control\nIf more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored. 0 1 read-write 0 Disabled #0 1 Enabled #1 CHEN1 Analog Input Channel 1 Enable Control\n 1 1 read-write 0 Disabled #0 1 Enabled #1 CHEN10 Analog Input Channel 10 Enable Control\n 10 1 read-write 0 Disabled #0 1 Enabled #1 CHEN2 Analog Input Channel 2 Enable Control\n 2 1 read-write 0 Disabled #0 1 Enabled #1 CHEN3 Analog Input Channel 3 Enable Control\n 3 1 read-write 0 Disabled #0 1 Enabled #1 CHEN4 Analog Input Channel 4 Enable Control\n 4 1 read-write 0 Disabled #0 1 Enabled #1 CHEN5 Analog Input Channel 5 Enable Control\n 5 1 read-write 0 Disabled #0 1 Enabled #1 CHEN6 Anaslog Input Channel 6 Enable Control\n 6 1 read-write 0 Disabled #0 1 Enabled #1 CHEN7 Analog Input Channel 7 Enable Control\n 7 1 read-write 0 Disabled #0 1 Enabled #1 ADCMPR0 ADCMPR0 A/D Compare Register 0 0x38 read-write n 0x0 0x0 CMPCH Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~10. 3 4 read-write CMPCOND Compare Condition Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF (ADSR[2,1]) will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one #1 CMPD Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software. 18 10 read-write CMPEN Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1, and CMPMATCNT is 0, the CMPF (ADSR[2,1]) will be set once the match is hit 0 1 read-write 0 Compare Disabled #0 1 Compare Enabled #1 CMPIE Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF (ADSR[2,1]) will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated. 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set. 8 4 read-write ADCMPR1 ADCMPR1 A/D Compare Register 1 0x3C read-write n 0x0 0x0 ADCR ADCR A/D Control Register 0x30 -1 read-write n 0x0 0x0 ADEN A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption. 0 1 read-write 0 Disabled #0 1 Enabled #1 ADIE A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1. 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode\n 2 2 read-write 0 Single conversion #00 1 Reserved #01 2 Single-cycle scan #10 3 Continuous scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again. 11 1 read-write 0 Conversion stopped and A/D converter enter idle state #0 1 Conversion starts #1 PTEN PDMA Transfer Enable\n 9 1 read-write 0 PDMA data transfer Disabled #0 1 PDMA data transfer in ADC_RESULT 0~10 Enabled #1 REFSEL Reference Voltage Source Selection\n 16 2 read-write 0 Select power as reference voltage #00 1 Select VBG as reference voltage #01 2 Select external voltage as reference voltage #10 3 Ch7 #11 TMSEL Select A/D Enable Time-Out Source \n 12 2 read-write 0 TMR0 #00 1 TMR1 #01 2 TMR2 #10 3 TMR3 #11 TMTRGMOD Timer Event Trigger ADC Conversion\nsetting TMSEL to select timer event from timer0~3 15 1 read-write 0 This function Disabled #0 1 ADC Enabled by TIMER out event #1 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.\n 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n 8 1 read-write 0 Disabled #0 1 Enabled #1 TRGS Hardware Trigger Source\nSoftware should disable TRGE and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time. 4 2 read-write 0 A/D conversion is started by external STADC pin #00 1 Reserved #01 2 Reserved #10 3 Reserved #11 ADFCR ADFCR A/D FPGA Control Register+ 0x54 read-write n 0x0 0x0 ADPDMA ADPDMA A/D PDMA Current Transfer Data Register 0x60 read-only n 0x0 0x0 AD_PDMA ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data. 0 12 read-only ADSR ADSR A/D Status Register 0x40 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be cleared by writing 1 to it. 0 1 read-write BUSY BUSY/IDLE\n 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel (Read Only)\n 4 4 read-only CMPF0 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0 1 1 read-write 0 Conversion result in ADC_RESULTx does not meet ADCMPR0setting #0 1 Conversion result in ADC_RESULTx meets ADCMPR0setting #1 CMPF1 Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1 2 1 read-write 0 Conversion result in ADC_RESULTx does not meet ADCMPR1 setting #0 1 Conversion result in ADC_RESULTx meets ADCMPR1 setting #1 OVERRUN27_24 Over Run Flag\nWhen VALID is high and ADC converts finish, this field will set to high.\nNote: Those flag are for ADC_RESULT0~7 20 8 read-write OVERRUN30 Over Run Flag\nWhen VALID is high and ADC converts finish, this field will set to high.\nNote: This flag is for ADC_RESULT10 30 1 read-write VALID15_8 Data Valid Flag\nAfter ADC converts finish, this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: Those flags are for ADC_RESULT0~7 8 8 read-write VALID18 Data Valid Flag\nAfter ADC converts finish, this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: This flag is for ADC_RESULT10 18 1 read-write RESULT0 ADC_RESULT0 A/D Result Register 0 0x0 read-only n 0x0 0x0 RSLT A/D Conversion Result\nThis field contains 12 bits conversion result. 0 12 read-only RESULT1 ADC_RESULT1 A/D Result Register 1 0x4 read-write n 0x0 0x0 RESULT10 ADC_RESULT10 A/D Result Register 10 0x28 read-write n 0x0 0x0 RESULT2 ADC_RESULT2 A/D Result Register 2 0x8 read-write n 0x0 0x0 RESULT3 ADC_RESULT3 A/D Result Register 3 0xC read-write n 0x0 0x0 RESULT4 ADC_RESULT4 A/D Result Register 4 0x10 read-write n 0x0 0x0 RESULT5 ADC_RESULT5 A/D Result Register 5 0x14 read-write n 0x0 0x0 RESULT6 ADC_RESULT6 A/D Result Register 6 0x18 read-write n 0x0 0x0 RESULT7 ADC_RESULT7 A/D Result Register 7 0x1C read-write n 0x0 0x0 CLK CLK Register Map CLK 0x0 0x0 0x2C registers n 0x30 0x4 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 DMA_EN DMA Controller Clock Enable\n 1 1 read-write 0 Disabled #0 1 Enabled #1 EBI_EN EBI Controller Clock Enable\n 3 1 read-write 0 Disabled #0 1 Enabled #1 GPIO_EN GPIO Controller Clock Enable \n 0 1 read-write 0 Disabled #0 1 Enabled #1 ISP_EN Flash ISP Controller Clock Enable\n 2 1 read-write 0 Disabled #0 1 Enabled #1 SRAM_EN SRAM Controller Clock Enable\n 4 1 read-write 0 Disabled #0 1 Enabled #1 TICK_EN System Tick Clock Enable\n 5 1 read-write 0 Disabled #0 1 Enabled #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 -1 read-write n 0x0 0x0 ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control\n 28 1 read-write 0 Disabled #0 1 Enabled #1 FDIV_EN Frequency Divider Output Clock Enable Control\n 6 1 read-write 0 Disabled #0 1 Enabled #1 I2C0_EN I2C0 Clock Enable Control \n 8 1 read-write 0 Disabled #0 1 Enabled #1 I2C1_EN I2C1 Clock Enable Control \n 9 1 read-write 0 Disabled #0 1 Enabled #1 I2S_EN I2S Clock Enable Control\n 29 1 read-write 0 Disabled #0 1 Enabled #1 PWM0_CH01_EN PWM0 Channel 0 And Channel 1Clock Enable Control\n 20 1 read-write 0 Disabled #0 1 Enabled #1 PWM0_CH23_EN PWM0 Channel 2 And Channel 3 Clock Enable Control\n 21 1 read-write 0 Disabled #0 1 Enabled #1 PWM1_CH01_EN PWM1 Channel 0 And Channel 1 Clock Enable Control\n 22 1 read-write 0 Disabled #0 1 Enabled #1 PWM1_CH23_EN PWM1 Channel 2 And Channel 3 Clock Enable Control\n 23 1 read-write 0 Disabled #0 1 Enabled #1 RTC_EN Real-Time-Clock Clock Enable Control \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.\n 1 1 read-write 0 Disabled #0 1 Enabled #1 SC0_EN SmartCard 0 Clock Enable Control\n 30 1 read-write 0 Disabled #0 1 Enabled #1 SC1_EN SmartCard 1 Clock Enable Control\n 31 1 read-write 0 Disabled #0 1 Enabled #1 SPI0_EN SPI0 Clock Enable Control \n 12 1 read-write 0 Disabled #0 1 Enabled #1 SPI1_EN SPI1 Clock Enable Control \n 13 1 read-write 0 Disabled #0 1 Enabled #1 SPI2_EN SPI2 Clock Enable Control \n 14 1 read-write 0 Disabled #0 1 Enabled #1 TMR0_EN Timer0 Clock Enable Control\n 2 1 read-write 0 Disabled #0 1 Enabled #1 TMR1_EN Timer1 Clock Enable Control\n 3 1 read-write 0 Disabled #0 1 Enabled #1 TMR2_EN Timer2 Clock Enable Control\n 4 1 read-write 0 Disabled #0 1 Enabled #1 TMR3_EN Timer3 Clock Enable Control\n 5 1 read-write 0 Disabled #0 1 Enabled #1 UART0_EN UART0 Clock Enable Control\n 16 1 read-write 0 Disabled #0 1 Enabled #1 UART1_EN UART1 Clock Enable Control\n 17 1 read-write 0 Disabled #0 1 Enabled #1 USBD_EN USB FS Device Controller Clock Enable Control\n 27 1 read-write 0 Disabled #0 1 Enabled #1 WDT_EN Watch-Dog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.\n 0 1 read-write 0 Disabled #0 1 Enabled #1 CLKDIV0 CLKDIV0 Clock Divider Number Register 0 0x1C read-write n 0x0 0x0 ADC_N ADC Clock Divide Number From ADC Clock Source\n 16 8 read-write HCLK_N HCLK Clock Divide Number From HCLK Clock Source\n 0 4 read-write I2S_N I2S Clock Divide Number From I2S Clock Source\n 12 4 read-write SC0_N SC 0 Clock Divide Number From SC 0 Clock Source\n 28 4 read-write UART_N UART Clock Divide Number From UART Clock Source\n 8 4 read-write USB_N USB Clock Divide Number From PLL Clock \n 4 4 read-write CLKDIV1 CLKDIV1 Clock Divider Number Register 1 0x20 read-write n 0x0 0x0 SC1_N SC 1 Clock Divide Number From SC 1 Clock Source\n 0 4 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Selection\n 0 3 read-write CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADC_S ADC Clock Source Selection\n 2 2 read-write PWM0_CH01_S PWM0 Channel 0 And Channel 1 Clock Source Selection\n 4 2 read-write PWM0_CH23_S PWM0 Channel 2 And Channel 3 Clock Source Selection\n 6 2 read-write TMR0_S TIMER 0 Clock Source Selection\n 8 3 read-write TMR1_S TIMER 1 Clock Source Selection\n 12 3 read-write UART_S UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)\n 0 2 read-write CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x18 -1 read-write n 0x0 0x0 FRQDIV_S Clock Divider Clock Source Selection\n 2 2 read-write I2S_S I2S Clock Source Selection\n 16 2 read-write PWM1_CH01_S PWM1 Channel 0 And Channel 1 Clock Source Selection\n 4 2 read-write PWM1_CH23_S PWM1 Channel 2 And Channel 2 Clock Source Selection\n 6 2 read-write SC_S SC Clock Source Selection\n 18 2 read-write TMR2_S TIMER 2 Clock Source Selection\n 8 3 read-write TMR3_S TIMER 3 Clock Source Selection\n 12 3 read-write CLKSTATUS CLKSTATUS Clock Status Monitor Register 0xC -1 read-only n 0x0 0x0 CLK_SW_FAIL Clock Switch Fail Flag\nThis bit will be set when target switch Clock Source is not stable. This bit is write 1 clear 7 1 read-only 0 Clock switch success #0 1 Clock switch fail #1 HIRC_STB HIRC Clock Source Stable Flag\n 4 1 read-only 0 HIRC clock is not stable or not enable #0 1 HIRC clock is stable #1 HXT_STB HEXT Clock Source Stable Flag\n 0 1 read-only 0 HXT clock is not stable or not enable #0 1 HXT clock is stable #1 LIRC_STB LIRC Clock Source Stable Flag\n 3 1 read-only 0 LIRC clock is not stable or not enable #0 1 LIRC clock is stable #1 LXT_STB LEXT Clock Source Stable Flag\n 1 1 read-only 0 LXT clock is not stable or not enable #0 1 LXT clock is stable #1 PLL_STB PLL Clock Source Stable Flag\n 2 1 read-only 0 PLL clock is not stable or not enable #0 1 PLL clock is stable #1 FRQDIV FRQDIV Frequency Divider Control Register 0x28 read-write n 0x0 0x0 FDIV_EN Frequency Divider Enable Bit\n 4 1 read-write 0 Frequency Divider Disabled #0 1 Frequency Divider Enabled #1 FSEL Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL(FRQDIV[3:0]). 0 4 read-write PD_WK_IS PD_WK_IS Power-down Wake-up Interrupt Status Register 0x30 read-only n 0x0 0x0 PD_WK_IS Wake-Up Interrupt Sstatus In Chip Power-Down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit. 0 1 read-only PLLCTL PLLCTL PLL Control Register 0x24 -1 read-write n 0x0 0x0 FB_DV PLL Feedback Divider Control Pins \nRefer to the formulas below the table.\nThe range of FB_DV is from 0 to 63. 0 5 read-write IN_DV PLL Input Divider Control Pins\nRefer to the formulas below the table. 8 2 read-write OUT_DV PLL Output Divider Control Pins \nRefer to the formulas below the table. 12 1 read-write PD Power-Down Mode If set the PD_EN(PWRCTL[6]) 1 , the PLL will enter Power-down mode too 16 1 read-write 0 PLL is in normal mode #0 1 PLL is in power-down mode (default) #1 PLL_SRC PLL Source Clock Select\n 17 1 read-write 0 PLL source clock from HXT #0 1 PLL source clock from HIRC #1 PWRCTL PWRCTL System Power Down Control Register 0x0 -1 read-write n 0x0 0x0 HIRC_EN HIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nHIRC is enabled by default. 2 1 read-write 0 Disabled #0 1 Enabled #1 HXT_EN HXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe bit default value is set by flash controller user configuration register config0 [26]. \nHXT is disabled by default. 0 1 read-write 0 Disabled #0 1 Enabled #1 HXT_GAIN HXT Gain Control Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off. \n 9 1 read-write 0 Gain control Disabled. It means HXT gain is always high #0 1 Gain control Enabled. HXT gain will be high lasting 2ms then low. This is for power saving #1 HXT_SELXT HXT SELXT\nThis is a protected register. Please refer to open lock sequence to program it.\n 8 1 read-write 0 High frequency crystal loop back path Disabled. It is used for external oscillator #0 1 High frequency crystal loop back path Enabled. It is used for external crystal #1 LIRC_EN LIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLIRC is enabled by default. 3 1 read-write 0 Disabled #0 1 Enabled #1 LXT_EN LXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLXT is disabled by default. 1 1 read-write 0 Disabled #0 1 Enabled #1 LXT_SCNT LXT Stable Time Control\nThis is a protected register. Please refer to open lock sequence to program it.\n 10 1 read-write 0 Delay 4096 LXT before LXT output #0 1 Delay 8192 LXT before LXT output #1 PD_EN Chip Power-Down Mode Enable Bit This is a protected register. Please refer to open lock sequence to program it. When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active. When chip wakes up from Power-down mode, this bit will be auto cleared. When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode. When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC. In Power-down mode, flash macro power is ON. NOTE: It inhibits to set both PD_EN and DPD_EN high. 6 1 read-write 0 Chip operated in Normal mode #0 1 Chip power down Enabled #1 PD_WK_IE Power-Down Mode Wake-Up Interrupt Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nPD_WK_INT will be set if both PD_WK_IS (PD_WK_IS[0]) and PD_WK_IE (PWRCTL[5]) are high. 5 1 read-write 0 Disabled #0 1 Enabled #1 WK_DLY Wake-Up Delay Counter Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.\n 4 1 read-write 0 Delay clock cycle delay Disabled #0 1 Delay clock cycle delay Enabled #1 DMA_GCR VDMA Register Map VDMA 0x0 0x0 0x10 registers n DMA_DSSR0 DMA_DSSR0 DMA Service Selection Control Register 0 0x4 -1 read-write n 0x0 0x0 CH1_SEL Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral by setting CH1_SEL.\n 8 5 read-write 0 Connect to SPI0_TX #00000 1 Connect to SPI1_TX #00001 2 Connect to UART0_TX #00010 3 Connect to UART1_TX #00011 4 Connect to USB_TX #00100 5 Connect to I2S_TX #00101 6 Reserved #00110 7 Reserved #00111 8 Connect to SPI2_TX #01000 9 Connect to TMR0 CH0 #01001 10 Connect to TMR0 CH1 #01010 11 Connect to TMR1 CH0 #01011 12 Connect to TMR1 CH1 #01100 16 Connect to SPI0_RX #10000 17 Connect to SPI1_RX #10001 18 Connect to UART0_RX #10010 19 Connect to UART1_RX #10011 20 Connect to USB_RX #10100 21 Connect to I2S_RX #10101 22 Connect to ADC #10110 23 Reserved #10111 24 Connect to SPI2_RX #11000 25 Connect to PWM0_CH0 #11001 26 Connect to PWM0_CH2 #11010 27 Connect to PWM1_CH0 #11011 28 Connect to PWM1_CH2 #11100 CH2_SEL Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by CH2_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL. 16 5 read-write CH3_SEL Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by CH3_SEL. The channel configuration is the same as CH1_SEL field. Please refer to the explanation of CH1_SEL. 24 5 read-write DMA_DSSR1 DMA_DSSR1 DMA Service Selection Control Register 1 0x8 -1 read-write n 0x0 0x0 CH4_SEL Channel 4 Selection \nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral by setting CH4_SEL.\n 0 5 read-write 0 Connect to SPI0_TX #00000 1 Connect to SPI1_TX #00001 2 Connect to UART0_TX #00010 3 Connect to UART1_TX #00011 4 Connect to USB_TX #00100 5 Connect to I2S_TX #00101 6 Reserved #00110 7 Reserved #00111 8 Connect to SPI2_TX #01000 9 Connect to TMR0 CH0 #01001 10 Connect to TMR0 CH1 #01010 11 Connect to TMR1 CH0 #01011 12 Connect to TMR1 CH1 #01100 16 Connect to SPI0_RX #10000 17 Connect to SPI1_RX #10001 18 Connect to UART0_RX #10010 19 Connect to UART1_RX #10011 20 Connect to USB_RX #10100 21 Connect to I2S_RX #10101 22 Connect to ADC #10110 23 Reserved #10111 24 Connect to SPI2_RX #11000 25 Connect to PWM0_CH0 #11001 26 Connect to PWM0_CH2 #11010 27 Connect to PWM1_CH0 #11011 28 Connect to PWM1_CH2 #11100 DMA_GCRCSR DMA_GCRCSR DMA Global Control Register 0x0 read-write n 0x0 0x0 CLK0_EN DMA Controller Channel 0 Clock Enable Control\n 8 1 read-write 0 Disabled #0 1 Enabled #1 CLK1_EN DMA Controller Channel 1 Clock Enable Control\n 9 1 read-write 0 Disabled #0 1 Enabled #1 CLK2_EN DMA Controller Channel 2 Clock Enable Control\n 10 1 read-write 0 Disabled #0 1 Enabled #1 CLK3_EN DMA Controller Channel 3 Clock Enable Control\n 11 1 read-write 0 Disabled #0 1 Enabled #1 CLK4_EN DMA Controller Channel 4 Clock Enable Control\n 12 1 read-write 0 Disabled #0 1 Enabled #1 DMA_GCRISR DMA_GCRISR DMA Global Interrupt Status Register 0xC read-only n 0x0 0x0 INTR0 Interrupt Status Of Channel 0 (Read Only)\nThis bit is the Interrupt status of DMA channel 0. 0 1 read-only INTR1 Interrupt Status Of Channel 1 (Read Only)\nThis bit is the Interrupt status of DMA channel 1. 1 1 read-only INTR2 Interrupt Status Of Channel 2 (Read Only)\nThis bit is the Interrupt status of DMA channel 2. 2 1 read-only INTR3 Interrupt Status Of Channel 3 (Read Only)\nThis bit is the Interrupt status of DMA channel 3. 3 1 read-only INTR4 Interrupt Status Of Channel 4 (Read Only)\nThis bit is the Interrupt status of DMA channel 4. 4 1 read-only EBI EBI Register Map EBI 0x0 0x0 0x8 registers n EBICON EBICON External Bus Interface General Control Register 0x0 read-write n 0x0 0x0 ExtBW16 EBI Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n 1 1 read-write 0 EBI data width is 8-bit #0 1 EBI data width is 16-bit #1 ExtEN EBI Enable Control\nThis bit is the functional enable bit for EBI.\n 0 1 read-write 0 EBI function is disabled #0 1 EBI function is enabled #1 ExttALE Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n 16 3 read-write MCLKDIV External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as shown in the following table.\n 8 3 read-write 0 HCLK/1 0x0 1 HCLK/2 0x1 2 HCLK/4 0x2 3 HCLK/8 0x3 4 HCLK/16 0x4 5 HCLK/32 0x5 6 HCLK/1 0x6 7 HCLK/1 0x7 MCLKEN External Clock Enable Control\nThis bit control if EBI generates the clock to external device.\nIf external device is a synchronous device, it's necessary to set this bit high to enable EBI generating clock to external device.\n 11 1 read-write 1 Enabled EBI to generate clock to external device #1 EXTIME EXTIME External Bus Interface Timing Control Register 0x4 read-write n 0x0 0x0 ExtIR2R Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n 24 4 read-write ExtIR2W Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS return to high if ExtIR2W is not zero.\n 16 4 read-write ExtIW2X Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n 12 4 read-write ExttACC EBI Data Access Time\nExttACC define data access time (tACC).\n 0 5 read-write ExttAHD EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).\n 8 3 read-write FMC FMC Register Map FMC 0x0 0x0 0x18 registers n 0x40 0x4 registers n DFBADR DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBA Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. 0 32 read-only ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address\nThis chip supports word program only. ISPADR[1:0] must be kept 00b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 FCEN ISP Command\nThe ISP command table is shown as follows. 4 1 read-write FCTRL ISP Command\n 0 4 read-write FOEN ISP Command\nThe ISP command table is shown as follows. 5 1 read-write ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 BS Boot Select (Write-Protection Bit) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset. 1 1 read-write 0 boot from APROM #0 1 boot from LDROM #1 ET Flash Erase Time (Write-Protection Bits)\n 12 3 read-write ISPEN ISP Enable (Erite-Protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed when the MCU is running in APROM\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear. 6 1 read-write PT Flash Program Time (Write-Protection Bits)\n 8 3 read-write SWRST Software Reset\nWriting 1 to this bit to start software reset. \nIt is cleared by hardware after reset is finished. 7 1 read-write ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTA ISPSTA ISP Status Register 0x40 read-write n 0x0 0x0 CBS Config Boot Selection Status\n 1 2 read-write ISPBUSY ISP BUSY\n\nRead Only 0 1 read-write 0 ISP operation is finished #0 1 ISP operation is busy #1 ISPFF ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself. \n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear. 6 1 read-write VECMAP Vector Page Mapping Address (Read Only) The current system memory space 0x0000_0000~0x0000_01FF is mapped to flash memory page with base address (VECMAP[11:0] 9). When chip is reset, the remapping address (VECMAP) is clear to CONFIG0 (CBS) default address setting. 9 12 read-only ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n 0 1 read-write 0 ISP operation is finished #0 1 ISP is on going #1 GCR GCR Register Map GCR 0x0 0x0 0x14 registers n 0x100 0x4 registers n 0x20 0x4 registers n 0x30 0x2C registers n 0x60 0x10 registers n 0x80 0xC registers n BODCTL BODCTL Brown-out Detector Control Register 0x64 -1 read-write n 0x0 0x0 BOD17_EN Brown-Out Detector 1.7V Function Enable \n 0 1 read-write 0 Brown-out Detector 1.7V function Disabled #0 1 Brown-out Detector 1.7V function Enabled #1 BOD17_INT_EN BOD 1.7 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n 8 1 read-write 0 Interrupt does not issue when BOD17 occurs #0 1 Interrupt issues when BOD17 occurs #1 BOD17_RST_EN BOD 1.7 V Reset Enable\n 4 1 read-write 0 Reset does not issue when BOD17 occurs #0 1 Reset issues when BOD17 occurs #1 BOD20_EN Brown-Out Detector 2.0 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nBOD20_EN is default on. If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode. If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically. 1 1 read-write 0 Brown-out Detector 2.0 V function Disabled #0 1 Brown-out Detector 2.0 V function Enabled #1 BOD20_INT_EN BOD 2.0 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n 9 1 read-write 0 Interrupt does not issue when BOD20 occurs #0 1 Interrupt issues when BOD20 occurs #1 BOD20_RST_EN BOD 2.0 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19] 5 1 read-write 0 Reset does not issue when BOD20 occurs #0 1 Reset issues when BOD20 occurs #1 BOD25_EN Brown-Out Detector 2.5 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\n 2 1 read-write 0 Brown-out Detector 2.5 V function Disabled #0 1 Brown-out Detector 2.5 V function Enabled #1 BOD25_INT_EN BOD 2.5 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n 10 1 read-write 0 Interrupt does not issue when BOD25 occurs #0 1 Interrupt issues when BOD25 occurs #1 BOD25_RST_EN BOD 2.5 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19] 6 1 read-write 0 Reset does not issue when BOD25 occurs #0 1 Reset issues when BOD25 occurs #1 BODSTS BODSTS Brown-out Detector Status Register 0x68 read-only n 0x0 0x0 BOD17_OUT Brown-Out Detector Output Status\n 1 1 read-only 0 Brown-out Detector output status is 0. It means the detected voltage is higher than target detected voltage setting #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than target detected voltage setting (1.7V). If the BOD17_EN is 0 , BOD17 function disabled, this bit always responds 0 #1 BOD20_OUT Brown-Out Detector Output Status\n 2 1 read-only 0 Brown-out Detector output status is 0. It means the detected voltage is higher than target detected voltage setting #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than target detected voltage setting (2.0 V). If the BOD20_EN is 0 , BOD20 function disabled, this bit always responds 0 #1 BOD25_OUT Brown-Out Detector Output Status\n 3 1 read-only 0 Brown-out Detector output status is 0. It means the detected voltage is higher than target detected voltage setting #0 1 Brown-out Detector output status is 1. It means the detected voltage is lower than target detected voltage setting (2.5 V). If the BOD25_EN is 0 , BOD25 function disabled, this bit always responds 0 #1 BOD_INT Brown-Out Detector Interrupt Status\nThis bit is cleared by writing 1 to itself. 0 1 read-only 0 Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled #0 1 When Brown-out Detector detects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage and Brown-out interrupt is enabled, this bit will be set to 1 #1 CPR CPR Chip Performance Register 0x10 -1 read-write n 0x0 0x0 HPE High Performance Enable\nThis bit is used to control chip operation performance.\nWhen this bit set, internal RAM and GPIO access is working with zero wait state, Flash controller will predict next address more efficiently \n 0 1 read-write 0 Chip operation at normal mode #0 1 Chip operation at high performance mode #1 IPRST_CTL1 IPRST_CTL1 IP Reset Control Resister 1 0x8 read-write n 0x0 0x0 CHIP_RST CHIP One Shot Reset This is a protected register. Please refer to open lock sequence to program it. Setting this bit will reset the whole chip, including CPU kernel and all peripherals like power-on reset and this bit will automatically return to 0 after the 2 clock cycles. The chip setting from flash will be also reloaded when chip one shot reset. Note: In the following condition, chip setting from flash will be reloaded The Power-On Reset Brown-Out-Detected Reset The low level on the /RESET pin Set CHIP_RST(IPRST_CTL1[0]) 0 1 read-write 0 Normal #0 1 Reset CHIP #1 CPU_RST CPU Kernel One Shot Reset This is a protected register. Please refer to open lock sequence to program it. Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles 1 1 read-write 0 Normal #0 1 Reset CPU #1 DMA_RST DMA Controller Reset This is a protected register. Please refer to open lock sequence to program it. Set this bit 1 will generate a reset signal to the DMA. SW needs to set this bit to low to release reset signal. 2 1 read-write 0 Normal operation #0 1 DMA IP reset #1 EBI_RST EBI Controller Reset This is a protected register. Please refer to open lock sequence to program it. Set this bit 1 will generate a reset signal to the EBI. SW needs to set this bit to low to release reset signal. 3 1 read-write 0 Normal operation #0 1 EBI IP reset #1 IPRST_CTL2 IPRST_CTL2 IP Reset Control Resister 2 0xC read-write n 0x0 0x0 ADC_RST ADC Controller Reset\n 28 1 read-write 0 ADC block normal operation #0 1 ADC block reset #1 GPIO_RST GPIO Controller Reset\n 1 1 read-write 0 GPIO normal operation #0 1 GPIO reset #1 I2C0_RST I2C0 Controller Reset\n 8 1 read-write 0 I2C0 normal operation #0 1 I2C0 block reset #1 I2C1_RST I2C1 Controller Reset\n 9 1 read-write 0 I2C1 block normal operation #0 1 I2C1 block reset #1 I2S_RST I2S Controller Reset\n 29 1 read-write 0 I2S block normal operation #0 1 I2S block reset #1 PWM0_RST PWM0 Controller Reset\n 20 1 read-write 0 PWM0 block normal operation #0 1 PWM0 block reset #1 PWM1_RST PWM1 Controller Reset\n 21 1 read-write 0 PWM1 block normal operation #0 1 PWM1 block reset #1 SC0_RST SC 0 Controller Reset\n 30 1 read-write 0 SC block normal operation #0 1 SC block reset #1 SC1_RST SC 1 Controller Reset\n 31 1 read-write 0 SC block normal operation #0 1 SC block reset #1 SPI0_RST SPI0 Controller Reset\n 12 1 read-write 0 SPI0 block normal operation #0 1 SPI0 block reset #1 SPI1_RST SPI1 Controller Reset\n 13 1 read-write 0 SPI1 normal operation #0 1 SPI1 block reset #1 SPI2_RST SPI2 Controller Reset\n 14 1 read-write 0 SPI2 normal operation #0 1 SPI2 block reset #1 TMR0_RST Timer0 Controller Reset\n 2 1 read-write 0 Timer0 normal operation #0 1 Timer0 reset #1 TMR1_RST Timer1 Controller Reset\n 3 1 read-write 0 Timer1 normal operation #0 1 Timer1 block reset #1 TMR2_RST Timer2 Controller Reset\n 4 1 read-write 0 Timer2 normal operation #0 1 Timer2 block reset #1 TMR3_RST Timer3 Controller Reset\n 5 1 read-write 0 Timer3 normal operation #0 1 Timer3 block reset #1 UART0_RST UART0 Controller Reset\n 16 1 read-write 0 UART0 normal operation #0 1 UART0 block reset #1 UART1_RST UART1 Controller Reset\n 17 1 read-write 0 UART1 normal operation #0 1 UART1 block reset #1 USBD_RST USB Device Controller Reset\n 27 1 read-write 0 USB block normal operation #0 1 USB block reset #1 IRCTRIMCTL IRCTRIMCTL HIRC Trim Control Register 0x80 read-write n 0x0 0x0 TRIM_LOOP Trim Calculation Loop\n 4 2 read-write TRIM_RETRY_CNT Trim Value Update Limitation Count\n 6 2 read-write TRIM_SEL Trim Frequency Selection\n 0 2 read-write IRCTRIMIEN IRCTRIMIEN HIRC Trim Interrupt Enable Register 0x84 read-write n 0x0 0x0 TRIM_FAIL_IEN Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]).\nIf this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n 1 1 read-write 0 TRIM_FAIL_INT (IRCTRIMINT[1]) status Disabled to trigger an interrupt to CPU #0 1 TRIM_FAIL_INT (IRCTRIMINT[1]) status Enabled to trigger an interrupt to CPU #1 _32K_ERR_IEN 32.768 KHz Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.\nIf this bit is high, and 32K_ERR_INT (IRCTRIMINT[2]) is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.\n 2 1 read-write 0 32K_ERR_INT (IRCTRIMINT[2]) status Disabled to trigger an interrupt to CPU #0 1 32K_ERR_INT (IRCTRIMINT[2]) status Enabled to trigger an interrupt to CPU #1 IRCTRIMINT IRCTRIMINT HIRC Trim Interrupt Status Register 0x88 read-write n 0x0 0x0 FREQ_LOCK HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt. 0 1 read-write TRIM_FAIL_INT Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN (IRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to zero.\n 1 1 read-write 0 Trim value update limitation count doesn't reach #0 1 Trim value update limitation count reached and HIRC frequency still doesn't lock #1 _32K_ERR_INT 32.768 KHz Clock Error Interrupt Status\nThis bit indicates that 32.768 kHz clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN (IRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy. Write 1 to clear this to zero.\n 2 1 read-write 0 32.768 kHz clock frequency is accuracy #0 1 32.768 kHz clock frequency is inaccuracy #1 PA_H_MFP PA_H_MFP Port A High Byte Multiple Function Control Register 0x34 read-write n 0x0 0x0 PA10_MFP PA.10 Pin Function Selection\n 8 3 read-write PA11_MFP PA.11 Pin Function Selection\n 12 3 read-write PA12_MFP PA.12 Pin Function Selection\n 16 3 read-write PA13_MFP PA.13 Pin Function Selection\n 20 3 read-write PA14_MFP PA.14 Pin Function Selection\n 24 3 read-write PA15_MFP PA.15 Pin Function Selection\n 28 3 read-write PA8_MFP PA.8 Pin Function Selection\n 0 3 read-write PA9_MFP PA.9 Pin Function Selection\n 4 3 read-write PA_L_MFP PA_L_MFP Port A Low Byte Multiple Function Control Register 0x30 read-write n 0x0 0x0 PA0_MFP PA.0 Pin Function Selection\n 0 3 read-write PA1_MFP PA.1 Pin Function Selection\n 4 3 read-write PA2_MFP PA.2 Pin Function Selection\n 8 3 read-write PA3_MFP PA.3 Pin Function Selection\n 12 3 read-write PA4_MFP PA.4 Pin Function Selection\n 16 3 read-write PA5_MFP PA.5 Pin Function Selection\n 20 3 read-write PA6_MFP PA.6 Pin Function Selection\n 24 3 read-write PA7_MFP PA.7 Pin Function Selection\n 28 3 read-write PB_H_MFP PB_H_MFP Port B High Byte Multiple Function Control Register 0x3C read-write n 0x0 0x0 PB10_MFP PB.10 Pin Function Selection\n 8 3 read-write PB11_MFP PB.11 Pin Function Selection\n 12 3 read-write PB12_MFP PB.12 Pin Function Selection\n 16 3 read-write PB13_MFP PB.13 Pin Function Selection\n 20 3 read-write PB14_MFP PB.14 Pin Function Selection\n 24 3 read-write PB15_MFP PB.15 Pin Function Selection\n 28 3 read-write PB8_MFP PB.8 Pin Function Selection\n 0 3 read-write PB9_MFP PB.9 Pin Function Selection\n 4 3 read-write PB_L_MFP PB_L_MFP Port B Low Byte Multiple Function Control Register 0x38 read-write n 0x0 0x0 PB0_MFP PB.0 Pin Function Selection\n 0 3 read-write PB1_MFP PB.1 Pin Function Selection\n 4 3 read-write PB2_MFP PB.2 Pin Function Selection\n 8 3 read-write PB3_MFP PB.3 Pin Function Selection\n 12 3 read-write PB4_MFP PB.4 Pin Function Selection\n 16 3 read-write PB5_MFP PB.5 Pin Function Selection\n 20 3 read-write PB6_MFP PB.6 Pin Function Selection\n 24 3 read-write PB7_MFP PB.7 Pin Function Selection\n 28 3 read-write PC_H_MFP PC_H_MFP Port C High Byte Multiple Function Control Register 0x44 read-write n 0x0 0x0 PC10_MFP PC.10 Pin Function Selection\n 8 3 read-write PC11_MFP PC.11 Pin Function Selection\n 12 3 read-write PC12_MFP PC.12 Pin Function Selection\n 16 3 read-write PC13_MFP PC.13 Pin Function Selection\n 20 3 read-write PC14_MFP PC.14 Pin Function Selection\n 24 3 read-write PC15_MFP PC.15 Pin Function Selection\n 28 3 read-write PC8_MFP PC.8 Pin Function Selection\n 0 3 read-write PC9_MFP PC.9 Pin Function Selection\n 4 3 read-write PC_L_MFP PC_L_MFP Port C Low Byte Multiple Function Control Register 0x40 read-write n 0x0 0x0 PC0_MFP PC.0 Pin Function Selection\n 0 3 read-write PC1_MFP PC.1 Pin Function Selection\n 4 3 read-write PC2_MFP PC.2 Pin Function Selection\n 8 3 read-write PC3_MFP PC.3 Pin Function Selection\n 12 3 read-write PC4_MFP PC.4 Pin Function Selection\n 16 3 read-write PC5_MFP PC.5 Pin Function Selection\n 20 3 read-write PC6_MFP PC.6 Pin Function Selection\n\n 24 3 read-write PC7_MFP PC.7 Pin Function Selection\n 28 3 read-write PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device ID \nThis register reflects device part number code. Software can read this register to identify which device is used. 0 32 read-only PD_H_MFP PD_H_MFP Port D High Byte Multiple Function Control Register 0x4C read-write n 0x0 0x0 PD10_MFP PD.10 Pin Function Selection\n 8 3 read-write PD11_MFP PD.11 Pin Function Selection\n 12 3 read-write PD12_MFP PD.12 Pin Function Selection\n 16 3 read-write PD13_MFP PD.13 Pin Function Selection\n 20 3 read-write PD14_MFP PD.14 Pin Function Selection\n 24 3 read-write PD15_MFP PD.15 Pin Function Selection\n 28 3 read-write PD8_MFP PD.8 Pin Function Selection\n 0 3 read-write PD9_MFP PD.9 Pin Function Selection\n 4 3 read-write PD_L_MFP PD_L_MFP Port D Low Byte Multiple Function Control Register 0x48 read-write n 0x0 0x0 PD0_MFP PD.0 Pin Function Selection\n 0 3 read-write PD1_MFP PD.1 Pin Function Selection\n 4 3 read-write PD2_MFP PD.2 Pin Function Selection\n 8 3 read-write PD3_MFP PD.3 Pin Function Selection\n 12 3 read-write PD4_MFP PD.4 Pin Function Selection\n\n 16 3 read-write PD5_MFP PD.5 Pin Function Selection\n 20 3 read-write PD6_MFP PD.6 Pin Function Selection\n 24 3 read-write PD7_MFP PD.7 Pin Function Selection\n 28 3 read-write PE_H_MFP PE_H_MFP Port E High Byte Multiple Function Control Register 0x54 read-write n 0x0 0x0 PE10_MFP PE.10 Pin Function Selection\n 8 3 read-write PE11_MFP PE.11 Pin Function Selection\n 12 3 read-write PE12_MFP PE.12 Pin Function Selection\n 16 3 read-write PE13_MFP PE.13 Pin Function Selection\n 20 3 read-write PE14_MFP PE.14 Pin Function Selection\n 24 3 read-write PE15_MFP PE.15 Pin Function Selection\n 28 3 read-write PE8_MFP PE.8 Pin Function Selection\n 0 3 read-write PE9_MFP PE.9 Pin Function Selection\n 4 3 read-write PE_L_MFP PE_L_MFP Port E Low Byte Multiple Function Control Register 0x50 read-write n 0x0 0x0 PE0_MFP PE.0 Pin Function Selection\n 0 3 read-write PE1_MFP PE.1 Pin Function Selection\n 4 3 read-write PE2_MFP PE.2 Pin Function Selection\n 8 3 read-write PE3_MFP PE.3 Pin Function Selection\n 12 3 read-write PE4_MFP PE.4 Pin Function Selection\n 16 3 read-write PE5_MFP PE.5 Pin Function Selection\n 20 3 read-write PE6_MFP PE.6 Pin Function Selection\nAll setting : GPIOE[6] 24 3 read-write PE7_MFP PE.7 Pin Function Selection\n 28 3 read-write PF_L_MFP PF_L_MFP Port F Low Byte Multiple Function Control Register 0x58 -1 read-write n 0x0 0x0 PF0_MFP PF.0 Pin Function Selection\n 0 3 read-write PF1_MFP PF.1 Pin Function Selection\n 4 3 read-write PF2_MFP PF.2 Pin Function Selection\n 8 3 read-write PF3_MFP PF.3 Pin Function Selection\n 12 3 read-write PF4_MFP PF.4 Pin Function Selection\n 16 3 read-write PF5_MFP PF.5 Pin Function Selection\n 20 3 read-write PORCTL PORCTL Power-On-reset Controller Register 0x60 read-write n 0x0 0x0 POR_DIS_CODE Power-On Reset Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function 0 16 read-write RegLockAddr RegLockAddr Register Lock Key Address Register 0x100 read-write n 0x0 0x0 RegUnLock None 0 1 read-write 0 Protected register are locked. Any write to the target register is ignored #0 1 Protected registers are Unlock #1 RST_SRC RST_SRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD The RSTS_BOD Flag Is Set By The Reset Signal From The Brown-Out-Detected Module To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself. 4 1 read-write 0 No reset from BOD #0 1 The Brown-Out-Detected module had issued the reset signal to reset the system #1 RSTS_CPU The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) 1 To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC) This bit is cleared by writing 1 to itself. 7 1 read-write 0 No reset from CPU #0 1 The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1 #1 RSTS_PAD The RSTS_PAD Flag Is Set By The Reset Signal From The /RESET Pin To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself. 1 1 read-write 0 No reset from /RESET pin #0 1 The /RESET pin had issued the reset signal to reset the system #1 RSTS_POR The RSTS_POR Flag Is Set By The Reset Signal From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRST_CTL1[0]) To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself. 0 1 read-write 0 No reset from POR or CHIP_RST #0 1 The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system #1 RSTS_SYS The RSTS_SYS Flag Is Set By The Reset Signal From The Cortex_M0 Kernel To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself. 5 1 read-write 0 No reset from Cortex_M0 #0 1 The Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel #1 RSTS_WDT The RSTS_WDT Flag Is Set By The Reset Signal From The Watch-Dog Timer Module To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself. 2 1 read-write 0 No reset from Watch-Dog Timer #0 1 The Watch-Dog Timer module had issued the reset signal to reset the system #1 TEMPCTL TEMPCTL Temperature Sensor Control Register 0x20 read-write n 0x0 0x0 VTEMP_EN Temperature Sensor Enable\n 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 VREFCTL VREFCTL Voltage Reference Control Register 0x6C -1 read-write n 0x0 0x0 BGP_EN Band-Gap Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5V or 2.5V reference voltage.\n 0 1 read-write 0 Disabled #0 1 Enabled #1 EXT_MODE Regulator External Mode\nThis is a protected register. Please refer to open lock sequence to program it.\nUsers can output regulator output voltage in Vref pin if EXT_MODE is high.\n 3 1 read-write 0 No connection with external VREF pin #0 1 Connet to external VREF pin. Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable #1 REG_EN Regulator Enable\nEnable internal 1.5V or 2.5V reference voltage.\nThis is a protected register. Please refer to open lock sequence to program it.\n 1 1 read-write 0 Disabled #0 1 Enabled #1 SEL25 Regulator Output Voltage Selection\nSelect internal reference voltage level.\nThis is a protected register. Please refer to open lock sequence to program it.\n 2 1 read-write 0 1.5V #0 1 2.5V #1 GP GP Register Map GP 0x0 0x0 0x28 registers n 0x100 0x28 registers n 0x140 0x28 registers n 0x180 0x4 registers n 0x200 0x158 registers n 0x40 0x28 registers n 0x80 0x28 registers n 0xC0 0x28 registers n DBNCECON DBNCECON De-bounce Cycle Control Register 0x180 read-write n 0x0 0x0 DBCLKSEL De-Bounce Sampling Cycle Selection\n 0 4 read-write 0 Sample interrupt input once per 1 clock #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-Bounce Counter Clock Source Selection\n 4 1 read-write 0 De-bounce counter Clock Source is the HCLK #0 1 De-bounce counter Clock Source is the internal 10 kHz clock #1 DBCLK_ON De-Bounce Clock Enable\nThis bit controls if the de-bounce clock is enabled.\nHowever, if GPIO pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.\n 5 1 read-write 0 De-bounce clock Disabled #0 1 De-bounce clock Enabled #1 GPIOA0 GPIOA0 GPIO Port A Bit 0 Data Register 0x200 read-write n 0x0 0x0 GPIO GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port [x] pin [n] value.\nRead:\nNote: The write operation will not be affected by register GPIOx_DMASK. 0 1 read-write 0 The corresponding GPIO port [x] pin [n] value is low.\nSet corresponding GPIO port [x] pin [n] to low #0 1 The corresponding GPIO port [x] pin [n] value is high.\nSet corresponding GPIO port [x] pin [n] to high #1 GPIOA1 GPIOA1 GPIO Port A Bit 1 Data Register 0x204 read-write n 0x0 0x0 GPIOA10 GPIOA10 GPIO Port A Bit 10 Data Register 0x228 read-write n 0x0 0x0 GPIOA11 GPIOA11 GPIO Port A Bit 11 Data Register 0x22C read-write n 0x0 0x0 GPIOA12 GPIOA12 GPIO Port A Bit 12 Data Register 0x230 read-write n 0x0 0x0 GPIOA13 GPIOA13 GPIO Port A Bit 13 Data Register 0x234 read-write n 0x0 0x0 GPIOA14 GPIOA14 GPIO Port A Bit 14 Data Register 0x238 read-write n 0x0 0x0 GPIOA15 GPIOA15 GPIO Port A Bit 15 Data Register 0x23C read-write n 0x0 0x0 GPIOA2 GPIOA2 GPIO Port A Bit 2 Data Register 0x208 read-write n 0x0 0x0 GPIOA3 GPIOA3 GPIO Port A Bit 3 Data Register 0x20C read-write n 0x0 0x0 GPIOA4 GPIOA4 GPIO Port A Bit 4 Data Register 0x210 read-write n 0x0 0x0 GPIOA5 GPIOA5 GPIO Port A Bit 5 Data Register 0x214 read-write n 0x0 0x0 GPIOA6 GPIOA6 GPIO Port A Bit 6 Data Register 0x218 read-write n 0x0 0x0 GPIOA7 GPIOA7 GPIO Port A Bit 7 Data Register 0x21C read-write n 0x0 0x0 GPIOA8 GPIOA8 GPIO Port A Bit 8 Data Register 0x220 read-write n 0x0 0x0 GPIOA9 GPIOA9 GPIO Port A Bit 9 Data Register 0x224 read-write n 0x0 0x0 GPIOA_DBEN GPIOA_DBEN GPIO Port A De-bounce Enable Register 0x14 read-write n 0x0 0x0 DBEN0 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 0 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN1 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 1 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN10 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 10 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN11 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 11 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN12 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 12 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN13 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 13 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN14 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 14 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN15 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 15 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN2 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 2 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN3 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 3 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN4 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 4 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN5 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 5 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN6 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 6 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN7 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 7 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN8 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 8 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 DBEN9 GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved. 9 1 read-write 0 The GPIO port [x] Pin [n] input signal de-bounce function is disabled #0 1 The GPIO port [x] Pin [n] input signal de-bounce function is enabled #1 GPIOA_DMASK GPIOA_DMASK GPIO Port A Data Output Write Mask Register 0xC read-write n 0x0 0x0 DMASK0 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 0 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK1 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 1 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK10 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 10 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK11 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 11 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK12 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 12 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK13 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 13 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK14 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 14 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK15 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 15 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK2 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 2 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK3 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 3 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK4 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 4 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK5 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 5 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK6 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 6 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK7 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 7 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK8 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 8 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 DMASK9 GPIO Port [X] Pin [N] Data Output Write Mask These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored Note: For GPIOF_DMASK, bits [15:6] are reserved. Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect. 9 1 read-write 0 the corresponding GPIO_DOUT bit [n] can be updated #0 1 the corresponding GPIO_DOUT bit [n] is protected #1 GPIOA_DOUT GPIOA_DOUT GPIO Port A Data Output Value Register 0x8 -1 read-write n 0x0 0x0 DOUT0 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 0 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT1 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 1 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT10 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 10 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT11 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 11 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT12 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 12 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT13 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 13 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT14 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 14 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT15 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 15 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT2 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 2 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT3 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 3 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT4 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 4 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT5 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 5 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT6 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 6 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT7 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 7 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT8 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 8 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 DOUT9 GPIO Port [X] Pin [N] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPIO pin is configures as output or open-drain mode\nNote: \nFor GPIOC_OFFD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_OFFD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_OFFD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_DOUT, bits [15:2] are reserved. 9 1 read-write 0 GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set #0 1 GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set #1 GPIOA_IER GPIOA_IER GPIO Port A Interrupt Enable Register 0x1C read-write n 0x0 0x0 FIER0 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 0 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER1 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 1 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER10 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 10 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER11 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 11 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER12 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 12 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER13 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 13 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER14 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 14 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER15 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 15 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER2 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 2 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER3 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 3 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER4 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 4 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER5 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 5 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER6 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 6 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER7 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 7 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER8 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 8 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 FIER9 GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved. 9 1 read-write 0 PIN[n] state low-level or high-to-low change interrupt Disabled #0 1 PIN[n] state low-level or high-to-low change interrupt Enabled #1 RIER0 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 16 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER1 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 17 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER10 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 26 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER11 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 27 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER12 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 28 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER13 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 29 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER14 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 30 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER15 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 31 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER2 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 18 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER3 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 19 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER4 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 20 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER5 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 21 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER6 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 22 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER7 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 23 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER8 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 24 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 RIER9 GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved. 25 1 read-write 0 PIN[n] level-high or low-to-high interrupt Disabled #0 1 PIN[n] level-high or low-to-high interrupt Enabled #1 GPIOA_IMD GPIOA_IMD GPIO Port A Interrupt Mode Control Register 0x18 read-write n 0x0 0x0 IMD0 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 0 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD1 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 1 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD10 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 10 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD11 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 11 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD12 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 12 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD13 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 13 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD14 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 14 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD15 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 15 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD2 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 2 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD3 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 3 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD4 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 4 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD5 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 5 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD6 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 6 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD7 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 7 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD8 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 8 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 IMD9 GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved. 9 1 read-write 0 Edge trigger interrupt #0 1 Level trigger interrupt #1 GPIOA_ISRC GPIOA_ISRC GPIO Port A Interrupt Trigger Source Status Register 0x20 read-write n 0x0 0x0 ISRC0 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 0 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC1 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 1 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC10 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 10 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC11 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 11 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC12 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 12 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC13 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 13 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC14 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 14 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC15 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 15 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC2 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 2 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC3 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 3 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC4 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 4 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC5 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 5 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC6 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 6 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC7 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 7 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC8 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 8 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 ISRC9 GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved. 9 1 read-write 0 No interrupt at Port x[n].\nNo action #0 1 Port x[n] generate an interrupt.\nClear the correspond pending interrupt #1 GPIOA_OFFD GPIOA_OFFD GPIO Port A Pin OFF Digital Enable Register 0x4 read-write n 0x0 0x0 OFFD0 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 16 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD1 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 17 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD10 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 26 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD11 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 27 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD12 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 28 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD13 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 29 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD14 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 30 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD15 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 31 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD2 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 18 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD3 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 19 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD4 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 20 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD5 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 21 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD6 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 22 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD7 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 23 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD8 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 24 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 OFFD9 GPIO Port [X] Pin [N] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: \nFor GPIOC_OFFD, bits [21:20] and [29:28] are reserved.\nFor GPIOD_OFFD, bits [21:16] and [29:24] are reserved.\nFor GPIOE_OFFD, bits [20:16] and [31:22] are reserved.\nFor GPIOF_OFFD, bits [31:18] are reserved. 25 1 read-write 0 digital input path of GPIO port [x] pin [n] Enabled #0 1 digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low) #1 GPIOA_PIN GPIOA_PIN GPIO Port A Pin Value Register 0x10 read-only n 0x0 0x0 PIN0 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 0 1 read-only PIN1 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 1 1 read-only PIN10 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 10 1 read-only PIN11 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 11 1 read-only PIN12 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 12 1 read-only PIN13 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 13 1 read-only PIN14 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 14 1 read-only PIN15 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 15 1 read-only PIN2 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 2 1 read-only PIN3 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 3 1 read-only PIN4 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 4 1 read-only PIN5 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 5 1 read-only PIN6 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 6 1 read-only PIN7 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 7 1 read-only PIN8 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 8 1 read-only PIN9 GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved. 9 1 read-only GPIOA_PMD GPIOA_PMD GPIO Port A Pin I/O Mode Control Register 0x0 read-write n 0x0 0x0 PMD0 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 0 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD1 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 2 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD10 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 20 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD11 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 22 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD12 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 24 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD13 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 26 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD14 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 28 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD15 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 30 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD2 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 4 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD3 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 6 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD4 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 8 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD5 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 10 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD6 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 12 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD7 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 14 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD8 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 16 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 PMD9 GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved. 18 2 read-write 0 GPIO port [x] pin [n] is in INPUT mode #00 1 GPIO port [x] pin [n] is in OUTPUT mode #01 2 GPIO port [x] pin [n] is in Open-Drain mode #10 3 Reserved #11 GPIOA_PUEN GPIOA_PUEN GPIO Port A Pull-up Enable Register 0x24 read-write n 0x0 0x0 PUEN0 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 0 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN1 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 1 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN10 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 10 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN11 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 11 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN12 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 12 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN13 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 13 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN14 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 14 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN15 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 15 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN2 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 2 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN3 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 3 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN4 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 4 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN5 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 5 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN6 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 6 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN7 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 7 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN8 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 8 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 PUEN9 GPIO Port [X] Pin [N] Pull-Up Enable Register\nRead :\nNote: \nFor GPIOC_PUEN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PUEN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PUEN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PUEN, bits [15:2] are reserved. 9 1 read-write 0 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled #0 1 GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled #1 GPIOB0 GPIOB0 GPIO Port B Bit 0 Data Register 0x240 read-write n 0x0 0x0 GPIOB1 GPIOB1 GPIO Port B Bit 1 Data Register 0x244 read-write n 0x0 0x0 GPIOB10 GPIOB10 GPIO Port B Bit 10 Data Register 0x268 read-write n 0x0 0x0 GPIOB11 GPIOB11 GPIO Port B Bit 11 Data Register 0x26C read-write n 0x0 0x0 GPIOB12 GPIOB12 GPIO Port B Bit 12 Data Register 0x270 read-write n 0x0 0x0 GPIOB13 GPIOB13 GPIO Port B Bit 13 Data Register 0x274 read-write n 0x0 0x0 GPIOB14 GPIOB14 GPIO Port B Bit 14 Data Register 0x278 read-write n 0x0 0x0 GPIOB15 GPIOB15 GPIO Port B Bit 15 Data Register 0x27C read-write n 0x0 0x0 GPIOB2 GPIOB2 GPIO Port B Bit 2 Data Register 0x248 read-write n 0x0 0x0 GPIOB3 GPIOB3 GPIO Port B Bit 3 Data Register 0x24C read-write n 0x0 0x0 GPIOB4 GPIOB4 GPIO Port B Bit 4 Data Register 0x250 read-write n 0x0 0x0 GPIOB5 GPIOB5 GPIO Port B Bit 5 Data Register 0x254 read-write n 0x0 0x0 GPIOB6 GPIOB6 GPIO Port B Bit 6 Data Register 0x258 read-write n 0x0 0x0 GPIOB7 GPIOB7 GPIO Port B Bit 7 Data Register 0x25C read-write n 0x0 0x0 GPIOB8 GPIOB8 GPIO Port B Bit 8 Data Register 0x260 read-write n 0x0 0x0 GPIOB9 GPIOB9 GPIO Port B Bit 9 Data Register 0x264 read-write n 0x0 0x0 GPIOB_DBEN GPIOB_DBEN GPIO Port B De-bounce Enable Register 0x54 read-write n 0x0 0x0 GPIOB_DMASK GPIOB_DMASK GPIO Port B Data Output Write Mask Register 0x4C read-write n 0x0 0x0 GPIOB_DOUT GPIOB_DOUT GPIO Port B Data Output Value Register 0x48 read-write n 0x0 0x0 GPIOB_IER GPIOB_IER GPIO Port B Interrupt Enable Register 0x5C read-write n 0x0 0x0 GPIOB_IMD GPIOB_IMD GPIO Port B Interrupt Mode Control Register 0x58 read-write n 0x0 0x0 GPIOB_ISRC GPIOB_ISRC GPIO Port B Interrupt Trigger Source Status Register 0x60 read-write n 0x0 0x0 GPIOB_OFFD GPIOB_OFFD GPIO Port B Pin OFF Digital Enable Register 0x44 read-write n 0x0 0x0 GPIOB_PIN GPIOB_PIN GPIO Port B Pin Value Register 0x50 read-write n 0x0 0x0 GPIOB_PMD GPIOB_PMD GPIO Port B Pin I/O Mode Control Register 0x40 read-write n 0x0 0x0 GPIOB_PUEN GPIOB_PUEN GPIO Port B Pull-up Enable Register 0x64 read-write n 0x0 0x0 GPIOC0 GPIOC0 GPIO Port C Bit 0 Data Register 0x280 read-write n 0x0 0x0 GPIOC1 GPIOC1 GPIO Port C Bit 1 Data Register 0x284 read-write n 0x0 0x0 GPIOC10 GPIOC10 GPIO Port C Bit 10 Data Register 0x2A8 read-write n 0x0 0x0 GPIOC11 GPIOC11 GPIO Port C Bit 11 Data Register 0x2AC read-write n 0x0 0x0 GPIOC12 GPIOC12 GPIO Port C Bit 12 Data Register 0x2B0 read-write n 0x0 0x0 GPIOC13 GPIOC13 GPIO Port C Bit 13 Data Register 0x2B4 read-write n 0x0 0x0 GPIOC14 GPIOC14 GPIO Port C Bit 14 Data Register 0x2B8 read-write n 0x0 0x0 GPIOC15 GPIOC15 GPIO Port C Bit 15 Data Register 0x2BC read-write n 0x0 0x0 GPIOC2 GPIOC2 GPIO Port C Bit 2 Data Register 0x288 read-write n 0x0 0x0 GPIOC3 GPIOC3 GPIO Port C Bit 3 Data Register 0x28C read-write n 0x0 0x0 GPIOC4 GPIOC4 GPIO Port C Bit 4 Data Register 0x290 read-write n 0x0 0x0 GPIOC5 GPIOC5 GPIO Port C Bit 5 Data Register 0x294 read-write n 0x0 0x0 GPIOC6 GPIOC6 GPIO Port C Bit 6 Data Register 0x298 read-write n 0x0 0x0 GPIOC7 GPIOC7 GPIO Port C Bit 7 Data Register 0x29C read-write n 0x0 0x0 GPIOC8 GPIOC8 GPIO Port C Bit 8 Data Register 0x2A0 read-write n 0x0 0x0 GPIOC9 GPIOC9 GPIO Port C Bit 9 Data Register 0x2A4 read-write n 0x0 0x0 GPIOC_DBEN GPIOC_DBEN GPIO Port C De-bounce Enable Register 0x94 read-write n 0x0 0x0 GPIOC_DMASK GPIOC_DMASK GPIO Port C Data Output Write Mask Register 0x8C read-write n 0x0 0x0 GPIOC_DOUT GPIOC_DOUT GPIO Port C Data Output Value Register 0x88 read-write n 0x0 0x0 GPIOC_IER GPIOC_IER GPIO Port C Interrupt Enable Register 0x9C read-write n 0x0 0x0 GPIOC_IMD GPIOC_IMD GPIO Port C Interrupt Mode Control Register 0x98 read-write n 0x0 0x0 GPIOC_ISRC GPIOC_ISRC GPIO Port C Interrupt Trigger Source Status Register 0xA0 read-write n 0x0 0x0 GPIOC_OFFD GPIOC_OFFD GPIO Port C Pin OFF Digital Enable Register 0x84 read-write n 0x0 0x0 GPIOC_PIN GPIOC_PIN GPIO Port C Pin Value Register 0x90 read-write n 0x0 0x0 GPIOC_PMD GPIOC_PMD GPIO Port C Pin I/O Mode Control Register 0x80 read-write n 0x0 0x0 GPIOC_PUEN GPIOC_PUEN GPIO Port C Pull-up Enable Register 0xA4 read-write n 0x0 0x0 GPIOD0 GPIOD0 GPIO Port D Bit 0 Data Register 0x2C0 read-write n 0x0 0x0 GPIOD1 GPIOD1 GPIO Port D Bit 1 Data Register 0x2C4 read-write n 0x0 0x0 GPIOD10 GPIOD10 GPIO Port D Bit 10 Data Register 0x2E8 read-write n 0x0 0x0 GPIOD11 GPIOD11 GPIO Port D Bit 11 Data Register 0x2EC read-write n 0x0 0x0 GPIOD12 GPIOD12 GPIO Port D Bit 12 Data Register 0x2F0 read-write n 0x0 0x0 GPIOD13 GPIOD13 GPIO Port D Bit 13 Data Register 0x2F4 read-write n 0x0 0x0 GPIOD14 GPIOD14 GPIO Port D Bit 14 Data Register 0x2F8 read-write n 0x0 0x0 GPIOD15 GPIOD15 GPIO Port D Bit 15 Data Register 0x2FC read-write n 0x0 0x0 GPIOD2 GPIOD2 GPIO Port D Bit 2 Data Register 0x2C8 read-write n 0x0 0x0 GPIOD3 GPIOD3 GPIO Port D Bit 3 Data Register 0x2CC read-write n 0x0 0x0 GPIOD4 GPIOD4 GPIO Port D Bit 4 Data Register 0x2D0 read-write n 0x0 0x0 GPIOD5 GPIOD5 GPIO Port D Bit 5 Data Register 0x2D4 read-write n 0x0 0x0 GPIOD6 GPIOD6 GPIO Port D Bit 6 Data Register 0x2D8 read-write n 0x0 0x0 GPIOD7 GPIOD7 GPIO Port D Bit 7 Data Register 0x2DC read-write n 0x0 0x0 GPIOD8 GPIOD8 GPIO Port D Bit 8 Data Register 0x2E0 read-write n 0x0 0x0 GPIOD9 GPIOD9 GPIO Port D Bit 9 Data Register 0x2E4 read-write n 0x0 0x0 GPIOD_DBEN GPIOD_DBEN GPIO Port D De-bounce Enable Register 0xD4 read-write n 0x0 0x0 GPIOD_DMASK GPIOD_DMASK GPIO Port D Data Output Write Mask Register 0xCC read-write n 0x0 0x0 GPIOD_DOUT GPIOD_DOUT GPIO Port D Data Output Value Register 0xC8 read-write n 0x0 0x0 GPIOD_IER GPIOD_IER GPIO Port D Interrupt Enable Register 0xDC read-write n 0x0 0x0 GPIOD_IMD GPIOD_IMD GPIO Port D Interrupt Mode Control Register 0xD8 read-write n 0x0 0x0 GPIOD_ISRC GPIOD_ISRC GPIO Port D Interrupt Trigger Source Status Register 0xE0 read-write n 0x0 0x0 GPIOD_OFFD GPIOD_OFFD GPIO Port D Pin OFF Digital Enable Register 0xC4 read-write n 0x0 0x0 GPIOD_PIN GPIOD_PIN GPIO Port D Pin Value Register 0xD0 read-write n 0x0 0x0 GPIOD_PMD GPIOD_PMD GPIO Port D Pin I/O Mode Control Register 0xC0 read-write n 0x0 0x0 GPIOD_PUEN GPIOD_PUEN GPIO Port D Pull-up Enable Register 0xE4 read-write n 0x0 0x0 GPIOE0 GPIOE0 GPIO Port E Bit 0 Data Register 0x300 read-write n 0x0 0x0 GPIOE1 GPIOE1 GPIO Port E Bit 1 Data Register 0x304 read-write n 0x0 0x0 GPIOE10 GPIOE10 GPIO Port E Bit 10 Data Register 0x328 read-write n 0x0 0x0 GPIOE11 GPIOE11 GPIO Port E Bit 11 Data Register 0x32C read-write n 0x0 0x0 GPIOE12 GPIOE12 GPIO Port E Bit 12 Data Register 0x330 read-write n 0x0 0x0 GPIOE13 GPIOE13 GPIO Port E Bit 13 Data Register 0x334 read-write n 0x0 0x0 GPIOE14 GPIOE14 GPIO Port E Bit 14 Data Register 0x338 read-write n 0x0 0x0 GPIOE15 GPIOE15 GPIO Port E Bit 15 Data Register 0x33C read-write n 0x0 0x0 GPIOE2 GPIOE2 GPIO Port E Bit 2 Data Register 0x308 read-write n 0x0 0x0 GPIOE3 GPIOE3 GPIO Port E Bit 3 Data Register 0x30C read-write n 0x0 0x0 GPIOE4 GPIOE4 GPIO Port E Bit 4 Data Register 0x310 read-write n 0x0 0x0 GPIOE5 GPIOE5 GPIO Port E Bit 5 Data Register 0x314 read-write n 0x0 0x0 GPIOE6 GPIOE6 GPIO Port E Bit 6 Data Register 0x318 read-write n 0x0 0x0 GPIOE7 GPIOE7 GPIO Port E Bit 7 Data Register 0x31C read-write n 0x0 0x0 GPIOE8 GPIOE8 GPIO Port E Bit 8 Data Register 0x320 read-write n 0x0 0x0 GPIOE9 GPIOE9 GPIO Port E Bit 9 Data Register 0x324 read-write n 0x0 0x0 GPIOE_DBEN GPIOE_DBEN GPIO Port E De-bounce Enable Register 0x114 read-write n 0x0 0x0 GPIOE_DMASK GPIOE_DMASK GPIO Port E Data Output Write Mask Register 0x10C read-write n 0x0 0x0 GPIOE_DOUT GPIOE_DOUT GPIO Port E Data Output Value Register 0x108 read-write n 0x0 0x0 GPIOE_IER GPIOE_IER GPIO Port E Interrupt Enable Register 0x11C read-write n 0x0 0x0 GPIOE_IMD GPIOE_IMD GPIO Port E Interrupt Mode Control Register 0x118 read-write n 0x0 0x0 GPIOE_ISRC GPIOE_ISRC GPIO Port E Interrupt Trigger Source Status Register 0x120 read-write n 0x0 0x0 GPIOE_OFFD GPIOE_OFFD GPIO Port E Pin OFF Digital Enable Register 0x104 read-write n 0x0 0x0 GPIOE_PIN GPIOE_PIN GPIO Port E Pin Value Register 0x110 read-write n 0x0 0x0 GPIOE_PMD GPIOE_PMD GPIO Port E Pin I/O Mode Control Register 0x100 read-write n 0x0 0x0 GPIOE_PUEN GPIOE_PUEN GPIO Port E Pull-up Enable Register 0x124 read-write n 0x0 0x0 GPIOF0 GPIOF0 GPIO Port F Bit 0 Data Register 0x340 read-write n 0x0 0x0 GPIOF1 GPIOF1 GPIO Port F Bit 1 Data Register 0x344 read-write n 0x0 0x0 GPIOF2 GPIOF2 GPIO Port F Bit 2 Data Register 0x348 read-write n 0x0 0x0 GPIOF3 GPIOF3 GPIO Port F Bit 3 Data Register 0x34C read-write n 0x0 0x0 GPIOF4 GPIOF4 GPIO Port F Bit 4 Data Register 0x350 read-write n 0x0 0x0 GPIOF5 GPIOF5 GPIO Port F Bit 5 Data Register 0x354 read-write n 0x0 0x0 GPIOF_DBEN GPIOF_DBEN GPIO Port F De-bounce Enable Register 0x154 read-write n 0x0 0x0 GPIOF_DMASK GPIOF_DMASK GPIO Port F Data Output Write Mask Register 0x14C read-write n 0x0 0x0 GPIOF_DOUT GPIOF_DOUT GPIO Port F Data Output Value Register 0x148 read-write n 0x0 0x0 GPIOF_IER GPIOF_IER GPIO Port F Interrupt Enable Register 0x15C read-write n 0x0 0x0 GPIOF_IMD GPIOF_IMD GPIO Port F Interrupt Mode Control Register 0x158 read-write n 0x0 0x0 GPIOF_ISRC GPIOF_ISRC GPIO Port F Interrupt Trigger Source Status Register 0x160 read-write n 0x0 0x0 GPIOF_OFFD GPIOF_OFFD GPIO Port F Pin OFF Digital Enable Register 0x144 read-write n 0x0 0x0 GPIOF_PIN GPIOF_PIN GPIO Port F Pin Value Register 0x150 read-write n 0x0 0x0 GPIOF_PMD GPIOF_PMD GPIO Port F Pin I/O Mode Control Register 0x140 read-write n 0x0 0x0 GPIOF_PUEN GPIOF_PUEN GPIO Port F Pull-up Enable Register 0x164 read-write n 0x0 0x0 I2C0 I2C Register Map I2C 0x0 0x0 0x20 registers n 0x28 0x8 registers n I2CDATA I2CDATA I2C DATA Register 0x14 read-write n 0x0 0x0 DATA I2C Data Bits\nThe DATA contains a byte of serial data to be transmitted or a byte which has just been received. \nNote: Refer to Data register section for more detail information. 0 8 read-write I2CDIV I2CDIV I2C Clock Divided Register 0xC read-write n 0x0 0x0 CLK_DIV I2C Clock Divided Bits\nNote: the minimum value of CLK_DIV is 4. 0 8 read-write I2CINTSTS I2CINTSTS I2C Interrupt Status Register 0x4 read-write n 0x0 0x0 INTSTS I2C STATUS's Interrupt Status\n 0 1 read-write 0 No bus event occurred #0 1 New state is presented in the I2CSTATUS. Software can write 1 to cleat this bit #1 TIF Time-Out Status\n 1 1 read-write 0 No Time-out flag. Software can cleat this flag #0 1 Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set #1 I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 ACK Assert Acknowledge Control Bit\n 1 1 read-write 0 When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse #0 1 When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when (a). A slave is acknowledging the address sent from master. (b). The receiver devices are acknowledging the data sent by transmitter #1 I2C_STS I2C Status\nWhen a new state is present in the I2CSTATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.\n 4 1 read-write 0 I2C's Status disabled and the I2C protocol function will go ahead #0 1 I2C's Status active #1 INTEN Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 IPEN I2C Function Enable Control\n 0 1 read-write 0 I2C function Disabled #0 1 I2C function Enabled #1 START I2C START Command\nSetting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.\n 3 1 read-write 0 After START or repeat START is active #0 1 Sends a START or repeat START condition to bus #1 STOP I2C STOP Control Bit In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically. In Slave mode, set this bit to 1 to reset the controller to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 2 1 read-write 0 Will be cleared by hardware automatically if a STOP condition is detected #0 1 Sends a STOP condition to bus in Master mode or reset the controller to not addressed in Slave mode #1 I2CSADDR0 I2CSADDR0 Slave Address Register 0 0x18 read-write n 0x0 0x0 GCALL General Call Function \nNote: Refer to Address Register section for more detail information.. 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 SADDR I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched. 1 7 read-write I2CSADDR1 I2CSADDR1 Slave Address Register 1 0x1C read-write n 0x0 0x0 I2CSAMASK0 I2CSAMASK0 Slave Address Mask Register 0 0x28 read-write n 0x0 0x0 SAMASK I2C Slave Address Mask Bits\n 1 7 read-write 0 Mask disable (the received corresponding register bit should be exact the same as address register) 0 1 Mask enable (the received corresponding address bit is don't care). 1 I2CSAMASK1 I2CSAMASK1 Slave Address Mask Register 1 0x2C read-write n 0x0 0x0 I2CSTATUS I2CSTATUS I2C Status Register 0x8 -1 read-only n 0x0 0x0 STATUS I2C Status Bits (Read Only)\nIndicates the current status code of the bus information. The detail information about the status is described in the sections of I2C protocol register and operation mode. 0 8 read-only I2CTOUT I2CTOUT I2C Time Out Counter Register 0x10 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock Divider By 4 \nWhen Enabled, the time-out period is extended 4 times. 1 1 read-write 0 Disabled #0 1 Enabled #1 TOUTEN Time-Out Counter Enable/Disable Control\nWhen set this bit to enable, the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after INTSTS is cleared. 0 1 read-write 0 Disabled #0 1 Enabled #1 I2C1 I2C Register Map I2C 0x0 0x0 0x20 registers n 0x28 0x8 registers n I2CDATA I2CDATA I2C DATA Register 0x14 read-write n 0x0 0x0 DATA I2C Data Bits\nThe DATA contains a byte of serial data to be transmitted or a byte which has just been received. \nNote: Refer to Data register section for more detail information. 0 8 read-write I2CDIV I2CDIV I2C Clock Divided Register 0xC read-write n 0x0 0x0 CLK_DIV I2C Clock Divided Bits\nNote: the minimum value of CLK_DIV is 4. 0 8 read-write I2CINTSTS I2CINTSTS I2C Interrupt Status Register 0x4 read-write n 0x0 0x0 INTSTS I2C STATUS's Interrupt Status\n 0 1 read-write 0 No bus event occurred #0 1 New state is presented in the I2CSTATUS. Software can write 1 to cleat this bit #1 TIF Time-Out Status\n 1 1 read-write 0 No Time-out flag. Software can cleat this flag #0 1 Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set #1 I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 ACK Assert Acknowledge Control Bit\n 1 1 read-write 0 When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse #0 1 When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when (a). A slave is acknowledging the address sent from master. (b). The receiver devices are acknowledging the data sent by transmitter #1 I2C_STS I2C Status\nWhen a new state is present in the I2CSTATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.\n 4 1 read-write 0 I2C's Status disabled and the I2C protocol function will go ahead #0 1 I2C's Status active #1 INTEN Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 IPEN I2C Function Enable Control\n 0 1 read-write 0 I2C function Disabled #0 1 I2C function Enabled #1 START I2C START Command\nSetting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.\n 3 1 read-write 0 After START or repeat START is active #0 1 Sends a START or repeat START condition to bus #1 STOP I2C STOP Control Bit In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically. In Slave mode, set this bit to 1 to reset the controller to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 2 1 read-write 0 Will be cleared by hardware automatically if a STOP condition is detected #0 1 Sends a STOP condition to bus in Master mode or reset the controller to not addressed in Slave mode #1 I2CSADDR0 I2CSADDR0 Slave Address Register 0 0x18 read-write n 0x0 0x0 GCALL General Call Function \nNote: Refer to Address Register section for more detail information.. 0 1 read-write 0 General Call Function Disabled #0 1 General Call Function Enabled #1 SADDR I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched. 1 7 read-write I2CSADDR1 I2CSADDR1 Slave Address Register 1 0x1C read-write n 0x0 0x0 I2CSAMASK0 I2CSAMASK0 Slave Address Mask Register 0 0x28 read-write n 0x0 0x0 SAMASK I2C Slave Address Mask Bits\n 1 7 read-write 0 Mask disable (the received corresponding register bit should be exact the same as address register) 0 1 Mask enable (the received corresponding address bit is don't care) 1 I2CSAMASK1 I2CSAMASK1 Slave Address Mask Register 1 0x2C read-write n 0x0 0x0 I2CSTATUS I2CSTATUS I2C Status Register 0x8 -1 read-only n 0x0 0x0 STATUS I2C Status Bits (Read Only)\nIndicates the current status code of the bus information. The detail information about the status is described in the sections of I2C protocol register and operation mode. 0 8 read-only I2CTOUT I2CTOUT I2C Time Out Counter Register 0x10 read-write n 0x0 0x0 DIV4 Time-Out Counter Input Clock Divider By 4 \nWhen Enabled, the time-out period is extended 4 times. 1 1 read-write 0 Disabled #0 1 Enabled #1 TOUTEN Time-Out Counter Enable/Disable Control\nWhen set this bit to enable, the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after INTSTS is cleared. 0 1 read-write 0 Disabled #0 1 Enabled #1 I2S I2S Register Map I2S 0x0 0x0 0x18 registers n CLKDIV I2S_CLKDIV I2S Clock Divider Register 0x4 read-write n 0x0 0x0 BCLK_DIV Bit Clock Divider\nIf I2S is operated in Master mode, bit clock is provided by this chip. Software can program these bits to generate sampling rate clock frequency.\n 8 8 read-write MCLK_DIV Master Clock Divider If the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip. If MCLK_DIV is set to 0 , MCLK is the same as external clock input. 0 3 read-write CTRL I2S_CTRL I2S Control Register 0x0 read-write n 0x0 0x0 CLR_RXFIFO Clear Receiving FIFO Write 1 to clear receiving FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty. This bit is cleared by hardware automatically, and read it return zero. 19 1 read-write CLR_TXFIFO Clear Transmit FIFO Write 1 to clear transmitting FIFO, internal pointer is reset to FIFO start point, TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed. This bit is clear by hardware automatically, read it return zero. 18 1 read-write FORMAT Data Format Selection\n 7 1 read-write 0 I2S data format #0 1 MSB justified data format #1 I2SEN I2S Controller Enable\n 0 1 read-write 0 Disabled #0 1 Enabled #1 LCHZCEN Left Channel Zero Cross Detect Enable If this bit is set to 1 , when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1 . It works on transmitting mode only. 17 1 read-write 0 Left channel zero cross detection Disabled #0 1 Left channel zero cross detection Enabled #1 MCLKEN Master Clock Enable\nEnable master MCLK timing output to the external audio codec device. The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register.\n 15 1 read-write 0 Master Clock Disabled #0 1 Master Clock Enabled #1 MONO Monaural Data Selection\n 6 1 read-write 0 Data is stereo format #0 1 Data is monaural format and gets the right channel data from I2S bus when this mode is enabled #1 MUTE Transmitting Mute Enable\n 3 1 read-write 0 Transmit data in buffer to channel #0 1 Transmit '0' to channel #1 RCHZCEN Right Channel Zero Cross Detect Enable If this bit is set to 1 , when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to 1 . It works on transmitting mode only. 16 1 read-write 0 Right channel zero cross detection Disabled #0 1 Right channel zero cross detection Enabled #1 RXDMA Enable Receive DMA\nWhen RX DMA is enabled, I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty.\n 21 1 read-write 0 RX DMA Disabled #0 1 RX DMA Enabled #1 RXEN Receive Enable\n 2 1 read-write 0 Data receiving Disabled #0 1 Data receiving Enabled #1 RXTH Receiving FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n 12 3 read-write 0 1 word data in receiving FIFO 0x0 1 2 words data in receiving FIFO 0x1 2 3 words data in receiving FIFO 0x2 3 4 words data in receiving FIFO 0x3 4 5 words data in receiving FIFO 0x4 5 6 words data in receiving FIFO 0x5 6 7 words data in receiving FIFO 0x6 7 8 words data in receiving FIFO 0x7 SLAVE Slave Mode Selection\nI2S can operate as master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC. When act as Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from the outer audio CODEC chip.\n 8 1 read-write 0 Master mode #0 1 Slave mode #1 TXDMA Enable Transmit DMA\nWhen TX DMA is enabled, I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full\n 20 1 read-write 0 TX DMA Disabled #0 1 TX DMA Enabled #1 TXEN Transmit Enable\n 1 1 read-write 0 Data transmitting Disabled #0 1 Data transmitting Enabled #1 TXTH Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set.\n 9 3 read-write 0 1 word data in transmitting FIFO 0x0 1 2 words data in transmitting FIFO 0x1 2 3 words data in transmitting FIFO 0x2 3 4 words data in transmitting FIFO 0x3 4 5 words data in transmitting FIFO 0x4 5 6 words data in transmitting FIFO 0x5 6 7 words data in transmitting FIFO 0x6 7 8 words data in transmitting FIFO 0x7 WORDWIDTH Word Width \nThis bit field indicates the bit-width of data word.\n 4 2 read-write 0 data word is 8-bit 0x0 1 data word is 16-bit 0x1 2 data word is 24-bit 0x2 3 data word is 32-bit 0x3 INTEN I2S_INTEN I2S Interrupt Enable Register 0x8 read-write n 0x0 0x0 LZCIE Left Channel Zero Cross Interrupt Enable Interrupt occurs if this bit is set to 1 and left channel is zero crossing. 12 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXOVFIE Receiving FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and receiving FIFO overflow flag is set to 1 1 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXTHIE Receiving FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in receiving FIFO is less than RXTH[2:0]. 2 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXUDFIE Receiving FIFO Underflow Interrupt Enable Interrupt occurs if this bit is set to 1 and receiving FIFO underflow flag is set to 1 . 0 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RZCIE Right Channel Zero Cross Interrupt Enable Interrupt occurs if this bit is set to 1 and right channel is zero crossing. 11 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXOVFIE Transmitting FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmitting FIFO overflow flag is set to 1 9 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXTHIE Transmitting FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in transmitting FIFO is less than TXTH[2:0]. 10 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 TXUDFIE Transmitting FIFO Underflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmitting FIFO underflow flag is set to 1 . 8 1 read-write 0 Interrupt Disabled #0 1 Interrupt Enabled #1 RXFIFO I2S_RXFIFO I2S Receive FIFO Register 0x14 read-only n 0x0 0x0 RXFIFO Receiving FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data receiving. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register. This register is read only. 0 32 read-only STATUS I2S_STATUS I2S Status Register 0xC -1 read-write n 0x0 0x0 I2SINT I2S Interrupt Flag\nNote: This bit is read only and it is wire-OR of I2STXINT and I2SRXINT bits. 0 1 read-write 0 No I2S interrupt #0 1 I2S interrupt occurs #1 I2SRXINT I2S Receiving Interrupt\nNote: This bit is read only 1 1 read-write 0 No receiving interrupt occurs #0 1 Receiving interrupt occurs #1 I2STXINT I2S Transmit Interrupt\nNote: This bit is read only 2 1 read-write 0 No transmit interrupt occurs #0 1 Transmit interrupt occurs #1 LZCF Left Channel Zero Cross Flag \nIt indicates the next sample data sign bit of left channel is changed or all data bits are zero.\nNote: This bit is cleared by writing 1. 23 1 read-write 0 No zero cross #0 1 Left channel zero cross is detected #1 RIGHT Right Channel\nThis bit indicates the current transmitting data is belong to right channel\nNote: This bit is read only 3 1 read-write 0 Left channel #0 1 Right channel #1 RXEMPTY Receiving FIFO Empty\nThis bit reflect data word number in the receiving FIFO is zero\nNote: This bit is read only. 12 1 read-write 0 Empty #0 1 Not empty #1 RXFULL Receiving FIFO Full\nThis bit reflect data word number in the receiving FIFO is 8\nNote: This bit is read only 11 1 read-write 0 Full #0 1 Not full #1 RXOVF Receiving FIFO Overflow Flag When the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to 1 . Data in 1st buffer is overwritten. Note: This bit is cleared by writing 1. 9 1 read-write 0 No overflow occur #0 1 Overflow occurs #1 RXTHF Receiving FIFO Threshold Flag When data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0], the RXTHF bit becomes to 1 . It keeps at 1 till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from the RXFIFO register. Note: This bit is read only 10 1 read-write 0 Data word(s) in receiving FIFO is lower than threshold level #0 1 Data word(s) in receiving FIFO is equal to or higher than threshold level #1 RXUDF Receiving FIFO Underflow Flag Read the receiving FIFO when it is empty, this bit set to 1 indicate underflow occur. Note: This bit is cleared by writing 1. 8 1 read-write 0 No underflow occur #0 1 Underflow occurs #1 RX_LEVEL Receive FIFO Level\nThese bits indicate the number of data word(s) in the receiving FIFO.\n 24 4 read-write 0 No data in the receiving FIFO 0x0 1 1 word in the receiving FIFO 0x1 2 2 words in the receiving FIFO 0x2 8 8 words in the receiving FIFO 0x8 RZCF Right Channel Zero Cross Flag \nIt indicates the data sign of right channel next sample data is changed or all data bits are zero.\nNote: This bit is cleared by writing 1. 22 1 read-write 0 No zero cross #0 1 Right channel zero cross is detected #1 TXBUSY Transmitting Busy\nThis bit is clear to 0 when all data in the transmitting FIFO and shift buffer is shifted out. Set this bit to 1 when 1st data is loading to shift buffer. \nNote: This bit is read only. 21 1 read-write 0 Transmit shift buffer is empty #0 1 Transmit shift buffer is busy #1 TXEMPTY Transmitting FIFO Empty\nThis bit reflect data word number in the transmitting FIFO is zero\nNote: This bit is read only. 20 1 read-write 0 Empty #0 1 Not empty #1 TXFULL Transmitting FIFO Full\nThis bit reflect data word number in the transmitting FIFO is 8\nNote: This bit is read only 19 1 read-write 0 Full #0 1 Not full #1 TXOVF Transmit FIFO Overflow Flag Write data to the transmitting FIFO when it is full and this bit will set to 1 Note: This bit is cleared by writing 1. 17 1 read-write 0 No overflow #0 1 Overflow #1 TXTHF Transmitting FIFO Threshold Flag When data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0],the TXTHF bit becomes to 1 . It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes data into the TXFIFO register. Note: This bit is read only 18 1 read-write 0 Data word(s) in transmitting FIFO is higher than threshold level #0 1 Data word(s) in transmitting FIFO is equal or lower than threshold level #1 TXUDF Transmitting FIFO Underflow Flag When the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to 1 . Note: This bit is cleared by writing 1. 16 1 read-write 0 No underflow #0 1 Underflow #1 TX_LEVEL Transmitting FIFO Level\nThese bits indicate the number of data word(s) in the transmitting FIFO.\n 28 4 read-write 0 No data in the transmitting FIFO 0x0 1 1 word in the transmitting FIFO 0x1 2 2 words in the transmitting FIFO 0x2 8 8 words in the transmitting FIFO 0x8 TXFIFO I2S_TXFIFO I2S Transmit FIFO Register 0x10 write-only n 0x0 0x0 TXFIFO Transmitting FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data transmitting. Write data to this register in order to prepare data for transmitting. The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS register. This register is write only. 0 32 write-only INT SCS Register Map SCS 0x0 0x0 0x88 registers n IRQ0_SRC IRQ0_SRC MCU IRQ0 (BOD_INT) Interrupt Source Identify 0x0 read-only n 0x0 0x0 INT_SRC Interrupt Source\nDefine the interrupt sources for interrupt event. 0 4 read-only IRQ10_SRC IRQ10_SRC MCU IRQ10 (TMR2_INT) Interrupt Source Identify 0x28 read-write n 0x0 0x0 IRQ11_SRC IRQ11_SRC MCU IRQ11 (TMR3_INT) Interrupt Source Identify 0x2C read-write n 0x0 0x0 IRQ12_SRC IRQ12_SRC MCU IRQ12 (UART0_INT) Interrupt Source Identify 0x30 read-write n 0x0 0x0 IRQ13_SRC IRQ13_SRC MCU IRQ13 (UART1_INT) Interrupt Source Identify 0x34 read-write n 0x0 0x0 IRQ14_SRC IRQ14_SRC MCU IRQ14 (SPI0_INT) Interrupt Source Identify 0x38 read-write n 0x0 0x0 IRQ15_SRC IRQ15_SRC MCU IRQ15 (SPI1_INT) Interrupt Source Identify 0x3C read-write n 0x0 0x0 IRQ16_SRC IRQ16_SRC MCU IRQ16 (SPI2_INT) Interrupt Source Identify 0x40 read-write n 0x0 0x0 IRQ17_SRC IRQ17_SRC MCU IRQ17 (IRC_INT) Interrupt Source Identify 0x44 read-write n 0x0 0x0 IRQ18_SRC IRQ18_SRC MCU IRQ18 (I2C0_INT) Interrupt Source Identify 0x48 read-write n 0x0 0x0 IRQ19_SRC IRQ19_SRC MCU IRQ19 (I2C1_INT) Interrupt Source Identify 0x4C read-write n 0x0 0x0 IRQ1_SRC IRQ1_SRC MCU IRQ1 (WDT_INT) Interrupt Source Identify 0x4 read-write n 0x0 0x0 IRQ20_SRC IRQ20_SRC MCU IRQ20 (Reserved) Interrupt Source Identify 0x50 read-write n 0x0 0x0 IRQ21_SRC IRQ21_SRC MCU IRQ21 (SC0_INT) Interrupt Source Identify 0x54 read-write n 0x0 0x0 IRQ22_SRC IRQ22_SRC MCU IRQ22 (SC1_INT) Interrupt Source Identify 0x58 read-write n 0x0 0x0 IRQ23_SRC IRQ23_SRC MCU IRQ23 (USB_INT) Interrupt Source Identify 0x5C read-write n 0x0 0x0 IRQ24_SRC IRQ24_SRC Reserved 0x60 read-write n 0x0 0x0 IRQ25_SRC IRQ25_SRC Reserved 0x64 read-write n 0x0 0x0 IRQ26_SRC IRQ26_SRC MCU IRQ26 (DMA_INT) Interrupt Source Identify 0x68 read-write n 0x0 0x0 IRQ27_SRC IRQ27_SRC MCU IRQ27 (I2S_INT) Interrupt Source Identify 0x6C read-write n 0x0 0x0 IRQ28_SRC IRQ28_SRC MCU IRQ28 (PDWU_INT) Interrupt Source Identify 0x70 read-write n 0x0 0x0 IRQ29_SRC IRQ29_SRC MCU IRQ29 (ADC_INT) Interrupt Source Identify 0x74 read-write n 0x0 0x0 IRQ2_SRC IRQ2_SRC MCU IRQ2 (EINT0) Interrupt Source Identify 0x8 read-write n 0x0 0x0 IRQ30_SRC IRQ30_SRC Reserved 0x78 read-write n 0x0 0x0 IRQ31_SRC IRQ31_SRC MCU IRQ31 (RTC_INT) Interrupt Source Identify 0x7C read-write n 0x0 0x0 IRQ3_SRC IRQ3_SRC MCU IRQ3 (EINT1) Interrupt Source Identify 0xC read-write n 0x0 0x0 IRQ4_SRC IRQ4_SRC MCU IRQ4 (GPABC_INT) Interrupt Source Identify 0x10 read-write n 0x0 0x0 IRQ5_SRC IRQ5_SRC MCU IRQ5 (GPDEF_INT) Interrupt Source Identify 0x14 read-write n 0x0 0x0 IRQ6_SRC IRQ6_SRC MCU IRQ6 (PWM0_INT) Interrupt Source Identify 0x18 read-write n 0x0 0x0 IRQ7_SRC IRQ7_SRC MCU IRQ7 (PWM1_INT) Interrupt Source Identify 0x1C read-write n 0x0 0x0 IRQ8_SRC IRQ8_SRC MCU IRQ8 (TMR0_INT) Interrupt Source Identify 0x20 read-write n 0x0 0x0 IRQ9_SRC IRQ9_SRC MCU IRQ9 (TMR1_INT) Interrupt Source Identify 0x24 read-write n 0x0 0x0 MCU_IRQ MCU_IRQ MCU Interrupt Request Source Register 0x84 read-write n 0x0 0x0 MCU_IRQ MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode. When the MCU_IRQ[n] is 0 , set MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 NVIC[n]. When the MCU_IRQ[n] is 1 (mean an interrupt is assert), set the MCU_bit[n] will clear the interrupt Set MCU_IRQ[n] 0 : no any effect 0 32 read-write NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_SEL The NMI Interrupt To Cortex-M0 Can Be Selected From One Of The Interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source 0 5 read-write PDMA_CH1 VDMA Register Map VDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n 0x80 0x4 registers n PDMA_BCR PDMA_BCR PDMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 PDMA_BCR PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n 0 16 read-write PDMA_BUF PDMA_BUF PDMA Internal Buffer FIFO 0x80 read-only n 0x0 0x0 PDMA_BUF PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_CBCR PDMA_CBCR PDMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 PDMA_CBCR PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address). 0 24 read-only PDMA_CDAR PDMA_CDAR PDMA Current Destination Address Register 0x18 read-only n 0x0 0x0 PDMA_CDAR PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Current Source Address Register 0x14 read-only n 0x0 0x0 PDMA_CSAR PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Control Register 0x0 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Transfer Destination Address Direction Selection\n 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to 0, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 MODE_SEL PDMA Mode Selection\n 2 2 read-write 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 3 Reserved #11 PDMACEN PDMA Channel Enable Control Setting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CBCR is equal to 0, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 SW_RST Software Engine Reset\n 1 1 read-write 0 No effect #0 1 Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 TO_EN Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero, the TO_IS will be set.\n 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIG_EN Trigger Enable Control\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channel, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data read or write transfer Enabled #1 PDMA_DAR PDMA_DAR PDMA Destination Address Register 0x8 read-write n 0x0 0x0 PDMA_DAR PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment 0 32 read-write PDMA_IER PDMA_IER PDMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable Control\n 0 1 read-write 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 TD_IE PDMA Transfer Done Interrupt Enable Control\n 1 1 read-write 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 TO_IE Time-Out Interrupt Enable Control\n 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 WRA_BCR_IE Wrap Around Byte Count Interrupt Enable Control\n 2 4 read-write 1 Interrupt enable of PDMA_CBCR equals 0 #0001 4 Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR #0100 PDMA_ISR PDMA_ISR PDMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABORT_IS PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TD_IS Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TO_IS Time-Out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 WRA_BCR_IS Wrap Around Transfer Byte Count Interrupt Status Flag\n 2 4 read-write PDMA_SAR PDMA_SAR PDMA Source Address Register 0x4 read-write n 0x0 0x0 PDMA_SAR PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TCR PDMA_TCR PDMA Timer Counter Setting Register 0x28 read-write n 0x0 0x0 PDMA_TCR PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts counting down when setting TO_EN (PDMA_CSRx[12]). PDMA will request interrupt when this internal counter reaches 0 and TO_IE (PDMA_IERx[6]) is 1. 0 16 read-write PDMA_CH2 VDMA Register Map VDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n 0x80 0x4 registers n PDMA_BCR PDMA_BCR PDMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 PDMA_BCR PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n 0 16 read-write PDMA_BUF PDMA_BUF PDMA Internal Buffer FIFO 0x80 read-only n 0x0 0x0 PDMA_BUF PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_CBCR PDMA_CBCR PDMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 PDMA_CBCR PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address). 0 24 read-only PDMA_CDAR PDMA_CDAR PDMA Current Destination Address Register 0x18 read-only n 0x0 0x0 PDMA_CDAR PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Current Source Address Register 0x14 read-only n 0x0 0x0 PDMA_CSAR PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Control Register 0x0 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Transfer Destination Address Direction Selection\n 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to 0, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 MODE_SEL PDMA Mode Selection\n 2 2 read-write 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 3 Reserved #11 PDMACEN PDMA Channel Enable Control Setting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CBCR is equal to 0, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 SW_RST Software Engine Reset\n 1 1 read-write 0 No effect #0 1 Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 TO_EN Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero, the TO_IS will be set.\n 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIG_EN Trigger Enable Control\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channel, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data read or write transfer Enabled #1 PDMA_DAR PDMA_DAR PDMA Destination Address Register 0x8 read-write n 0x0 0x0 PDMA_DAR PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment 0 32 read-write PDMA_IER PDMA_IER PDMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable Control\n 0 1 read-write 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 TD_IE PDMA Transfer Done Interrupt Enable Control\n 1 1 read-write 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 TO_IE Time-Out Interrupt Enable Control\n 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 WRA_BCR_IE Wrap Around Byte Count Interrupt Enable Control\n 2 4 read-write 1 Interrupt enable of PDMA_CBCR equals 0 #0001 4 Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR #0100 PDMA_ISR PDMA_ISR PDMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABORT_IS PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TD_IS Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TO_IS Time-Out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 WRA_BCR_IS Wrap Around Transfer Byte Count Interrupt Status Flag\n 2 4 read-write PDMA_SAR PDMA_SAR PDMA Source Address Register 0x4 read-write n 0x0 0x0 PDMA_SAR PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TCR PDMA_TCR PDMA Timer Counter Setting Register 0x28 read-write n 0x0 0x0 PDMA_TCR PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts counting down when setting TO_EN (PDMA_CSRx[12]). PDMA will request interrupt when this internal counter reaches 0 and TO_IE (PDMA_IERx[6]) is 1. 0 16 read-write PDMA_CH3 VDMA Register Map VDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n 0x80 0x4 registers n PDMA_BCR PDMA_BCR PDMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 PDMA_BCR PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n 0 16 read-write PDMA_BUF PDMA_BUF PDMA Internal Buffer FIFO 0x80 read-only n 0x0 0x0 PDMA_BUF PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_CBCR PDMA_CBCR PDMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 PDMA_CBCR PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address). 0 24 read-only PDMA_CDAR PDMA_CDAR PDMA Current Destination Address Register 0x18 read-only n 0x0 0x0 PDMA_CDAR PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Current Source Address Register 0x14 read-only n 0x0 0x0 PDMA_CSAR PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Control Register 0x0 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Transfer Destination Address Direction Selection\n 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to 0, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 MODE_SEL PDMA Mode Selection\n 2 2 read-write 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 3 Reserved #11 PDMACEN PDMA Channel Enable Control Setting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CBCR is equal to 0, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 SW_RST Software Engine Reset\n 1 1 read-write 0 No effect #0 1 Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 TO_EN Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero, the TO_IS will be set.\n 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIG_EN Trigger Enable Control\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channel, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data read or write transfer Enabled #1 PDMA_DAR PDMA_DAR PDMA Destination Address Register 0x8 read-write n 0x0 0x0 PDMA_DAR PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment 0 32 read-write PDMA_IER PDMA_IER PDMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable Control\n 0 1 read-write 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 TD_IE PDMA Transfer Done Interrupt Enable Control\n 1 1 read-write 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 TO_IE Time-Out Interrupt Enable Control\n 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 WRA_BCR_IE Wrap Around Byte Count Interrupt Enable Control\n 2 4 read-write 1 Interrupt enable of PDMA_CBCR equals 0 #0001 4 Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR #0100 PDMA_ISR PDMA_ISR PDMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABORT_IS PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TD_IS Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TO_IS Time-Out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 WRA_BCR_IS Wrap Around Transfer Byte Count Interrupt Status Flag\n 2 4 read-write PDMA_SAR PDMA_SAR PDMA Source Address Register 0x4 read-write n 0x0 0x0 PDMA_SAR PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TCR PDMA_TCR PDMA Timer Counter Setting Register 0x28 read-write n 0x0 0x0 PDMA_TCR PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts counting down when setting TO_EN (PDMA_CSRx[12]). PDMA will request interrupt when this internal counter reaches 0 and TO_IE (PDMA_IERx[6]) is 1. 0 16 read-write PDMA_CH4 VDMA Register Map VDMA 0x0 0x0 0x10 registers n 0x14 0x18 registers n 0x80 0x4 registers n PDMA_BCR PDMA_BCR PDMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 PDMA_BCR PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n 0 16 read-write PDMA_BUF PDMA_BUF PDMA Internal Buffer FIFO 0x80 read-only n 0x0 0x0 PDMA_BUF PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer. 0 32 read-only PDMA_CBCR PDMA_CBCR PDMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 PDMA_CBCR PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address). 0 24 read-only PDMA_CDAR PDMA_CDAR PDMA Current Destination Address Register 0x18 read-only n 0x0 0x0 PDMA_CDAR PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSAR PDMA_CSAR PDMA Current Source Address Register 0x14 read-only n 0x0 0x0 PDMA_CSAR PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred. 0 32 read-only PDMA_CSR PDMA_CSR PDMA Control Register 0x0 read-write n 0x0 0x0 APB_TWS Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral). 19 2 read-write 0 One word (32-bit) is transferred for every PDMA operation #00 1 One byte (8-bit) is transferred for every PDMA operation #01 2 One half-word (16-bit) is transferred for every PDMA operation #10 3 Reserved #11 DAD_SEL Transfer Destination Address Direction Selection\n 6 2 read-write 0 Transfer Destination address is incremented successively #00 1 Reserved #01 2 Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination) #10 3 Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to 0, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 MODE_SEL PDMA Mode Selection\n 2 2 read-write 0 Memory to Memory mode (Memory-to-Memory) #00 1 Peripheral to Memory mode (Peripheral-to-Memory) #01 2 Memory to Peripheral mode (Memory-to-Peripheral) #10 3 Reserved #11 PDMACEN PDMA Channel Enable Control Setting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state. 0 1 read-write SAD_SEL Transfer Source Address Direction Selection\n 4 2 read-write 0 Transfer Source address is incremented successively #00 1 Reserved #01 2 Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations) #10 3 Transfer Source address is wrap around (When the PDMA_CBCR is equal to 0, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address) #11 SW_RST Software Engine Reset\n 1 1 read-write 0 No effect #0 1 Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 TO_EN Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero, the TO_IS will be set.\n 12 1 read-write 0 PDMA internal counter Disabled #0 1 PDMA internal counter Enabled #1 TRIG_EN Trigger Enable Control\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channel, and then trigger again. 23 1 read-write 0 No effect #0 1 PDMA data read or write transfer Enabled #1 PDMA_DAR PDMA_DAR PDMA Destination Address Register 0x8 read-write n 0x0 0x0 PDMA_DAR PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment 0 32 read-write PDMA_IER PDMA_IER PDMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABORT_IE PDMA Read/Write Target Abort Interrupt Enable Control\n 0 1 read-write 0 Target abort interrupt generation Disabled during PDMA transfer #0 1 Target abort interrupt generation Enabled during PDMA transfer #1 TD_IE PDMA Transfer Done Interrupt Enable Control\n 1 1 read-write 0 Interrupt generator Disabled when PDMA transfer is done #0 1 Interrupt generator Enabled when PDMA transfer is done #1 TO_IE Time-Out Interrupt Enable Control\n 6 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 WRA_BCR_IE Wrap Around Byte Count Interrupt Enable Control\n 2 4 read-write 1 Interrupt enable of PDMA_CBCR equals 0 #0001 4 Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR #0100 PDMA_ISR PDMA_ISR PDMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABORT_IS PDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TD_IS Transfer Done Interrupt Status Flag This bit indicates that PDMA has finished all transfer. Note: This bit is cleared by writing 1 to it. 1 1 read-write 0 Not finished yet #0 1 Done #1 TO_IS Time-Out Interrupt Status Flag This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR. Note: This bit is cleared by writing 1 to it. 6 1 read-write 0 No time-out flag #0 1 Time-out flag #1 WRA_BCR_IS Wrap Around Transfer Byte Count Interrupt Status Flag\n 2 4 read-write PDMA_SAR PDMA_SAR PDMA Source Address Register 0x4 read-write n 0x0 0x0 PDMA_SAR PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment. 0 32 read-write PDMA_TCR PDMA_TCR PDMA Timer Counter Setting Register 0x28 read-write n 0x0 0x0 PDMA_TCR PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts counting down when setting TO_EN (PDMA_CSRx[12]). PDMA will request interrupt when this internal counter reaches 0 and TO_IE (PDMA_IERx[6]) is 1. 0 16 read-write PWM0 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x8 registers n 0x28 0x8 registers n 0x34 0x8 registers n 0x40 0x8 registers n 0x54 0x34 registers n CAPCTL PWM0_CAPCTL Capture Control Register 0x54 read-write n 0x0 0x0 CAPCH0EN Capture Channel 0 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL0 (Rising latch) and PWMx_CFL0 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL0 and PWMx_CFL0, and disable Channel 0 Interrupt. 1 1 read-write 0 Capture function on channel 0 Disabled #0 1 Capture function on channel 0 Enabled #1 CAPCH0PADEN Capture Input Enable Register\n 2 1 read-write 0 Disable the channel 0 input capture signal from corresponding multi-function pin #0 1 Enable the channel 0 input capture signal from corresponding multi-function pin #1 CAPCH1EN Capture Channel 1 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-counter and saved to PWMx_CRL1 (Rising latch) and PWMx_CFL1 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL1 and PWMx_CFL1, and disable Channel 1 Interrupt. 9 1 read-write 0 Capture function on channel 1 Disabled #0 1 Capture function on channel 1 Enabled #1 CAPCH1PADEN Capture Input Enable Register\n 10 1 read-write 0 Disable the channel 1 input capture signal from corresponding multi-function pin #0 1 Enable the channel 1 input capture signal from corresponding multi-function pin #1 CAPCH2EN Capture Channel 2 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL2 (Rising latch) and PWMx_CFL2 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL2 and PWMx_CFL2, and disable Channel 2 Interrupt. 17 1 read-write 0 Capture function on channel 2 Disabled #0 1 Capture function on channel 2 Enabled #1 CAPCH2PADEN Capture Input Enable Register\n 18 1 read-write 0 Disable the channel 2 input capture signal from corresponding multi-function pin #0 1 Enable the channel 2 input capture signal from corresponding multi-function pin #1 CAPCH3EN Capture Channel 3 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-timer and saved to PWMx_CRL3 (Rising latch) and PWMx_CFL3 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL3 and PWMx_CFL3, and disable Channel 3 Interrupt. 25 1 read-write 0 Capture function on channel 3 Disabled #0 1 Capture function on channel 3 Enabled #1 CAPCH3PADEN Capture Input Enable Register\n 26 1 read-write 0 Disable the channel 3 input capture signal from corresponding multi-function pin #0 1 Enable the channel 3 input capture signal from corresponding multi-function pin #1 CAPRELOADFEN0 Reload CNR0 When CH0 Capture Falling Event Comes\n 7 1 read-write 0 Falling capture reload for CH0 Disabled #0 1 Falling capture reload for CH0 Enabled #1 CAPRELOADFEN1 Reload CNR1 When CH1 Capture Falling Event Coming \n 15 1 read-write 0 Capture falling reload for CH1 Disabled #0 1 Capture falling reload for CH1 Enabled #1 CAPRELOADFEN2 Reload CNR2 When CH2 Capture Failing Event Coming \n 23 1 read-write 0 Failing capture reload for CH2 Disabled #0 1 Failing capture reload for CH2 Enabled #1 CAPRELOADFEN3 Reload CNR3 When CH3 Falling Capture Event Comes \n 31 1 read-write 0 Falling capture reload for CH3 Disabled #0 1 Falling capture reload for CH3 Enabled #1 CAPRELOADREN0 Reload CNR0 When CH0 Capture Rising Event Comes \n 6 1 read-write 0 Rising capture reload for CH0 Disabled #0 1 Rising capture reload for CH0 Enabled #1 CAPRELOADREN1 Reload CNR1 When CH1 Capture Rising Event Comes\n 14 1 read-write 0 Rising capture reload for CH1 Disabled #0 1 Rising capture reload for CH1 Enabled #1 CAPRELOADREN2 Reload CNR2 When CH2 Capture Rising Event Coming \n 22 1 read-write 0 Rising capture reload for CH2 Disabled #0 1 Rising capture reload for CH2 Enabled #1 CAPRELOADREN3 Reload CNR3 When CH3 Rising Capture Event Comes\n 30 1 read-write 0 Rising capture reload for CH3 Disabled #0 1 Rising capture reload for CH3 Enabled #1 CH01CASK Cascade channel 0 and channel 1 PWM timer for capturing usage 13 1 read-write CH0PDMAEN Channel 0 PDMA Enable\n 3 1 read-write 0 Channel 0 PDMA function Disabled #0 1 Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory #1 CH0RFORDER None 12 1 read-write 0 PWMx_CFL0 is the first captured data to memory #0 1 PWMx_CRL0 is the first captured data to memory #1 CH23CASK Cascade channel 2 and channel 3 PWM counter for capturing usage 29 1 read-write CH2PDMAEN Channel 2 PDMA Enable\n 19 1 read-write 0 Channel 2 PDMA function Disabled #0 1 Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory #1 CH2RFORDER None 28 1 read-write 0 PWMx_CFL2 is the first captured data to memory #0 1 PWMx_CRL2 is the first captured data to memory #1 INV0 Channel 0 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 Channel 1 Inverter ON/OFF\n 8 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV2 Channel 2 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 Channel 3 Inverter ON/OFF\n 24 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 PDMACAPMOD0 Select CRL0 Or CFL0 For PDMA Transfer\n 4 2 read-write 0 reserved #00 1 CRL0 will be transmitted #01 2 CFL0 will be transmitted #10 3 Both CRL0 and CFL0 will be transmitted #11 PDMACAPMOD2 Select CRL2 Or CFL2 For PDMA Transfer\n 20 2 read-write 0 reserved #00 1 CRL2 will be transmitted #01 2 CFL2 will be transmitted #10 3 Both CRL2 and CFL2 will be transmitted #11 CAPINTEN PWM0_CAPINTEN Capture Interrupt Enable Register 0x58 read-write n 0x0 0x0 CFL_IE0 Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt. 1 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt. 9 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE2 Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt. 17 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE3 Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt. 25 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRL_IE0 When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt. 0 1 read-write 1 Rising latch interrupt Enabled #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt. 8 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE2 Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt. 16 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE3 Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt. 24 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CAPINTSTS PWM0_CAPINTSTS Capture Interrupt Indication Register 0x5C read-write n 0x0 0x0 CAPIF0 Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt (CRL_IE0, PWMx_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWMx_CAPINTEN[1]) is enabled. This flag is cleared by software with a write 1 on it. 0 1 read-write CAPIF1 Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt (CRL_IE1, PWMx_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWMx_CAPINTEN[9]) is enabled. This flag is cleared by software with a write 1 on it. 8 1 read-write CAPIF2 Capture2 Interrupt Indication Flag If channel 2 rising latch interrupt (CRL_IE2, PWMx_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWMx_CAPINTEN[17]) is enabled. This flag is cleared by software with a write 1 on it. 16 1 read-write CAPIF3 Capture3 Interrupt Indication Flag If channel 3 rising latch interrupt (CRL_IE3, PWMx_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWMx_CAPINTEN[25]) is enabled. This flag is cleared by software with a write 1 on it. 24 1 read-write CAPOVF0 Capture Falling Flag Over Run For Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWMx_CAPINTSTS[2]) 4 1 read-write CAPOVF1 Capture Falling Flag Over Run For Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWMx_CAPINTSTS[10]) 12 1 read-write CAPOVF2 Capture Falling Flag Over Run For Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWMx_CAPINTSTS[18]) 20 1 read-write CAPOVF3 Capture Falling Flag Over Run For Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWMx_CAPINTSTS[26]) 28 1 read-write CAPOVR0 Capture Rising Flag Over Run For Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWMx_CAPINTSTS[1]). 3 1 read-write CAPOVR1 Capture Rising Flag Over Run For Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWMx_CAPINTSTS[9]) 11 1 read-write CAPOVR2 Capture Rising Flag Over Run For Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWMx_CAPINTSTS[17]) 19 1 read-write CAPOVR3 Capture Rising Flag Over Run For Channel 3\nThis flag indicate CRL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWMx_CAPINTSTS[25]) 27 1 read-write CFLI0 PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition, PWMx_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 2 1 read-write CFLI1 PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition, PWMx_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a 1 to it. 10 1 read-write CFLI2 PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition, PWMx_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 18 1 read-write CFLI3 PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition, PWMx_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 26 1 read-write CRLI0 PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition, PWMx_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 1 1 read-write CRLI1 PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition, PWMx_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 9 1 read-write CRLI2 PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition, PWMx_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 17 1 read-write CRLI3 PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition, PWMx_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 25 1 read-write CFL0 PWM0_CFL0 Capture Falling Latch Register (Channel 0) 0x64 read-only n 0x0 0x0 CFL Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. 0 16 read-only CFL_H Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit, 16 16 read-only CFL1 PWM0_CFL1 Capture Falling Latch Register (Channel 1) 0x6C read-write n 0x0 0x0 CFL2 PWM0_CFL2 Capture Falling Latch Register (Channel 2) 0x74 read-write n 0x0 0x0 CFL3 PWM0_CFL3 Capture Falling Latch Register (Channel 3) 0x7C read-write n 0x0 0x0 CLKSEL PWM0_CLKSEL PWM Clock Select Register 0x4 read-write n 0x0 0x0 CLKSEL0 Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3) 0 3 read-write CLKSEL1 Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3) 4 3 read-write CLKSEL2 Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3) 8 3 read-write CLKSEL3 Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n 12 3 read-write 0 input clock is divided by 2 #000 1 input clock is divided by 4 #001 2 input clock is divided by 8 #010 3 input clock is divided by 16 #011 4 input clock is divided by 1 #100 CRL0 PWM0_CRL0 Capture Rising Latch Register (Channel 0) 0x60 read-only n 0x0 0x0 CRL Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit, 16 16 read-only CRL1 PWM0_CRL1 Capture Rising Latch Register (Channel 1) 0x68 read-write n 0x0 0x0 CRL2 PWM0_CRL2 Capture Rising Latch Register (Channel 2) 0x70 read-write n 0x0 0x0 CRL3 PWM0_CRL3 Capture Rising Latch Register (Channel 3) 0x78 read-write n 0x0 0x0 CTL PWM0_CTL PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable/Disable Start Run\n 0 1 read-write 0 PWM-Timer 0 Running Stopped #0 1 PWM-Timer 0 Start Run Enabled #1 CH0INV PWM-Timer 0 Output Inverter ON/OFF\n 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH0MOD PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY0 to be cleared. 3 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH1EN PWM-Timer 1 Enable/Disable Start Run\n 8 1 read-write 0 PWM-Timer 1 Running Stopped #0 1 PWM-Timer 1 Start Run Enabled #1 CH1INV PWM-Timer 1 Output Inverter ON/OFF\n 10 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH1MOD PWM-Timer 1 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY1 to be cleared. 11 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH2EN PWM-Timer 2 Enable/Disable Start Run\n 16 1 read-write 0 PWM-Timer 2 Running Stopped #0 1 PWM-Timer 2 Start Run Enabled #1 CH2INV PWM-Timer 2 Output Inverter ON/OFF\n 18 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH2MOD PWM-Timer 2 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY2 be cleared. 19 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH3EN PWM-Timer 3 Enable/Disable Start Run\n 24 1 read-write 0 PWM-Timer 3 Running Stopped #0 1 PWM-Timer 3 Start Run Enabled #1 CH3INV PWM-Timer 3 Output Inverter ON/OFF\n 26 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH3MOD PWM-Timer 3 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY3 to be cleared. 27 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 DZEN01 Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair. 4 1 read-write 0 Disabled #0 1 Enabled #1 DZEN23 Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair. 5 1 read-write 0 Disabled #0 1 Enabled #1 DATA0 PWM0_DATA0 PWM Data Register 0 0x20 read-only n 0x0 0x0 DATA PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y. 0 16 read-only DATA_H PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set 16 15 read-only sync Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel 31 1 read-only 0 CNR value is sync to PWM counter #0 1 CNR value is not sync to PWM counter #1 DATA1 PWM0_DATA1 PWM Data Register 1 0x2C read-write n 0x0 0x0 DATA2 PWM0_DATA2 PWM Data Register 2 0x38 read-write n 0x0 0x0 DATA3 PWM0_DATA3 PWM Data Register 3 0x44 read-write n 0x0 0x0 DUTY0 PWM0_DUTY0 PWM Counter/Comparator Register 0 0x1C read-write n 0x0 0x0 CM PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle. 16 16 read-write CN PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle. 0 16 read-write DUTY1 PWM0_DUTY1 PWM Counter/Comparator Register 1 0x28 read-write n 0x0 0x0 DUTY2 PWM0_DUTY2 PWM Counter/Comparator Register 2 0x34 read-write n 0x0 0x0 DUTY3 PWM0_DUTY3 PWM Counter/Comparator Register 3 0x40 read-write n 0x0 0x0 INTEN PWM0_INTEN PWM Interrupt Enable Register 0xC read-write n 0x0 0x0 TMIE0 PWM Timer 0 Interrupt Enable\n 0 1 read-write 0 Disabled #0 1 Enabled #1 TMIE1 PWM Timer 1 Interrupt Enable\n 1 1 read-write 0 Disabled #0 1 Enabled #1 TMIE2 PWM Timer 2 Interrupt Enable\n 2 1 read-write 0 Disabled #0 1 Enabled #1 TMIE3 PWM Timer 3 Interrupt Enable\n 3 1 read-write 0 Disabled #0 1 Enabled #1 INTSTS PWM0_INTSTS PWM Interrupt Indication Register 0x10 -1 read-write n 0x0 0x0 Duty0Syncflag Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle 4 1 read-write 0 Duty0 has been synchronized to ECLK domain #0 1 Duty0 is synchronizing to ECLK domain #1 Duty1Syncflag Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle 5 1 read-write 0 Duty1 has been synchronized to ECLK domain #0 1 Duty1 is synchronizing to ECLK domain #1 Duty2Syncflag Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle 6 1 read-write 0 Duty2 has been synchronized to ECLK domain #0 1 Duty2 is synchronizing to ECLK domain #1 Duty3Syncflag Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle 7 1 read-write 0 Duty3 has been synchronized to ECLK domain #0 1 Duty3 is synchronizing to ECLK domain #1 PresSyncFlag Prescale Synchronize Flag Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle 8 1 read-write 0 Prescale has been synchronized to ECLK domain #0 1 Prescale is synchronizing to ECLK domain #1 TMINT0 PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. 0 1 read-write TMINT1 PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. 1 1 read-write TMINT2 PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. 2 1 read-write TMINT3 PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. 3 1 read-write OE PWM0_OE PWM Output Enable Register for CH0 ~ CH3 0x14 read-write n 0x0 0x0 CH0_OE PWM CH0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 0 1 read-write 0 PWM CH0 output to pin Disabled #0 1 PWM CH0 output to pin Enabled #1 CH1_OE PWM CH1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 1 1 read-write 0 PWM CH1 output to pin Disabled #0 1 PWM CH1 output to pin Enabled #1 CH2_OE PWM CH2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 2 1 read-write 0 PWM CH2 output to pin Disabled #0 1 PWM CH2 output to pin Enabled #1 CH3_OE PWM CH3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 3 1 read-write 0 PWM CH3 output to pin Disabled #0 1 PWM CH3 output to pin Enabled #1 PDMACH0 PWM0_PDMACH0 PDMA Channel 0 Captured Data 0x80 read-only n 0x0 0x0 PDMACH01 Captured Data Of Channel 0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0 0 8 read-only PDMACH02 Captured Data Of Channel 0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0 8 8 read-only PDMACH03 Captured Data Of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0 16 8 read-only PDMACH04 Captured Data Of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the fourth byte of 32 bit capturing data for channel 0 24 8 read-only PDMACH2 PWM0_PDMACH2 PDMA Channel 2 Captured Data 0x84 read-only n 0x0 0x0 PDMACH21 Captured Data Of Channel 2\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2 0 8 read-only PDMACH22 Captured Data Of Channel 2\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2 8 8 read-only PDMACH23 Captured Data Of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2 16 8 read-only PDMACH24 Captured Data Of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the fourth byte of 32 bit capturing data for channel 2 24 8 read-only PRES PWM0_PRES PWM Prescaler Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler 0 For PWM Timer 0 1 Clock input is divided by (CP01 + 1) before it is fed to the counter 0 1 0 8 read-write CP23 Clock Prescaler 2 For PWM Timer 2 3 Clock input is divided by (CP23 + 1) before it is fed to the counter 2 3 8 8 read-write DZ01 Dead Zone Interval Register For CH0 And CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0. 16 8 read-write DZ23 Dead Zone Interval Register For CH2 And CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2. 24 8 read-write PWM1_CAPCTL PWM1_CAPCTL Capture Control Register PWM0_CAPCTL 0x54 read-write n 0x0 0x0 PWM1_CAPINTEN PWM1_CAPINTEN Capture Interrupt Enable Register PWM0_CAPINTEN 0x58 read-write n 0x0 0x0 PWM1_CAPINTSTS PWM1_CAPINTSTS Capture Interrupt Indication Register PWM0_CAPINTSTS 0x5C read-write n 0x0 0x0 PWM1_CFL0 PWM1_CFL0 Capture Falling Latch Register (Channel 0) PWM0_CFL0 0x64 read-write n 0x0 0x0 PWM1_CFL1 PWM1_CFL1 Capture Falling Latch Register (Channel 1) PWM0_CFL1 0x6C read-write n 0x0 0x0 PWM1_CFL2 PWM1_CFL2 Capture Falling Latch Register (Channel 2) PWM0_CFL2 0x74 read-write n 0x0 0x0 PWM1_CFL3 PWM1_CFL3 Capture Falling Latch Register (Channel 3) PWM0_CFL3 0x7C read-write n 0x0 0x0 PWM1_CLKSEL PWM1_CLKSEL PWM Clock Select Register PWM0_CLKSEL 0x4 read-write n 0x0 0x0 PWM1_CRL0 PWM1_CRL0 Capture Rising Latch Register (Channel 0) PWM0_CRL0 0x60 read-write n 0x0 0x0 PWM1_CRL1 PWM1_CRL1 Capture Rising Latch Register (Channel 1) PWM0_CRL1 0x68 read-write n 0x0 0x0 PWM1_CRL2 PWM1_CRL2 Capture Rising Latch Register (Channel 2) PWM0_CRL2 0x70 read-write n 0x0 0x0 PWM1_CRL3 PWM1_CRL3 Capture Rising Latch Register (Channel 3) PWM0_CRL3 0x78 read-write n 0x0 0x0 PWM1_CTL PWM1_CTL PWM Control Register PWM0_CTL 0x8 read-write n 0x0 0x0 PWM1_DATA0 PWM1_DATA0 PWM Data Register 0 PWM0_DATA0 0x20 read-write n 0x0 0x0 PWM1_DATA1 PWM1_DATA1 PWM Data Register 1 PWM0_DATA1 0x2C read-write n 0x0 0x0 PWM1_DATA2 PWM1_DATA2 PWM Data Register 2 PWM0_DATA2 0x38 read-write n 0x0 0x0 PWM1_DATA3 PWM1_DATA3 PWM Data Register 3 PWM0_DATA3 0x44 read-write n 0x0 0x0 PWM1_DUTY0 PWM1_DUTY0 PWM Counter/Comparator Register 0 PWM0_DUTY0 0x1C read-write n 0x0 0x0 PWM1_DUTY1 PWM1_DUTY1 PWM Counter/Comparator Register 1 PWM0_DUTY1 0x28 read-write n 0x0 0x0 PWM1_DUTY2 PWM1_DUTY2 PWM Counter/Comparator Register 2 PWM0_DUTY2 0x34 read-write n 0x0 0x0 PWM1_DUTY3 PWM1_DUTY3 PWM Counter/Comparator Register 3 PWM0_DUTY3 0x40 read-write n 0x0 0x0 PWM1_INTEN PWM1_INTEN PWM Interrupt Enable Register PWM0_INTEN 0xC read-write n 0x0 0x0 PWM1_INTSTS PWM1_INTSTS PWM Interrupt Indication Register PWM0_INTSTS 0x10 read-write n 0x0 0x0 PWM1_OE PWM1_OE PWM Output Enable Register for CH0 ~ CH3 PWM0_OE 0x14 read-write n 0x0 0x0 PWM1_PDMACH0 PWM1_PDMACH0 PDMA Channel 0 Captured Data PWM0_PDMACH0 0x80 read-write n 0x0 0x0 PWM1_PDMACH2 PWM1_PDMACH2 PDMA Channel 2 Captured Data PWM0_PDMACH2 0x84 read-write n 0x0 0x0 PWM1_PRES PWM1_PRES PWM Prescaler Register PWM0_PRES 0x0 read-write n 0x0 0x0 PWM1 PWM Register Map PWM 0x0 0x0 0x18 registers n 0x1C 0x8 registers n 0x28 0x8 registers n 0x34 0x8 registers n 0x40 0x8 registers n 0x54 0x34 registers n CAPCTL PWM1_CAPCTL Capture Control Register PWM0_CAPCTL 0x54 read-write n 0x0 0x0 CAPINTEN PWM1_CAPINTEN Capture Interrupt Enable Register PWM0_CAPINTEN 0x58 read-write n 0x0 0x0 CAPINTSTS PWM1_CAPINTSTS Capture Interrupt Indication Register PWM0_CAPINTSTS 0x5C read-write n 0x0 0x0 CFL0 PWM1_CFL0 Capture Falling Latch Register (Channel 0) PWM0_CFL0 0x64 read-write n 0x0 0x0 CFL1 PWM1_CFL1 Capture Falling Latch Register (Channel 1) PWM0_CFL1 0x6C read-write n 0x0 0x0 CFL2 PWM1_CFL2 Capture Falling Latch Register (Channel 2) PWM0_CFL2 0x74 read-write n 0x0 0x0 CFL3 PWM1_CFL3 Capture Falling Latch Register (Channel 3) PWM0_CFL3 0x7C read-write n 0x0 0x0 CLKSEL PWM1_CLKSEL PWM Clock Select Register PWM0_CLKSEL 0x4 read-write n 0x0 0x0 CRL0 PWM1_CRL0 Capture Rising Latch Register (Channel 0) PWM0_CRL0 0x60 read-write n 0x0 0x0 CRL1 PWM1_CRL1 Capture Rising Latch Register (Channel 1) PWM0_CRL1 0x68 read-write n 0x0 0x0 CRL2 PWM1_CRL2 Capture Rising Latch Register (Channel 2) PWM0_CRL2 0x70 read-write n 0x0 0x0 CRL3 PWM1_CRL3 Capture Rising Latch Register (Channel 3) PWM0_CRL3 0x78 read-write n 0x0 0x0 CTL PWM1_CTL PWM Control Register PWM0_CTL 0x8 read-write n 0x0 0x0 DATA0 PWM1_DATA0 PWM Data Register 0 PWM0_DATA0 0x20 read-write n 0x0 0x0 DATA1 PWM1_DATA1 PWM Data Register 1 PWM0_DATA1 0x2C read-write n 0x0 0x0 DATA2 PWM1_DATA2 PWM Data Register 2 PWM0_DATA2 0x38 read-write n 0x0 0x0 DATA3 PWM1_DATA3 PWM Data Register 3 PWM0_DATA3 0x44 read-write n 0x0 0x0 DUTY0 PWM1_DUTY0 PWM Counter/Comparator Register 0 PWM0_DUTY0 0x1C read-write n 0x0 0x0 DUTY1 PWM1_DUTY1 PWM Counter/Comparator Register 1 PWM0_DUTY1 0x28 read-write n 0x0 0x0 DUTY2 PWM1_DUTY2 PWM Counter/Comparator Register 2 PWM0_DUTY2 0x34 read-write n 0x0 0x0 DUTY3 PWM1_DUTY3 PWM Counter/Comparator Register 3 PWM0_DUTY3 0x40 read-write n 0x0 0x0 INTEN PWM1_INTEN PWM Interrupt Enable Register PWM0_INTEN 0xC read-write n 0x0 0x0 INTSTS PWM1_INTSTS PWM Interrupt Indication Register PWM0_INTSTS 0x10 read-write n 0x0 0x0 OE PWM1_OE PWM Output Enable Register for CH0 ~ CH3 PWM0_OE 0x14 read-write n 0x0 0x0 PDMACH0 PWM1_PDMACH0 PDMA Channel 0 Captured Data PWM0_PDMACH0 0x80 read-write n 0x0 0x0 PDMACH2 PWM1_PDMACH2 PDMA Channel 2 Captured Data PWM0_PDMACH2 0x84 read-write n 0x0 0x0 PRES PWM1_PRES PWM Prescaler Register PWM0_PRES 0x0 read-write n 0x0 0x0 PWM0_CAPCTL PWM0_CAPCTL Capture Control Register 0x54 read-write n 0x0 0x0 CAPCH0EN Capture Channel 0 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL0 (Rising latch) and PWMx_CFL0 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL0 and PWMx_CFL0, and disable Channel 0 Interrupt. 1 1 read-write 0 Capture function on channel 0 Disabled #0 1 Capture function on channel 0 Enabled #1 CAPCH0PADEN Capture Input Enable Register\n 2 1 read-write 0 Disable the channel 0 input capture signal from corresponding multi-function pin #0 1 Enable the channel 0 input capture signal from corresponding multi-function pin #1 CAPCH1EN Capture Channel 1 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-counter and saved to PWMx_CRL1 (Rising latch) and PWMx_CFL1 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL1 and PWMx_CFL1, and disable Channel 1 Interrupt. 9 1 read-write 0 Capture function on channel 1 Disabled #0 1 Capture function on channel 1 Enabled #1 CAPCH1PADEN Capture Input Enable Register\n 10 1 read-write 0 Disable the channel 1 input capture signal from corresponding multi-function pin #0 1 Enable the channel 1 input capture signal from corresponding multi-function pin #1 CAPCH2EN Capture Channel 2 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL2 (Rising latch) and PWMx_CFL2 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL2 and PWMx_CFL2, and disable Channel 2 Interrupt. 17 1 read-write 0 Capture function on channel 2 Disabled #0 1 Capture function on channel 2 Enabled #1 CAPCH2PADEN Capture Input Enable Register\n 18 1 read-write 0 Disable the channel 2 input capture signal from corresponding multi-function pin #0 1 Enable the channel 2 input capture signal from corresponding multi-function pin #1 CAPCH3EN Capture Channel 3 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-timer and saved to PWMx_CRL3 (Rising latch) and PWMx_CFL3 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL3 and PWMx_CFL3, and disable Channel 3 Interrupt. 25 1 read-write 0 Capture function on channel 3 Disabled #0 1 Capture function on channel 3 Enabled #1 CAPCH3PADEN Capture Input Enable Register\n 26 1 read-write 0 Disable the channel 3 input capture signal from corresponding multi-function pin #0 1 Enable the channel 3 input capture signal from corresponding multi-function pin #1 CAPRELOADFEN0 Reload CNR0 When CH0 Capture Falling Event Comes\n 7 1 read-write 0 Falling capture reload for CH0 Disabled #0 1 Falling capture reload for CH0 Enabled #1 CAPRELOADFEN1 Reload CNR1 When CH1 Capture Falling Event Coming \n 15 1 read-write 0 Capture falling reload for CH1 Disabled #0 1 Capture falling reload for CH1 Enabled #1 CAPRELOADFEN2 Reload CNR2 When CH2 Capture Failing Event Coming \n 23 1 read-write 0 Failing capture reload for CH2 Disabled #0 1 Failing capture reload for CH2 Enabled #1 CAPRELOADFEN3 Reload CNR3 When CH3 Falling Capture Event Comes \n 31 1 read-write 0 Falling capture reload for CH3 Disabled #0 1 Falling capture reload for CH3 Enabled #1 CAPRELOADREN0 Reload CNR0 When CH0 Capture Rising Event Comes \n 6 1 read-write 0 Rising capture reload for CH0 Disabled #0 1 Rising capture reload for CH0 Enabled #1 CAPRELOADREN1 Reload CNR1 When CH1 Capture Rising Event Comes\n 14 1 read-write 0 Rising capture reload for CH1 Disabled #0 1 Rising capture reload for CH1 Enabled #1 CAPRELOADREN2 Reload CNR2 When CH2 Capture Rising Event Coming \n 22 1 read-write 0 Rising capture reload for CH2 Disabled #0 1 Rising capture reload for CH2 Enabled #1 CAPRELOADREN3 Reload CNR3 When CH3 Rising Capture Event Comes\n 30 1 read-write 0 Rising capture reload for CH3 Disabled #0 1 Rising capture reload for CH3 Enabled #1 CH01CASK Cascade channel 0 and channel 1 PWM timer for capturing usage 13 1 read-write CH0PDMAEN Channel 0 PDMA Enable\n 3 1 read-write 0 Channel 0 PDMA function Disabled #0 1 Channel 0 PDMA function Enabled for the channel 0 captured data and transfer to memory #1 CH0RFORDER None 12 1 read-write 0 PWMx_CFL0 is the first captured data to memory #0 1 PWMx_CRL0 is the first captured data to memory #1 CH23CASK Cascade channel 2 and channel 3 PWM counter for capturing usage 29 1 read-write CH2PDMAEN Channel 2 PDMA Enable\n 19 1 read-write 0 Channel 2 PDMA function Disabled #0 1 Channel 2 PDMA function Enabled for the channel 2 captured data and transfer to memory #1 CH2RFORDER None 28 1 read-write 0 PWMx_CFL2 is the first captured data to memory #0 1 PWMx_CRL2 is the first captured data to memory #1 INV0 Channel 0 Inverter ON/OFF\n 0 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 Channel 1 Inverter ON/OFF\n 8 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV2 Channel 2 Inverter ON/OFF\n 16 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 Channel 3 Inverter ON/OFF\n 24 1 read-write 0 Inverter OFF #0 1 Inverter ON. Reverse the input signal from GPIO before fed to Capture timer #1 PDMACAPMOD0 Select CRL0 Or CFL0 For PDMA Transfer\n 4 2 read-write 0 reserved #00 1 CRL0 will be transmitted #01 2 CFL0 will be transmitted #10 3 Both CRL0 and CFL0 will be transmitted #11 PDMACAPMOD2 Select CRL2 Or CFL2 For PDMA Transfer\n 20 2 read-write 0 reserved #00 1 CRL2 will be transmitted #01 2 CFL2 will be transmitted #10 3 Both CRL2 and CFL2 will be transmitted #11 PWM0_CAPINTEN PWM0_CAPINTEN Capture Interrupt Enable Register 0x58 read-write n 0x0 0x0 CFL_IE0 Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt. 1 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt. 9 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE2 Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt. 17 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE3 Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt. 25 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRL_IE0 When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt. 0 1 read-write 1 Rising latch interrupt Enabled #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt. 8 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE2 Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt. 16 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE3 Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt. 24 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 PWM0_CAPINTSTS PWM0_CAPINTSTS Capture Interrupt Indication Register 0x5C read-write n 0x0 0x0 CAPIF0 Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt (CRL_IE0, PWMx_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWMx_CAPINTEN[1]) is enabled. This flag is cleared by software with a write 1 on it. 0 1 read-write CAPIF1 Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt (CRL_IE1, PWMx_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWMx_CAPINTEN[9]) is enabled. This flag is cleared by software with a write 1 on it. 8 1 read-write CAPIF2 Capture2 Interrupt Indication Flag If channel 2 rising latch interrupt (CRL_IE2, PWMx_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWMx_CAPINTEN[17]) is enabled. This flag is cleared by software with a write 1 on it. 16 1 read-write CAPIF3 Capture3 Interrupt Indication Flag If channel 3 rising latch interrupt (CRL_IE3, PWMx_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWMx_CAPINTEN[25]) is enabled. This flag is cleared by software with a write 1 on it. 24 1 read-write CAPOVF0 Capture Falling Flag Over Run For Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWMx_CAPINTSTS[2]) 4 1 read-write CAPOVF1 Capture Falling Flag Over Run For Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWMx_CAPINTSTS[10]) 12 1 read-write CAPOVF2 Capture Falling Flag Over Run For Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWMx_CAPINTSTS[18]) 20 1 read-write CAPOVF3 Capture Falling Flag Over Run For Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWMx_CAPINTSTS[26]) 28 1 read-write CAPOVR0 Capture Rising Flag Over Run For Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWMx_CAPINTSTS[1]). 3 1 read-write CAPOVR1 Capture Rising Flag Over Run For Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWMx_CAPINTSTS[9]) 11 1 read-write CAPOVR2 Capture Rising Flag Over Run For Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWMx_CAPINTSTS[17]) 19 1 read-write CAPOVR3 Capture Rising Flag Over Run For Channel 3\nThis flag indicate CRL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWMx_CAPINTSTS[25]) 27 1 read-write CFLI0 PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition, PWMx_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 2 1 read-write CFLI1 PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition, PWMx_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a 1 to it. 10 1 read-write CFLI2 PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition, PWMx_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 18 1 read-write CFLI3 PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition, PWMx_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 26 1 read-write CRLI0 PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition, PWMx_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 1 1 read-write CRLI1 PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition, PWMx_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 9 1 read-write CRLI2 PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition, PWMx_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 17 1 read-write CRLI3 PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition, PWMx_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it. 25 1 read-write PWM0_CFL0 PWM0_CFL0 Capture Falling Latch Register (Channel 0) 0x64 read-only n 0x0 0x0 CFL Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition. 0 16 read-only CFL_H Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit, 16 16 read-only PWM0_CFL1 PWM0_CFL1 Capture Falling Latch Register (Channel 1) 0x6C read-write n 0x0 0x0 PWM0_CFL2 PWM0_CFL2 Capture Falling Latch Register (Channel 2) 0x74 read-write n 0x0 0x0 PWM0_CFL3 PWM0_CFL3 Capture Falling Latch Register (Channel 3) 0x7C read-write n 0x0 0x0 PWM0_CLKSEL PWM0_CLKSEL PWM Clock Select Register 0x4 read-write n 0x0 0x0 CLKSEL0 Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3) 0 3 read-write CLKSEL1 Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3) 4 3 read-write CLKSEL2 Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3) 8 3 read-write CLKSEL3 Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n 12 3 read-write 0 input clock is divided by 2 #000 1 input clock is divided by 4 #001 2 input clock is divided by 8 #010 3 input clock is divided by 16 #011 4 input clock is divided by 1 #100 PWM0_CRL0 PWM0_CRL0 Capture Rising Latch Register (Channel 0) 0x60 read-only n 0x0 0x0 CRL Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition. 0 16 read-only CRL_H Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit, 16 16 read-only PWM0_CRL1 PWM0_CRL1 Capture Rising Latch Register (Channel 1) 0x68 read-write n 0x0 0x0 PWM0_CRL2 PWM0_CRL2 Capture Rising Latch Register (Channel 2) 0x70 read-write n 0x0 0x0 PWM0_CRL3 PWM0_CRL3 Capture Rising Latch Register (Channel 3) 0x78 read-write n 0x0 0x0 PWM0_CTL PWM0_CTL PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable/Disable Start Run\n 0 1 read-write 0 PWM-Timer 0 Running Stopped #0 1 PWM-Timer 0 Start Run Enabled #1 CH0INV PWM-Timer 0 Output Inverter ON/OFF\n 2 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH0MOD PWM-Timer 0 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY0 to be cleared. 3 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH1EN PWM-Timer 1 Enable/Disable Start Run\n 8 1 read-write 0 PWM-Timer 1 Running Stopped #0 1 PWM-Timer 1 Start Run Enabled #1 CH1INV PWM-Timer 1 Output Inverter ON/OFF\n 10 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH1MOD PWM-Timer 1 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY1 to be cleared. 11 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH2EN PWM-Timer 2 Enable/Disable Start Run\n 16 1 read-write 0 PWM-Timer 2 Running Stopped #0 1 PWM-Timer 2 Start Run Enabled #1 CH2INV PWM-Timer 2 Output Inverter ON/OFF\n 18 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH2MOD PWM-Timer 2 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY2 be cleared. 19 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 CH3EN PWM-Timer 3 Enable/Disable Start Run\n 24 1 read-write 0 PWM-Timer 3 Running Stopped #0 1 PWM-Timer 3 Start Run Enabled #1 CH3INV PWM-Timer 3 Output Inverter ON/OFF\n 26 1 read-write 0 Inverter OFF #0 1 Inverter ON #1 CH3MOD PWM-Timer 3 Continuous/One-Shot Mode\nNote: If there is a rising transition at this bit, it will cause CN and CM of PWMx_DUTY3 to be cleared. 27 1 read-write 0 One-shot Mode #0 1 Continuous Mode #1 DZEN01 Dead-Zone 0 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair. 4 1 read-write 0 Disabled #0 1 Enabled #1 DZEN23 Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair. 5 1 read-write 0 Disabled #0 1 Enabled #1 PWM0_DATA0 PWM0_DATA0 PWM Data Register 0 0x20 read-only n 0x0 0x0 DATA PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y. 0 16 read-only DATA_H PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set 16 15 read-only sync Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel 31 1 read-only 0 CNR value is sync to PWM counter #0 1 CNR value is not sync to PWM counter #1 PWM0_DATA1 PWM0_DATA1 PWM Data Register 1 0x2C read-write n 0x0 0x0 PWM0_DATA2 PWM0_DATA2 PWM Data Register 2 0x38 read-write n 0x0 0x0 PWM0_DATA3 PWM0_DATA3 PWM Data Register 3 0x44 read-write n 0x0 0x0 PWM0_DUTY0 PWM0_DUTY0 PWM Counter/Comparator Register 0 0x1C read-write n 0x0 0x0 CM PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle. 16 16 read-write CN PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle. 0 16 read-write PWM0_DUTY1 PWM0_DUTY1 PWM Counter/Comparator Register 1 0x28 read-write n 0x0 0x0 PWM0_DUTY2 PWM0_DUTY2 PWM Counter/Comparator Register 2 0x34 read-write n 0x0 0x0 PWM0_DUTY3 PWM0_DUTY3 PWM Counter/Comparator Register 3 0x40 read-write n 0x0 0x0 PWM0_INTEN PWM0_INTEN PWM Interrupt Enable Register 0xC read-write n 0x0 0x0 TMIE0 PWM Timer 0 Interrupt Enable\n 0 1 read-write 0 Disabled #0 1 Enabled #1 TMIE1 PWM Timer 1 Interrupt Enable\n 1 1 read-write 0 Disabled #0 1 Enabled #1 TMIE2 PWM Timer 2 Interrupt Enable\n 2 1 read-write 0 Disabled #0 1 Enabled #1 TMIE3 PWM Timer 3 Interrupt Enable\n 3 1 read-write 0 Disabled #0 1 Enabled #1 PWM0_INTSTS PWM0_INTSTS PWM Interrupt Indication Register 0x10 -1 read-write n 0x0 0x0 Duty0Syncflag Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle 4 1 read-write 0 Duty0 has been synchronized to ECLK domain #0 1 Duty0 is synchronizing to ECLK domain #1 Duty1Syncflag Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle 5 1 read-write 0 Duty1 has been synchronized to ECLK domain #0 1 Duty1 is synchronizing to ECLK domain #1 Duty2Syncflag Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle 6 1 read-write 0 Duty2 has been synchronized to ECLK domain #0 1 Duty2 is synchronizing to ECLK domain #1 Duty3Syncflag Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle 7 1 read-write 0 Duty3 has been synchronized to ECLK domain #0 1 Duty3 is synchronizing to ECLK domain #1 PresSyncFlag Prescale Synchronize Flag Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle 8 1 read-write 0 Prescale has been synchronized to ECLK domain #0 1 Prescale is synchronizing to ECLK domain #1 TMINT0 PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it. 0 1 read-write TMINT1 PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it. 1 1 read-write TMINT2 PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it. 2 1 read-write TMINT3 PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it. 3 1 read-write PWM0_OE PWM0_OE PWM Output Enable Register for CH0 ~ CH3 0x14 read-write n 0x0 0x0 CH0_OE PWM CH0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 0 1 read-write 0 PWM CH0 output to pin Disabled #0 1 PWM CH0 output to pin Enabled #1 CH1_OE PWM CH1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 1 1 read-write 0 PWM CH1 output to pin Disabled #0 1 PWM CH1 output to pin Enabled #1 CH2_OE PWM CH2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 2 1 read-write 0 PWM CH2 output to pin Disabled #0 1 PWM CH2 output to pin Enabled #1 CH3_OE PWM CH3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP) 3 1 read-write 0 PWM CH3 output to pin Disabled #0 1 PWM CH3 output to pin Enabled #1 PWM0_PDMACH0 PWM0_PDMACH0 PDMA Channel 0 Captured Data 0x80 read-only n 0x0 0x0 PDMACH01 Captured Data Of Channel 0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 0 0 8 read-only PDMACH02 Captured Data Of Channel 0\nWhen CH01CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 0\nWhen CH01CASK is enabled, It is the second byte of 32 bit capturing data for channel 0 8 8 read-only PDMACH03 Captured Data Of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the third byte of 32 bit capturing data for channel 0 16 8 read-only PDMACH04 Captured Data Of Channel 0\nWhen CH01CASK is disabled, this byte is 0\nWhen CH01CASK is enabled, It is the fourth byte of 32 bit capturing data for channel 0 24 8 read-only PWM0_PDMACH2 PWM0_PDMACH2 PDMA Channel 2 Captured Data 0x84 read-only n 0x0 0x0 PDMACH21 Captured Data Of Channel 2\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the for the first byte of 32 bit capturing data for channel 2 0 8 read-only PDMACH22 Captured Data Of Channel 2\nWhen CH23CASK is disabled, it is the capturing value(CFL0/CRL0) for channel 2\nWhen CH23CASK is enabled, It is the second byte of 32 bit capturing data for channel 2 8 8 read-only PDMACH23 Captured Data Of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the third byte of 32 bit capturing data for channel 2 16 8 read-only PDMACH24 Captured Data Of Channel 2\nWhen CH23CASK is disabled, this byte is 0\nWhen CH23CASK is enabled, It is the fourth byte of 32 bit capturing data for channel 2 24 8 read-only PWM0_PRES PWM0_PRES PWM Prescaler Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler 0 For PWM Timer 0 1 Clock input is divided by (CP01 + 1) before it is fed to the counter 0 1 0 8 read-write CP23 Clock Prescaler 2 For PWM Timer 2 3 Clock input is divided by (CP23 + 1) before it is fed to the counter 2 3 8 8 read-write DZ01 Dead Zone Interval Register For CH0 And CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0. 16 8 read-write DZ23 Dead Zone Interval Register For CH2 And CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2. 24 8 read-write RTC RTC Register Map RTC 0x0 0x0 0x30 registers n 0x3C 0x54 registers n AER RTC_AER RTC Access Enable Register 0x4 read-write n 0x0 0x0 AER RTC Register Access Enable Password (Write Only)\n 0 16 write-only 43365 Enable RTC acces.s 0xa965 ENF RTC Register Access Enable Flag (Read Only)\n 16 1 read-only 0 RTC register read/write disable #0 1 RTC register read/write enable #1 CAR RTC_CAR Calendar Alarm Register 0x20 read-write n 0x0 0x0 _10DAY 10 Day Calendar Digit of Alarm Setting (0~3) 4 2 read-write _10MON 10 Month Calendar Digit of Alarm Setting (0~1) 12 1 read-write _10YEAR 10 Year Calendar Digit of Alarm Setting (0~9) 20 4 read-write _1DAY 1 Day Calendar Digit of Alarm Setting (0~9) 0 4 read-write _1MON 1 Month Calendar Digit of Alarm Setting (0~9) 8 4 read-write _1YEAR 1 Year Calendar Digit of Alarm Setting (0~9) 16 4 read-write CLR RTC_CLR Calendar Loading Register 0x10 -1 read-write n 0x0 0x0 _10DAY 10 Day Calendar Digit (0~3) 4 2 read-write _10MON 10 Month Calendar Digit (0~1) 12 1 read-write _10YEAR 10 Year Calendar Digit (0~9) 20 4 read-write _1DAY 1 Day Calendar Digit (0~9) 0 4 read-write _1MON 1 Month Calendar Digit (0~9) 8 4 read-write _1YEAR 1 Year Calendar Digit (0~9) 16 4 read-write DWR RTC_DWR Day of the Week Register 0x18 -1 read-write n 0x0 0x0 DWR Day Of The Week Register \n 0 3 read-write FCR RTC_FCR RTC Frequency Compensation Register 0x8 -1 read-write n 0x0 0x0 FRACTION Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number. 0 6 read-write INTEGER Integer Part\n 8 4 read-write INIR RTC_INIR RTC Initiation Register 0x0 read-write n 0x0 0x0 INIR RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIR is a write-only field and read value will be always 0 . RTC Active Status (Read Only), 0 32 write-only 0 RTC is at reset state 0 1 RTC is at normal active state 1 LIR RTC_LIR RTC Leap Year Indication Register 0x24 read-only n 0x0 0x0 LIR Leap Year Indication REGISTER (Read Only)\n 0 1 read-only 0 This year is not a leap year #0 1 This year is leap year #1 RIER RTC_RIER RTC Interrupt Enable Register 0x28 read-write n 0x0 0x0 AIER Alarm Interrupt Enable\n 0 1 read-write 0 RTC Alarm Interrupt is disabled #0 1 RTC Alarm Interrupt is enabled #1 SNOOPIER Snooper Pin Event Detection Interrupt Enable\n 2 1 read-write 0 Snooper Pin Event Detection Interrupt is disabled #0 1 Snooper Pin Event Detection Interrupt is enabled #1 TIER Time Tick Interrupt And Wake-Up By Tick Enable\n 1 1 read-write 0 RTC Time Tick Interrupt is disabled #0 1 RTC Time Tick Interrupt is enabled #1 RIIR RTC_RIIR RTC Interrupt Indicator Register 0x2C read-write n 0x0 0x0 AIS RTC Alarm Interrupt Status RTC unit will set AIF to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. When this bit is set and AIER is also high, RTC will generate an interrupt to CPU. This bit is software clear by writing 1 to it. 0 1 read-write 0 Indicates RCT Alarm Interrupt condition never occurred #0 1 Indicates RTC Alarm Interrupt is requested if RIER.AIER=1 #1 SNOOPIS Snooper Pin Event Detection Interrupt Status When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set. While this bit is set and SNOOPIER is also high, RTC will generate an interrupt to CPU. Write 1 to clear this bit to 0 . 2 1 read-write 0 Snooper pin event defined by SNOOPEDGE never detected #0 1 Snooper pin event defined by SNOOPEDGE detected #1 TIS RTC Time Tick Interrupt Status RTC unit will set TIF to high periodically in the period selected by TTR(RTC_TTR[2:0]). When this bit is set and TIER is also high, RTC will generate an interrupt to CPU. This bit is software clear by writing 1 to it. 1 1 read-write 0 Indicates RCT Time Tick Interrupt condition never occurred #0 1 Indicates RTC Time Tick Interrupt is requested #1 SPR0 RTC_SPR0 RTC Spare Register 0 0x40 read-write n 0x0 0x0 SPARE SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected. 0 32 read-write SPR1 RTC_SPR1 RTC Spare Register 1 0x44 read-write n 0x0 0x0 SPR10 RTC_SPR10 RTC Spare Register 10 0x68 read-write n 0x0 0x0 SPR11 RTC_SPR11 RTC Spare Register 11 0x6C read-write n 0x0 0x0 SPR12 RTC_SPR12 RTC Spare Register 12 0x70 read-write n 0x0 0x0 SPR13 RTC_SPR13 RTC Spare Register 13 0x74 read-write n 0x0 0x0 SPR14 RTC_SPR14 RTC Spare Register 14 0x78 read-write n 0x0 0x0 SPR15 RTC_SPR15 RTC Spare Register 15 0x7C read-write n 0x0 0x0 SPR16 RTC_SPR16 RTC Spare Register 16 0x80 read-write n 0x0 0x0 SPR17 RTC_SPR17 RTC Spare Register 17 0x84 read-write n 0x0 0x0 SPR18 RTC_SPR18 RTC Spare Register 18 0x88 read-write n 0x0 0x0 SPR19 RTC_SPR19 RTC Spare Register 19 0x8C read-write n 0x0 0x0 SPR2 RTC_SPR2 RTC Spare Register 2 0x48 read-write n 0x0 0x0 SPR3 RTC_SPR3 RTC Spare Register 3 0x4C read-write n 0x0 0x0 SPR4 RTC_SPR4 RTC Spare Register 4 0x50 read-write n 0x0 0x0 SPR5 RTC_SPR5 RTC Spare Register 5 0x54 read-write n 0x0 0x0 SPR6 RTC_SPR6 RTC Spare Register 6 0x58 read-write n 0x0 0x0 SPR7 RTC_SPR7 RTC Spare Register 7 0x5C read-write n 0x0 0x0 SPR8 RTC_SPR8 RTC Spare Register 8 0x60 read-write n 0x0 0x0 SPR9 RTC_SPR9 RTC Spare Register 9 0x64 read-write n 0x0 0x0 SPRCTL RTC_SPRCTL RTC Spare Functional Control Register 0x3C -1 read-write n 0x0 0x0 SNOOPEDGE Snooper Active Edge Selection\nThis bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.\n 1 1 read-write 0 Rising edge of snooper pin generates snooper pin detected event #0 1 Falling edge of snooper pin generates snooper pin detected event #1 SNOOPEN Snooper Pin Event Detection Enable This bit enables the snooper pin event detection. When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to 0 by hardware automatically. And, the SNOOPIF will also be set. In addition, RTC will also generate wake-up event to wake system up. 0 1 read-write 0 Snooper pin event detection function Disabled #0 1 Snooper pin event detection function Enabled #1 SPRRDY SPR Register Ready\nThis bit indicates if the registers SPR0 ~ SPR19 are ready to read.\nAfter CPU writing registers SPR0 ~ SPR19, polling this bit to check if SP0 ~ SPR19 are updated done is necessary.\nThis it is a read only bit and any write to this bit won't take any effect.\n 7 1 read-write 0 SPR0 ~ SPR19 updating is in progress #0 1 SPR0 ~ SPR19 are updated done and ready to read #1 TAR RTC_TAR Time Alarm Register 0x1C read-write n 0x0 0x0 _10HR 10 Hour Time Digit of Alarm Setting (0~2) 20 2 read-write _10MIN 10 Min Time Digit of Alarm Setting (0~5) 12 3 read-write _10SEC 10 Sec Time Digit of Alarm Setting (0~5) 4 3 read-write _1HR 1 Hour Time Digit of Alarm Setting (0~9) 16 4 read-write _1MIN 1 Min Time Digit of Alarm Setting (0~9) 8 4 read-write _1SEC 1 Sec Time Digit of Alarm Setting (0~9) 0 4 read-write TLR RTC_TLR Time Loading Register 0xC read-write n 0x0 0x0 _10HR 10 Hour Time Digit (0~2) 20 2 read-write _10MIN 10 Min Time Digit (0~5) 12 3 read-write _10SEC 10 Sec Time Digit (0~5) 4 3 read-write _1HR 1 Hour Time Digit (0~9) 16 4 read-write _1MIN 1 Min Time Digit (0~9) 8 4 read-write _1SEC 1 Sec Time Digit (0~9) 0 4 read-write TSSR RTC_TSSR Time Scale Selection Register 0x14 -1 read-write n 0x0 0x0 _24hr_12hr 24-Hour / 12-Hour Mode Selection\n 0 1 read-write 0 select 12-hour time scale with AM and PM indication #0 1 select 24-hour time scale #1 TTR RTC_TTR RTC Time Tick Register 0x30 read-write n 0x0 0x0 TTR Time Tick Register\n 0 3 read-write TWKE RTC Timer Wake-Up CPU Function Enable Bit\nIf TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit.\nNote: Tick timer setting follows the TTR description. 3 1 read-write 0 Time Tick wake-up CPU function Disabled #0 1 Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick #1 SC0 SC Register Map SC 0x0 0x0 0x40 registers n SC_ALTCTL SC_ALTCTL SC Alternate Control Register. 0x8 read-write n 0x0 0x0 ACT_EN Activation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 DACT_EN Deactivation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INIT_SEL Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in 5.14.4.1.\nWarm-reset: refer to Warm-Reset Sequence in 5.14.4.1\nDeactivation: refer to Deactivation Sequence in 5.14.4.1 8 2 read-write OUTSEL Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode\n 16 1 read-write 0 Quasi mode #0 1 Open-drain mode #1 RX_BGT_EN Receiver Block Guard Time Function Enable Control\n 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RX_RST Rx Software Reset\nWhen RX_RST (SC_ALTCTL[1]) is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 TMR0_ATV Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 TMR0_SEN Internal Timer0 Start Enable Control\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stop counting #0 1 Start counting #1 TMR1_ATV Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 TMR1_SEN Internal Timer1 Start Enable Control\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stop counting #0 1 Start counting #1 TMR2_ATV Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 TMR2_SEN Internal Timer2 Start Enable Control\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stop counting #0 1 Start counting #1 TX_RST TX Software Reset\nWhen TX_RST (SC_ALTCTL[0]) is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARST_EN Warm Reset Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register. 0x4 read-write n 0x0 0x0 AUTO_CON_EN Auto Convention Enable Control\n 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL (SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CON_SEL (SC_CTL[5:4]) will be set to 11 #1 BGT Block Guard Time (BGT)\n\nIn RX mode, software can enable RX_BGT_EN (SC_ALTCTL[12]) to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\nNote: The real block guard time is BGT + 1. 8 5 read-write CD_DEB_SEL Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks #00 1 De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks #01 2 De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks #10 3 De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks #11 CON_SEL Convention Selection\nNote: If AUTO_CON_EN (SC_CTL[3]) enabled, this fields are ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 DIS_RX RX Transition Disable Control\nNote: If AUTO_CON_EN (SC_CTL[3]) is enabled, these fields must be ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 DIS_TX TX Transition Disable Control\n 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 RX_ERETRY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. 16 3 read-write RX_ERETRY_EN RX Error Retry Enable Control\n 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RX_FTRI_LEV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if RDA_IEN (IER[0]) is enabled, an interrupt will be generated).\n 6 2 read-write 0 INTR_RDA Trigger Level with 01 byte #00 1 INTR_RDA Trigger Level with 02 bytes #01 2 INTR_RDA Trigger Level with 03 bytes #10 3 Reserved #11 SC_CEN SC Engine Enable Control\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state 0 1 read-write SLEN Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 TMR_SEL Timer Selection \n 13 2 read-write 0 All internal timer function Disabled #00 1 Internal 24-bit timer Enabled. Software can configure it by setting SC_TMR0[23:0]. SC_TMR1 and SC_TMR2 will be ignored in this mode #01 2 internal 24-bit timer and 8-bit internal timer Enabled. Software can configure the 24-bit timer by setting SC_TMR0[23:0] and configure the 8-bit timer by setting SC_TMR1[7:0]. SC_TMR2 will be ignored in this mode #10 3 Internal 24-bit timer and two 8-bit timers Enabled. Software can configure them by setting SC_TMR0[23:0], SC_TMR1[7:0] and SC_TMR2[7:0] #11 TX_ERETRY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value. 20 3 read-write TX_ERETRY_EN TX Error Retry Enable Control\nThis bit enables transmitter retry function when parity error has occurred.\n 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_EGTR SC_EGTR SC Extend Guard Time Register. 0xC read-write n 0x0 0x0 EGT Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT. 0 8 read-write SC_ETUCR SC_ETUCR SC ETU Control Register. 0x14 -1 read-write n 0x0 0x0 COMPEN_EN Compensation Mode Enable Control\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETU_RDIV .\n 15 1 read-write 0 Compensation function Disabled #0 1 Compensation function Enabled #1 ETU_RDIV ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004. 0 12 read-write SC_IER SC_IER SC Interrupt Enable Control Register. 0x18 read-write n 0x0 0x0 ACON_ERR_IE Auto Convention Error Interrupt Enable Control \nThis field is used for auto-convention error interrupt enable.\n 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGT_IE Block Guard Time Interrupt Enable Control\nThis field is used for block guard time interrupt enable.\n 6 1 read-write 0 Block guard time Disabled #0 1 Block guard time Enabled #1 CD_IE Card Detect Interrupt Enable Control\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F (SC_SR[12]) \n 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INIT_IE Initial End Interrupt Enable Control\n 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDA_IE Receive Data Reach Interrupt Enable Control\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RTMR_IE Receiver Buffer Time-Out Interrupt Enable Control \nThis field is used for receiver buffer time-out interrupt enable.\n 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBE_IE Transmit Buffer Empty Interrupt Enable Control\nThis field is used for transmit buffer empty interrupt enable.\n 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERR_IE Transfer Error Interrupt Enable Control\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]), frame error RX_EFR_F (SC_SR[5]), parity error RX_EPA_F (SC_SR[4]), receiver buffer overflow error RX_OVER_F (SC_SR[0]), transmit buffer overflow error TX_OVER_F (SC_SR[8]), receiver retry over limit error RX_OVER_REERR (SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR (SC_SR[30]).\n 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0_IE Timer0 Interrupt Enable Control\nThis field is used to enable the TMR0 interrupt.\n 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1_IE Timer1 Interrupt Enable Control\nThis field is used to enable the TMR1 interrupt.\n 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2_IE Timer2 Interrupt Enable Control\nThis field is used for TMR2 interrupt enable.\n 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SC_ISR SC_ISR SC Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 ACON_ERR_IS Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 10 1 read-only BGT_IS \n 6 1 read-only CD_IS Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F (SC_SR[11]). Note: This field is the status flag of CD_INS_F (SC_SR[12]), CD_INS_F (SC_PINCSR[3]) or CD_REM_F (SC_SR[11]). So if software wants to clear this bit, software must write 1 to this field. 7 1 read-only INIT_IS Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN (SC_ALTCTL[3])), deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only RDA_IS Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). If software reads data from SC_RBR and receiver buffer data byte number is less than RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically. 0 1 read-only RTMR_IS Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_RBR buffer, 9 1 read-only TBE_IS Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_THR buffer and then this bit will be cleared automatically. 1 1 read-only TERR_IS Transfer Error Interrupt Status Flag (Read Only) This field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]), frame error RX_EFR_F (SC_SR[5]), parity error RX_EPA_F (SC_SR[4]) and receiver buffer overflow error RX_OVER_F (SC_SR[0]), transmit buffer overflow error TX_OVER_F (SC_SR[8]), receiver retry over limit error RX_OVER_REERR (SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR (SC_SC[30]). Note: This field is the status flag of RX_EBR_F(SC_SR[6]), RX_EFR_F (SC_SR[5]), RX_EPA_F (SC_SR[4]), RX_OVER_F (SC_SR[0]), TX_OVER_F (SC_SR[8]), RX_OVER_REERR (SC_SR[22] or TX_OVER_REERR (SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field. 2 1 read-only TMR0_IS Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 3 1 read-only TMR1_IS Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 4 1 read-only TMR2_IS Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 5 1 read-only SC_PINCSR SC_PINCSR SC Pin Control State Register. 0x24 read-write n 0x0 0x0 ADAC_CD_EN Auto Deactivation When Card Removal\nNote: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU. 7 1 read-write 0 Auto deactivation Disabled when hardware detected the card is removal #0 1 Auto deactivation Enabled when hardware detected the card is removal #1 CD_INS_F Card Detect Insert Status Of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 3 1 read-only 0 No effect #0 1 Card insert #1 CD_LEV Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable 10 1 read-write 0 When hardware detects the card detect pin from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin from low to high, it indicates a card is detected #1 CD_PIN_ST Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n 4 1 read-only 0 SC_CD pin state at low #0 1 SC_CD pin state at high #1 CD_REM_F Card Detect Removal Status Of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 2 1 read-only 0 No effect #0 1 Card Removal #1 CLK_KEEP SC Clock Enable Control \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 POW_EN SC_POW_EN Pin Signal\nSoftware can set POW_EN and POW_INV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 0 1 read-write 0 SC_PWR pin status is low #0 1 SC_PWR pin status is high #1 SC_DATA_I_ST SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I\n 16 1 read-only 0 The SC_DATA_I pin is low #0 1 The SC_DATA_I pin is high #1 SC_DATA_O SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes. 9 1 read-write 0 Drive SC_DATA_O pin to low #0 1 Drive SC_DATA_O pin to high #1 SC_OEN_ST SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n 8 1 read-only 0 The SC_DATA_OEN pin state at low #0 1 The SC_DATA_OEN pin state at high #1 SC_RST SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST pin status is low #0 1 Drive SC_RST pin to high.\nSC_RST pin status is high #1 SC_RBR SC_RBR SC Receiving Buffer Register. 0x0 read-only n 0x0 0x0 RBR Receiving Buffer \nBy reading RBR, the SC will return an 8-bit received data. 0 8 read-only SC_RFTMR SC_RFTMR SC Receive Buffer Time-out Register. 0x10 read-write n 0x0 0x0 RFTM SC Receiver Buffer Time-Out (ETU Base) Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5 Note2: Fill all 0 to this field indicates to disable this function. 0 9 read-write SC_TDRA SC_TDRA SC Timer Current Data Register A. 0x38 -1 read-only n 0x0 0x0 TDR0 Timer0 Current Data Value (Read Only)\nThis field indicates the current count values of Timer0. 0 24 read-only SC_TDRB SC_TDRB SC Timer Current Data Register B. 0x3C -1 read-only n 0x0 0x0 TDR1 Timer1 Current Data Value (Read Only)\nThis field indicates the current count values of Timer1. 0 8 read-only TDR2 Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of Timer2. 8 8 read-only SC_THR SC_THR SC Transmit Holding Register. SC_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Buffer\nBy writing data to THR, the SC will send out an 8-bit data.\nNote: If SC_CEN (SC_CTL[0]) is not enabled, THR cannot be programmed. 0 8 write-only SC_TMR0 SC_TMR0 SC Internal Timer Control Register 0. 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 24 read-write MODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection. 24 4 read-write SC_TMR1 SC_TMR1 SC Internal Timer Control Register 1. 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 8 read-write MODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection. 24 4 read-write SC_TMR2 SC_TMR2 SC Internal Timer Control Register 2. 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 8 read-write MODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection 24 4 read-write SC_TRSR SC_TRSR SC Status Register. 0x20 -1 read-write n 0x0 0x0 CD_INS_F Card Detect Insert Status Of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: The card detect engine will start after SC_CEN (SC_CTL[0]) set. 12 1 read-only 0 No effect #0 1 Card insert #1 CD_PIN_F Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n 13 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CD_REM_F Card Detect Removal Status Of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 11 1 read-only 0 No effect #0 1 Card removed #1 RX_ATV Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished. 23 1 read-only RX_EBR_F Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 6 1 read-only RX_EFR_F Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 5 1 read-only RX_EMPTY_F Receiver Buffer Empty Status Flag (Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data. 1 1 read-only RX_EPA_F Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 4 1 read-only RX_FULL_F Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. 2 1 read-only RX_OVER_F RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 0 1 read-only RX_OVER_REERR Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]), the RX_EPA_F (SC_SR[4]) flag will be ignored (hardware will not set RX_EPA_F (SC_SR[4])). 22 1 read-only RX_POINT_F Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F (SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU, RX_POINT_F (SC_SR[17:16]) decreases one. 16 2 read-only RX_REERR Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RX_ERETRY_EN (SC_CTL[19]) , the RX_EPA_F (SC_SR[4]) flag will be ignored (hardware will not set RX_EPA_F (SC_SR[4])). 21 1 read-only TX_ATV Transmit In Active Status Flag (Read Only)\n 31 1 read-only 0 This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed #0 1 This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted #1 TX_EMPTY_F Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty). 9 1 read-only TX_FULL_F Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. 10 1 read-only TX_OVER_F TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to SC_THR will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only TX_OVER_REERR Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 30 1 read-only TX_POINT_F Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one. 24 2 read-only TX_REERR Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-only SC_UACTL SC_UACTL SC UART Mode Control Register. 0x34 read-write n 0x0 0x0 DATA_LEN Data Length\nNote: In smart card mode, this DATA_LEN must be '00' 4 2 read-write 0 Character Data Length is 8 bits #00 1 Character Data Length is 7 bits #01 2 Character Data length is 6 bits #10 3 Character Data Length is 5 bits #11 OPE Odd Parity Enable Control\nNote: This bit has effect only when PBDIS bit is '0'. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBDIS Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit) 6 1 read-write 0 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UA_MODE_EN UART Mode Enable Control\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 SC1 SC Register Map SC 0x0 0x0 0x40 registers n SC_ALTCTL SC_ALTCTL SC Alternate Control Register. 0x8 read-write n 0x0 0x0 ACT_EN Activation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 3 1 read-write 0 No effect #0 1 Activation sequence generator Enabled #1 DACT_EN Deactivation Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INIT_IS(SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 2 1 read-write 0 No effect #0 1 Deactivation sequence generator Enabled #1 INIT_SEL Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: Refer to SC Activation Sequence in 5.14.4.1.\nWarm-reset: refer to Warm-Reset Sequence in 5.14.4.1\nDeactivation: refer to Deactivation Sequence in 5.14.4.1 8 2 read-write OUTSEL Smartcard Data Pin Output Mode Selection\nUse this bit to select smartcard data pin output mode\n 16 1 read-write 0 Quasi mode #0 1 Open-drain mode #1 RX_BGT_EN Receiver Block Guard Time Function Enable Control\n 12 1 read-write 0 Receiver block guard time function Disabled #0 1 Receiver block guard time function Enabled #1 RX_RST Rx Software Reset\nWhen RX_RST (SC_ALTCTL[1]) is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 1 1 read-write 0 No effect #0 1 Reset the Rx internal state machine and pointers #1 TMR0_ATV Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n 13 1 read-only 0 Timer0 is not active #0 1 Timer0 is active #1 TMR0_SEN Internal Timer0 Start Enable Control\nThis bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 5 1 read-write 0 Stop counting #0 1 Start counting #1 TMR1_ATV Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n 14 1 read-only 0 Timer1 is not active #0 1 Timer1 is active #1 TMR1_SEN Internal Timer1 Start Enable Control\nThis bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 6 1 read-write 0 Stop counting #0 1 Start counting #1 TMR2_ATV Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n 15 1 read-only 0 Timer2 is not active #0 1 Timer2 is active #1 TMR2_SEN Internal Timer2 Start Enable Control\nThis bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.\nNote3: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote4: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed. 7 1 read-write 0 Stop counting #0 1 Start counting #1 TX_RST TX Software Reset\nWhen TX_RST (SC_ALTCTL[0]) is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete. 0 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WARST_EN Warm Reset Sequence Generator Enable Control\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INIT_IS (SC_ISR[8]) will be set to 1.\nNote2: This field will be cleared by TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]). So don't fill these two bits TX_RST (SC_ALTCTL[0]) and RX_RST (SC_ALTCTL[1]) at the same time.\nNote3: If SC_CEN (SC_CTL[0]) is not enabled, this filed cannot be programmed 4 1 read-write 0 No effect #0 1 Warm reset sequence generator Enabled #1 SC_CTL SC_CTL SC Control Register. 0x4 read-write n 0x0 0x0 AUTO_CON_EN Auto Convention Enable Control\n 3 1 read-write 0 Auto-convention Disabled #0 1 Auto-convention Enabled. When hardware receives TS in answer to reset state and the TS is direct convention, CON_SEL (SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CON_SEL (SC_CTL[5:4]) will be set to 11 #1 BGT Block Guard Time (BGT)\n\nIn RX mode, software can enable RX_BGT_EN (SC_ALTCTL[12]) to detect the first coming character timing. If the incoming data timing less than BGT, an interrupt will be generated.\nNote: The real block guard time is BGT + 1. 8 5 read-write CD_DEB_SEL Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n 24 2 read-write 0 De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks #00 1 De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks #01 2 De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks #10 3 De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks #11 CON_SEL Convention Selection\nNote: If AUTO_CON_EN (SC_CTL[3]) enabled, this fields are ignored. 4 2 read-write 0 Direct convention #00 1 Reserved #01 2 Reserved #10 3 Inverse convention #11 DIS_RX RX Transition Disable Control\nNote: If AUTO_CON_EN (SC_CTL[3]) is enabled, these fields must be ignored. 1 1 read-write 0 The receiver Enabled #0 1 The receiver Disabled #1 DIS_TX TX Transition Disable Control\n 2 1 read-write 0 The transceiver Enabled #0 1 The transceiver Disabled #1 RX_ERETRY RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RX_ERETRY_EN enabled. The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value. 16 3 read-write RX_ERETRY_EN RX Error Retry Enable Control\n 19 1 read-write 0 RX error retry function Disabled #0 1 RX error retry function Enabled #1 RX_FTRI_LEV Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RX_FTRI_LEV, the RDA_IF will be set (if RDA_IEN (IER[0]) is enabled, an interrupt will be generated).\n 6 2 read-write 0 INTR_RDA Trigger Level with 01 byte #00 1 INTR_RDA Trigger Level with 02 bytes #01 2 INTR_RDA Trigger Level with 03 bytes #10 3 Reserved #11 SC_CEN SC Engine Enable Control\nSet this bit to 1 to enable SC operation. If this bit is cleared, SC will force all transition to IDLE state 0 1 read-write SLEN Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2. SMC and UART adopts SLEN to program the stop bit length 15 1 read-write 0 The stop bit length is 2 ETU #0 1 The stop bit length is 1 ETU #1 TMR_SEL Timer Selection \n 13 2 read-write 0 All internal timer function Disabled #00 1 Internal 24-bit timer Enabled. Software can configure it by setting SC_TMR0[23:0]. SC_TMR1 and SC_TMR2 will be ignored in this mode #01 2 internal 24-bit timer and 8-bit internal timer Enabled. Software can configure the 24-bit timer by setting SC_TMR0[23:0] and configure the 8-bit timer by setting SC_TMR1[7:0]. SC_TMR2 will be ignored in this mode #10 3 Internal 24-bit timer and two 8-bit timers Enabled. Software can configure them by setting SC_TMR0[23:0], SC_TMR1[7:0] and SC_TMR2[7:0] #11 TX_ERETRY TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TX_ERETRY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TX_ERETRY_EN enabled. The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value. 20 3 read-write TX_ERETRY_EN TX Error Retry Enable Control\nThis bit enables transmitter retry function when parity error has occurred.\n 23 1 read-write 0 TX error retry function Disabled #0 1 TX error retry function Enabled #1 SC_EGTR SC_EGTR SC Extend Guard Time Register. 0xC read-write n 0x0 0x0 EGT Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT. 0 8 read-write SC_ETUCR SC_ETUCR SC ETU Control Register. 0x14 -1 read-write n 0x0 0x0 COMPEN_EN Compensation Mode Enable Control\nThis bit enables clock compensation function. When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETU_RDIV .\n 15 1 read-write 0 Compensation function Disabled #0 1 Compensation function Enabled #1 ETU_RDIV ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETU_RDIV + 1.\nNote: Software can configure this field, but this field must be greater than 0x004. 0 12 read-write SC_IER SC_IER SC Interrupt Enable Control Register. 0x18 read-write n 0x0 0x0 ACON_ERR_IE Auto Convention Error Interrupt Enable Control \nThis field is used for auto-convention error interrupt enable.\n 10 1 read-write 0 Auto-convention error interrupt Disabled #0 1 Auto-convention error interrupt Enabled #1 BGT_IE Block Guard Time Interrupt Enable Control\nThis field is used for block guard time interrupt enable.\n 6 1 read-write 0 Block guard time Disabled #0 1 Block guard time Enabled #1 CD_IE Card Detect Interrupt Enable Control\nThis field is used for card detect interrupt enable. The card detect status is CD_INS_F (SC_SR[12]) \n 7 1 read-write 0 Card detect interrupt Disabled #0 1 Card detect interrupt Enabled #1 INIT_IE Initial End Interrupt Enable Control\n 8 1 read-write 0 Initial end interrupt Disabled #0 1 Initial end interrupt Enabled #1 RDA_IE Receive Data Reach Interrupt Enable Control\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt enable.\n 0 1 read-write 0 Receive data reach trigger level interrupt Disabled #0 1 Receive data reach trigger level interrupt Enabled #1 RTMR_IE Receiver Buffer Time-Out Interrupt Enable Control \nThis field is used for receiver buffer time-out interrupt enable.\n 9 1 read-write 0 Receiver buffer time-out interrupt Disabled #0 1 Receiver buffer time-out interrupt Enabled #1 TBE_IE Transmit Buffer Empty Interrupt Enable Control\nThis field is used for transmit buffer empty interrupt enable.\n 1 1 read-write 0 Transmit buffer empty interrupt Disabled #0 1 Transmit buffer empty interrupt Enabled #1 TERR_IE Transfer Error Interrupt Enable Control\nThis field is used for transfer error interrupt enable. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]), frame error RX_EFR_F (SC_SR[5]), parity error RX_EPA_F (SC_SR[4]), receiver buffer overflow error RX_OVER_F (SC_SR[0]), transmit buffer overflow error TX_OVER_F (SC_SR[8]), receiver retry over limit error RX_OVER_REERR (SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR (SC_SR[30]).\n 2 1 read-write 0 Transfer error interrupt Disabled #0 1 Transfer error interrupt Enabled #1 TMR0_IE Timer0 Interrupt Enable Control\nThis field is used to enable the TMR0 interrupt.\n 3 1 read-write 0 Timer0 interrupt Disabled #0 1 Timer0 interrupt Enabled #1 TMR1_IE Timer1 Interrupt Enable Control\nThis field is used to enable the TMR1 interrupt.\n 4 1 read-write 0 Timer1 interrupt Disabled #0 1 Timer1 interrupt Enabled #1 TMR2_IE Timer2 Interrupt Enable Control\nThis field is used for TMR2 interrupt enable.\n 5 1 read-write 0 Timer2 interrupt Disabled #0 1 Timer2 interrupt Enabled #1 SC_ISR SC_ISR SC Interrupt Status Register. 0x1C -1 read-write n 0x0 0x0 ACON_ERR_IS Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 10 1 read-only BGT_IS \n 6 1 read-only CD_IS Card Detect Interrupt Status Flag (Read Only) This field is used for card detect interrupt status flag. The card detect status is CD_INS_F (SC_SR[12]) and CD_REM_F (SC_SR[11]). Note: This field is the status flag of CD_INS_F (SC_SR[12]), CD_INS_F (SC_PINCSR[3]) or CD_REM_F (SC_SR[11]). So if software wants to clear this bit, software must write 1 to this field. 7 1 read-only INIT_IS Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACT_EN (SC_ALTCTL[3])), deactivation (DACT_EN (SC_ALTCTL[2])) and warm reset (WARST_EN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only RDA_IS Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RX_FTRI_LEV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RX_FTRI_LEV (SC_CTL[7:6]). If software reads data from SC_RBR and receiver buffer data byte number is less than RX_FTRI_LEV (SC_CTL[7:6]), this bit will be cleared automatically. 0 1 read-only RTMR_IS Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_RBR buffer, 9 1 read-only TBE_IS Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state. If software wants to clear this bit, software must write data to SC_THR buffer and then this bit will be cleared automatically. 1 1 read-only TERR_IS Transfer Error Interrupt Status Flag (Read Only) This field is used for transfer error interrupt status flag. The transfer error states is at SC_SR register which includes receiver break error RX_EBR_F (SC_SR[6]), frame error RX_EFR_F (SC_SR[5]), parity error RX_EPA_F (SC_SR[4]) and receiver buffer overflow error RX_OVER_F (SC_SR[0]), transmit buffer overflow error TX_OVER_F (SC_SR[8]), receiver retry over limit error RX_OVER_REERR (SC_SR[22]) and transmitter retry over limit error TX_OVER_REERR (SC_SC[30]). Note: This field is the status flag of RX_EBR_F(SC_SR[6]), RX_EFR_F (SC_SR[5]), RX_EPA_F (SC_SR[4]), RX_OVER_F (SC_SR[0]), TX_OVER_F (SC_SR[8]), RX_OVER_REERR (SC_SR[22] or TX_OVER_REERR (SC_SC[30]). So, if software wants to clear this bit, software must write 1 to each field. 2 1 read-only TMR0_IS Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 3 1 read-only TMR1_IS Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 4 1 read-only TMR2_IS Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 5 1 read-only SC_PINCSR SC_PINCSR SC Pin Control State Register. 0x24 read-write n 0x0 0x0 ADAC_CD_EN Auto Deactivation When Card Removal\nNote: When the card is removal, hardware will stop any process and then do deactivation sequence (if this bit be setting). If this process completes. Hardware will generate an interrupt INT_INIT to CPU. 7 1 read-write 0 Auto deactivation Disabled when hardware detected the card is removal #0 1 Auto deactivation Enabled when hardware detected the card is removal #1 CD_INS_F Card Detect Insert Status Of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 3 1 read-only 0 No effect #0 1 Card insert #1 CD_LEV Card Detect Level\n\nNote: Software must select card detect level before Smart Card engine enable 10 1 read-write 0 When hardware detects the card detect pin from high to low, it indicates a card is detected #0 1 When hardware detects the card detect pin from low to high, it indicates a card is detected #1 CD_PIN_ST Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n 4 1 read-only 0 SC_CD pin state at low #0 1 SC_CD pin state at high #1 CD_REM_F Card Detect Removal Status Of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 2 1 read-only 0 No effect #0 1 Card Removal #1 CLK_KEEP SC Clock Enable Control \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 6 1 read-write 0 SC clock generation Disabled #0 1 SC clock always keeps free running #1 POW_EN SC_POW_EN Pin Signal\nSoftware can set POW_EN and POW_INV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer POW_INV description for programming SC_PWR pin voltage level. \nRead this field to get SC_PWR pin status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 0 1 read-write 0 SC_PWR pin status is low #0 1 SC_PWR pin status is high #1 SC_DATA_I_ST SC Data Input Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_I\n 16 1 read-only 0 The SC_DATA_I pin is low #0 1 The SC_DATA_I pin is high #1 SC_DATA_O SC Data Output Pin \nThis bit is the pin status of SC_DATA_O but user can drive SC_DATA_O pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when SC is in these modes. 9 1 read-write 0 Drive SC_DATA_O pin to low #0 1 Drive SC_DATA_O pin to high #1 SC_OEN_ST SC Data Output Enable Pin Status (Read Only)\nThis bit is the pin status of SC_DATA_OEN\n 8 1 read-only 0 The SC_DATA_OEN pin state at low #0 1 The SC_DATA_OEN pin state at high #1 SC_RST SC_RST Pin Signal\nThis bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.\nWrite this field to drive SC_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. So don't fill this field when operating in these modes. 1 1 read-write 0 Drive SC_RST pin to low.\nSC_RST pin status is low #0 1 Drive SC_RST pin to high.\nSC_RST pin status is high #1 SC_RBR SC_RBR SC Receiving Buffer Register. 0x0 read-only n 0x0 0x0 RBR Receiving Buffer \nBy reading RBR, the SC will return an 8-bit received data. 0 8 read-only SC_RFTMR SC_RFTMR SC Receive Buffer Time-out Register. 0x10 read-write n 0x0 0x0 RFTM SC Receiver Buffer Time-Out (ETU Base) Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5 Note2: Fill all 0 to this field indicates to disable this function. 0 9 read-write SC_TDRA SC_TDRA SC Timer Current Data Register A. 0x38 -1 read-only n 0x0 0x0 TDR0 Timer0 Current Data Value (Read Only)\nThis field indicates the current count values of Timer0. 0 24 read-only SC_TDRB SC_TDRB SC Timer Current Data Register B. 0x3C -1 read-only n 0x0 0x0 TDR1 Timer1 Current Data Value (Read Only)\nThis field indicates the current count values of Timer1. 0 8 read-only TDR2 Timer2 Current Data Value (Read Only)\nThis field indicates the current count values of Timer2. 8 8 read-only SC_THR SC_THR SC Transmit Holding Register. SC_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Buffer\nBy writing data to THR, the SC will send out an 8-bit data.\nNote: If SC_CEN (SC_CTL[0]) is not enabled, THR cannot be programmed. 0 8 write-only SC_TMR0 SC_TMR0 SC Internal Timer Control Register 0. 0x28 read-write n 0x0 0x0 CNT Timer 0 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 24 read-write MODE Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection. 24 4 read-write SC_TMR1 SC_TMR1 SC Internal Timer Control Register 1. 0x2C read-write n 0x0 0x0 CNT Timer 1 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 8 read-write MODE Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection. 24 4 read-write SC_TMR2 SC_TMR2 SC Internal Timer Control Register 2. 0x30 read-write n 0x0 0x0 CNT Timer 2 Counter Value (ETU Base) This field indicates the internal timer operation values. 0 8 read-write MODE Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection 24 4 read-write SC_TRSR SC_TRSR SC Status Register. 0x20 -1 read-write n 0x0 0x0 CD_INS_F Card Detect Insert Status Of SC_CD Pin (Read Only) This bit is set whenever card has been inserted. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: The card detect engine will start after SC_CEN (SC_CTL[0]) set. 12 1 read-only 0 No effect #0 1 Card insert #1 CD_PIN_F Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n 13 1 read-only 0 The SC_CD pin state at low #0 1 The SC_CD pin state at high #1 CD_REM_F Card Detect Removal Status Of SC_CD Pin (Read Only) This bit is set whenever card has been removal. Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: Card detect engine will start after SC_CEN (SC_CTL[0]) set. 11 1 read-only 0 No effect #0 1 Card removed #1 RX_ATV Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished. 23 1 read-only RX_EBR_F Receiver Break Error Status Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 6 1 read-only RX_EFR_F Receiver Frame Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 5 1 read-only RX_EMPTY_F Receiver Buffer Empty Status Flag (Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when SC receives any new data. 1 1 read-only RX_EPA_F Receiver Parity Error Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but it can be cleared by writing 1 to it. Note2: If CPU sets receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]) , hardware will not set this flag. 4 1 read-only RX_FULL_F Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware. 2 1 read-only RX_OVER_F RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 0 1 read-only RX_OVER_REERR Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RX_ERETRY_EN (SC_CTL[19]), the RX_EPA_F (SC_SR[4]) flag will be ignored (hardware will not set RX_EPA_F (SC_SR[4])). 22 1 read-only RX_POINT_F Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag. When SC receives one byte from external device, RX_POINT_F (SC_SR[17:16]) increases one. When one byte of RX buffer is read by CPU, RX_POINT_F (SC_SR[17:16]) decreases one. 16 2 read-only RX_REERR Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retry function by setting RX_ERETRY_EN (SC_CTL[19]) , the RX_EPA_F (SC_SR[4]) flag will be ignored (hardware will not set RX_EPA_F (SC_SR[4])). 21 1 read-only TX_ATV Transmit In Active Status Flag (Read Only)\n 31 1 read-only 0 This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed #0 1 This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted #1 TX_EMPTY_F Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into SC_THR (TX buffer not empty). 9 1 read-only TX_FULL_F Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware. 10 1 read-only TX_OVER_F TX Overflow Error Interrupt Status Flag (Read Only) If TX buffer is full, an additional write to SC_THR will cause this bit be set to 1 by hardware. Note: This bit is read only, but it can be cleared by writing 1 to it. 8 1 read-only TX_OVER_REERR Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only, but it can be cleared by writing 1 to it. 30 1 read-only TX_POINT_F Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag. When CPU writes data into SC_THR, TX_POINT_F increases one. When one byte of TX Buffer is transferred to transmitter shift register, TX_POINT_F decreases one. 24 2 read-only TX_REERR Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU. 29 1 read-only SC_UACTL SC_UACTL SC UART Mode Control Register. 0x34 read-write n 0x0 0x0 DATA_LEN Data Length\nNote: In smart card mode, this DATA_LEN must be '00' 4 2 read-write 0 Character Data Length is 8 bits #00 1 Character Data Length is 7 bits #01 2 Character Data length is 6 bits #10 3 Character Data Length is 5 bits #11 OPE Odd Parity Enable Control\nNote: This bit has effect only when PBDIS bit is '0'. 7 1 read-write 0 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 PBDIS Parity Bit Disable Control\nNote: In smart card mode, this field must be '0' (default setting is with parity bit) 6 1 read-write 0 Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 1 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer #1 UA_MODE_EN UART Mode Enable Control\nNote3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine. 0 1 read-write 0 Smart Card mode #0 1 UART mode #1 SCS SCS Register Map SCS 0x0 0x10 0xC registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x200 0x4 registers n 0x280 0x4 registers n 0x400 0x20 registers n 0xD00 0x8 registers n 0xD0C 0x8 registers n 0xD1C 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xD0C -1 read-write n 0x0 0x0 SYSRESETREQ Writing This Bit 1 Will Cause A Reset Signal To Be Asserted To The Chip To Indicate A Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Set This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack. 1 1 read-write VECTORKEY When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable. 16 16 read-write CPUID CPUID CPUID Base Register 0xD00 -1 read-only n 0x0 0x0 IMPLEMENTER None 24 8 read-only PART Reads as 0xC for ARMv6-M parts 16 4 read-only PARTNO Reads as 0xC20. 4 12 read-only REVISION Reads as 0x0 0 4 read-only ICSR ICSR Interrupt Control State Register 0xD04 read-write n 0x0 0x0 ISRPENDING Indicates if an external configurable (NVIC generated) interrupt is pending. 22 1 read-write ISRPREEMPT If set, a pending exception will be serviced on exit from the debug halt state. 23 1 read-write NMIPENDSET Setting This Bit Will Activate An NMI\nSince NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 31 1 read-write PENDSTCLR Write 1 to clear a pending SysTick. 25 1 read-write PENDSTSET Set A Pending SysTick Reads back with current state (1 if Pending, 0 if not). 26 1 read-write PENDSVCLR Write 1 to clear a pending PendSV interrupt. 27 1 read-write PENDSVSET Set A Pending PendSV Interrupt\nThis is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not). 28 1 read-write VECTACTIVE If value of VECTACTIVE 1: the exception number for the current executing exception. 0 9 read-write 0 Thread mode 0 VECTPENDING Indicates The Exception Number For The Highest Priority Pending Exception\nThe pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions. 12 9 read-write NVIC_ICER NVIC_ICER IRQ0~IRQ31 Clear-enable Control Register 0x180 read-write n 0x0 0x0 CLRENA Disable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ICPR NVIC_ICPR IRQ0~IRQ31 Clear-pending Control Register 0x280 read-write n 0x0 0x0 CLRPEND Writing 1 To A Bit To Remove The Pending State Of Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write NVIC_IPR0 NVIC_IPR0 IRQ0~IRQ3 Priority Control Register 0x400 read-write n 0x0 0x0 PRI_0 Priority Of IRQ0 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_1 Priority Of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_2 Priority Of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_3 Priority Of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR1 NVIC_IPR1 IRQ4~IRQ7 Priority Control Register 0x404 read-write n 0x0 0x0 PRI_4 Priority Of IRQ4 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_5 Priority Of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_6 Priority Of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_7 Priority Of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR2 NVIC_IPR2 IRQ8~IRQ11 Priority Control Register 0x408 read-write n 0x0 0x0 PRI_10 Priority Of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_11 Priority Of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write PRI_8 Priority Of IRQ8 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_9 Priority Of IRQ9 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write NVIC_IPR3 NVIC_IPR3 IRQ12~IRQ15 Priority Control Register 0x40C read-write n 0x0 0x0 PRI_12 Priority Of IRQ12 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_13 Priority Of IRQ13 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_14 Priority Of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority Of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR4 NVIC_IPR4 IRQ16~IRQ19 Priority Control Register 0x410 read-write n 0x0 0x0 PRI_16 Priority Of IRQ16 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_17 Priority Of IRQ17 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_18 Priority Of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_19 Priority Of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR5 NVIC_IPR5 IRQ20~IRQ23 Priority Control Register 0x414 read-write n 0x0 0x0 PRI_20 Priority Of IRQ20 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_21 Priority Of IRQ21 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_22 Priority Of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_23 Priority Of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR6 NVIC_IPR6 IRQ24~IRQ27 Priority Control Register 0x418 read-write n 0x0 0x0 PRI_24 Priority Of IRQ24 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_25 Priority Of IRQ25 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_26 Priority Of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_27 Priority Of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_IPR7 NVIC_IPR7 IRQ28~IRQ31 Priority Control Register 0x41C read-write n 0x0 0x0 PRI_28 Priority Of IRQ28 0 denotes the highest priority and 3 denotes the lowest priority. 6 2 read-write PRI_29 Priority Of IRQ29 0 denotes the highest priority and 3 denotes the lowest priority. 14 2 read-write PRI_30 Priority Of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_31 Priority Of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write NVIC_ISER NVIC_ISER IRQ0~IRQ31 Set-enable Control Register 0x100 read-write n 0x0 0x0 SETENA Enable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state. 0 32 read-write NVIC_ISPR NVIC_ISPR IRQ0~IRQ31 Set-pending Control Register 0x200 read-write n 0x0 0x0 SETPEND Writing 1 To A Bit To Set Pending State Of The Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state. 0 32 read-write SCR SCR System Control Register 0xD10 read-write n 0x0 0x0 SEVONPEND When enabled, interrupt transitions from Inactive to Pending are included in the list of wake-up events for the WFE instruction. 4 1 read-write SLEEPDEEP A qualifying hint that indicates waking from sleep might take longer. 2 1 read-write SLEEPONEXIT When Set To 1, The Core Can Enter A Sleep State On An Exception Return To Thread Mode This is the mode and exception level entered at reset, the base level of execution. 1 1 read-write SHPR2 SHPR2 System Handler Priority Register 2 0xD1C read-write n 0x0 0x0 PRI_11 Priority Of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0xD20 read-write n 0x0 0x0 PRI_14 Priority Of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes the lowest priority. 22 2 read-write PRI_15 Priority Of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes the lowest priority. 30 2 read-write SYST_CTL SYST_CTL SysTick Control and Status 0x10 -1 read-write n 0x0 0x0 CLKSRC None 2 1 read-write 0 Clock Source is (optional) external reference clock #0 1 Core clock used for SysTick If no external clock provided, this bit will read as 1 and ignore writes #1 COUNTFLAG Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\n COUNTFLAG is set by a count transition from 1 to 0.\n COUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE None 0 1 read-write 0 The counter is Disabled #0 1 The counter will operate in a multi-shot manner #1 TICKINT None 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 SYST_CVR SYST_CVR SysTick Current Value 0x18 read-write n 0x0 0x0 CURRENT Current Counter Value \nThis is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (Read As Zero, writes ignore) (See SysTick Reload Value register). 0 24 read-write SYST_RVR SYST_RVR SysTick Reload Value Register 0x14 read-write n 0x0 0x0 RELOAD The value to load into the Current Value register when the counter reaches 0. 0 24 read-write SPI0 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x34 0xC registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER1 Clock Divider 1 Register \nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/\n\nNote 1: The DIVIDER1 can be set as 0. If the DIVIDER1 is set as zero, the frequency of SPI_SCLK is the same as PCLK in Master mode.\nNote 2: In Slave mode, the period of SPI clock driven by a master shall equal to or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register \nThe value is the 2nd 2nd frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/ 16 16 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SPICLK is low #0 1 The default level of SPICLK is high #1 FIFOM FIFO Mode Enable\nNote: Refer to Dual FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GO_BUSY Go And Busy Status During the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Note 1: All registers should be set before writing 1 to the GO_BUSY bit in the SPI_CTL register. Note 2: In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.. 0 1 read-write 0 Writing this bit 0 to stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master #1 INTEN Interrupt Enable\n 17 1 read-write 0 SPI Interrupt Disabled #0 1 SPI Interrupt Enabled #1 LSB Send LSB First\nNote: Refer to LSB First section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1) #1 REORDER Reorder Mode Selection\nNote: The suspend interval is defined in SP_CYCLE 19 2 read-write 0 Disable both byte reorder and suspend functions #00 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word) #01 2 Enable byte reorder function, but disable byte suspend function #10 3 Disable byte reorder function, but insert a suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word) #11 RX_NEG Receive At Negative Edge\nNote: Refer to Edge Condition section. 1 1 read-write 0 The received data is latched at the rising edge of SPICLK #0 1 The received data is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller is set as Master mode #0 1 SPI controller is set as Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\n 12 4 read-write TWOB 2 Data Channel Transfer Mode Active\nNote: When enabling TWOB, the setting of TX_NUM must be programmed as 00. 22 1 read-write 0 2data channel transfer mode Disabled #0 1 2data channel transfer mode Enabled #1 TX_BIT_LEN Transmit Bit Length\n 3 5 read-write TX_NEG Transmit At Negative Edge\nNote: Refer to Edge Condition section. 2 1 read-write 0 The transmitted data output is changed at the rising edge of SPICLK #0 1 The transmitted data output is changed at the falling edge of SPICLK #1 TX_NUM Number Of Transmit/Receive Transaction\n 8 2 read-write VARCLK_EN Variable Clock Enable\nNote: Refer to Variable Serial Clock Frequency section. 23 1 read-write 0 The serial clock output frequency is fixed and only decided by the value of DIVIDER1 #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1 and DIVIDER2 #1 WKEUP_EN Wake-Up Enable\nNote: When the system enters the power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up, this bit must be clear by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled when the system enters the power-down mode #0 1 Wake-up function Enabled #1 SPI_FFCLR SPI_FFCLR SPI FIFO Counter Clear Control Register 0x3C read-write n 0x0 0x0 RX_CLR Receiving FIFO Counter Clear Note: This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 TX_CLR Transmitting FIFO Counter Clear Note: This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 No clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 SPI_PDMA SPI_PDMA SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMA_RST PDMA Reset It is used to reset the SPI PDMA function into default state. Note: It is auto cleared to 0 after the reset function done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RX_DMA_EN Receiver PDMA Enable (PDMA Reads SPI Data To Memory) Note 1: Refer to DMA section for more detail information. Note 2: Hardware will clear this bit to 0 automatically after PDMA transfer done. Note 3: In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clocks + 4 APB clocks. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TX_DMA_EN Transmit PDMA Enable (PDMA Writes Data To SPI)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\nNote 3: If the 2 data channel function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nNote 4: Hardware will clear this bit to 0 automatically after PDMA transfer done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RXDATA Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1, the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOB mode.\nNote 2: These two registers are read only. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR SPI Slave Select Register 0xC read-write n 0x0 0x0 AUTOSS Automatic Slave Selection (Master Only)\n 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register #0 1 If this bit is set as 1 , SPISS[1:0] signals are generated automatically. It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by setting the GO_BUSY bit, and is de-asserted after each transaction is done #1 NOSLVSEL No Slave Selected In Slave Mode This is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO and SPI_MOSI when it is set as a slave device. Note 1: Refer to No Slave Select Mode. Note 2: In no slave select signal mode, the SS_LTRIG (SPI_SSR[4]) shall be set as 1 . 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input #1 SLV_ABORT Abort In Slave Mode With No Slave Selected Note 1:Refer to No Slave Select Mode. Note 2: It is auto clear to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SSR Slave Select Active Register (Master Only) If AUTOSS bit (SPI_SSR[3]) is cleared, writing 1 to SSR[0] bit sets the SPISS[0] line to an active state and writing 0 sets the line back to inactive state.( the same as SSR[1] for SPISS[1]) Note 1: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer. Note 2: SPISS[0] is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPISS[1] and SPISS[0] are inactive #00 1 SPISS[1] is inactive, SPISS[0] is active.\nSPISS[1] is inactive, SPISS[0] is active on the duration of transaction #01 2 SPISS[1] is active, SPISS[0] is inactive.\nSPISS[1] is active on the duration of transaction, SPISS[0] is inactive #10 3 Both SPISS[1] and SPISS[0] are active.\nBoth SPISS[1] and SPISS[0] are active on the duration of transaction #11 SSTA_INTEN Slave Start Interrupt Enable\nNote : Refer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear) #1 SS_LTRIG Slave Select Level Trigger\n 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nIt defines the active level of device/slave select signals (SPISS[1:0]).\n 2 1 read-write 0 The SPISS slave select signal is active Low #0 1 The SPISS slave select signal is active High #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 INTSTS Interrupt Status Note: This bit is read only, but can be cleared by writing 1 to this bit. 7 1 read-write 0 Transfer is not finished yet #0 1 Transfer is done. The interrupt is requested when the INTEN (SPI_CTL[17]) bit is enabled #1 LTRIG_FLAG Level Trigger Flag (INTERNAL ONLY)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is read only 4 1 read-write 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 RX_EMPTY Received Dual FIFO_EMPTY Status\n 0 1 read-write 0 Received data FIFO is not empty in the dual FIFO mode #0 1 Received data FIFO is empty in the dual FIFO mode #1 RX_FULL Received Dual FIFO_FULL Status\n 1 1 read-write 0 Received data FIFO is not full in dual FIFO mode #0 1 Received data FIFO is full in the dual FIFO mode #1 SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to indicate that the transfer has started in Slave mode with no slave select.\n 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is auto clear by transfer done or writing one clear #1 TX_EMPTY Transmitted Dual FIFO_EMPTY Status\n 2 1 read-write 0 Transmitted data FIFO is not empty in the dual FIFO mode #0 1 Transmitted data FIFO is empty in the dual FIFO mode #1 TX_FULL Transmitted Dual FIFO_FULL Status\n 3 1 read-write 0 Transmitted data FIFO is not full in the dual FIFO mode #0 1 Transmitted data FIFO is full in the dual FIFO mode #1 SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TDATA Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in twodata channel mode. SPI_TX0 shall be written first in TWOB mode. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK SPI Variable Clock Pattern Flag Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK.\n 0 32 read-write SPI1 SPI Register Map SPI 0x0 0x0 0x18 registers n 0x20 0x8 registers n 0x34 0xC registers n SPI_CLKDIV SPI_CLKDIV SPI Clock Divider Register 0x8 read-write n 0x0 0x0 DIVIDER1 Clock Divider 1 Register \nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/\n\nNote 1: The DIVIDER1 can be set as 0. If the DIVIDER1 is set as zero, the frequency of SPI_SCLK is the same as PCLK in Master mode.\nNote 2: In Slave mode, the period of SPI clock driven by a master shall equal to or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK. 0 16 read-write DIVIDER2 Clock Divider 2 Register \nThe value is the 2nd 2nd frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/ 16 16 read-write SPI_CTL SPI_CTL SPI Control Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\nNote: Refer to Clock Parity section. 11 1 read-write 0 The default level of SPICLK is low #0 1 The default level of SPICLK is high #1 FIFOM FIFO Mode Enable\nNote: Refer to Dual FIFO Mode section. 21 1 read-write 0 FIFO mode Disabled (in Normal mode) #0 1 FIFO mode Enabled #1 GO_BUSY Go And Busy Status During the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically. Note 1: All registers should be set before writing 1 to the GO_BUSY bit in the SPI_CTL register. Note 2: In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit.. 0 1 read-write 0 Writing this bit 0 to stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master #1 INTEN Interrupt Enable\n 17 1 read-write 0 SPI Interrupt Disabled #0 1 SPI Interrupt Enabled #1 LSB Send LSB First\nNote: Refer to LSB First section. 10 1 read-write 0 The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first #0 1 The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1) #1 REORDER Reorder Mode Selection\nNote: The suspend interval is defined in SP_CYCLE 19 2 read-write 0 Disable both byte reorder and suspend functions #00 1 Enable byte reorder function and insert a byte suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word) #01 2 Enable byte reorder function, but disable byte suspend function #10 3 Disable byte reorder function, but insert a suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word) #11 RX_NEG Receive At Negative Edge\nNote: Refer to Edge Condition section. 1 1 read-write 0 The received data is latched at the rising edge of SPICLK #0 1 The received data is latched at the falling edge of SPICLK #1 SLAVE Slave Mode Indication\nNote: Refer to Slave Selection section 18 1 read-write 0 SPI controller is set as Master mode #0 1 SPI controller is set as Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\n 12 4 read-write TWOB 2 Data Channel Transfer Mode Active\nNote: When enabling TWOB, the setting of TX_NUM must be programmed as 00. 22 1 read-write 0 2data channel transfer mode Disabled #0 1 2data channel transfer mode Enabled #1 TX_BIT_LEN Transmit Bit Length\n 3 5 read-write TX_NEG Transmit At Negative Edge\nNote: Refer to Edge Condition section. 2 1 read-write 0 The transmitted data output is changed at the rising edge of SPICLK #0 1 The transmitted data output is changed at the falling edge of SPICLK #1 TX_NUM Number Of Transmit/Receive Transaction\n 8 2 read-write VARCLK_EN Variable Clock Enable\nNote: Refer to Variable Serial Clock Frequency section. 23 1 read-write 0 The serial clock output frequency is fixed and only decided by the value of DIVIDER1 #0 1 The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1 and DIVIDER2 #1 WKEUP_EN Wake-Up Enable\nNote: When the system enters the power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up, this bit must be clear by user to disable the wake-up requirement. 31 1 read-write 0 Wake-up function Disabled when the system enters the power-down mode #0 1 Wake-up function Enabled #1 SPI_FFCLR SPI_FFCLR SPI FIFO Counter Clear Control Register 0x3C read-write n 0x0 0x0 RX_CLR Receiving FIFO Counter Clear Note: This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to 1 . 0 1 read-write 0 No clear the received FIFO #0 1 Clear the received FIFO #1 TX_CLR Transmitting FIFO Counter Clear Note: This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to 1 . 1 1 read-write 0 No clear the transmitted FIFO #0 1 Clear the transmitted FIFO #1 SPI_PDMA SPI_PDMA SPI PDMA Control Register 0x38 read-write n 0x0 0x0 PDMA_RST PDMA Reset It is used to reset the SPI PDMA function into default state. Note: It is auto cleared to 0 after the reset function done. 2 1 read-write 0 After reset PDMA function or in normal operation #0 1 Reset PDMA function #1 RX_DMA_EN Receiver PDMA Enable (PDMA Reads SPI Data To Memory) Note 1: Refer to DMA section for more detail information. Note 2: Hardware will clear this bit to 0 automatically after PDMA transfer done. Note 3: In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clocks + 4 APB clocks. 1 1 read-write 0 Receiver PDMA function Disabled #0 1 Receiver PDMA function Enabled #1 TX_DMA_EN Transmit PDMA Enable (PDMA Writes Data To SPI)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\nNote 3: If the 2 data channel function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nNote 4: Hardware will clear this bit to 0 automatically after PDMA transfer done. 0 1 read-write 0 Transmit PDMA function Disabled #0 1 Transmit PDMA function Enabled #1 SPI_RX0 SPI_RX0 SPI Receive Data FIFO Register 0 0x10 read-only n 0x0 0x0 RXDATA Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1, the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOB mode.\nNote 2: These two registers are read only. 0 32 read-only SPI_RX1 SPI_RX1 SPI Receive Data FIFO Register 1 0x14 read-write n 0x0 0x0 SPI_SSR SPI_SSR SPI Slave Select Register 0xC read-write n 0x0 0x0 AUTOSS Automatic Slave Selection (Master Only)\n 3 1 read-write 0 If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register #0 1 If this bit is set as 1 , SPISS[1:0] signals are generated automatically. It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by setting the GO_BUSY bit, and is de-asserted after each transaction is done #1 NOSLVSEL No Slave Selected In Slave Mode This is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO and SPI_MOSI when it is set as a slave device. Note 1: Refer to No Slave Select Mode. Note 2: In no slave select signal mode, the SS_LTRIG (SPI_SSR[4]) shall be set as 1 . 5 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input #1 SLV_ABORT Abort In Slave Mode With No Slave Selected Note 1:Refer to No Slave Select Mode. Note 2: It is auto clear to 0 by hardware when the abort event is active. 8 1 read-write 0 No force the slave abort #0 1 Force the current transfer done in no slave select mode #1 SSR Slave Select Active Register (Master Only) If AUTOSS bit (SPI_SSR[3]) is cleared, writing 1 to SSR[0] bit sets the SPISS[0] line to an active state and writing 0 sets the line back to inactive state.( the same as SSR[1] for SPISS[1]) Note 1: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer. Note 2: SPISS[0] is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software. 0 2 read-write 0 Both SPISS[1] and SPISS[0] are inactive #00 1 SPISS[1] is inactive, SPISS[0] is active.\nSPISS[1] is inactive, SPISS[0] is active on the duration of transaction #01 2 SPISS[1] is active, SPISS[0] is inactive.\nSPISS[1] is active on the duration of transaction, SPISS[0] is inactive #10 3 Both SPISS[1] and SPISS[0] are active.\nBoth SPISS[1] and SPISS[0] are active on the duration of transaction #11 SSTA_INTEN Slave Start Interrupt Enable\nNote : Refer to No Slave Select Mode. 9 1 read-write 0 Transfer start interrupt Disabled in no slave select mode #0 1 Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear) #1 SS_LTRIG Slave Select Level Trigger\n 4 1 read-write 0 The input slave select signal is edge-trigger #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nIt defines the active level of device/slave select signals (SPISS[1:0]).\n 2 1 read-write 0 The SPISS slave select signal is active Low #0 1 The SPISS slave select signal is active High #1 SPI_STATUS SPI_STATUS SPI Status Register 0x4 -1 read-write n 0x0 0x0 INTSTS Interrupt Status Note: This bit is read only, but can be cleared by writing 1 to this bit. 7 1 read-write 0 Transfer is not finished yet #0 1 Transfer is done. The interrupt is requested when the INTEN (SPI_CTL[17]) bit is enabled #1 LTRIG_FLAG Level Trigger Flag (INTERNAL ONLY)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is read only 4 1 read-write 0 The transferred bit length of one transaction does not meet the specified requirement #0 1 The transferred bit length meets the specified requirement which defined in TX_BIT_LEN #1 RX_EMPTY Received Dual FIFO_EMPTY Status\n 0 1 read-write 0 Received data FIFO is not empty in the dual FIFO mode #0 1 Received data FIFO is empty in the dual FIFO mode #1 RX_FULL Received Dual FIFO_FULL Status\n 1 1 read-write 0 Received data FIFO is not full in dual FIFO mode #0 1 Received data FIFO is full in the dual FIFO mode #1 SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to indicate that the transfer has started in Slave mode with no slave select.\n 6 1 read-write 0 Slave started transfer no active #0 1 Transfer has started in Slave mode with no slave select. It is auto clear by transfer done or writing one clear #1 TX_EMPTY Transmitted Dual FIFO_EMPTY Status\n 2 1 read-write 0 Transmitted data FIFO is not empty in the dual FIFO mode #0 1 Transmitted data FIFO is empty in the dual FIFO mode #1 TX_FULL Transmitted Dual FIFO_FULL Status\n 3 1 read-write 0 Transmitted data FIFO is not full in the dual FIFO mode #0 1 Transmitted data FIFO is full in the dual FIFO mode #1 SPI_TX0 SPI_TX0 SPI Transmit Data FIFO Register 0 0x20 write-only n 0x0 0x0 TDATA Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in twodata channel mode. SPI_TX0 shall be written first in TWOB mode. 0 32 write-only SPI_TX1 SPI_TX1 SPI Transmit Data FIFO Register 1 0x24 read-write n 0x0 0x0 SPI_VARCLK SPI_VARCLK SPI Variable Clock Pattern Flag Register 0x34 -1 read-write n 0x0 0x0 VARCLK Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK.\n 0 32 read-write TMR0 TMR Register Map TMR 0x0 0x0 0x1C registers n 0x200 0x18 registers n CMPR TMR0_CMPR Timer 0 Compare Register 0x8 read-write n 0x0 0x0 TMR_CMP Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0 or 1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL[0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. 0 24 read-write CTL TMR0_CTL Timer 0 Control Register 0x0 read-write n 0x0 0x0 ADC_TEEN TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n 8 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled #1 CAP_CNT_MOD Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of Tcapture pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAP_TRG_EN TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN, or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]), or ADC_TEEN(TMRx_CTL[8])) is also set.\n 11 1 read-write 0 TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC #0 1 TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC #1 DBGACK_EN ICE Debug Mode Acknowledge Ineffective Enable\n 3 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged #0 1 ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not #1 EVENT_EDGE Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n 13 1 read-write 0 A falling edge of external event enabling the timer to increase 1 #0 1 A rising edge of external event enabling the timer to increase 1 #1 EVENT_EN Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n 12 1 read-write 0 Timer counting is not controlled by external event pin #0 1 Timer counting is controlled by external event pin #1 EVNT_DEB_EN External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption. 14 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx +1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0. 24 1 read-write 0 Inter-timer trigger mode is disabled #0 1 Inter-timer trigger mode is enabled #1 MODE_SEL Timer Operating Mode Select\n 4 2 read-write PDMA_TEEN TMR_IS Or TCAP_IS Trigger PDMA Enable This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller. 10 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])trigger PDMA Enabled #1 SW_RST Software Reset Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0. Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL[0]) bit #1 TCAP_DEB_EN TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption. 22 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 TCAP_EDGE TCapture Pin Edge Detect Selection\n 18 2 read-write TCAP_EN TCapture Pin Functional Enable This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function. Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high. 16 1 read-write 0 The transition on TCapture pin is ignored #0 1 The transition on TCapture pin will result in the capture or reset of 24-bit timer counter #1 TCAP_MODE TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low. 17 1 read-write 0 Transition on TCapture pin is used as timer capture function #0 1 Transition on TCapture pin is used as timer counter reset function #1 TMR_ACT Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n 7 1 read-only 0 Timer is not active #0 1 Timer is in active #1 TMR_EN Timer Counter Enable Bit\n 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 WAKE_EN Wake-Up Enable When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up trigger event disable #0 1 Wake-up trigger event enable #1 DR TMR0_DR Timer 0 Data Register 0x14 read-write n 0x0 0x0 TDR Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value. 0 24 read-write GPA_SHADOW GPA_SHADOW GPIO Port A Pin Value Shadow Register 0x200 read-only n 0x0 0x0 PIN0 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 0 1 read-only PIN1 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 1 1 read-only PIN10 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 10 1 read-only PIN11 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 11 1 read-only PIN12 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 12 1 read-only PIN13 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 13 1 read-only PIN14 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 14 1 read-only PIN15 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 15 1 read-only PIN2 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 2 1 read-only PIN3 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 3 1 read-only PIN4 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 4 1 read-only PIN5 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 5 1 read-only PIN6 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 6 1 read-only PIN7 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 7 1 read-only PIN8 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 8 1 read-only PIN9 GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved. 9 1 read-only GPB_SHADOW GPB_SHADOW GPIO Port B Pin Value Shadow Register 0x204 read-write n 0x0 0x0 GPC_SHADOW GPC_SHADOW GPIO Port C Pin Value Shadow Register 0x208 read-write n 0x0 0x0 GPD_SHADOW GPD_SHADOW GPIO Port D Pin Value Shadow Register 0x20C read-write n 0x0 0x0 GPE_SHADOW GPE_SHADOW GPIO Port E Pin Value Shadow Register 0x210 read-write n 0x0 0x0 GPF_SHADOW GPF_SHADOW GPIO Port F Pin Value Shadow Register 0x214 read-write n 0x0 0x0 IER TMR0_IER Timer 0 Interrupt Enable Register 0xC read-write n 0x0 0x0 TCAP_IE Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18])setting. 1 1 read-write 0 Timer External Pin Function Interrupt Disabled #0 1 Timer External Pin Function Interrupt Enabled #1 TMR_IE Timer Interrupt Enable\nNOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 ISR TMR0_ISR Timer 0 Interrupt Status Register 0x10 read-write n 0x0 0x0 NCAP_DET_STS New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS (TMRx_ISR[1]) is cleared.\n 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status #0 1 New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status #1 TCAP_IS Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU. 1 1 read-write TMR_IS Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU. 0 1 read-write TMR_Wake_STS Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down mode by Timer timeout. 4 1 read-write PRECNT TMR0_PRECNT Timer 0 Pre-scale Counter Register 0x4 read-write n 0x0 0x0 PRESCALE_CNT Pre-Scale Counter\n 0 8 read-write TCAP TMR0_TCAP Timer 0 Capture Data Register 0x18 read-only n 0x0 0x0 CAP Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value. 0 24 read-only TMR1 TMR Register Map TMR 0x0 0x0 0x1C registers n CMPR TMR1_CMPR Timer 1 Compare Register 0x8 read-write n 0x0 0x0 TMR_CMP Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0 or 1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL[0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. 0 24 read-write CTL TMR1_CTL Timer 1 Control Register 0x0 read-write n 0x0 0x0 ADC_TEEN TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n 8 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled #1 CAP_CNT_MOD Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of Tcapture pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAP_TRG_EN TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN, or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]), or ADC_TEEN(TMRx_CTL[8])) is also set.\n 11 1 read-write 0 TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC #0 1 TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC #1 DBGACK_EN ICE Debug Mode Acknowledge Ineffective Enable\n 3 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged #0 1 ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not #1 EVENT_EDGE Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n 13 1 read-write 0 A falling edge of external event enabling the timer to increase 1 #0 1 A rising edge of external event enabling the timer to increase 1 #1 EVENT_EN Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n 12 1 read-write 0 Timer counting is not controlled by external event pin #0 1 Timer counting is controlled by external event pin #1 EVNT_DEB_EN External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption. 14 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx +1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0. 24 1 read-write 0 Inter-timer trigger mode is disabled #0 1 Inter-timer trigger mode is enabled #1 MODE_SEL Timer Operating Mode Select\n 4 2 read-write PDMA_TEEN TMR_IS Or TCAP_IS Trigger PDMA Enable This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller. 10 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])trigger PDMA Enabled #1 SW_RST Software Reset Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0. Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL[0]) bit #1 TCAP_DEB_EN TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption. 22 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 TCAP_EDGE TCapture Pin Edge Detect Selection\n 18 2 read-write TCAP_EN TCapture Pin Functional Enable This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function. Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high. 16 1 read-write 0 The transition on TCapture pin is ignored #0 1 The transition on TCapture pin will result in the capture or reset of 24-bit timer counter #1 TCAP_MODE TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low. 17 1 read-write 0 Transition on TCapture pin is used as timer capture function #0 1 Transition on TCapture pin is used as timer counter reset function #1 TMR_ACT Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n 7 1 read-only 0 Timer is not active #0 1 Timer is in active #1 TMR_EN Timer Counter Enable Bit\n 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 WAKE_EN Wake-Up Enable When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up trigger event disable #0 1 Wake-up trigger event enable #1 DR TMR1_DR Timer 1 Data Register 0x14 read-write n 0x0 0x0 TDR Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value. 0 24 read-write IER TMR1_IER Timer 1 Interrupt Enable Register 0xC read-write n 0x0 0x0 TCAP_IE Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18])setting. 1 1 read-write 0 Timer External Pin Function Interrupt Disabled #0 1 Timer External Pin Function Interrupt Enabled #1 TMR_IE Timer Interrupt Enable\nNOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 ISR TMR1_ISR Timer 1 Interrupt Status Register 0x10 read-write n 0x0 0x0 NCAP_DET_STS New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS (TMRx_ISR[1]) is cleared.\n 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status #0 1 New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status #1 TCAP_IS Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU. 1 1 read-write TMR_IS Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU. 0 1 read-write TMR_Wake_STS Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down mode by Timer timeout. 4 1 read-write PRECNT TMR1_PRECNT Timer 1 Pre-scale Counter Register 0x4 read-write n 0x0 0x0 PRESCALE_CNT Pre-Scale Counter\n 0 8 read-write TCAP TMR1_TCAP Timer 1 Capture Data Register 0x18 read-only n 0x0 0x0 CAP Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value. 0 24 read-only TMR2 TMR Register Map TMR 0x0 0x0 0x1C registers n CMPR TMR2_CMPR Timer 2 Compare Register 0x8 read-write n 0x0 0x0 TMR_CMP Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0 or 1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL[0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. 0 24 read-write CTL TMR2_CTL Timer 2 Control Register 0x0 read-write n 0x0 0x0 ADC_TEEN TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n 8 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled #1 CAP_CNT_MOD Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of Tcapture pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAP_TRG_EN TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN, or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]), or ADC_TEEN(TMRx_CTL[8])) is also set.\n 11 1 read-write 0 TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC #0 1 TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC #1 DBGACK_EN ICE Debug Mode Acknowledge Ineffective Enable\n 3 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged #0 1 ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not #1 EVENT_EDGE Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n 13 1 read-write 0 A falling edge of external event enabling the timer to increase 1 #0 1 A rising edge of external event enabling the timer to increase 1 #1 EVENT_EN Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n 12 1 read-write 0 Timer counting is not controlled by external event pin #0 1 Timer counting is controlled by external event pin #1 EVNT_DEB_EN External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption. 14 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx +1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0. 24 1 read-write 0 Inter-timer trigger mode is disabled #0 1 Inter-timer trigger mode is enabled #1 MODE_SEL Timer Operating Mode Select\n 4 2 read-write PDMA_TEEN TMR_IS Or TCAP_IS Trigger PDMA Enable This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller. 10 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])trigger PDMA Enabled #1 SW_RST Software Reset Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0. Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL[0]) bit #1 TCAP_DEB_EN TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption. 22 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 TCAP_EDGE TCapture Pin Edge Detect Selection\n 18 2 read-write TCAP_EN TCapture Pin Functional Enable This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function. Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high. 16 1 read-write 0 The transition on TCapture pin is ignored #0 1 The transition on TCapture pin will result in the capture or reset of 24-bit timer counter #1 TCAP_MODE TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low. 17 1 read-write 0 Transition on TCapture pin is used as timer capture function #0 1 Transition on TCapture pin is used as timer counter reset function #1 TMR_ACT Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n 7 1 read-only 0 Timer is not active #0 1 Timer is in active #1 TMR_EN Timer Counter Enable Bit\n 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 WAKE_EN Wake-Up Enable When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up trigger event disable #0 1 Wake-up trigger event enable #1 DR TMR2_DR Timer 2 Data Register 0x14 read-write n 0x0 0x0 TDR Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value. 0 24 read-write IER TMR2_IER Timer 2 Interrupt Enable Register 0xC read-write n 0x0 0x0 TCAP_IE Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18])setting. 1 1 read-write 0 Timer External Pin Function Interrupt Disabled #0 1 Timer External Pin Function Interrupt Enabled #1 TMR_IE Timer Interrupt Enable\nNOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 ISR TMR2_ISR Timer 2 Interrupt Status Register 0x10 read-write n 0x0 0x0 NCAP_DET_STS New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS (TMRx_ISR[1]) is cleared.\n 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status #0 1 New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status #1 TCAP_IS Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU. 1 1 read-write TMR_IS Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU. 0 1 read-write TMR_Wake_STS Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down mode by Timer timeout. 4 1 read-write PRECNT TMR2_PRECNT Timer 2 Pre-scale Counter Register 0x4 read-write n 0x0 0x0 PRESCALE_CNT Pre-Scale Counter\n 0 8 read-write TCAP TMR2_TCAP Timer 2 Capture Data Register 0x18 read-only n 0x0 0x0 CAP Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value. 0 24 read-only TMR3 TMR Register Map TMR 0x0 0x0 0x1C registers n CMPR TMR3_CMPR Timer 3 Compare Register 0x8 read-write n 0x0 0x0 TMR_CMP Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0 or 1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL[0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count. 0 24 read-write CTL TMR3_CTL Timer 3 Control Register 0x0 read-write n 0x0 0x0 ADC_TEEN TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n 8 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger ADC Enabled #1 CAP_CNT_MOD Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of Tcapture pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode. 20 1 read-write 0 Capture with free-counting timer mode #0 1 Capture with trigger-counting timer mode #1 CAP_TRG_EN TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN, or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]), or ADC_TEEN(TMRx_CTL[8])) is also set.\n 11 1 read-write 0 TMR_IS (TMRx_ISR[0]) is used to trigger PDMA and ADC #0 1 TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC #1 DBGACK_EN ICE Debug Mode Acknowledge Ineffective Enable\n 3 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting and TIMER counter will be held while ICE debug mode acknowledged #0 1 ICE debug mode acknowledgement is ineffective and TIMER counter will keep going no matter ICE debug mode acknowledged or not #1 EVENT_EDGE Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n 13 1 read-write 0 A falling edge of external event enabling the timer to increase 1 #0 1 A rising edge of external event enabling the timer to increase 1 #1 EVENT_EN Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n 12 1 read-write 0 Timer counting is not controlled by external event pin #0 1 Timer counting is controlled by external event pin #1 EVNT_DEB_EN External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption. 14 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx +1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0. 24 1 read-write 0 Inter-timer trigger mode is disabled #0 1 Inter-timer trigger mode is enabled #1 MODE_SEL Timer Operating Mode Select\n 4 2 read-write PDMA_TEEN TMR_IS Or TCAP_IS Trigger PDMA Enable This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller. 10 1 read-write 0 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) trigger PDMA Disabled #0 1 TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1])trigger PDMA Enabled #1 SW_RST Software Reset Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0. Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles. 1 1 read-write 0 No effect #0 1 Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_EN (TMRx_CTL[0]) bit #1 TCAP_DEB_EN TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption. 22 1 read-write 0 De-bounce circuit Disabled #0 1 De-bounce circuit Enabled #1 TCAP_EDGE TCapture Pin Edge Detect Selection\n 18 2 read-write TCAP_EN TCapture Pin Functional Enable This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function. Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high. 16 1 read-write 0 The transition on TCapture pin is ignored #0 1 The transition on TCapture pin will result in the capture or reset of 24-bit timer counter #1 TCAP_MODE TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low. 17 1 read-write 0 Transition on TCapture pin is used as timer capture function #0 1 Transition on TCapture pin is used as timer counter reset function #1 TMR_ACT Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n 7 1 read-only 0 Timer is not active #0 1 Timer is in active #1 TMR_EN Timer Counter Enable Bit\n 0 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 WAKE_EN Wake-Up Enable When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU. 2 1 read-write 0 Wake-up trigger event disable #0 1 Wake-up trigger event enable #1 DR TMR3_DR Timer 3 Data Register 0x14 read-write n 0x0 0x0 TDR Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value. 0 24 read-write IER TMR3_IER Timer 3 Interrupt Enable Register 0xC read-write n 0x0 0x0 TCAP_IE Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18])setting. 1 1 read-write 0 Timer External Pin Function Interrupt Disabled #0 1 Timer External Pin Function Interrupt Enabled #1 TMR_IE Timer Interrupt Enable\nNOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR. 0 1 read-write 0 Timer Interrupt Disabled #0 1 Timer Interrupt Enabled #1 ISR TMR3_ISR Timer 3 Interrupt Status Register 0x10 read-write n 0x0 0x0 NCAP_DET_STS New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS (TMRx_ISR[1]) is cleared.\n 5 1 read-write 0 New incoming capture event didn't detect before CPU clearing TCAP_IS (TMRx_ISR[1]) status #0 1 New incoming capture event detected before CPU clearing TCAP_IS (TMRx_ISR[1]) status #1 TCAP_IS Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU. 1 1 read-write TMR_IS Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU. 0 1 read-write TMR_Wake_STS Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down mode by Timer timeout. 4 1 read-write PRECNT TMR3_PRECNT Timer 3 Pre-scale Counter Register 0x4 read-write n 0x0 0x0 PRESCALE_CNT Pre-Scale Counter\n 0 8 read-write TCAP TMR3_TCAP Timer 3 Capture Data Register 0x18 read-only n 0x0 0x0 CAP Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value. 0 24 read-only UART0 UART Register Map UART 0x0 0x0 0x28 registers n 0x30 0xC registers n UART_ALT_CTL UART_ALT_CTL UART Alternate Control State Register. 0x34 read-write n 0x0 0x0 ADDR_PID_MATCH Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). 24 8 read-write BIT_ERR_EN Bit Error Detect Enable\n 8 1 read-write 0 Bit error detection Disabled #0 1 Bit error detection Enabled.Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN) #1 LIN_HEAD_SEL LIN Header Selection\n 4 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field + sync field #01 2 The LIN header includes break field + sync field + PID field #10 3 Reserved #11 LIN_RX_EN LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_BCNT LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8. 0 3 read-write LIN_TX_EN LIN TX Header Trigger Enable\nNote2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit. 7 1 read-write 0 LIN TX Header Trigger Disabled #0 1 LIN TX Header Trigger Enabled.Note1: This bit will be cleared automatically and generate a interrupt to CPU (INT_LIN) #1 RS_485_AAD RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\n 17 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled.Note: It can't be active in RS-485_NMM Operation mode #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is used to enable RS-485 hardware address detection mode.\n 19 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled.Note: This field is used for RS-485 any operation mode #1 RS_485_AUD RS-485 Auto Direction Mode (RS-485 AUD Mode)\n 18 1 read-write 0 RS-485 Auto Direction mode (AUD) Disabled #0 1 RS-485 Auto Direction mode (AUD) Enabled.Note: It can be active in RS-485_AAD or RS-485_NMM operation mode #1 RS_485_NMM RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\n 16 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled.Note: It can't be active in RS-485_AAD Operation mode #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider \n 0 16 read-write DIV_16_EN Divider 16 Enable\nNote: In IrDA mode, this bit must disable. 31 1 read-write 0 The equation of baud rate is UART_CLK / [ (BRD+1)] #0 1 The equation of baud rate is UART_CLK / [16 * (BRD+1)] #1 UART_CTL UART_CTL UART Control Register. 0x4 read-write n 0x0 0x0 ABAUD_EN Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled). 12 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 AUTO_CTS_EN CTSn Auto-Flow Control Enable \n 5 1 read-write 1 CTSn auto-flow control Enabled #1 AUTO_RTS_EN RTSn Auto-Flow Control Enable \nWhen RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]), the UART will reassert RTSn signal.\n 4 1 read-write 0 RTSn auto-flow control. Disabled #0 1 RTSn auto-flow control Enabled #1 DMA_RX_EN RX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA receive request operation continue. 6 1 read-write 0 RX PDMA service function Enabled #0 1 RX PDMA service function Disabled #1 DMA_TX_EN TX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA transmit request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA transmit request operation continue. 7 1 read-write 0 TX PDMA service function Enabled #0 1 TX PDMA service function Disabled #1 RX_DIS Receiver Disable Register Note1: In RS-485 NMM mode, user can setting this bit to receive data or not that before detect address byte. Note2: In RS-485 NMM mode, this bit will be setting to 1 automatically. Note3: In RS-485 AAD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. 2 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RX_RST RX Software Reset\nWhen RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART peripheral clock cycles. 0 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TX_DIS Transfer Disable Register\n 3 1 read-write 0 Transfer Enabled #0 1 Transfer Disabled #1 TX_RST TX Software Reset\nWhen TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART engine clock cycles. 1 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WAKE_CTS_EN CTSn Wake-Up Function Enable \n 8 1 read-write 0 CTSn wake-up system function Disabled 1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode #0 WAKE_DATA_EN Incoming Data Wake-Up Function Enable Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable. 9 1 read-write 0 Incoming data wake-up system Disabled #0 1 Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode #1 UART_FSR UART_FSR UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BI_F Break Status Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0 ) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FE_F Framing Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0 ), and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PE_F Parity Error State Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RX_EMPTY_F Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.\n 1 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL_F Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.\n 2 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_F RX Overflow Error Status Flag This bit is set when RX-FIFO overflow. If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set. Note: This bit can be cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER_F RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one. 16 5 read-only TE_F Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\n 11 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_EMPTY_F Transmitter FIFO Empty (Read Only) This bit indicates TX-FIFO empty or not. When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX-FIFO not empty). 9 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL_F Transmitter FIFO Full (Read Only) This bit indicates TX-FIFO full or not. This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware. 10 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_F TX Overflow Error Interrupt Status Flag If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic 1 . Note: This bit can be cleared by writing 1 to it. 8 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER_F TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one. 24 5 read-only UART_FUN_SEL UART_FUN_SEL UART Function Select Register. 0x38 read-write n 0x0 0x0 FUN_SEL Function Select Enable\n 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_IER UART_IER UART Interrupt Enable Register. 0xC read-write n 0x0 0x0 ABAUD_IE Auto-Baud Rate Interrupt Enable\n 7 1 read-write 0 INT_ABAUD Disable #0 1 INT_ABAUD Enabled #1 BUF_ERR_IE Buffer Error Interrupt Enable\n 5 1 read-write 0 INT_BUT_ERR Disable #0 1 INT_BUF_ERR Enabled #1 LIN_IE LIN Interrupt Enable\n 8 1 read-write 0 INT_LIN Disable #0 1 INT_LIN Enabled #1 MODEM_IE Modem Status Interrupt Enable \n 3 1 read-write 0 INT_MOS Disable #0 1 INT_MOS Enabled #1 RDA_IE Receive Data Available Interrupt Enable\n 0 1 read-write 0 INT_RDA Disable #0 1 INT_RDA Enabled #1 RLS_IE Receive Line Status Interrupt Enable \n 2 1 read-write 0 INT_RLS Disable #0 1 INT_RLS Enabled #1 RTO_IE RX Time-Out Interrupt Enable\n 4 1 read-write 0 INT_TOUT Disable #0 1 INT_TOUT Enabled #1 THRE_IE Transmit Holding Register Empty Interrupt Enable\n 1 1 read-write 0 INT_THRE Disable #0 1 INT_THRE Enabled #1 WAKE_IE Wake-Up Interrupt Enable\n 6 1 read-write 0 INT_WAKE Disable #0 1 INT_WAKE Enabled #1 UART_IRCR UART_IRCR UART IrDA Control Register. 0x30 -1 read-write n 0x0 0x0 INV_RX INV_RX\n 6 1 read-write 0 RX input signal no inversion #0 1 RX input signal inversion #1 INV_TX INV_TX\n 5 1 read-write 0 TX output signal no inversion #0 1 TX output signal inversion #1 TX_SELECT TX_SELECT\n 1 1 read-write 0 Select IrDA receiver #0 1 Select IrDA transmitter #1 UART_ISR UART_ISR UART Interrupt Status Register. 0x10 -1 read-write n 0x0 0x0 ABAUD_IS Auto-Baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (IER [7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]). Note2: This bit is cleared when both that the ABAUD_TOUT_F and ABAUD_F are cleared. 7 1 read-only 0 No Auto-Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 BUF_ERR_IS Buffer Error Interrupt Status Flag (Read Only) This bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set, the transfer maybe not correct. If BUF_ER_IEN (IER [5]) is set then the buffer error interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]). Note2: This bit is cleared when both that the TX_OVER_F and RX_OVER_F are cleared. 5 1 read-only 0 No Buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 LIN_IS LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE (IER [8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]). Note2: This bit is cleared when both that the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared. 8 1 read-only 0 No LIN interrupt is generated #0 1 LIN interrupt is generated #1 MODEM_IS MODEM Interrupt Status Flag (Read Only) Note: This bit is read only, but can be cleared by it by writing 1 to DCT_F (UART_MCSR [18]). 3 1 read-only 0 No MODEM interrupt is generated #0 1 MODEM interrupt is generated #1 RDA_IS Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (IER [0]) is set then the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No Receive Data available interrupt is generated #0 1 Receive Data available interrupt is generated #1 RLS_IS Receive Line Interrupt Status Flag (Read Only) This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]). Note2: This bit is cleared when both that the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared. 2 1 read-only 0 No Receive Line interrupt is generated #0 1 Receive Line interrupt is generated #1 RTO_IS RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If Tout_IEN (IER [4]) is set then the tout interrupt will be generated. \nNote: This bit is read only and user can read UART_RBR (RX is in active) to clear it. 4 1 read-only 0 No RX Time-Out interrupt is generated #0 1 RX Time-Out interrupt is generated #1 THRE_IS Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (IER [1]) is set that the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty). 1 1 read-only 0 No Transmit Holding register empty interrupt is generated #0 1 Transmit Holding register empty interrupt generated #1 WAKE_IS Wake-Up Interrupt Status Flag This bit is set in Power-down mode, the receiver received data or CTSn signal. If WAKE_IE (IER [6]) is set then the wake-up interrupt will be generated. Note: This bit can be cleared by it by writing 1 to it. 6 1 read-write 0 No Wake-Up interrupt is generated #0 1 Wake-Up interrupt is generated #1 UART_MCSR UART_MCSR UART Modem Status Register. 0x1C -1 read-write n 0x0 0x0 CTS_ST CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.\n 17 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCT_F Detect CTSn State Change Status Flag (Read Only) This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when Modem_IEN (UART_IER [3]). Note: This bit is read only, but it can be cleared by writing 1 to it. 18 1 read-only 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTSn Trigger Level\n 16 1 read-write 0 Low level triggered #0 1 High level triggered #1 LEV_RTS RTSn Trigger Level \n 0 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS_ST RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n 1 1 read-only 0 RTS pin input is low level voltage logic state #0 1 RTS pin input is high level voltage logic state #1 UART_RBR UART_RBR UART Receive Buffer Register. 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UART_THR UART_THR UART Transmit Holding Register. UART_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UART_TLCTL UART_TLCTL UART Transfer Line Control Register. 0x8 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1 , the serial data output (TX) is forced to the Spacing State (logic 0 ). This bit acts only on TX pin and has no effect on the transmitter logic. 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 DATA_LEN Data Length\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 EPE Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 NSB Number Of STOP Bit Length\n 2 1 read-write 0 1 STOP bit is generated in the transmitted data #0 1 1.5 STOP bit is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit is generated when 6, 7 and 8 bit data length is selected #1 PBE Parity Bit Enable\n 3 1 read-write 0 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.1 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 RFITL RX-FIFO Interrupt (INT_RDA) Trigger Level When the number of bytes in the receiving FIFO equals to the RFITL then the RDA_IF will be set (if RDA_IEN (IER [0]) is enabled, an interrupt will be generated) Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 . 8 2 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #00 1 RX FIFO Interrupt Trigger Level is 4 bytes #01 2 RX FIFO Interrupt Trigger Level is 8 bytes #10 3 RX FIFO Interrupt Trigger Level is 14 bytes #11 RTS_TRI_LEV RTSn Trigger Level (For Auto-Flow Control Use)\nNote: This field is used for auto RTSn flow control. 12 2 read-write 0 RTS Trigger Level is 1 byte #00 1 RTS Trigger Level is 4 bytes #01 2 RTS Trigger Level is 8 bytes #10 3 RTS Trigger Level is 14 bytes #11 SPE Stick Parity Enable Stick Parity Enable Control Note1: When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as 0 . When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as 1 . Note2: In RS-485 mode, PBE, EPE and SPE can control bit 9, the bit 9 setting are shown as follows. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 UART_TMCTL UART_TMCTL UART Time-out Control Register. 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is use to programming the transfer delay time between the last stop bit and next start bit. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3: The counting clock is baud rate clock. 16 8 read-write TOIC Time-Out Comparator The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 bit data + parity bit + stop bit, so although software can configure this field by any value but it is recommend to filled this field great than 0xA. 0 9 read-write UART_TRSR UART_TRSR UART Transfer Status Register. 0x14 read-write n 0x0 0x0 ABAUD_F Auto-Baud Rate Interrupt This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit can be cleared by writing 1 to it. 1 1 read-write 0 No Auto- Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 ABAUD_TOUT_F Auto-Baud Rate Time-Out Interrupt This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note: This bit can be cleared by writing 1 to it. 2 1 read-write 0 No Auto-Baud Rate Time-Out interrupt is generated #0 1 Auto-Baud Rate Time-Out interrupt is generated #1 BIT_ERR_F Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\n 5 1 read-write 0 No Bit error interrupt is generated #0 1 Bit error interrupt is generated #1 LIN_RX_F LIN RX Interrupt Flag This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL [5:4]) register. Note: This bit can be cleared by writing 1 to it. 4 1 read-write 0 No LIN Rx interrupt is generated #0 1 LIN Rx interrupt is generated #1 LIN_RX_SYNC_ERR_F LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register. Note: This bit is read only, but can be cleared by writing 1 to LIN_RX_F. 8 1 read-only 0 No LIN Rx sync error is generated #0 1 LIN Rx sync error is generated #1 LIN_TX_F LIN TX Interrupt Flag This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. Note: This bit can be cleared by writing 1 to it. 3 1 read-write 0 No LIN Tx interrupt is generated #0 1 LIN Tx interrupt is generated #1 RS_485_ADDET_F RS-485 Address Byte Detection Status Flag Note1: This field is used for RS-485 mode. Note2: This bit can be cleared by writing 1 to it. 0 1 read-write 0 No RS-485 address detection interrupt is generated #0 1 RS-485 address detection interrupt is generated #1 UART1 UART Register Map UART 0x0 0x0 0x28 registers n 0x30 0xC registers n UART_ALT_CTL UART_ALT_CTL UART Alternate Control State Register. 0x34 read-write n 0x0 0x0 ADDR_PID_MATCH Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID). 24 8 read-write BIT_ERR_EN Bit Error Detect Enable\n 8 1 read-write 0 Bit error detection Disabled #0 1 Bit error detection Enabled.Note: In LIN function mode, when bit error occurs, hardware will generate an interrupt to CPU (INT_LIN) #1 LIN_HEAD_SEL LIN Header Selection\n 4 2 read-write 0 The LIN header includes break field #00 1 The LIN header includes break field + sync field #01 2 The LIN header includes break field + sync field + PID field #10 3 Reserved #11 LIN_RX_EN LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)\n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_BCNT LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8. 0 3 read-write LIN_TX_EN LIN TX Header Trigger Enable\nNote2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit. 7 1 read-write 0 LIN TX Header Trigger Disabled #0 1 LIN TX Header Trigger Enabled.Note1: This bit will be cleared automatically and generate a interrupt to CPU (INT_LIN) #1 RS_485_AAD RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\n 17 1 read-write 0 RS-485 Auto Address Detection Operation mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation mode (AAD) Enabled.Note: It can't be active in RS-485_NMM Operation mode #1 RS_485_ADD_EN RS-485 Address Detection Enable\nThis bit is used to enable RS-485 hardware address detection mode.\n 19 1 read-write 0 Address detection mode Disabled #0 1 Address detection mode Enabled.Note: This field is used for RS-485 any operation mode #1 RS_485_AUD RS-485 Auto Direction Mode (RS-485 AUD Mode)\n 18 1 read-write 0 RS-485 Auto Direction mode (AUD) Disabled #0 1 RS-485 Auto Direction mode (AUD) Enabled.Note: It can be active in RS-485_AAD or RS-485_NMM operation mode #1 RS_485_NMM RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\n 16 1 read-write 0 RS-485 Normal Multi-drop Operation mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation mode (NMM) Enabled.Note: It can't be active in RS-485_AAD Operation mode #1 UART_BAUD UART_BAUD UART Baud Rate Divisor Register 0x24 read-write n 0x0 0x0 BRD Baud Rate Divider \n 0 16 read-write DIV_16_EN Divider 16 Enable\nNote: In IrDA mode, this bit must disable. 31 1 read-write 0 The equation of baud rate is UART_CLK / [ (BRD+1)] #0 1 The equation of baud rate is UART_CLK / [16 * (BRD+1)] #1 UART_CTL UART_CTL UART Control Register. 0x4 read-write n 0x0 0x0 ABAUD_EN Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled). 12 1 read-write 0 Auto-baud rate detect function Disabled #0 1 Auto-baud rate detect function Enabled #1 AUTO_CTS_EN CTSn Auto-Flow Control Enable \n 5 1 read-write 1 CTSn auto-flow control Enabled #1 AUTO_RTS_EN RTSn Auto-Flow Control Enable \nWhen RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]), the UART will reassert RTSn signal.\n 4 1 read-write 0 RTSn auto-flow control. Disabled #0 1 RTSn auto-flow control Enabled #1 DMA_RX_EN RX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA receive request operation continue. 6 1 read-write 0 RX PDMA service function Enabled #0 1 RX PDMA service function Disabled #1 DMA_TX_EN TX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA transmit request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA transmit request operation continue. 7 1 read-write 0 TX PDMA service function Enabled #0 1 TX PDMA service function Disabled #1 RX_DIS Receiver Disable Register Note1: In RS-485 NMM mode, user can setting this bit to receive data or not that before detect address byte. Note2: In RS-485 NMM mode, this bit will be setting to 1 automatically. Note3: In RS-485 AAD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit. 2 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 RX_RST RX Software Reset\nWhen RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART peripheral clock cycles. 0 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 TX_DIS Transfer Disable Register\n 3 1 read-write 0 Transfer Enabled #0 1 Transfer Disabled #1 TX_RST TX Software Reset\nWhen TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART engine clock cycles. 1 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 WAKE_CTS_EN CTSn Wake-Up Function Enable \n 8 1 read-write 0 CTSn wake-up system function Disabled 1 = Wake-up function Enabled when the system is in power-down mode, an external CTSn change will wake-up system from power-down mode #0 WAKE_DATA_EN Incoming Data Wake-Up Function Enable Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable. 9 1 read-write 0 Incoming data wake-up system Disabled #0 1 Incoming data wake-up function Enabled when the system is in power-down mode, incoming data will wake-up system from power-down mode #1 UART_FSR UART_FSR UART FIFO Status Register. 0x18 -1 read-write n 0x0 0x0 BI_F Break Status Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0 ) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 6 1 read-write 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FE_F Framing Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0 ), and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 5 1 read-write 0 No framing error is generated #0 1 Framing error is generated #1 PE_F Parity Error State Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it. 4 1 read-write 0 No parity error is generated #0 1 Parity error is generated #1 RX_EMPTY_F Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.\n 1 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL_F Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.\n 2 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_F RX Overflow Error Status Flag This bit is set when RX-FIFO overflow. If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set. Note: This bit can be cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER_F RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one. 16 5 read-only TE_F Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\n 11 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_EMPTY_F Transmitter FIFO Empty (Read Only) This bit indicates TX-FIFO empty or not. When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX-FIFO not empty). 9 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL_F Transmitter FIFO Full (Read Only) This bit indicates TX-FIFO full or not. This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware. 10 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_F TX Overflow Error Interrupt Status Flag If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic 1 . Note: This bit can be cleared by writing 1 to it. 8 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER_F TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one. 24 5 read-only UART_FUN_SEL UART_FUN_SEL UART Function Select Register. 0x38 read-write n 0x0 0x0 FUN_SEL Function Select Enable\n 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UART_IER UART_IER UART Interrupt Enable Register. 0xC read-write n 0x0 0x0 ABAUD_IE Auto-Baud Rate Interrupt Enable\n 7 1 read-write 0 INT_ABAUD Disable #0 1 INT_ABAUD Enabled #1 BUF_ERR_IE Buffer Error Interrupt Enable\n 5 1 read-write 0 INT_BUT_ERR Disable #0 1 INT_BUF_ERR Enabled #1 LIN_IE LIN Interrupt Enable\n 8 1 read-write 0 INT_LIN Disable #0 1 INT_LIN Enabled #1 MODEM_IE Modem Status Interrupt Enable \n 3 1 read-write 0 INT_MOS Disable #0 1 INT_MOS Enabled #1 RDA_IE Receive Data Available Interrupt Enable\n 0 1 read-write 0 INT_RDA Disable #0 1 INT_RDA Enabled #1 RLS_IE Receive Line Status Interrupt Enable \n 2 1 read-write 0 INT_RLS Disable #0 1 INT_RLS Enabled #1 RTO_IE RX Time-Out Interrupt Enable\n 4 1 read-write 0 INT_TOUT Disable #0 1 INT_TOUT Enabled #1 THRE_IE Transmit Holding Register Empty Interrupt Enable\n 1 1 read-write 0 INT_THRE Disable #0 1 INT_THRE Enabled #1 WAKE_IE Wake-Up Interrupt Enable\n 6 1 read-write 0 INT_WAKE Disable #0 1 INT_WAKE Enabled #1 UART_IRCR UART_IRCR UART IrDA Control Register. 0x30 -1 read-write n 0x0 0x0 INV_RX INV_RX\n 6 1 read-write 0 RX input signal no inversion #0 1 RX input signal inversion #1 INV_TX INV_TX\n 5 1 read-write 0 TX output signal no inversion #0 1 TX output signal inversion #1 TX_SELECT TX_SELECT\n 1 1 read-write 0 Select IrDA receiver #0 1 Select IrDA transmitter #1 UART_ISR UART_ISR UART Interrupt Status Register. 0x10 -1 read-write n 0x0 0x0 ABAUD_IS Auto-Baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (IER [7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]). Note2: This bit is cleared when both that the ABAUD_TOUT_F and ABAUD_F are cleared. 7 1 read-only 0 No Auto-Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 BUF_ERR_IS Buffer Error Interrupt Status Flag (Read Only) This bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set, the transfer maybe not correct. If BUF_ER_IEN (IER [5]) is set then the buffer error interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]). Note2: This bit is cleared when both that the TX_OVER_F and RX_OVER_F are cleared. 5 1 read-only 0 No Buffer error interrupt is generated #0 1 Buffer error interrupt is generated #1 LIN_IS LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE (IER [8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]). Note2: This bit is cleared when both that the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared. 8 1 read-only 0 No LIN interrupt is generated #0 1 LIN interrupt is generated #1 MODEM_IS MODEM Interrupt Status Flag (Read Only) Note: This bit is read only, but can be cleared by it by writing 1 to DCT_F (UART_MCSR [18]). 3 1 read-only 0 No MODEM interrupt is generated #0 1 MODEM interrupt is generated #1 RDA_IS Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (IER [0]) is set then the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No Receive Data available interrupt is generated #0 1 Receive Data available interrupt is generated #1 RLS_IS Receive Line Interrupt Status Flag (Read Only) This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]). Note2: This bit is cleared when both that the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared. 2 1 read-only 0 No Receive Line interrupt is generated #0 1 Receive Line interrupt is generated #1 RTO_IS RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If Tout_IEN (IER [4]) is set then the tout interrupt will be generated. \nNote: This bit is read only and user can read UART_RBR (RX is in active) to clear it. 4 1 read-only 0 No RX Time-Out interrupt is generated #0 1 RX Time-Out interrupt is generated #1 THRE_IS Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (IER [1]) is set that the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty). 1 1 read-only 0 No Transmit Holding register empty interrupt is generated #0 1 Transmit Holding register empty interrupt generated #1 WAKE_IS Wake-Up Interrupt Status Flag This bit is set in Power-down mode, the receiver received data or CTSn signal. If WAKE_IE (IER [6]) is set then the wake-up interrupt will be generated. Note: This bit can be cleared by it by writing 1 to it. 6 1 read-write 0 No Wake-Up interrupt is generated #0 1 Wake-Up interrupt is generated #1 UART_MCSR UART_MCSR UART Modem Status Register. 0x1C -1 read-write n 0x0 0x0 CTS_ST CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.\n 17 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCT_F Detect CTSn State Change Status Flag (Read Only) This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when Modem_IEN (UART_IER [3]). Note: This bit is read only, but it can be cleared by writing 1 to it. 18 1 read-only 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTSn Trigger Level\n 16 1 read-write 0 Low level triggered #0 1 High level triggered #1 LEV_RTS RTSn Trigger Level \n 0 1 read-write 0 low level triggered #0 1 high level triggered #1 RTS_ST RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n 1 1 read-only 0 RTS pin input is low level voltage logic state #0 1 RTS pin input is high level voltage logic state #1 UART_RBR UART_RBR UART Receive Buffer Register. 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first). 0 8 read-only UART_THR UART_THR UART Transmit Holding Register. UART_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first). 0 8 write-only UART_TLCTL UART_TLCTL UART Transfer Line Control Register. 0x8 read-write n 0x0 0x0 BCB Break Control Bit When this bit is set to logic 1 , the serial data output (TX) is forced to the Spacing State (logic 0 ). This bit acts only on TX pin and has no effect on the transmitter logic. 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 DATA_LEN Data Length\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 EPE Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set. 4 1 read-write 0 Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode #0 1 Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode #1 NSB Number Of STOP Bit Length\n 2 1 read-write 0 1 STOP bit is generated in the transmitted data #0 1 1.5 STOP bit is generated in the transmitted data when 5-bit word length is selected, and 2 STOP bit is generated when 6, 7 and 8 bit data length is selected #1 PBE Parity Bit Enable\n 3 1 read-write 0 Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.1 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data #0 RFITL RX-FIFO Interrupt (INT_RDA) Trigger Level When the number of bytes in the receiving FIFO equals to the RFITL then the RDA_IF will be set (if RDA_IEN (IER [0]) is enabled, an interrupt will be generated) Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 . 8 2 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #00 1 RX FIFO Interrupt Trigger Level is 4 bytes #01 2 RX FIFO Interrupt Trigger Level is 8 bytes #10 3 RX FIFO Interrupt Trigger Level is 14 bytes #11 RTS_TRI_LEV RTSn Trigger Level (For Auto-Flow Control Use)\nNote: This field is used for auto RTSn flow control. 12 2 read-write 0 RTS Trigger Level is 1 byte #00 1 RTS Trigger Level is 4 bytes #01 2 RTS Trigger Level is 8 bytes #10 3 RTS Trigger Level is 14 bytes #11 SPE Stick Parity Enable Stick Parity Enable Control Note1: When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as 0 . When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as 1 . Note2: In RS-485 mode, PBE, EPE and SPE can control bit 9, the bit 9 setting are shown as follows. 5 1 read-write 0 Stick parity Disabled #0 1 Stick parity Enabled #1 UART_TMCTL UART_TMCTL UART Time-out Control Register. 0x20 -1 read-write n 0x0 0x0 DLY TX Delay Time Value This field is use to programming the transfer delay time between the last stop bit and next start bit. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3: The counting clock is baud rate clock. 16 8 read-write TOIC Time-Out Comparator The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 bit data + parity bit + stop bit, so although software can configure this field by any value but it is recommend to filled this field great than 0xA. 0 9 read-write UART_TRSR UART_TRSR UART Transfer Status Register. 0x14 read-write n 0x0 0x0 ABAUD_F Auto-Baud Rate Interrupt This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit can be cleared by writing 1 to it. 1 1 read-write 0 No Auto- Baud Rate interrupt is generated #0 1 Auto-Baud Rate interrupt is generated #1 ABAUD_TOUT_F Auto-Baud Rate Time-Out Interrupt This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note: This bit can be cleared by writing 1 to it. 2 1 read-write 0 No Auto-Baud Rate Time-Out interrupt is generated #0 1 Auto-Baud Rate Time-Out interrupt is generated #1 BIT_ERR_F Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\n 5 1 read-write 0 No Bit error interrupt is generated #0 1 Bit error interrupt is generated #1 LIN_RX_F LIN RX Interrupt Flag This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL [5:4]) register. Note: This bit can be cleared by writing 1 to it. 4 1 read-write 0 No LIN Rx interrupt is generated #0 1 LIN Rx interrupt is generated #1 LIN_RX_SYNC_ERR_F LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register. Note: This bit is read only, but can be cleared by writing 1 to LIN_RX_F. 8 1 read-only 0 No LIN Rx sync error is generated #0 1 LIN Rx sync error is generated #1 LIN_TX_F LIN TX Interrupt Flag This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. Note: This bit can be cleared by writing 1 to it. 3 1 read-write 0 No LIN Tx interrupt is generated #0 1 LIN Tx interrupt is generated #1 RS_485_ADDET_F RS-485 Address Byte Detection Status Flag Note1: This field is used for RS-485 mode. Note2: This bit can be cleared by writing 1 to it. 0 1 read-write 0 No RS-485 address detection interrupt is generated #0 1 RS-485 address detection interrupt is generated #1 USB USB Register Map USB 0x0 0x0 0x1C registers n 0x20 0xC registers n 0x30 0xC registers n 0x40 0xC registers n 0x50 0xC registers n 0x60 0xC registers n 0x70 0xC registers n 0xA4 0x4 registers n BUFSEG USB_BUFSEG Setup Token Buffer Segmentation Register 0x18 read-write n 0x0 0x0 BUFSEG None 3 6 read-write BUFSEG0 USB_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x20 read-write n 0x0 0x0 BUFSEG Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description. 3 6 read-write BUFSEG1 USB_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x30 read-write n 0x0 0x0 BUFSEG2 USB_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x40 read-write n 0x0 0x0 BUFSEG3 USB_BUFSEG3 Endpoint 3 Buffer Segmentation Register 0x50 read-write n 0x0 0x0 BUFSEG4 USB_BUFSEG4 Endpoint 4 Buffer Segmentation Register 0x60 read-write n 0x0 0x0 BUFSEG5 USB_BUFSEG5 Endpoint 5 Buffer Segmentation Register 0x70 read-write n 0x0 0x0 BUSSTS USB_BUSSTS USB Bus Status Register 0x4 read-only n 0x0 0x0 FLDET Device Floating Detection\n 4 1 read-only 0 The controller didn't attach into the USB #0 1 When the controller is attached into the USB, this bit will be set as 1 #1 RESUME Resume Status\n 2 1 read-only 1 Resume from suspend. It is read only #1 SUSPEND Suspend Status \n 1 1 read-only 1 Bus idle more than 3mS, either cable is plugged off or host is sleeping. It is read only #1 TIMEOUT Time Out Flag\n 3 1 read-only 1 Bus no any response more than 18 bits time. It is read only #1 USBRST USB Reset Status \n 0 1 read-only 1 Bus reset when SE0 (single-ended 0) more than 2.5uS. It is read only #1 CFG0 USB_CFG0 Endpoint 0 Configuration Register 0x28 read-write n 0x0 0x0 CSTALL Clear STALL Response\n 8 1 read-write 0 Disabled to the device to clear the STALL handshake in setup stage #0 1 Clear the device to response STALL handshake in setup stage #1 DSQ_SYNC Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens, the user shall take care of it to confirm the right PID in its transaction. 7 1 read-write 0 DATA0 PID #0 1 DATA1 PID #1 EPMODE Endpoint Mode\n 5 2 read-write EP_NUM Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint 0 4 read-write ISOCH Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake. 4 1 read-write SSTALL Set STALL Response\n 9 1 read-write 0 Disabled the device to response STALL #0 1 Set the device to respond STALL automatically #1 CFG1 USB_CFG1 Endpoint 1 Configuration Register 0x38 read-write n 0x0 0x0 CFG2 USB_CFG2 Endpoint 2 Configuration Register 0x48 read-write n 0x0 0x0 CFG3 USB_CFG3 Endpoint 3 Configuration Register 0x58 read-write n 0x0 0x0 CFG4 USB_CFG4 Endpoint 4 Configuration Register 0x68 read-write n 0x0 0x0 CFG5 USB_CFG5 Endpoint 5 Configuration Register 0x78 read-write n 0x0 0x0 CTL USB_CTL USB Control Register 0x0 -1 read-write n 0x0 0x0 DPPU_EN Pull-Up Resistor On USB_DP Enable\n 3 1 read-write 0 Disabled the pull-up resistor in USB_DP bus #0 1 Pull-up resistor in USB_DP bus will be active #1 DRVSE0 Force USB PHY Transceiver To Drive SE0 (Single Ended Zero) The Single Ended Zero is present when both lines (USB_DP, USB_DM) are being pulled low. The default value is 1 . 4 1 read-write 0 None #0 1 Force USB PHY transceiver to drive SE0 #1 PHY_EN PHY Transceiver Enable\n 1 1 read-write 0 PHY transceiver Disabled #0 1 PHY transceiver Enabled #1 PWRDB Power Down PHY Transceiver, Low Active\n 2 1 read-write 0 Power-down related circuit of PHY transceiver #0 1 Turn-on related circuit of PHY transceiver #1 RWAKEUP Remote Wake-Up\n 8 1 read-write 0 Don't force USB bus to K state #0 1 Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up #1 USB_EN USB Function Enable\n 0 1 read-write 0 USB Disabled #0 1 USB Enabled #1 WAKEUP_EN Wake-Up Function Enable\n 9 1 read-write 0 USB wake-up function Disabled #0 1 USB wake-up function Enabled #1 EPSTS USB_EPSTS Endpoint Status Register 0x14 read-only n 0x0 0x0 EPSTS0 Endpoint 0 Bus Status\n 8 4 read-only EPSTS1 Endpoint 1 Bus Status\n 12 4 read-only EPSTS2 Endpoint 2 Bus Status\n 16 4 read-only EPSTS3 Endpoint 3 Bus Status\n 20 4 read-only EPSTS4 Endpoint 4 Bus Status\n 24 4 read-only EPSTS5 Endpoint 5 Bus Status\n 28 4 read-only OVERRUN Overrun\nIt means the received data is over the maximum payload number or not.\n 7 1 read-only 0 No overrun #0 1 Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes #1 FADDR USB_FADDR Device Function Address Register 0x10 read-write n 0x0 0x0 FADDR USB device's function address 0 7 read-write INTEN USB_INTEN Interrupt Enable Register 0x8 read-write n 0x0 0x0 BUSEVT_IE Bus Event Interrupt Enable\n 0 1 read-write 0 BUS event interrupt Disabled #0 1 BUS event interrupt Enabled #1 FLDET_IE Floating Detect Interrupt Enable\n 2 1 read-write 0 Floating detect Interrupt Disabled #0 1 Floating detect Interrupt Enabled #1 USBEVT_IE USB Event Interrupt Enable\n 1 1 read-write 0 USB event interrupt Disabled #0 1 USB event interrupt Enabled #1 WAKEUP_IE USB Wake-Up Interrupt Enable\n 3 1 read-write 0 Wake-up Interrupt Disabled #0 1 Wake-up Interrupt Enabled #1 INTSTS USB_INTSTS Interrupt Event Status Register 0xC read-write n 0x0 0x0 BUS_STS BUS Interrupt Status\nThe BUS event means there is bus suspense or bus resume in the bus. This bit is used to indicate that there is one of events in the bus.\n 0 1 read-write 0 No BUS event is occurred #0 1 BUS event occurred check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS [0] #1 EPEVT0 USB Event Status On EP0\n 16 1 read-write 0 No event occurred in Endpoint 0 #0 1 USB event occurred on Endpoint 0, check USB_EPSTS[11:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [16] or USB_INTSTS [1] #1 EPEVT1 USB Event Status On EP1\n 17 1 read-write 0 No event occurred in Endpoint 1 #0 1 USB event occurred on Endpoint 1, check USB_EPSTS[15:12] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [17] or USB_INTSTS [1] #1 EPEVT2 USB Event Status On EP2\n 18 1 read-write 0 No event occurred in Endpoint 2 #0 1 USB event occurred on Endpoint 2, check USB_EPSTS[19:16] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [18] or USB_INTSTS [1] #1 EPEVT3 USB Event Status On EP3\n 19 1 read-write 0 No event occurred in Endpoint 3 #0 1 USB event occurred on Endpoint 3, check USB_EPSTS[23:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [19] or USB_INTSTS [1] #1 EPEVT4 USB Event Status On EP4\n 20 1 read-write 0 No event occurred in Endpoint 4 #0 1 USB event occurred on Endpoint 4, check USB_EPSTS[27:24] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [20] or USB_INTSTS [1] #1 EPEVT5 USB Event Status On EP5\n 21 1 read-write 0 No event occurred in Endpoint 5 #0 1 USB event occurred on Endpoint 5, check USB_EPSTS[31:28] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [21] or USB_INTSTS [1] #1 FLD_STS Floating Interrupt Status\n 2 1 read-write 0 There is not attached event in the USB #0 1 There is attached event in the USB and it is cleared by write 1 to USB_INTSTS [2] #1 SETUP Setup Event Status \n 31 1 read-write 0 No Setup event #0 1 Setup event occurred, cleared by write 1 to USB_INTSTS[31] #1 USB_STS USB Interrupt Status\nThe USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. This bit is used to indicate that there is one of events in the bus.\n 1 1 read-write 0 No USB event is occurred #0 1 USB event occurred, check EPSTS0~5[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~5 #1 WKEUP_STS Wake-Up Interrupt Status\n 3 1 read-write 0 No wake-up event is occurred #0 1 Wake-up event occurred, cleared by write 1 to USB_INTSTS [3] #1 MXPLD0 USB_MXPLD0 Endpoint 0 Maximal Payload Register 0x24 read-write n 0x0 0x0 MXPLD Maximal Payload It is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. (1). When the register is written by CPU, For IN token, the value of MXPLD is used to define the length of data to be transmitted and indicate the data buffer is ready. For OUT token, it means that the controller is ready to receive data from host and the value of MXPLD is the maximal data length comes from host. (2). When the register is read by CPU, For IN token, the value of MXPLD is indicated the length of data be transmitted to host For OUT token, the value of MXPLD is indicated the actual length of data receiving from host. Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. 0 9 read-write MXPLD1 USB_MXPLD1 Endpoint 1 Maximal Payload Register 0x34 read-write n 0x0 0x0 MXPLD2 USB_MXPLD2 Endpoint 2 Maximal Payload Register 0x44 read-write n 0x0 0x0 MXPLD3 USB_MXPLD3 Endpoint 3 Maximal Payload Register 0x54 read-write n 0x0 0x0 MXPLD4 USB_MXPLD4 Endpoint 4 Maximal Payload Register 0x64 read-write n 0x0 0x0 MXPLD5 USB_MXPLD5 Endpoint 5 Maximal Payload Register 0x74 read-write n 0x0 0x0 PDMA USB_PDMA USB PDMA Control Register 0xA4 read-write n 0x0 0x0 BYTEM CPU Access USB SRAM Size Mode Select\n 2 1 read-write 0 Word Mode: The size of the transfer from CPU to USB SRAM is Word order #0 1 Byte Mode: The size of the transfer from CPU to USB SRAM is Byte order #1 PDMA_RST PDMA Reset\nIt is used to reset the USB PDMA function into default state. \nNote: it is auto clear to 0 after the reset function done. 3 1 read-write 0 No Reset PDMA Reset Disable #0 1 Reset the PDMA function in this controller #1 PDMA_RW PDMA_RW\n 0 1 read-write 0 The PDMA will read data from memory to USB buffer #0 1 The PDMA will read data from USB buffer to memory #1 PDMA_TRG Active PDMA Function\nThis bit will be automatically cleared after PDMA transfer done. 1 1 read-write 0 The PDMA function is not active #0 1 The PDMA function in USB is active #1 VDMA VDMA Register Map VDMA 0x0 0x0 0x10 registers n 0x14 0x14 registers n 0x2C 0x8 registers n 0x80 0x8 registers n BCR VDMA_BCR VDMA Transfer Byte Count Register 0xC read-write n 0x0 0x0 VDMA_BCR VDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count number of VDMA.\n 0 16 read-write BUF0 VDMA_BUF0 VDMA Internal Buffer FIFO 0 0x80 read-only n 0x0 0x0 VDMA_BUF0 VDMA Internal Buffer FIFO 0 (Read Only)\nVDMA channel has its own 2 words internal buffer. 0 32 read-only BUF1 VDMA_BUF1 VDMA Internal Buffer FIFO 1 0x84 read-only n 0x0 0x0 VDMA_BUF1 VDMA Internal Buffer FIFO 1 (Read Only)\nVDMA channel has its own 2 words internal buffer. 0 32 read-only CBCR VDMA_CBCR VDMA Current Transfer Byte Count Register 0x1C read-only n 0x0 0x0 VDMA_CBCR VDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of VDMA. 0 16 read-only CDAR VDMA_CDAR VDMA Current Destination Address Register 0x18 read-only n 0x0 0x0 VDMA_CDAR VDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the VDMA transfer just occurred. 0 32 read-only CSAR VDMA_CSAR VDMA Current Source Address Register 0x14 read-only n 0x0 0x0 VDMA_CSAR VDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the VDMA transfer just occurred. 0 32 read-only CSR VDMA_CSR VDMA Control Register 0x0 read-write n 0x0 0x0 DIR_SEL Transfer Source/Destination Address Direction Selection\n 11 1 read-write 0 Transfer address is incremented successively #0 1 Transfer address is decremented successively #1 STRIDE_EN Stride Mode Enable Control\n 10 1 read-write 0 Stride transfer mode Disabled #0 1 Stride transfer mode Enabled #1 SW_RST Software Engine Reset\n 1 1 read-write 0 No effect #0 1 Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles #1 TRIG_EN Trigger Enable Control\nNote: When VDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all VDMA transfer will be stopped. User must reset all VDMA channel, and then trigger again. 23 1 read-write 0 No effect #0 1 VDMA data read or write transfer Enabled #1 VDMACEN VDMA Channel Enable Control Setting this bit to 1 enables VDMA's operation. If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit. 0 1 read-write DAR VDMA_DAR VDMA Destination Address Register 0x8 read-write n 0x0 0x0 VDMA_DAR VDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of VDMA. 0 32 read-write DASOCR VDMA_DASOCR VDMA Destination Address Stride Offset Register 0x30 read-write n 0x0 0x0 DASTOBL VDMA Destination Address Stride Offset Byte Length\nThe 16-bit register defines the destination address stride transfer offset count of each row. 0 16 read-write IER VDMA_IER VDMA Interrupt Enable Register 0x20 -1 read-write n 0x0 0x0 TABORT_IE VDMA Read/Write Target Abort Interrupt Enable Control\n 0 1 read-write 0 Target abort interrupt generation Disabled during VDMA transfer #0 1 Target abort interrupt generation Enabled during VDMA transfer #1 TD_IE VDMA Transfer Done Interrupt Enable Control\n 1 1 read-write 0 Iinterrupt generator Disabled during VDMA transfer done #0 1 Interrupt generator Enabled during VDMA transfer done #1 ISR VDMA_ISR VDMA Interrupt Status Register 0x24 read-write n 0x0 0x0 TABORT_IS VDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. VDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset VDMA controller, and then transfer those data again. 0 1 read-write 0 No bus ERROR response received #0 1 Bus ERROR response received #1 TD_IS Transfer Done Interrupt Status Flag\nThis bit indicates that VDMA has finished all transfer. \n 1 1 read-write 0 Not finished yet #0 1 Done. Note: This bit is cleared by writing 1 to it #1 SAR VDMA_SAR VDMA Source Address Register 0x4 read-write n 0x0 0x0 VDMA_SAR VDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of VDMA. 0 32 read-write SASOCR VDMA_SASOCR VDMA Source Address Stride Offset Register 0x2C read-write n 0x0 0x0 SASTOBL VDMA Source Address Stride Offset Byte Length\nThe 16-bit register defines the source address stride transfer offset count of each row. 0 16 read-write STBC VDMA Stride Transfer Byte Count\nThe 16-bit register defines the stride transfer byte count of each row. 16 16 read-write WDT WDT Register Map WDT 0x0 0x0 0xC registers n CTL WDT_CTL Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 WTE Watchdog Timer Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n 3 1 read-write 0 Watchdog timer Disabled (this action will reset the internal counter) #0 1 Watchdog timer Enabled #1 WTIS Watchdog Timer Interval Selection (Write Protect)\nPlease refer to open lock sequence to program it.\nThe three bits select the time-out interval for the Watchdog timer. This count is free running counter.\nPlease refer to Table 5.191 Watchdog Time-out Interval Selection 4 3 read-write WTR Clear Watchdog Timer (Write Protect)\nPlease refer to open lock sequence to program it.\nSet this bit will clear the Watchdog timer. \nNote: This bit will auto clear after few clock cycle 0 1 read-write 0 No effect #0 1 Reset the contents of the Watchdog timer #1 WTRE Watchdog Timer Reset Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will enable the Watchdog timer reset function.\n 1 1 read-write 0 Watchdog timer reset function Disabled #0 1 Watchdog timer reset function Enabled #1 WTWKE Watchdog Timer Wake-Up Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n 2 1 read-write 0 Watchdog timer Wake-up CPU function Disabled #0 1 Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode #1 IER WDT_IER Watchdog Timer Interrupt Enable Register 0x4 read-write n 0x0 0x0 WDT_IE Watchdog Timer Interrupt Enable Control\n 0 1 read-write 0 Watchdog timer interrupt Disabled #0 1 Watchdog timer interrupt Enabled #1 ISR WDT_ISR Watchdog Timer Interrupt Status Register 0x8 read-write n 0x0 0x0 WDT_IS Watchdog Timer Interrupt Status (Read Only) If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed. Note: This bit is read only, but can be cleared by writing 1 to it. 0 1 read-only 0 Watchdog timer interrupt does not occur #0 1 Watchdog timer interrupt occurs #1 WDT_RST_IS Watchdog Timer Reset Status (Read Only) When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is read only, but can be cleared by writing 1 to it. 1 1 read-only 0 Watchdog timer reset does not occur #0 1 Watchdog timer reset occurs #1 WDT_WAKE_IS Watchdog Timer Wake-Up Status (Read Only) If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit. Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. Note2: After one engine clock., this bit can be cleared by writing 1 to it 2 1 read-only 0 Watchdog timer does not cause system wake-up #0 1 Wake system up from power-down mode by Watchdog time-out #1