nuvoTon NM1330AE_v1 2024.04.27 NM1330AE_v1 SVD file 8 32 ACMP01 ACMP Register Map ACMP 0x0 0x0 0xC registers n ACMP_CR0 ACMP_CR0 Analog Comparator 0 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Analog Comparator 0 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set. 0 1 read-write 0 Analog Comparator 0 Disabled #0 1 Analog Comparator 0 Enabled #1 ACMPIE Analog Comparator 0 Interrupt Enable Control\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 ACMPOINV Analog Comparator 0 Output Inverse Enable Control \n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 HYSEN Analog Comparator 0 Hysteresis Enable Control\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 NEGSEL Analog Comparator 0 Negative Input Selection\n 4 1 read-write 0 The source of the negative comparator input is from ACMP0_N pin #0 1 The internal band-gap voltage is selected as the source of negative comparator input #1 ACMP_CR1 ACMP_CR1 Analog Comparator 1 Control Register 0x4 read-write n 0x0 0x0 ACMPEN Analog Comparator 1 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set. 0 1 read-write 0 Analog comparator 1 Disabled #0 1 Analog comparator 1 Enabled #1 ACMPIE Analog Comparator 1 Interrupt Enable Control\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 ACMPOINV Analog Comparator 1 Output Inverse Enable Control \n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 HYSEN Analog Comparator 1 Hysteresis Enable Control\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 NEGSEL Analog Comparator 1 Negative Input Selection\n 4 1 read-write 0 The source of the negative comparator input is from ACMP1_N pin #0 1 The internal band-gap voltage is selected as the source of negative comparator input #1 ACMP_SR01 ACMP_SR01 Analog Comparator 0/1 Status Register 0x8 read-write n 0x0 0x0 ACMPF0 Analog Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will generate an interrupt if ACMP_CR0[1] is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write 0 Analog comparator 0 output does not change #0 1 Analog comparator 0 output changed since this bit was cleared to 0 #1 ACMPF1 Analog Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will generate an interrupt if ACMP_CR1[1] is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write 0 Analog comparator 1 output does not change #0 1 Analog comparator 1 output changed since this bit was cleared to 0 #1 ACMPO0 Analog Comparator 0 Output\n 2 1 read-write 0 Analog comparator 0 outputs 0 #0 1 Analog comparator 0 outputs 1 #1 ACMPO1 Analog Comparator 1 Output\n 3 1 read-write 0 Analog comparator 1 outputs 0 #0 1 Analog comparator 1 outputs 1 #1 ACMP23 ACMP Register Map ACMP 0x0 0x0 0xC registers n ACMP_CR2 ACMP_CR2 Analog Comparator 2 Control Register 0x0 read-write n 0x0 0x0 ACMPEN Analog Comparator 2 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set. 0 1 read-write 0 Analog Comparator 2 Disabled #0 1 Analog Comparator 2 Enabled #1 ACMPIE Analog Comparator 2 Interrupt Enable Control\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 ACMPOINV Analog Comparator 2 Output Inverse Enable Control\n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 HYSEN Analog Comparator 2 Hysteresis Enable Control\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 NEGSEL Analog Comparator 2 Negative Input Selection\n 4 1 read-write 0 The source of the negative comparator input is from ACMP2_N pin #0 1 The internal band-gap voltage is selected as the source of negative comparator input #1 ACMP_CR3 ACMP_CR3 Analog Comparator 3 Control Register 0x4 read-write n 0x0 0x0 ACMPEN Analog Comparator 3 Enable Control\nNote: Analog comparator output needs to wait 2 us stable time after ACMPEN is set. 0 1 read-write 0 Analog comparator 3 Disabled #0 1 Analog comparator 3 Enabled #1 ACMPIE Analog Comparator 3 Interrupt Enable Control\n 1 1 read-write 0 Interrupt function Disabled #0 1 Interrupt function Enabled #1 ACMPOINV Analog Comparator 3 Output Inverse Enable Control\n 6 1 read-write 0 The comparator output inverse function Disabled #0 1 The comparator output inverse function Enabled #1 HYSEN Analog Comparator 3 Hysteresis Enable Control\n 2 1 read-write 0 Hysteresis function Disabled #0 1 Hysteresis function Enabled #1 NEGSEL Analog Comparator 3 Negative Input Selection\n 4 1 read-write 0 The source of the negative comparator input is from ACMP3_N pin #0 1 The internal band-gap voltage is selected as the source of negative comparator input #1 ACMP_SR23 ACMP_SR23 Analog Comparator 2/3 Status Register 0x8 read-write n 0x0 0x0 ACMPF2 Analog Comparator 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state. This will generate an interrupt if ACMP_CR2[1] is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write 0 Analog comparator 2 output does not change #0 1 Analog comparator 2 output changed since this bit was cleared to 0 #1 ACMPF3 Analog Comparator 3 Flag\nThis bit is set by hardware whenever the comparator 3 output changes state. This will generate an interrupt if ACMP_CR3[1] is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write 0 Analog comparator 3 output does not change #0 1 Analog comparator 3 output changed since this bit was cleared to 0 #1 ACMPO2 Analog Comparator 2 Output\n 2 1 read-write 0 Analog comparator 2 outputs 0 #0 1 Analog comparator 2 outputs 1 #1 ACMPO3 Analog Comparator 3 Output\n 3 1 read-write 0 Analog comparator 3 outputs 0 #0 1 Analog comparator 3 outputs 1 #1 ADC ADC Register Map ADC 0x0 0x0 0x30 registers n 0x44 0x4 registers n ADCHER ADCHER ADC Channel Enable Register 0x24 read-write n 0x0 0x0 CHEN Analog Input Channel Enable Control\nSet CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\n 0 8 read-write 0 Channel Disabled 0 1 Channel Enabled 1 PRESEL Analog Input Channel 7 Source Selection\nNote: When the band-gap voltage is selected as the analog input source of ADC channel 7, ADC peripheral clock rate needs to be limited to lower than 300 kHz. 8 2 read-write 0 External analog input #00 1 Internal band-gap voltage #01 2 Internal temperature sensor #10 3 Reserved #11 ADCMPR0 ADCMPR0 ADC Compare Register 0 0x28 read-write n 0x0 0x0 CMPCH Compare Channel Selection\n 3 3 read-write 0 Channel 0 conversion result is selected to be compared #000 1 Channel 1 conversion result is selected to be compared #001 2 Channel 2 conversion result is selected to be compared #010 3 Channel 3 conversion result is selected to be compared #011 4 Channel 4 conversion result is selected to be compared #100 5 Channel 5 conversion result is selected to be compared #101 6 Channel 6 conversion result is selected to be compared #110 7 Channel 7 conversion result is selected to be compared #111 CMPCOND Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set. 2 1 read-write 0 Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #0 1 Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one #1 CMPD Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: When DIFFEN bit is set to 1, ADC comparator compares CMPD with conversion result with unsigned format (M05xxBN only). CMPD should be filled in unsigned format (straight binary format). 16 12 read-write CMPEN Compare Enable Control\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.\n 0 1 read-write 0 Compare function Disabled #0 1 Compare function Enabled #1 CMPIE Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.\n 1 1 read-write 0 Compare function interrupt Disabled #0 1 Compare function interrupt Enabled #1 CMPMATCNT Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set. 8 4 read-write ADCMPR1 ADCMPR1 0x2C read-write n 0x0 0x0 ADCR ADCR ADC Control Register 0x20 read-write n 0x0 0x0 ADEN A/D Converter Enable\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption. 0 1 read-write 0 A/D converter Disabled #0 1 A/D converter Enabled #1 ADIE A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n 1 1 read-write 0 A/D interrupt function Disabled #0 1 A/D interrupt function Enabled #1 ADMD A/D Converter Operation Mode Control\nNote1: When changing the operation mode, software should clear ADST bit firstly.\nNote2: In Burst mode, the A/D result data always at Data Register 0. 2 2 read-write 0 Single conversion #00 1 Burst conversion #01 2 Single-cycle Scan #10 3 Continuous Scan #11 ADST A/D Conversion Start\nADST bit can be set to 1 from two sources: software or external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.\nNote: After the ADST bit is cleared to 0, user must wait at least one ADC peripheral clock cycle before setting the ADST bit to 1 again (M05xxBN only). 11 1 read-write 0 Conversion stops and A/D converter enters idle state #0 1 Conversion starts #1 DIFFEN Differential Input Mode Control\n 10 1 read-write 0 Single-end analog input mode #0 1 Differential analog input mode #1 DMOF Differential Input Mode Output Format\nNote: Burst mode and ADC compare function cannot suppert 2's complement output format, this DMOF bit must be cleared to 0 (M05xxBN only). 31 1 read-write 0 A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format) #0 1 A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format #1 TRGCOND External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.\n 6 2 read-write 0 Low level #00 1 High level #01 2 Falling edge #10 3 Rising edge #11 TRGEN External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode. 8 1 read-write 0 External trigger Disabled #0 1 External trigger Enabled #1 TRGS Hardware Trigger Source\nSoftware should clear TRGEN bit and ADST bit to 0 before changing TRGS.\nNote: ADC hardware trigger source does not support PWM trigger (M05xxBN only). 4 2 read-write 0 A/D conversion is started by external STADC pin #00 3 A/D conversion is started by PWM trigger #11 ADDR0 ADDR0 ADC Data Register 0 0x0 read-only n 0x0 0x0 OVERRUN Overrun Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read. 16 1 read-only 0 Data in RSLT is not overwrote #0 1 Data in RSLT is overwrote #1 RSLT A/D Conversion Result\nThis field contains conversion result of ADC. 0 16 read-only VALID Valid Flag \nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.\nThis is a read only bit.\nNote: When ADC is converting, if user wants to monitor the VALID flag of a specified channel, user should poll the VALID bit of ADSR register instead of polling this bit (M05xxBN only). 17 1 read-only 0 Data in RSLT bits is not valid #0 1 Data in RSLT bits is valid #1 ADDR1 ADDR1 0x4 read-write n 0x0 0x0 ADDR2 ADDR2 0x8 read-write n 0x0 0x0 ADDR3 ADDR3 0xC read-write n 0x0 0x0 ADDR4 ADDR4 0x10 read-write n 0x0 0x0 ADDR5 ADDR5 0x14 read-write n 0x0 0x0 ADDR6 ADDR6 0x18 read-write n 0x0 0x0 ADDR7 ADDR7 0x1C read-write n 0x0 0x0 ADSR ADSR ADC Status Register 0x30 read-write n 0x0 0x0 ADF A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than 4 samples in FIFO in Burst mode. 0 1 read-write BUSY BUSY/IDLE\nThis bit is a mirror of ADST bit in ADCR register. It is read only.\n 3 1 read-write 0 A/D converter is in idle state #0 1 A/D converter is busy at conversion #1 CHANNEL Current Conversion Channel\nIt is read only. 4 3 read-write CMPF0 Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 then this bit is set to 1. This bit is cleared by writing 1 to it.\n 1 1 read-write 0 Conversion result in ADDR does not meet ADCMPR0 setting #0 1 Conversion result in ADDR meets ADCMPR0 setting #1 CMPF1 Compare Flag 1 When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 then this bit is set to 1 it is cleared by writing 1 to self. 2 1 read-write 0 Conversion result in ADDR does not meet ADCMPR1 setting #0 1 Conversion result in ADDR meets ADCMPR1 setting #1 OVERRUN Overrun Flag (Read Only)\nIt is a mirror of OVERRUN bit in ADDRx register.\nWhen ADC is in Burst mode and the FIFO is overrun, all bits of OVERRUN[7:0] will be set to 1. 16 8 read-only VALID Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADDRx register.\nWhen ADC is in Burst mode and any conversion result is valid, all bits of VALID[7:0] will be set to 1. 8 8 read-only ADTDCR ADTDCR ADC Trigger Delay Control Register 0x44 read-write n 0x0 0x0 PTDT PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock 0 8 read-write CLK CLK Register Map CLK 0x0 0x0 0x28 registers n AHBCLK AHBCLK AHB Devices Clock Enable Control Register 0x4 -1 read-write n 0x0 0x0 EBI_EN EBI Controller Clock Enable Control\n 3 1 read-write 0 EBI engine clock Disabled #0 1 EBI engine clock Enabled #1 HDIV_EN Divider Controller Clock Enable Control \n 4 1 read-write 0 Divider controller engine clock Disabled #0 1 Divider controller engine clock Enabled #1 ISP_EN Flash ISP Controller Clock Enable Control\n 2 1 read-write 0 Flash ISP engine clock Disabled #0 1 Flash ISP engine clock Enabled #1 APBCLK APBCLK APB Devices Clock Enable Control Register 0x8 read-write n 0x0 0x0 ACMP01_EN Analog Comparator 0/1 Clock Enable Control\n 30 1 read-write 0 Analog Comparator 0/1 clock Disabled #0 1 Analog Comparator 0/1 clock Enabled #1 ACMP23_EN Analog Comparator 2/3 Clock Enable Control (M051xxDE Only)\n 31 1 read-write 0 Analog Comparator 2/3 clock Disabled #0 1 Analog Comparator 2/3 clock Enabled #1 ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control\n 28 1 read-write 0 ADC peripheral clock Disabled #0 1 ADC peripheral clock Enabled #1 FDIV_EN Frequency Divider Output Clock Enable Control\n 6 1 read-write 0 FDIV clock Disabled #0 1 FDIV clock Enabled #1 I2C0_EN I2C0 Clock Enable Control\n 8 1 read-write 0 I2C clock Disabled #0 1 I2C clock Enabled #1 I2C1_EN I2C1 Clock Enable Control (M051xxDE Only)\n 9 1 read-write 0 I2C clock Disabled #0 1 I2C clock Enabled #1 PWM01_EN PWM_01 Clock Enable Control\n 20 1 read-write 0 PWM01 clock Disabled #0 1 PWM01 clock Enabled #1 PWM23_EN PWM_23 Clock Enable Control\n 21 1 read-write 0 PWM23 clock Disabled #0 1 PWM23 clock Enabled #1 PWM45_EN PWM_45 Clock Enable Control\n 22 1 read-write 0 PWM45 clock Disabled #0 1 PWM45 clock Enabled #1 PWM67_EN PWM_67 Clock Enable Control\n 23 1 read-write 0 PWM67 clock Disabled #0 1 PWM67 clock Enabled #1 SPI0_EN SPI0 Peripheral Clock Enable Control\n 12 1 read-write 0 SPI0 peripheral clock Disabled #0 1 SPI0 peripheral clock Enabled #1 SPI1_EN SPI1 Peripheral Clock Enable Control\n 13 1 read-write 0 SPI1 peripheral clock Disabled #0 1 SPI1 peripheral clock Enabled #1 TMR0_EN Timer0 Clock Enable Control\n 2 1 read-write 0 Timer0 clock Disabled #0 1 Timer0 clock Enabled #1 TMR1_EN Timer1 Clock Enable Control\n 3 1 read-write 0 Timer1 clock Disabled #0 1 Timer1 clock Enabled #1 TMR2_EN Timer2 Clock Enable Control\n 4 1 read-write 0 Timer2 clock Disabled #0 1 Timer2 clock Enabled #1 TMR3_EN Timer3 Clock Enable Control\n 5 1 read-write 0 Timer3 clock Disabled #0 1 Timer3 clock Enabled #1 UART0_EN UART0 Clock Enable Control\n 16 1 read-write 0 UART0 clock Disabled #0 1 UART0 clock Enabled #1 UART1_EN UART1 Clock Enable Control\n 17 1 read-write 0 UART1 clock Disabled #0 1 UART1 clock Enabled #1 WDT_EN Watchdog Timer Clock Enable Control (Write Protect) Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Watchdog Timer clock Disabled #0 1 Watchdog Timer clock Enabled #1 CLKDIV CLKDIV Clock Divider Number Register 0x18 read-write n 0x0 0x0 ADC_N ADC peripheral Clock Divide Number from ADC peripheral Clock Source\n 16 8 read-write HCLK_N HCLK Clock Divide Number from HCLK Clock Source\n 0 4 read-write UART_N UART Clock Divide Number from UART Clock Source\n 8 4 read-write CLKSEL0 CLKSEL0 Clock Source Select Control Register 0 0x10 -1 read-write n 0x0 0x0 HCLK_S HCLK Clock Source Selection (Write Protect) Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable. Note2: The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. Note3: These bits are protected bit, and programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 3 read-write 0 Clock source is from HXT #000 1 Reserved #001 2 Clock source is from PLL #010 3 Clock source is from LIRC #011 7 Clock source is from HIRC #111 STCLK_S Cortex-M0 SysTick Clock Source Selection from Reference Clock (Write Protect)\n 3 3 read-write 0 Clock source is from HXT #000 1 Reserved #001 2 Clock source is from HXT/2 #010 3 Clock source is from HCLK/2 #011 7 Clock source is from HIRC/2 #111 CLKSEL1 CLKSEL1 Clock Source Select Control Register 1 0x14 -1 read-write n 0x0 0x0 ADC_S ADC Peripheral Clock Source Selection\n 2 2 read-write 0 Clock source is from HXT #00 1 Clock source is from PLL #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 PWM01_S PWM0 and PWM1 Clock Source Selection PWM0 and PWM1 use the same Engine clock source both of them use the same prescaler. 28 2 read-write 0 Clock source is from HXT #00 1 Clock source is from LIRC. (M051xxDE Only) #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 PWM23_S PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 use the same Engine clock source both of them use the same prescaler. 30 2 read-write 0 Clock source is from HXT #00 1 Clock source is from LIRC. (M051xxDE Only) #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 SPI0_S SPI0 clock Source Selection (M051xxDN/DE Only)\n 4 1 read-write 0 Clock source is from PLL #0 1 Clock source is from HCLK #1 SPI1_S SPI1 clock Source Selection (M051xxDN/DE Only)\n 5 1 read-write 0 Clock source is from PLL #0 1 Clock source is from HCLK #1 TMR0_S TIMER0 Clock Source Selection\n 8 3 read-write 0 Clock source is from HXT #000 2 Clock source is from HCLK #010 3 Clock source is from external trigger T0. (M051xxDN/DE Only) #011 5 Clock source is from LIRC. (M051xxDN/DE Only) #101 7 Clock source is from HIRC #111 TMR1_S TIMER1 Clock Source Selection\n 12 3 read-write 0 Clock source is from HXT #000 2 Clock source is from HCLK #010 3 Clock source is from external trigger T1. (M051xxDN/DE Only) #011 5 Clock source is from LIRC. (M051xxDN/DE Only) #101 7 Clock source is from HIRC #111 TMR2_S TIMER2 Clock Source Selection\n 16 3 read-write 0 Clock source is from HXT #000 2 Clock source is from HCLK #010 3 Clock source is from external trigger T2. (M051xxDN/DE Only) #011 5 Clock source is from LIRC. (M051xxDN/DE Only) #101 7 Clock source is from HIRC #111 TMR3_S TIMER3 Clock Source Selection\n 20 3 read-write 0 Clock source is from HXT #000 2 Clock source is from HCLK #010 3 Clock source is from external trigger T3. (M051xxDN/DE Only) #011 5 Clock source is from LIRC. (M051xxDN/DE Only) #101 7 Clock source is from HIRC #111 UART_S UART Clock Source Selection\n 24 2 read-write 0 Clock source is from HXT #00 1 Clock source is from PLL #01 2 Reserved #10 3 Clock source is from HIRC #11 WDT_S Watchdog Timer Clock Source Selection (Write Protect) Note: These bits are protected bits, and programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 2 read-write 0 Reserved #00 1 Reserved #01 2 Clock source is from HCLK/2048 clock #10 3 Clock source is from LIRC #11 CLKSEL2 CLKSEL2 Clock Source Select Control Register 2 0x1C -1 read-write n 0x0 0x0 FRQDIV_S Clock Divider Clock Source Selection\n 2 2 read-write 0 Clock source is from HXT #00 1 Clock source is from LIRC. (M051xxDE Only) #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 PWM45_S PWM4 and PWM5 Clock Source Selection PWM4 and PWM5 use the same Engine clock source both of them used the same prescaler. 4 2 read-write 0 Clock source is from HXT #00 1 Clock source is from LIRC. (M051xxDE Only) #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 PWM67_S PWM6 and PWM7 Clock Source Selection PWM6 and PWM7 used the same Engine clock source both of them used the same prescaler. 6 2 read-write 0 Clock source is from HXT #00 1 Clock source is from LIRC. (M051xxDE Only) #01 2 Clock source is from HCLK #10 3 Clock source is from HIRC #11 WWDT_S Window Watchdog Timer Clock Source Selection (M051xxDN/DE Only)\n 16 2 read-write 2 Clock source is from HCLK/2048 clock #10 3 Clock source is from LIRC #11 CLKSTATUS CLKSTATUS Clock status monitor Register 0xC read-write n 0x0 0x0 CLK_SW_FAIL Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: On M05xxBN, software can write 1 to clear the bit to 0.\nNote3: On M05xxDN/DE, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SE_FAIL will be cleared automatically by hardware. 7 1 read-write 0 Clock switching success #0 1 Clock switching failed #1 OSC10K_STB 10 kHz Internal Low Speed RC Oscillator (LIRC) Stable Flag (Read Only)\n 3 1 read-only 0 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) clock is stable #1 OSC22M_STB 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Stable Flag (Read Only)\n 4 1 read-only 0 22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable #1 PLL_STB Internal PLL Clock Source Stable Flag (Read Only)\n 2 1 read-only 0 Internal PLL clock is not stable or disabled #0 1 Internal PLL clock is stable #1 XTL12M_STB 4~24 MHz External High Speed Crystal (HXT) Stable Flag (Read Only)\n 0 1 read-only 0 4~24 MHz external high speed crystal (HXT) clock is not stable or disabled #0 1 4~24 MHz external high speed crystal (HXT) clock is stable #1 FRQDIV FRQDIV Frequency Divider Control Register 0x24 read-write n 0x0 0x0 DIVIDER1 Frequency Divider 1 Enable Control (M051xxDE Only) \n 5 1 read-write 0 Divider output frequency is depended on FSEL value #0 1 Divider output frequency is the same as input clock frequency #1 DIVIDER_EN Frequency Divider Enable Control\n 4 1 read-write 0 Frequency Divider Disabled #0 1 Frequency Divider Enabled #1 FSEL Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]. 0 4 read-write PLLCON PLLCON PLL Control Register 0x20 -1 read-write n 0x0 0x0 BP PLL Bypass Control\n 17 1 read-write 0 PLL is in Normal mode (default) #0 1 PLL clock output is same as PLL source clock input #1 FB_DV PLL Feedback Divider Control\nRefer to the formulas below the table. 0 9 read-write IN_DV PLL Input Divider Control\nRefer to the formulas below the table. 9 5 read-write OE PLL OE (FOUT Enable) Pin Control\n 18 1 read-write 0 PLL FOUT Enabled #0 1 PLL FOUT is fixed low #1 OUT_DV PLL Output Divider Control\nRefer to the formulas below the table. 14 2 read-write PD Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n 16 1 read-write 0 PLL is in Normal mode #0 1 PLL is in Power-down mode (default) #1 PLL_SRC PLL Source Clock Selection\n 19 1 read-write 0 PLL source clock from HXT #0 1 PLL source clock from HIRC #1 PWRCON PWRCON System Power-down Control Register 0x0 -1 read-write n 0x0 0x0 OSC10K_EN 10 kHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\n 3 1 read-write 0 10 kHz internal low speed RC oscillator (LIRC) Disabled #0 1 10 kHz internal low speed RC oscillator (LIRC) Enabled #1 OSC22M_EN 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\n 2 1 read-write 0 22.1184 MHz internal high speed RC oscillator (HIRC) Disabled #0 1 22.1184 MHz internal high speed RC oscillator (HIRC) Enabled #1 PD_WAIT_CPU Power-down Entry Condition Control (Write Protect)\n 8 1 read-write 0 Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1 #0 1 Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction #1 PD_WU_DLY Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal (HXT), and 256 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\n 4 1 read-write 0 Clock cycles delay Disabled #0 1 Clock cycles delay Enabled #1 PD_WU_INT_EN Power-down Mode Wake-up Interrupt Enable Control (Write Protect) Note: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. 5 1 read-write 0 Disabled #0 1 Enabled #1 PD_WU_STS Power-down Mode Wake-up Interrupt Status Set by Power-down wake-up event , which indicates that resume from Power-down mode The flag is set if the GPIO, UART, WDT, ACMP or BOD wake-up occurred. Note: This bit works only if PD_WU_INT_EN (PWRCON[5]) set to 1. Write 1 to clear the bit to 0. 6 1 read-write PWR_DOWN_EN System Power-down Enable Bit (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, then the chip keeps active till CPU run WFI instruction.\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.\n 7 1 read-write 0 Chip operating normally or chip in Idle mode because of WFI command #0 1 Chip enters Power-down mode instantly or waits CPU sleep command WFI #1 XTL12M_EN 4~24 MHz External High Speed Crystal (HXT) Enable Control (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal, this bit is set to 1 automatically.\n 0 1 read-write 0 4 ~ 24 MHz external high speed crystal oscillator (HXT) Disabled #0 1 4 ~ 24 MHz external high speed crystal oscillator (HXT) Enabled #1 EBI EBI Register Map EBI 0x0 0x0 0xC registers n EBICON EBICON External Bus Interface General Control Register 0x0 read-write n 0x0 0x0 ExtBW16 EBI Data Width 16-bit / 8-bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n 1 1 read-write 0 EBI data width is 8 bit #0 1 EBI data width is 16 bit #1 ExtEN EBI Enable Control\nThis bit is the functional enable bit for EBI.\n 0 1 read-write 0 EBI function Disabled #0 1 EBI function Enabled #1 ExttALE Expand Time of ALE\nThis field is used to control the ALE pulse width (tALE) for address latch.\n 16 3 read-write MCLKDIV External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follows:\nNote: The default value of output clock is HCLK/1. 8 3 read-write 0 MCLK frequency is HCLK/1 #000 1 MCLK frequency is HCLK/2 #001 2 MCLK frequency is HCLK/4 #010 3 MCLK frequency is HCLK/8 #011 4 MCLK frequency is HCLK/16 #100 5 MCLK frequency is HCLK/32 #101 EBICON2 EBICON2 External Bus Interface General Control Register 2 0x8 read-write n 0x0 0x0 RAHD_OFF Access Hold Time Disable Control When Read\n 1 1 read-write 0 tAHD is controlled by ExttAHD[2:0] when read through EBI #0 1 Zero tAHD when read through EBI #1 WAHD_OFF Access Hold Time Disable Control When Write\n 2 1 read-write 0 tAHD is controlled by ExttAHD[2:0] when write through EBI #0 1 Zero tAHD when write through EBI #1 WBUFF_EN EBI Write Buffer Enable Control\nEnable this function to improve CPU and EBI access performance.\n 0 1 read-write 0 EBI write buffer Disabled #0 1 EBI write buffer Enabled #1 EXTIME EXTIME External Bus Interface Timing Control Register 0x4 read-write n 0x0 0x0 ExtIR2R Idle State Cycle Between Read-Read\nWhen read action is finished and the next action is going to read, idle state is inserted and nCS signal return to high if ExtIR2R is not 0.\n 24 4 read-write ExtIW2X Idle State Cycle After Write\nWhen write action is finished, idle state is inserted and nCS signal return to high if ExtIW2X is not 0.\n 12 4 read-write ExttACC EBI Data Access Time\nExttACC defines data access time (tACC).\n 3 5 read-write ExttAHD EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD).\n 8 3 read-write FMC FMC Register Map FMC 0x0 0x0 0x1C registers n 0x40 0x4 registers n DFBADR DFBADR Data Flash Base Address 0x14 -1 read-only n 0x0 0x0 DFBADR Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nFor 8/16/32/64 Kbytes flash memory device, the Data Flash size is 4 Kbytes and it start address is fixed at 0x0001_F000 by hardware internally. 0 32 read-only FATCON FATCON Flash Access Time Control Register 0x18 read-write n 0x0 0x0 LFOM Low Frequency Optimization Mode Control (Write Protect)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n 4 1 read-write 0 Low frequency optimization mode Disabled #0 1 Low frequency optimization mode Enabled #1 ISPADR ISPADR ISP Address Register 0x4 read-write n 0x0 0x0 ISPADR ISP Address \nThe M05xxBN/DN/DE has a maximum 16K x 32-bit (64 KB) of embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00'b for ISP operation. 0 32 read-write ISPCMD ISPCMD ISP Command Register 0xC read-write n 0x0 0x0 ISPCMD ISP Command \nISP commands are shown below:\n 0 6 read-write 0 Read 0x00 4 Read Unique ID 0x04 11 Read Company ID (0xDA) 0x0b 33 Program 0x21 34 Page Erase 0x22 46 Set Vector Page Re-Map 0x2e ISPCON ISPCON ISP Control Register 0x0 read-write n 0x0 0x0 APUEN APROM Update Enable Control (Write Protect)\n 3 1 read-write 0 APROM cannot be updated when chip runs in APROM #0 1 APROM can be updated when chip runs in APROM #1 BS Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.\n 1 1 read-write 0 Boot from APROM #0 1 Boot from LDROM #1 CFGUEN CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n 4 1 read-write 0 ISP update User Configuration Disabled #0 1 ISP update User Configuration Enabled #1 ISPEN ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n 0 1 read-write 0 ISP function Disabled #0 1 ISP function Enabled #1 ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself. \n(3) Destination address is illegal, such as over an available range.\nNote: Write 1 to clear this bit to 0. 6 1 read-write LDUEN LDROM Update Enable Control (Write Protect)\n 5 1 read-write 0 LDROM cannot be updated #0 1 LDROM can be updated when the MCU runs in APROM #1 ISPDAT ISPDAT ISP Data Register 0x8 read-write n 0x0 0x0 ISPDAT ISP Data \nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation. 0 32 read-write ISPSTA ISPSTA ISP Status Register 0x40 read-write n 0x0 0x0 CBS Chip Boot Select (Read Only)\nThis is a mirror of CBS in CONFIG0. 1 2 read-only ISPFF ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: The function of this bit is the same as ISPCON bit 6 6 1 read-write ISPGO ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0 0 1 read-only 0 ISP operation is finished #0 1 ISP operation is progressed #1 VECMAP Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF} 9 12 read-only ISPTRG ISPTRG ISP Trigger Control Register 0x10 read-write n 0x0 0x0 ISPGO ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n 0 1 read-write 0 ISP operation is finished #0 1 ISP operation is progressed #1 GCR GCR Register Map GCR 0x0 0x0 0x10 registers n 0x100 0x4 registers n 0x18 0x8 registers n 0x24 0x4 registers n 0x30 0x14 registers n BODCR BODCR Brown-out Detector Control Register 0x18 -1 read-write n 0x0 0x0 BOD_EN Brown-out Detector Enable Control (Write Protect) The default value is set by flash controller user configuration register config0 bit[23] Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Brown-out Detector function Disabled #0 1 Brown-out Detector function Enabled #1 BOD_INTF Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write 0 Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting #0 1 When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled #1 BOD_LPM Brown-out Detector Low power Mode (Write Protect) Note1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response. Note2: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 5 1 read-write 0 BOD operated in Normal mode (default) #0 1 BOD Low Power mode Enabled #1 BOD_OUT Brown-out Detector Output Status\n 6 1 read-write 0 Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0 #0 1 Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled, this bit always responds to 0 #1 BOD_RSTEN Brown-out Reset Enable Control (Write Protect) Note1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high). Note2: The default value is set by flash controller user configuration register config0 bit[20]. Note3: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 Brown-out INTERRUPT function Enabled #0 1 Brown-out RESET function Enabled #1 BOD_VL Brown-out Detector Threshold Voltage Select (Write Protect)\n 1 2 read-write LVR_EN Low Voltage Reset Enable Control (Write Protect) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 7 1 read-write 0 Low Voltage Reset function Disabled #0 1 Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default) #1 IPRSTC1 IPRSTC1 Peripheral Reset Control Register 1 0x8 read-write n 0x0 0x0 CHIP_RST Chip One-shot Reset (Write Protect) Setting this bit will reset the whole chip, including Cortext-M0 core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset. All the chip controllers are reset and the chip setting from CONFIG0 are also reload. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 1 read-write 0 Chip normal operation #0 1 Chip one-shot reset #1 CPU_RST Cortext-M0 Core One-shot Reset (Write Protect) Setting this bit will only reset the Cortext-M0 core and Flash Memory Controller (FMC), and this bit will automatically return 0 after the two clock cycles. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 1 1 read-write 0 Cortext-M0 core normal operation #0 1 Cortext-M0 core one-shot reset #1 EBI_RST EBI Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 3 1 read-write 0 EBI controller normal operation #0 1 EBI controller reset #1 HDIV_RST HDIV Controller Reset (Write Protect) Set this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 4 1 read-write 0 Hardware divider controller normal operation #0 1 Hardware divider controller reset #1 IPRSTC2 IPRSTC2 Peripheral Reset Control Register 2 0xC read-write n 0x0 0x0 ACMP01_RST Analog Comparator A Controller Reset\n 22 1 read-write 0 Analog Comparator A controller normal operation #0 1 Analog Comparator A controller reset #1 ACMP23_RST Analog Comparator B Controller Reset \n 23 1 read-write 0 Analog Comparator B controller normal operation #0 1 Analog Comparator B controller reset #1 ADC_RST ADC Controller Reset\n 28 1 read-write 0 ADC controller normal operation #0 1 ADC controller reset #1 GPIO_RST GPIO (P0~P4) Controller Reset\n 1 1 read-write 0 GPIO controller normal operation #0 1 GPIO controller reset #1 I2C0_RST I2C Controller Reset\n 8 1 read-write 0 I2C0 controller normal operation #0 1 I2C0 controller reset #1 I2C1_RST I2C1 Controller Reset \n 9 1 read-write 0 I2C1 controller normal operation #0 1 I2C1 controller reset #1 PWM03_RST PWM03 Controller Reset\n 20 1 read-write 0 PWM03 controller normal operation #0 1 PWM03 controller reset #1 PWM47_RST PWM47 Controller Reset\n 21 1 read-write 0 PWM47 controller normal operation #0 1 PWM47 controller reset #1 SPI0_RST SPI0 Controller Reset\n 12 1 read-write 0 SPI0 controller normal operation #0 1 SPI0 controller reset #1 SPI1_RST SPI1 Controller Reset\n 13 1 read-write 0 SPI1 controller normal operation #0 1 SPI1 controller reset #1 TMR0_RST Timer0 Controller Reset\n 2 1 read-write 0 Timer0 controller normal operation #0 1 Timer0 controller reset #1 TMR1_RST Timer1 Controller Reset\n 3 1 read-write 0 Timer1 controller normal operation #0 1 Timer1 controller reset #1 TMR2_RST Timer2 Controller Reset\n 4 1 read-write 0 Timer2 controller normal operation #0 1 Timer2 controller reset #1 TMR3_RST Timer3 Controller Reset\n 5 1 read-write 0 Timer3 controller normal operation #0 1 Timer3 controller reset #1 UART0_RST UART0 Controller Reset\n 16 1 read-write 0 UART0 controller normal operation #0 1 UART0 controller reset #1 UART1_RST UART1 Controller Reset\n 17 1 read-write 0 UART1 controller normal operation #0 1 UART1 controller reset #1 P0_MFP P0_MFP P0 Multiple Function and Input Type Control Register 0x30 read-write n 0x0 0x0 P0_ALT0 P0.0 Alternate Function Selection\n 8 1 read-write P0_ALT1 P0.1 Alternate Function Selection\n 9 1 read-write P0_ALT10 P0.0 Alternate Function Selection1 \nThe pin function of P0.0 depends on P0_MFP[0], P0_ALT[0], and P0_ALT1[0].\nRefer to P0_ALT[0] for detailed description. 24 1 read-write P0_ALT11 P0.1 Alternate Function Selection1 \nThe pin function of P0.1 depends on P0_MFP[1], P0_ALT[1], and P0_ALT1[1].\nRefer to P0_ALT[1] for detailed description. 25 1 read-write P0_ALT2 P0.2 Alternate Function Selection\n 10 1 read-write P0_ALT3 P0.3 Alternate Function Selection\n 11 1 read-write P0_ALT4 P0.4 Alternate Function Selection\n 12 1 read-write P0_ALT5 P0.5 Alternate Function Selection\n 13 1 read-write P0_ALT6 P0.6 Alternate Function Selection\n 14 1 read-write P0_ALT7 P0.7 Alternate Function Selection\n 15 1 read-write P0_MFP P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for detailed description. 0 8 read-write P0_TYPEn P0[7:0] Input Schmitt Trigger Function Enable Control\n 16 8 read-write 0 P0[7:0] I/O input Schmitt Trigger function Disabled 0 1 P0[7:0] I/O input Schmitt Trigger function Enabled 1 P1_MFP P1_MFP P1 Multiple Function and Input Type Control Register 0x34 read-write n 0x0 0x0 P1_ALT0 P1.0 Alternate Function Selection\n 8 1 read-write P1_ALT1 P1.1 Alternate Function Selection\n 9 1 read-write P1_ALT2 P1.2 Alternate Function Selection\n 10 1 read-write P1_ALT3 P1.3 Alternate Function Selection\n 11 1 read-write P1_ALT4 P1.4 Alternate Function Selection\n 12 1 read-write P1_ALT5 P1.5 Alternate Function Selection\n 13 1 read-write P1_ALT6 P1.6 Alternate Function Selection\n 14 1 read-write P1_ALT7 P1.7 Alternate Function Selection\n 15 1 read-write P1_MFP P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT for detailed description. 0 8 read-write P1_TYPEn P1[7:0] Input Schmitt Trigger function Enable Control\n 16 8 read-write 0 P1[7:0] I/O input Schmitt Trigger function Disabled 0 1 P1[7:0] I/O input Schmitt Trigger function Enabled 1 P2_MFP P2_MFP P2 Multiple Function and Input Type Control Register 0x38 read-write n 0x0 0x0 P2_ALT0 P2.0 Alternate Function Selection\n 8 1 read-write P2_ALT1 P2.1 Alternate Function Selection\n 9 1 read-write P2_ALT2 P2.2 Alternate Function Selection\n 10 1 read-write P2_ALT3 P2.3 Alternate Function Selection\n 11 1 read-write P2_ALT4 P2.4 Alternate Function Selection\n 12 1 read-write P2_ALT5 P2.5 Alternate Function Selection\n 13 1 read-write P2_ALT6 P2.6 Alternate Function Selection\n 14 1 read-write P2_ALT7 P2.7 Alternate Function Selection\n 15 1 read-write P2_MFP P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for detailed description. 0 8 read-write P2_TYPEn P2[7:0] Input Schmitt Trigger Function Enable Control\n 16 8 read-write 0 P2[7:0] I/O input Schmitt Trigger function Disabled 0 1 P2[7:0] I/O input Schmitt Trigger function Enabled 1 P3_MFP P3_MFP P3 Multiple Function and Input Type Control Register 0x3C read-write n 0x0 0x0 P3_ALT0 P3.0 Alternate Function Selection\n 8 1 read-write P3_ALT1 P3.1 Alternate Function Selection\n 9 1 read-write P3_ALT2 P3.2 Alternate Function Selection\n 10 1 read-write P3_ALT3 P3.3 Alternate Function Selection\n 11 1 read-write P3_ALT4 P3.4 Alternate Function Selection\n 12 1 read-write P3_ALT5 P3.5 Alternate Function Selection\n 13 1 read-write P3_ALT6 P3.6 Alternate Function Selection\n 14 1 read-write P3_ALT7 P3.7 Alternate Function Selection\n 15 1 read-write P3_MFP P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT for detailed description. 0 8 read-write P3_TYPEn P3[7:0] Input Schmitt Trigger function Enable\n 16 8 read-write 0 P3[7:0] I/O input Schmitt Trigger function Disabled 0 1 P3[7:0] I/O input Schmitt Trigger function Enabled 1 P4_MFP P4_MFP P4 Multiple Function and Input Type Control Register 0x40 -1 read-write n 0x0 0x0 P4_ALT0 P4.0 Alternate Function Selection\n 8 1 read-write P4_ALT1 P4.1 Alternate Function Selection\n 9 1 read-write P4_ALT2 P4.2 Alternate Function Selection\n 10 1 read-write P4_ALT3 P4.3 Alternate Function Selection\n 11 1 read-write P4_ALT4 P4.4 Alternate Function Selection\n 12 1 read-write P4_ALT5 P4.5 Alternate Function Selection\n 13 1 read-write P4_ALT6 P4.6 Alternate Function Selection\n 14 1 read-write P4_ALT7 P4.7 Alternate Function Selection\n 15 1 read-write P4_MFP P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT for detailed description. 0 8 read-write P4_TYPEn P4[7:0] Input Schmitt Trigger function Enable Control\n 16 8 read-write 0 P4[7:0] I/O input Schmitt Trigger function Disabled 0 1 P4[7:0] I/O input Schmitt Trigger function Enabled 1 PDID PDID Part Device Identification Number Register 0x0 -1 read-only n 0x0 0x0 PDID Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used. For example, M052LBN PDID code is 0x1000_5200. 0 32 read-only PORCR PORCR Power-on Reset Controller Register 0x24 read-write n 0x0 0x0 POR_DIS_CODE Power-on Reset Enable Control (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRST, Watchdog reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 16 read-write REGWRPROT REGWRPROT Register Write-Protection Control Register 0x100 read-write n 0x0 0x0 REGPROTDIS Register Write-Protection Disable index (Read Only)\n 0 1 read-only 0 Write-protection Enabled for writing protected registers. Any write to the protected register is ignored #0 1 Write-protection Disabled for writing protected registers #1 REGWRPROT Register Write-Protection Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write. 0 8 write-only RSTSRC RSTSRC System Reset Source Register 0x4 read-write n 0x0 0x0 RSTS_BOD Brown-out Detector Reset Flag The RSTS_BOD flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 4 1 read-write 0 No reset from BOD #0 1 The BOD had issued the reset signal to reset the system #1 RSTS_CPU CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0. 7 1 read-write 0 No reset from CPU #0 1 Cortex-M0 core and FMC are reset by software setting CPU_RST to 1 #1 RSTS_LVR Low Voltage Reset Flag The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 3 1 read-write 0 No reset from LVR #0 1 The LVR controller had issued the reset signal to reset the system #1 RSTS_MCU MCU Reset Flag The RSTS_MCU flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 5 1 read-write 0 No reset from Cortex-M0 #0 1 The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core #1 RSTS_POR Power-on Reset Flag The RSTS_POR flag is set by the reset signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 0 1 read-write 0 No reset from POR or CHIP_RST #0 1 The Power-on Reset (POR) or CHIP_RST had issued the reset signal to reset the system #1 RSTS_RESET Reset Pin Reset Flag The RSTS_RESET flag is set by the reset signal from the nRST pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 1 1 read-write 0 No reset from the nRST pin #0 1 The nRST pin had issued the reset signal to reset the system #1 RSTS_WDT Watchdog Reset Flag The RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source. Note: Write 1 to clear this bit to 0. 2 1 read-write 0 No reset from watchdog timer #0 1 The watchdog timer had issued the reset signal to reset the system #1 TEMPCR TEMPCR Temperature Sensor Control Register 0x1C read-write n 0x0 0x0 VTEMP_EN Temperature Sensor Enable Control\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from the ADC conversion result. Please refer to the ADC chapter for detailed ADC conversion functional description. 0 1 read-write 0 Temperature sensor function Disabled (default) #0 1 Temperature sensor function Enabled #1 GP GPIO Register Map GPIO 0x0 0x0 0x24 registers n 0x100 0x24 registers n 0x180 0x4 registers n 0x200 0xA0 registers n 0x40 0x24 registers n 0x80 0x24 registers n 0xC0 0x24 registers n DBNCECON DBNCECON Interrupt De-bounce Control 0x180 -1 read-write n 0x0 0x0 DBCLKSEL De-bounce Sampling Cycle Selection\n 0 4 read-write 0 Sample interrupt input once per 1 clocks #0000 1 Sample interrupt input once per 2 clocks #0001 2 Sample interrupt input once per 4 clocks #0010 3 Sample interrupt input once per 8 clocks #0011 4 Sample interrupt input once per 16 clocks #0100 5 Sample interrupt input once per 32 clocks #0101 6 Sample interrupt input once per 64 clocks #0110 7 Sample interrupt input once per 128 clocks #0111 8 Sample interrupt input once per 256 clocks #1000 9 Sample interrupt input once per 2*256 clocks #1001 10 Sample interrupt input once per 4*256 clocks #1010 11 Sample interrupt input once per 8*256 clocks #1011 12 Sample interrupt input once per 16*256 clocks #1100 13 Sample interrupt input once per 32*256 clocks #1101 14 Sample interrupt input once per 64*256 clocks #1110 15 Sample interrupt input once per 128*256 clocks #1111 DBCLKSRC De-bounce Counter Clock Source Selection\n 4 1 read-write 0 De-bounce counter clock source is the HCLK #0 1 De-bounce counter clock source is the 10 kHz internal low speed oscillator #1 ICLK_ON Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern. 5 1 read-write 0 Edge detection circuit is active only if I/O pin corresponding Px_IEN bit is set to 1 #0 1 All I/O pins edge detection circuit is always active after reset #1 P00_PDIO P00_PDIO GPIO P0.n Pin Data Input/Output 0x200 read-write n 0x0 0x0 Pxn_PDIO GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n]. 0 1 read-write 0 Corresponding GPIO pin set to low #0 1 Corresponding GPIO pin set to high #1 P01_PDIO P01_PDIO 0x204 read-write n 0x0 0x0 P02_PDIO P02_PDIO 0x208 read-write n 0x0 0x0 P03_PDIO P03_PDIO 0x20C read-write n 0x0 0x0 P04_PDIO P04_PDIO 0x210 read-write n 0x0 0x0 P05_PDIO P05_PDIO 0x214 read-write n 0x0 0x0 P06_PDIO P06_PDIO 0x218 read-write n 0x0 0x0 P07_PDIO P07_PDIO 0x21C read-write n 0x0 0x0 P0_DBEN P0_DBEN P0 De-bounce Enable Control 0x14 read-write n 0x0 0x0 DBEN Port 0-4 Pin [n] Input Signal De-bounce Enable Control DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0]. Note2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system waken up which caused by Px.n de-bounce function. 0 16 read-write 0 Px.n de-bounce function Disabled 0 1 Px.n de-bounce function Enabled 1 P0_DMASK P0_DMASK P0 Data Output Write Mask 0xC read-write n 0x0 0x0 DMASK Port 0-4 Pin [n] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit. 0 8 read-write 0 Corresponding Px_DOUT[n] bit can be updated 0 1 Corresponding Px_DOUT[n] bit protected 1 P0_DOUT P0_DOUT P0 Data Output Value 0x8 -1 read-write n 0x0 0x0 DOUT Port 0-4 Pin [n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n 0 16 read-write 0 Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode 0 1 Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode 1 P0_IEN P0_IEN P0 Interrupt Enable Control 0x1C read-write n 0x0 0x0 IF_EN Port 0-4 Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EN[n] bit to 1 :\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\n 0 8 read-write 0 Px.n level low or high to low interrupt Disabled 0 1 Px.n level low or high to low interrupt Enabled 1 IR_EN Port 0-4 Pin [n] Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the IR_EN[n] bit to 1 :\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n 16 8 read-write 0 Px.n level high or low to high interrupt Disabled 0 1 Px.n level high or low to high interrupt Enabled 1 P0_IMD P0_IMD P0 Interrupt Mode Control 0x18 read-write n 0x0 0x0 IMD Port 0-4 Pin [n] Edge or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n 0 16 read-write 0 Edge trigger interrupt 0 1 Level trigger interrupt 1 P0_ISRC P0_ISRC P0 Interrupt Source Flag 0x20 read-write n 0x0 0x0 ISRC Port 0-4 Pin [n] Interrupt Source Flag\nWrite :\n 0 8 read-write 0 No action.\nNo interrupt at Px.n 0 1 Clear the corresponding pending interrupt.\nPx.n generates an interrupt 1 P0_OFFD P0_OFFD P0 Digital Input Path Disable Control 0x4 read-write n 0x0 0x0 OFFD Port 0-4 Pin [n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\n 16 8 read-write 0 Px.n digital input path Enabled 0 1 Px.n digital input path Disabled (digital input tied to low) 1 P0_PIN P0_PIN P0 Pin Value 0x10 read-only n 0x0 0x0 PIN Port 0-4 Pin [n] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. 0 16 read-only P0_PMD P0_PMD P0 I/O Mode Control 0x0 read-write n 0x0 0x0 PMDn Port 0-4 I/O Pin [n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote2: The default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip is powered on (only for M05xxBN).\nNote3: The initial value of this field is defined by CIOINI (CONFIG[10]) (only for M05xxDN/DE).If CIOINI is set to 1, the default value is 0x0000_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 0, the default value is 0x0000_0000 and all pins will be input tri-state mode after chip powered on. 0 16 read-write 0 Px.n is in Input mode 00 1 Px.n is in Push-pull Output mode 01 10 Px.n is in Open-drain Output mode 10 11 Px.n is in Quasi-bidirectional mode 11 P10_PDIO P10_PDIO 0x220 read-write n 0x0 0x0 P11_PDIO P11_PDIO 0x224 read-write n 0x0 0x0 P12_PDIO P12_PDIO 0x228 read-write n 0x0 0x0 P13_PDIO P13_PDIO 0x22C read-write n 0x0 0x0 P14_PDIO P14_PDIO 0x230 read-write n 0x0 0x0 P15_PDIO P15_PDIO 0x234 read-write n 0x0 0x0 P16_PDIO P16_PDIO 0x238 read-write n 0x0 0x0 P17_PDIO P17_PDIO 0x23C read-write n 0x0 0x0 P1_DBEN P1_DBEN 0x54 read-write n 0x0 0x0 P1_DMASK P1_DMASK 0x4C read-write n 0x0 0x0 P1_DOUT P1_DOUT 0x48 read-write n 0x0 0x0 P1_IEN P1_IEN 0x5C read-write n 0x0 0x0 P1_IMD P1_IMD 0x58 read-write n 0x0 0x0 P1_ISRC P1_ISRC 0x60 read-write n 0x0 0x0 P1_OFFD P1_OFFD 0x44 read-write n 0x0 0x0 P1_PIN P1_PIN 0x50 read-write n 0x0 0x0 P1_PMD P1_PMD 0x40 read-write n 0x0 0x0 P20_PDIO P20_PDIO 0x240 read-write n 0x0 0x0 P21_PDIO P21_PDIO 0x244 read-write n 0x0 0x0 P22_PDIO P22_PDIO 0x248 read-write n 0x0 0x0 P23_PDIO P23_PDIO 0x24C read-write n 0x0 0x0 P24_PDIO P24_PDIO 0x250 read-write n 0x0 0x0 P25_PDIO P25_PDIO 0x254 read-write n 0x0 0x0 P26_PDIO P26_PDIO 0x258 read-write n 0x0 0x0 P27_PDIO P27_PDIO 0x25C read-write n 0x0 0x0 P2_DBEN P2_DBEN 0x94 read-write n 0x0 0x0 P2_DMASK P2_DMASK 0x8C read-write n 0x0 0x0 P2_DOUT P2_DOUT 0x88 read-write n 0x0 0x0 P2_IEN P2_IEN 0x9C read-write n 0x0 0x0 P2_IMD P2_IMD 0x98 read-write n 0x0 0x0 P2_ISRC P2_ISRC 0xA0 read-write n 0x0 0x0 P2_OFFD P2_OFFD 0x84 read-write n 0x0 0x0 P2_PIN P2_PIN 0x90 read-write n 0x0 0x0 P2_PMD P2_PMD 0x80 read-write n 0x0 0x0 P30_PDIO P30_PDIO 0x260 read-write n 0x0 0x0 P31_PDIO P31_PDIO 0x264 read-write n 0x0 0x0 P32_PDIO P32_PDIO 0x268 read-write n 0x0 0x0 P33_PDIO P33_PDIO 0x26C read-write n 0x0 0x0 P34_PDIO P34_PDIO 0x270 read-write n 0x0 0x0 P35_PDIO P35_PDIO 0x274 read-write n 0x0 0x0 P36_PDIO P36_PDIO 0x278 read-write n 0x0 0x0 P37_PDIO P37_PDIO 0x27C read-write n 0x0 0x0 P3_DBEN P3_DBEN 0xD4 read-write n 0x0 0x0 P3_DMASK P3_DMASK 0xCC read-write n 0x0 0x0 P3_DOUT P3_DOUT 0xC8 read-write n 0x0 0x0 P3_IEN P3_IEN 0xDC read-write n 0x0 0x0 P3_IMD P3_IMD 0xD8 read-write n 0x0 0x0 P3_ISRC P3_ISRC 0xE0 read-write n 0x0 0x0 P3_OFFD P3_OFFD 0xC4 read-write n 0x0 0x0 P3_PIN P3_PIN 0xD0 read-write n 0x0 0x0 P3_PMD P3_PMD 0xC0 read-write n 0x0 0x0 P40_PDIO P40_PDIO 0x280 read-write n 0x0 0x0 P41_PDIO P41_PDIO 0x284 read-write n 0x0 0x0 P42_PDIO P42_PDIO 0x288 read-write n 0x0 0x0 P43_PDIO P43_PDIO 0x28C read-write n 0x0 0x0 P44_PDIO P44_PDIO 0x290 read-write n 0x0 0x0 P45_PDIO P45_PDIO 0x294 read-write n 0x0 0x0 P46_PDIO P46_PDIO 0x298 read-write n 0x0 0x0 P47_PDIO P47_PDIO 0x29C read-write n 0x0 0x0 P4_DBEN P4_DBEN 0x114 read-write n 0x0 0x0 P4_DMASK P4_DMASK 0x10C read-write n 0x0 0x0 P4_DOUT P4_DOUT 0x108 read-write n 0x0 0x0 P4_IEN P4_IEN 0x11C read-write n 0x0 0x0 P4_IMD P4_IMD 0x118 read-write n 0x0 0x0 P4_ISRC P4_ISRC 0x120 read-write n 0x0 0x0 P4_OFFD P4_OFFD 0x104 read-write n 0x0 0x0 P4_PIN P4_PIN 0x110 read-write n 0x0 0x0 P4_PMD P4_PMD 0x100 read-write n 0x0 0x0 HDIV HDIV Register Map HDIV 0x0 0x0 0x14 registers n DIVIDEND DIVIDEND Dividend Source Register 0x0 read-write n 0x0 0x0 DIVIDEND Dividend Source\nThis register is given the dividend of divider before calculation starting. 0 32 read-write DIVISOR DIVISOR Divisor Source Resister 0x4 -1 read-write n 0x0 0x0 DIVISOR Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate. 0 16 read-write DIVQUO DIVQUO Quotient Result Resister 0x8 read-write n 0x0 0x0 QUOTIENT Quotient Result\nThis register holds the quotient result of divider after calculation complete. 0 32 read-write DIVREM DIVREM Remainder Result Register 0xC read-write n 0x0 0x0 REMAINDER15_0 Remainder Result\nThis register holds the remainder result of divider after calculation complete. 0 16 read-write REMAINDER31_16 Sign Extension of REMAINDER[15:0]\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer. 16 16 read-write DIVSTS DIVSTS Divider Status Register 0x10 -1 read-only n 0x0 0x0 DIV0 Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only. 1 1 read-only 0 The divisor is not 0 #0 1 The divisor is 0 #1 I2C0 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function Enable Control\n 0 1 read-write 0 General Call function Disabled #0 1 General Call Function Enabled #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched. 1 7 read-write I2CADDR1 I2CADDR1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADM I2C Address Mask\n 1 7 read-write 0 I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register) 0 1 I2C address mask Enabled (the received corresponding address bit is Don't care ) 1 I2CADM1 I2CADM1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divided \nNote: The minimum value of I2CLK is 4. 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write EI I2C Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 ENS1 I2C Controller Enable Control \n 6 1 read-write 0 I2C Controller Disabled #0 1 I2C Controller Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to it. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 I2CSTATUS I2C Status\n 0 8 read-only I2CTOC I2CTOC I2C Time-out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-out Counter Input Clock Divided by 4 \nNote: When Enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out counter input clock divided by 4 Disabled #0 1 Time-out counter input clock divided by 4 Enabled #1 ENTI Time-out Counter Enable Control\nNote: When the 14 bit Time-out counter is enabled, it will start counting when SI is cleared. Writing 1 to the Si flag will reset the counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKUPEN I2C Wakeup Function Enable Control\n 0 1 read-write 0 I2C wake up function Disabled #0 1 I2C wake up function Enabled #1 I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKUPIF I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write I2C1 I2C Register Map I2C 0x0 0x0 0x30 registers n 0x3C 0x8 registers n I2CADDR0 I2CADDR0 I2C Slave Address Register0 0x4 read-write n 0x0 0x0 GC General Call Function Enable Control\n 0 1 read-write 0 General Call function Disabled #0 1 General Call Function Enabled #1 I2CADDR I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched. 1 7 read-write I2CADDR1 I2CADDR1 0x18 read-write n 0x0 0x0 I2CADDR2 I2CADDR2 0x1C read-write n 0x0 0x0 I2CADDR3 I2CADDR3 0x20 read-write n 0x0 0x0 I2CADM0 I2CADM0 I2C Slave Address Mask Register0 0x24 read-write n 0x0 0x0 I2CADM I2C Address Mask\n 1 7 read-write 0 I2C address mask Disabled (the received corresponding register bit should be exactly the same as address register) 0 1 I2C address mask Enabled (the received corresponding address bit is Don't care ) 1 I2CADM1 I2CADM1 0x28 read-write n 0x0 0x0 I2CADM2 I2CADM2 0x2C read-write n 0x0 0x0 I2CADM3 I2CADM3 0x30 read-write n 0x0 0x0 I2CDAT I2CDAT I2C Data Register 0x8 read-write n 0x0 0x0 I2CDAT I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port. 0 8 read-write I2CLK I2CLK I2C Clock Divided Register 0x10 read-write n 0x0 0x0 I2CLK I2C Clock Divided \nNote: The minimum value of I2CLK is 4. 0 8 read-write I2CON I2CON I2C Control Register 0x0 read-write n 0x0 0x0 AA Assert Acknowledge Control\n 2 1 read-write EI I2C Interrupt Enable Control\n 7 1 read-write 0 I2C interrupt Disabled #0 1 I2C interrupt Enabled #1 ENS1 I2C Controller Enable Control \n 6 1 read-write 0 I2C Controller Disabled #0 1 I2C Controller Enabled #1 SI I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to it. 3 1 read-write STA I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 5 1 read-write STO I2C STOP Control In master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device. 4 1 read-write I2CSTATUS I2CSTATUS I2C Status Register 0xC -1 read-only n 0x0 0x0 I2CSTATUS I2C Status\n 0 8 read-only I2CTOC I2CTOC I2C Time-out Counter Register 0x14 read-write n 0x0 0x0 DIV4 Time-out Counter Input Clock Divided by 4 \nNote: When Enabled, the time-out period is extended 4 times. 1 1 read-write 0 Time-out counter input clock divided by 4 Disabled #0 1 Time-out counter input clock divided by 4 Enabled #1 ENTI Time-out Counter Enable Control\nNote: When the 14 bit Time-out counter is enabled, it will start counting when SI is cleared. Writing 1 to the Si flag will reset the counter and re-start up counting after SI is cleared. 2 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 TIF Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit. 0 1 read-write I2CWKUPCON I2CWKUPCON I2C Wake-up Control Register 0x3C read-write n 0x0 0x0 WKUPEN I2C Wakeup Function Enable Control\n 0 1 read-write 0 I2C wake up function Disabled #0 1 I2C wake up function Enabled #1 I2CWKUPSTS I2CWKUPSTS I2C Wake-up Status Register 0x40 read-write n 0x0 0x0 WKUPIF I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit. 0 1 read-write INT INT Register Map INT 0x0 0x0 0x84 registers n IRQ0_SRC IRQ0_SRC IRQ0 (BOD) Interrupt Source Identity 0x0 read-only n 0x0 0x0 INT_SRC IRQ0 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ0 source is not from BOD interrupt (BOD_INT) 0 1 IRQ0 source is from BOD interrupt (BOD_INT) 1 IRQ10_SRC IRQ10_SRC IRQ10 (TMR2) Interrupt Source Identity 0x28 read-only n 0x0 0x0 INT_SRC IRQ10 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ10 source is not from Timer2 interrupt (TMR2_INT) 0 1 IRQ10 source is from Timer2 interrupt (TMR2_INT) 1 IRQ11_SRC IRQ11_SRC IRQ11 (TMR3) Interrupt Source Identity 0x2C read-only n 0x0 0x0 INT_SRC IRQ11 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ11 source is not from Timer3 interrupt (TMR3_INT) 0 1 IRQ11 source is from Timer3 interrupt (TMR3_INT) 1 IRQ12_SRC IRQ12_SRC IRQ12 (UART0) Interrupt Source Identity 0x30 read-only n 0x0 0x0 INT_SRC IRQ12 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ12 source is not from UART0 interrupt (UART0_INT) 0 1 IRQ12 source is from UART0 interrupt (UART0_INT) 1 IRQ13_SRC IRQ13_SRC IRQ13 (UART1) Interrupt Source Identity 0x34 read-only n 0x0 0x0 INT_SRC IRQ13 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ13 source is not from UART1 interrupt (UART1_INT) 0 1 IRQ13 source is from UART1 interrupt (UART1_INT) 1 IRQ14_SRC IRQ14_SRC IRQ14 (SPI0) Interrupt Source Identity 0x38 read-only n 0x0 0x0 INT_SRC IRQ14 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ14 source is not from SPI0 interrupt (SPI0_INT) 0 1 IRQ14 source is from SPI0 interrupt (SPI0_INT) 1 IRQ15_SRC IRQ15_SRC IRQ15 (SPI1) Interrupt Source Identity 0x3C read-only n 0x0 0x0 INT_SRC IRQ15 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ15 source is not from SPI1 interrupt (SPI1_INT) 0 1 IRQ15 source is from SPI1 interrupt (SPI1_INT) 1 IRQ16_SRC IRQ16_SRC Reserved. 0x40 read-only n 0x0 0x0 IRQ17_SRC IRQ17_SRC Reserved. 0x44 read-only n 0x0 0x0 IRQ18_SRC IRQ18_SRC IRQ18 (I2C0) Interrupt Source Identity 0x48 read-only n 0x0 0x0 INT_SRC IRQ18 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ18 source is not from I2C0 interrupt (I2C0_INT) 0 1 IRQ18 source is from I2C0 interrupt (I2C0_INT) 1 IRQ19_SRC IRQ19_SRC IRQ19 (I2C1) Interrupt Source Identity 0x4C read-only n 0x0 0x0 INT_SRC IRQ19 Source Identity \nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ19 source is not from I2C1 interrupt (I2C1_INT) 0 1 IRQ19 source is from I2C1 interrupt (I2C1_INT) 1 IRQ1_SRC IRQ1_SRC IRQ1 (WDT) Interrupt Source Identity 0x4 read-only n 0x0 0x0 INT_SRC IRQ1 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ1 source is not from watchdog interrupt (WDT _INT) 0 1 IRQ1 source is from watchdog interrupt (WDT_INT) 1 IRQ20_SRC IRQ20_SRC Reserved. 0x50 read-only n 0x0 0x0 IRQ21_SRC IRQ21_SRC Reserved. 0x54 read-only n 0x0 0x0 IRQ22_SRC IRQ22_SRC Reserved. 0x58 read-only n 0x0 0x0 IRQ23_SRC IRQ23_SRC Reserved. 0x5C read-only n 0x0 0x0 IRQ24_SRC IRQ24_SRC Reserved. 0x60 read-only n 0x0 0x0 IRQ25_SRC IRQ25_SRC IRQ25 (ACMP01) Interrupt Source Identity 0x64 read-only n 0x0 0x0 INT_SRC IRQ25 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ25 source is not from ACMP01 interrupt (ACMP01_INT) 0 1 IRQ25 source is from ACMP01 interrupt (ACMP01_INT) 1 IRQ26_SRC IRQ26_SRC IRQ26 (ACMP23) Interrupt Source Identity 0x68 read-only n 0x0 0x0 INT_SRC IRQ26 Source Identity \nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ26 source is not from ACMP23 interrupt (ACMP23_INT) 0 1 IRQ26 source is from ACMP23 interrupt (ACMP23_INT) 1 IRQ27_SRC IRQ27_SRC Reserved. 0x6C read-only n 0x0 0x0 IRQ28_SRC IRQ28_SRC IRQ28 (PWRWU) Interrupt Source Identity 0x70 read-only n 0x0 0x0 INT_SRC IRQ28 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ28 source is not from Power-down mode Wake-up interrupt (PWRWU_INT) 0 1 IRQ28 source is from Power-down mode Wake-up interrupt interrupt (PWRWU_INT) 1 IRQ29_SRC IRQ29_SRC IRQ29 (ADC) Interrupt Source Identity 0x74 read-only n 0x0 0x0 INT_SRC IRQ29 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ29 source is not from ADC interrupt (ADC_INT) 0 1 IRQ29 source is from ADC interrupt (ADC_INT) 1 IRQ2_SRC IRQ2_SRC IRQ2 (EINT0) Interrupt Source Identity 0x8 read-only n 0x0 0x0 INT_SRC IRQ2 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ2 source is not from external signal interrupt 0 - P3.2 (EINT0) 0 1 IRQ2 source is from external signal interrupt 0 - P3.2 (EINT0) 1 IRQ30_SRC IRQ30_SRC Reserved. 0x78 read-only n 0x0 0x0 IRQ31_SRC IRQ31_SRC Reserved. 0x7C read-only n 0x0 0x0 IRQ3_SRC IRQ3_SRC IRQ3 (EINT1) Interrupt Source Identity 0xC read-only n 0x0 0x0 INT_SRC IRQ3 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ3 source is not from external signal interrupt 1 - P3.3 (EINT1) 0 1 IRQ3 source is from external signal interrupt 1 - P3.3 (EINT1) 1 IRQ4_SRC IRQ4_SRC IRQ4 (P0/1) Interrupt Source Identity 0x10 read-only n 0x0 0x0 INT_SRC IRQ4 Source Identity\nNote1: IRQ4 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ4 source is not from P1 interrupt (P1_INT).\nIRQ4 source is not from P0 interrupt (P0_INT) 0 1 IRQ4 source is from P1 interrupt (P1_INT).\nIRQ4 source is from P0 interrupt (P0_INT) 1 IRQ5_SRC IRQ5_SRC IRQ5 (P2/3/4) Interrupt Source Identity 0x14 read-only n 0x0 0x0 INT_SRC IRQ5 Source Identity\nINT_SRC[2]:\nNote1: IRQ5 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ5 source is not from P4 interrupt (P4_INT).\nIRQ5 source is not from P3 interrupt (P3_INT).\nIRQ5 source is not from P2 interrupt (P2_INT) 0 1 IRQ5 source is from P4 interrupt (P4_INT).\nIRQ5 source is from P3 interrupt (P3_INT).\nIRQ5 source is from P2 interrupt (P2_INT) 1 IRQ6_SRC IRQ6_SRC IRQ6 (PWMA) Interrupt Source Identity 0x18 read-only n 0x0 0x0 INT_SRC IRQ6 Source Identity\nINT_SRC[3]:\nNote1: IRQ6 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 4 read-only 0 IRQ6 source is not from PWM3(PWMA channel 3) interrupt (PWM3_INT).\nIRQ6 source is not from PWM2(PWMA channel 2) interrupt (PWM2_INT).\nIRQ6 source is not from PWM1(PWMA channel 1) interrupt (PWM1_INT).\nIRQ6 source is not from PWM0(PWMA channel 0) interrupt (PWM0_INT) 0 1 IRQ6 source is from PWM3(PWMA channel 3) interrupt (PWM3_INT).\nIRQ6 source is from PWM2(PWMA channel 2) interrupt (PWM2_INT).\nIRQ6 source is from PWM1(PWMA channel 1) interrupt (PWM1_INT).\nIRQ6 source is from PWM0(PWMA channel 0) interrupt (PWM0_INT) 1 IRQ7_SRC IRQ7_SRC IRQ7 (PWMB) Interrupt Source Identity 0x1C read-only n 0x0 0x0 INT_SRC IRQ7 Source Identity\nINT_SRC[3]:\nNote1: IRQ7 source can be from multiple interrupt sources at the same time.\nNote2: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 4 read-only 0 IRQ7 source is not from PWM7(PWMB channel 3) interrupt (PWM7_INT).\nIRQ7 source is not from PWM6(PWMB channel 2) interrupt (PWM6_INT).\nIRQ7 source is not from PWM5(PWMB channel 1) interrupt (PWM5_INT).\nIRQ7 source is not from PWM4(PWMB channel 0) interrupt (PWM4_INT) 0 1 IRQ7 source is from PWM7(PWMB channel 3) interrupt (PWM7_INT).\nIRQ7 source is from PWM6(PWMB channel 2) interrupt (PWM6_INT).\nIRQ7 source is from PWM5(PWMB channel 1) interrupt (PWM5_INT).\nIRQ7 source is from PWM4(PWMB channel 0) interrupt (PWM4_INT) 1 IRQ8_SRC IRQ8_SRC IRQ8 (TMR0) Interrupt Source Identity 0x20 read-only n 0x0 0x0 INT_SRC IRQ8 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ8 source is not from Timer0 interrupt (TMR0_INT) 0 1 IRQ8 source is from Timer0 interrupt (TMR0_INT) 1 IRQ9_SRC IRQ9_SRC IRQ9 (TMR1) Interrupt Source Identity 0x24 read-only n 0x0 0x0 INT_SRC IRQ9 Source Identity\nNote: When the interrupt flag is cleared, the corresponding bits will be cleared automatically. 0 3 read-only 0 IRQ9 source is not from Timer1 interrupt (TMR1_INT) 0 1 IRQ9 source is from Timer1 interrupt (TMR1_INT) 1 NMI_SEL NMI_SEL NMI Source Interrupt Select Control Register 0x80 read-write n 0x0 0x0 NMI_EN NMI Interrupt Enable Control (Write Protect) Note: This bit is the protected bit and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100 8 1 read-write 0 NMI interrupt Disabled #0 1 NMI interrupt Enabled #1 NMI_SEL NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL. 0 5 read-write NVIC NVIC Register Map NVIC 0x0 0x0 0x4 registers n 0x100 0x4 registers n 0x180 0x4 registers n 0x300 0x20 registers n 0x80 0x4 registers n ICER NVIC_ICER IRQ0 ~ IRQ31 Clear-Enable Control Register 0x80 read-write n 0x0 0x0 CLRENA Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled 1 ICPR NVIC_ICPR IRQ0 ~ IRQ31 Clear-Pending Control Register 0x180 read-write n 0x0 0x0 CLRPEND Clear Interrupt Pending register\nWrite:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 IPR0 NVIC_IPR0 IRQ0 ~ IRQ3 Interrupt Priority Control Register 0x300 read-write n 0x0 0x0 PRI_0 Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_1 Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_2 Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_3 Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR1 NVIC_IPR1 IRQ4 ~ IRQ7 Interrupt Priority Control Register 0x304 read-write n 0x0 0x0 PRI_4 Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_5 Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_6 Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_7 Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR2 NVIC_IPR2 IRQ8 ~ IRQ11 Interrupt Priority Control Register 0x308 read-write n 0x0 0x0 PRI_10 Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_11 Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write PRI_8 Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_9 Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write IPR3 NVIC_IPR3 IRQ12 ~ IRQ15 Interrupt Priority Control Register 0x30C read-write n 0x0 0x0 PRI_12 Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_13 Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_14 Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_15 Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR4 NVIC_IPR4 IRQ16 ~ IRQ19 Interrupt Priority Control Register 0x310 read-write n 0x0 0x0 PRI_16 Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_17 Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_18 Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_19 Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR5 NVIC_IPR5 IRQ20 ~ IRQ23 Interrupt Priority Control Register 0x314 read-write n 0x0 0x0 PRI_20 Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_21 Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_22 Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_23 Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR6 NVIC_IPR6 IRQ24 ~ IRQ27 Interrupt Priority Control Register 0x318 read-write n 0x0 0x0 PRI_24 Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_25 Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_26 Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_27 Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write IPR7 NVIC_IPR7 IRQ28 ~ IRQ31 Interrupt Priority Control Register 0x31C read-write n 0x0 0x0 PRI_28 Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority. 6 2 read-write PRI_29 Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority. 14 2 read-write PRI_30 Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority. 22 2 read-write PRI_31 Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority. 30 2 read-write ISER NVIC_ISER IRQ0 ~ IRQ31 Set-Enable Control Register 0x0 read-write n 0x0 0x0 SETENA Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status. 0 32 read-write 0 No effect.\nAssociated interrupt status is Disabled 0 1 Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled 1 ISPR NVIC_ISPR IRQ0 ~ IRQ31 Set-Pending Control Register 0x100 read-write n 0x0 0x0 SETPEND Set Interrupt Pending register\nWrite:\nRead value indicates the current pending status. 0 32 read-write 0 No effect.\nAssociated interrupt in not in pending status 0 1 Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status 1 PWMA PWM Register Map PWM 0x0 0x0 0x3C registers n 0x40 0x8 registers n 0x50 0x38 registers n 0x98 0x4 registers n CAPENR CAPENR PWM Capture Input 0~3 Enable Register 0x78 read-write n 0x0 0x0 CAPENR Capture Input Enable Register CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.0 or P4.0. User can only select one of pins by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.1 or P4.1. User can only select one of pins by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.2 or P4.2. User can only select one of pins by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.3 or P4.3. User can only select one of pins by setting multi-function pin register. Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.4 by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.5 by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.6 by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.7 by setting multi-function pin register. 0 4 read-write 0 Capture input Disabled. (PWMx multi-function pin input does not affect input capture function.) 0 1 Capture input Enabled. (PWMx multi-function pin input will affect its input capture function.) 1 CCR0 CCR0 PWM Capture Control Register 0 0x50 read-write n 0x0 0x0 CAPCH0EN Channel 0 Capture Function Enable Control\nNote1: When Enabled, Capture latches the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 read-write 0 Capture function on PWM group channel 0 Disabled #0 1 Capture function on PWM group channel 0 Enabled #1 CAPCH1EN Channel 1 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 read-write 0 Capture function on PWM group channel 1 Disabled #0 1 Capture function on PWM group channel 1 Enabled #1 CAPIF0 Channel 0 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write CAPIF1 Channel 1 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 20 1 read-write CFLRI0 CFLR0 Latched Indicator Control\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 7 1 read-write CFLRI1 CFLR1 Latched Indicator\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 23 1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has falling transition, and Capture will issue an Interrupt. 2 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt. 18 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRLRI0 CRLR0 Latched Indicator When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Note: Write 1 to clear this bit to 0. 6 1 read-write CRLRI1 CRLR1 Latched Indicator \nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 22 1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt. 1 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt. 17 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 INV0 Capture Channel 0 Inverter Enable Control\n 0 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 Capture Channel 1 Inverter Enable Control\n 16 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 CCR2 CCR2 PWM Capture Control Register 2 0x54 read-write n 0x0 0x0 CAPCH2EN Channel 2 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 read-write 0 Capture function on PWM group channel 2 Disabled #0 1 Capture function on PWM group channel 2 Enabled #1 CAPCH3EN Channel 3 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 read-write 0 Capture function on PWM group channel 3 Disabled #0 1 Capture function on PWM group channel 3 Enabled #1 CAPIF2 Channel 2 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write CAPIF3 Channel 3 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 20 1 read-write CFLRI2 CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 7 1 read-write CFLRI3 CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 23 1 read-write CFL_IE2 Channel 2 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt. 2 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE3 Channel 3 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt. 18 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRLRI2 CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 6 1 read-write CRLRI3 CRLR3 Latched Indicator \nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 22 1 read-write CRL_IE2 Channel 2 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt. 1 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE3 Channel 3 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt. 17 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 INV2 Capture Channel 2 Inverter Enable Control\n 0 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 Capture Channel 3 Inverter Enable Control\n 16 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 CFLR0 CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLRx Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition. 0 16 read-only CFLR1 CFLR1 0x64 read-write n 0x0 0x0 CFLR2 CFLR2 0x6C read-write n 0x0 0x0 CFLR3 CFLR3 0x74 read-write n 0x0 0x0 CMR0 CMR0 PWM Comparator Register 0 0x10 read-write n 0x0 0x0 CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 CMR1 0x1C read-write n 0x0 0x0 CMR2 CMR2 0x28 read-write n 0x0 0x0 CMR3 CMR3 0x34 read-write n 0x0 0x0 CNR0 CNR0 PWM Counter Register 0 0xC read-write n 0x0 0x0 CNRx PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0, PWM output is always high.\nNote3: When PWM operating at center-aligned type, CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF, the PWM will work unpredictable. 0 16 read-write CNR1 CNR1 0x18 read-write n 0x0 0x0 CNR2 CNR2 0x24 read-write n 0x0 0x0 CNR3 CNR3 0x30 read-write n 0x0 0x0 CRLR0 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLRx Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition. 0 16 read-only CRLR1 CRLR1 0x60 read-write n 0x0 0x0 CRLR2 CRLR2 0x68 read-write n 0x0 0x0 CRLR3 CRLR3 0x70 read-write n 0x0 0x0 CSR CSR PWM Clock Source Divider Select Register 0x4 read-write n 0x0 0x0 CSR0 PWM Timer 0 Clock Source Divider Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3) 0 3 read-write CSR1 PWM Timer 1 Clock Source Divider Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3) 4 3 read-write CSR2 PWM Timer 2 Clock Source Divider Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3) 8 3 read-write CSR3 PWM Timer 3 Clock Source Divider Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n 12 3 read-write PCR PCR PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n 0 1 read-write 0 The corresponding PWM-Timer stops running #0 1 The corresponding PWM-Timer starts running #1 CH0INV PWM-Timer 0 Output Inverter Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n 2 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared. 3 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH0PINV PWM-Timer 0 Output Polar Inverse Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B) \n 1 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH1EN PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n 8 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH1INV PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n 10 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared. 11 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH1PINV PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) \n 9 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH2EN PWM-Timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n 16 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH2INV PWM-Timer 2 Output Inverter Enable Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n 18 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared. 19 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH2PINV PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B) \n 17 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH3EN PWM-Timer 3 Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n 24 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH3INV PWM-Timer 3 Output Inverter Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n 26 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared. 27 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH3PINV PWM-Timer 3 Output Polar Inverse Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B) \n 25 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 DZEN01 Dead-zone 0 Generator Enable Control (PWM0 and PWM1 pair for PWM Group A, PWM4 and PWM5 pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B. 4 1 read-write 0 Disabled #0 1 Enabled #1 DZEN23 Dead-zone 2 Generator Enable (PWM2 and PWM3 pair for PWM Group A, PWM6 and PWM7 pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. 5 1 read-write 0 Disabled #0 1 Enabled #1 PWM01TYPE PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \n 30 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PWM23TYPE PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \n 31 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PDR0 PDR0 PWM Data Register 0 0x14 read-only n 0x0 0x0 PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter. 0 16 read-only PDR1 PDR1 0x20 read-write n 0x0 0x0 PDR2 PDR2 0x2C read-write n 0x0 0x0 PDR3 PDR3 0x38 read-write n 0x0 0x0 PIER PIER PWM Interrupt Enable Register 0x40 read-write n 0x0 0x0 INT01DTYPE PWM01 Duty Interrupt Type Selection (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type. 24 1 read-write 0 PWMDIFx will be set if PWM counter down count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #0 1 PWMDIFx will be set when PWM counter up count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #1 INT01TYPE PWM01 Interrupt Period Type Selection (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \nNote: Setting INT01TYPE to 1 only works when PWM operating is in center-aligned type. 16 1 read-write 0 PWMIFx will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #0 1 PWMIFx will be set if PWM counter matches CNRx register. PWM will trigger ADC to conversion when PWM counter matches CNRx register if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #1 INT23DTYPE PWM23 Duty Interrupt Type Selection (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type. 25 1 read-write 0 PWMDIFx will be set if PWM counter down count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #0 1 PWMDIFx will be set when PWM counter up count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #1 INT23TYPE PWM23 Interrupt Period Type Selection (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \nNote: Setting INT23TYPE to 1 only works when PWM operating is in center-aligned type. 17 1 read-write 0 PWMIFx will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #0 1 PWMIFx will be set if PWM counter matches CNRx register. PWM will trigger ADC to conversion when PWM counter matches CNRx register if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #1 PWMDIE0 PWM channel 0 Duty Interrupt Enable Control \n 8 1 read-write 0 PWM channel 0 duty interrupt Disabled #0 1 PWM channel 0 duty interrupt Enabled #1 PWMDIE1 PWM channel 1 Duty Interrupt Enable Control \n 9 1 read-write 0 PWM channel 1 duty interrupt Disabled #0 1 PWM channel 1 duty interrupt Enabled #1 PWMDIE2 PWM channel 2 Duty Interrupt Enable Control \n 10 1 read-write 0 PWM channel 2 duty interrupt Disabled #0 1 PWM channel 2 duty interrupt Enabled #1 PWMDIE3 PWM channel 3 Duty Interrupt Enable Control \n 11 1 read-write 0 PWM channel 3 duty interrupt Disabled #0 1 PWM channel 3 duty interrupt Enabled #1 PWMIE0 PWM channel 0 Period Interrupt Enable Control\n 0 1 read-write 0 PWM channel 0 period interrupt Disabled #0 1 PWM channel 0 period interrupt Enabled #1 PWMIE1 PWM channel 1 Period Interrupt Enable Control\n 1 1 read-write 0 PWM channel 1 period interrupt Disabled #0 1 PWM channel 1 period interrupt Enabled #1 PWMIE2 PWM channel 2 Period Interrupt Enable Control\n 2 1 read-write 0 PWM channel 2 period interrupt Disabled #0 1 PWM channel 2 period interrupt Enabled #1 PWMIE3 PWM channel 3 Period Interrupt Enable Control\n 3 1 read-write 0 PWM channel 3 period interrupt Disabled #0 1 PWM channel 3 period interrupt Enabled #1 PIIR PIIR PWM Interrupt Indication Register 0x44 read-write n 0x0 0x0 PWMDIF0 PWM Channel 0 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 8 1 read-write PWMDIF1 PWM Channel 1 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 9 1 read-write PWMDIF2 PWM channel 2 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 10 1 read-write PWMDIF3 PWM Channel 3 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 11 1 read-write PWMIF0 PWM Channel 0 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 0 1 read-write PWMIF1 PWM channel 1 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 1 1 read-write PWMIF2 PWM Channel 2 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 2 1 read-write PWMIF3 PWM Channel 3 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 3 1 read-write POE POE PWM Output Enable Register for Channel 0~3 0x7C read-write n 0x0 0x0 PWM0 Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 0 1 read-write 0 PWM channel 0 output to pin Disabled #0 1 PWM channel 0 output to pin Enabled #1 PWM1 Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 1 1 read-write 0 PWM channel 1 output to pin Disabled #0 1 PWM channel 1 output to pin Enabled #1 PWM2 Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 2 1 read-write 0 PWM channel 2 output to pin Disabled #0 1 PWM channel 2 output to pin Enabled #1 PWM3 Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 3 1 read-write 0 PWM channel 3 output to pin Disabled #0 1 PWM channel 3 output to pin Enabled #1 PPR PPR PWM Prescaler Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler 0 (PWM-Timer 0 / 1 for group A and PWM-Timer 4 / 5 for group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-Timer\n 0 8 read-write CP23 Clock Prescaler 2 (PWM-Timer 2 / 3 for group A and PWM-Timer 6 / 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-Timer.\n 8 8 read-write DZI01 Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8-bit determine the Dead-zone length.\n 16 8 read-write DZI23 Dead-zone Interval for Pair of Channel 2 and Channel 3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8-bit determine the Dead-zone length.\n 24 8 read-write PSCR PSCR PWM Synchronous Control Register 0x98 read-write n 0x0 0x0 PSSEN0 Channel 0 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 0 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 0 1 read-write 0 Channel 0 PWM-Timer Synchronous Start Disabled #0 1 Channel 0 PWM-Timer Synchronous Start Enabled #1 PSSEN1 Channel 1 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 1 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 8 1 read-write 0 Channel 1 PWM-Timer Synchronous Start Disabled #0 1 Channel 1 PWM-Timer Synchronous Start Enabled #1 PSSEN2 Channel 2 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 2 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 16 1 read-write 0 Channel 2 PWM-Timer Synchronous Start Disabled #0 1 Channel 2 PWM-Timer Synchronous Start Enabled #1 PSSEN3 Channel 3 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 3 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 24 1 read-write 0 Channel 3 PWM-Timer Synchronous Start Disabled #0 1 Channel 3 PWM-Timer Synchronous Start Enabled #1 TCON TCON PWM Trigger Control Register for Channel 0~3 0x80 read-write n 0x0 0x0 PWM0DTEN Channel 0 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to match CMR0.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count or down count to match CMR0 based on INT01DTYPE setting. 8 1 read-write 0 PWM channel 0 duty trigger ADC function Disabled #0 1 PWM channel 0 duty trigger ADC function Enabled #1 PWM0TEN Channel 0 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count to (CNR0 + 1) or down count to underflow based on INT01PTYPE setting. 0 1 read-write 0 PWM channel 0 period trigger ADC function Disabled #0 1 PWM channel 0 period trigger ADC function Enabled #1 PWM1DTEN Channel 1 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to match CMR1.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count or down count to match CMR1 based on INT01DTYPE setting. 9 1 read-write 0 PWM channel 1 duty trigger ADC function Disabled #0 1 PWM channel 1 duty trigger ADC function Enabled #1 PWM1TEN Channel 1 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count to (CNR1 + 1) or down count to underflow based on INT01PTYPE setting. 1 1 read-write 0 PWM channel 1 period trigger ADC function Disabled #0 1 PWM channel 1 period trigger ADC function Enabled #1 PWM2DTEN Channel 2 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to match CMR2.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count or down count to match CMR2 based on INT23DTYPE setting. 10 1 read-write 0 PWM channel 2 duty trigger ADC function Disabled #0 1 PWM channel 2 duty trigger ADC function Enabled #1 PWM2TEN Channel 2 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count to (CNR2 + 1) or down count to underflow based on INT23PTYPE setting. 2 1 read-write 0 PWM channel 2 period trigger ADC function Disabled #0 1 PWM channel 2 period trigger ADC function Enabled #1 PWM3DTEN Channel 3 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to match CMR3.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count or down count to match CMR3 based on INT23DTYPE setting. 11 1 read-write 0 PWM channel 3 duty trigger ADC function Disabled #0 1 PWM channel 3 duty trigger ADC function Enabled #1 PWM3TEN Channel 3 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count to (CNR3 + 1) or down count to underflow based on INT23PTYPE setting. 3 1 read-write 0 PWM channel 3 period trigger ADC function Disabled #0 1 PWM channel 3 period trigger ADC function Enabled #1 TSTATUS TSTATUS PWM Trigger Status Register 0x84 read-write n 0x0 0x0 PWM0TF Channel 0 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 0 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write PWM1TF Channel 1 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 1 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write PWM2TF Channel 2 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 2 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 2 1 read-write PWM3TF Channel 3 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 3 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 3 1 read-write PWMB PWM Register Map PWM 0x0 0x0 0x3C registers n 0x40 0x8 registers n 0x50 0x38 registers n 0x98 0x4 registers n CAPENR CAPENR PWM Capture Input 0~3 Enable Register 0x78 read-write n 0x0 0x0 CAPENR Capture Input Enable Register CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.0 or P4.0. User can only select one of pins by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.1 or P4.1. User can only select one of pins by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.2 or P4.2. User can only select one of pins by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.3 or P4.3. User can only select one of pins by setting multi-function pin register. Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.4 by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.5 by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.6 by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.7 by setting multi-function pin register. 0 4 read-write 0 Capture input Disabled. (PWMx multi-function pin input does not affect input capture function.) 0 1 Capture input Enabled. (PWMx multi-function pin input will affect its input capture function.) 1 CCR0 CCR0 PWM Capture Control Register 0 0x50 read-write n 0x0 0x0 CAPCH0EN Channel 0 Capture Function Enable Control\nNote1: When Enabled, Capture latches the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt. 3 1 read-write 0 Capture function on PWM group channel 0 Disabled #0 1 Capture function on PWM group channel 0 Enabled #1 CAPCH1EN Channel 1 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt. 19 1 read-write 0 Capture function on PWM group channel 1 Disabled #0 1 Capture function on PWM group channel 1 Enabled #1 CAPIF0 Channel 0 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write CAPIF1 Channel 1 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 20 1 read-write CFLRI0 CFLR0 Latched Indicator Control\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 7 1 read-write CFLRI1 CFLR1 Latched Indicator\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 23 1 read-write CFL_IE0 Channel 0 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has falling transition, and Capture will issue an Interrupt. 2 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE1 Channel 1 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt. 18 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRLRI0 CRLR0 Latched Indicator When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Note: Write 1 to clear this bit to 0. 6 1 read-write CRLRI1 CRLR1 Latched Indicator \nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 22 1 read-write CRL_IE0 Channel 0 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt. 1 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE1 Channel 1 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt. 17 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 INV0 Capture Channel 0 Inverter Enable Control\n 0 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 INV1 Capture Channel 1 Inverter Enable Control\n 16 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 CCR2 CCR2 PWM Capture Control Register 2 0x54 read-write n 0x0 0x0 CAPCH2EN Channel 2 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt. 3 1 read-write 0 Capture function on PWM group channel 2 Disabled #0 1 Capture function on PWM group channel 2 Enabled #1 CAPCH3EN Channel 3 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt. 19 1 read-write 0 Capture function on PWM group channel 3 Disabled #0 1 Capture function on PWM group channel 3 Enabled #1 CAPIF2 Channel 2 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 4 1 read-write CAPIF3 Channel 3 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0. 20 1 read-write CFLRI2 CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 7 1 read-write CFLRI3 CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 23 1 read-write CFL_IE2 Channel 2 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt. 2 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CFL_IE3 Channel 3 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt. 18 1 read-write 0 Falling latch interrupt Disabled #0 1 Falling latch interrupt Enabled #1 CRLRI2 CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 6 1 read-write CRLRI3 CRLR3 Latched Indicator \nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0. 22 1 read-write CRL_IE2 Channel 2 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt. 1 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 CRL_IE3 Channel 3 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt. 17 1 read-write 0 Rising latch interrupt Disabled #0 1 Rising latch interrupt Enabled #1 INV2 Capture Channel 2 Inverter Enable Control\n 0 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 INV3 Capture Channel 3 Inverter Enable Control\n 16 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer #1 CFLR0 CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x5C read-only n 0x0 0x0 CFLRx Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition. 0 16 read-only CFLR1 CFLR1 0x64 read-write n 0x0 0x0 CFLR2 CFLR2 0x6C read-write n 0x0 0x0 CFLR3 CFLR3 0x74 read-write n 0x0 0x0 CMR0 CMR0 PWM Comparator Register 0 0x10 read-write n 0x0 0x0 CMRx PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle. 0 16 read-write CMR1 CMR1 0x1C read-write n 0x0 0x0 CMR2 CMR2 0x28 read-write n 0x0 0x0 CMR3 CMR3 0x34 read-write n 0x0 0x0 CNR0 CNR0 PWM Counter Register 0 0xC read-write n 0x0 0x0 CNRx PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0, PWM output is always high.\nNote3: When PWM operating at center-aligned type, CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF, the PWM will work unpredictable. 0 16 read-write CNR1 CNR1 0x18 read-write n 0x0 0x0 CNR2 CNR2 0x24 read-write n 0x0 0x0 CNR3 CNR3 0x30 read-write n 0x0 0x0 CRLR0 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x58 read-only n 0x0 0x0 CRLRx Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition. 0 16 read-only CRLR1 CRLR1 0x60 read-write n 0x0 0x0 CRLR2 CRLR2 0x68 read-write n 0x0 0x0 CRLR3 CRLR3 0x70 read-write n 0x0 0x0 CSR CSR PWM Clock Source Divider Select Register 0x4 read-write n 0x0 0x0 CSR0 PWM Timer 0 Clock Source Divider Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3) 0 3 read-write CSR1 PWM Timer 1 Clock Source Divider Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3) 4 3 read-write CSR2 PWM Timer 2 Clock Source Divider Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3) 8 3 read-write CSR3 PWM Timer 3 Clock Source Divider Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n 12 3 read-write PCR PCR PWM Control Register 0x8 read-write n 0x0 0x0 CH0EN PWM-Timer 0 Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n 0 1 read-write 0 The corresponding PWM-Timer stops running #0 1 The corresponding PWM-Timer starts running #1 CH0INV PWM-Timer 0 Output Inverter Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n 2 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH0MOD PWM-Timer 0 Auto-reload/One-Shot Mode Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared. 3 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH0PINV PWM-Timer 0 Output Polar Inverse Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B) \n 1 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH1EN PWM-Timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n 8 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH1INV PWM-Timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n 10 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH1MOD PWM-Timer 1 Auto-reload/One-Shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared. 11 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH1PINV PWM-Timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) \n 9 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH2EN PWM-Timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n 16 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH2INV PWM-Timer 2 Output Inverter Enable Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n 18 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH2MOD PWM-Timer 2 Auto-reload/One-Shot Mode Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared. 19 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH2PINV PWM-Timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B) \n 17 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 CH3EN PWM-Timer 3 Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n 24 1 read-write 0 Corresponding PWM-Timer Stopped #0 1 Corresponding PWM-Timer Start Running #1 CH3INV PWM-Timer 3 Output Inverter Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n 26 1 read-write 0 Inverter Disabled #0 1 Inverter Enabled #1 CH3MOD PWM-Timer 3 Auto-reload/One-Shot Mode Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared. 27 1 read-write 0 One-shot mode #0 1 Auto-reload mode #1 CH3PINV PWM-Timer 3 Output Polar Inverse Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B) \n 25 1 read-write 0 Polar Inverter Disabled #0 1 Polar Inverter Enabled #1 DZEN01 Dead-zone 0 Generator Enable Control (PWM0 and PWM1 pair for PWM Group A, PWM4 and PWM5 pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B. 4 1 read-write 0 Disabled #0 1 Enabled #1 DZEN23 Dead-zone 2 Generator Enable (PWM2 and PWM3 pair for PWM Group A, PWM6 and PWM7 pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B. 5 1 read-write 0 Disabled #0 1 Enabled #1 PWM01TYPE PWM01 Aligned Type Selection Bit (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \n 30 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PWM23TYPE PWM23 Aligned Type Selection Bit (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \n 31 1 read-write 0 Edge-aligned type #0 1 Center-aligned type #1 PDR0 PDR0 PWM Data Register 0 0x14 read-only n 0x0 0x0 PDRx PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter. 0 16 read-only PDR1 PDR1 0x20 read-write n 0x0 0x0 PDR2 PDR2 0x2C read-write n 0x0 0x0 PDR3 PDR3 0x38 read-write n 0x0 0x0 PIER PIER PWM Interrupt Enable Register 0x40 read-write n 0x0 0x0 INT01DTYPE PWM01 Duty Interrupt Type Selection (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type. 24 1 read-write 0 PWMDIFx will be set if PWM counter down count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #0 1 PWMDIFx will be set when PWM counter up count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #1 INT01TYPE PWM01 Interrupt Period Type Selection (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B) \nNote: Setting INT01TYPE to 1 only works when PWM operating is in center-aligned type. 16 1 read-write 0 PWMIFx will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #0 1 PWMIFx will be set if PWM counter matches CNRx register. PWM will trigger ADC to conversion when PWM counter matches CNRx register if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #1 INT23DTYPE PWM23 Duty Interrupt Type Selection (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type. 25 1 read-write 0 PWMDIFx will be set if PWM counter down count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter down count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #0 1 PWMDIFx will be set when PWM counter up count and matches CMRx register. PWM will trigger ADC to conversion when PWM counter up count and matches CMRx register if correlate PWM trigger enable bit (PWMxDTEN) is set to 1 #1 INT23TYPE PWM23 Interrupt Period Type Selection (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B) \nNote: Setting INT23TYPE to 1 only works when PWM operating is in center-aligned type. 17 1 read-write 0 PWMIFx will be set if PWM counter underflow. PWM will trigger ADC to conversion when PWM counter underflow if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #0 1 PWMIFx will be set if PWM counter matches CNRx register. PWM will trigger ADC to conversion when PWM counter matches CNRx register if correlate PWM trigger enable bit (PWMxTEN) is set to 1 #1 PWMDIE0 PWM channel 0 Duty Interrupt Enable Control \n 8 1 read-write 0 PWM channel 0 duty interrupt Disabled #0 1 PWM channel 0 duty interrupt Enabled #1 PWMDIE1 PWM channel 1 Duty Interrupt Enable Control \n 9 1 read-write 0 PWM channel 1 duty interrupt Disabled #0 1 PWM channel 1 duty interrupt Enabled #1 PWMDIE2 PWM channel 2 Duty Interrupt Enable Control \n 10 1 read-write 0 PWM channel 2 duty interrupt Disabled #0 1 PWM channel 2 duty interrupt Enabled #1 PWMDIE3 PWM channel 3 Duty Interrupt Enable Control \n 11 1 read-write 0 PWM channel 3 duty interrupt Disabled #0 1 PWM channel 3 duty interrupt Enabled #1 PWMIE0 PWM channel 0 Period Interrupt Enable Control\n 0 1 read-write 0 PWM channel 0 period interrupt Disabled #0 1 PWM channel 0 period interrupt Enabled #1 PWMIE1 PWM channel 1 Period Interrupt Enable Control\n 1 1 read-write 0 PWM channel 1 period interrupt Disabled #0 1 PWM channel 1 period interrupt Enabled #1 PWMIE2 PWM channel 2 Period Interrupt Enable Control\n 2 1 read-write 0 PWM channel 2 period interrupt Disabled #0 1 PWM channel 2 period interrupt Enabled #1 PWMIE3 PWM channel 3 Period Interrupt Enable Control\n 3 1 read-write 0 PWM channel 3 period interrupt Disabled #0 1 PWM channel 3 period interrupt Enabled #1 PIIR PIIR PWM Interrupt Indication Register 0x44 read-write n 0x0 0x0 PWMDIF0 PWM Channel 0 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 8 1 read-write PWMDIF1 PWM Channel 1 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 9 1 read-write PWMDIF2 PWM channel 2 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 10 1 read-write PWMDIF3 PWM Channel 3 Duty Interrupt Status \nNote: Write 1 to clear this bit to 0. 11 1 read-write PWMIF0 PWM Channel 0 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 0 1 read-write PWMIF1 PWM channel 1 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 1 1 read-write PWMIF2 PWM Channel 2 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 2 1 read-write PWMIF3 PWM Channel 3 Period Interrupt Status\nNote: Write 1 to clear this bit to 0. 3 1 read-write POE POE PWM Output Enable Register for Channel 0~3 0x7C read-write n 0x0 0x0 PWM0 Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 0 1 read-write 0 PWM channel 0 output to pin Disabled #0 1 PWM channel 0 output to pin Enabled #1 PWM1 Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 1 1 read-write 0 PWM channel 1 output to pin Disabled #0 1 PWM channel 1 output to pin Enabled #1 PWM2 Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 2 1 read-write 0 PWM channel 2 output to pin Disabled #0 1 PWM channel 2 output to pin Enabled #1 PWM3 Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function. 3 1 read-write 0 PWM channel 3 output to pin Disabled #0 1 PWM channel 3 output to pin Enabled #1 PPR PPR PWM Prescaler Register 0x0 read-write n 0x0 0x0 CP01 Clock Prescaler 0 (PWM-Timer 0 / 1 for group A and PWM-Timer 4 / 5 for group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-Timer\n 0 8 read-write CP23 Clock Prescaler 2 (PWM-Timer 2 / 3 for group A and PWM-Timer 6 / 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-Timer.\n 8 8 read-write DZI01 Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8-bit determine the Dead-zone length.\n 16 8 read-write DZI23 Dead-zone Interval for Pair of Channel 2 and Channel 3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8-bit determine the Dead-zone length.\n 24 8 read-write PSCR PSCR PWM Synchronous Control Register 0x98 read-write n 0x0 0x0 PSSEN0 Channel 0 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 0 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 0 1 read-write 0 Channel 0 PWM-Timer Synchronous Start Disabled #0 1 Channel 0 PWM-Timer Synchronous Start Enabled #1 PSSEN1 Channel 1 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 1 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 8 1 read-write 0 Channel 1 PWM-Timer Synchronous Start Disabled #0 1 Channel 1 PWM-Timer Synchronous Start Enabled #1 PSSEN2 Channel 2 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 2 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 16 1 read-write 0 Channel 2 PWM-Timer Synchronous Start Disabled #0 1 Channel 2 PWM-Timer Synchronous Start Enabled #1 PSSEN3 Channel 3 PWM-Timer Synchronous Start Enable Control \nIf this bit is set to 1, the PWM-Timer channel 3 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A. 24 1 read-write 0 Channel 3 PWM-Timer Synchronous Start Disabled #0 1 Channel 3 PWM-Timer Synchronous Start Enabled #1 TCON TCON PWM Trigger Control Register for Channel 0~3 0x80 read-write n 0x0 0x0 PWM0DTEN Channel 0 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to match CMR0.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count or down count to match CMR0 based on INT01DTYPE setting. 8 1 read-write 0 PWM channel 0 duty trigger ADC function Disabled #0 1 PWM channel 0 duty trigger ADC function Enabled #1 PWM0TEN Channel 0 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count to (CNR0 + 1) or down count to underflow based on INT01PTYPE setting. 0 1 read-write 0 PWM channel 0 period trigger ADC function Disabled #0 1 PWM channel 0 period trigger ADC function Enabled #1 PWM1DTEN Channel 1 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to match CMR1.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count or down count to match CMR1 based on INT01DTYPE setting. 9 1 read-write 0 PWM channel 1 duty trigger ADC function Disabled #0 1 PWM channel 1 duty trigger ADC function Enabled #1 PWM1TEN Channel 1 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count to (CNR1 + 1) or down count to underflow based on INT01PTYPE setting. 1 1 read-write 0 PWM channel 1 period trigger ADC function Disabled #0 1 PWM channel 1 period trigger ADC function Enabled #1 PWM2DTEN Channel 2 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to match CMR2.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count or down count to match CMR2 based on INT23DTYPE setting. 10 1 read-write 0 PWM channel 2 duty trigger ADC function Disabled #0 1 PWM channel 2 duty trigger ADC function Enabled #1 PWM2TEN Channel 2 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count to (CNR2 + 1) or down count to underflow based on INT23PTYPE setting. 2 1 read-write 0 PWM channel 2 period trigger ADC function Disabled #0 1 PWM channel 2 period trigger ADC function Enabled #1 PWM3DTEN Channel 3 PWM Duty Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to match CMR3.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count or down count to match CMR3 based on INT23DTYPE setting. 11 1 read-write 0 PWM channel 3 duty trigger ADC function Disabled #0 1 PWM channel 3 duty trigger ADC function Enabled #1 PWM3TEN Channel 3 PWM Period Trigger ADC Enable Control \nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count to (CNR3 + 1) or down count to underflow based on INT23PTYPE setting. 3 1 read-write 0 PWM channel 3 period trigger ADC function Disabled #0 1 PWM channel 3 period trigger ADC function Enabled #1 TSTATUS TSTATUS PWM Trigger Status Register 0x84 read-write n 0x0 0x0 PWM0TF Channel 0 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 0 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 0 1 read-write PWM1TF Channel 1 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 1 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 1 1 read-write PWM2TF Channel 2 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 2 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 2 1 read-write PWM3TF Channel 3 PWM Trigger ADC Flag \nThis bit is set to 1 by hardware when PWM channel 3 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0. 3 1 read-write SCB SCB Register Map SCB 0x0 0x0 0x8 registers n 0x1C 0x8 registers n 0xC 0x8 registers n AIRCR AIRCR Application Interrupt and Reset Control Register 0xC -1 read-write n 0x0 0x0 SYSRESETREQ System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence. 2 1 read-write VECTCLRACTIVE Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable. 1 1 read-write VECTORKEY Register Access Key\nWrite:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead:\nRead as 0xFA05. 16 16 read-write CPUID CPUID CPUID Register 0x0 -1 read-only n 0x0 0x0 IMPLEMENTER Implementer Code\n 24 8 read-only PART Architecture of the Processor\nRead as 0xC for ARMv6-M parts. 16 4 read-only PARTNO Part Number of the Processor\nRead as 0xC20. 4 12 read-only REVISION Revision Number\nRead as 0x0. 0 4 read-only ICSR ICSR Interrupt Control State Register 0x4 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag, excluding NMI and Faults (Read Only)\n 22 1 read-only 0 Interrupt not pending #0 1 Interrupt pending #1 ISRPREEMPT Interrupt Preempt Bit\nIf set, a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only. 23 1 read-write NMIPENDSET NMI Set-pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 1 read-write 0 No effect.\nNMI exception not pending #0 1 Changes NMI exception state to pending.\nNMI exception pending #1 PENDSTCLR SysTick Exception Clear-pending Bit Write: Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time. 25 1 read-write 0 No effect #0 1 Removes the pending state from the SysTick exception #1 PENDSTSET SysTick Exception Set-pending Bit\nWrite:\n 26 1 read-write 0 No effect.\nSysTick exception is not pending #0 1 Changes SysTick exception state to pending.\nSysTick exception is pending #1 PENDSVCLR PendSV Clear-pending Bit Write: This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time. 27 1 read-write 0 No effect #0 1 Removes the pending state from the PendSV exception #1 PENDSVSET PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending 28 1 read-write 0 No effect.\nPendSV exception is not pending #0 1 Changes PendSV exception state to pending.\nPendSV exception is pending #1 VECTACTIVE Contains the Active Exception Number\n 0 6 read-write 0 Thread mode 0 VECTPENDING Exception Number of the Highest Priority Pending Enabled Exception\n 12 6 read-write 0 No pending exceptions 0 SCR SCR System Control Register 0x10 read-write n 0x0 0x0 SEVONPEND Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event. 4 1 read-write 0 Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded #0 1 Enabled events and all interrupts, including disabled interrupts, can wake-up the processor #1 SLEEPDEEP Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n 2 1 read-write 0 Sleep mode #0 1 Deep Sleep mode #1 SLEEPONEXIT Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. 1 1 read-write 0 Do not sleep when returning to Thread mode #0 1 Enter Sleep or Deep Sleep when returning from ISR to Thread mode #1 SHPR2 SHPR2 System Handler Priority Register 2 0x1C read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes the lowest priority 30 2 read-write SHPR3 SHPR3 System Handler Priority Register 3 0x20 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes the lowest priority 22 2 read-write PRI_15 Priority of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes the lowest priority 30 2 read-write SPI0 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 FIFO FIFO Mode Enable Control \nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.\nNote 1: Before enabling FIFO mode, the other related settings should be set in advance.\nNote 2: On M05xxBN, this bit must be 0. 21 1 read-write 0 FIFO Mode Disabled #0 1 FIFO Mode Enabled #1 GO_BUSY SPI Transfer Trigger and Busy Status\nIn FIFO mode, this bit will be controlled by hardware. Software cannot modify this bit.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In M05xxDN/DE SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit-Transfer Interrupt Enable Control\n 17 1 read-write 0 SPI unit-transfer interrupt Disabled #0 1 SPI unit-transfer interrupt Enabled #1 IF Unit-Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB LSB First\n 10 1 read-write 0 The MSB is transmitted/received first #0 1 The LSB is transmitted/received first #1 REORDER Byte Reorder Function and Byte Suspend Function Selection\nNote: Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte reorder function and byte suspend function are Disabled #0 1 Byte reorder function Enabled. Byte suspend interval is determined by the setting of SP_CYCLE. Set SP_CYCLE to 0 to disabled byte suspend function #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_CNTRL[24]. \n 24 1 read-only 0 Indicates that the receive FIFO buffer is not empty #0 1 Indicates that the receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Indicates that the receive FIOF buffer is not full #0 1 Indicates that the receive FIFO buffer is full #1 RX_NEG Receive on Negative Edge\n 1 1 read-write 0 The received data input signal is latched on the rising edge of SPICLK #0 1 The received data input signal is latched on the falling edge of SPICLK #1 SLAVE Slave Mode Control\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.\nThe default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n 12 4 read-write TX_BIT_LEN Transfer Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[26]. \n 26 1 read-only 0 Indicates that the transmit FIFO buffer is not empty #0 1 Indicates that the transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[27]. \n 27 1 read-only 0 Indicates that the transmit FIFO buffer is not full #0 1 Indicates that the transmit FIFO buffer is full #1 TX_NEG Transmit on Negative Edge\n 2 1 read-write 0 The transmitted data output signal is driven on the rising edge of SPICLK #0 1 The transmitted data output signal is driven on the falling edge of SPICLK #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write n 0x0 0x0 BCn Clock Configuration Backward Compatible Option \nRefer to the description of SPI_DIVIDER register for details. 31 1 read-write 0 The clock configuration is backward compatible to M05xxBN #0 1 The clock configuration is not backward compatible to M05xxBN #1 NOSLVSEL Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI when this bit is set to 1.\nNote: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1. 8 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set to 1, the controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1 #1 SLV_ABORT Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN and TX_NUM. The TX_NUM setting is not available on M05xxDN/DE, and only the setting of TX_BIT_LEN will be considered.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SLV_START_INTSTS Slave 3-wire Mode Start Interrupt Status\nThis bit dedicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave does not detect any SPI bus clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0 #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nOnly DIVIDER[7:0] is available. The value in this field is the frequency divider to determine the SPI peripheral clock frequency, fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation.\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register. 0 16 read-write DIVIDER2 Clock Divider 2 (M05xxBN Master Mode Only)\nThe value in this field is the 2nd frequency divider for generating the bus clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Control\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared #1 RX_INTEN Receive Threshold Interrupt Enable Control\n 2 1 read-write 0 Receive threshold interrupt Disabled #0 1 Receive threshold interrupt Enabled #1 RX_THRESHOLD Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 2 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable Control\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared #1 TX_INTEN Transmit Threshold Interrupt Enable Control\n 3 1 read-write 0 Transmit threshold interrupt Disabled #0 1 Transmit threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 2 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Registers are read-only registers. 0 32 read-only SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing SSR bit #0 1 If this bit is set, SPISSx signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only and only available in Slave mode. 5 1 read-write 0 The transaction number or the transferred bit length of one transaction does not meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. The TX_NUM setting is not available on M05xxDN/DE, only the setting of TX_BIT_LEN will be considered #1 SSR Slave Select Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n 0 1 read-write 0 Set the SPISSx line to inactive state.\nKeep the SPISSx line at inactive state #0 1 Set the proper SPISSx line to active state.\nSelect the SPISSx line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL bit #1 SS_LTRIG Slave Select Level Trigger Enable (Slave Only)\n 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx).\n 2 1 read-write 0 The slave select signal SPISSx is active at low-level/falling-edge #0 1 The slave select signal SPISSx is active at high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 IF SPI Unit-Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16]. \nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 The transfer does not finish yet #0 1 The SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]. \n 24 1 read-only 0 The receive FIFO buffer is not empty #0 1 The receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25]. \n 25 1 read-only 0 The receive FIFO buffer is not full #0 1 The receive FIFO buffer is full #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 The transfer is not started #0 1 The transfer has started in Slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit #1 TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]. \n 26 1 read-only 0 The transmit FIFO buffer is not empty #0 1 The transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 The transmit FIFO buffer is not full #0 1 The transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SPI1 SPI Register Map SPI 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x20 0x8 registers n 0x34 0x4 registers n 0x3C 0xC registers n SPI_CNTRL SPI_CNTRL Control and Status Register 0x0 -1 read-write n 0x0 0x0 CLKP Clock Polarity\n 11 1 read-write 0 SPICLK idle low #0 1 SPICLK idle high #1 FIFO FIFO Mode Enable Control \nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.\nNote 1: Before enabling FIFO mode, the other related settings should be set in advance.\nNote 2: On M05xxBN, this bit must be 0. 21 1 read-write 0 FIFO Mode Disabled #0 1 FIFO Mode Enabled #1 GO_BUSY SPI Transfer Trigger and Busy Status\nIn FIFO mode, this bit will be controlled by hardware. Software cannot modify this bit.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In M05xxDN/DE SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state. 0 1 read-write 0 Writing 0 to this bit to stop data transfer if SPI is transferring #0 1 In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master #1 IE Unit-Transfer Interrupt Enable Control\n 17 1 read-write 0 SPI unit-transfer interrupt Disabled #0 1 SPI unit-transfer interrupt Enabled #1 IF Unit-Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 No transaction has been finished since this bit was cleared to 0 #0 1 SPI controller has finished one unit transfer #1 LSB LSB First\n 10 1 read-write 0 The MSB is transmitted/received first #0 1 The LSB is transmitted/received first #1 REORDER Byte Reorder Function and Byte Suspend Function Selection\nNote: Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits. 19 1 read-write 0 Byte reorder function and byte suspend function are Disabled #0 1 Byte reorder function Enabled. Byte suspend interval is determined by the setting of SP_CYCLE. Set SP_CYCLE to 0 to disabled byte suspend function #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_CNTRL[24]. \n 24 1 read-only 0 Indicates that the receive FIFO buffer is not empty #0 1 Indicates that the receive FIFO buffer is empty #1 RX_FULL Receive FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[25].\n 25 1 read-only 0 Indicates that the receive FIOF buffer is not full #0 1 Indicates that the receive FIFO buffer is full #1 RX_NEG Receive on Negative Edge\n 1 1 read-write 0 The received data input signal is latched on the rising edge of SPICLK #0 1 The received data input signal is latched on the falling edge of SPICLK #1 SLAVE Slave Mode Control\n 18 1 read-write 0 Master mode #0 1 Slave mode #1 SP_CYCLE Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.\nThe default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n 12 4 read-write TX_BIT_LEN Transfer Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n 3 5 read-write TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[26]. \n 26 1 read-only 0 Indicates that the transmit FIFO buffer is not empty #0 1 Indicates that the transmit FIFO buffer is empty #1 TX_FULL Transmit FIFO Buffer Full Indicator (Read Only) \nIt is a mutual mirror bit of SPI_STATUS[27]. \n 27 1 read-only 0 Indicates that the transmit FIFO buffer is not full #0 1 Indicates that the transmit FIFO buffer is full #1 TX_NEG Transmit on Negative Edge\n 2 1 read-write 0 The transmitted data output signal is driven on the rising edge of SPICLK #0 1 The transmitted data output signal is driven on the falling edge of SPICLK #1 SPI_CNTRL2 SPI_CNTRL2 Control and Status Register 2 0x3C read-write n 0x0 0x0 BCn Clock Configuration Backward Compatible Option \nRefer to the description of SPI_DIVIDER register for details. 31 1 read-write 0 The clock configuration is backward compatible to M05xxBN #0 1 The clock configuration is not backward compatible to M05xxBN #1 NOSLVSEL Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI when this bit is set to 1.\nNote: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1. 8 1 read-write 0 The controller is 4-wire bi-direction interface #0 1 The controller is 3-wire bi-direction interface in Slave mode. When this bit is set to 1, the controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1 #1 SLV_ABORT Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN and TX_NUM. The TX_NUM setting is not available on M05xxDN/DE, and only the setting of TX_BIT_LEN will be considered.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software. 9 1 read-write SLV_START_INTSTS Slave 3-wire Mode Start Interrupt Status\nThis bit dedicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n 11 1 read-write 0 Slave does not detect any SPI bus clock transition since the SSTA_INTEN bit was set to 1 #0 1 A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit #1 SSTA_INTEN Slave 3-wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\n 10 1 read-write 0 Transaction start interrupt Disabled #0 1 Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0 #1 SS_INT_OPT Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n 16 1 read-write 0 As the slave select signal goes to inactive level, the IF bit will NOT be set to 1 #0 1 As the slave select signal goes to inactive level, the IF bit will be set to 1 #1 SPI_DIVIDER SPI_DIVIDER Clock Divider Register 0x4 read-write n 0x0 0x0 DIVIDER Clock Divider\nOn M05xxBN:\nOnly available in Master mode. The value in this field is the frequency divider to determine the master's peripheral clock frequency and the bus clock frequency on the SPICLK output pin. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI bus clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI bus clock is the fifth of the frequency of slave's PCLK.\n\nOn M05xxDN/DE:\nOnly DIVIDER[7:0] is available. The value in this field is the frequency divider to determine the SPI peripheral clock frequency, fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation.\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register. 0 16 read-write DIVIDER2 Clock Divider 2 (M05xxBN Master Mode Only)\nThe value in this field is the 2nd frequency divider for generating the bus clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning. 16 16 read-write SPI_FIFO_CTL SPI_FIFO_CTL SPI FIFO Control Register 0x40 -1 read-write n 0x0 0x0 RXOV_INTEN Receive FIFO Overrun Interrupt Enable Control\n 6 1 read-write 0 Receive FIFO overrun interrupt Disabled #0 1 Receive FIFO overrun interrupt Enabled #1 RX_CLR Clear Receive FIFO Buffer\n 0 1 read-write 0 No effect #0 1 Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared #1 RX_INTEN Receive Threshold Interrupt Enable Control\n 2 1 read-write 0 Receive threshold interrupt Disabled #0 1 Receive threshold interrupt Enabled #1 RX_THRESHOLD Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0. 24 2 read-write TIMEOUT_INTEN Receive FIFO Time-out Interrupt Enable Control\n 21 1 read-write 0 Time-out interrupt Disabled #0 1 Time-out interrupt Enabled #1 TX_CLR Clear Transmit FIFO Buffer\n 1 1 read-write 0 No effect #0 1 Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared #1 TX_INTEN Transmit Threshold Interrupt Enable Control\n 3 1 read-write 0 Transmit threshold interrupt Disabled #0 1 Transmit threshold interrupt Enabled #1 TX_THRESHOLD Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0. 28 2 read-write SPI_RX0 SPI_RX0 Data Receive Register 0 0x10 read-only n 0x0 0x0 RX Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Registers are read-only registers. 0 32 read-only SPI_SSR SPI_SSR Slave Select Register 0x8 read-write n 0x0 0x0 AUTOSS Automatic Slave Select Function Enable (Master Only)\n 3 1 read-write 0 If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing SSR bit #0 1 If this bit is set, SPISSx signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished #1 LTRIG_FLAG Level Trigger Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only and only available in Slave mode. 5 1 read-write 0 The transaction number or the transferred bit length of one transaction does not meet the specified requirements #0 1 The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. The TX_NUM setting is not available on M05xxDN/DE, only the setting of TX_BIT_LEN will be considered #1 SSR Slave Select Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n 0 1 read-write 0 Set the SPISSx line to inactive state.\nKeep the SPISSx line at inactive state #0 1 Set the proper SPISSx line to active state.\nSelect the SPISSx line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL bit #1 SS_LTRIG Slave Select Level Trigger Enable (Slave Only)\n 4 1 read-write 0 The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge #0 1 The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high #1 SS_LVL Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx).\n 2 1 read-write 0 The slave select signal SPISSx is active at low-level/falling-edge #0 1 The slave select signal SPISSx is active at high-level/rising-edge #1 SPI_STATUS SPI_STATUS SPI Status Register 0x44 -1 read-write n 0x0 0x0 IF SPI Unit-Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16]. \nNote: This bit will be cleared by writing 1 to itself. 16 1 read-write 0 The transfer does not finish yet #0 1 The SPI controller has finished one unit transfer #1 RX_EMPTY Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]. \n 24 1 read-only 0 The receive FIFO buffer is not empty #0 1 The receive FIFO buffer is empty #1 RX_FIFO_COUNT Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer. 12 4 read-only RX_FULL Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25]. \n 25 1 read-only 0 The receive FIFO buffer is not full #0 1 The receive FIFO buffer is full #1 RX_INTSTS Receive FIFO Threshold Interrupt Status (Read Only)\n 0 1 read-only 0 The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD #0 1 The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD #1 RX_OVERRUN Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself. 2 1 read-write SLV_START_INTSTS Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n 11 1 read-write 0 The transfer is not started #0 1 The transfer has started in Slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit #1 TIMEOUT Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself. 20 1 read-write 0 No receive FIFO time-out event #0 1 The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically #1 TX_EMPTY Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]. \n 26 1 read-only 0 The transmit FIFO buffer is not empty #0 1 The transmit FIFO buffer is empty #1 TX_FIFO_COUNT Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer. 28 4 read-only TX_FULL Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n 27 1 read-only 0 The transmit FIFO buffer is not full #0 1 The transmit FIFO buffer is full #1 TX_INTSTS Transmit FIFO Threshold Interrupt Status (Read Only)\n 4 1 read-only 0 The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD #0 1 The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD #1 SPI_TX0 SPI_TX0 Data Transmit Register 0 0x20 write-only n 0x0 0x0 TX Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0]. 0 32 write-only SYST SYST Register Map SYST 0x0 0x0 0xC registers n CSR SYST_CSR SysTick Control and Status Register 0x0 read-write n 0x0 0x0 CLKSRC System Tick Clock Source Selection\n 2 1 read-write 0 Clock source is optional, refer to STCLK_S #0 1 Core clock used for SysTick timer #1 COUNTFLAG System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register. 16 1 read-write ENABLE System Tick Counter Enabled\n 0 1 read-write 0 Counter Disabled #0 1 Counter Enabled and will operate in a multi-shot manner #1 TICKINT System Tick Interrupt Enabled\n 1 1 read-write 0 Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to 0 has occurred #0 1 Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended #1 CVR SYST_CVR SysTick Current Value Register 0x8 read-write n 0x0 0x0 CURRENT System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register). 0 24 read-write RVR SYST_RVR SysTick Reload Value Register 0x4 read-write n 0x0 0x0 RELOAD System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0. 0 24 read-write TMR01 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP0 TCAP0 Timer0 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\nWhen TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately. 0 24 read-only TCAP1 TCAP1 0x30 read-write n 0x0 0x0 TCMPR0 TCMPR0 Timer0 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field. 0 24 read-write TCMPR1 TCMPR1 0x24 read-write n 0x0 0x0 TCSR0 TCSR0 Timer0 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAP_SRC Capture Pin Source selection \n 22 1 read-write 0 Capture Function source is from TxEX pin #0 1 Capture Function source is from internal ACMPx output signal #1 CEN Timer Enable Control\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset\n 26 1 read-write 0 No effect #0 1 Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1 #1 CTB Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.13.5.3 for detail description.\n 24 1 read-write 0 External event counter mode Disabled #0 1 External event counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable Control \nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 MODE Timer Operating Mode\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PERIODIC_SEL Periodic Mode Behavior Selection Enable If updated TCMP value TDR, TDR will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while Timer counter is active #1 TOUT_SEL Toggle-output Pin Selection \n 21 1 read-write 0 Toggle-output pin is from Tx pin #0 1 Toggle-output pin is from TxEx pin #1 WAKE_EN Wake-up Function Enable Control \n 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TCSR1 TCSR1 0x20 read-write n 0x0 0x0 TDR0 TDR0 Timer0 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf TDR_EN is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TDR1 TDR1 0x2C read-write n 0x0 0x0 TEXCON0 TEXCON0 Timer0 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Timer External Reset Counter / Timer External Capture Mode Selection\n 4 1 read-write 0 Transition on TxEX pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1 #0 1 Transition on TxEX pin is using to reset the 24-bit up counter #1 TCDB Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx pin de-bounce Disabled #0 1 Tx pin de-bounce Enabled #1 TEXDB Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of TxEX pin is detected with de-bounce circuit. 6 1 read-write 0 TxEX pin de-bounce Disabled #0 1 TxEX pin de-bounce Enabled #1 TEXEN Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n 3 1 read-write 0 RSTCAPSEL function of TxEX pin will be ignored #0 1 RSTCAPSEL function of TxEX pin is active #1 TEXIEN Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1. 5 1 read-write 0 TxEX pin detection Interrupt Disabled #0 1 TxEX pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect Selection\n 1 2 read-write 0 A 1 to 0 transition on TxEX pin will be detected #00 1 A 0 to 1 transition on TxEX pin will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TxEX pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n 0 1 read-write 0 A falling edge of Tx pin will be counted #0 1 A rising edge of Tx pin will be counted #1 TEXCON1 TEXCON1 0x34 read-write n 0x0 0x0 TEXISR0 TEXISR0 Timer0 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled, TxEX pin selected as external capture function, and a transition on TxEX pin matched the TEX_EDGE setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 TxEX pin interrupt did not occur #0 1 TxEX pin interrupt occurred #1 TEXISR1 TEXISR1 0x38 read-write n 0x0 0x0 TISR0 TISR0 Timer0 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TWF Timer Wake-up Flag \nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TISR1 TISR1 0x28 read-write n 0x0 0x0 TMR23 TIMER Register Map TIMER 0x0 0x0 0x1C registers n 0x20 0x1C registers n TCAP2 TCAP2 Timer2 Capture Data Register 0x10 read-only n 0x0 0x0 TCAP Timer Capture Data Register\nWhen TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately. 0 24 read-only TCAP3 TCAP3 0x30 read-write n 0x0 0x0 TCMPR2 TCMPR2 Timer2 Compare Register 0x4 read-write n 0x0 0x0 TCMP Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field. 0 24 read-write TCMPR3 TCMPR3 0x24 read-write n 0x0 0x0 TCSR2 TCSR2 Timer2 Control and Status Register 0x0 -1 read-write n 0x0 0x0 CACT Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n 25 1 read-only 0 24-bit up counter is not active #0 1 24-bit up counter is active #1 CAP_SRC Capture Pin Source selection \n 22 1 read-write 0 Capture Function source is from TxEX pin #0 1 Capture Function source is from internal ACMPx output signal #1 CEN Timer Enable Control\n 30 1 read-write 0 Stops/Suspends counting #0 1 Starts counting #1 CRST Timer Reset\n 26 1 read-write 0 No effect #0 1 Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1 #1 CTB Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.13.5.3 for detail description.\n 24 1 read-write 0 External event counter mode Disabled #0 1 External event counter mode Enabled #1 DBGACK_TMR ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects TIMER counting #0 1 ICE debug mode acknowledgement Disabled #1 IE Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU. 29 1 read-write 0 Timer Interrupt function Disabled #0 1 Timer Interrupt function Enabled #1 INTR_TRG_EN Inter-Timer Trigger Mode Enable Control \nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0. 19 1 read-write 0 Inter-Timer Trigger Capture mode Disabled #0 1 Inter-Timer Trigger Capture mode Enabled #1 MODE Timer Operating Mode\n 27 2 read-write 0 The Timer controller is operated in One-shot mode #00 1 The Timer controller is operated in Periodic mode #01 2 The Timer controller is operated in Toggle-output mode #10 3 The Timer controller is operated in Continuous Counting mode #11 PERIODIC_SEL Periodic Mode Behavior Selection Enable If updated TCMP value TDR, TDR will be reset to default value. 20 1 read-write 0 The behavior selection in periodic mode is Disabled #0 1 The behavior selection in periodic mode is Enabled #1 PRESCALE Prescale Counter\n 0 8 read-write TDR_EN Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n 16 1 read-write 0 Timer Data Register update Disabled #0 1 Timer Data Register update Enabled while Timer counter is active #1 TOUT_SEL Toggle-output Pin Selection \n 21 1 read-write 0 Toggle-output pin is from Tx pin #0 1 Toggle-output pin is from TxEx pin #1 WAKE_EN Wake-up Function Enable Control \n 23 1 read-write 0 Wake-up trigger event Disabled #0 1 Wake-up trigger event Enabled #1 TCSR3 TCSR3 0x20 read-write n 0x0 0x0 TDR2 TDR2 Timer2 Data Register 0xC read-only n 0x0 0x0 TDR Timer Data Register\nIf TDR_EN is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value. 0 24 read-only TDR3 TDR3 0x2C read-write n 0x0 0x0 TEXCON2 TEXCON2 Timer2 External Control Register 0x14 read-write n 0x0 0x0 RSTCAPSEL Timer External Reset Counter / Timer External Capture Mode Selection\n 4 1 read-write 0 Transition on TxEX pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1 #0 1 Transition on TxEX pin is using to reset the 24-bit up counter #1 TCDB Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit. 7 1 read-write 0 Tx pin de-bounce Disabled #0 1 Tx pin de-bounce Enabled #1 TEXDB Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of TxEX pin is detected with de-bounce circuit. 6 1 read-write 0 TxEX pin de-bounce Disabled #0 1 TxEX pin de-bounce Enabled #1 TEXEN Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n 3 1 read-write 0 RSTCAPSEL function of TxEX pin will be ignored #0 1 RSTCAPSEL function of TxEX pin is active #1 TEXIEN Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1. 5 1 read-write 0 TxEX pin detection Interrupt Disabled #0 1 TxEX pin detection Interrupt Enabled #1 TEX_EDGE Timer External Capture Pin Edge Detect Selection\n 1 2 read-write 0 A 1 to 0 transition on TxEX pin will be detected #00 1 A 0 to 1 transition on TxEX pin will be detected #01 2 Either 1 to 0 or 0 to 1 transition on TxEX pin will be detected #10 3 Reserved #11 TX_PHASE Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n 0 1 read-write 0 A falling edge of Tx pin will be counted #0 1 A rising edge of Tx pin will be counted #1 TEXCON3 TEXCON3 0x34 read-write n 0x0 0x0 TEXISR2 TEXISR2 Timer2 External Interrupt Status Register 0x18 read-write n 0x0 0x0 TEXIF Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled, TxEX pin selected as external capture function, and a transition on TxEX pin matched the TEX_EDGE setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 TxEX pin interrupt did not occur #0 1 TxEX pin interrupt occurred #1 TEXISR3 TEXISR3 0x38 read-write n 0x0 0x0 TISR2 TISR2 Timer2 Interrupt Status Register 0x8 read-write n 0x0 0x0 TIF Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 TDR value matches the TCMP value #1 TWF Timer Wake-up Flag \nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 Timer does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated #1 TISR3 TISR3 0x28 read-write n 0x0 0x0 UART0 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_RX_EN LIN RX Enable Control \n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break Mode Disabled #0 1 LIN TX Break Mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) Control\nNote: It cannot be active with RS485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation Mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation Mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control\nThis bit is use to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 RS-485 address detection mode Disabled #0 1 RS-485 address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485_AAD or RS485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation Mode (AUD) Disabled #0 1 RS-485 Auto Direction Operation Mode (AUD) Enabled #1 RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation Mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation Mode (NMM) Enabled #1 UA_LIN_BKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2. 0 4 read-write UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicated the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nNote1: Refer to the section 6.14.5.1 for more information.\nNote2: In IrDA function mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal 1\nNote1: Refer to the section 6.14.5.1 for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable, an interrupt will generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_IF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select\nUART Controller function mode selection.\n 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto-Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto-flow control Disabled #0 1 CTS auto-flow control Enabled #1 AUTO_RTS_EN RTS Auto-Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will reassert RTS signal. 12 1 read-write 0 RTS auto-flow control Disabled #0 1 RTS auto-flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_RX_BRK_IEN LIN RX Break Field Detected Interrupt Enable Control\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus RX break filed interrupt Disabled #0 1 LIN bus RX break filed interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 RTO_IEN RX Time-out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-out counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 WAKE_EN UART Wake-up Function Enable Control\nNote: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode. 6 1 read-write 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX Inverse RX Input Control\n 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX Inverse RX Output Control\n 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT IrDA Receiver Enable Control\n 1 1 read-write 0 IrDA receiver Enabled #0 1 IrDA transmitter Enabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. On M05xxBN, this bit is also set when Break Interrupt Flag, Parity Error Flag or Frame Error Flag (BIF, PEF or FEF) is set.\nWhen BUF_ERR_IF is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote1: On M05xxDN/DE, this bit is read only and reset to 0 when all bits of TX_OVER_IF and RX_OVER_IF are cleared. \nNote2: On M05xxBN, this bit is read only and reset to 0 when all bits of TX_OVER_IF, RX_OVER_IF, BIF, FEF and PEF are cleared. (M05xxBN Only) 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 buffer error interrupt is generated #1 LIN_RX_BREAK_IF LIN Bus RX Break Field Detected Flag\nThis bit is set when RX received LIN Break Field. If LIN_RX_BRK_IEN (UA_IER [8]) is enabled the LIN RX Break interrupt will be generated.\nNote: This bit is cleared by writing 1 to it. 7 1 read-write 0 No LIN RX Break received #0 1 LIN RX Break received #1 LIN_RX_BREAK_INT LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.\n 15 1 read-only 0 No LIN RX Break interrupt is generated #0 1 LIN RX Break interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS485_ADD_DETF are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n 12 1 read-only 0 No Time-out interrupt is generated #0 1 Time-out interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6100 and Figure 6101 for UART function mode.\nNote2: Refer to Figure 6105 and Figure 6106 for RS-485 function mode. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTS RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTS_ST RTS Pin Status (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCTSF Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 699 for more information. 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART Controller will return an 8-bit data received from UART_RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART Controller will send out an 8-bit data through the UART_ TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-out Interrupt Comparator\n 0 8 read-write UART1 UART Register Map UART 0x0 0x0 0x30 registers n UA_ALT_CSR UA_ALT_CSR UART Alternate Control/Status Register 0x2C read-write n 0x0 0x0 ADDR_MATCH Address Match Value Register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode. 24 8 read-write LIN_RX_EN LIN RX Enable Control \n 6 1 read-write 0 LIN RX mode Disabled #0 1 LIN RX mode Enabled #1 LIN_TX_EN LIN TX Break Mode Enable Control\nNote: When TX break field transfer operation finished, this bit will be cleared automatically. 7 1 read-write 0 LIN TX Break Mode Disabled #0 1 LIN TX Break Mode Enabled #1 RS485_AAD RS-485 Auto Address Detection Operation Mode (AAD) Control\nNote: It cannot be active with RS485_NMM operation mode. 9 1 read-write 0 RS-485 Auto Address Detection Operation Mode (AAD) Disabled #0 1 RS-485 Auto Address Detection Operation Mode (AAD) Enabled #1 RS485_ADD_EN RS-485 Address Detection Enable Control\nThis bit is use to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode. 15 1 read-write 0 RS-485 address detection mode Disabled #0 1 RS-485 address detection mode Enabled #1 RS485_AUD RS-485 Auto Direction Mode (AUD) Control\nNote: It can be active with RS485_AAD or RS485_NMM operation mode. 10 1 read-write 0 RS-485 Auto Direction Operation Mode (AUD) Disabled #0 1 RS-485 Auto Direction Operation Mode (AUD) Enabled #1 RS485_NMM RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode. 8 1 read-write 0 RS-485 Normal Multi-drop Operation Mode (NMM) Disabled #0 1 RS-485 Normal Multi-drop Operation Mode (NMM) Enabled #1 UA_LIN_BKFL UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2. 0 4 read-write UA_BAUD UA_BAUD UART Baud Rate Divisor Register 0x24 -1 read-write n 0x0 0x0 BRD Baud Rate Divider\nThe field indicated the baud rate divider. 0 16 read-write DIVIDER_X Divider X\n 24 4 read-write DIV_X_EN Divider X Enable Control\nNote1: Refer to the section 6.14.5.1 for more information.\nNote2: In IrDA function mode, this bit must disable. 29 1 read-write 0 Divider X Disabled (the equation of M = 16) #0 1 Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8) #1 DIV_X_ONE Divider X Equal 1\nNote1: Refer to the section 6.14.5.1 for more information. 28 1 read-write 0 Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8) #0 1 Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 8) #1 UA_FCR UA_FCR UART FIFO Control Register 0x8 -1 read-write n 0x0 0x0 RFITL RX FIFO Interrupt (RDA_INT) Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDA_IF will be set (if RDA_IEN in UA_IER register is enable, an interrupt will generated).\n 4 4 read-write 0 RX FIFO Interrupt Trigger Level is 1 byte #0000 1 RX FIFO Interrupt Trigger Level is 4 bytes #0001 2 RX FIFO Interrupt Trigger Level is 8 bytes #0010 3 RX FIFO Interrupt Trigger Level is 14 bytes #0011 RFR RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles. 1 1 read-write 0 No effect #0 1 Reset the RX internal state machine and pointers #1 RTS_TRI_LEV RTS Trigger Level (for Auto-flow Control Use)\nNote: This field is used for RTS auto-flow control. 16 4 read-write 0 RTS Trigger Level is 1 byte #0000 1 RTS Trigger Level is 4 bytes #0001 2 RTS Trigger Level is 8 bytes #0010 3 RTS Trigger Level is 14 bytes #0011 RX_DIS Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR [8]) is programmed. 8 1 read-write 0 Receiver Enabled #0 1 Receiver Disabled #1 TFR TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART Controller peripheral clock cycles. 2 1 read-write 0 No effect #0 1 Reset the TX internal state machine and pointers #1 UA_FSR UA_FSR UART FIFO Status Register 0x18 -1 read-write n 0x0 0x0 BIF Break Interrupt Flag (Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 6 1 read-only 0 No Break interrupt is generated #0 1 Break interrupt is generated #1 FEF Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 5 1 read-only 0 No framing error is generated #0 1 Framing error is generated #1 PEF Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note1: This bit is read only, but can be cleared by writing '1' to it . Note2: This bit is read only, but can be cleared by writing '1' to RFR (UA_FCR [1]) (Available on M05xxBN and M05xxDN/DE). 4 1 read-only 0 No parity error is generated #0 1 Parity error is generated #1 RS485_ADD_DETF RS-485 Address Byte Detection Flag\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it. 3 1 read-write RX_EMPTY Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data. 14 1 read-only 0 RX FIFO is not empty #0 1 RX FIFO is empty #1 RX_FULL Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 15 1 read-only 0 RX FIFO is not full #0 1 RX FIFO is full #1 RX_OVER_IF RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 RX FIFO is not overflow #0 1 RX FIFO is overflow #1 RX_POINTER RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15. 8 6 read-only TE_FLAG Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 28 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_EMPTY Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). 22 1 read-only 0 TX FIFO is not empty #0 1 TX FIFO is empty #1 TX_FULL Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware. 23 1 read-only 0 TX FIFO is not full #0 1 TX FIFO is full #1 TX_OVER_IF TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it. 24 1 read-write 0 TX FIFO is not overflow #0 1 TX FIFO is overflow #1 TX_POINTER TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15. 16 6 read-only UA_FUN_SEL UA_FUN_SEL UART Function Select Register 0x30 read-write n 0x0 0x0 FUN_SEL Function Select\nUART Controller function mode selection.\n 0 2 read-write 0 UART function mode #00 1 LIN function mode #01 2 IrDA function mode #10 3 RS-485 function mode #11 UA_IER UA_IER UART Interrupt Enable Register 0x4 read-write n 0x0 0x0 AUTO_CTS_EN CTS Auto-Flow Control Enable Control\nNote: When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted). 13 1 read-write 0 CTS auto-flow control Disabled #0 1 CTS auto-flow control Enabled #1 AUTO_RTS_EN RTS Auto-Flow Control Enable Control\nNote: When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will reassert RTS signal. 12 1 read-write 0 RTS auto-flow control Disabled #0 1 RTS auto-flow control Enabled #1 BUF_ERR_IEN Buffer Error Interrupt Enable Control\n 5 1 read-write 0 BUF_ERR_INT Masked off #0 1 BUF_ERR_INT Enabled #1 LIN_RX_BRK_IEN LIN RX Break Field Detected Interrupt Enable Control\nNote: This bit is used for LIN function mode. 8 1 read-write 0 LIN bus RX break filed interrupt Disabled #0 1 LIN bus RX break filed interrupt Enabled #1 MODEM_IEN Modem Status Interrupt Enable Control\n 3 1 read-write 0 MODEM_INT Masked off #0 1 MODEM_INT Enabled #1 RDA_IEN Receive Data Available Interrupt Enable Control\n 0 1 read-write 0 RDA_INT Masked off #0 1 RDA_INT Enabled #1 RLS_IEN Receive Line Status Interrupt Enable Control\n 2 1 read-write 0 RLS_INT Masked off #0 1 RLS_INT Enabled #1 RTO_IEN RX Time-out Interrupt Enable Control\n 4 1 read-write 0 TOUT_INT Masked off #0 1 TOUT_INT Enabled #1 THRE_IEN Transmit Holding Register Empty Interrupt Enable Control\n 1 1 read-write 0 THRE_INT Masked off #0 1 THRE_INT Enabled #1 TIME_OUT_EN Time-out counter Enable Control\n 11 1 read-write 0 Time-out counter Disabled #0 1 Time-out counter Enabled #1 WAKE_EN UART Wake-up Function Enable Control\nNote: when the chip is in Power-down mode, an external CTS change will wake-up chip from Power-down mode. 6 1 read-write 0 UART wake-up function Disabled #0 1 UART wake-up function Enabled #1 UA_IRCR UA_IRCR UART IrDA Control Register 0x28 -1 read-write n 0x0 0x0 INV_RX Inverse RX Input Control\n 6 1 read-write 0 No inversion #0 1 Inverse RX input signal #1 INV_TX Inverse RX Output Control\n 5 1 read-write 0 No inversion #0 1 Inverse TX output signal #1 TX_SELECT IrDA Receiver Enable Control\n 1 1 read-write 0 IrDA receiver Enabled #0 1 IrDA transmitter Enabled #1 UA_ISR UA_ISR UART Interrupt Status Register 0x1C -1 read-write n 0x0 0x0 BUF_ERR_IF Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TX_OVER_IF or RX_OVER_IF) is set. On M05xxBN, this bit is also set when Break Interrupt Flag, Parity Error Flag or Frame Error Flag (BIF, PEF or FEF) is set.\nWhen BUF_ERR_IF is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote1: On M05xxDN/DE, this bit is read only and reset to 0 when all bits of TX_OVER_IF and RX_OVER_IF are cleared. \nNote2: On M05xxBN, this bit is read only and reset to 0 when all bits of TX_OVER_IF, RX_OVER_IF, BIF, FEF and PEF are cleared. (M05xxBN Only) 5 1 read-only 0 No buffer error interrupt flag is generated #0 1 Buffer error interrupt flag is generated #1 BUF_ERR_INT Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n 13 1 read-only 0 No buffer error interrupt is generated #0 1 buffer error interrupt is generated #1 LIN_RX_BREAK_IF LIN Bus RX Break Field Detected Flag\nThis bit is set when RX received LIN Break Field. If LIN_RX_BRK_IEN (UA_IER [8]) is enabled the LIN RX Break interrupt will be generated.\nNote: This bit is cleared by writing 1 to it. 7 1 read-write 0 No LIN RX Break received #0 1 LIN RX Break received #1 LIN_RX_BREAK_INT LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.\n 15 1 read-only 0 No LIN RX Break interrupt is generated #0 1 LIN RX Break interrupt is generated #1 MODEM_IF MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF. 3 1 read-only 0 No Modem interrupt flag is generated #0 1 Modem interrupt flag is generated #1 MODEM_INT MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n 11 1 read-only 0 No Modem interrupt is generated #0 1 Modem interrupt is generated #1 RDA_IF Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL). 0 1 read-only 0 No RDA interrupt flag is generated #0 1 RDA interrupt flag is generated #1 RDA_INT Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n 8 1 read-only 0 No RDA interrupt is generated #0 1 RDA interrupt is generated #1 RLS_IF Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF, FEF, PEF and RS485_ADD_DETF are cleared. 2 1 read-only 0 No RLS interrupt flag is generated #0 1 RLS interrupt flag is generated #1 RLS_INT Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.\n 10 1 read-only 0 No RLS interrupt is generated #0 1 RLS interrupt is generated #1 THRE_IF Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty). 1 1 read-only 0 No THRE interrupt flag is generated #0 1 THRE interrupt flag is generated #1 THRE_INT Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n 9 1 read-only 0 No THRE interrupt is generated #0 1 THRE interrupt is generated #1 TOUT_IF Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RTO_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it. 4 1 read-only 0 No Time-out interrupt flag is generated #0 1 Time-out interrupt flag is generated #1 TOUT_INT Time-out Interrupt Indicator (Read Only)\nThis bit is set if RTO_IEN and TOUT_IF are both set to 1.\n 12 1 read-only 0 No Time-out interrupt is generated #0 1 Time-out interrupt is generated #1 UA_LCR UA_LCR UART Line Control Register 0xC read-write n 0x0 0x0 BCB Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n 6 1 read-write 0 Break control Disabled #0 1 Break control Enabled #1 EPE Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set. 4 1 read-write 0 Odd number of logic 1's is transmitted and checked in each word #0 1 Even number of logic 1's is transmitted and checked in each word #1 NSB Number of STOP bit 2 1 read-write 0 One STOP bit is generated in the transmitted data #0 1 When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. When select 6-, 7- and 8-bti word length, 2 STOP bit is generated in the transmitted data #1 PBE Parity Bit Enable Control\n 3 1 read-write 0 No parity bit #0 1 Parity bit is generated on each outgoing character and is checked on each incoming data #1 SPE Stick Parity Enable Control\n 5 1 read-write 0 Stick parity Disabled #0 1 If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1 #1 WLS Word Length Selection\n 0 2 read-write 0 Word length is 5-bit #00 1 Word length is 6-bit #01 2 Word length is 7-bit #10 3 Word length is 8-bit #11 UA_MCR UA_MCR UART Modem Control Register 0x10 -1 read-write n 0x0 0x0 LEV_RTS RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6100 and Figure 6101 for UART function mode.\nNote2: Refer to Figure 6105 and Figure 6106 for RS-485 function mode. 9 1 read-write 0 RTS pin output is high level active #0 1 RTS pin output is low level active #1 RTS RTS (Request-To-Send) Signal Control\nThis bit is direct control internal RTS signal active or not, and then drive the RTS pin output with LEV_RTS bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is enabled in UART function mode.\nNote2: This RTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 1 1 read-write 0 RTS signal is active #0 1 RTS signal is inactive #1 RTS_ST RTS Pin Status (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n 13 1 read-only 0 RTS pin output is low level voltage logic state #0 1 RTS pin output is high level voltage logic state #1 UA_MSR UA_MSR UART Modem Status Register 0x14 -1 read-write n 0x0 0x0 CTS_ST CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and CTS multi-function port is selected. 4 1 read-only 0 CTS pin input is low level voltage logic state #0 1 CTS pin input is high level voltage logic state #1 DCTSF Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 CTS input has not change state #0 1 CTS input has change state #1 LEV_CTS CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\nNote: Refer to Figure 699 for more information. 8 1 read-write 0 CTS pin input is high level active #0 1 CTS pin input is low level active #1 UA_RBR UA_RBR UART Receive Buffer Register 0x0 read-only n 0x0 0x0 RBR Receive Buffer Register (Read Only)\nBy reading this register, the UART Controller will return an 8-bit data received from UART_RX pin (LSB first). 0 8 read-only UA_THR UA_THR UART Transmit Holding Register UA_RBR 0x0 write-only n 0x0 0x0 THR Transmit Holding Register\nBy writing to this register, the UART Controller will send out an 8-bit data through the UART_ TX pin (LSB first). 0 8 write-only UA_TOR UA_TOR UART Time-out Register 0x20 read-write n 0x0 0x0 DLY TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit. 8 8 read-write TOIC Time-out Interrupt Comparator\n 0 8 read-write WDT WDT Register Map WDT 0x0 0x0 0x8 registers n WTCR WTCR Watchdog Timer Control Register 0x0 -1 read-write n 0x0 0x0 DBGACK_WDT ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WDT counting #0 1 ICE debug mode acknowledgement Disabled #1 WTE Watchdog Timer Enable Control (Write Protect)\n 7 1 read-write 0 WDT Disabled. (This action will reset the internal up counter value.) #0 1 WDT Enabled #1 WTIE Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n 6 1 read-write 0 WDT time-out interrupt Disabled #0 1 WDT time-out interrupt Enabled #1 WTIF Watchdog Timer Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it. 3 1 read-write 0 WDT time-out interrupt did not occur #0 1 WDT time-out interrupt occurred #1 WTIS Watchdog Timer Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n 8 3 read-write 0 24 *TWDT #000 1 26 *TWDT #001 2 28 *TWDT #010 3 210 *TWDT #011 4 212 *TWDT #100 5 214 *TWDT #101 6 216 *TWDT #110 7 218 *TWDT #111 WTR Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware. 0 1 read-write 0 No effect #0 1 Reset the internal 18-bit WDT up counter value #1 WTRE Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: Fixed 1024 * TWDT delay period on M05xxBN.\nSelectable 3/18/130/1026 * TWDT delay period controlled by WTRDSEL on M05xxDE. 1 1 read-write 0 WDT time-out reset function Disabled #0 1 WDT time-out reset function Enabled #1 WTRF Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 2 1 read-write 0 WDT time-out reset did not occur #0 1 WDT time-out reset occurred #1 WTWKE Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator. 4 1 read-write 0 Wake-up trigger event Disabled if WDT time-out interrupt signal generated #0 1 Wake-up trigger event Enabled if WDT time-out interrupt signal generated #1 WTWKF Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it. 5 1 read-write 0 WDT does not cause chip wake-up #0 1 Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated #1 WTCRALT WTCRALT Watchdog Timer Alternative Control Register 0x4 read-write n 0x0 0x0 WTRDSEL Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, software has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT Reset Delay Period for different WDT time-out period.\nNote: This register will be reset to 0 if WDT time-out reset happened. 0 2 read-write 0 Watchdog Timer Reset Delay Period is 1026 * WDT_CLK #00 1 Watchdog Timer Reset Delay Period is 130* WDT_CLK #01 2 Watchdog Timer Reset Delay Period is 18 * WDT_CLK #10 3 Watchdog Timer Reset Delay Period is 3 * WDT_CLK #11 WWDT WWDT Register Map WWDT 0x0 0x0 0x10 registers n WWDTCR WWDTCR Window Watchdog Timer Control Register 0x4 -1 read-write n 0x0 0x0 DBGACK_WWDT ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not. 31 1 read-write 0 ICE debug mode acknowledgement effects WWDT counting #0 1 ICE debug mode acknowledgement Disabled #1 PERIODSEL WWDT Counter Prescale Period Selection\n 8 4 read-write 0 Pre-scale is 1 Max time-out period is 1 * 64 * TWWDT #0000 1 Pre-scale is 2 Max time-out period is 2 * 64 * TWWDT #0001 2 Pre-scale is 4 Max time-out period is 4 * 64 * TWWDT #0010 3 Pre-scale is 8 Max time-out period is 8 * 64 * TWWDT #0011 4 Pre-scale is 16 Max time-out period is 16 * 64 * TWWDT #0100 5 Pre-scale is 32 Max time-out period is 32 * 64 * TWWDT #0101 6 Pre-scale is 64 Max time-out period is 64 * 64 * TWWDT #0110 7 Pre-scale is 128 Max time-out period is 128 * 64 * TWWDT #0111 8 Pre-scale is 192 Max time-out period is 192 * 64 * TWWDT #1000 9 Pre-scale is 256 Max time-out period is 256 * 64 * TWWDT #1001 10 Pre-scale is 384 Max time-out period is 384 * 64 * TWWDT #1010 11 Pre-scale is 512 Max time-out period is 512 * 64 * TWWDT #1011 12 Pre-scale is 768 Max time-out period is 768 * 64 * TWWDT #1100 13 Pre-scale is 1024 Max time-out period is 1024 * 64 * TWWDT #1101 14 Pre-scale is 1536 Max time-out period is 1536 * 64 * TWWDT #1110 15 Pre-scale is 2048 Max time-out period is 2048 * 64 * TWWDT #1111 WINCMP WWDT Window Compare Register Set this register to adjust the valid reload window. Note: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately. 16 6 read-write WWDTEN WWDT Enable Control\n 0 1 read-write 0 WWDT counter is stopped #0 1 WWDT counter is starting counting #1 WWDTIE WWDT Interrupt Enable Control\nIf this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.\n 1 1 read-write 0 WWDT counter compare match interrupt Disabled #0 1 WWDT counter compare match interrupt Enabled #1 WWDTCVR WWDTCVR Window Watchdog Timer Counter Value Register 0xC -1 read-only n 0x0 0x0 WWDTCVAL WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value. 0 6 read-only WWDTRLD WWDTRLD Window Watchdog Timer Reload Counter Register 0x0 write-only n 0x0 0x0 WWDTRLD WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. \nNote: Software can only write WWDTRLD to reload WWDT counter value whencurrent WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when current WWDT counter value is larger than WINCMP, WWDT reset signal will generate immediately. 0 32 write-only WWDTSR WWDTSR Window Watchdog Timer Status Register 0x8 read-write n 0x0 0x0 WWDTIF WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP value.\nNote: This bit is cleared by writing 1 to it. 0 1 read-write 0 No effect #0 1 WWDT counter value matches WINCMP value #1 WWDTRF WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it. 1 1 read-write 0 WWDT time-out reset did not occur #0 1 WWDT time-out reset occurred #1