nuvoTon
NM1500_v1
2024.05.05
NM1500_v1 SVD file
8
32
ACMP
ACMP Register Map
ACMP
0x0
0x0
0x10
registers
n
ACMP0CR
ACMP0CR
Analog Comparator 0 Control Register
0x0
read-write
n
0x0
0x0
ACMP0INV
Analog Comparator 0 output inverse select
6
1
read-write
0
The comparator output inverse function Disabled
#0
1
The comparator output inverse function Enabled
#1
ACMP0_EN
Analog Comparator 0 Enable\nComparator output need wait stable 10 us after ACMP0_EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ACMP0_HYS_EN
CMP Hysteresis Enable
2
1
read-write
0
Hysteresis function Disabled (Default).
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
ACMPIE0
Analog Comparator 0 Interrupt Enable
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CN0
Analog Comparator 0 negative input select
4
1
read-write
0
The comparator reference pin P8.3/CPN0 is selected as the negative comparator input
#0
1
The internal comparator reference voltage (Vref=1.2V) is selected as the negative comparator input
#1
CP0
Analog Comparator 0 positive input select
3
1
read-write
0
The comparator reference pin P8.4/CPP0 is selected as the positive comparator input
#0
1
The internal OP amplifier 0 output is selected as the positive comparator input
#1
ACMP1CR
ACMP1CR
Analog Comparator 1 Control Register
0x4
read-write
n
0x0
0x0
ACMP1INV
Analog Comparator 1 output inverse select
6
1
read-write
0
The comparator output inverse function Disabled
#0
1
The comparator output inverse function Enabled
#1
ACMP1_EN
Analog Comparator 1 Enable\nComparator output need wait stable 10 us after ACMP1_EN is set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ACMP1_HYS_EN
CMP Hysteresis Enable
2
1
read-write
0
Hysteresis function Disabled (Default).
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
ACMPIE1
Analog Comparator 1 Interrupt Enable
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CN1
Analog Comparator 1 negative input select
4
1
read-write
0
The comparator reference pin P6.4/CPN1 is selected as the negative comparator input
#0
1
The internal comparator reference voltage (Vref=1.2V) is selected as the negative comparator input
#1
CP1
Analog Comparator 1 positive input select
3
1
read-write
0
The comparator reference pin P6.5/CPP1 is selected as the positive comparator input
#0
1
The internal OP amplifier 1 output is selected as the positive comparator input
#1
ACMP2CR
ACMP2CR
Analog Comparator 2 Control Register
0x8
read-write
n
0x0
0x0
ACMP2INV
Analog Comparator 2 output inverse select
6
1
read-write
0
The comparator output inverse function Disabled
#0
1
The comparator output inverse function Enabled
#1
ACMP2_EN
Analog Comparator 2 Enable\nComparator output need wait stable 10 us after ACMP2_EN is first set.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ACMP2_HYS_EN
CMP Hysteresis Enable
2
1
read-write
0
Hysteresis function Disabled (Default).
#0
1
Hysteresis function Enabled. The typical range is 20mV
#1
ACMPIE2
Analog Comparator 2 Interrupt Enable
1
1
read-write
0
Interrupt function Disabled
#0
1
Interrupt function Enabled
#1
CN2
Analog Comparator 2 negative input select
4
1
read-write
0
The comparator reference pin P7.4/CPN2 is selected as the negative comparator input
#0
1
The internal comparator reference voltage (Vref=1.2V) is selected as the negative comparator input
#1
ACMPSR
ACMPSR
Analog Comparator Status Register
0xC
read-write
n
0x0
0x0
ACMPF0
Compare 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if ACMPCR0[1] is set to 1.\nWrite 1 to clear this bit to 0.
0
1
read-write
ACMPF1
Compare 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if ACMPCR1[1] is set to 1.\nWrite 1 to clear this bit to 0.
1
1
read-write
ACMPF2
Compare 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state. This will cause an interrupt if ACMPCR2[1] is set to 1.\nWrite 1 to clear this bit to 0.
2
1
read-write
CO0
Compare 0 Output
8
1
read-write
CO1
Compare 1 Output
9
1
read-write
CO2
Compare 2 Output
10
1
read-write
ADC
ADC Register Map
ADC
0x0
0x0
0x9C
registers
n
0xA4
0x18
registers
n
ADCHISELR
ADCHISELR
A/D Channel Input Sources Select Register
0x44
read-write
n
0x0
0x0
AINA0SEL
A/D Channel AINA[0] Analog Input Selection
0
1
read-write
0
AINA[0] pin P6.0/AINA0 is selected as the ADC AINA[0] input signal
#0
1
OP Amplifier 0 output is selected as the ADC AINA[0] input signal
#1
AINB0SEL
A/D Channel AINB[0] Analog Input Selection
1
1
read-write
0
AINB[0] pin P7.0/AINB0 is selected as the A/D AINB[0] input signal
#0
1
OP Amplifier 1 output is selected as the A/D AINB[0] input signal
#1
PRESEL
A/D Channel AINA[7] Analog Input Selection
2
2
read-write
0
Analog Input Channel AINA7
#00
1
Band-gap (VBG) Analog Input
#01
2
VTEMP Internal Temperature Sensor Analog Input
#10
3
Analog ground
#11
ADCMPR0
ADCMPR0
A/D Result Compare Register 0
0xA8
read-write
n
0x0
0x0
ADCMPIE
A/D Result Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, ADCMPF bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
1
1
read-write
0
Compare function interrupt Disabled
#0
1
Compare function interrupt Enabled
#1
ADCMP_EN
A/D Result Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified SAMPLE conversion result when converted data is loaded into ADDR register.
0
1
read-write
0
Compare Disabled
#0
1
Compare Enabled
#1
CMPCOND
Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
2
1
read-write
0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#0
1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1
CMPD
Comparison Data\nThe 12 bits data is used to compare with the conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
16
12
read-write
CMPMATCNT
Compare Match Count\nWhen the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
8
4
read-write
CMPSMPL
Compare SAMPLE Selection
3
3
read-write
0
SAMPLEA0 conversion result ADDRA0 is selected to be compared
#000
1
SAMPLEA1 conversion result ADDRA1 is selected to be compared
#001
2
SAMPLEA2 conversion result ADDRA2 is selected to be compared
#010
3
SAMPLEA3 conversion result ADDRA3 is selected to be compared
#011
4
SAMPLEB0 conversion result ADDRB0 is selected to be compared
#100
5
SAMPLEB1 conversion result ADDRB1 is selected to be compared
#101
6
SAMPLEB2 conversion result ADDRB2 is selected to be compared
#110
7
SAMPLEB3 conversion result ADDRB3 is selected to be compared
#111
ADCMPR1
ADCMPR1
0xAC
read-write
n
0x0
0x0
ADCR
ADCR
A/D Control Register
0x40
read-write
n
0x0
0x0
ADIE0
Specific SAMPLE A/D ADINT0 Interrupt Enable\nThe A/D converter generates a conversion end ADF0 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE0 bit is set then conversion end interrupt request ADINT0 is generated.
2
1
read-write
0
Specific SAMPLE A/D ADINT0 interrupt function Disabled
#0
1
Specific SAMPLE A/D ADINT0 interrupt function Enabled
#1
ADIE1
Specific SAMPLE A/D ADINT1 Interrupt Enable\nThe A/D converter generates a conversion end ADF1 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE1 bit is set then conversion end interrupt request ADINT1 is generated.
3
1
read-write
0
Specific SAMPLE A/D ADINT1 interrupt function Disabled
#0
1
Specific SAMPLE A/D ADINT1 interrupt function Enabled
#1
ADIE2
Specific SAMPLE A/D ADINT2 Interrupt Enable\nThe A/D converter generates a conversion end ADF2 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE2 bit is set then conversion end interrupt request ADINT2 is generated.
4
1
read-write
0
Specific SAMPLE A/D ADINT2 interrupt function Disabled
#0
1
Specific SAMPLE A/D ADINT2 interrupt function Enabled
#1
ADIE3
Specific SAMPLE A/D ADINT3 Interrupt Enable\nThe A/D converter generates a conversion end ADF3 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE3 bit is set then conversion end interrupt request ADINT3 is generated.
5
1
read-write
0
Specific SAMPLE A/D ADINT3 interrupt function Disabled
#0
1
Specific SAMPLE A/D ADINT3 interrupt function Enabled
#1
ADRESET
ADCA, ADCB A/D Converter control circuits reset\nADRESET bit remains 1 during ADC reset, when ADC reset end, the ADRESET bit is automatically cleared to 0.
1
1
read-write
0
Writing 0 has no effect
#0
1
Writing 1 will cause ADC control circuits reset to initial state, but not change the ADC registers value
#1
AD_EN
A/D Converter Enable\nBefore starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
0
1
read-write
0
Disabled
#0
1
Enabled
#1
ADDRA0
ADDRA0
A/D Data Register 0 for SAMPLEA0
0x0
read-only
n
0x0
0x0
OVERRUN
Over Run Flag\nIf converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
16
1
read-only
0
Data in RSLT[11:0] is the recent conversion result
#0
1
Data in RSLT[11:0] is overwritten
#1
RSLT
A/D Conversion Result\nThis field contains 12-bit conversion result.
0
12
read-only
VALID
Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is read.
17
1
read-only
0
Data in RSLT[11:0] bits is not valid
#0
1
Data in RSLT[11:0] bits is valid
#1
ADDRA1
ADDRA1
0x4
read-write
n
0x0
0x0
ADDRA2
ADDRA2
0x8
read-write
n
0x0
0x0
ADDRA3
ADDRA3
0xC
read-write
n
0x0
0x0
ADDRA4
ADDRA4
0x10
read-write
n
0x0
0x0
ADDRA5
ADDRA5
0x14
read-write
n
0x0
0x0
ADDRA6
ADDRA6
0x18
read-write
n
0x0
0x0
ADDRA7
ADDRA7
0x1C
read-write
n
0x0
0x0
ADDRB0
ADDRB0
0x20
read-write
n
0x0
0x0
ADDRB1
ADDRB1
0x24
read-write
n
0x0
0x0
ADDRB2
ADDRB2
0x28
read-write
n
0x0
0x0
ADDRB3
ADDRB3
0x2C
read-write
n
0x0
0x0
ADDRB4
ADDRB4
0x30
read-write
n
0x0
0x0
ADDRB5
ADDRB5
0x34
read-write
n
0x0
0x0
ADDRB6
ADDRB6
0x38
read-write
n
0x0
0x0
ADDRB7
ADDRB7
0x3C
read-write
n
0x0
0x0
ADIFOVR
ADIFOVR
A/D ADINT3~0 Interrupt Flag Over Run Register
0x50
read-write
n
0x0
0x0
ADFOV0
A/D ADINT0 Interrupt flag over run bit
It is cleared by write 1.
0
1
read-write
0
ADINT0 interrupt flag is not overwrite to 1
#0
1
ADINT0 interrupt flag is overwrite to 1
#1
ADFOV1
A/D ADINT1 Interrupt flag over run bit
It is cleared by write 1.
1
1
read-write
0
ADINT1 interrupt flag is not overwrite to 1
#0
1
ADINT1 interrupt flag is overwrite to 1
#1
ADFOV2
A/D ADINT2 Interrupt flag over run bit
It is cleared by write 1.
2
1
read-write
0
ADINT2 interrupt flag is not overwrite to 1
#0
1
ADINT2 interrupt flag is overwrite to 1
#1
ADFOV3
A/D ADINT3 Interrupt flag over run bit
It is cleared by write 1.
3
1
read-write
0
ADINT3 interrupt flag is not overwrite to 1
#0
1
ADINT3 interrupt flag is overwrite to 1
#1
ADITSSELR
ADITSSELR
A/D Interrupt Trigger Source Select Register
0x98
read-write
n
0x0
0x0
ADINT0SEL
A/D ADINT0 Interrupt Trigger Source Selection
0
5
read-write
ADINT1SEL
A/D ADINT1 Interrupt Trigger Source Selection
8
5
read-write
ADINT2SEL
A/D ADINT2 Interrupt Trigger Source Selection
16
4
read-write
ADINT3SEL
A/D ADINT3 Interrupt Trigger Source Selection
24
4
read-write
ADSMSELR
ADSMSELR
A/D SAMPLE Simultaneous Mode Select Register
0xA4
read-write
n
0x0
0x0
SIMUSEL0
A/D SAMPLEA0, SAMPLEB0 Simultaneous Sampling Mode Selection
0
1
read-write
0
SAMPLEA0, SAMPLEB0 are in single sampling mode, both SAMPLEA0 and SAMPLEB0's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA0, SAMPLEB0 are in simultaneous sampling mode, Only SAMPLEA0 can trigger both the ADC conversions of SAMPLEA0 and SAMPLEB0, SAMPLEB0.trigger select TRGSEL is ignored. if SAMPLEA0's CHSEL = 1, and SAMPLEB0's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL1
A/D SAMPLEA1, SAMPLEB1 Simultaneous Sampling Mode Selection
1
1
read-write
0
SAMPLEA1, SAMPLEB1 are in single sampling mode, both SAMPLEA1 and SAMPLEB1's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA1, SAMPLEB1 are in simultaneous sampling mode, Only SAMPLEA1 can trigger both the ADC conversions of SAMPLEA1 and SAMPLEB1, SAMPLEB1.trigger select TRGSEL is ignored. if SAMPLEA1's CHSEL = 1, and SAMPLEB1's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL2
A/D SAMPLEA2, SAMPLEB2 Simultaneous Sampling Mode Selection
2
1
read-write
0
SAMPLEA2, SAMPLEB2 are in single sampling mode, both SAMPLEA2 and SAMPLEB2's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA2, SAMPLEB2 are in simultaneous sampling mode, Only SAMPLEA2 can trigger both the ADC conversions of SAMPLEA2 and SAMPLEB2, SAMPLEB2.trigger select TRGSEL is ignored. if SAMPLEA2's CHSEL = 1, and SAMPLEB2's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL3
A/D SAMPLEA3, SAMPLEB3 Simultaneous Sampling Mode Select ion
3
1
read-write
0
SAMPLEA3, SAMPLEB3 are in single sampling mode, both SAMPLEA3 and SAMPLEB3's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA3, SAMPLEB3 are in simultaneous sampling mode, Only SAMPLEA3 can trigger both the ADC conversions of SAMPLEA3 and SAMPLEB3, SAMPLEB3.trigger select TRGSEL is ignored. if SAMPLEA3's CHSEL = 1, and SAMPLEB3's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL4
A/D SAMPLEA4, SAMPLEB4 Simultaneous Sampling Mode Select ion
4
1
read-write
0
SAMPLEA4, SAMPLEB4 are in single sampling mode, both SAMPLEA4 and SAMPLEB4's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA4, SAMPLEB4 are in simultaneous sampling mode, Only SAMPLEA4 can trigger both the ADC conversions of SAMPLEA4 and SAMPLEB4, SAMPLEB4.trigger select TRGSEL is ignored. if SAMPLEA4's CHSEL = 1, and SAMPLEB4's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL5
A/D SAMPLEA5, SAMPLEB5 Simultaneous Sampling Mode Selection
5
1
read-write
0
SAMPLEA5, SAMPLEB5 are in single sampling mode, both SAMPLEA5 and SAMPLEB5's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA5, SAMPLEB5 are in simultaneous sampling mode, Only SAMPLEA5 can trigger both the ADC conversions of SAMPLEA5 and SAMPLEB5, SAMPLEB5.trigger select TRGSEL is ignored. if SAMPLEA5's CHSEL = 1, and SAMPLEB5's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL6
A/D SAMPLEA6, SAMPLEB6 Simultaneous Sampling Mode Selection
6
1
read-write
0
SAMPLEA6, SAMPLEB6 are in single sampling mode, both SAMPLEA6 and SAMPLEB6's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA6, SAMPLEB6 are in simultaneous sampling mode, Only SAMPLEA6 can trigger both the ADC conversions of SAMPLEA6 and SAMPLEB6, SAMPLEB6.trigger select TRGSEL is ignored. if SAMPLEA6's CHSEL = 1, and SAMPLEB6's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
SIMUSEL7
A/D SAMPLEA7, SAMPLEB7 Simultaneous Sampling Mode Selection
7
1
read-write
0
SAMPLEA7, SAMPLEB7 are in single sampling mode, both SAMPLEA7 and SAMPLEB7's 3 bits of CHSEL define the ADC channels to be converted
#0
1
SAMPLEA7, SAMPLEB7 are in simultaneous sampling mode, Only SAMPLEA7 can trigger both the ADC conversions of SAMPLEA7 and SAMPLEB7, SAMPLEB7.trigger select TRGSEL is ignored. if SAMPLEA7's CHSEL = 1, SAMPLEB7's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
#1
ADSPCRA0
ADSPCRA0
A/D SAMPLEA0 Control Register
0x58
read-write
n
0x0
0x0
CHSEL
A/D SAMPLEA,B Channel Selection
0
3
read-write
TRGDLYCNT
A/D SAMPLE Start Conversion Trigger Delay Time
8
8
read-write
TRGDLYDIV
A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:
16
2
read-write
0
ADC_CLK/1
#00
1
ADC_CLK/2
#01
2
ADC_CLK/4
#10
3
ADC_CLK/16
#11
TRGSEL
A/D SAMPLE Start Conversion Trigger Source Selection
4
4
read-write
TRGTYPE
A/D SAMPLE Trigger Type Selection
18
2
read-write
0
Rising edge trigger
#00
1
Falling edge trigger
#01
2
PWM center-align trigger at center point (Only available when PWM is in Center-aligned mode)
#10
3
PWM center-align trigger at period end point (Only available when PWM is in Center-aligned mode)
#11
ADSPCRA1
ADSPCRA1
0x5C
read-write
n
0x0
0x0
ADSPCRA2
ADSPCRA2
0x60
read-write
n
0x0
0x0
ADSPCRA3
ADSPCRA3
0x64
read-write
n
0x0
0x0
ADSPCRA4
ADSPCRA4
A/D SAMPLEA4 Control Register
0x68
read-write
n
0x0
0x0
CHSEL
A/D SAMPLEA,B Channel Selection
0
3
read-write
TRGSEL
A/D SAMPLE Start Conversion Trigger Source Selection
4
3
read-write
TRGTYPE
A/D SAMPLEx Trigger Type Selection
18
1
read-write
0
Rising edge trigger
#0
1
Falling edge trigger
#1
ADSPCRA5
ADSPCRA5
0x6C
read-write
n
0x0
0x0
ADSPCRA6
ADSPCRA6
0x70
read-write
n
0x0
0x0
ADSPCRA7
ADSPCRA7
0x74
read-write
n
0x0
0x0
ADSPCRB0
ADSPCRB0
0x78
read-write
n
0x0
0x0
ADSPCRB1
ADSPCRB1
0x7C
read-write
n
0x0
0x0
ADSPCRB2
ADSPCRB2
0x80
read-write
n
0x0
0x0
ADSPCRB3
ADSPCRB3
0x84
read-write
n
0x0
0x0
ADSPCRB4
ADSPCRB4
0x88
read-write
n
0x0
0x0
ADSPCRB5
ADSPCRB5
0x8C
read-write
n
0x0
0x0
ADSPCRB6
ADSPCRB6
0x90
read-write
n
0x0
0x0
ADSPCRB7
ADSPCRB7
0x94
read-write
n
0x0
0x0
ADSPOVFR
ADSPOVFR
A/D SAMPLE Start of Conversion Over Run Flag Register
0x54
read-write
n
0x0
0x0
SPOVF15_8
A/D SAMPLEB7~0 Start Conversion Over Run Flag\nIt is cleared by writing 1.
8
8
read-write
0
No SAMPLE event over run
0
1
A new SAMPLEB event is generated while an old one event is pending
1
SPOVF7_0
A/D SAMPLEA7~0 Start Conversion Over Run Flag\nIt is cleared by writing 1.
0
8
read-write
0
No SAMPLE event over run
0
1
A new SAMPLEA event is generated while an old one event is pending
1
ADSR0
ADSR0
A/D Status Register 0
0xB0
read-only
n
0x0
0x0
OVERRUN15_8
ADDRB7~0 Over Run Flag\nIt is a mirror to OVERRUN bit in SAMPLEB A/D result data register ADDRBx
24
8
read-only
OVERRUN7_0
ADDRA7~0 Over Run Flag\nIt is a mirror to OVERRUN bit in SAMPLEA A/D result data register ADDRAx
16
8
read-only
VALID15_8
ADDRB7~0 Data Valid Flag\nIt is a mirror of VALID bit in SAMPLEB A/D result data register ADDRBx
8
8
read-only
VALID7_0
ADDRA7~0 Data Valid Flag\nIt is a mirror of VALID bit in SAMPLEA A/D result data register ADDRAx
0
8
read-only
ADSR1
ADSR1
A/D Status Register 1
0xB4
read-write
n
0x0
0x0
AADFOV
All A/D Interrupt Flag Over Run Bits Check \nThis bit will keep 1 when any ADFOVx Flag is equal to 1.
24
1
read-write
0
None of ADINT interrupt flag ADFOVx is overwritten to 1
#0
1
Any one of ADINT interrupt flag ADFOVx is overwritten to 1
#1
ADCMPF0
ADC Compare 0 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by write 1.
6
1
read-write
0
Conversion result in ADDR does not meet ADCMPR0 setting
#0
1
Conversion result in ADDR meets ADCMPR0 setting
#1
ADCMPF1
ADC Compare 1 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by write 1.
7
1
read-write
0
Conversion result in ADDR does not meet ADCMPR1 setting
#0
1
Conversion result in ADDR meets ADCMPR1 setting
#1
ADCMPO0
ADC Compare 0 Output Status Bit
The 12 bits compare0 data (ADCMPR0[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
4
1
read-write
0
Conversion result in ADDR is less than ADCMPR0[27:16] setting
#0
1
Conversion result in ADDR is great than or equal ADCMPR0[27:16] setting
#1
ADCMPO1
ADC Compare 1 Output Status Bit
The 12 bits compare1 data (ADCMPR1[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
5
1
read-write
0
Conversion result in ADDR less than ADCMPR1[27:16] setting
#0
1
Conversion result in ADDR great than or equal ADCMPR1[27:16] setting
#1
ADF0
A/D ADINT0 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
0
1
read-write
0
No ADINT0 interrupt pulse received
#0
1
ADINT0 interrupt pulse received
#1
ADF1
A/D ADINT1 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
1
1
read-write
0
no ADINT1 interrupt pulse received
#0
1
ADINT1 interrupt pulse has been received
#1
ADF2
A/D ADINT2 Interrupt Flag\nIt is cleared by writing 1. \nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed.
2
1
read-write
0
No ADINT2 interrupt pulse received
#0
1
ADINT2 interrupt pulse received
#1
ADF3
A/D ADINT3 Interrupt Flag\nIt is cleared by writing 1.\nThis bit indicates whether an A/D conversion of specific SAMPLE has been completed
3
1
read-write
0
No ADINT3 interrupt pulse received
#0
1
ADINT3 interrupt pulse received
#1
AOVERRUN
All SAMPLE A/D Result Data Register Over Run Flags Check \nThis bit will keep 1 when any OVERRUNx Flag is equal to 1.
27
1
read-write
0
None of SAMPLE data register over run flag OVERRUNx is set to 1
#0
1
Any one of SAMPLE data register over run flag OVERRUNx is set to 1
#1
ASPOVF
All A/D SAMPLE Start Conversion Over Run Flags Check\nThis bit will keep 1 when any SPOVFx Flag is equal to 1.
25
1
read-write
0
None of SAMPLE event over run flag SPOVFx is set to 1
#0
1
Any one of SAMPLE event over run flag SPOVFx is set to 1
#1
AVALID
All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check\nThis bit will keep 1 when any VALIDx Flag is equal to 1.
26
1
read-write
0
None of SAMPLE data register valid flag VALIDx is set to 1
#0
1
Any one of SAMPLE data register valid flag VALIDx is set to 1
#1
BUSYA
BUSY/IDLE\nIt is read only.
8
1
read-write
0
A/D converter A (ADCA) is in idle state
#0
1
A/D converter A (ADCA) is busy at conversion
#1
BUSYB
BUSY/IDLE\nIt is read only.
16
1
read-write
0
A/D converter B (ADCB) is in idle state
#0
1
A/D converter B (ADCB) is busy at conversion
#1
CHANNELA
Current Conversion Channel
12
3
read-write
CHANNELB
Current Conversion Channel
20
3
read-write
ADSSTR
ADSSTR
A/D SAMPLE Software Start Register
0x48
write-only
n
0x0
0x0
ADST15_8
A/D SAMPLEB7~0 Software Force to Start ADC Conversion Register
8
8
write-only
0
No effect
0
1
Cause an ADC conversion when the priority is given to SAMPLEB
1
ADST7_0
A/D SAMPLEA7~0 Software Force to Start ADC Conversion Register
0
8
write-only
0
No effect
0
1
Cause an ADC conversion when the priority is given to SAMPLEA
1
ADSTPFR
ADSTPFR
A/D SAMPLE Start of Conversion Pending Flag Register
0x4C
read-only
n
0x0
0x0
STPF15_8
A/D SAMPLEB7~0 Start Conversion Pending Flag \nThis bit remains 1 during pending state, when the respective ADC conversion is started, the STPFx bit is automatically cleared to 0.
8
8
read-only
0
No pending conversion for SAMPLEB
0
1
SAMPLEB ADC start of conversion is pending
1
STPF7_0
A/D SAMPLEA7~0 Start Conversion Pending Flag \nThis bit remains 1 during pending state, when the respective ADC conversion is started, the STPFx bit is automatically cleared to 0.
0
8
read-only
0
There is no pending conversion for SAMPLEA
0
1
SAMPLEA ADC start of conversion is pending
1
ADTCR
ADTCR
A/D Timing Control Register
0xB8
read-write
n
0x0
0x0
ADAEST
ADCA Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
0
8
read-write
ADBEST
ADCB Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
16
8
read-write
BPWM
BPWM Register Map
BPWM
0x0
0x0
0x24
registers
n
0x40
0x8
registers
n
0x50
0x4
registers
n
0x58
0x10
registers
n
0x78
0x8
registers
n
CAPENR
CAPENR
Basic PWM Capture Input Enable Register
0x78
read-write
n
0x0
0x0
CINEN0
Channel 0 Capture Input Enable
0
1
read-write
0
BPWM Channel 0 capture input path Disabled. The input of BPWM channel 0 capture function is always regarded as 0
#0
1
BPWM Channel 0 capture input path Enabled. The input of BPWM channel 0 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM20
#1
CINEN1
Channel 1 Capture Input Enable
1
1
read-write
0
BPWM Channel 1 capture input path Disabled. The input of BPWM channel 1 capture function is always regarded as 0
#0
1
BPWM Channel 1 capture input path Enabled. The input of BPWM channel 1 capture function comes from correlative multifunction pin if GPIO multi-function is set as PWM21
#1
CCR
CCR
Basic PWM Capture Control Register
0x50
read-write
n
0x0
0x0
CAPCH0EN
Channel 0 Capture Function Enable\nWhen Enabled, Capture latched the BPWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable BPWM channel 0 Interrupt.
3
1
read-write
0
Capture function on BPWM channel 0 Disabled
#0
1
Capture function on BPWM channel 0 Enabled
#1
CAPCH1EN
Channel 1 Capture Function Enable\nWhen Enabled, Capture latched the BPWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disabled, Capture does not update CRLR and CFLR, and disable PWM channel 1 Interrupt.
19
1
read-write
0
Capture function on BPWM channel 1 Disabled
#0
1
Capture function on BPWM channel 1 Enabled
#1
CAPIF0
Channel 0 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
CAPIF1
Channel 1 Capture Interrupt Indication Flag\nWrite 1 to clear this bit to 0.
20
1
read-write
CFLRI0
CFLR0 Latched Indicator Bit\nWhen BPWM input channel 0 has a falling transition, CFLR0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
7
1
read-write
CFLRI1
CFLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a falling transition, CFLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0
23
1
read-write
CFL_IE0
Channel 0 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 0 has falling transition, Capture will issue an Interrupt.
2
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CFL_IE1
Channel 1 Falling Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 1 has falling transition, Capture will issue an Interrupt.
18
1
read-write
0
Falling latch interrupt Disabled
#0
1
Falling latch interrupt Enabled
#1
CRLRI0
CRLR0 Latched Indicator Bit\nWhen BPWM input channel 0 has a rising transition, CRLR0 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to 0.
6
1
read-write
CRLRI1
CRLR1 Latched Indicator Bit\nWhen BPWM input channel 1 has a rising transition, CRLR1 was latched with the value of BPWM down-counter and this bit is set by hardware.\nSoftware can write 1 to clear this bit to0.
22
1
read-write
CRL_IE0
Channel 0 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 0 has rising transition, Capture will issue an Interrupt.
1
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
CRL_IE1
Channel 1 Rising Latch Interrupt Enable\nWhen Enabled, if Capture detects BPWM channel 1 has rising transition, Capture will issue an Interrupt.
17
1
read-write
0
Rising latch interrupt Disabled
#0
1
Rising latch interrupt Enabled
#1
INV0
Channel 0 Inverter Enable
0
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
INV1
Channel 1 Inverter Enable
16
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer
#1
CFLR0
CFLR0
Basic PWM Capture Falling Latch Register (Channel 0)
0x5C
read-only
n
0x0
0x0
CFLRx
Capture Falling Latch Register\nLatch the BPWM counter when Channel 0/1 has Falling transition.
0
16
read-only
CFLR1
CFLR1
0x64
read-write
n
0x0
0x0
CMR0
CMR0
Basic PWM Comparator Register 0
0x10
read-write
n
0x0
0x0
CMRx
PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle.
0
16
read-write
CMR1
CMR1
0x1C
read-write
n
0x0
0x0
CNR0
CNR0
Basic PWM Counter Register 0
0xC
read-write
n
0x0
0x0
CNRx
PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the PWM will work unpredictable.\nNote: When CNR value is set to 0, PWM output is always high.
0
16
read-write
CNR1
CNR1
0x18
read-write
n
0x0
0x0
CRLR0
CRLR0
Basic PWM Capture Rising Latch Register (Channel 0)
0x58
read-only
n
0x0
0x0
CRLRx
Capture Rising Latch Register\nLatch the BPWM counter when Channel 0/1 has rising transition.
0
16
read-only
CRLR1
CRLR1
0x60
read-write
n
0x0
0x0
CSR
CSR
Basic PWM Clock Source Divider Select Register
0x4
read-write
n
0x0
0x0
CSR0
PWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR1)
0
3
read-write
CSR1
PWM Timer 1 Clock Source Divider Selection
4
3
read-write
PCR
PCR
Basic PWM Control Register
0x8
read-write
n
0x0
0x0
CH0EN
PWM-Timer 0 Enable
0
1
read-write
0
The corresponding PWM-Timer stops running
#0
1
The corresponding PWM-Timer starts running
#1
CH0INV
PWM-Timer 0 Output Inverter Enable
2
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH0MOD
PWM-Timer 0 Auto-reload/One-Shot Mode\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
3
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH0PINV
PWM-Timer 0 Output Polar Inverse Enable
1
1
read-write
0
PWM0 output polar inverse Disabled
#0
1
PWM0 output polar inverse Enabled
#1
CH1EN
PWM-Timer 1 Enable
8
1
read-write
0
Corresponding PWM-Timer Stopped
#0
1
Corresponding PWM-Timer Start Running
#1
CH1INV
PWM-Timer 1 Output Inverter Enable
10
1
read-write
0
Inverter Disabled
#0
1
Inverter Enabled
#1
CH1MOD
PWM-Timer 1 Auto-reload/One-Shot Mode\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
11
1
read-write
0
One-shot mode
#0
1
Auto-reload mode
#1
CH1PINV
PWM-Timer 1 Output Polar Inverse Enable
9
1
read-write
0
PWM1 output polar inverse Disabled
#0
1
PWM1 output polar inverse Enabled
#1
DZEN01
Dead-zone 0 Generator Enable\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair.
4
1
read-write
0
Disabled
#0
1
Enabled
#1
PWM01TYPE
PWM01 Aligned Type Selection Bit
30
1
read-write
0
Edge-aligned type
#0
1
Center-aligned type
#1
PDR0
PDR0
Basic PWM Data Register 0
0x14
read-only
n
0x0
0x0
PDRx
PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
0
16
read-only
PDR1
PDR1
0x20
read-write
n
0x0
0x0
PIER
PIER
Basic PWM Interrupt Enable Register
0x40
read-write
n
0x0
0x0
BPWMDIE0
BPWM channel 0 Duty Interrupt Enable
8
1
read-write
0
Disabled
#0
1
Enabled
#1
BPWMDIE1
BPWM channel 1 Duty Interrupt Enable
9
1
read-write
0
Disabled
#0
1
Enabled
#1
BPWMIE0
BPWM channel 0 Period Interrupt Enable
0
1
read-write
0
Disabled
#0
1
Enabled
#1
BPWMIE1
BPWM channel 1 Period Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
INTTYPE
BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only.
16
1
read-write
0
BPWMIFn will be set if BPWM counter underflow
#0
1
BPWMIFn will be set if BPWM counter matches CNRn register
#1
PIIR
PIIR
Basic PWM Interrupt Indication Register
0x44
read-write
n
0x0
0x0
BPWMDIF0
BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 BPWM counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
8
1
read-write
BPWMDIF1
BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 BPWM counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
9
1
read-write
BPWMIF0
BPWM channel 0 Period Interrupt Status\nThis bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register), software can write 1 to clear this bit to 0.
0
1
read-write
BPWMIF1
BPWM channel 1 Period Interrupt Status\nThis bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register), software can write 1 to clear this bit to 0.
1
1
read-write
POE
POE
Basic PWM Output Enable
0x7C
read-write
n
0x0
0x0
POE0
Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
0
1
read-write
0
BPWM channel 0 output to pin Disabled
#0
1
BPWM channel 0 output to pin Enabled
#1
POE1
Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function
1
1
read-write
0
BPWM channel 1 output to pin Disabled
#0
1
BPWM channel 1 output to pin Enabled
#1
PPR
PPR
Basic PWM Pre-scalar Register
0x0
read-write
n
0x0
0x0
CP01
Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
0
8
read-write
DZI01
Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.
16
8
read-write
CAN0
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
-1
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment before the sample Point Minus Sync_seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
-1
read-write
n
0x0
0x0
CCE
Configuration Change Enable
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME CAN_BRP) allowed. (while Init bit =1)
#1
DAR
Disable Automatic Re-transmission
5
1
read-write
0
Automatic Retransmission of disturbed messages Enabled
#0
1
Automatic Retransmission Disabled
#1
EIE
Error Interrupt Enable
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization
0
1
read-write
0
Normal operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable
7
1
read-write
0
Normal operation
#0
1
Test mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IF1 Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame')
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IF1 Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\nOn TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame')
0
13
read-write
MsgVal
Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register. This bit must also be reset before the identifier Id28-0, the control bits Xtd, Dir, or the Data Length Code DLC3-0 are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier
14
1
read-write
0
The 11-bit ('standard') Identifier will be used for this Message Object
#0
1
The 29-bit ('extended') Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IF1 Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir + Xtd + MsgVal to Message Object\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit
3
1
read-write
0
IntPnd bit remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits
4
1
read-write
0
Control Bits unchanged\nControl Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IF1 Command Request Register
0x20
-1
read-write
n
0x0
0x0
Busy
Busy Flag
15
1
read-write
0
Read/write action has been finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IF1 Data A1 Register
0x3C
read-write
n
0x0
0x0
Data0
Data byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IF1 Data A2 Register
0x40
read-write
n
0x0
0x0
Data2
Data byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IF1 Data B1 Register
0x44
read-write
n
0x0
0x0
Data4
Data byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IF1 Data B2 Register
0x48
read-write
n
0x0
0x0
Data6
Data byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IF1 Mask 1 Register
0x28
-1
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IF1 Mask 2 Register
0x2C
-1
read-write
n
0x0
0x0
MDir
Mask Message Direction
14
1
read-write
0
The message direction bit (Dir) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18. For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IF1 Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData 0: 1st data byte of a CAN Data Frame\nData 1: 2nd data byte of a CAN Data Frame\nData 2: 3rd data byte of a CAN Data Frame\nData 3: 4th data byte of a CAN Data Frame\nData 4: 5th data byte of a CAN Data Frame\nData 5: 6th data byte of a CAN Data Frame\nData 6: 7th data byte of a CAN Data Frame\nData 7 : 8th data byte of a CAN Data Frame\nNote: The Data0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable
9
1
read-write
0
At the reception of a Remote Frame, TxRqst is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable
10
1
read-write
0
IntPnd will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable
11
1
read-write
0
IntPnd will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates the source of the interrupt. Refer to Error! Reference source not found.)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit. The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd
Interrupt Pending Bits 16-1 (of all Message Objects)
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd
Interrupt Pending Bits 32-17(of all Message Objects)
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal
Message Valid Bits 16-1 (of all Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal
Message Valid Bits 32-17 (of all Message Objects) (Read only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData
New Data Bits 16-1 (of all Message Objects)
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData
New Data Bits 32-17 (of all Message Objects)
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-off Status (Read Only)
7
1
read-only
0
CAN module is not in bus-off state
#0
1
CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)
5
1
read-only
0
CAN Core is error active
#0
1
CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. Error! Reference source not found. describes the error code.
0
3
read-write
RxOK
Received a Message Successfully
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted a Message Successfully
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register
0x14
read-write
n
0x0
0x0
Basic
Basic Mode
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode
4
1
read-write
0
Loop Back Mode Disabled
#0
1
Loop Back Mode Enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors the actual value of CAN_RXD Pin (Read Only)
7
1
read-only
0
The CAN bus is dominant (CAN_RXD = '0')
#0
1
The CAN bus is recessive (CAN_RXD = '1')
#1
Silent
Silent Mode
3
1
read-write
0
Normal operation
#0
1
The module is in Silent mode
#1
Tx
Tx[1:0]: Control of CAN_TXD pin
5
2
read-write
0
Reset value, CAN_TXD is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TXD pin
#01
2
CAN_TXD pin drives a dominant ('0') value
#10
3
CAN_TXD pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst
Transmission Request Bits 16-1 (of all Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not done yet
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst
Transmission Request Bits 32-17 (of all Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not done yet
1
CAN_WU_EN
CAN_WU_EN
Wake-Up Enable Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake Up Enable\nNote: User can wake up system when there is a falling edge in the CAN_RXD pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-Up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake Up Status \nNote: The bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CAN1
CAN Register Map
CAN
0x0
0x0
0x1C
registers
n
0x100
0x8
registers
n
0x120
0x8
registers
n
0x140
0x8
registers
n
0x160
0x10
registers
n
0x20
0x2C
registers
n
0x80
0x2C
registers
n
CAN_BRPE
CAN_BRPE
Baud Rate Prescaler Extension Register
0x18
read-write
n
0x0
0x0
BRPE
BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
0
4
read-write
CAN_BTIME
CAN_BTIME
Bit Timing Register
0xC
-1
read-write
n
0x0
0x0
BRP
Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
0
6
read-write
SJW
(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
6
2
read-write
TSeg1
Time Segment before the sample Point Minus Sync_seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by hardware of this value is such that one more than the value programmed is used.
8
4
read-write
TSeg2
Time Segment After sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by hardware of this value is such that one more than the value programmed here is used.
12
3
read-write
CAN_CON
CAN_CON
Control Register
0x0
-1
read-write
n
0x0
0x0
CCE
Configuration Change Enable
6
1
read-write
0
No write access to the Bit Timing Register
#0
1
Write access to the Bit Timing Register (CAN_BTIME CAN_BRP) allowed. (while Init bit =1)
#1
DAR
Disable Automatic Re-transmission
5
1
read-write
0
Automatic Retransmission of disturbed messages Enabled
#0
1
Automatic Retransmission Disabled
#1
EIE
Error Interrupt Enable
3
1
read-write
0
Disabled - No Error Status Interrupt will be generated
#0
1
Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt
#1
IE
Module Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
Init
Init Initialization
0
1
read-write
0
Normal operation
#0
1
Initialization is started
#1
SIE
Status Change Interrupt Enable
2
1
read-write
0
Disabled - No Status Change Interrupt will be generated
#0
1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
#1
Test
Test Mode Enable
7
1
read-write
0
Normal operation
#0
1
Test mode
#1
CAN_ERR
CAN_ERR
Error Counter Register
0x8
read-only
n
0x0
0x0
REC
Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
8
7
read-only
RP
Receive Error Passive
15
1
read-only
0
The Receive Error Counter is below the error passive level
#0
1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
#1
TEC
Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
0
8
read-only
CAN_IF1_ARB1
CAN_IF1_ARB1
IF1 Arbitration 1 Register
0x30
read-write
n
0x0
0x0
ID
Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame')
0
16
read-write
CAN_IF1_ARB2
CAN_IF1_ARB2
IF1 Arbitration 2 Register
0x34
read-write
n
0x0
0x0
Dir
Message Direction\nOn TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
13
1
read-write
0
Direction is receive
#0
1
Direction is transmit
#1
ID
Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ('Extended Frame').\nID28 - ID18, 11-bit Identifier ('Standard Frame')
0
13
read-write
MsgVal
Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register. This bit must also be reset before the identifier Id28-0, the control bits Xtd, Dir, or the Data Length Code DLC3-0 are modified, or if the Messages Object is no longer required.
15
1
read-write
0
The Message Object is ignored by the Message Handler
#0
1
The Message Object is configured and should be considered by the Message Handler
#1
Xtd
Extended Identifier
14
1
read-write
0
The 11-bit ('standard') Identifier will be used for this Message Object
#0
1
The 29-bit ('extended') Identifier will be used for this Message Object
#1
CAN_IF1_CMASK
CAN_IF1_CMASK
IF1 Command Mask Register
0x24
read-write
n
0x0
0x0
Arb
Access Arbitration Bits
5
1
read-write
0
Arbitration bits unchanged
#0
1
Transfer Identifier + Dir + Xtd + MsgVal to Message Object\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
#1
ClrIntPnd
Clear Interrupt Pending Bit
3
1
read-write
0
IntPnd bit remains unchanged
#0
1
Clear IntPnd bit in the Message Object
#1
Control
Control Access Control Bits
4
1
read-write
0
Control Bits unchanged\nControl Bits unchanged
#0
1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
#1
DAT_A
Access Data Bytes [3:0]
1
1
read-write
0
Data Bytes [3:0] unchanged
#0
1
Transfer Data Bytes [3:0] to Message Object\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
#1
DAT_B
Access Data Bytes [7:4]
0
1
read-write
0
Data Bytes [7:4] unchanged
#0
1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
#1
Mask
Access Mask Bits
6
1
read-write
0
Mask bits unchanged
#0
1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
#1
TxRqst_NewDat
Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
2
1
read-write
0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#0
1
Set TxRqst bit.\nClear NewDat bit in the Message Object
#1
WR_RD
Write / Read
7
1
read-write
0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#0
1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
#1
CAN_IF1_CREQ
CAN_IF1_CREQ
IF1 Command Request Register
0x20
-1
read-write
n
0x0
0x0
Busy
Busy Flag
15
1
read-write
0
Read/write action has been finished
#0
1
Writing to the IFn Command Request Register is in progress. This bit can only be read by software
#1
MessageNumber
Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
0
6
read-write
CAN_IF1_DAT_A1
CAN_IF1_DAT_A1
IF1 Data A1 Register
0x3C
read-write
n
0x0
0x0
Data0
Data byte 0\n1st data byte of a CAN Data Frame
0
8
read-write
Data1
Data byte 1\n2nd data byte of a CAN Data Frame
8
8
read-write
CAN_IF1_DAT_A2
CAN_IF1_DAT_A2
IF1 Data A2 Register
0x40
read-write
n
0x0
0x0
Data2
Data byte 2\n3rd data byte of CAN Data Frame
0
8
read-write
Data3
Data byte 3\n4th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B1
CAN_IF1_DAT_B1
IF1 Data B1 Register
0x44
read-write
n
0x0
0x0
Data4
Data byte 4\n5th data byte of CAN Data Frame
0
8
read-write
Data5
Data byte 5\n6th data byte of CAN Data Frame
8
8
read-write
CAN_IF1_DAT_B2
CAN_IF1_DAT_B2
IF1 Data B2 Register
0x48
read-write
n
0x0
0x0
Data6
Data byte 6\n7th data byte of CAN Data Frame.
0
8
read-write
Data7
Data byte 7\n8th data byte of CAN Data Frame.
8
8
read-write
CAN_IF1_MASK1
CAN_IF1_MASK1
IF1 Mask 1 Register
0x28
-1
read-write
n
0x0
0x0
Msk
Identifier Mask 15-0
0
16
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
CAN_IF1_MASK2
CAN_IF1_MASK2
IF1 Mask 2 Register
0x2C
-1
read-write
n
0x0
0x0
MDir
Mask Message Direction
14
1
read-write
0
The message direction bit (Dir) has no effect on the acceptance filtering
#0
1
The message direction bit (Dir) is used for acceptance filtering
#1
Msk
Identifier Mask 28-16
0
13
read-write
0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
0
1
The corresponding identifier bit is used for acceptance filtering
1
MXtd
Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18. For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 are considered.
15
1
read-write
0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#0
1
The extended identifier bit (IDE) is used for acceptance filtering
#1
CAN_IF1_MCON
CAN_IF1_MCON
IF1 Message Control Register
0x38
read-write
n
0x0
0x0
DLC
Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData 0: 1st data byte of a CAN Data Frame\nData 1: 2nd data byte of a CAN Data Frame\nData 2: 3rd data byte of a CAN Data Frame\nData 3: 4th data byte of a CAN Data Frame\nData 4: 5th data byte of a CAN Data Frame\nData 5: 6th data byte of a CAN Data Frame\nData 6: 7th data byte of a CAN Data Frame\nData 7 : 8th data byte of a CAN Data Frame\nNote: The Data0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
0
4
read-write
EoB
End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
7
1
read-write
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#0
1
Single Message Object or last Message Object of a FIFO Buffer
#1
IntPnd
Interrupt Pending
13
1
read-write
0
This message object is not the source of an interrupt
#0
1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
#1
MsgLst
None
14
1
read-write
0
No message lost since last time this bit was reset by the CPU
#0
1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
#1
NewDat
New Data
15
1
read-write
0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
#1
RmtEn
Remote Enable
9
1
read-write
0
At the reception of a Remote Frame, TxRqst is left unchanged
#0
1
At the reception of a Remote Frame, TxRqst is set
#1
RxIE
Receive Interrupt Enable
10
1
read-write
0
IntPnd will be left unchanged after a successful reception of a frame
#0
1
IntPnd will be set after a successful reception of a frame
#1
TxIE
Transmit Interrupt Enable
11
1
read-write
0
IntPnd will be left unchanged after the successful transmission of a frame
#0
1
IntPnd will be set after a successful transmission of a frame
#1
TxRqst
Transmit Request
8
1
read-write
0
This Message Object is not waiting for transmission
#0
1
The transmission of this Message Object is requested and is not yet done
#1
UMask
Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal is set to one.
12
1
read-write
0
Mask ignored
#0
1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
#1
CAN_IF2_ARB1
CAN_IF2_ARB1
0x90
read-write
n
0x0
0x0
CAN_IF2_ARB2
CAN_IF2_ARB2
0x94
read-write
n
0x0
0x0
CAN_IF2_CMASK
CAN_IF2_CMASK
0x84
read-write
n
0x0
0x0
CAN_IF2_CREQ
CAN_IF2_CREQ
0x80
read-write
n
0x0
0x0
CAN_IF2_DAT_A1
CAN_IF2_DAT_A1
0x9C
read-write
n
0x0
0x0
CAN_IF2_DAT_A2
CAN_IF2_DAT_A2
0xA0
read-write
n
0x0
0x0
CAN_IF2_DAT_B1
CAN_IF2_DAT_B1
0xA4
read-write
n
0x0
0x0
CAN_IF2_DAT_B2
CAN_IF2_DAT_B2
0xA8
read-write
n
0x0
0x0
CAN_IF2_MASK1
CAN_IF2_MASK1
0x88
read-write
n
0x0
0x0
CAN_IF2_MASK2
CAN_IF2_MASK2
0x8C
read-write
n
0x0
0x0
CAN_IF2_MCON
CAN_IF2_MCON
0x98
read-write
n
0x0
0x0
CAN_IIDR
CAN_IIDR
Interrupt Identifier Register
0x10
read-only
n
0x0
0x0
IntId
Interrupt Identifier (Indicates the source of the interrupt. Refer to Error! Reference source not found.)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit. The Status Interrupt is cleared by reading the Status Register.
0
16
read-only
CAN_IPND1
CAN_IPND1
Interrupt Pending Register 1
0x140
read-only
n
0x0
0x0
IntPnd
Interrupt Pending Bits 16-1 (of all Message Objects)
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_IPND2
CAN_IPND2
Interrupt Pending Register 2
0x144
read-only
n
0x0
0x0
IntPnd
Interrupt Pending Bits 32-17(of all Message Objects)
0
16
read-only
0
This message object is not the source of an interrupt
0
1
This message object is the source of an interrupt
1
CAN_MVLD1
CAN_MVLD1
Message Valid Register 1
0x160
read-only
n
0x0
0x0
MsgVal
Message Valid Bits 16-1 (of all Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_MVLD2
CAN_MVLD2
Message Valid Register 2
0x164
read-only
n
0x0
0x0
MsgVal
Message Valid Bits 32-17 (of all Message Objects) (Read only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
0
16
read-only
0
This Message Object is ignored by the Message Handler
0
1
This Message Object is configured and should be considered by the Message Handler
1
CAN_NDAT1
CAN_NDAT1
New Data Register 1
0x120
read-only
n
0x0
0x0
NewData
New Data Bits 16-1 (of all Message Objects)
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_NDAT2
CAN_NDAT2
New Data Register 2
0x124
read-only
n
0x0
0x0
NewData
New Data Bits 32-17 (of all Message Objects)
0
16
read-only
0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
0
1
The Message Handler or the application software has written new data into the data portion of this Message Object
1
CAN_STATUS
CAN_STATUS
Status Register
0x4
read-write
n
0x0
0x0
BOff
Bus-off Status (Read Only)
7
1
read-only
0
CAN module is not in bus-off state
#0
1
CAN module is in bus-off state
#1
EPass
Error Passive (Read Only)
5
1
read-only
0
CAN Core is error active
#0
1
CAN Core is in the error passive state as defined in the CAN Specification
#1
EWarn
Error Warning Status (Read Only)
6
1
read-only
0
Both error counters are below the error warning limit of 96
#0
1
At least one of the error counters in the EML has reached the error warning limit of 96
#1
LEC
Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. Error! Reference source not found. describes the error code.
0
3
read-write
RxOK
Received a Message Successfully
4
1
read-write
0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#0
1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
#1
TxOK
Transmitted a Message Successfully
3
1
read-write
0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#0
1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
#1
CAN_TEST
CAN_TEST
Test Register
0x14
read-write
n
0x0
0x0
Basic
Basic Mode
2
1
read-write
0
Basic Mode disabled
#0
1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
#1
LBack
Loop Back Mode
4
1
read-write
0
Loop Back Mode Disabled
#0
1
Loop Back Mode Enabled
#1
Res
Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
0
2
read-write
Rx
Monitors the actual value of CAN_RXD Pin (Read Only)
7
1
read-only
0
The CAN bus is dominant (CAN_RXD = '0')
#0
1
The CAN bus is recessive (CAN_RXD = '1')
#1
Silent
Silent Mode
3
1
read-write
0
Normal operation
#0
1
The module is in Silent mode
#1
Tx
Tx[1:0]: Control of CAN_TXD pin
5
2
read-write
0
Reset value, CAN_TXD is controlled by the CAN Core
#00
1
Sample Point can be monitored at CAN_TXD pin
#01
2
CAN_TXD pin drives a dominant ('0') value
#10
3
CAN_TXD pin drives a recessive ('1') value
#11
CAN_TXREQ1
CAN_TXREQ1
Transmission Request Register 1
0x100
read-only
n
0x0
0x0
TxRqst
Transmission Request Bits 16-1 (of all Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not done yet
1
CAN_TXREQ2
CAN_TXREQ2
Transmission Request Register 2
0x104
read-only
n
0x0
0x0
TxRqst
Transmission Request Bits 32-17 (of all Message Objects)\nThese bits are read only.
0
16
read-only
0
This Message Object is not waiting for transmission
0
1
The transmission of this Message Object is requested and is not done yet
1
CAN_WU_EN
CAN_WU_EN
Wake-Up Enable Register
0x168
read-write
n
0x0
0x0
WAKUP_EN
Wake Up Enable\nNote: User can wake up system when there is a falling edge in the CAN_RXD pin..
0
1
read-write
0
The wake-up function Disabled
#0
1
The wake-up function Enabled
#1
CAN_WU_STATUS
CAN_WU_STATUS
Wake-Up Status Register
0x16C
read-write
n
0x0
0x0
WAKUP_STS
Wake Up Status \nNote: The bit can be cleared by writing '0'.
0
1
read-write
0
No wake-up event occurred
#0
1
Wake-up event occurred
#1
CAP0
CAP Register Map
CAP
0x0
0x0
0x20
registers
n
CAP_CNT
CAP_CNT
Input Capture Counter (24-bit up counter)
0x0
read-write
n
0x0
0x0
CAP_CNT
Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
0
24
read-write
CAP_CNTCMP
CAP_CNTCMP
Input Capture Counter Compare Register
0x10
read-write
n
0x0
0x0
CAP_CNTCMP
Input Capture Counter Compare Register
0
24
read-write
CAP_CTR0
CAP_CTR0
Input Capture Control Register 0
0x14
read-write
n
0x0
0x0
CAPCMP_IEN
Enable CAPCMPF Trigger Input Capture Interrupt
21
1
read-write
0
Disabling flag CAPCMPF can trigger Input Capture interrupt
#0
1
Enabling flag CAPCMPF can trigger Input Capture interrupt
#1
CAPNF_DIS
Disable Input Capture Noise Filter
3
1
read-write
0
Noise filter of Input Capture Enabled
#0
1
The noise filter of Input Capture Disabled
#1
CAPOV_IEN
Enable CAPOVF Trigger Input Capture Interrupt
20
1
read-write
0
Disabling flag OVUNF can trigger Input Capture interrupt
#0
1
Enabling flag OVUNF can trigger Input Capture interrupt
#1
CAPSEL0
CAP0 Input Source Selection Bit
8
2
read-write
0
CAP0 input is from port pin IC0
#00
1
CAP0 input is from signal CPO0 (Analog comparator 0 output)
#01
2
CAP0 input is from signal CHA of QEI controller unit x
#10
3
CAP0 input is from signal OPDO0 (OP0 digital output)
#11
CAPSEL1
CAP1 Input Source Selection Bit
10
2
read-write
0
CAP1 input is from port pin IC1
#00
1
CAP1 input is from signal CPO1 (Analog comparator 1 output)
#01
2
CAP1 input is from signal CHB of QEI controller unit x
#10
3
CAP1 input is from signal OPDO1 (OP1 digital output)
#11
CAPSEL2
CAP2 Input Source Selection Bit
12
2
read-write
0
CAP2 input is from port pin IC2
#00
1
CAP2 input is from signal CPO2 (Analog comparator 2 output)
#01
2
CAP2 input is from signal CHX of QEI controller unit x
#10
3
CAP2 input is from signal ADCMPOx (ADC compare output x)
#11
CAPTF0_IEN
Enable Input Capture Channel 0 Interrupt
16
1
read-write
0
Disabling flag CAPTF0 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF0 can trigger Input Capture interrupt
#1
CAPTF1_IEN
Enable Input Capture Channel 1 Interrupt
17
1
read-write
0
Disabling flag CAPTF1 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF1 can trigger Input Capture interrupt
#1
CAPTF2_IEN
Enable Input Capture Channel 2 Interrupt
18
1
read-write
0
Disabling flag CAPTF2 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF2 can trigger Input Capture interrupt
#1
CAP_EN
Input Capture Timer/Counter Enable Bit
29
1
read-write
0
Input Capture function Disabled
#0
1
Input Capture function Enabled
#1
CMPCLR
Input Capture Counter Clear by Compare-match Control Bit
25
1
read-write
0
Compare-match event (CAMCMPF) can clear capture counter (CAP_CNT) Disabled
#0
1
Compare-match event (CAMCMPF) can clear capture counter (CAP_CNT) Enabled
#1
CMP_EN
The Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting CAP_CNT with the compare register CAP_CNTCMP, if CAP_CNT value reaches CAP_CNTCMP, the flag CAPCMPF will be set.
28
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CPTCLR
Input Capture Counter Clear by Capture Events Control Bit\nIf this bit is set to 1, the capture counter (CAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.
26
1
read-write
0
Capture events (CAPTF0~3) can clear capture counter (CAP_CNT) Disabled
#0
1
Capture events (CAPTF0~3) can clear capture counter (CAP_CNT) Enabled
#1
CPTST
Input Capture Counter Start Bit\nSetting this bit to 1, the capture counter (CAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
24
1
read-write
0
CAP_CNT stop counting
#0
1
CAP_CNT starts up-counting
#1
IC0_EN
Enable Port Pin IC0 Input to Input Capture Unit
4
1
read-write
0
IC0 input to Input Capture Unit Disabled
#0
1
IC0 input to Input Capture Unit Enabled
#1
IC1_EN
Enable Port Pin IC1 Input to Input Capture Unit
5
1
read-write
0
IC1 input to Input Capture Unit Disabled
#0
1
IC1 input to Input Capture Unit Enabled
#1
IC2_EN
Enable Port Pin IC2 Input to Input Capture Unit
6
1
read-write
0
IC2 input to Input Capture Unit Disabled
#0
1
IC2 input to Input Capture Unit Enabled
#1
NFCLK_S
Noise Filter Clock Pre-divided Selection
0
2
read-write
RLD_EN
The Reload Function Enable Bit\nSetting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload CAP_CNTCMP into CAP_CNT.
27
1
read-write
0
Reload function Disabled
#0
1
Reload function Enabled
#1
CAP_CTR1
CAP_CTR1
Input Capture Control Register 1
0x18
read-write
n
0x0
0x0
CAPCNT_SRC
Capture Timer/Counter Clock Source Select
16
2
read-write
CAPDIV
Capture Timer Clock Divide Selection
12
2
read-write
CAPEDG0
Channel 0 Captured Edge Selection
0
2
read-write
CAPEDG1
Channel 1 Captured Edge Selection
2
2
read-write
CAPEDG2
Channel 2 Captured Edge Selection
4
2
read-write
CPRLD_S
CAPCNT Reload Trigger Source Selection
8
3
read-write
CAP_HLD0
CAP_HLD0
Input Capture Counter Hold Register 0
0x4
read-write
n
0x0
0x0
CAP_HLD
Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the CAPCNT value is latched into the corresponding holding register. Each input channel has itself holding register named by CAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
0
24
read-write
CAP_HLD1
CAP_HLD1
0x8
read-write
n
0x0
0x0
CAP_HLD2
CAP_HLD2
0xC
read-write
n
0x0
0x0
CAP_STS
CAP_STS
Input Capture Status Register
0x1C
read-write
n
0x0
0x0
CAPCMPF
Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (CAP_CNT) up counts and reach to the CAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
4
1
read-write
0
CAP_CNT does not match with CAP_CNTCMP value
#0
1
CAP_CNT counts to the same as CAP_CNTCMP value
#1
CAPOVF
Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (CAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to itself through software.
5
1
read-write
0
No overflow occurs in CAP_CNT
#0
1
CAP_CNT overflows
#1
CAPTF0
Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
0
1
read-write
0
No valid edge change is detected at CAP0 input
#0
1
A valid edge change is detected at CAP0 input
#1
CAPTF1
Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
1
1
read-write
0
No valid edge change is detected at CAP1 input
#0
1
A valid edge change is detected at CAP1 input
#1
CAPTF2
Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
2
1
read-write
0
No valid edge change is detected at CAP2 input
#0
1
A valid edge change is detected at CAP2 input
#1
CAP1
CAP Register Map
CAP
0x0
0x0
0x20
registers
n
CAP_CNT
CAP_CNT
Input Capture Counter (24-bit up counter)
0x0
read-write
n
0x0
0x0
CAP_CNT
Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
0
24
read-write
CAP_CNTCMP
CAP_CNTCMP
Input Capture Counter Compare Register
0x10
read-write
n
0x0
0x0
CAP_CNTCMP
Input Capture Counter Compare Register
0
24
read-write
CAP_CTR0
CAP_CTR0
Input Capture Control Register 0
0x14
read-write
n
0x0
0x0
CAPCMP_IEN
Enable CAPCMPF Trigger Input Capture Interrupt
21
1
read-write
0
Disabling flag CAPCMPF can trigger Input Capture interrupt
#0
1
Enabling flag CAPCMPF can trigger Input Capture interrupt
#1
CAPNF_DIS
Disable Input Capture Noise Filter
3
1
read-write
0
Noise filter of Input Capture Enabled
#0
1
The noise filter of Input Capture Disabled
#1
CAPOV_IEN
Enable CAPOVF Trigger Input Capture Interrupt
20
1
read-write
0
Disabling flag OVUNF can trigger Input Capture interrupt
#0
1
Enabling flag OVUNF can trigger Input Capture interrupt
#1
CAPSEL0
CAP0 Input Source Selection Bit
8
2
read-write
0
CAP0 input is from port pin IC0
#00
1
CAP0 input is from signal CPO0 (Analog comparator 0 output)
#01
2
CAP0 input is from signal CHA of QEI controller unit x
#10
3
CAP0 input is from signal OPDO0 (OP0 digital output)
#11
CAPSEL1
CAP1 Input Source Selection Bit
10
2
read-write
0
CAP1 input is from port pin IC1
#00
1
CAP1 input is from signal CPO1 (Analog comparator 1 output)
#01
2
CAP1 input is from signal CHB of QEI controller unit x
#10
3
CAP1 input is from signal OPDO1 (OP1 digital output)
#11
CAPSEL2
CAP2 Input Source Selection Bit
12
2
read-write
0
CAP2 input is from port pin IC2
#00
1
CAP2 input is from signal CPO2 (Analog comparator 2 output)
#01
2
CAP2 input is from signal CHX of QEI controller unit x
#10
3
CAP2 input is from signal ADCMPOx (ADC compare output x)
#11
CAPTF0_IEN
Enable Input Capture Channel 0 Interrupt
16
1
read-write
0
Disabling flag CAPTF0 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF0 can trigger Input Capture interrupt
#1
CAPTF1_IEN
Enable Input Capture Channel 1 Interrupt
17
1
read-write
0
Disabling flag CAPTF1 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF1 can trigger Input Capture interrupt
#1
CAPTF2_IEN
Enable Input Capture Channel 2 Interrupt
18
1
read-write
0
Disabling flag CAPTF2 can trigger Input Capture interrupt
#0
1
Enabling flag CAPTF2 can trigger Input Capture interrupt
#1
CAP_EN
Input Capture Timer/Counter Enable Bit
29
1
read-write
0
Input Capture function Disabled
#0
1
Input Capture function Enabled
#1
CMPCLR
Input Capture Counter Clear by Compare-match Control Bit
25
1
read-write
0
Compare-match event (CAMCMPF) can clear capture counter (CAP_CNT) Disabled
#0
1
Compare-match event (CAMCMPF) can clear capture counter (CAP_CNT) Enabled
#1
CMP_EN
The Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting CAP_CNT with the compare register CAP_CNTCMP, if CAP_CNT value reaches CAP_CNTCMP, the flag CAPCMPF will be set.
28
1
read-write
0
Compare function Disabled
#0
1
Compare function Enabled
#1
CPTCLR
Input Capture Counter Clear by Capture Events Control Bit\nIf this bit is set to 1, the capture counter (CAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.
26
1
read-write
0
Capture events (CAPTF0~3) can clear capture counter (CAP_CNT) Disabled
#0
1
Capture events (CAPTF0~3) can clear capture counter (CAP_CNT) Enabled
#1
CPTST
Input Capture Counter Start Bit\nSetting this bit to 1, the capture counter (CAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
24
1
read-write
0
CAP_CNT stop counting
#0
1
CAP_CNT starts up-counting
#1
IC0_EN
Enable Port Pin IC0 Input to Input Capture Unit
4
1
read-write
0
IC0 input to Input Capture Unit Disabled
#0
1
IC0 input to Input Capture Unit Enabled
#1
IC1_EN
Enable Port Pin IC1 Input to Input Capture Unit
5
1
read-write
0
IC1 input to Input Capture Unit Disabled
#0
1
IC1 input to Input Capture Unit Enabled
#1
IC2_EN
Enable Port Pin IC2 Input to Input Capture Unit
6
1
read-write
0
IC2 input to Input Capture Unit Disabled
#0
1
IC2 input to Input Capture Unit Enabled
#1
NFCLK_S
Noise Filter Clock Pre-divided Selection
0
2
read-write
RLD_EN
The Reload Function Enable Bit\nSetting this bit to enable reload function. If the reload control is enabled, an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload CAP_CNTCMP into CAP_CNT.
27
1
read-write
0
Reload function Disabled
#0
1
Reload function Enabled
#1
CAP_CTR1
CAP_CTR1
Input Capture Control Register 1
0x18
read-write
n
0x0
0x0
CAPCNT_SRC
Capture Timer/Counter Clock Source Select
16
2
read-write
CAPDIV
Capture Timer Clock Divide Selection
12
2
read-write
CAPEDG0
Channel 0 Captured Edge Selection
0
2
read-write
CAPEDG1
Channel 1 Captured Edge Selection
2
2
read-write
CAPEDG2
Channel 2 Captured Edge Selection
4
2
read-write
CPRLD_S
CAPCNT Reload Trigger Source Selection
8
3
read-write
CAP_HLD0
CAP_HLD0
Input Capture Counter Hold Register 0
0x4
read-write
n
0x0
0x0
CAP_HLD
Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the CAPCNT value is latched into the corresponding holding register. Each input channel has itself holding register named by CAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
0
24
read-write
CAP_HLD1
CAP_HLD1
0x8
read-write
n
0x0
0x0
CAP_HLD2
CAP_HLD2
0xC
read-write
n
0x0
0x0
CAP_STS
CAP_STS
Input Capture Status Register
0x1C
read-write
n
0x0
0x0
CAPCMPF
Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (CAP_CNT) up counts and reach to the CAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
4
1
read-write
0
CAP_CNT does not match with CAP_CNTCMP value
#0
1
CAP_CNT counts to the same as CAP_CNTCMP value
#1
CAPOVF
Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (CAP_CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to itself through software.
5
1
read-write
0
No overflow occurs in CAP_CNT
#0
1
CAP_CNT overflows
#1
CAPTF0
Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
0
1
read-write
0
No valid edge change is detected at CAP0 input
#0
1
A valid edge change is detected at CAP0 input
#1
CAPTF1
Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
1
1
read-write
0
No valid edge change is detected at CAP1 input
#0
1
A valid edge change is detected at CAP1 input
#1
CAPTF2
Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to itself through software.
2
1
read-write
0
No valid edge change is detected at CAP2 input
#0
1
A valid edge change is detected at CAP2 input
#1
CLK
CLK Register Map
CLK
0x0
0x0
0x28
registers
n
AHBCLK
AHBCLK
AHB Devices Clock Enable Control Register
0x4
-1
read-write
n
0x0
0x0
DIV_EN
Hardware Divider Controller Clock Enable Control
4
1
read-write
0
Hardware Divider engine clock Disabled
#0
1
Hardware Divider engine clock Enabled
#1
ISP_EN
Flash ISP Controller Clock Enable Control
2
1
read-write
0
Flash ISP engine clock Disabled
#0
1
Flash ISP engine clock Enabled
#1
APBCLK
APBCLK
APB Devices Clock Enable Control Register
0x8
-1
read-write
n
0x0
0x0
ACMP_EN
Analog comparator Clock Enable
22
1
read-write
0
Analog comparator clock Disabled
#0
1
Analog comparator clock Enabled
#1
ADC_EN
ADC Clock Enable
28
1
read-write
0
ADC clock Disabled
#0
1
ADC clock Enabled
#1
BPWM_EN
Basic PWM Clock Enable
19
1
read-write
0
Basic PWM clock Disabled
#0
1
Basic PWM clock Enabled
#1
CAN_EN
CAN Bus Controller Clock Enable
24
1
read-write
0
CAN clock Disabled
#0
1
CAN clock Enabled
#1
CAP0_EN
Input Capture 0 Clock Enable
26
1
read-write
0
Input capture 0 clock Disabled
#0
1
Input capture 0 clock Enabled
#1
CAP1_EN
Input Capture 1 Clock Enable
27
1
read-write
0
Input capture 1 clock Disabled
#0
1
Input capture 1 clock Enabled
#1
EPWM0_EN
Enhanced PWM0 Clock Enable
20
1
read-write
0
Enhanced PWM0 clock Disabled
#0
1
Enhanced PWM0 clock Enabled
#1
EPWM1_EN
Enhanced PWM1 Clock Enable
21
1
read-write
0
Enhanced PWM1 clock Disabled
#0
1
Enhanced PWM1 clock Enabled
#1
FDIV_EN
Frequency Divider Output Clock Enable
6
1
read-write
0
Frequency divider output clock Disabled
#0
1
Frequency divider output clock Enabled
#1
I2C_EN
I2C Clock Enable
8
1
read-write
0
I2C clock Disabled
#0
1
I2C clock Enabled
#1
MDU_EN
MDU Clock Enable
18
1
read-write
0
MDU clock Disabled
#0
1
MDU clock Enabled
#1
OPA_EN
OPA0 and OPA1 Clock Enable
29
1
read-write
0
OPA0 and OPA1 clock Disabled
#0
1
OPA0 and OPA1 clock Enabled
#1
QEI0_EN
QEI0 Clock Enable
30
1
read-write
0
QEI0 clock Disabled
#0
1
QEI0 clock Enabled
#1
QEI1_EN
QEI1 Clock Enable
31
1
read-write
0
QEI1 clock Disabled
#0
1
QEI1 clock Enabled
#1
SPI0_EN
SPI0 Clock Enable
12
1
read-write
0
SPI0 clock Disabled
#0
1
SPI0 clock Enabled
#1
SPI1_EN
SPI1 Clock Enable
13
1
read-write
0
SPI1 clock Disabled
#0
1
SPI1 clock Enabled
#1
SPI2_EN
SPI2 Clock Enable
14
1
read-write
0
SPI2 clock Disabled
#0
1
SPI2 clock Enabled
#1
TMR0_EN
Timer0 Clock Enable
2
1
read-write
0
Timer0 clock Disabled
#0
1
Timer0 clock Enabled
#1
TMR1_EN
Timer1 Clock Enable
3
1
read-write
0
Timer1 clock Disabled
#0
1
Timer1 clock Enabled
#1
TMR2_EN
Timer2 Clock Enable
4
1
read-write
0
Timer2 clock Disabled
#0
1
Timer2 clock Enabled
#1
TMR3_EN
Timer3 Clock Enable
5
1
read-write
0
Timer3 clock Disabled
#0
1
Timer3 clock Enabled
#1
UART0_EN
UART0 Clock Enable
16
1
read-write
0
UART0 clock Disabled
#0
1
UART0 clock Enabled
#1
UART1_EN
UART1 clock enable.
17
1
read-write
0
UART1 clock Disabled
#0
1
UART1 clock Enabled
#1
WDT_EN
Watchdog Timer Clock Enable (Write-protection Bit)\nThis bit is the protected bit. It means programming this needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Watchdog Timer clock Disabled
#0
1
Watchdog Timer clock Enabled
#1
CLKDIV
CLKDIV
Clock Divider Number Register
0x18
read-write
n
0x0
0x0
ADC_N
ADC clock divider.
16
8
read-write
HCLK_N
HCLK Clock Divider
0
4
read-write
UART_N
UART Clock Divider
8
4
read-write
CLKSEL0
CLKSEL0
Clock Source Select Control Register 0
0x10
read-write
n
0x0
0x0
HCLK_S
HCLK Clock Source Selection (Write-protection Bits)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nThese bits are protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
0
3
read-write
0
Clock source from external 4~24 MHz crystal clock
#000
1
Reserved.
#001
2
Clock source from PLL clock
#010
3
Clock source from internal 10 kHz oscillator clock
#011
7
Clock source from internal 22.1184 MHz oscillator clock
#111
STCLK_S
Cortex_M0 SysTick Clock Source Selection (Write-protection Bits)
3
3
read-write
0
Clock source from external 4~24 MHz crystal clock
#000
1
Reserved.
#001
2
Clock source from external 4~24 MHz crystal clock/2
#010
3
Clock source from HCLK/2
#011
7
Clock source from internal 22.1184 MHz oscillator clock/2
#111
CLKSEL1
CLKSEL1
Clock Source Select Control Register 1
0x14
-1
read-write
n
0x0
0x0
UART_S
UART Clock Source Selection
24
2
read-write
0
Clock source from external 4~24 MHz crystal clock
#00
1
Clock source from PLL clock
#01
2
Reserved.
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
WDT_S
Watchdog Timer Clock Source Selection (Write-protection Bits)\nThese bits are protected bits, programing them need to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
0
2
read-write
0
Clock source from HCLK/128 clock
#00
1
Clock source from HCLK/512 clock
#01
2
Clock source from HCLK/2048 clock
#10
3
Clock source from internal 10 kHz oscillator clock
#11
CLKSEL2
CLKSEL2
Clock Source Select Control Register 2
0x1C
-1
read-write
n
0x0
0x0
FRQDIV_S
Clock Divider Clock Source Selection
2
2
read-write
0
Clock source from external 4~24 MHz crystal clock
#00
1
Reserved.
#01
2
Clock source from HCLK
#10
3
Clock source from internal 22.1184 MHz oscillator clock
#11
CLKSTATUS
CLKSTATUS
Clock status monitor Register
0xC
-1
read-write
n
0x0
0x0
CLK_SW_FAIL
Clock Switching Fail Flag (Write-protection Bit)\nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nWrite 1 to clear the bit to zero.
7
1
read-write
0
Clock switching success
#0
1
Clock switching failure
#1
OSC10K_STB
Internal 10k Hz Clock Source Stable Flag\nThis bit is read only.
3
1
read-write
0
Internal 10k Hz oscillator clock is not stable or disabled
#0
1
Internal 10k Hz oscillator clock is stable
#1
OSC22M_STB
Internal 22.1184M Hz Oscillator Clock Source Stable Flag\nThis bit is read only.
4
1
read-write
0
Internal 22.1184M Hz oscillator clock is not stable or disabled
#0
1
Internal 22.1184M Hz oscillator clock is stable
#1
PLL_STB
PLL Clock Source Stable Flag\nThis bit is read only.
2
1
read-write
0
PLL clock is not stable or disabled
#0
1
PLL clock is stable
#1
XTL_STB
External 4~24 MHz Crystal Clock Source Stable Flag\nThis bit is read only.
0
1
read-write
0
External 4~24 MHz crystal clock is not stable or disabled
#0
1
External 4~24 MHz crystal clock is stable
#1
FRQDIV
FRQDIV
Frequency Divider Control Register
0x24
read-write
n
0x0
0x0
DIVIDER_EN
Frequency Divider Enable Bit
4
1
read-write
0
Frequency divider Disabled
#0
1
Frequency divider Enabled
#1
FSEL
Frequency Divider Output Selection Bits\nThe output formula is:\nwhere FFRQDIV_CLK is the input clock frequency, FCLKO is the clock divider output frequency and N is the 4-bit value in FSEL[3:0].
0
4
read-write
PLLCON
PLLCON
PLL Control Register
0x20
-1
read-write
n
0x0
0x0
BP
PLL Bypass Control
17
1
read-write
0
PLL is in normal mode (default)
#0
1
PLL clock output is same as clock input (XTALin)
#1
FB_DV
PLL Feedback Divider Control Pins\nRefer to the formulas below the table.
0
9
read-write
IN_DV
PLL Input Divider Control Pins\nRefer to the formulas below the table.
9
5
read-write
OE
PLL OE (FOUT enable) Pin Control
18
1
read-write
0
PLL FOUT enable
#0
1
PLL FOUT is fixed low
#1
OUT_DV
PLL Output Divider Control Pins\nRefer to the formulas below the table.
14
2
read-write
PD
Power-down Mode
16
1
read-write
0
PLL is in normal mode
#0
1
PLL is in power-down mode (default)
#1
PLL_SRC
PLL Source Clock Selection
19
1
read-write
0
PLL source clock from external 4~24 MHz crystal
#0
1
PLL source clock from internal 22.1184 MHz oscillator
#1
PWRCON
PWRCON
System Power Down Control Register
0x0
-1
read-write
n
0x0
0x0
OSC10K_EN
Internal 10 kHz Oscillator Enable (Write-protection Bit)
3
1
read-write
0
10 kHz Oscillation Disabled
#0
1
10 kHz Oscillation Enabled
#1
OSC22M_EN
Internal 22.1184 MHz Oscillator Enable (Write-protection Bit)
2
1
read-write
0
22.1184 MHz Oscillation Disabled
#0
1
22.1184 MHz Oscillation Enabled
#1
PD_WU_INT_EN
Power-down Mode Wake-up Interrupt Enable (Write-protection Bit)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
5
1
read-write
0
Disabled
#0
1
Enabled
#1
PD_WU_STS
Power-down Mode Wake-up Interrupt Status\nSet by 'power down wake up event', it indicates that resume from Power-down mode'\nWrite 1 to clear the bit to zero.
6
1
read-write
XTL12M_EN
External 4~24 MHz Crystal Enable (Write-protection Bit)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically
0
1
read-write
0
External 4~24 MHz crystal Disabled
#0
1
External 4~24 MHz crystal Enabled
#1
DIV
DIV Register Map
DIV
0x0
0x0
0x18
registers
n
DIVCON
DIVCON
Divider Control Register
0x0
write-only
n
0x0
0x0
DIVST
Divider Start.\nSet this to 1 will start trigger divider operation once. This bit will be auto clear by hardware will calculation complete.
0
1
write-only
DIVIDEND
DIVIDEND
Dividend Source Register (Signed 32-bit)
0x4
read-write
n
0x0
0x0
Dividend
Dividend Source.\nThis register is given the dividend (signed 32-bit) of divider before calculation starts.
0
32
read-write
DIVISOR
DIVISOR
Divisor Source Resister (Signed 16-bit)
0x8
-1
read-write
n
0x0
0x0
Divisor
Divisor Source.\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculation.
0
16
read-write
DIVQUO
DIVQUO
Quotient Result Resister (Signed 32-bit)
0xC
read-only
n
0x0
0x0
Quotient
Quotient Result\nThis register holds the quotient (signed 32-bit) result of divider after calculation completes.
0
32
read-only
DIVREM
DIVREM
Reminder Result Register (Signed 16-bit)
0x10
read-only
n
0x0
0x0
Reminder
Reminder Result\nThis register holds the reminder (signed 16-bit) result of divider after calculation completes.
0
16
read-only
DIVSTS
DIVSTS
Divider Status Register
0x14
-1
read-write
n
0x0
0x0
DIV0
Divisor Zero Warning.\nThis register is read only.
1
1
read-write
0
The divisor is not 0
#0
1
The divisor is 0
#1
DIVFF
Divider Operation Finish Flag\nWhen divider calculation has finished, this bit is set to 1. This bit is cleared to 0 by writing 1 to it through software
2
1
read-write
DIV_FINISH
Divider Operation Finished\nThis register is read only.
0
1
read-write
0
The divider calculation not finished yet
#0
1
The divider calculation finished
#1
EPWM0
EPWM Register Map
EPWM
0x0
0x0
0x20
registers
n
0x2C
0xC
registers
n
0x3C
0x8
registers
n
PDTC
PDTC
EPWM Dead-time Control Register
0x2C
read-write
n
0x0
0x0
DTCNT
Dead-time Counter\nThe dead-time can be calculated according to the following formula:
0
11
read-write
DTEN0
Enable Dead-time Insertion for PWMx Pair (PWM0, PWM1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM0, PWM1)
#0
1
Dead-time insertion Enabled on the pin pair (PWM0, PWM1)
#1
DTEN2
Enable Dead-time Insertion for PWMx Pair (PWM2, PWM3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
17
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM2, PWM3)
#0
1
Dead-time insertion Enabled on the pin pair (PWM2, PWM3)
#1
DTEN4
Enable Dead-time Insertion for PWMx Pair (PWM4, PWM5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
18
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM4, PWM5)
#0
1
Dead-time insertion Enabled on the pin pair (PWM4, PWM5)
#1
PMSKD
PMSKD
EPWM Mask Mode Data Register
0x1C
read-write
n
0x0
0x0
PMSKD
PWM Mask Data Bit
0
6
read-write
0
Output logic low to PWMn
0
1
Output logic high to PWMn
1
PMSKE
PMSKE
EPWM Mask Mode Enable Register
0x18
read-write
n
0x0
0x0
PMSKE
PWM Mask Enable Bit\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with PMD.n data.
0
6
read-write
0
PWM generator signal is output to next stage
0
1
PWM generator signal is masked and PMD.n is output to next stage
1
PNPC
PNPC
EPWM Negative Polarity Control
0x34
read-write
n
0x0
0x0
PNPn
PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.
0
6
read-write
0
PWMn output is active high
0
1
PWMn output is active low
1
PWM0
PWM0
EPWM PWM0 Duty Register
0xC
read-write
n
0x0
0x0
PWM_Duty
PWM Duty Register\nEdge-aligned:
0
16
read-write
PWM2
PWM2
0x10
read-write
n
0x0
0x0
PWM4
PWM4
0x14
read-write
n
0x0
0x0
PWMB
PWMB
EPWM Brake Output
0x30
read-write
n
0x0
0x0
PWMB
PWM Brake Output\nWhen PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWMB bit0~5 setting, respectively.
0
6
read-write
0
PWMn output before polarity control is low when Brake is asserted
0
1
PWMn output before polarity control is high when Brake is asserted
1
PWMCON
PWMCON
EPWM Control Register
0x0
read-write
n
0x0
0x0
AUTOLD
Auto Load Enable Bit
30
1
read-write
0
PWM duty registers PWMx0~PWMx4 are updated by software
#0
1
PWM duty registers PWMx0~PWMx4 are auto-load from motor drive unit (MDU) when MDU update a set of new duty values for PWM unit
#1
BK0FILT
Brake 0 (BKPx0 pin) Edge Detector Filter Clock Selection
20
2
read-write
BK0NF_DIS
PWM Brake 0 Noise Filter Disable
28
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BK1FILT
Brake 1 (BKPx1 pin) Edge Detector Filter Clock Selection
22
2
read-write
BK1NF_DIS
PWM Brake 1 Noise Filter Disable
29
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BK1SEL
Brake Function 1 Source Selection
18
2
read-write
BKEN0
BKPx0 Pin Trigger Brake Function0 Enable
16
1
read-write
0
PWMx Brake Function 0 Disabled
#0
1
PWMx Brake Function 0 Enabled
#1
BKEN1
BKPx1 Pin Trigger Brake Function Enable
17
1
read-write
0
PWMx Brake Function 1 Disabled
#0
1
PWMx Brake Function 1 Enabled
#1
BRKI_EN
Enable Brake0 and Brak1 Interrupt
5
1
read-write
0
Flags BFK0 and BFK1 Disabled to trigger PWM interrupt
#0
1
Flags BKF0 and BKF1 Enabled to trigger PWM interrupt
#1
CLDMD
Center Reload Mode Enable\nThis bit only works when EPWM operating in Center-aligned mode.
31
1
read-write
0
EPWM reload duty register at the period point of PWM counter
#0
1
EPWM reload duty register at the center point of PWM counter
#1
CLRPWM
Clear PWM Counter Control Bit.\nNote: It is automatically cleared by hardware.
11
1
read-write
1
Clear 16-bit PWM counter to 000H
#1
CPO0BK_EN
Enable CPO0 Digital Output as Brake0 Source
24
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BK_EN
Enable CPO1 Digital Output as Brake 0 Source
25
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BK_EN
CPO2 Digital Output as Brake 0 Source Enable
26
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
GRP
Group bit
13
1
read-write
0
The signals timing of PWM0, PWM2 and PWM4 are independent
#0
1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
#1
INT_TYPE
PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only.
8
1
read-write
0
PWMF will be set if PWM counter underflow
#0
1
PWMF will be set if PWM counter matches PWMP register
#1
INVBKP0
Inverse BKP0 State
14
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
INVBKP1
Inverse BKP1 State
15
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
LOAD
Reload PWM period registers (PWMP) and PWM Duty Registers (PWM0~3) Control Bit\nNote2: This bit is written by software, cleared by hardware, and always read as 0.
6
1
read-write
0
No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) are not loaded to PWM counter and Comparator registers
#0
1
Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
#1
LVDBK_EN
Low-level Detection Trigger PWM Brake Function 1 Enable
27
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
PWMDIV
PWM Clock Pre-divider Selection
2
2
read-write
PWMINV
Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.
9
1
read-write
0
Not inverse PWM comparator output
#0
1
Inverse PWM comparator output
#1
PWMI_EN
Enable PWM Interrupt
4
1
read-write
0
Flag PWMF Disabled to trigger PWM interrupt
#0
1
Flag PWMF Enabled to trigger PWM interrupt
#1
PWMMOD
PWM Mode Selection
0
2
read-write
PWMRUN
Start PWMRUN Control Bit
7
1
read-write
0
The PWM stops running
#0
1
The PWM counter starts running
#1
PWMTYPE
PWM Aligned Type Selection Bit.
12
1
read-write
0
Edge-aligned type
#0
1
Centre-aligned type
#1
PWMEIC
PWMEIC
EPWM Edge Interrupt Control Register
0x40
read-write
n
0x0
0x0
EINT0_TYPE
PWMx0 Edge Interrupt Type
8
1
read-write
0
PWM0EF will be set if falling edge is detected at PWMx0
#0
1
PWM0EF will be set if rising edge is detected at PWMx0
#1
EINT2_TYPE
PWMx2 Edge Interrupt Type
9
1
read-write
0
PWM2EF will be set if falling edge is detected at PWMx2
#0
1
PWM2EF will be set if rising edge is detected at PWMx2
#1
EINT4_TYPE
PWMx4 Edge Interrupt Type
10
1
read-write
0
PWM4EF will be set if falling edge is detected at PWMx4
#0
1
PWM4EF will be set if rising edge is detected at PWMx4
#1
PWM0EI_EN
Enable PWMx0 Edge Interrupt
0
1
read-write
0
Flag PWM0EF Disabled to trigger PWM interrupt
#0
1
Flag PWM0EF Enabled to trigger PWM interrupt
#1
PWM2EI_EN
Enable PWMx2 Edge Interrupt
1
1
read-write
0
Flag PWM2EF Disabled to trigger PWM interrupt
#0
1
Flag PWM2EF Enabled to trigger PWM interrupt
#1
PWM4EI_EN
Enable PWMx4 Edge Interrupt
2
1
read-write
0
Flag PWM4EF Disabled to trigger PWM interrupt
#0
1
Flag PWM4EF Enabled to trigger PWM interrupt
#1
PWMFCNT
PWMFCNT
EPWMF Compared Counter
0x3C
read-write
n
0x0
0x0
PWMFCNT
PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF to request the PWM period interrupt. \nPWMF will be set in every (1 + PWMFCNT[3:0]) time of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs
0
4
read-write
PWMP
PWMP
EPWM Period Register
0x8
read-write
n
0x0
0x0
PWMP
PWM Period Register\nEdge-aligned:
0
16
read-write
PWMSTS
PWMSTS
EPWM Status Register
0x4
read-write
n
0x0
0x0
BK0STS
Brake 0 Status (Read Only)
24
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BK1STS
Brake 1 Status (Read Only)
25
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
BKF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
0
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BKF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
1
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
BKLK0
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to itself through software.
8
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
PWM0EF
PWMx0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
4
1
read-write
0
PWMx0 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx0 rising or falling. If EINT0_TYPE = 0, this bit is set when PWMx0 falling is detected. If EINT0_TYPE = 1, this bit is set when PWMx0 rising is detected
#1
PWM2EF
PWMx2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
5
1
read-write
0
PWMx2 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx2 rising or falling. If EINT2_TYPE = 0, this bit is set when PWMx2 falling is detected. If EINT2_TYPE = 1, this bit is set when PWMx2 rising is detected
#1
PWM4EF
PWMx4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
6
1
read-write
0
PWMx4 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx4 rising or falling. If EINT4_TYPE = 0, this bit is set when PWMx4 falling is detected. If EINT4_TYPE = 1, this bit is set when PWMx4 rising is detected
#1
PWMF
PWM Period Flag.\nNote: This bit must be cleared by writing 1 to itself through software.
2
1
read-write
0
The PWM Counter has not up counted to the value of PWMP or down counted with underflow
#0
1
Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
#1
EPWM1
EPWM Register Map
EPWM
0x0
0x0
0x20
registers
n
0x2C
0xC
registers
n
0x3C
0x8
registers
n
PDTC
PDTC
EPWM Dead-time Control Register
0x2C
read-write
n
0x0
0x0
DTCNT
Dead-time Counter\nThe dead-time can be calculated according to the following formula:
0
11
read-write
DTEN0
Enable Dead-time Insertion for PWMx Pair (PWM0, PWM1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
16
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM0, PWM1)
#0
1
Dead-time insertion Enabled on the pin pair (PWM0, PWM1)
#1
DTEN2
Enable Dead-time Insertion for PWMx Pair (PWM2, PWM3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
17
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM2, PWM3)
#0
1
Dead-time insertion Enabled on the pin pair (PWM2, PWM3)
#1
DTEN4
Enable Dead-time Insertion for PWMx Pair (PWM4, PWM5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
18
1
read-write
0
Dead-time insertion Disabled on the pin pair (PWM4, PWM5)
#0
1
Dead-time insertion Enabled on the pin pair (PWM4, PWM5)
#1
PMSKD
PMSKD
EPWM Mask Mode Data Register
0x1C
read-write
n
0x0
0x0
PMSKD
PWM Mask Data Bit
0
6
read-write
0
Output logic low to PWMn
0
1
Output logic high to PWMn
1
PMSKE
PMSKE
EPWM Mask Mode Enable Register
0x18
read-write
n
0x0
0x0
PMSKE
PWM Mask Enable Bit\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with PMD.n data.
0
6
read-write
0
PWM generator signal is output to next stage
0
1
PWM generator signal is masked and PMD.n is output to next stage
1
PNPC
PNPC
EPWM Negative Polarity Control
0x34
read-write
n
0x0
0x0
PNPn
PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.
0
6
read-write
0
PWMn output is active high
0
1
PWMn output is active low
1
PWM0
PWM0
EPWM PWM0 Duty Register
0xC
read-write
n
0x0
0x0
PWM_Duty
PWM Duty Register\nEdge-aligned:
0
16
read-write
PWM2
PWM2
0x10
read-write
n
0x0
0x0
PWM4
PWM4
0x14
read-write
n
0x0
0x0
PWMB
PWMB
EPWM Brake Output
0x30
read-write
n
0x0
0x0
PWMB
PWM Brake Output\nWhen PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWMB bit0~5 setting, respectively.
0
6
read-write
0
PWMn output before polarity control is low when Brake is asserted
0
1
PWMn output before polarity control is high when Brake is asserted
1
PWMCON
PWMCON
EPWM Control Register
0x0
read-write
n
0x0
0x0
AUTOLD
Auto Load Enable Bit
30
1
read-write
0
PWM duty registers PWMx0~PWMx4 are updated by software
#0
1
PWM duty registers PWMx0~PWMx4 are auto-load from motor drive unit (MDU) when MDU update a set of new duty values for PWM unit
#1
BK0FILT
Brake 0 (BKPx0 pin) Edge Detector Filter Clock Selection
20
2
read-write
BK0NF_DIS
PWM Brake 0 Noise Filter Disable
28
1
read-write
0
Noise filter of PWM Brake 0 Enabled
#0
1
Noise filter of PWM Brake 0 Disabled
#1
BK1FILT
Brake 1 (BKPx1 pin) Edge Detector Filter Clock Selection
22
2
read-write
BK1NF_DIS
PWM Brake 1 Noise Filter Disable
29
1
read-write
0
Noise filter of PWM Brake 1 Enabled
#0
1
Noise filter of PWM Brake 1 Disabled
#1
BK1SEL
Brake Function 1 Source Selection
18
2
read-write
BKEN0
BKPx0 Pin Trigger Brake Function0 Enable
16
1
read-write
0
PWMx Brake Function 0 Disabled
#0
1
PWMx Brake Function 0 Enabled
#1
BKEN1
BKPx1 Pin Trigger Brake Function Enable
17
1
read-write
0
PWMx Brake Function 1 Disabled
#0
1
PWMx Brake Function 1 Enabled
#1
BRKI_EN
Enable Brake0 and Brak1 Interrupt
5
1
read-write
0
Flags BFK0 and BFK1 Disabled to trigger PWM interrupt
#0
1
Flags BKF0 and BKF1 Enabled to trigger PWM interrupt
#1
CLDMD
Center Reload Mode Enable\nThis bit only works when EPWM operating in Center-aligned mode.
31
1
read-write
0
EPWM reload duty register at the period point of PWM counter
#0
1
EPWM reload duty register at the center point of PWM counter
#1
CLRPWM
Clear PWM Counter Control Bit.\nNote: It is automatically cleared by hardware.
11
1
read-write
1
Clear 16-bit PWM counter to 000H
#1
CPO0BK_EN
Enable CPO0 Digital Output as Brake0 Source
24
1
read-write
0
CPO0 as one brake source in Brake 0 Disabled
#0
1
CPO0 as one brake source in Brake 0 Enabled
#1
CPO1BK_EN
Enable CPO1 Digital Output as Brake 0 Source
25
1
read-write
0
CPO1 as one brake source in Brake 0 Disabled
#0
1
CPO1 as one brake source in Brake 0 Enabled
#1
CPO2BK_EN
CPO2 Digital Output as Brake 0 Source Enable
26
1
read-write
0
CPO2 as one brake source in Brake 0 Disabled
#0
1
CPO2 as one brake source in Brake 0 Enabled
#1
GRP
Group bit
13
1
read-write
0
The signals timing of PWM0, PWM2 and PWM4 are independent
#0
1
Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0
#1
INT_TYPE
PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only.
8
1
read-write
0
PWMF will be set if PWM counter underflow
#0
1
PWMF will be set if PWM counter matches PWMP register
#1
INVBKP0
Inverse BKP0 State
14
1
read-write
0
The state of pin BKPx0 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx0 is passed to the negative edge detector
#1
INVBKP1
Inverse BKP1 State
15
1
read-write
0
The state of pin BKPx1 is passed to the negative edge detector
#0
1
The inversed state of pin BKPx1 is passed to the negative edge detector
#1
LOAD
Reload PWM period registers (PWMP) and PWM Duty Registers (PWM0~3) Control Bit\nNote2: This bit is written by software, cleared by hardware, and always read as 0.
6
1
read-write
0
No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) are not loaded to PWM counter and Comparator registers
#0
1
Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWMn0~PWMn3) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
#1
LVDBK_EN
Low-level Detection Trigger PWM Brake Function 1 Enable
27
1
read-write
0
Brake Function 1 triggered by Low-level detection Disabled
#0
1
Brake Function 1 triggered by Low-level detection Enabled
#1
PWMDIV
PWM Clock Pre-divider Selection
2
2
read-write
PWMINV
Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.
9
1
read-write
0
Not inverse PWM comparator output
#0
1
Inverse PWM comparator output
#1
PWMI_EN
Enable PWM Interrupt
4
1
read-write
0
Flag PWMF Disabled to trigger PWM interrupt
#0
1
Flag PWMF Enabled to trigger PWM interrupt
#1
PWMMOD
PWM Mode Selection
0
2
read-write
PWMRUN
Start PWMRUN Control Bit
7
1
read-write
0
The PWM stops running
#0
1
The PWM counter starts running
#1
PWMTYPE
PWM Aligned Type Selection Bit.
12
1
read-write
0
Edge-aligned type
#0
1
Centre-aligned type
#1
PWMEIC
PWMEIC
EPWM Edge Interrupt Control Register
0x40
read-write
n
0x0
0x0
EINT0_TYPE
PWMx0 Edge Interrupt Type
8
1
read-write
0
PWM0EF will be set if falling edge is detected at PWMx0
#0
1
PWM0EF will be set if rising edge is detected at PWMx0
#1
EINT2_TYPE
PWMx2 Edge Interrupt Type
9
1
read-write
0
PWM2EF will be set if falling edge is detected at PWMx2
#0
1
PWM2EF will be set if rising edge is detected at PWMx2
#1
EINT4_TYPE
PWMx4 Edge Interrupt Type
10
1
read-write
0
PWM4EF will be set if falling edge is detected at PWMx4
#0
1
PWM4EF will be set if rising edge is detected at PWMx4
#1
PWM0EI_EN
Enable PWMx0 Edge Interrupt
0
1
read-write
0
Flag PWM0EF Disabled to trigger PWM interrupt
#0
1
Flag PWM0EF Enabled to trigger PWM interrupt
#1
PWM2EI_EN
Enable PWMx2 Edge Interrupt
1
1
read-write
0
Flag PWM2EF Disabled to trigger PWM interrupt
#0
1
Flag PWM2EF Enabled to trigger PWM interrupt
#1
PWM4EI_EN
Enable PWMx4 Edge Interrupt
2
1
read-write
0
Flag PWM4EF Disabled to trigger PWM interrupt
#0
1
Flag PWM4EF Enabled to trigger PWM interrupt
#1
PWMFCNT
PWMFCNT
EPWMF Compared Counter
0x3C
read-write
n
0x0
0x0
PWMFCNT
PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF to request the PWM period interrupt. \nPWMF will be set in every (1 + PWMFCNT[3:0]) time of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs
0
4
read-write
PWMP
PWMP
EPWM Period Register
0x8
read-write
n
0x0
0x0
PWMP
PWM Period Register\nEdge-aligned:
0
16
read-write
PWMSTS
PWMSTS
EPWM Status Register
0x4
read-write
n
0x0
0x0
BK0STS
Brake 0 Status (Read Only)
24
1
read-only
0
PWM had been out of Brake 0 state
#0
1
PWM is in Brake 0 state
#1
BK1STS
Brake 1 Status (Read Only)
25
1
read-only
0
PWM had been out of Brake 1 state
#0
1
PWM is in Brake 1 state
#1
BKF0
PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
0
1
read-write
0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#0
1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
#1
BKF1
PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
1
1
read-write
0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#0
1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
#1
BKLK0
PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to itself through software.
8
1
read-write
0
Brake 0 state is released
#0
1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
#1
PWM0EF
PWMx0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
4
1
read-write
0
PWMx0 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx0 rising or falling. If EINT0_TYPE = 0, this bit is set when PWMx0 falling is detected. If EINT0_TYPE = 1, this bit is set when PWMx0 rising is detected
#1
PWM2EF
PWMx2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
5
1
read-write
0
PWMx2 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx2 rising or falling. If EINT2_TYPE = 0, this bit is set when PWMx2 falling is detected. If EINT2_TYPE = 1, this bit is set when PWMx2 rising is detected
#1
PWM4EF
PWMx4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
6
1
read-write
0
PWMx4 not toggled
#0
1
Hardware will set this flag to high at the time of PWMx4 rising or falling. If EINT4_TYPE = 0, this bit is set when PWMx4 falling is detected. If EINT4_TYPE = 1, this bit is set when PWMx4 rising is detected
#1
PWMF
PWM Period Flag.\nNote: This bit must be cleared by writing 1 to itself through software.
2
1
read-write
0
The PWM Counter has not up counted to the value of PWMP or down counted with underflow
#0
1
Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
#1
FMC
FMC Register Map
FMC
0x0
0x0
0x1C
registers
n
0x40
0x4
registers
n
DFBADR
DFBADR
Data Flash Base Address
0x14
read-only
n
0x0
0x0
DFBADR
Data Flash Base Address\nThis register indicates data flash start address. It is read only.\nFor 128 KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip is powered on but for 64/32 KB device, it is fixed at 0x0001_F000.
0
32
read-only
FATCON
FATCON
Flash Access Time Control Register
0x18
read-write
n
0x0
0x0
LFOM
Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1
4
1
read-write
0
Low frequency optimization mode Disabled
#0
1
Low frequency optimization mode Enabled
#1
ISPADR
ISPADR
ISP Address Register
0x4
read-write
n
0x0
0x0
ISPADR
ISP Address\nThe NuMicro( MT5xx Series has a maximum 32Kx32 (128 KB) of embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
0
32
read-write
ISPCMD
ISPCMD
ISP Command Register
0xC
read-write
n
0x0
0x0
ISPCMD
ISP Command
0
6
read-write
ISPCON
ISPCON
ISP Control Register
0x0
read-write
n
0x0
0x0
APUEN
APROM Update Enable (Write-protection Bit)
3
1
read-write
0
APROM cannot be updated when chip runs in APROM
#0
1
APROM can be updated when chip runs in APROM
#1
BS
Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
1
1
read-write
0
Boot from APROM
#0
1
Boot from LDROM
#1
CFGUEN
Enable Config-bits Update by ISP (Write-protection Bit)
4
1
read-write
0
ISP update config-bits Disabled
#0
1
ISP update config-bits Enabled
#1
ISPEN
ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.
0
1
read-write
0
ISP function Disabled
#0
1
ISP function Enabled
#1
ISPFF
ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear to this bit to 0.
6
1
read-write
LDUEN
LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.
5
1
read-write
0
LDROM cannot be updated
#0
1
LDROM can be updated when chip runs in APROM
#1
ISPDAT
ISPDAT
ISP Data Register
0x8
read-write
n
0x0
0x0
ISPDAT
ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
0
32
read-write
ISPSTA
ISPSTA
ISP Status Register
0x40
read-write
n
0x0
0x0
CBS
Chip Boot Selection (Read Only)\nThis is a mirror of CBS in Config0.
1
2
read-only
ISPFF
ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: This bit function is the same as ISPCON bit6
6
1
read-write
ISPGO
ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit0
0
1
read-only
0
ISP operation finished
#0
1
ISP operation progressed
#1
VECMAP
Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
9
12
read-only
ISPTRG
ISPTRG
ISP Trigger Control Register
0x10
read-write
n
0x0
0x0
ISPGO
ISP Start Trigger (Write-protection Bit)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
ISP operation finished
#0
1
ISP progressed
#1
GCR
GCR Register Map
GCR
0x0
0x0
0x10
registers
n
0x100
0x4
registers
n
0x118
0x8
registers
n
0x18
0x8
registers
n
0x24
0x4
registers
n
0x30
0x2C
registers
n
BODCR
BODCR
Brown Out Detector Control Register
0x18
-1
read-write
n
0x0
0x0
BOD_EN
Brown-out Detector Enable (Write-protection Bit)\nThe default value is set by flash controller user configuration register config0 bit[23]\nThis bit is the protected bit which means programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
0
1
read-write
0
Brown-out Detector function Disabled
#0
1
Brown-out Detector function Enabled
#1
BOD_INTF
Brown-out Detector Interrupt Flag\nWrite 1 to clear this bit to 0.
4
1
read-write
0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#0
1
When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
#1
BOD_LPM
Brown-out Detector Low power Mode (Write-protection Bit)\nThe BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit which means programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
5
1
read-write
0
BOD operated in Normal mode (default)
#0
1
BOD Low Power mode Enabled
#1
BOD_OUT
Brown-out Detector Output Status
6
1
read-write
0
Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#0
1
Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0
#1
BOD_RSTEN
Brown-out Reset Enable (Write-protection Bit)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low).\nThe default value is set by flash controller user configuration register config0 bit[20].\nThis bit is the protected bit. It means programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
3
1
read-write
0
Brown-out 'INTERRUPT' function Enabled
#0
1
Brown-out 'RESET' function Enabled
#1
BOD_VL
Brown-out Detector Threshold Voltage Selection (Write-protection Bit)
1
2
read-write
LVR_EN
Low Voltage Reset Enable (Write-protection Bit)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.\nThis bit is the protected bit. It means programming it needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
7
1
read-write
0
Low Voltage Reset function Disabled
#0
1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default)
#1
IPRSTC1
IPRSTC1
Peripheral Reset Control Register1
0x8
read-write
n
0x0
0x0
CHIP_RST
CHIP One-shot Reset (Write-protection Bit)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload.\nFor the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2\nThis bit is the protected bit. It means programming this bit needs to write '59h', '16h', and '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
0
1
read-write
0
CHIP normal operation
#0
1
CHIP one-shot reset
#1
CPU_RST
CPU Kernel One-shot Reset (Write-protection Bit)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return 0 after the two clock cycles\nThis bit is the protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
1
1
read-write
0
CPU normal operation
#0
1
CPU one-shot reset
#1
DIV_RST
DIV Controller Reset (Write-protection Bit)\nSet this bit to 1 will generate a reset signal to the DIVIDER. User need to set this bit to 0 to release from the reset state.\nThis bit is the protected bit, It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100
4
1
read-write
0
DIVIDER controller normal operation
#0
1
DIVIDER controller reset
#1
IPRSTC2
IPRSTC2
Peripheral Reset Control Register2
0xC
read-write
n
0x0
0x0
ACMP_RST
Analog Comparator Controller Reset
22
1
read-write
0
Analog Comparator controller normal operation
#0
1
Analog Comparator controller reset
#1
ADC_RST
ADC Controller Reset
28
1
read-write
0
ADC controller normal operation
#0
1
ADC controller reset
#1
BPWM_RST
Basic PWM Controller Reset
19
1
read-write
0
Basic PWM controller normal operation
#0
1
Basic PWM controller reset
#1
CAN_RST
CAN Controller Reset
24
1
read-write
0
CAN controller normal operation
#0
1
CAN controller reset
#1
CAP0_RST
Input Capture 0 Controller Reset
26
1
read-write
0
Input capture 0 controller normal operation
#0
1
Input capture 0 controller reset
#1
CAP1_RST
Input Capture 1 Controller Reset
27
1
read-write
0
Input capture 1 controller normal operation
#0
1
Input capture 1 controller reset
#1
EPWM0_RST
Enhanced PWM0 Controller Reset
20
1
read-write
0
PWM03 controller normal operation
#0
1
PWM03 controller reset
#1
EPWM1_RST
Enhanced PWM1 Controller Reset
21
1
read-write
0
PWM47 controller normal operation
#0
1
PWM47 controller reset
#1
GPIO_RST
GPIO Controller Reset
1
1
read-write
0
GPIO controller normal operation
#0
1
GPIO controller reset
#1
I2C_RST
I2C Controller Reset
8
1
read-write
0
I2C controller normal operation
#0
1
I2C controller reset
#1
MDU_RST
MDU Controller Reset
18
1
read-write
0
MDU controller normal operation
#0
1
MDU controller reset
#1
OPA_RST
OPA0 and OPA1 Controller Reset
29
1
read-write
0
OPA0 and OPA1 controller normal operation
#0
1
OPA0 and OPA1 controller reset
#1
QEI0_RST
QEI0 Controller Reset
30
1
read-write
0
QEI0 controller normal operation
#0
1
QEI0 controller reset
#1
QEI1_RST
QEI1 Controller Reset
31
1
read-write
0
QEI1 controller normal operation
#0
1
QEI1 controller reset
#1
SPI0_RST
SPI0 Controller Reset
12
1
read-write
0
SPI0 controller normal operation
#0
1
SPI0 controller reset
#1
SPI1_RST
SPI1 Controller Reset
13
1
read-write
0
SPI1 controller normal operation
#0
1
SPI1 controller reset
#1
SPI2_RST
SPI2 Controller Reset
14
1
read-write
0
SPI2 controller normal operation
#0
1
SPI2 controller reset
#1
TMR0_RST
Timer0 Controller Reset
2
1
read-write
0
Timer0 controller normal operation
#0
1
Timer0 controller reset
#1
TMR1_RST
Timer1 Controller Reset
3
1
read-write
0
Timer1 controller normal operation
#0
1
Timer1 controller reset
#1
TMR2_RST
Timer2 Controller Reset
4
1
read-write
0
Timer2 controller normal operation
#0
1
Timer2 controller reset
#1
TMR3_RST
Timer3 Controller Reset
5
1
read-write
0
Timer3 controller normal operation
#0
1
Timer3 controller reset
#1
UART0_RST
UART0 Controller Reset
16
1
read-write
0
UART0 controller normal operation
#0
1
UART0 controller reset
#1
UART1_RST
UART1 Controller Reset
17
1
read-write
0
UART1 controller normal operation
#0
1
UART1 controller reset
#1
IRCCR
IRCCR
IRC Auto Trim Control Register
0x118
read-write
n
0x0
0x0
IRCSR
IRCSR
IRC Auto Trim Status Register
0x11C
read-write
n
0x0
0x0
P0_MFP
P0_MFP
P0 Multiple Function and Input Type Control Register
0x30
read-write
n
0x0
0x0
P0_MFP0
P0.0 Multi-function Selection
0
1
read-write
0
The GPIO P0.0 is selected
#0
1
The EPWM0.0 function is selected
#1
P0_MFP1
P0.1 Multi-function Selection
1
1
read-write
0
The GPIO P0.1 is selected
#0
1
The EPWM0.1 function is selected
#1
P0_MFP2
P0.2 Multi-function Selection
2
1
read-write
0
The GPIO P0.2 is selected
#0
1
The EPWM0.2 function is selected
#1
P0_MFP3
P0.3 Multi-function Selection
3
1
read-write
0
The GPIO P0.3 is selected
#0
1
The EPWM0.3 function is selected
#1
P0_MFP4
P0.4 Multi-function Selection
4
1
read-write
0
The GPIO P0.4 is selected
#0
1
The EPWM0.4 function is selected
#1
P0_MFP5
P0.5 Multi-function Selection
5
1
read-write
0
The GPIO P0.5 is selected
#0
1
The EPWM0.5 function is selected
#1
P0_MFP6
P0.6 Multi-function Selection
6
1
read-write
0
The GPIO P0.6 is selected
#0
1
The BKP01 function is selected
#1
P0_MFP7
P0.7 Multi-function Selection
7
1
read-write
0
The GPIO P0.7 is selected
#0
1
The STADC function is selected
#1
P0_TYPE0
Port 0 Schmitt Trigger Input Enable
16
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE1
Port 0 Schmitt Trigger Input Enable
17
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE2
Port 0 Schmitt Trigger Input Enable
18
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE3
Port 0 Schmitt Trigger Input Enable
19
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE4
Port 0 Schmitt Trigger Input Enable
20
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE5
Port 0 Schmitt Trigger Input Enable
21
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE6
Port 0 Schmitt Trigger Input Enable
22
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P0_TYPE7
Port 0 Schmitt Trigger Input Enable
23
1
read-write
0
Port 0 bit m Schmitt trigger input function Disabled
#0
1
Port 0 bit m Schmitt trigger input function Enabled
#1
P1_MFP
P1_MFP
P1 Multiple Function and Input Type Control Register
0x34
read-write
n
0x0
0x0
P1_MFP0
P1.0 Multi-function Selection
0
1
read-write
0
The GPIO P1.0 is selected
#0
1
The EPWM1.0 function is selected
#1
P1_MFP1
P1.1 Multi-function Selection
1
1
read-write
0
The GPIO P1.1 is selected
#0
1
The EPWM1.1 function is selected
#1
P1_MFP2
P1.2 Multi-function Selection
2
1
read-write
0
The GPIO P1.2 is selected
#0
1
The EPWM1.2 function is selected
#1
P1_MFP3
P1.3 Multi-function Selection
3
1
read-write
0
The GPIO P1.3 is selected
#0
1
The EPWM1.3 function is selected
#1
P1_MFP4
P1.4 Multi-function Selection
4
1
read-write
0
The GPIO P1.4 is selected
#0
1
The EPWM1.4 function is selected
#1
P1_MFP5
P1.5 Multi-function Selection
5
1
read-write
0
The GPIO P1.5 is selected
#0
1
The EPWM1.5 function is selected
#1
P1_MFP6
P1.6 Multi-function Selection
6
1
read-write
0
The GPIO P1.6 is selected
#0
1
The BKP00 function is selected
#1
P1_MFP7
P1.7 Multi-function Selection
7
1
read-write
0
The GPIO P1.7 is selected
#0
1
The BKP10 function is selected
#1
P1_TYPE0
Port 1 Schmitt Trigger Input Enable
16
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE1
Port 1 Schmitt Trigger Input Enable
17
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE2
Port 1 Schmitt Trigger Input Enable
18
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE3
Port 1 Schmitt Trigger Input Enable
19
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE4
Port 1 Schmitt Trigger Input Enable
20
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE5
Port 1 Schmitt Trigger Input Enable
21
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE6
Port 1 Schmitt Trigger Input Enable
22
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P1_TYPE7
Port 1 Schmitt Trigger Input Enable
23
1
read-write
0
Port 1 bit m Schmitt trigger input function Disabled
#0
1
Port 1 bit m Schmitt trigger input function Enabled
#1
P2_MFP
P2_MFP
P2 Multiple Function and Input Type Control Register
0x38
read-write
n
0x0
0x0
P2_ALT0
P2.0 Alternative Function\nSee P2_MFP[0].
8
1
read-write
P2_ALT6
P2.6 Alternative Function\nSee P2_MFP[6].
14
1
read-write
P2_ALT7
P2.7 Alternative Function\nSee P2_MFP[7].
15
1
read-write
P2_MFP0
P2.0 Multi-function Selection
0
1
read-write
P2_MFP1
P2.1 Multi-function Selection
1
1
read-write
0
The GPIO P2.1 is selected
#0
1
The IC02 function is selected
#1
P2_MFP2
P2.2 Multi-function Selection
2
1
read-write
0
The GPIO P2.2 is selected
#0
1
The IC01 function is selected
#1
P2_MFP3
P2.3 Multi-function Selection
3
1
read-write
0
The GPIO P2.3 is selected
#0
1
The IC00 function is selected
#1
P2_MFP4
P2.4 Multi-function Selection
4
1
read-write
0
The GPIO P2.4 is selected
#0
1
The QEIA0 function is selected
#1
P2_MFP5
P2.5 Multi-function Selection
5
1
read-write
0
The GPIO P2.5 is selected
#0
1
The QEIB0 function is selected
#1
P2_MFP6
P2.6 Multi-function Selection
6
1
read-write
P2_MFP7
P2.7 Multi-function Selection
7
1
read-write
P2_TYPE0
Port 2 Schmitt Trigger Input Enable
16
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE1
Port 2 Schmitt Trigger Input Enable
17
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE2
Port 2 Schmitt Trigger Input Enable
18
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE3
Port 2 Schmitt Trigger Input Enable
19
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE4
Port 2 Schmitt Trigger Input Enable
20
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE5
Port 2 Schmitt Trigger Input Enable
21
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE6
Port 2 Schmitt Trigger Input Enable
22
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P2_TYPE7
Port 2 Schmitt Trigger Input Enable
23
1
read-write
0
Port 2 bit m Schmitt trigger input function Disabled
#0
1
Port 2 bit m Schmitt trigger input function Enabled
#1
P3_MFP
P3_MFP
P3 Multiple Function and Input Type Control Register
0x3C
read-write
n
0x0
0x0
P3_ALT1
P3.1 Alternative Function\nSee P3_MFP[1].
9
1
read-write
P3_ALT4
P3.4 Alternative Function\nSee P3_MFP[4].
12
1
read-write
P3_ALT5
P3.5 Alternative Function\nSee P3_MFP[5].
13
1
read-write
P3_MFP0
P3.0 Multi-function Selection
0
1
read-write
0
The GPIO P3.0 is selected
#0
1
The RX0 function is selected
#1
P3_MFP1
P3.1 Multi-function Selection
1
1
read-write
P3_MFP2
P3.2 Multi-function Selection
2
1
read-write
0
The GPIO P3.2 is selected
#0
1
The /INT0 function is selected
#1
P3_MFP3
P3.3 Multi-function Selection
3
1
read-write
0
The GPIO P3.3 is selected
#0
1
The /INT1 function is selected
#1
P3_MFP4
P3.4 Multi-function Selection
4
1
read-write
P3_MFP5
P3.5 Multi-function Selection
5
1
read-write
P3_MFP6
P3.6 Multi-function Selection
6
1
read-write
0
The GPIO P3.6 is selected
#0
1
The CANRX function is selected
#1
P3_MFP7
P3.7 Multi-function Selection
7
1
read-write
0
The GPIO P3.7 is selected
#0
1
The CANTX function is selected
#1
P3_TYPE0
Port 3 Schmitt Trigger Input Enable
16
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE1
Port 3 Schmitt Trigger Input Enable
17
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE2
Port 3 Schmitt Trigger Input Enable
18
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE3
Port 3 Schmitt Trigger Input Enable
19
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE4
Port 3 Schmitt Trigger Input Enable
20
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE5
Port 3 Schmitt Trigger Input Enable
21
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE6
Port 3 Schmitt Trigger Input Enable
22
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P3_TYPE7
Port 3 Schmitt Trigger Input Enable
23
1
read-write
0
Port 3 bit m Schmitt trigger input function Disabled
#0
1
Port 3 bit m Schmitt trigger input function Enabled
#1
P4_MFP
P4_MFP
P4 Multiple Function and Input Type Control Register
0x40
read-write
n
0x0
0x0
P4_ALT
P4.6 Alternative Function.\nSee P4_MFP[6].
14
1
read-write
P4_MFP0
P4.0 Multi-function Selection
0
1
read-write
0
The GPIO P4.0 is selected
#0
1
The IC10 function is selected
#1
P4_MFP1
P4.1 Multi-function Selection
1
1
read-write
0
The GPIO P4.1 is selected
#0
1
The IC11 function is selected
#1
P4_MFP2
P4.2 Multi-function Selection
2
1
read-write
0
The GPIO P4.2 is selected
#0
1
The IC12 function is selected
#1
P4_MFP4
P4.4 Multi-function Selection
4
1
read-write
0
The GPIO P4.4 is selected
#0
1
The QEIA1 function is selected
#1
P4_MFP5
P4.5 Multi-function Selection
5
1
read-write
0
The GPIO P4.5 is selected
#0
1
The QEIB1 function is selected
#1
P4_MFP6
P4.6 Multi-function Selection
6
1
read-write
P4_MFP7
P4.7 Multi-function Selection
7
1
read-write
0
The GPIO P4.7 is selected
#0
1
The T3 function is selected
#1
P4_TYPE0
Port 4 Schmitt Trigger Input Enable
16
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE1
Port 4 Schmitt Trigger Input Enable
17
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE2
Port 4 Schmitt Trigger Input Enable
18
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE3
Port 4 Schmitt Trigger Input Enable
19
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE4
Port 4 Schmitt Trigger Input Enable
20
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE5
Port 4 Schmitt Trigger Input Enable
21
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE6
Port 4 Schmitt Trigger Input Enable
22
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P4_TYPE7
Port 4 Schmitt Trigger Input Enable
23
1
read-write
0
Port 4 bit m Schmitt trigger input function Disabled
#0
1
Port 4 bit m Schmitt trigger input function Enabled
#1
P5_MFP
P5_MFP
P5 Multiple Function and Input Type Control Register
0x44
read-write
n
0x0
0x0
P5_ALT0
P5.0 Alternative Function\nSee P5_MFP[0].
8
1
read-write
P5_ALT1
P5.1 Alternative Function\nSee P5_MFP[1].
9
1
read-write
P5_ALT2
P5.2 Alternative Function.\nSee P5_MFP[2].
10
1
read-write
P5_MFP0
P5.0 Multi-function Selection
0
1
read-write
P5_MFP1
P5.1 Multi-function Selection
1
1
read-write
P5_MFP2
P5.2 Multi-function Selection
2
1
read-write
P5_MFP3
P5.3 Multi-function Selection
3
1
read-write
0
The GPIO P5.3 is selected
#0
1
The SPI_CLK2 function is selected
#1
P5_MFP4
P5.4 Multi-function Selection
4
1
read-write
0
The GPIO P5.4 is selected
#0
1
The /SS2 function is selected
#1
P5_MFP5
P5.5 Multi-function Selection
5
1
read-write
0
The GPIO P5.5 is selected
#0
1
The CLKO function is selected
#1
P5_MFP6
P5.6 Multi-function Selection
6
1
read-write
0
The GPIO P5.6 is selected
#0
1
The BPWM0 function is selected
#1
P5_MFP7
P5.7 Multi-function Selection
7
1
read-write
0
The GPIO P5.7 is selected
#0
1
The BPWM1 function is selected
#1
P5_TYPE0
Port 5 Schmitt Trigger Input Enable
16
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE1
Port 5 Schmitt Trigger Input Enable
17
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE2
Port 5 Schmitt Trigger Input Enable
18
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE3
Port 5 Schmitt Trigger Input Enable
19
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE4
Port 5 Schmitt Trigger Input Enable
20
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE5
Port 5 Schmitt Trigger Input Enable
21
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE6
Port 5 Schmitt Trigger Input Enable
22
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P5_TYPE7
Port 5 Schmitt Trigger Input Enable
23
1
read-write
0
Port 5 bit m Schmitt trigger input function Disabled
#0
1
Port 5 bit m Schmitt trigger input function Enabled
#1
P6_MFP
P6_MFP
P6 Multiple Function and Input Type Control Register
0x48
read-write
n
0x0
0x0
P6_MFP0
P6.0 Multi-function Selection
0
1
read-write
0
The GPIO P6.0 is selected
#0
1
The AINA0 function is selected
#1
P6_MFP1
P6.1 Multi-function Selection
1
1
read-write
0
The GPIO P6.1 is selected
#0
1
The AINA1 function is selected
#1
P6_MFP2
P6.2 Multi-function Selection
2
1
read-write
0
The GPIO P6.2 is selected
#0
1
The AINA2 function is selected
#1
P6_MFP3
P6.3 Multi-function Selection
3
1
read-write
0
The GPIO P6.3 is selected
#0
1
The AINA3 function is selected
#1
P6_MFP4
P6.4 Multi-function Selection
4
1
read-write
0
The GPIO P6.4 is selected
#0
1
The AINA4 or CPN1 function is selected
#1
P6_MFP5
P6.5 Multi-function Selection
5
1
read-write
0
The GPIO P6.5 is selected
#0
1
The AINA5 or CPP1 function is selected
#1
P6_MFP6
P6.6 Multi-function Selection
6
1
read-write
0
The GPIO P6.6 is selected
#0
1
The AINA6 function is selected
#1
P6_MFP7
P6.7 Multi-function Selection
7
1
read-write
0
The GPIO P6.7 is selected
#0
1
The AINA7 function is selected
#1
P6_TYPE0
Port 6 Schmitt Trigger Input Enable
16
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE1
Port 6 Schmitt Trigger Input Enable
17
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE2
Port 6 Schmitt Trigger Input Enable
18
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE3
Port 6 Schmitt Trigger Input Enable
19
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE4
Port 6 Schmitt Trigger Input Enable
20
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE5
Port 6 Schmitt Trigger Input Enable
21
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE6
Port 6 Schmitt Trigger Input Enable
22
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P6_TYPE7
Port 6 Schmitt Trigger Input Enable
23
1
read-write
0
Port 6 bit m Schmitt trigger input function Disabled
#0
1
Port 6 bit m Schmitt trigger input function Enabled
#1
P7_MFP
P7_MFP
P7 Multiple Function and Input Type Control Register
0x4C
read-write
n
0x0
0x0
P7_MFP0
P7.0 Multi-function Selection
0
1
read-write
0
The GPIO P7.0 is selected
#0
1
The AINB0 function is selected
#1
P7_MFP1
P7.1 Multi-function Selection
1
1
read-write
0
The GPIO P7.1 is selected
#0
1
The AINB1 function is selected
#1
P7_MFP2
P7.2 Multi-function Selection
2
1
read-write
0
The GPIO P7.2 is selected
#0
1
The AINB2 function is selected
#1
P7_MFP3
P7.3 Multi-function Selection
3
1
read-write
0
The GPIO P7.3 is selected
#0
1
The AINB3 function is selected
#1
P7_MFP4
P7.4 Multi-function Selection
4
1
read-write
0
The GPIO P7.4 is selected
#0
1
The AINB4 or CPN2 function is selected
#1
P7_MFP5
P7.5 Multi-function Selection
5
1
read-write
0
The GPIO P7.5 is selected
#0
1
The AINB5 or CPP2 function is selected
#1
P7_MFP6
P7.6 Multi-function Selection
6
1
read-write
0
The GPIO P7.6 is selected
#0
1
The AINB6 function is selected
#1
P7_MFP7
P7.7 Multi-function Selection
7
1
read-write
0
The GPIO P7.7 is selected
#0
1
The AINB7 function is selected
#1
P7_TYPE0
Port 7 Schmitt Trigger Input Enable
16
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE1
Port 7 Schmitt Trigger Input Enable
17
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE2
Port 7 Schmitt Trigger Input Enable
18
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE3
Port 7 Schmitt Trigger Input Enable
19
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE4
Port 7 Schmitt Trigger Input Enable
20
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE5
Port 7 Schmitt Trigger Input Enable
21
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE6
Port 7 Schmitt Trigger Input Enable
22
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P7_TYPE7
Port 7 Schmitt Trigger Input Enable
23
1
read-write
0
Port 7 bit m Schmitt trigger input function Disabled
#0
1
Port 7 bit m Schmitt trigger input function Enabled
#1
P8_MFP
P8_MFP
P8 Multiple Function and Input Type Control Register
0x50
read-write
n
0x0
0x0
P8_MFP0
P8.0 Multi-function Selection
0
1
read-write
0
The GPIO P8.0 is selected
#0
1
The OPP0 function is selected
#1
P8_MFP1
P8.1 Multi-function Selection
1
1
read-write
0
The GPIO P8.1 is selected
#0
1
The OPN0 function is selected
#1
P8_MFP2
P8.2 Multi-function Selection
2
1
read-write
0
The GPIO P8.2 is selected
#0
1
The OPO0 function is selected
#1
P8_MFP3
P8.3 Multi-function Selection
3
1
read-write
0
The GPIO P8.3 is selected
#0
1
The CPN function is selected
#1
P8_MFP4
P8.4 Multi-function Selection
4
1
read-write
0
The GPIO P8.4 is selected
#0
1
The CPP function is selected
#1
P8_MFP7
P8.7 Multi-function Selection
7
1
read-write
0
The GPIO P8.7 is selected
#0
1
The CPO function is selected
#1
P8_TYPE0
Port 8 Schmitt Trigger Input Enable
16
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE1
Port 8 Schmitt Trigger Input Enable
17
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE2
Port 8 Schmitt Trigger Input Enable
18
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE3
Port 8 Schmitt Trigger Input Enable
19
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE4
Port 8 Schmitt Trigger Input Enable
20
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE5
Port 8 Schmitt Trigger Input Enable
21
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE6
Port 8 Schmitt Trigger Input Enable
22
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P8_TYPE7
Port 8 Schmitt Trigger Input Enable
23
1
read-write
0
Port 8 bit m Schmitt trigger input function Disabled
#0
1
Port 8 bit m Schmitt trigger input function Enabled
#1
P9_MFP
P9_MFP
P9 Multiple Function and Input Type Control Register
0x54
read-write
n
0x0
0x0
P9_MFP0
P9.0 Multi-function Selection
0
1
read-write
0
The GPIO P9.0 is selected
#0
1
The OPO1 function is selected
#1
P9_MFP1
P9.1 Multi-function Selection
1
1
read-write
0
The GPIO P9.1 is selected
#0
1
The OPN1 function is selected
#1
P9_MFP2
P9.2 Multi-function Selection
2
1
read-write
0
The GPIO P9.2 is selected
#0
1
The OPP1 function is selected
#1
P9_MFP3
P9.3 Multi-function Selection
3
1
read-write
0
The GPIO P9.3 is selected
#0
1
The BKP11 function is selected
#1
P9_MFP4
P9.4 Multi-function Selection
4
1
read-write
0
The GPIO P9.4 is selected
#0
1
The SPI_CLK1 function is selected
#1
P9_MFP5
P9.5 Multi-function Selection
5
1
read-write
0
The GPIO P9.5 is selected
#0
1
The MISO1 function is selected
#1
P9_MFP6
P9.6 Multi-function Selection
6
1
read-write
0
The GPIO P9.6 is selected
#0
1
The MOSI1 function is selected
#1
P9_MFP7
P9.7 Multi-function Selection
7
1
read-write
0
The GPIO P9.7 is selected
#0
1
The /SS1 function is selected
#1
P9_TYPE0
Port 9 Schmitt Trigger Input Enable
16
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE1
Port 9 Schmitt Trigger Input Enable
17
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE2
Port 9 Schmitt Trigger Input Enable
18
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE3
Port 9 Schmitt Trigger Input Enable
19
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE4
Port 9 Schmitt Trigger Input Enable
20
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE5
Port 9 Schmitt Trigger Input Enable
21
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE6
Port 9 Schmitt Trigger Input Enable
22
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
P9_TYPE7
Port 9 Schmitt Trigger Input Enable
23
1
read-write
0
Port 9 bit m Schmitt trigger input function Disabled
#0
1
Port 9 bit m Schmitt trigger input function Enabled
#1
PA_MFP
PA_MFP
PA Multiple Function and Input Type Control Register
0x58
read-write
n
0x0
0x0
PA_MFP0
PA.0 Multi-function Selection
0
1
read-write
0
The GPIO PA.0 is selected
#0
1
The TX1 function is selected
#1
PA_MFP1
PA.1 Multi-function Selection
1
1
read-write
0
The GPIO PA.1 is selected
#0
1
The RX1 function is selected
#1
PA_TYPE0
Port A Schmitt Trigger Input Enable
16
1
read-write
0
Port A bit m Schmitt trigger input function Disabled
#0
1
Port A bit m Schmitt trigger input function Enabled
#1
PA_TYPE1
Port A Schmitt Trigger Input Enable
17
1
read-write
0
Port A bit m Schmitt trigger input function Disabled
#0
1
Port A bit m Schmitt trigger input function Enabled
#1
PDID
PDID
Part Device Identification Number Register
0x0
-1
read-only
n
0x0
0x0
PDID
Part Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.
0
32
read-only
PORCR
PORCR
Power-On-Reset Controller Register
0x24
read-write
n
0x0
0x0
REGWRPROT
REGWRPROT
Register Write-Protection Control Register
0x100
read-write
n
0x0
0x0
REGPROTDIS
Register Write- Protection disable index (Read only).
0
1
read-only
0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
#0
1
Write-protection Disabled for writing protected registers
#1
REGWRPROT
Register Write-Protection code (Write Only).\nSome write-protection registers have to be disabled the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
0
8
write-only
RSTSRC
RSTSRC
System Reset Source Register
0x4
read-write
n
0x0
0x0
RSTS_BOD
The RSTS_BOD flag is set by the 'reset signal' from the Brown-out Detector to indicate the previous reset source.\nWrite 1 to clear this bit to 0.
4
1
read-write
0
No reset from BOD
#0
1
The BOD had issued the reset signal to reset the system
#1
RSTS_CPU
The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nWrite 1 to clear this bit to 0.
7
1
read-write
0
No reset from CPU
#0
1
Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1
#1
RSTS_LVR
The RSTS_LVR flag is set by the 'reset signal' from the Low-Voltage-Reset controller to indicate the previous reset source.\nWrite 1 to clear this bit to 0.
3
1
read-write
0
No reset from LVR
#0
1
The LVR controller had issued the reset signal to reset the system
#1
RSTS_POR
The RSTS_POR flag is set by the 'reset signal' from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nWrite 1 to clear this bit to 0.
0
1
read-write
0
No reset from POR or CHIP_RST
#0
1
The Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system
#1
RSTS_RESET
The RSTS_RESET flag is set by the 'reset signal' from the nRESET pin to indicate the previous reset source.\nWrite 1 to clear this bit to 0.
1
1
read-write
0
No reset from the nRESET pin
#0
1
The nRESET pin had issued the reset signal to reset the system
#1
RSTS_SYS
The RSTS_SYS flag is set by the 'reset signal' from the Cortex-M0 kernel to indicate the previous reset source.\nWrite 1 to clear this bit to 0.
5
1
read-write
0
No reset from Cortex-M0
#0
1
The Cortex-M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 kernel
#1
RSTS_WDT
The RSTS_WDT flag is set by the 'reset signal' from the watchdog timer to indicate the previous reset source.\nWrite 1 to clear this bit to0.
2
1
read-write
0
No reset from watchdog timer
#0
1
The watchdog timer had issued the reset signal to reset the system
#1
TEMPCR
TEMPCR
Temperature Sensor Control Register
0x1C
read-write
n
0x0
0x0
VTEMP_EN
Temperature Sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature can be obtained from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. Please refer to the ADC function chapter for detail ADC conversion functional description.
0
1
read-write
0
Temperature sensor function Disabled (default)
#0
1
Temperature sensor function Enabled
#1
GP0
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
0x2E0
0x8
registers
n
DBNCECON
DBNCECON
External Interrupt De-bounce Control
0x2E0
read-write
n
0x0
0x0
DBCLKSEL
De-bounce sampling cycle selection.
0
4
read-write
DBCLKSRC
De-bounce Counter Clock Source Selection
4
1
read-write
0
De-bounce counter clock source is the HCLK
#0
1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
#1
ICLK_ON
Interrupt Clock On Mode\nIt is recommended to turn off this bit to save system power if no special application concern.
5
1
read-write
0
Edge detection circuit is active only if I/O pin corresponding Pn_IEN bit is set to 1
#0
1
All I/O pins edge detection circuit is always active after reset
#1
PWMPOEN
PWMPOEN
PWM Port Output Enable
0x2E4
read-write
n
0x0
0x0
HZ_BPWM
Basic PWM Ports Output Control\nThe initial value is loaded from config0[CHZ_BPWM] after any reset.
4
1
read-write
0
The driving mode of Basic PWM ports are controlled by GPIO mode register (Pn_PMD) or multi-function register (Pn_MFP)
#0
1
The driving mode of Basic PWM ports are forced in tri-state (Hi-Z) all the time
#1
HZ_Even0
PWM Unit0 Even Ports Output Control\nThe initial value is loaded from config0[CHZ_Even0] after any reset.
0
1
read-write
0
The driving mode of PWM unit0 even ports are controlled by GPIO mode register (Pn_PMD) or multi-function register (Pn_MFP)
#0
1
The driving mode of PWM unit0 even ports are forced in tri-state (Hi-Z) all the time
#1
HZ_Even1
PWM Unit1 Even Ports Output Control\nThe initial value is loaded from config0[CHZ_Even1] after any reset.
2
1
read-write
0
The driving mode of PWM unit1 even ports are controlled by GPIO mode register (Pn_PMD) or multi-function register (Pn_MFP)
#0
1
The driving mode of PWM unit1 even ports are forced in tri-state (Hi-Z) all the time
#1
HZ_Odd0
PWM Unit0 Odd Ports Output Control\nThe initial value is loaded from config0[CHZ_Odd0] after any reset.
1
1
read-write
0
The driving mode of PWM unit0 odd ports are controlled by GPIO mode register (Pn_PMD) or multi-function register (Pn_MFP)
#0
1
The driving mode of PWM unit0 odd ports are forced in tri-state (Hi-Z) all the time
#1
HZ_Odd1
PWM Unit1 Odd Ports Output Control\nThe initial value is loaded from config0[CHZ_Odd1] after any reset.
3
1
read-write
0
The driving mode of PWM unit1 odd ports are controlled by GPIO mode register (Pn_PMD) or multi-function register (Pn_MFP)
#0
1
The driving mode of PWM unit1 odd ports are forced in tri-state (Hi-Z) all the time
#1
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP1
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP10
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP2
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP3
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP4
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP5
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP6
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP7
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP8
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GP9
GPIO Register Map
GPIO
0x0
0x0
0x24
registers
n
Px_DBEN
Px_DBEN
GPIO Port De-bounce Enable
0x14
read-write
n
0x0
0x0
DBEN0
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
0
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN1
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
1
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN2
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
2
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN3
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
3
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN4
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
4
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN5
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
5
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN6
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
6
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
DBEN7
Port x Bit m Input De-bounce Enable
DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for 'edge-triggered' interrupt only and is ignored for 'level triggered' interrupt.
If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by DBNCECON register.
7
1
read-write
0
Bit[m] de-bounce function Disabled
#0
1
Bit[m] de-bounce function Enabled
#1
Px_DMASK
Px_DMASK
GPIO Port Data Output Write Mask
0xC
read-write
n
0x0
0x0
DMASK0
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
0
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK1
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
1
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK2
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
2
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK3
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
3
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK4
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
4
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK5
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
5
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK6
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
6
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
DMASK7
Port x bit m data output write mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DMASK[m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.
7
1
read-write
0
Corresponding Pn_DOUT[m] bit can be updated
#0
1
Corresponding Pn_DOUT[m] bit protected
#1
Px_DOUT
Px_DOUT
GPIO Port Data Output
0x8
-1
read-write
n
0x0
0x0
DOUT0
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
0
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT1
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
1
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT2
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
2
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT3
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
3
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT4
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
4
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT5
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
5
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT6
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
6
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
DOUT7
Port x bit m output.\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or quasi bi-directional mode.
7
1
read-write
0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
#0
1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[m] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
#1
Px_IEN
Px_IEN
GPIO Port Interrupt Enable
0x1C
read-write
n
0x0
0x0
IF_EN0
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
0
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN1
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
1
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN2
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
2
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN3
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
3
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN4
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
4
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN5
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
5
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN6
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
6
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IF_EN7
Port x Bit m Interrupt Enabled for Falling Edge or Low Level Input\nIF_EN[n] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
7
1
read-write
0
Port n bit m low-level or falling edge interrupt Disabled
#0
1
Port n bit m low-level or falling edge interrupt Enabled
#1
IR_EN0
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
16
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN1
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
17
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN2
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
18
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN3
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
19
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN4
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
20
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN5
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
21
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN6
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
22
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
IR_EN7
Port x Bit m Interrupt Enabled for Rising Edge or High Level Input\nIR_EN[m] enables the interrupt for each of the corresponding input of Port x. Set bit to 1 also enable the pin wakeup function.
23
1
read-write
0
Port n bit m high-level or rising edge interrupt Disabled
#0
1
Port n bit m high-level or rising edge interrupt Enabled
#1
Px_IMD
Px_IMD
GPIO Port Interrupt Mode Select
0x18
read-write
n
0x0
0x0
IMD0
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD1
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD2
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
2
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD3
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
3
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD4
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
4
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD5
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
5
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD6
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
6
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
IMD7
Port x bit m Edge or Level Triggered Interrupt Control\nIMD[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
7
1
read-write
0
Edge triggered interrupt
#0
1
Level triggered interrupt
#1
Px_ISF
Px_ISF
GPIO Port Interrupt Source Flag
0x20
read-write
n
0x0
0x0
IF_ISF0
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
0
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF1
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
1
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF2
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
2
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF3
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
3
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF4
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
4
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF5
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
5
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF6
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
6
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
IF_ISF7
Port x Bit m Trigger Source Indicator\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :
7
1
read-write
0
No interrupt at Port x.\nNo effect
#0
1
Indicates Port x bit m detects a trigger event.\nClear the corresponding pending interrupt
#1
Px_OFFD
Px_OFFD
GPIO Port Bit Off Digital Enable
0x4
read-write
n
0x0
0x0
OFFD0
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
16
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD1
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
17
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD2
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
18
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD3
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
19
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD4
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
20
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD5
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
21
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD6
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
22
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
OFFD7
Port x bit m off digital input path.\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.
23
1
read-write
0
I/O digital input path Enabled
#0
1
I/O digital input path Disabled (digital input tied to low)
#1
Px_PIN
Px_PIN
GPIO Port Pin Value
0x10
read-only
n
0x0
0x0
PIN0
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
0
1
read-only
PIN1
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
1
1
read-only
PIN2
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
2
1
read-only
PIN3
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
3
1
read-only
PIN4
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
4
1
read-only
PIN5
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
5
1
read-only
PIN6
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
6
1
read-only
PIN7
Port x Bit m Pin Value
Each bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
7
1
read-only
Px_PMD
Px_PMD
GPIO Port Bit Mode Control
0x0
read-write
n
0x0
0x0
PMD0
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
0
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD1
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
2
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD10
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
20
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD11
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
22
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD12
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
24
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD13
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
26
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD14
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
28
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD15
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
30
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD2
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
4
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD3
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
6
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD4
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
8
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD5
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
10
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD6
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
12
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD7
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
14
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD8
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
16
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
PMD9
Port x bit m Mode Control\nDetermine each I/O mode of Px pins.
18
2
read-write
0
GPIO port [n] pin is in Input mode
#00
1
GPIO port [n] pin is in Push-pull Output mode
#01
2
GPIO port [n] pin is in Open-drain Output mode
#10
3
GPIO port [n] pin is in Quasi-bidirectional mode
#11
GPIOB
GPIO Register Map
GPIO
0x0
0x0
0x160
registers
n
0x0
0x160
registers
n
P0_0
P0_0
GPIO Port n bit m I/O value
0x0
read-write
n
0x0
0x0
Pnm
Port n bit m (Pnm) value.\nWrite:\nFor example: a writing of P00 reflects the value of bit P0_DOUT[0], a reading returns the value of P0_PIN[0].\nNote: The write operation will not be affected by register GPIOx_DMASK
0
1
read-write
0
Clear Pnm latch to output low.\nPort pin of Pnm is a low level
#0
1
Set Pnm latch to output high.\nPort pin of Pnm is a high level
#1
P0_1
P0_1
0x4
read-write
n
0x0
0x0
P0_2
P0_2
0x8
read-write
n
0x0
0x0
P0_3
P0_3
0xC
read-write
n
0x0
0x0
P0_4
P0_4
0x10
read-write
n
0x0
0x0
P0_5
P0_5
0x14
read-write
n
0x0
0x0
P0_6
P0_6
0x18
read-write
n
0x0
0x0
P0_7
P0_7
0x1C
read-write
n
0x0
0x0
P10_0
P10_0
0x140
read-write
n
0x0
0x0
P10_1
P10_1
0x144
read-write
n
0x0
0x0
P10_2
P10_2
0x148
read-write
n
0x0
0x0
P10_3
P10_3
0x14C
read-write
n
0x0
0x0
P10_4
P10_4
0x150
read-write
n
0x0
0x0
P10_5
P10_5
0x154
read-write
n
0x0
0x0
P10_6
P10_6
0x158
read-write
n
0x0
0x0
P10_7
P10_7
0x15C
read-write
n
0x0
0x0
P1_0
P1_0
0x20
read-write
n
0x0
0x0
P1_1
P1_1
0x24
read-write
n
0x0
0x0
P1_2
P1_2
0x28
read-write
n
0x0
0x0
P1_3
P1_3
0x2C
read-write
n
0x0
0x0
P1_4
P1_4
0x30
read-write
n
0x0
0x0
P1_5
P1_5
0x34
read-write
n
0x0
0x0
P1_6
P1_6
0x38
read-write
n
0x0
0x0
P1_7
P1_7
0x3C
read-write
n
0x0
0x0
P2_0
P2_0
0x40
read-write
n
0x0
0x0
P2_1
P2_1
0x44
read-write
n
0x0
0x0
P2_2
P2_2
0x48
read-write
n
0x0
0x0
P2_3
P2_3
0x4C
read-write
n
0x0
0x0
P2_4
P2_4
0x50
read-write
n
0x0
0x0
P2_5
P2_5
0x54
read-write
n
0x0
0x0
P2_6
P2_6
0x58
read-write
n
0x0
0x0
P2_7
P2_7
0x5C
read-write
n
0x0
0x0
P3_0
P3_0
0x60
read-write
n
0x0
0x0
P3_1
P3_1
0x64
read-write
n
0x0
0x0
P3_2
P3_2
0x68
read-write
n
0x0
0x0
P3_3
P3_3
0x6C
read-write
n
0x0
0x0
P3_4
P3_4
0x70
read-write
n
0x0
0x0
P3_5
P3_5
0x74
read-write
n
0x0
0x0
P3_6
P3_6
0x78
read-write
n
0x0
0x0
P3_7
P3_7
0x7C
read-write
n
0x0
0x0
P4_0
P4_0
0x80
read-write
n
0x0
0x0
P4_1
P4_1
0x84
read-write
n
0x0
0x0
P4_2
P4_2
0x88
read-write
n
0x0
0x0
P4_3
P4_3
0x8C
read-write
n
0x0
0x0
P4_4
P4_4
0x90
read-write
n
0x0
0x0
P4_5
P4_5
0x94
read-write
n
0x0
0x0
P4_6
P4_6
0x98
read-write
n
0x0
0x0
P4_7
P4_7
0x9C
read-write
n
0x0
0x0
P5_0
P5_0
0xA0
read-write
n
0x0
0x0
P5_1
P5_1
0xA4
read-write
n
0x0
0x0
P5_2
P5_2
0xA8
read-write
n
0x0
0x0
P5_3
P5_3
0xAC
read-write
n
0x0
0x0
P5_4
P5_4
0xB0
read-write
n
0x0
0x0
P5_5
P5_5
0xB4
read-write
n
0x0
0x0
P5_6
P5_6
0xB8
read-write
n
0x0
0x0
P5_7
P5_7
0xBC
read-write
n
0x0
0x0
P6_0
P6_0
0xC0
read-write
n
0x0
0x0
P6_1
P6_1
0xC4
read-write
n
0x0
0x0
P6_2
P6_2
0xC8
read-write
n
0x0
0x0
P6_3
P6_3
0xCC
read-write
n
0x0
0x0
P6_4
P6_4
0xD0
read-write
n
0x0
0x0
P6_5
P6_5
0xD4
read-write
n
0x0
0x0
P6_6
P6_6
0xD8
read-write
n
0x0
0x0
P6_7
P6_7
0xDC
read-write
n
0x0
0x0
P7_0
P7_0
0xE0
read-write
n
0x0
0x0
P7_1
P7_1
0xE4
read-write
n
0x0
0x0
P7_2
P7_2
0xE8
read-write
n
0x0
0x0
P7_3
P7_3
0xEC
read-write
n
0x0
0x0
P7_4
P7_4
0xF0
read-write
n
0x0
0x0
P7_5
P7_5
0xF4
read-write
n
0x0
0x0
P7_6
P7_6
0xF8
read-write
n
0x0
0x0
P7_7
P7_7
0xFC
read-write
n
0x0
0x0
P8_0
P8_0
0x100
read-write
n
0x0
0x0
P8_1
P8_1
0x104
read-write
n
0x0
0x0
P8_2
P8_2
0x108
read-write
n
0x0
0x0
P8_3
P8_3
0x10C
read-write
n
0x0
0x0
P8_4
P8_4
0x110
read-write
n
0x0
0x0
P8_5
P8_5
0x114
read-write
n
0x0
0x0
P8_6
P8_6
0x118
read-write
n
0x0
0x0
P8_7
P8_7
0x11C
read-write
n
0x0
0x0
P9_0
P9_0
0x120
read-write
n
0x0
0x0
P9_1
P9_1
0x124
read-write
n
0x0
0x0
P9_2
P9_2
0x128
read-write
n
0x0
0x0
P9_3
P9_3
0x12C
read-write
n
0x0
0x0
P9_4
P9_4
0x130
read-write
n
0x0
0x0
P9_5
P9_5
0x134
read-write
n
0x0
0x0
P9_6
P9_6
0x138
read-write
n
0x0
0x0
P9_7
P9_7
0x13C
read-write
n
0x0
0x0
I2C0
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched.
1
7
read-write
I2CADDR1
I2CADDR1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
2
1
read-write
EI
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined 'not addressed' Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:
0
8
read-only
I2CTOC
I2CTOC
I2C Time Out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time out Counter Input Clock is Divided by 4\nWhen Enabled, the time out period is extend 4 times.
1
1
read-write
0
The time out counter input clock divided by 4 Disabled
#0
1
The time out counter input clock divided by 4 Enabled
#1
ENTI
Time out Counter Enable\nWhen Enabled, the 14-bit time out counter will start counting when SI is clear. Write 1 to SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time out counter Disabled
#0
1
Time out counter Enabled
#1
TIF
Time out Flag\nThis bit is set by H/W when I2C time out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake Up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-up Function Enable
0
1
read-write
0
I2C wake up function Disabled
#0
1
I2C wake up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake Up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake Up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit
0
1
read-write
I2C1
I2C Register Map
I2C
0x0
0x0
0x30
registers
n
0x3C
0x8
registers
n
I2CADDR0
I2CADDR0
I2C Slave Address Register0
0x4
read-write
n
0x0
0x0
GC
General Call Function
0
1
read-write
0
General Call function Disabled
#0
1
General Call function Enabled
#1
I2CADDR
I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if one of the addresses is matched.
1
7
read-write
I2CADDR1
I2CADDR1
0x18
read-write
n
0x0
0x0
I2CADDR2
I2CADDR2
0x1C
read-write
n
0x0
0x0
I2CADDR3
I2CADDR3
0x20
read-write
n
0x0
0x0
I2CADM0
I2CADM0
I2C Slave Address Mask Register0
0x24
read-write
n
0x0
0x0
I2CADM
I2C Address Mask register\nI2C bus controller supports multiple address recognition with four address mask registers. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
1
7
read-write
0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
0
1
Mask Enabled (the received corresponding address bit is don't care.)
1
I2CADM1
I2CADM1
0x28
read-write
n
0x0
0x0
I2CADM2
I2CADM2
0x2C
read-write
n
0x0
0x0
I2CADM3
I2CADM3
0x30
read-write
n
0x0
0x0
I2CDAT
I2CDAT
I2C Data Register
0x8
read-write
n
0x0
0x0
I2CDAT
I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
0
8
read-write
I2CLK
I2CLK
I2C Clock Divided Register
0x10
read-write
n
0x0
0x0
I2CLK
I2C clock divided Register\nNote: The minimum value of I2CLK is 4.
0
8
read-write
I2CON
I2CON
I2C Control Register
0x0
read-write
n
0x0
0x0
AA
Assert Acknowledge Control Bit
2
1
read-write
EI
Enable Interrupt
7
1
read-write
0
I2C interrupt Disabled
#0
1
I2C interrupt Enabled
#1
ENS1
I2C Controller Enable Bit
6
1
read-write
0
Disabled
#0
1
Enabled
#1
SI
I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
3
1
read-write
STA
I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
5
1
read-write
STO
I2C STOP Control Bit\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined 'not addressed' Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
4
1
read-write
I2CSTATUS
I2CSTATUS
I2C Status Register
0xC
-1
read-only
n
0x0
0x0
I2CSTATUS
I2C Status Register\nThe status register of I2C:
0
8
read-only
I2CTOC
I2CTOC
I2C Time Out Counter Register
0x14
read-write
n
0x0
0x0
DIV4
Time out Counter Input Clock is Divided by 4\nWhen Enabled, the time out period is extend 4 times.
1
1
read-write
0
The time out counter input clock divided by 4 Disabled
#0
1
The time out counter input clock divided by 4 Enabled
#1
ENTI
Time out Counter Enable\nWhen Enabled, the 14-bit time out counter will start counting when SI is clear. Write 1 to SI flag will reset counter and re-start up counting after SI is cleared.
2
1
read-write
0
Time out counter Disabled
#0
1
Time out counter Enabled
#1
TIF
Time out Flag\nThis bit is set by H/W when I2C time out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nSoftware can write 1 to clear this bit.
0
1
read-write
I2CWKUPCON
I2CWKUPCON
I2C Wake Up Control Register
0x3C
read-write
n
0x0
0x0
WKUPEN
I2C Wake-up Function Enable
0
1
read-write
0
I2C wake up function Disabled
#0
1
I2C wake up function Enabled
#1
I2CWKUPSTS
I2CWKUPSTS
I2C Wake Up Status Register
0x40
read-write
n
0x0
0x0
WKUPIF
I2C Wake Up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit
0
1
read-write
INT
INT Register Map
INT
0x0
0x0
0x88
registers
n
IRQ0_SRC
IRQ0_SRC
IRQ0 (BOD) interrupt source identity
0x0
read-only
n
0x0
0x0
BOD_INT
Identify BOD interrupt source.
0
1
read-only
IRQ10_SRC
IRQ10_SRC
IRQ10 (TMR2) interrupt source identity
0x28
read-only
n
0x0
0x0
TMR2_INT
Identify TMR2 interrupt source.
0
1
read-only
IRQ11_SRC
IRQ11_SRC
IRQ11 (TMR3) interrupt source identity
0x2C
read-only
n
0x0
0x0
TMR3_INT
Identify TMR3 interrupt source.
0
1
read-only
IRQ12_SRC
IRQ12_SRC
IRQ12 (UART0) interrupt source identity
0x30
read-only
n
0x0
0x0
UART0_INT
Identify UART0 interrupt source.
0
1
read-only
IRQ13_SRC
IRQ13_SRC
IRQ13 (UART1) interrupt source identity
0x34
read-only
n
0x0
0x0
UART1_INT
Identify UART1 interrupt source.
0
1
read-only
IRQ14_SRC
IRQ14_SRC
IRQ14 (SPI0) interrupt source identity
0x38
read-only
n
0x0
0x0
SPI0_INT
Identify SPI0 interrupt source.
0
1
read-only
IRQ15_SRC
IRQ15_SRC
IRQ15 (SPI1) interrupt source identity
0x3C
read-only
n
0x0
0x0
SPI1_INT
Identify SPI1 interrupt source.
0
1
read-only
IRQ16_SRC
IRQ16_SRC
IRQ16 (SPI2) interrupt source identity
0x40
read-only
n
0x0
0x0
SPI2_INT
Identify SPI2 interrupt source.
0
1
read-only
IRQ17_SRC
IRQ17_SRC
IRQ17 (MDU) interrupt source identity
0x44
read-only
n
0x0
0x0
MDU_INT
Identify MDU interrupt source.
0
1
read-only
IRQ18_SRC
IRQ18_SRC
IRQ18 (I2C) interrupt source identity
0x48
read-only
n
0x0
0x0
I2C_INT
Identify I2C0 interrupt source.
0
1
read-only
IRQ19_SRC
IRQ19_SRC
IRQ19 (Reserved) interrupt source identity
0x4C
read-only
n
0x0
0x0
IRQ1_SRC
IRQ1_SRC
IRQ1 (WDT) interrupt source identity
0x4
read-only
n
0x0
0x0
WDT_INT
Identify WDT interrupt source.
0
1
read-only
IRQ20_SRC
IRQ20_SRC
IRQ20 (CAN) interrupt source identity
0x50
read-only
n
0x0
0x0
CAN_INT
Identify CAN interrupt source.
0
1
read-only
IRQ21_SRC
IRQ21_SRC
IRQ21 (EPWM0) interrupt source identity
0x54
read-only
n
0x0
0x0
EPWM0_INT
Identify EPWM0 interrupt source.
0
1
read-only
IRQ22_SRC
IRQ22_SRC
IRQ22 (EPWM1) interrupt source identity
0x58
read-only
n
0x0
0x0
EPWM1_INT
Identify EPWM1 interrupt source.
0
1
read-only
IRQ23_SRC
IRQ23_SRC
IRQ23 (CAP0) interrupt source identity
0x5C
read-only
n
0x0
0x0
CAP0_INT
Identify CAP0 interrupt source.
0
1
read-only
IRQ24_SRC
IRQ24_SRC
IRQ24 (CAP1) interrupt source identity
0x60
read-only
n
0x0
0x0
CAP1_INT
Identify CAP1 interrupt source.
0
1
read-only
IRQ25_SRC
IRQ25_SRC
IRQ25 (ACMP) interrupt source identity
0x64
read-only
n
0x0
0x0
ACMP_INT
Identify ACMP interrupt source.
0
1
read-only
IRQ26_SRC
IRQ26_SRC
IRQ26 (QEI0) interrupt source identity
0x68
read-only
n
0x0
0x0
QEI0_INT
Identify QEI0 interrupt source.
0
1
read-only
IRQ27_SRC
IRQ27_SRC
IRQ27 (QEI1) interrupt source identity
0x6C
read-only
n
0x0
0x0
QEI1_INT
Identify QEI1 interrupt source.
0
1
read-only
IRQ28_SRC
IRQ28_SRC
IRQ28 (PWRWU) interrupt source identity
0x70
read-only
n
0x0
0x0
PWRWU_INT
Identify PWRWU interrupt source.
0
1
read-only
IRQ29_SRC
IRQ29_SRC
IRQ29 (ADC1) interrupt source identity
0x74
read-only
n
0x0
0x0
ADC1_INT
Identify ADC1 interrupt source.
0
1
read-only
IRQ2_SRC
IRQ2_SRC
IRQ2 (EINT0) interrupt source identity
0x8
read-only
n
0x0
0x0
EINT0
Identify EINT0 interrupt source.\nEINT0 is external interrupt 0 from P3.2.
0
1
read-only
IRQ30_SRC
IRQ30_SRC
IRQ30 (ADC2) interrupt source identity
0x78
read-only
n
0x0
0x0
ADC2_INT
Identify ADC2 interrupt source.
0
1
read-only
IRQ31_SRC
IRQ31_SRC
IRQ31 (ADC3) interrupt source identity
0x7C
read-only
n
0x0
0x0
ADC3_INT
Identify ADC3 interrupt source.
0
1
read-only
IRQ3_SRC
IRQ3_SRC
IRQ3 (EINT1) interrupt source identity
0xC
read-only
n
0x0
0x0
EINT1
Identify EINT1 interrupt source.\nEINT1 is external interrupt from P3.3.
0
1
read-only
IRQ4_SRC
IRQ4_SRC
IRQ4 (P0-P4) interrupt source identity
0x10
read-only
n
0x0
0x0
P0_INT
Identify P0 interrupt source.
0
1
read-only
P1_INT
Identify P1 interrupt source.
1
1
read-only
P2_INT
Identify P2 interrupt source.
2
1
read-only
P3_INT
Identify P3 interrupt source.
3
1
read-only
P4_INT
Identify P4 interrupt source.
4
1
read-only
IRQ5_SRC
IRQ5_SRC
IRQ5 (P5-PA) interrupt source identity
0x14
read-only
n
0x0
0x0
P5_INT
Identify P5 interrupt source.
0
1
read-only
P6_INT
Identify P6 interrupt source.
1
1
read-only
P7_INT
Identify P7 interrupt source.
2
1
read-only
P8_INT
Identify P8 interrupt source.
3
1
read-only
P9_INT
Identify P9 interrupt source.
4
1
read-only
PA_INT
Identify PA interrupt source.
5
1
read-only
IRQ6_SRC
IRQ6_SRC
IRQ6 (BPWM) interrupt source identity
0x18
read-only
n
0x0
0x0
BPWM0_INT
Identify BPWM0 interrupt source.
0
1
read-only
BPWM1_INT
Identify BPWM1 interrupt source.
1
1
read-only
IRQ7_SRC
IRQ7_SRC
IRQ7 (ADC0) interrupt source identity
0x1C
read-only
n
0x0
0x0
ADC0_INT
Identify ADC0 interrupt source.
0
1
read-only
IRQ8_SRC
IRQ8_SRC
IRQ8 (TMR0) interrupt source identity
0x20
read-only
n
0x0
0x0
TMR0_INT
Identify TMR0 interrupt source.
0
1
read-only
IRQ9_SRC
IRQ9_SRC
IRQ9 (TMR1) interrupt source identity
0x24
read-only
n
0x0
0x0
TMR1_INT
Identify TMR1 interrupt source.
0
1
read-only
MCU_IRQ
MCU_IRQ
MCU interrupt request source register
0x84
read-write
n
0x0
0x0
MCU_IRQ
MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0:
0
32
read-write
0
No effect
0
1
Generate an interrupt to Cortex_M0 NVIC[n].\nClear the interrupt and MCU_IRQ[n]
1
NMI_CON
NMI_CON
NMI interrupt control register
0x80
read-write
n
0x0
0x0
NMI_EN
NMI Interrupt Enable
8
1
read-write
0
IRQ0~31 assigned to NMI Disabled. (NMI still can be software triggered by setting its pending flag.)
#0
1
IRQ0~31 assigned to NMI Enabled
#1
NMI_SEL
NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number. The default NMI interrupt is assigned as IRQ0 interrupt if NMI is enabled by setting NMI_SEL[8].
0
5
read-write
MDU0
MDU Register Map
MDU
0x0
0x0
0x88
registers
n
0x100
0x3C
registers
n
COS
COS
0x18
read-write
n
0x0
0x0
Ia
Ia
Phase A Current Register, Represented in Q-15 Format
0x0
read-write
n
0x0
0x0
DATA
Motor Phase Current Data Register\nThis register stores the phase current data represented in Q-15 format. \nThe MCU must update registers Ia, Ib and Ic in the beginning of a FOC process flow.
0
16
read-write
Ialfa
Ialfa
Clarke Transformation Output Register, the Current Along alpha-axis
0xC
read-write
n
0x0
0x0
DATA
Clarke Transformation Output Data Register\nThis data content is produced by Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Ib
Ib
0x4
read-write
n
0x0
0x0
Ibeta
Ibeta
0x10
read-write
n
0x0
0x0
Ic
Ic
0x8
read-write
n
0x0
0x0
Id
Id
Park Transformation Output Register, the Current Along d-axis.
0x1C
read-write
n
0x0
0x0
DATA
Park Transformation Output Data Register\nThis data content is produced by Park Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Id_CMD
Id_CMD
PI_d Controller Command Input Register, Represented in Q-15 Format.
0x24
read-write
n
0x0
0x0
CMD
PI Controller Command Input Register\nThe register content stands for the PI controller command input. It must be normalized in Q-15 format.
0
16
read-write
Id_Err
Id_Err
Error of Id current = Id_CMD - Id Read only
0x134
-1
read-only
n
0x0
0x0
Iq
Iq
0x20
read-write
n
0x0
0x0
Iq_CMD
Iq_CMD
0x28
read-write
n
0x0
0x0
Iq_Err
Iq_Err
Error of Id current = Iq_CMD - Iq Read only.
0x138
-1
read-only
n
0x0
0x0
I_dMAX
I_dMAX
Maximum limit value of integral_d Controller in Q-15 Format
0x110
-1
read-write
n
0x0
0x0
MAX
Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the integral controller output.
0
16
read-write
I_dMIN
I_dMIN
Minimum limit value of integral_d Controller in Q-15 Format
0x114
-1
read-write
n
0x0
0x0
MIN
Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the integral controller output.
0
16
read-write
I_qMAX
I_qMAX
0x118
read-write
n
0x0
0x0
I_qMIN
I_qMIN
0x11C
read-write
n
0x0
0x0
KI_d
KI_d
0x30
read-write
n
0x0
0x0
KI_q
KI_q
0x38
read-write
n
0x0
0x0
KP_d
KP_d
Parameter KP for PI_d Controller, Represented in 18-bit I2Q-15 (Q2.15) Format
0x2C
read-write
n
0x0
0x0
DATA
PI Controller Parameter Register\nThe KP_d and KP_q stand for the proportional parameter of PI controller, the KI_d and KI_q stand for the integral parameter of PI controller. The register data value must be stored in Q-15 format.
0
18
read-write
KP_q
KP_q
0x34
read-write
n
0x0
0x0
MDUCON
MDUCON
Motor Driver Unit Control Register
0x80
read-write
n
0x0
0x0
ATCLRFG
Auto-Clear Flag Control Bit
When this bit is set to high, the complete flag of each function block in auto-mode is cleared automatically after SVPWM function block has updated PWM duty registers. The auto-clear flag function helps the FOC control flow runs smoothly without the need of software clearing flags.
16
1
read-write
0
Auto-clear flag function Disabled
#0
1
Auto-clear flag function Enabled
#1
CKSTR
Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
0
1
write-only
0
No action
#0
1
Start the process
#1
CK_IE
Clark Block Interrupt Enable Bit
24
1
read-write
0
Clark block interrupt Disabled
#0
1
Clark block interrupt Enabled
#1
INVCKAUTO
Inverse Clarke Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
13
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
INVCKSTR
Inverse Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
5
1
write-only
0
No action
#0
1
Start the process
#1
INVCK_IE
Inv-Clark Block Interrupt Enable Bit
29
1
read-write
0
Inv-Clark block interrupt Disabled
#0
1
Inv-Clark block interrupt Enabled
#1
INVPKAUTO
Inverse Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
12
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
INVPKSTR
Inverse Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
4
1
write-only
0
No action
#0
1
Start the process
#1
INVPK_IE
Inv-Park Block Interrupt Enable Bit
28
1
read-write
0
Inv-Park block interrupt Disabled
#0
1
Inv-Park block interrupt Enabled
#1
MDU_IE
MDU Interrupt Enable Bit
31
1
read-write
0
MDU interrupt Disabled
#0
1
MDU interrupt Enabled
#1
PIDAUTO
D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
10
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PIDSTR
D-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding D-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
2
1
write-only
0
No action
#0
1
Start the process
#1
PID_IE
D-axis PI Block Interrupt Enable Bit
26
1
read-write
0
D-axis PI controller block interrupt Disabled
#0
1
D-axis PI controller block interrupt Enabled
#1
PIQAUTO
D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
11
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PIQSTR
Q-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Q-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
3
1
write-only
0
No action
#0
1
Start the process
#1
PIQ_IE
Q-axis PI Block Interrupt Enable Bit
27
1
read-write
0
Q-axis PI controller block interrupt Disabled
#0
1
Q-axis PI controller block interrupt Enabled
#1
PKAUTO
Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
9
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PKSTR
Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
1
1
write-only
0
No action
#0
1
Start the process
#1
PK_IE
Park Block Interrupt Enable Bit
25
1
read-write
0
Park block interrupt Disabled
#0
1
Park block interrupt Enabled
#1
SVPWMAUTO
SVPWM Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the SVPWM function block is allowed to accept the start trigger from Inverse Clarke block and SVPWM function proceeds completed, it will automatically update the duty registers in PWM unit0 and set the reload bit (LOAD).
14
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
SVPWMSTR
SVPWM Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding SVPWM timing calculating and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
6
1
write-only
0
No action
#0
1
Start the process
#1
SVPWM_DIS
SVPWM Block Function Disable Bit
17
1
read-write
0
SVPWM function block produces the Space Vector PWM timing for PWM duty registers
#0
1
SVPWM operation Disabled
#1
SVPWM_IE
Clark Block Interrupt Enable Bit
30
1
read-write
0
SVPWM block interrupt Disabled
#0
1
SVPWM block interrupt Enabled. Interrupt will generate if MDUINT_EN and SVPWM_IE is set to 1 and SVPWMCPF is set
#1
MDUSTS
MDUSTS
Motor Driver Unit Status Register
0x84
-1
read-write
n
0x0
0x0
CKCPF
Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and CKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
0
1
read-write
INVCKCPF
Inverse Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVCKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
5
1
read-write
INVPKCPF
Inverse Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVPKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
4
1
read-write
PI_dCPF
PI_d Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_dAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
3
1
read-write
PI_qCPF
PI_q Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_qAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
2
1
read-write
PKCPF
Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
1
1
read-write
SVPWMCPF
SVPWM Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and SVPWMAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
6
1
read-write
ZONE
Zone Number Indicator\nA 360 degree space is equally divided into six zones where each zone is with 60 degree space. The SVPWM function block will internally produce the zone number during the operation which indicates the which zone the motor electric angle stays in the moment.
8
3
read-write
PI_dFW
PI_dFW
PI_d Controller Feed Forward Data Register
0x3C
read-write
n
0x0
0x0
DATA
PI Controller Feed Forward Data Register\nSoftware presets the feed forward value of the PI controller in this register.
0
16
read-write
PI_dMAX
PI_dMAX
Maximum limit value of PI_d Controller in Q-15 Format
0x100
-1
read-write
n
0x0
0x0
MAX
Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the PI controller and I controller output.
0
16
read-write
PI_dMIN
PI_dMIN
Minimum limit value of PI_d Controller in Q-15 Format
0x104
-1
read-write
n
0x0
0x0
MIN
Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the PI controller and I controller output.
0
16
read-write
PI_qFW
PI_qFW
0x40
read-write
n
0x0
0x0
PI_qMAX
PI_qMAX
0x108
read-write
n
0x0
0x0
PI_qMIN
PI_qMIN
0x10C
read-write
n
0x0
0x0
PWMMAX
PWMMAX
An unsigned 16-bit Maximum Limit Value of SVPWM Output
0x12C
-1
read-write
n
0x0
0x0
PWMMAX
Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
PWMMIN
PWMMIN
An unsigned 16-bit Minimum Limit Value of SVPWM Output
0x130
read-write
n
0x0
0x0
PWMMIN
Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
PWMNORM
PWMNORM
An Unsigned 16-bit PWM Normalization Value
0x128
read-write
n
0x0
0x0
PWMNORM
PWM Normalization Data\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
SIN
SIN
Trigonometric Value of SIN Register, Represented in Q-15 Format
0x14
read-write
n
0x0
0x0
DATA
Trigonometric Value of SIN / COS Data Register\nThe trigonometric value of SIN and COS, which is represented in Q-15 format, must be preset before operating Park and inverse Park transformation.
0
16
read-write
SVPDATA0
SVPDATA0
SVPWM output Data Register (it is an unsigned 16-bit value and denotes Taon time)
0x68
read-write
n
0x0
0x0
DATA
SVPWM Output Data Register\nThis data content is produced by SVPWM function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
SVPDATA0N
SVPDATA0N
An unsigned16-bit data Normalizes SVPDATA0 to PWMNORM and within the limit between PWMMAX and PWMMIN
0x74
read-write
n
0x0
0x0
DATA
Normalized SVPDATA Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. If SVPWM function block auto mode is active, each new SVPDATA0N/2N/4N will be reload to PWM unit 0 duty registers PWM0/2/4 after SVPWM operation is completed if PWMRUN and LOAD bits are enabled in PWM unit 0. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
SVPDATA2
SVPDATA2
0x6C
read-write
n
0x0
0x0
SVPDATA2N
SVPDATA2N
0x78
read-write
n
0x0
0x0
SVPDATA4
SVPDATA4
0x70
read-write
n
0x0
0x0
SVPDATA4N
SVPDATA4N
0x7C
read-write
n
0x0
0x0
UI_d
UI_d
D-axis I Control Output Data Register
0x44
read-write
n
0x0
0x0
DATA
Integral Controller Output Data Register\nThe PI function block content I (Integral) controller and P (Propotional) controller, and I controller output data will be used as the next PI control flow. Here is the register to save the output data of I controller and will update when PI controller finished once operation. Here, the register content is a Q-15 format value.
0
16
read-write
UI_q
UI_q
0x48
read-write
n
0x0
0x0
Valfa
Valfa
Inverse Park Transformation Output, the Voltage Along the alpha-axis
0x54
read-write
n
0x0
0x0
DATA
Inverse Park Transformation Output Data Register\nThis data content is produced by inverse Park Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vbeta
Vbeta
0x58
read-write
n
0x0
0x0
Vd
Vd
PI_d Controller Output of d-axis, Represented in Q-15 Format
0x4C
read-write
n
0x0
0x0
DATA
PI Controller Output Data Register (Inverse Park Transformation Input)\nThis data content is produced by PI controller function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vd_In
Vd_In
Inverse Park Transformation Input of d_axis represented in Q-15 Format
0x120
read-only
n
0x0
0x0
DATA
Inverse Park Transformation Input Data (Read Only)\nThis data content is produced by the PI controller with maximum and minimum limit operation and stored in Q-15 format. It is a read only register
0
16
read-only
Vq
Vq
0x50
read-write
n
0x0
0x0
Vq_In
Vq_In
0x124
read-write
n
0x0
0x0
Vref1
Vref1
Inverse Clarke Transformation Output Register
0x5C
read-write
n
0x0
0x0
DATA
Inverse Clarke Transformation Output Data Register\nThis data content is produced by inverse Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vref2
Vref2
0x60
read-write
n
0x0
0x0
Vref3
Vref3
0x64
read-write
n
0x0
0x0
MDU1
MDU Register Map
MDU
0x0
0x0
0x88
registers
n
0x100
0x3C
registers
n
COS
COS
0x18
read-write
n
0x0
0x0
Ia
Ia
Phase A Current Register, Represented in Q-15 Format
0x0
read-write
n
0x0
0x0
DATA
Motor Phase Current Data Register\nThis register stores the phase current data represented in Q-15 format. \nThe MCU must update registers Ia, Ib and Ic in the beginning of a FOC process flow.
0
16
read-write
Ialfa
Ialfa
Clarke Transformation Output Register, the Current Along alpha-axis
0xC
read-write
n
0x0
0x0
DATA
Clarke Transformation Output Data Register\nThis data content is produced by Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Ib
Ib
0x4
read-write
n
0x0
0x0
Ibeta
Ibeta
0x10
read-write
n
0x0
0x0
Ic
Ic
0x8
read-write
n
0x0
0x0
Id
Id
Park Transformation Output Register, the Current Along d-axis.
0x1C
read-write
n
0x0
0x0
DATA
Park Transformation Output Data Register\nThis data content is produced by Park Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Id_CMD
Id_CMD
PI_d Controller Command Input Register, Represented in Q-15 Format.
0x24
read-write
n
0x0
0x0
CMD
PI Controller Command Input Register\nThe register content stands for the PI controller command input. It must be normalized in Q-15 format.
0
16
read-write
Id_Err
Id_Err
Error of Id current = Id_CMD - Id Read only
0x134
-1
read-only
n
0x0
0x0
Iq
Iq
0x20
read-write
n
0x0
0x0
Iq_CMD
Iq_CMD
0x28
read-write
n
0x0
0x0
Iq_Err
Iq_Err
Error of Id current = Iq_CMD - Iq Read only.
0x138
-1
read-only
n
0x0
0x0
I_dMAX
I_dMAX
Maximum limit value of integral_d Controller in Q-15 Format
0x110
-1
read-write
n
0x0
0x0
MAX
Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the integral controller output.
0
16
read-write
I_dMIN
I_dMIN
Minimum limit value of integral_d Controller in Q-15 Format
0x114
-1
read-write
n
0x0
0x0
MIN
Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the integral controller output.
0
16
read-write
I_qMAX
I_qMAX
0x118
read-write
n
0x0
0x0
I_qMIN
I_qMIN
0x11C
read-write
n
0x0
0x0
KI_d
KI_d
0x30
read-write
n
0x0
0x0
KI_q
KI_q
0x38
read-write
n
0x0
0x0
KP_d
KP_d
Parameter KP for PI_d Controller, Represented in 18-bit I2Q-15 (Q2.15) Format
0x2C
read-write
n
0x0
0x0
DATA
PI Controller Parameter Register\nThe KP_d and KP_q stand for the proportional parameter of PI controller, the KI_d and KI_q stand for the integral parameter of PI controller. The register data value must be stored in Q-15 format.
0
18
read-write
KP_q
KP_q
0x34
read-write
n
0x0
0x0
MDUCON
MDUCON
Motor Driver Unit Control Register
0x80
read-write
n
0x0
0x0
ATCLRFG
Auto-Clear Flag Control Bit
When this bit is set to high, the complete flag of each function block in auto-mode is cleared automatically after SVPWM function block has updated PWM duty registers. The auto-clear flag function helps the FOC control flow runs smoothly without the need of software clearing flags.
16
1
read-write
0
Auto-clear flag function Disabled
#0
1
Auto-clear flag function Enabled
#1
CKSTR
Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
0
1
write-only
0
No action
#0
1
Start the process
#1
CK_IE
Clark Block Interrupt Enable Bit
24
1
read-write
0
Clark block interrupt Disabled
#0
1
Clark block interrupt Enabled
#1
INVCKAUTO
Inverse Clarke Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
13
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
INVCKSTR
Inverse Clarke Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Clarke Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
5
1
write-only
0
No action
#0
1
Start the process
#1
INVCK_IE
Inv-Clark Block Interrupt Enable Bit
29
1
read-write
0
Inv-Clark block interrupt Disabled
#0
1
Inv-Clark block interrupt Enabled
#1
INVPKAUTO
Inverse Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
12
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
INVPKSTR
Inverse Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Inverse Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
4
1
write-only
0
No action
#0
1
Start the process
#1
INVPK_IE
Inv-Park Block Interrupt Enable Bit
28
1
read-write
0
Inv-Park block interrupt Disabled
#0
1
Inv-Park block interrupt Enabled
#1
MDU_IE
MDU Interrupt Enable Bit
31
1
read-write
0
MDU interrupt Disabled
#0
1
MDU interrupt Enabled
#1
PIDAUTO
D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
10
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PIDSTR
D-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding D-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
2
1
write-only
0
No action
#0
1
Start the process
#1
PID_IE
D-axis PI Block Interrupt Enable Bit
26
1
read-write
0
D-axis PI controller block interrupt Disabled
#0
1
D-axis PI controller block interrupt Enabled
#1
PIQAUTO
D-axis PI Controller Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
11
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PIQSTR
Q-axis PI Controller Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Q-axis PI Control and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
3
1
write-only
0
No action
#0
1
Start the process
#1
PIQ_IE
Q-axis PI Block Interrupt Enable Bit
27
1
read-write
0
Q-axis PI controller block interrupt Disabled
#0
1
Q-axis PI controller block interrupt Enabled
#1
PKAUTO
Park Transformation Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the current function block is allowed to accept the previous start trigger and will trigger the start bit of the next function block after current function is completed.
9
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
PKSTR
Park Transformation Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding Park Transformation and it is automatically cleared when the transform process is completed by hardware. Writing it to 0 will stop and reset the function block.
1
1
write-only
0
No action
#0
1
Start the process
#1
PK_IE
Park Block Interrupt Enable Bit
25
1
read-write
0
Park block interrupt Disabled
#0
1
Park block interrupt Enabled
#1
SVPWMAUTO
SVPWM Auto-mode Enable Bit\nSetting this bit will enable auto-mode of the function block. If the auto-mode is active, the SVPWM function block is allowed to accept the start trigger from Inverse Clarke block and SVPWM function proceeds completed, it will automatically update the duty registers in PWM unit0 and set the reload bit (LOAD).
14
1
read-write
0
Auto-mode Disabled
#0
1
Auto-mode Enabled
#1
SVPWMSTR
SVPWM Start Bit (Write Only, Read 0)\nSetting this bit to high will start proceeding SVPWM timing calculating and it is automatically cleared when the process is completed by hardware. Writing it to 0 will stop and reset the function block.
6
1
write-only
0
No action
#0
1
Start the process
#1
SVPWM_DIS
SVPWM Block Function Disable Bit
17
1
read-write
0
SVPWM function block produces the Space Vector PWM timing for PWM duty registers
#0
1
SVPWM operation Disabled
#1
SVPWM_IE
Clark Block Interrupt Enable Bit
30
1
read-write
0
SVPWM block interrupt Disabled
#0
1
SVPWM block interrupt Enabled. Interrupt will generate if MDUINT_EN and SVPWM_IE is set to 1 and SVPWMCPF is set
#1
MDUSTS
MDUSTS
Motor Driver Unit Status Register
0x84
-1
read-write
n
0x0
0x0
CKCPF
Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and CKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
0
1
read-write
INVCKCPF
Inverse Clarke Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVCKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
5
1
read-write
INVPKCPF
Inverse Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and INVPKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
4
1
read-write
PI_dCPF
PI_d Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_dAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
3
1
read-write
PI_qCPF
PI_q Controller Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PI_qAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
2
1
read-write
PKCPF
Park Transformation Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and PKAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
1
1
read-write
SVPWMCPF
SVPWM Complete Flag\nWhen the function block completes the process, the corresponding complete flag will be set by hardware. This flag can be cleared by a writing one to itself.\nNote: If both the control bits ATCLRFG (Auto-clear flag control bit) and SVPWMAUTO (Auto-mode enable bit) are set to high, the complete flag is cleared automatically after SVPWM function block has set PWM LOAD bit to high.
6
1
read-write
ZONE
Zone Number Indicator\nA 360 degree space is equally divided into six zones where each zone is with 60 degree space. The SVPWM function block will internally produce the zone number during the operation which indicates the which zone the motor electric angle stays in the moment.
8
3
read-write
PI_dFW
PI_dFW
PI_d Controller Feed Forward Data Register
0x3C
read-write
n
0x0
0x0
DATA
PI Controller Feed Forward Data Register\nSoftware presets the feed forward value of the PI controller in this register.
0
16
read-write
PI_dMAX
PI_dMAX
Maximum limit value of PI_d Controller in Q-15 Format
0x100
-1
read-write
n
0x0
0x0
MAX
Maximum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the maximum value of the PI controller and I controller output.
0
16
read-write
PI_dMIN
PI_dMIN
Minimum limit value of PI_d Controller in Q-15 Format
0x104
-1
read-write
n
0x0
0x0
MIN
Minimum Limit of PI Controller and I Controller Output\nThe 16-bit value represented in Q-15 format limits the minimum value of the PI controller and I controller output.
0
16
read-write
PI_qFW
PI_qFW
0x40
read-write
n
0x0
0x0
PI_qMAX
PI_qMAX
0x108
read-write
n
0x0
0x0
PI_qMIN
PI_qMIN
0x10C
read-write
n
0x0
0x0
PWMMAX
PWMMAX
An unsigned 16-bit Maximum Limit Value of SVPWM Output
0x12C
-1
read-write
n
0x0
0x0
PWMMAX
Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
PWMMIN
PWMMIN
An unsigned 16-bit Minimum Limit Value of SVPWM Output
0x130
read-write
n
0x0
0x0
PWMMIN
Maximum Limit of SVPWM Output Data Register\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
PWMNORM
PWMNORM
An Unsigned 16-bit PWM Normalization Value
0x128
read-write
n
0x0
0x0
PWMNORM
PWM Normalization Data\nThe SVPWM function block will normalize the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
SIN
SIN
Trigonometric Value of SIN Register, Represented in Q-15 Format
0x14
read-write
n
0x0
0x0
DATA
Trigonometric Value of SIN / COS Data Register\nThe trigonometric value of SIN and COS, which is represented in Q-15 format, must be preset before operating Park and inverse Park transformation.
0
16
read-write
SVPDATA0
SVPDATA0
SVPWM output Data Register (it is an unsigned 16-bit value and denotes Taon time)
0x68
read-write
n
0x0
0x0
DATA
SVPWM Output Data Register\nThis data content is produced by SVPWM function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
SVPDATA0N
SVPDATA0N
An unsigned16-bit data Normalizes SVPDATA0 to PWMNORM and within the limit between PWMMAX and PWMMIN
0x74
read-write
n
0x0
0x0
DATA
Normalized SVPDATA Register\nThe SVPWM function block will normalizes the value of SVP0/2/4 to the range between 0000h and the value of PWMNORM and limit the PWM duty value within PWMMAX and PWMMIN. If SVPWM function block auto mode is active, each new SVPDATA0N/2N/4N will be reload to PWM unit 0 duty registers PWM0/2/4 after SVPWM operation is completed if PWMRUN and LOAD bits are enabled in PWM unit 0. Here, the register content is a 16-bit unsigned integer.
0
16
read-write
SVPDATA2
SVPDATA2
0x6C
read-write
n
0x0
0x0
SVPDATA2N
SVPDATA2N
0x78
read-write
n
0x0
0x0
SVPDATA4
SVPDATA4
0x70
read-write
n
0x0
0x0
SVPDATA4N
SVPDATA4N
0x7C
read-write
n
0x0
0x0
UI_d
UI_d
D-axis I Control Output Data Register
0x44
read-write
n
0x0
0x0
DATA
Integral Controller Output Data Register\nThe PI function block content I (Integral) controller and P (Propotional) controller, and I controller output data will be used as the next PI control flow. Here is the register to save the output data of I controller and will update when PI controller finished once operation. Here, the register content is a Q-15 format value.
0
16
read-write
UI_q
UI_q
0x48
read-write
n
0x0
0x0
Valfa
Valfa
Inverse Park Transformation Output, the Voltage Along the alpha-axis
0x54
read-write
n
0x0
0x0
DATA
Inverse Park Transformation Output Data Register\nThis data content is produced by inverse Park Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vbeta
Vbeta
0x58
read-write
n
0x0
0x0
Vd
Vd
PI_d Controller Output of d-axis, Represented in Q-15 Format
0x4C
read-write
n
0x0
0x0
DATA
PI Controller Output Data Register (Inverse Park Transformation Input)\nThis data content is produced by PI controller function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vd_In
Vd_In
Inverse Park Transformation Input of d_axis represented in Q-15 Format
0x120
read-only
n
0x0
0x0
DATA
Inverse Park Transformation Input Data (Read Only)\nThis data content is produced by the PI controller with maximum and minimum limit operation and stored in Q-15 format. It is a read only register
0
16
read-only
Vq
Vq
0x50
read-write
n
0x0
0x0
Vq_In
Vq_In
0x124
read-write
n
0x0
0x0
Vref1
Vref1
Inverse Clarke Transformation Output Register
0x5C
read-write
n
0x0
0x0
DATA
Inverse Clarke Transformation Output Data Register\nThis data content is produced by inverse Clarke Transformation function block and stored in Q-15 format. It is also writable by software.
0
16
read-write
Vref2
Vref2
0x60
read-write
n
0x0
0x0
Vref3
Vref3
0x64
read-write
n
0x0
0x0
MDUG
MDU Register Map
MDU
0x0
0x0
0x8
registers
n
MDUSCON
MDUSCON
MDU Switch Control
0x0
read-write
n
0x0
0x0
MDUS
MDU Switch Control Register
0
1
read-write
0
MDU is controlled by MDU0 control register
#0
1
MDU is controlled by MDU1 control register
#1
MDUSSTS
MDUSSTS
MDU Switch Status
0x4
read-write
n
0x0
0x0
MDU0BUSY
MDU0 Busy Register
0
1
read-write
0
MDU0 is idle
#0
1
MDU0 is busy
#1
MDU1BUSY
MDU1 Busy Register
1
1
read-write
0
MDU1 is idle
#0
1
MDU1 is busy
#1
MDUACT
MDU Active Set
2
1
read-write
0
MDU0 is active
#0
1
MDU1 is active
#1
NVIC
NVIC Register Map
NVIC
0x0
0x0
0x4
registers
n
0x100
0x4
registers
n
0x180
0x4
registers
n
0x300
0x20
registers
n
0x80
0x4
registers
n
ICER
NVIC_ICER
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x80
read-write
n
0x0
0x0
CLRENA
Interrupt Clear Enable\nThe ICER disables interrupts, and shows the interrupts that are enabled. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Disabled.\nInterrupt Enabled
1
ICPR
NVIC_ICPR
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x180
read-write
n
0x0
0x0
CLRPEND
Interrupt clear-pending.\nThe ICPR removes the pending state from interrupts, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
0
32
read-write
0
no effect.\ninterrupt is not pending
0
1
removes pending state an interrupt.\ninterrupt is pending
1
IPR0
NVIC_IPR0
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x300
read-write
n
0x0
0x0
PRI_0
Priority of IRQ0\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_1
Priority of IRQ1\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_2
Priority of IRQ2\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_3
Priority of IRQ3\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR1
NVIC_IPR1
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x304
read-write
n
0x0
0x0
PRI_4
Priority of IRQ4\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_5
Priority of IRQ5\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_6
Priority of IRQ6\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_7
Priority of IRQ7\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR2
NVIC_IPR2
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x308
read-write
n
0x0
0x0
PRI_10
Priority of IRQ10\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_11
Priority of IRQ11\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
PRI_8
Priority of IRQ8\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_9
Priority of IRQ9\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
IPR3
NVIC_IPR3
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x30C
read-write
n
0x0
0x0
PRI_12
Priority of IRQ12\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_13
Priority of IRQ13\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_14
Priority of IRQ14\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_15
Priority of IRQ15\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR4
NVIC_IPR4
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x310
read-write
n
0x0
0x0
PRI_16
Priority of IRQ16\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_17
Priority of IRQ17\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_18
Priority of IRQ18\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_19
Priority of IRQ19\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR5
NVIC_IPR5
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x314
read-write
n
0x0
0x0
PRI_20
Priority of IRQ20\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_21
Priority of IRQ21\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_22
Priority of IRQ22\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_23
Priority of IRQ23\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR6
NVIC_IPR6
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x318
read-write
n
0x0
0x0
PRI_24
Priority of IRQ24\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_25
Priority of IRQ25\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_26
Priority of IRQ26\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_27
Priority of IRQ27\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
IPR7
NVIC_IPR7
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x31C
read-write
n
0x0
0x0
PRI_28
Priority of IRQ28\n'0' denotes the highest priority and '3' denotes lowest priority
6
2
read-write
PRI_29
Priority of IRQ29\n'0' denotes the highest priority and '3' denotes lowest priority
14
2
read-write
PRI_30
Priority of IRQ30\n'0' denotes the highest priority and '3' denotes lowest priority
22
2
read-write
PRI_31
Priority of IRQ31\n'0' denotes the highest priority and '3' denotes lowest priority
30
2
read-write
ISER
NVIC_ISER
IRQ0 ~ IRQ31 Set-Enable Control Register
0x0
read-write
n
0x0
0x0
SETENA
Interrupt Enable\nThe ISER enables interrupts, and shows the interrupts that are enabled. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
0
32
read-write
0
No effect.\nInterrupt Disabled
0
1
Interrupt Enabled
1
ISPR
NVIC_ISPR
IRQ0 ~ IRQ31 Set-Pending Control Register
0x100
read-write
n
0x0
0x0
SETPEND
Interrupt set-pending.\nThe ISPR forces interrupts into the pending state, and shows the interrupts that are pending. Each bit represents an IRQ number from IRQ0 ~ IRQ31 (Exception number from 16 ~ 47).\nWrite:
0
32
read-write
0
no effect.\ninterrupt is not pending
0
1
changes interrupt state to pending.\ninterrupt is pending
1
OPA
OPA Register Map
OPA
0x0
0x0
0x8
registers
n
OPACR
OPACR
OP Amplifier Control Register
0x0
read-write
n
0x0
0x0
OP0_EN
OP Amplifier 0 Enable\nThe OP Amplifier 0 output needs to wait stable 20 s after OP0_EN is first set.
0
1
read-write
0
OP Amplifier 0 Disabled
#0
1
OP Amplifier 0 Enabled
#1
OP1_EN
OP Amplifier 1 Enable\nThe OP Amplifier 1 output needs to wait stable 20 s after OP1_EN is first set.
1
1
read-write
0
OP Amplifier 1 Disabled
#0
1
OP Amplifier 1 Enabled
#1
OPDIE0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable\nThe OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDIE0 is set to 1, a comparator interrupt request is generated.
8
1
read-write
0
OP Amplifier 0 digital output interrupt function Disabled
#0
1
OP Amplifier 0 digital output interrupt function Enabled
#1
OPDIE1
OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable\nThe OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDIE1 is set to 1, a comparator interrupt request is generated.
9
1
read-write
0
OP Amplifier 1 digital output interrupt function Disabled
#0
1
OP Amplifier 1 digital output interrupt function Enabled
#1
OPSCH0_EN
OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable
4
1
read-write
0
Disabled
#0
1
Enabled
#1
OPSCH1_EN
OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable
5
1
read-write
0
Disabled
#0
1
Enabled
#1
OPASR
OPASR
OP Amplifier Status Register
0x4
read-write
n
0x0
0x0
OPDF0
OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to itself.
4
1
read-write
OPDF1
OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to itself.
5
1
read-write
OPDO0
OP Amplifier 0 Digital Output
0
1
read-write
OPDO1
OP Amplifier 1 Digital Output
1
1
read-write
QEI0
QEI Register Map
QEI
0x0
0x0
0x10
registers
n
0x14
0x8
registers
n
0x2C
0x4
registers
n
QEI_CNT
QEI_CNT
QEI Pulse Counter
0x0
read-write
n
0x0
0x0
QEI_CNT
Quadrature Encoder Pulse Counter\nA 24-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIR in EQICTR is one or decreased by one if the bit DIR is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:
0
32
read-write
QEI_CNTCMP
QEI_CNTCMP
QEI Pulse Counter Compare Register
0xC
read-write
n
0x0
0x0
QEI_CNTCMP
Quadrature Encoder Pulse Counter Compare Register
0
32
read-write
QEI_CNTHLD
QEI_CNTHLD
QEI Pulse Counter Hold Register
0x4
read-write
n
0x0
0x0
QEI_CNTHLD
Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIxCTR[24]) goes from low to high, the QEPCNT value is copied into QEPCNTHLD register.
0
32
read-write
QEI_CNTILAT
QEI_CNTILAT
QEI Pulse Counter Index Latch Register
0x8
read-write
n
0x0
0x0
QEI_CNTILAT
Quadrature Encoder Pulse Counter Index Latch Register\nWhen bit IDXF (QEI_STS[18]) is set, the QEPI_CNT value is copied into QEI_CNTILAT register.
0
24
read-write
QEI_CTR
QEI_CTR
QEI Control Register
0x18
read-write
n
0x0
0x0
CMP_EN
The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEPCNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
28
1
read-write
0
The compare function Disabled
#0
1
The compare function Enabled
#1
CMP_IEN
Enable CMPF Trigger QEI Interrupt
18
1
read-write
0
The CMPF can trigger QEI controller interrupt Disabled
#0
1
The CMPF can trigger QEI controller interrupt Enabled
#1
DIR_IEN
Enable DIRF Trigger QEI Interrupt
17
1
read-write
0
The DIRF can trigger QEI controller interrupt Disabled
#0
1
The DIRF can trigger QEI controller interrupt Enabled
#1
HOLDBYT0
Hold QEI_CNT by Timer 0
20
1
read-write
0
TISR0.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR0.TIF in timer 0 sets HOLDCNT to 1
#1
HOLDBYT1
Hold QEI_CNT by Timer 1
21
1
read-write
0
TISR1.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR1.TIF in timer 1 sets HOLDCNT to 1
#1
HOLDBYT2
Hold QEI_CNT by Timer 2
22
1
read-write
0
TISR2.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR2.TIF in timer 2 sets HOLDCNT to 1
#1
HOLDBYT3
Hold QEI_CNT by Timer 3
23
1
read-write
0
TISR3.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR3.TIF in timer 3 sets HOLDCNT to 1
#1
HOLDCNT
Hold QEI_CNT Control Bit
When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHLD. This bit may be set by writing 1 to itself through software or Timer0~Timer3 interrupt flag (TISTR.TIF).
Note: This bit is automatically cleared after QEI_CNTHLD holds QEI_CNT value.
24
1
read-write
0
No operation
#0
1
QEI_CNT content captured and stored in QEI_CNTHLD
#1
IDXLAT
Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTILAT at every rising on signal CHX.
25
1
read-write
0
The index signal latch QEI counter function Disabled
#0
1
The index signal latch QEI counter function Enabled
#1
IDXRLD_EN
Index Trigger QEI_CNT Reload Enable Bit
27
1
read-write
0
The reload function Disabled
#0
1
The QEI_CNT re-initialized by Index signal Enabled
#1
IDX_EN
Enable IDX Input to QEI Controller
6
1
read-write
0
The IDX input to QEI Controller Disabled
#0
1
The IDX input to QEI Controller Enabled
#1
IDX_IEN
Enable IDXF Trigger QEI Interrupt
19
1
read-write
0
The IDXF can trigger QEI interrupt Disabled
#0
1
The IDXF can trigger QEI interrupt Enabled
#1
IDX_INV
Inverse IDX Input Polarity
14
1
read-write
0
Not inverse IDX input polarity
#0
1
IDX input polarity is inversed to QEI controller
#1
NFCLK_S
Noise Filter Clock Pre-divided Selection
0
2
read-write
OVUN_IEN
Enable OVUNF Trigger QEI Interrupt
16
1
read-write
0
The OVUNF can trigger QEI controller interrupt Disabled
#0
1
The OVUNF can trigger QEI controller interrupt Enabled
#1
QEA_EN
Enable QEA Input to QEI Controller
4
1
read-write
0
The QEA input to QEI Controller Disabled
#0
1
The QEA input to QEI Controller Enabled
#1
QEA_INV
Inverse QEA Input Polarity
12
1
read-write
0
Not inverse QEA input polarity
#0
1
QEA input polarity is inversed to QEI controller
#1
QEB_EN
Enable QEB Input to QEI Controller
5
1
read-write
0
The QEB input to QEI Controller Disabled
#0
1
The QEB input to QEI Controller Enabled
#1
QEB_INV
Inverse QEB Input Polarity
13
1
read-write
0
Not inverse QEB input polarity
#0
1
QEB input polarity is inversed to QEI controller
#1
QEIMODE
QEI Counting Mode Selection
8
2
read-write
QEINF_DIS
Disable QEI Controller Input Noise Filter
3
1
read-write
0
The noise filter of QEI controller Enabled
#0
1
The noise filter of QEI controller Disabled
#1
QEI_EN
Quadrature Encoder Interface Controller Enable Bit
29
1
read-write
0
QEI controller function Disabled
#0
1
QEI controller function Enabled
#1
QEI_MAXCNT
QEI_MAXCNT
QEI Pre-set Maximum Count Register
0x14
read-write
n
0x0
0x0
QEI_MAXCNT
Quadrature Encoder Preset Maximum Count Register\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
0
32
read-write
QEI_STS
QEI_STS
QEI Status Register
0x2C
read-write
n
0x0
0x0
CMPF
Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
1
1
read-write
0
QEI counter does not match with QEI_CNTCMP value
#0
1
QEI counter counts to the same as QEI_CNTCMP value
#1
DIR
QEI Counter Counting Direction Indication Bit\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
8
1
read-write
0
QEI Counter is in down-counting
#0
1
QEI Counter is in up-counting
#1
DIRF
Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed, software can clear this bit by writing a one to it.\nNote: This bit is only cleared by writing 1 to itself through software.
3
1
read-write
0
No change in QEI counter counting direction
#0
1
QEI counter counting direction is changed
#1
IDXF
IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to itself through software.
0
1
read-write
0
No rising edge detected on signal CHX
#0
1
A rising edge occurred on signal CHX
#1
OVUNF
QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to 0 in Free-counting mode or from the QEI_MAXCNT value to 0 in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from 0 to 0xFFFF_FFFF or QEI_MAXCNT.\nNote: This bit is only cleared by writing 1 to itself through software.
2
1
read-write
0
No overflow or underflow occurred in QEI counter
#0
1
QEI counter occurred counting overflow or underflow
#1
QEI1
QEI Register Map
QEI
0x0
0x0
0x10
registers
n
0x14
0x8
registers
n
0x2C
0x4
registers
n
QEI_CNT
QEI_CNT
QEI Pulse Counter
0x0
read-write
n
0x0
0x0
QEI_CNT
Quadrature Encoder Pulse Counter\nA 24-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIR in EQICTR is one or decreased by one if the bit DIR is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:
0
32
read-write
QEI_CNTCMP
QEI_CNTCMP
QEI Pulse Counter Compare Register
0xC
read-write
n
0x0
0x0
QEI_CNTCMP
Quadrature Encoder Pulse Counter Compare Register
0
32
read-write
QEI_CNTHLD
QEI_CNTHLD
QEI Pulse Counter Hold Register
0x4
read-write
n
0x0
0x0
QEI_CNTHLD
Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIxCTR[24]) goes from low to high, the QEPCNT value is copied into QEPCNTHLD register.
0
32
read-write
QEI_CNTILAT
QEI_CNTILAT
QEI Pulse Counter Index Latch Register
0x8
read-write
n
0x0
0x0
QEI_CNTILAT
Quadrature Encoder Pulse Counter Index Latch Register\nWhen bit IDXF (QEI_STS[18]) is set, the QEPI_CNT value is copied into QEI_CNTILAT register.
0
24
read-write
QEI_CTR
QEI_CTR
QEI Control Register
0x18
read-write
n
0x0
0x0
CMP_EN
The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEPCNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
28
1
read-write
0
The compare function Disabled
#0
1
The compare function Enabled
#1
CMP_IEN
Enable CMPF Trigger QEI Interrupt
18
1
read-write
0
The CMPF can trigger QEI controller interrupt Disabled
#0
1
The CMPF can trigger QEI controller interrupt Enabled
#1
DIR_IEN
Enable DIRF Trigger QEI Interrupt
17
1
read-write
0
The DIRF can trigger QEI controller interrupt Disabled
#0
1
The DIRF can trigger QEI controller interrupt Enabled
#1
HOLDBYT0
Hold QEI_CNT by Timer 0
20
1
read-write
0
TISR0.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR0.TIF in timer 0 sets HOLDCNT to 1
#1
HOLDBYT1
Hold QEI_CNT by Timer 1
21
1
read-write
0
TISR1.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR1.TIF in timer 1 sets HOLDCNT to 1
#1
HOLDBYT2
Hold QEI_CNT by Timer 2
22
1
read-write
0
TISR2.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR2.TIF in timer 2 sets HOLDCNT to 1
#1
HOLDBYT3
Hold QEI_CNT by Timer 3
23
1
read-write
0
TISR3.TIF has no effect on HOLDCNT
#0
1
A rising edge of bit TISR3.TIF in timer 3 sets HOLDCNT to 1
#1
HOLDCNT
Hold QEI_CNT Control Bit
When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHLD. This bit may be set by writing 1 to itself through software or Timer0~Timer3 interrupt flag (TISTR.TIF).
Note: This bit is automatically cleared after QEI_CNTHLD holds QEI_CNT value.
24
1
read-write
0
No operation
#0
1
QEI_CNT content captured and stored in QEI_CNTHLD
#1
IDXLAT
Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the QEI_CNT content will be latched into QEI_CNTILAT at every rising on signal CHX.
25
1
read-write
0
The index signal latch QEI counter function Disabled
#0
1
The index signal latch QEI counter function Enabled
#1
IDXRLD_EN
Index Trigger QEI_CNT Reload Enable Bit
27
1
read-write
0
The reload function Disabled
#0
1
The QEI_CNT re-initialized by Index signal Enabled
#1
IDX_EN
Enable IDX Input to QEI Controller
6
1
read-write
0
The IDX input to QEI Controller Disabled
#0
1
The IDX input to QEI Controller Enabled
#1
IDX_IEN
Enable IDXF Trigger QEI Interrupt
19
1
read-write
0
The IDXF can trigger QEI interrupt Disabled
#0
1
The IDXF can trigger QEI interrupt Enabled
#1
IDX_INV
Inverse IDX Input Polarity
14
1
read-write
0
Not inverse IDX input polarity
#0
1
IDX input polarity is inversed to QEI controller
#1
NFCLK_S
Noise Filter Clock Pre-divided Selection
0
2
read-write
OVUN_IEN
Enable OVUNF Trigger QEI Interrupt
16
1
read-write
0
The OVUNF can trigger QEI controller interrupt Disabled
#0
1
The OVUNF can trigger QEI controller interrupt Enabled
#1
QEA_EN
Enable QEA Input to QEI Controller
4
1
read-write
0
The QEA input to QEI Controller Disabled
#0
1
The QEA input to QEI Controller Enabled
#1
QEA_INV
Inverse QEA Input Polarity
12
1
read-write
0
Not inverse QEA input polarity
#0
1
QEA input polarity is inversed to QEI controller
#1
QEB_EN
Enable QEB Input to QEI Controller
5
1
read-write
0
The QEB input to QEI Controller Disabled
#0
1
The QEB input to QEI Controller Enabled
#1
QEB_INV
Inverse QEB Input Polarity
13
1
read-write
0
Not inverse QEB input polarity
#0
1
QEB input polarity is inversed to QEI controller
#1
QEIMODE
QEI Counting Mode Selection
8
2
read-write
QEINF_DIS
Disable QEI Controller Input Noise Filter
3
1
read-write
0
The noise filter of QEI controller Enabled
#0
1
The noise filter of QEI controller Disabled
#1
QEI_EN
Quadrature Encoder Interface Controller Enable Bit
29
1
read-write
0
QEI controller function Disabled
#0
1
QEI controller function Enabled
#1
QEI_MAXCNT
QEI_MAXCNT
QEI Pre-set Maximum Count Register
0x14
read-write
n
0x0
0x0
QEI_MAXCNT
Quadrature Encoder Preset Maximum Count Register\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode.
0
32
read-write
QEI_STS
QEI_STS
QEI Status Register
0x2C
read-write
n
0x0
0x0
CMPF
Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through software.
1
1
read-write
0
QEI counter does not match with QEI_CNTCMP value
#0
1
QEI counter counts to the same as QEI_CNTCMP value
#1
DIR
QEI Counter Counting Direction Indication Bit\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
8
1
read-write
0
QEI Counter is in down-counting
#0
1
QEI Counter is in up-counting
#1
DIRF
Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed, software can clear this bit by writing a one to it.\nNote: This bit is only cleared by writing 1 to itself through software.
3
1
read-write
0
No change in QEI counter counting direction
#0
1
QEI counter counting direction is changed
#1
IDXF
IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to itself through software.
0
1
read-write
0
No rising edge detected on signal CHX
#0
1
A rising edge occurred on signal CHX
#1
OVUNF
QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to 0 in Free-counting mode or from the QEI_MAXCNT value to 0 in compare-counting mode. Similarly, the flag is set wile QEI counter underflows from 0 to 0xFFFF_FFFF or QEI_MAXCNT.\nNote: This bit is only cleared by writing 1 to itself through software.
2
1
read-write
0
No overflow or underflow occurred in QEI counter
#0
1
QEI counter occurred counting overflow or underflow
#1
SCB
SCB Register Map
SCB
0x0
0x0
0x8
registers
n
0x1C
0x8
registers
n
0xC
0x8
registers
n
AIRCR
AIRCR
Application Interrupt and Reset Control Register
0xC
-1
read-write
n
0x0
0x0
SYSRESETREQ
System reset request. (Write only)
2
1
write-only
0
no effect
#0
1
requests a system level reset
#1
VECTKEY
Register key. (Write only)\nReads as Unknown. On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
16
16
write-only
CPUID
CPUID
CPUID Register
0x0
-1
read-only
n
0x0
0x0
Constant
Read as 0xC corresponding to ARMv6-M architecture.
16
4
read-only
Implementer
None
24
8
read-only
Partno
Reads as 0xC20 corresponding to Cortex-M0
4
12
read-only
Revision
Reads as 0x0.
0
4
read-only
Variant
Read as 0x0.
20
4
read-only
ICSR
ICSR
Interrupt Control State Register
0x4
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag. (Read only)\nIndicates if an external configurable (NVIC generated) interrupt is pending.
22
1
read-only
0
interrupt not pending
#0
1
interrupt pending
#1
NMIPENDSET
NMI set-pending bit.\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
31
1
read-write
0
no effect\nNMI exception is not pending
#0
1
changes NMI exception state to pending.\nNMI exception is pending
#1
PENDSTCLR
SysTick exception clear-pending bit. (Write only)\nWrite:
25
1
write-only
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick exception set-pending bit.\nWrite:
26
1
read-write
0
no effect.\nSysTick exception is not pending
#0
1
changes SysTick exception state to pending.\nSysTick exception is pending
#1
PENDSVCLR
PendSV clear-pending bit. (Write only)\nWrite:
27
1
write-only
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
28
1
read-write
0
no effect.\nPendSV exception is not pending
#0
1
changes PendSV exception state to pending.\nPendSV exception is pending
#1
VECTACTIVE
Vector active indicator. (Read only)\nThis field contains the active exception number:
0
6
read-only
0
Thread mode
0
VECTPENDING
Vector pending indicator. (Read only)\nThis field indicates the exception number of the highest priority pending enabled exception:
12
6
read-only
0
no pending exceptions
0
SCR
SCR
System Control Register
0x10
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
4
1
read-write
0
Oonly enabled interrupts or events can wake up the processor, disabled interrupts are excluded
#0
1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
#1
SLEEPDEEP
Deep Sleep Mode Enable\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:
2
1
read-write
0
Sleep
#0
1
Deep sleep
#1
SLEEPONEXIT
Sleep-on-Exit Enable\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
1
1
read-write
0
Do not sleep when returning to Thread mode
#0
1
Enter Sleep, or Deep Sleep, on return from an ISR to Thread mode
#1
SHPR2
SHPR2
System Handler Priority Register 2
0x1C
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11, SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority
30
2
read-write
SHPR3
SHPR3
System Handler Priority Register 3
0x20
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14, PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority
22
2
read-write
PRI_15
Priority of System Handler 15, SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority
30
2
read-write
SPI0
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPI clock is idle low
#0
1
SPI clock is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI clock
#0
1
Received data input signal is latched on the falling edge of SPI clock
#1
SLAVE
Slave Mode Enable
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI clock
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.
0
8
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX
SPI_RX
Data Receive Register
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0]
#0
1
If this bit is set, SPI_SS signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPI_SS line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).
2
1
read-write
0
The slave select signal SPI_SS is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX
SPI_TX
Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI1
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPI clock is idle low
#0
1
SPI clock is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI clock
#0
1
Received data input signal is latched on the falling edge of SPI clock
#1
SLAVE
Slave Mode Enable
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI clock
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.
0
8
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX
SPI_RX
Data Receive Register
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0]
#0
1
If this bit is set, SPI_SS signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPI_SS line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).
2
1
read-write
0
The slave select signal SPI_SS is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX
SPI_TX
Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SPI2
SPI Register Map
SPI
0x0
0x0
0xC
registers
n
0x10
0x4
registers
n
0x20
0x4
registers
n
0x3C
0xC
registers
n
SPI_CNTRL
SPI_CNTRL
Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CLKP
Clock Polarity
11
1
read-write
0
SPI clock is idle low
#0
1
SPI clock is idle high
#1
FIFO
FIFO Mode Enable
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
21
1
read-write
0
FIFO mode Disabled
#0
1
FIFO mode Enabled
#1
GO_BUSY
SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.
0
1
read-write
0
Data transfer stopped
#0
1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
#1
IE
Unit Transfer Interrupt Enable
17
1
read-write
0
SPI unit transfer interrupt Disabled
#0
1
SPI unit transfer interrupt Enabled
#1
IF
Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
LSB
Send LSB First
10
1
read-write
0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#0
1
The LSB, bit 0 of the SPI TX0/1 register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
#1
REORDER
Byte Reorder Function Enable\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.
19
1
read-write
0
Byte reorder function Disabled
#0
1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FULL
Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[25].
25
1
read-only
0
Receive FIOF buffer is not full
#0
1
Receive FIFO buffer is full
#1
RX_NEG
Receive on Negative Edge
1
1
read-write
0
Received data input signal is latched on the rising edge of SPI clock
#0
1
Received data input signal is latched on the falling edge of SPI clock
#1
SLAVE
Slave Mode Enable
18
1
read-write
0
Master mode
#0
1
Slave mode
#1
SP_CYCLE
Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:
12
4
read-write
TX_BIT_LEN
Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
3
5
read-write
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STAUTS[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_STATUS[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_NEG
Transmit on Negative Edge
2
1
read-write
0
Transmitted data output signal is changed on the rising edge of SPI clock
#0
1
Transmitted data output signal is changed on the falling edge of SPI clock
#1
SPI_CNTRL2
SPI_CNTRL2
Control and Status Register 2
0x3C
-1
read-write
n
0x0
0x0
BCn
SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
31
1
read-write
0
Backward compatible clock configuration
#0
1
Clock configuration is not backward compatible
#1
NOSLVSEL
Slave 3-Wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG, SPI_SSR[4] will be set as 1 automatically.
8
1
read-write
0
4-wire bi-direction interface
#0
1
3-wire bi-direction interface
#1
SLV_ABORT
Slave 3-Wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over the one transfer time in Slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
9
1
read-write
SLV_START_INTSTS
Slave 3-Wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
#1
SSTA_INTEN
Slave 3-Wire Mode Start Interrupt Enable\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
10
1
read-write
0
Transaction start interrupt Disabled
#0
1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
#1
SS_INT_OPT
Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
16
1
read-write
0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#0
1
As the slave select signal goes to inactive level, the IF bit will be set to 1
#1
SPI_DIVIDER
SPI_DIVIDER
Clock Divider Register
0x4
read-write
n
0x0
0x0
DIVIDER
Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation. \nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI engine clock source, which is defined in the CLKSEL1 register.
0
8
read-write
SPI_FIFO_CTL
SPI_FIFO_CTL
SPI FIFO Control Register
0x40
-1
read-write
n
0x0
0x0
RXOV_INTEN
Receive FIFO Overrun Interrupt Enable
6
1
read-write
0
Receive FIFO overrun interrupt Disabled
#0
1
Receive FIFO overrun interrupt Enabled
#1
RX_CLR
Clear Receive FIFO Buffer
0
1
read-write
0
No effect
#0
1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
RX_INTEN
Receive Threshold Interrupt Enable
2
1
read-write
0
RX threshold interrupt Disabled
#0
1
RX threshold interrupt Enabled
#1
RX_THRESHOLD
Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
24
3
read-write
TIMEOUT_INTEN
Receive FIFO Time-out Interrupt Enable
21
1
read-write
0
Time-out interrupt Disabled
#0
1
Time-out interrupt Enabled
#1
TX_CLR
Clear Transmit FIFO Buffer
1
1
read-write
0
No effect
#0
1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
#1
TX_INTEN
Transmit Threshold Interrupt Enable
3
1
read-write
0
TX threshold interrupt Disabled
#0
1
TX threshold interrupt Enabled
#1
TX_THRESHOLD
Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
28
3
read-write
SPI_RX
SPI_RX
Data Receive Register
0x10
read-only
n
0x0
0x0
RX
Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register. This is a read-only register.
0
32
read-only
SPI_SSR
SPI_SSR
Slave Select Register
0x8
read-write
n
0x0
0x0
AUTOSS
Automatic Slave Select Function Enable (Master Only)
3
1
read-write
0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0]
#0
1
If this bit is set, SPI_SS signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
#1
LTRIG_FLAG
Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \nNote: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning.
5
1
read-write
0
Transferred bit length of one transaction does not meet the specified requirement
#0
1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN
#1
SSR
Slave Select Control Bits (Master Only)
If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPI_SS line to an active state and writing 0 sets the line back to inactive state.
If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI_SS line at inactive state writing 1 to any bit location of this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPI_SS is specified in SS_LVL.
0
1
read-write
SS_LTRIG
Slave Select Level Trigger Enable (Slave Only)
4
1
read-write
0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#0
1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
#1
SS_LVL
Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).
2
1
read-write
0
The slave select signal SPI_SS is active on low-level/falling-edge
#0
1
The slave select signal SPI_SS is active on high-level/rising-edge
#1
SPI_STATUS
SPI_STATUS
SPI Status Register
0x44
-1
read-write
n
0x0
0x0
IF
SPI Unit Transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
16
1
read-write
0
No transaction has been finished since this bit was cleared to 0
#0
1
SPI controller has finished one unit transfer
#1
RX_EMPTY
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
24
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_FIFO_COUNT
Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
12
4
read-only
RX_FULL
Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24].
25
1
read-only
0
Receive FIFO buffer is not empty
#0
1
Receive FIFO buffer is empty
#1
RX_INTSTS
Receive FIFO Threshold Interrupt Status (Read Only)
0
1
read-only
0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#0
1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
#1
RX_OVERRUN
Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
2
1
read-write
SLV_START_INTSTS
Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].
11
1
read-write
0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#0
1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
#1
TIMEOUT
Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
20
1
read-write
0
No receive FIFO time-out event
#0
1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
#1
TX_EMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26].
26
1
read-only
0
Transmit FIFO buffer is not empty
#0
1
Transmit FIFO buffer is empty
#1
TX_FIFO_COUNT
Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
28
4
read-only
TX_FULL
Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].
27
1
read-only
0
Transmit FIFO buffer is not full
#0
1
Transmit FIFO buffer is full
#1
TX_INTSTS
Transmit FIFO Threshold Interrupt Status (Read Only)
4
1
read-only
0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#0
1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
#1
SPI_TX
SPI_TX
Data Transmit Register
0x20
write-only
n
0x0
0x0
TX
Data Transmit Register\nThe data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bits TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
0
32
write-only
SYST
SYST Register Map
SYST
0x0
0x0
0xC
registers
n
CSR
SYST_CSR
SysTick Control and Status Register
0x0
read-write
n
0x0
0x0
COUNTFLAG
SysTick flag.\nCOUNTFLAG is set when the counter transitions to zero.\nCOUNTFLAG is cleared by a read from this register or a write to the SYST_CVR.
16
1
read-write
ENABLE
Enables SysTick counter.
0
1
read-write
0
SysTick counter Disabled
#0
1
SysTick counter Enabled
#1
TICKINT
Enables SysTick exception request.
1
1
read-write
0
Counting down to zero does not assert the SysTick exception request
#0
1
Counting down to zero to asserts the SysTick exception request
#1
CVR
SYST_CVR
SysTick Current Value Register
0x8
read-write
n
0x0
0x0
CURRENT
Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the COUNTFLAG bit to 0.
0
24
read-write
RVR
SYST_RVR
SysTick Reload Value Register
0x4
read-write
n
0x0
0x0
RELOAD
Value to load into the SYST_CVR when the counter is enabled and when it reaches 0.
0
24
read-write
TMR01
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP0
TCAP0
Timer0 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
0
24
read-only
TCAP1
TCAP1
0x30
read-write
n
0x0
0x0
TCMPR0
TCMPR0
Timer0 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
0
24
read-write
TCMPR1
TCMPR1
0x24
read-write
n
0x0
0x0
TCSR0
TCSR0
Timer0 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.
26
1
read-write
0
No effect
#0
1
Reset 8-bit pre-scale counter, 24-bit up counter value and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 10.4.5 for detail description.
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode
27
2
read-write
PRESCALE
Pre-scale Counter
0
8
read-write
TDR_EN
Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
TCSR1
TCSR1
0x20
read-write
n
0x0
0x0
TDR0
TDR0
Timer0 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
0
24
read-only
TDR1
TDR1
0x2C
read-write
n
0x0
0x0
TEXCON0
TEXCON0
Timer0 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture Mode Select
4
1
read-write
0
Transition on TMx pin is using to save the 24-bit timer counter value (TDR value) to timer capture value (TCAP value) if TEXIF (TEXISR[0] timer external interrupt flag) is set to 1
#0
1
Transition on TMx pin is using to reset the 24-bit timer counter
#1
TCDB
Timer Counter pin De-bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture pin De-bounce Enable \nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
6
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXEN
Timer External Pin Enable\nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx pin.
3
1
read-write
0
RSTCAPSEL function of TMx pin will be ignored
#0
1
RSTCAPSEL function of TMx pin is active
#1
TEXIEN
Timer External interrupt Enable
5
1
read-write
0
TMx pin detection Interrupt Disabled
#0
1
TMx pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detect
1
2
read-write
0
A 1 to 0 transition on TMx pin will be detected
#00
1
A 0 to 1 transition on TMx pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx pin will be detected
#10
3
Reserved.
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TEXCON1
TEXCON1
0x34
read-write
n
0x0
0x0
TEXISR0
TEXISR0
Timer0 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag
This bit indicates the timer external interrupt flag status.
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware.
And it is cleared by software writing 1 to this bit.
0
1
read-write
TEXISR1
TEXISR1
0x38
read-write
n
0x0
0x0
TISR0
TISR0
Timer0 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by software writing 1 to this bit.
0
1
read-write
TISR1
TISR1
0x28
read-write
n
0x0
0x0
TMR23
TIMER Register Map
TIMER
0x0
0x0
0x1C
registers
n
0x20
0x1C
registers
n
TCAP2
TCAP2
Timer2 Capture Data Register
0x10
read-only
n
0x0
0x0
TCAP
Timer Capture Data Register
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
0
24
read-only
TCAP3
TCAP3
0x30
read-write
n
0x0
0x0
TCMPR2
TCMPR2
Timer2 Compare Register
0x4
read-write
n
0x0
0x0
TCMP
Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
0
24
read-write
TCMPR3
TCMPR3
0x24
read-write
n
0x0
0x0
TCSR2
TCSR2
Timer2 Control and Status Register
0x0
-1
read-write
n
0x0
0x0
CACT
Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.
25
1
read-only
0
24-bit up counter is not active
#0
1
24-bit up counter is active
#1
CEN
Timer Enable Bit
30
1
read-write
0
Stops/Suspends counting
#0
1
Starts counting
#1
CRST
Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.
26
1
read-write
0
No effect
#0
1
Reset 8-bit pre-scale counter, 24-bit up counter value and CEN bit
#1
CTB
Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 10.4.5 for detail description.
24
1
read-write
0
External counter mode Disabled
#0
1
External counter mode Enabled
#1
DBGACK_TMR
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement effects TIMER counting
#0
1
ICE debug mode acknowledgement disabled
#1
IE
Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
29
1
read-write
0
Timer Interrupt Disabled
#0
1
Timer Interrupt Enabled
#1
MODE
Timer Operating Mode
27
2
read-write
PRESCALE
Pre-scale Counter
0
8
read-write
TDR_EN
Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
16
1
read-write
0
Timer Data Register update Disabled
#0
1
Timer Data Register update Enabled while timer counter is active
#1
TCSR3
TCSR3
0x20
read-write
n
0x0
0x0
TDR2
TDR2
Timer2 Data Register
0xC
read-only
n
0x0
0x0
TDR
Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
0
24
read-only
TDR3
TDR3
0x2C
read-write
n
0x0
0x0
TEXCON2
TEXCON2
Timer2 External Control Register
0x14
read-write
n
0x0
0x0
RSTCAPSEL
Timer External Reset Counter / Capture Mode Select
4
1
read-write
0
Transition on TMx pin is using to save the 24-bit timer counter value (TDR value) to timer capture value (TCAP value) if TEXIF (TEXISR[0] timer external interrupt flag) is set to 1
#0
1
Transition on TMx pin is using to reset the 24-bit timer counter
#1
TCDB
Timer Counter pin De-bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
7
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXDB
Timer External Capture pin De-bounce Enable \nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
6
1
read-write
0
TMx pin de-bounce Disabled
#0
1
TMx pin de-bounce Enabled
#1
TEXEN
Timer External Pin Enable\nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx pin.
3
1
read-write
0
RSTCAPSEL function of TMx pin will be ignored
#0
1
RSTCAPSEL function of TMx pin is active
#1
TEXIEN
Timer External interrupt Enable
5
1
read-write
0
TMx pin detection Interrupt Disabled
#0
1
TMx pin detection Interrupt Enabled
#1
TEX_EDGE
Timer External Pin Edge Detect
1
2
read-write
0
A 1 to 0 transition on TMx pin will be detected
#00
1
A 0 to 1 transition on TMx pin will be detected
#01
2
Either 1 to 0 or 0 to 1 transition on TMx pin will be detected
#10
3
Reserved.
#11
TX_PHASE
Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.
0
1
read-write
0
A falling edge of external counting pin will be counted
#0
1
A rising edge of external counting pin will be counted
#1
TEXCON3
TEXCON3
0x34
read-write
n
0x0
0x0
TEXISR2
TEXISR2
Timer2 External Interrupt Status Register
0x18
read-write
n
0x0
0x0
TEXIF
Timer External Interrupt Flag
This bit indicates the timer external interrupt flag status.
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware.
And it is cleared by software writing 1 to this bit.
0
1
read-write
TEXISR3
TEXISR3
0x38
read-write
n
0x0
0x0
TISR2
TISR2
Timer2 Interrupt Status Register
0x8
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by software writing 1 to this bit.
0
1
read-write
TISR3
TISR3
0x28
read-write
n
0x0
0x0
UART0
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1
0
4
read-write
LIN_RX_EN
LIN RX Enable
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to Table 191 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to Table 191 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
nRTS Trigger Level for Auto-flow Control Use
16
4
read-write
RX_DIS
Receiver Disable Register.\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit', and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is clear to 0 and RX_POINTER will show 15.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is clear to 0 and TX_POINTER will show 15.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
nCTS Auto Flow Control Enable\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto flow control Disabled
#0
1
nCTS auto flow control Enabled
#1
AUTO_RTS_EN
nRTS Auto Flow Control Enable\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto flow control Disabled
#0
1
nRTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time Out Counter Enable
11
1
read-write
0
Time out counter Disabled
#0
1
Time out counter Enabled
#1
TOUT_IEN
RX Time Out Interrupt Enable
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
WAKE_EN
UART Wake-up Function Enable
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPENR_F and LINS_HERR_F all are cleared
7
1
read-only
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP bit'
2
1
read-write
0
One ' STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection
0
2
read-write
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in automatic resynchronization mode, the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of this field are explained in Slave mode with automatic resynchronization.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN slave automatic resynchronization mode. (for non-automatic resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in Slave mode with automatic resynchronization.
3
1
read-write
0
UA_BAUD is updated as soon as UA_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable
10
1
read-write
0
LIN break detection. Disabled
#0
1
LIN break detection Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL], User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This break field length is LIN_BKFL + 1.
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select
22
2
read-write
0
The LIN header includes 'break field'
#00
1
The LIN header includes 'break field' and 'sync field'
#01
2
The LIN header includes 'break field', 'sync field' and 'frame ID field'
#10
3
Reserved.
#11
LIN_IDPEN
LIN ID Parity Enable
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode.
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can filled any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
None
11
1
read-write
0
Error detection function Disabled
#0
1
Bit error detection Enabled
#1
LIN_SHD
LIN TX Send Header Enable
The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting LIN_HEAD_SEL register.
Note1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD] user can read/write it by setting UA_ALT_CSR [LIN_SHD] or UA_LIN_CTL [LIN_SHD].
Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by LIN_HEAD_SEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 without automatic resynchronization mode', 'sync field deviation error with automatic resynchronization mode', 'sync field measure time-out with automatic resynchronization mode' and 'LIN header reception time-out'.
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header/
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by software writing 1 to it.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (UA_ALT_CSR [LIN_BKDET_EN])
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
nRTS Trigger Level\nThis bit can change the nRTS trigger level.
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
nRTS (Request-To-Send) Signal
1
1
read-write
0
Drive nRTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive nRTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
nRTS Pin State (Read Only)\nThis bit is the output pin status of nRTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTS_ST
nCTS Pin Status (Read Only)\nThis bit is the pin status of nCTS.
4
1
read-only
DCTSF
Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0
0
1
read-only
LEV_CTS
nCTS Trigger Level\nThis bit can change the nCTS trigger level.
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator
0
8
read-write
UART1
UART Register Map
UART
0x0
0x0
0x3C
registers
n
UA_ALT_CSR
UA_ALT_CSR
UART Alternate Control/Status Register
0x2C
read-write
n
0x0
0x0
ADDR_MATCH
Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
24
8
read-write
LIN_BKFL
UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1
0
4
read-write
LIN_RX_EN
LIN RX Enable
6
1
read-write
0
LIN RX mode Disabled
#0
1
LIN RX mode Enabled
#1
LIN_TX_EN
LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
7
1
read-write
0
LIN TX Break mode Disabled
#0
1
LIN TX Break mode Enabled
#1
RS485_AAD
RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
9
1
read-write
0
RS-485 Auto Address Detection Operation mode (AAD) Disabled
#0
1
RS-485 Auto Address Detection Operation mode (AAD) Enabled
#1
RS485_ADD_EN
RS-485 Address Detection Enable \nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
15
1
read-write
0
Address detection mode Disabled
#0
1
Address detection mode Enabled
#1
RS485_AUD
RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
10
1
read-write
0
RS-485 Auto Direction Operation mode (AUO) Disabled
#0
1
RS-485 Auto Direction Operation mode (AUO) Enabled
#1
RS485_NMM
RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
8
1
read-write
0
RS-485 Normal Multi-drop Operation mode (NMM) Disabled
#0
1
RS-485 Normal Multi-drop Operation mode (NMM) Enabled
#1
UA_BAUD
UA_BAUD
UART Baud Rate Divisor Register
0x24
-1
read-write
n
0x0
0x0
BRD
Baud Rate Divider\nThe field indicates the baud rate divider
0
16
read-write
DIVIDER_X
Divider X
24
4
read-write
DIV_X_EN
Divider X Enable\nRefer to Table 191 for more information.\nNote: In IrDA mode, this bit must disable.
29
1
read-write
0
Divider X Disabled (the equation of M = 16)
#0
1
Divider X Enabled (the equation of M = X+1, but DIVIDER_X [27:24] must = 8)
#1
DIV_X_ONE
Divider X Equal to 1\nRefer to Table 191 for more information.
28
1
read-write
0
Divider M = X (the equation of M = X+1, but DIVIDER_X[27:24] must = 8)
#0
1
Divider M = 1 (the equation of M = 1, but BRD [15:0] must = 3)
#1
UA_FCR
UA_FCR
UART FIFO Control Register
0x8
read-write
n
0x0
0x0
RFITL
RX FIFO Interrupt (INT_RDA) Trigger Level
4
4
read-write
RFR
RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
1
1
read-write
0
No effect
#0
1
Reset the RX internal state machine and pointers
#1
RTS_TRI_LEV
nRTS Trigger Level for Auto-flow Control Use
16
4
read-write
RX_DIS
Receiver Disable Register.\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
8
1
read-write
0
Receiver Enabled
#0
1
Receiver Disabled
#1
TFR
TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
2
1
read-write
0
No effect
#0
1
Reset the TX internal state machine and pointers
#1
UA_FSR
UA_FSR
UART FIFO Status Register
0x18
-1
read-write
n
0x0
0x0
BIF
Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
6
1
read-only
FEF
Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
5
1
read-only
PEF
Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit', and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing '1' to it.
4
1
read-only
RS485_ADD_DETF
RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNote: This bit is read only, but can be cleared by writing '1' to it.
3
1
read-only
RX_EMPTY
Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
14
1
read-only
RX_FULL
Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not.\nThis bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
15
1
read-only
RX_OVER_IF
RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART, this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
0
1
read-only
RX_POINTER
RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is clear to 0 and RX_POINTER will show 15.
8
6
read-only
TE_FLAG
Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
28
1
read-only
TX_EMPTY
Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
22
1
read-only
TX_FULL
Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nThis bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
23
1
read-only
TX_OVER_IF
TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit is read only, but can be cleared by writing '1' to it.
24
1
read-only
TX_POINTER
TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is clear to 0 and TX_POINTER will show 15.
16
6
read-only
UA_FUN_SEL
UA_FUN_SEL
UART Function Select Register
0x30
read-write
n
0x0
0x0
FUN_SEL
Function Select Enable
0
2
read-write
0
UART function Enabled
#00
1
LIN function Enabled
#01
2
IrDA function Enabled
#10
3
RS-485 function Enabled
#11
UA_IER
UA_IER
UART Interrupt Enable Register
0x4
read-write
n
0x0
0x0
AUTO_CTS_EN
nCTS Auto Flow Control Enable\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
13
1
read-write
0
nCTS auto flow control Disabled
#0
1
nCTS auto flow control Enabled
#1
AUTO_RTS_EN
nRTS Auto Flow Control Enable\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert nRTS signal.
12
1
read-write
0
nRTS auto flow control Disabled
#0
1
nRTS auto flow control Enabled
#1
BUF_ERR_IEN
Buffer Error Interrupt Enable
5
1
read-write
0
Mask off INT_BUF_ERR Masked off
#0
1
INT_BUF_ERR Enabled
#1
LIN_IEN
LIN Bus Interrupt Enable\nNote: This field is used for LIN function mode.
8
1
read-write
0
Lin bus interrupt Disabled
#0
1
Lin bus interrupt Enabled
#1
MODEM_IEN
Modem Status Interrupt Enable
3
1
read-write
0
INT_MODEM Masked off
#0
1
INT_MODEM Enabled
#1
RDA_IEN
Receive Data Available Interrupt Enable
0
1
read-write
0
INT_RDA Masked off
#0
1
INT_RDA Enabled
#1
RLS_IEN
Receive Line Status Interrupt Enable
2
1
read-write
0
INT_RLS Masked off
#0
1
INT_RLS Enabled
#1
THRE_IEN
Transmit Holding Register Empty Interrupt Enable
1
1
read-write
0
INT_THRE Masked off
#0
1
INT_THRE Enabled
#1
TIME_OUT_EN
Time Out Counter Enable
11
1
read-write
0
Time out counter Disabled
#0
1
Time out counter Enabled
#1
TOUT_IEN
RX Time Out Interrupt Enable
4
1
read-write
0
INT_TOUT Masked off
#0
1
INT_TOUT Enabled
#1
WAKE_EN
UART Wake-up Function Enable
6
1
read-write
0
UART wake-up function Disabled
#0
1
UART wake-up function Enabled, when the chip is in Power-down mode, an external nCTS change will wake-up chip from Power-down mode
#1
UA_IRCR
UA_IRCR
UART IrDA Control Register
0x28
-1
read-write
n
0x0
0x0
INV_RX
INV_RX
6
1
read-write
0
No inversion
#0
1
Inverse RX input signal
#1
INV_TX
INV_TX
5
1
read-write
0
No inversion
#0
1
Inverse TX output signal
#1
TX_SELECT
TX_SELECT
1
1
read-write
0
IrDA receiver Enabled
#0
1
IrDA transmitter Enabled
#1
UA_ISR
UA_ISR
UART Interrupt Status Register
0x1C
-1
read-write
n
0x0
0x0
BUF_ERR_IF
Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF) is set. When BUF_ERR_IF is set, the transfer is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.
5
1
read-only
BUF_ERR_INT
Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.
13
1
read-only
0
No buffer error interrupt is generated
#0
1
Buffer error interrupt is generated
#1
LIN_IF
LIN Bus Flag (Read Only)\nNote: This bit is cleared when LINS_HDET_F, LIN_BKDET_F, BIT_ERR_F, LINS_IDPENR_F and LINS_HERR_F all are cleared
7
1
read-only
LIN_INT
LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN and LIN _IF are both set to 1.
15
1
read-only
0
No LIN Bus interrupt is generated
#0
1
The LIN Bus interrupt is generated
#1
MODEM_IF
MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF.
3
1
read-only
MODEM_INT
MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.
11
1
read-only
0
No Modem interrupt is generated
#0
1
Modem interrupt is generated
#1
RDA_IF
Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
0
1
read-only
RDA_INT
Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.
8
1
read-only
0
No RDA interrupt is generated
#0
1
RDA interrupt is generated
#1
RLS_IF
Receive Line Interrupt Flag (Read Only).
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated.
Note: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
2
1
read-only
RLS_INT
Receive Line Status Interrupt Indicator (Read Only). \nThis bit is set if RLS_IEN and RLS_IF are both set to 1.
10
1
read-only
0
No RLS interrupt is generated
#0
1
RLS interrupt is generated
#1
THRE_IF
Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
1
1
read-only
THRE_INT
Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.
9
1
read-only
0
No THRE interrupt is generated
#0
1
THRE interrupt is generated
#1
TOUT_IF
Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
4
1
read-only
TOUT_INT
Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.
12
1
read-only
0
No Tout interrupt is generated
#0
1
Tout interrupt is generated
#1
UA_LCR
UA_LCR
UART Line Control Register
0xC
read-write
n
0x0
0x0
BCB
Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
6
1
read-write
EPE
Even Parity Enable\nThis bit has effect only when PBE (UA_LCR[3]) is set.
4
1
read-write
0
Odd number of logic 1's is transmitted and checked in each word
#0
1
Even number of logic 1's is transmitted and checked in each word
#1
NSB
Number of 'STOP bit'
2
1
read-write
0
One ' STOP bit' is generated in the transmitted data
#0
1
When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. When select 6-,7- and 8-bti word length, 2 'STOP bit' is generated in the transmitted data
#1
PBE
Parity Bit Enable
3
1
read-write
0
No parity bit
#0
1
Parity bit is generated on each outgoing character and is checked on each incoming data
#1
SPE
Stick Parity Enable
5
1
read-write
0
Stick parity Disabled
#0
1
If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1
#1
WLS
Word Length Selection
0
2
read-write
UA_LIN_CTL
UA_LIN_CTL
UART LIN Control Register
0x34
-1
read-write
n
0x0
0x0
BIT_ERR_EN
Bit Error Detect Enable
12
1
read-write
0
Bit error detection function Disabled
#0
1
Bit error detection Enabled
#1
LINS_ARS_EN
LIN Slave Automatic Resynchronization Mode Enable\nNote2: When operation in automatic resynchronization mode, the baud rate setting must be mode2 (UA_BAUD [DIV_X_EN] and UA_BAUD [DIV_X_ONE] must be 1).\nNote3: The control and interactions of this field are explained in Slave mode with automatic resynchronization.
2
1
read-write
0
LIN automatic resynchronization Disabled
#0
1
LIN automatic resynchronization Enabled
#1
LINS_DUM_EN
LIN Slave Divider Update Method Enable\nNote2: This bit used for LIN slave automatic resynchronization mode. (for non-automatic resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in Slave mode with automatic resynchronization.
3
1
read-write
0
UA_BAUD is updated as soon as UA_BAUD is writing by software (if no automatic resynchronization update occurs at the same time)
#0
1
UA_BAUD is updated at the next received character. User must set the bit before checksum reception
#1
LINS_EN
LIN Slave Mode Enable
0
1
read-write
0
LIN slave mode Disabled
#0
1
LIN slave mode Enabled
#1
LINS_HDET_EN
LIN Slave Header Detection Enable
1
1
read-write
0
LIN slave header detection Disabled
#0
1
LIN slave header detection Enabled
#1
LIN_BKDET_EN
LIN Break Detection Enable
10
1
read-write
0
LIN break detection. Disabled
#0
1
LIN break detection Enabled
#1
LIN_BKFL
LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of UA_ALT_CSR [LIN_BKFL], User can read/write it by setting UA_ALT_CSR [LIN_BKFL] or UA_LIN_CTL [LIN_BKFL].\nNote2: This break field length is LIN_BKFL + 1.
16
4
read-write
LIN_BS_LEN
LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to sending header field.
20
2
read-write
0
The LIN break/sync delimiter length is 1 bit time
#00
2
The LIN break/sync delimiter length is 2 bit time.\nThe LIN break/sync delimiter length is 3 bit time
#10
3
The LIN break/sync delimiter length is 4 bit time
#11
LIN_HEAD_SEL
LIN Header Select
22
2
read-write
0
The LIN header includes 'break field'
#00
1
The LIN header includes 'break field' and 'sync field'
#01
2
The LIN header includes 'break field', 'sync field' and 'frame ID field'
#10
3
Reserved.
#11
LIN_IDPEN
LIN ID Parity Enable
9
1
read-write
0
LIN frame ID parity Disabled
#0
1
LIN frame ID parity Enabled
#1
LIN_MUTE_EN
LIN Mute Mode Enable\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode.
4
1
read-write
0
LIN mute mode Disabled
#0
1
LIN mute mode Enabled
#1
LIN_PID
LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on UA_LIN_CTL [LIN_IDPEN]. \n\nNote1: User can filled any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN master mode or slave mode.
24
8
read-write
LIN_RX_DIS
None
11
1
read-write
0
Error detection function Disabled
#0
1
Bit error detection Enabled
#1
LIN_SHD
LIN TX Send Header Enable
The LIN TX header can be 'break field' or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting LIN_HEAD_SEL register.
Note1: These registers are shadow registers of UA_ALT_CSR [LIN_SHD] user can read/write it by setting UA_ALT_CSR [LIN_SHD] or UA_LIN_CTL [LIN_SHD].
Note2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by LIN_HEAD_SEL field) transfer operation finished, this bit will be cleared automatically.
8
1
read-write
0
Send LIN TX header Disabled
#0
1
Send LIN TX header Enabled
#1
UA_LIN_SR
UA_LIN_SR
UART LIN Status Register
0x38
read-write
n
0x0
0x0
BIT_ERR_F
Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.
9
1
read-only
LINS_HDET_F
LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
0
1
read-only
0
LIN header not detected
#0
1
LIN header detected (break + sync + frame ID)
#1
LINS_HERR_F
LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short', 'frame error in sync field or Identifier field', 'sync field data is not 0x55 without automatic resynchronization mode', 'sync field deviation error with automatic resynchronization mode', 'sync field measure time-out with automatic resynchronization mode' and 'LIN header reception time-out'.
1
1
read-only
0
LIN header error not detected
#0
1
LIN header error detected
#1
LINS_IDPERR_F
LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.
2
1
read-only
0
no active
#0
1
Receipted frame ID parity is not correct
#1
LINS_SYNC_F
LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but it can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header/
3
1
read-write
0
The current character is not at LIN sync state
#0
1
The current character is at LIN sync state
#1
LIN_BKDET_F
LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by software writing 1 to it.\nNote1: This bit is read only, but it can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (UA_ALT_CSR [LIN_BKDET_EN])
8
1
read-only
0
LIN break not detected
#0
1
LIN break detected
#1
UA_MCR
UA_MCR
UART Modem Control Register
0x10
-1
read-write
n
0x0
0x0
LEV_RTS
nRTS Trigger Level\nThis bit can change the nRTS trigger level.
9
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
RTS
nRTS (Request-To-Send) Signal
1
1
read-write
0
Drive nRTS pin to logic 1 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 0 (If the LEV_RTS set to high level triggered)
#0
1
Drive nRTS pin to logic 0 (If the LEV_RTS set to low level triggered).\nDrive nRTS pin to logic 1 (If the LEV_RTS set to high level triggered)
#1
RTS_ST
nRTS Pin State (Read Only)\nThis bit is the output pin status of nRTS.
13
1
read-only
UA_MSR
UA_MSR
UART Modem Status Register
0x14
-1
read-write
n
0x0
0x0
CTS_ST
nCTS Pin Status (Read Only)\nThis bit is the pin status of nCTS.
4
1
read-only
DCTSF
Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nWrite 1 to clear this bit to 0
0
1
read-only
LEV_CTS
nCTS Trigger Level\nThis bit can change the nCTS trigger level.
8
1
read-write
0
Low level triggered
#0
1
High level triggered
#1
UA_RBR
UA_RBR
UART Receive Buffer Register
0x0
read-only
n
0x0
0x0
RBR
Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
0
8
read-only
UA_THR
UA_THR
UART Transmit Holding Register
UA_RBR
0x0
write-only
n
0x0
0x0
THR
Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the UART_TXD pin (LSB first).
0
8
write-only
UA_TOR
UA_TOR
UART Time Out Register
0x20
read-write
n
0x0
0x0
DLY
TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
8
8
read-write
TOIC
Time Out Interrupt Comparator
0
8
read-write
WDT
WDT Register Map
WDT
0x0
0x0
0x8
registers
n
WTCR
WTCR
Watchdog Timer Control Register
0x0
-1
read-write
n
0x0
0x0
DBGACK_WDT
ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter CPU is held by ICE or not.
31
1
read-write
0
ICE debug mode acknowledgement affects Watchdog Timer counting
#0
1
ICE debug mode acknowledgement Disabled
#1
WTE
Watchdog Timer Enable (Write-protection Bit)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
7
1
read-write
0
Watchdog Timer Disabled (This action will reset the internal counter)
#0
1
Watchdog Timer Enabled
#1
WTIE
Watchdog Timer Interrupt Enable (Write-protection Bit)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
6
1
read-write
0
Watchdog Timer interrupt Disabled
#0
1
Watchdog Timer interrupt Enabled
#1
WTIF
Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to this bit.
3
1
read-write
0
Watchdog Timer time-out interrupt did not occur
#0
1
Watchdog Timer time-out interrupt occurred
#1
WTIS
Watchdog Timer Interval Selection (Write-protection Bits)
8
3
read-write
WTR
Reset Watchdog Timer Counter (Write-protection Bit)\nNote: This bit will be automatically cleared by hardware.
0
1
read-write
0
No effect
#0
1
Reset the internal 18-bit WDT counter
#1
WTRE
Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires..
1
1
read-write
0
Watchdog Timer time-out reset function Disabled
#0
1
Watchdog Timer time-out reset function Enabled
#1
WTRF
Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to this bit.
2
1
read-write
0
Watchdog Timer time-out reset did not occur
#0
1
Watchdog Timer time-out reset occurred
#1
WTWKE
Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nIf this bit is set to 1, while WDT interrupt flag (WTCR[3] WTIF) is generated to 1 and WTIE (WTCR[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
4
1
read-write
0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#0
1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
#1
WTWKF
Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nThis bit is cleared by writing 1 to this bit..
5
1
read-write
0
Watchdog Timer does not cause chip wake-up
#0
1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
#1
WTCRALT
WTCRALT
Watchdog Timer Alternative Control Register
0x4
read-write
n
0x0
0x0
WTRDSEL
Watchdog Timer Reset Delay Select (Write-protection Bits)\nWhen WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened. Software can select a suitable value of WDT reset delay period for different WDT time-out period.\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nThis register will be reset to 0 if WDT time-out reset happened
0
2
read-write
0
Watchdog Timer reset delay period is (1024+2) * WDT_CLK
#00
1
Watchdog Timer reset delay period is (128+2) * WDT_CLK
#01
2
Watchdog Timer reset delay period is (16+2) * WDT_CLK
#10
3
Watchdog Timer reset delay period is (1+2) * WDT_CLK
#11
WWDT
WWDT Register Map
WWDT
0x0
0x0
0x10
registers
n
WWDTCR
WWDTCR
Window Watchdog Timer Control Register
0x4
-1
read-write
n
0x0
0x0
DBGACK_WWDT
ICE debug mode acknowledge Disable
31
1
read-write
0
WWDT counter stopped if system is in Debug mode
#0
1
WWDT still counted even system is in Debug mode
#1
PERIODSEL
WWDT Pre-scale Period Select
8
4
read-write
WINCMP
WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If Software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
16
6
read-write
WWDTEN
WWDT Enable\nSet this bit to enable Window Watchdog Timer counter counting.
0
1
read-write
0
Window Watchdog Timer counter is stopped
#0
1
Window Watchdog Timer counter is starting counting
#1
WWDTIE
WWDT Interrupt Enable\nSetting this bit to enable the Window Watchdog Timer time-out interrupt function.
1
1
read-write
0
WWDT time-out interrupt function Disabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#0
1
WWDT time-out interrupt function Enabled if WWDTIF (WWDTSR[0] WWDT compare match interrupt flag) is 1
#1
WWDTCVR
WWDTCVR
Window Watchdog Timer Counter Value Register
0xC
-1
read-only
n
0x0
0x0
WWDTCVAL
WWDT Counter Value\nThis register reflects the current WWDT counter value and this register is read only
0
6
read-only
WWDTRLD
WWDTRLD
Window Watchdog Timer Reload Counter Register
0x0
write-only
n
0x0
0x0
WWDTRLD
WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD to reload WWDT counter value when current WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when current WWDT counter value larger than WINCMP, WWDT reset signal will generate immediately.
0
32
write-only
WWDTSR
WWDTSR
Window Watchdog Timer Status Register
0x8
read-write
n
0x0
0x0
WWDTIF
WWDT Compare Match Interrupt Flag\nWhen current WWDT counter value matches to WWCMP, this bit is set to 1. This bit will be cleared by writing 1 to itself.
0
1
read-write
WWDTRF
WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value larger than WINCMP, chip will be reset and this bit is set to 1. This bit will be cleared to 0 by writing 1 to itself.
1
1
read-write